trunk/src/mame/drivers/model2.c
| r29616 | r29617 | |
|---|
| 7 | 7 | Hardware and protection reverse-engineering and general assistance by ElSemi. |
| 8 | 8 | MAME driver by R. Belmont, Olivier Galibert, and ElSemi. |
| 9 | 9 | |
| 10 | TODO (updated as for April 2014): |
| 11 | - all Model 2B games: FIFO comms looks way wrong, and 3d is mostly missing/incomplete. Games also stalls at some point; |
| 12 | - daytona: runs at half speed in gameplay; |
| 13 | - desert: several 3d bugs, presumably down to FIFO; |
| 14 | - dynamcop: stalls at stage select screen; |
| 15 | - fvipers: enables timers, but then irq register is empty, hence it crashes with an "interrupt halt" at POST (regression); |
| 16 | - manxtt: missing 3d; |
| 17 | - motoraid: stalls after course select; |
| 18 | - pltkidsa: after few secs of gameplay, background 3d disappears and everything reports a collision against the player; |
| 19 | - skytargt: MAME hardlocks after disclaimer screen; |
| 20 | - srallyc: opponent cars flickers like wild; |
| 21 | - vcop: lightgun input is offsetted; |
| 22 | - vcop: sound dies at enter initial screen (i.e. after played the game once); |
| 23 | - vcop: priority bug at stage select screen; |
| 24 | - vcop2: no 3d; |
| 25 | - vf2: stalls after disclaimer screen; |
| 26 | - zeroguna: stalls after some seconds of gameplay; |
| 27 | |
| 10 | 28 | OK (controls may be wrong/missing/incomplete) |
| 11 | 29 | -- |
| 12 | 30 | daytona/daytonat/daytonam |
| r29616 | r29617 | |
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| 337 | 355 | int tnum = (int)(FPTR)ptr; |
| 338 | 356 | int bit = tnum + 2; |
| 339 | 357 | |
| 358 | if(m_timerrun[tnum] == 0) |
| 359 | return; |
| 360 | |
| 340 | 361 | m_timers[tnum]->reset(); |
| 341 | 362 | |
| 342 | 363 | m_intreq |= (1<<bit); |
| 364 | //printf("%08x %08x (%08x)\n",m_intreq,m_intena,1<<bit); |
| 343 | 365 | model2_check_irq_state(); |
| 344 | 366 | |
| 345 | | m_timervals[tnum] = 0; |
| 367 | m_timervals[tnum] = -1; |
| 346 | 368 | m_timerrun[tnum] = 0; |
| 347 | 369 | } |
| 348 | 370 | |
| r29616 | r29617 | |
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| 1005 | 1027 | |
| 1006 | 1028 | void model2_state::model2_check_irq_state() |
| 1007 | 1029 | { |
| 1008 | | const int irq_type[16]= {I960_IRQ0,I960_IRQ1,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ3,I960_IRQ3}; |
| 1030 | const int irq_type[12]= {I960_IRQ0,I960_IRQ1,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ3,I960_IRQ3}; |
| 1009 | 1031 | |
| 1010 | | for(int i=0;i<16;i++) |
| 1032 | for(int i=0;i<12;i++) |
| 1011 | 1033 | { |
| 1012 | | if (m_intena & (1<<i) && m_intreq & 1<<i) |
| 1034 | if (m_intena & (1<<i) && m_intreq & (1<<i)) |
| 1035 | { |
| 1013 | 1036 | m_maincpu->set_input_line(irq_type[i], ASSERT_LINE); |
| 1037 | return; |
| 1038 | } |
| 1014 | 1039 | } |
| 1015 | 1040 | } |
| 1016 | 1041 | |
| 1042 | void model2_state::model2_check_irqack_state(UINT32 data) |
| 1043 | { |
| 1044 | const int irq_type[12]= {I960_IRQ0,I960_IRQ1,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ3,I960_IRQ3}; |
| 1045 | |
| 1046 | for(int i=0;i<12;i++) |
| 1047 | { |
| 1048 | if(data & 1<<i) |
| 1049 | m_maincpu->set_input_line(irq_type[i], CLEAR_LINE); |
| 1050 | } |
| 1051 | } |
| 1052 | |
| 1017 | 1053 | WRITE32_MEMBER(model2_state::model2_irq_w) |
| 1018 | 1054 | { |
| 1019 | 1055 | m_maincpu->i960_noburst(); |
| r29616 | r29617 | |
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| 1026 | 1062 | } |
| 1027 | 1063 | |
| 1028 | 1064 | m_intreq &= data; |
| 1029 | | /* TODO: improve this */ |
| 1030 | | UINT32 irq_ack = data ^ 0xffffffff; |
| 1031 | 1065 | |
| 1032 | | if(irq_ack & 1<<0) |
| 1033 | | m_maincpu->set_input_line(I960_IRQ0, CLEAR_LINE); |
| 1034 | | |
| 1035 | | if(irq_ack & 1<<10) |
| 1036 | | m_maincpu->set_input_line(I960_IRQ3, CLEAR_LINE); |
| 1037 | | |
| 1066 | model2_check_irqack_state(data ^ 0xffffffff); |
| 1038 | 1067 | } |
| 1039 | 1068 | |
| 1040 | 1069 | /* TODO: rewrite this part. */ |
| r29616 | r29617 | |
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| 1994 | 2023 | { |
| 1995 | 2024 | int scanline = param; |
| 1996 | 2025 | |
| 1997 | | if(scanline == 0) // 384 |
| 2026 | if(scanline == 384) |
| 1998 | 2027 | { |
| 2028 | m_intreq |= (1<<0); |
| 2029 | model2_check_irq_state(); |
| 2030 | } |
| 2031 | else if(scanline == 0) // 384 |
| 2032 | { |
| 1999 | 2033 | m_intreq |= (1<<10); |
| 2000 | 2034 | model2_check_irq_state(); |
| 2001 | 2035 | } |
| 2002 | | |
| 2003 | | if(scanline == 256) |
| 2036 | else if(scanline == 256) |
| 2004 | 2037 | { |
| 2038 | /* TODO: irq source? Source allocation in dynamcopc? */ |
| 2005 | 2039 | m_intreq |= (1<<2); |
| 2006 | 2040 | model2_check_irq_state(); |
| 2007 | 2041 | } |
| 2008 | 2042 | |
| 2009 | | if(scanline == 128) |
| 2010 | | { |
| 2011 | | m_intreq |= (1<<0); |
| 2012 | | model2_check_irq_state(); |
| 2013 | | } |
| 2043 | |
| 2014 | 2044 | } |
| 2015 | 2045 | |
| 2016 | 2046 | /* Model 2 sound board emulation */ |
| r29616 | r29617 | |
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| 2176 | 2206 | MCFG_MB86233_FIFO_WRITE_CB(WRITE32(model2_state,copro_tgp_fifoout_push)) |
| 2177 | 2207 | MCFG_MB86233_TABLE_REGION("user5") |
| 2178 | 2208 | |
| 2179 | | |
| 2180 | 2209 | MCFG_MACHINE_START_OVERRIDE(model2_state,model2) |
| 2181 | 2210 | MCFG_MACHINE_RESET_OVERRIDE(model2_state,model2) |
| 2182 | 2211 | |