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r29613 Sunday 13th April, 2014 at 17:34:40 UTC by Fabio Priuli
updated lsi53c810 to use delegates, and moved some formerly static stuff into bebox and model3 classes. nw.

[src/emu/machine]	53c810.c 53c810.h
[src/mame/drivers]	model3.c
[src/mame/includes]	model3.h
[src/mame/video]	model3.c
[src/mess/drivers]	bebox.c
[src/mess/includes]	bebox.h
[src/mess/machine]	bebox.c

trunk/src/mess/machine/bebox.c

r29612	r29613
116	116	*
117	117	*************************************/
118	118
119		static void bebox_update_interrupts(running_machine &machine);
120
121	119	static void bebox_mbreg32_w(UINT32 *target, UINT64 data, UINT64 mem_mask)
122	120	{
123	121	int i;
r29612	r29613
163	161	logerror("BeBox CPU #0 pc=0x%08X imask=0x%08x\n",
164	162	(unsigned) space.device().safe_pc( ), m_cpu_imask[0]);
165	163	}
166		bebox_update_interrupts(space.machine());
	164	bebox_update_interrupts();
167	165	}
168	166	}
169	167
r29612	r29613
180	178	logerror("BeBox CPU #1 pc=0x%08X imask=0x%08x\n",
181	179	(unsigned) space.device() .safe_pc( ), m_cpu_imask[1]);
182	180	}
183		bebox_update_interrupts(space.machine());
	181	bebox_update_interrupts();
184	182	}
185	183	}
186	184
r29612	r29613
253	251	}
254	252
255	253
256		static void bebox_update_interrupts(running_machine &machine)
	254	void bebox_state::bebox_update_interrupts()
257	255	{
258		bebox_state *state = machine.driver_data<bebox_state>();
259		int cpunum;
260	256	UINT32 interrupt;
261	257	static const char *const cputags[] = { "ppc1", "ppc2" };
262	258
263		for (cpunum = 0; cpunum < 2; cpunum++)
	259	for (int cpunum = 0; cpunum < 2; cpunum++)
264	260	{
265		interrupt = state->m_interrupts & state->m_cpu_imask[cpunum];
	261	interrupt = m_interrupts & m_cpu_imask[cpunum];
266	262
267	263	if (LOG_INTERRUPTS)
268	264	{
269	265	logerror("\tbebox_update_interrupts(): CPU #%d [%08X|%08X] IRQ %s\n", cpunum,
270		state->m_interrupts, state->m_cpu_imask[cpunum], interrupt ? "on" : "off");
	266	m_interrupts, m_cpu_imask[cpunum], interrupt ? "on" : "off");
271	267	}
272	268
273		machine.device(cputags[cpunum])->execute().set_input_line(INPUT_LINE_IRQ0, interrupt ? ASSERT_LINE : CLEAR_LINE);
	269	machine().device(cputags[cpunum])->execute().set_input_line(INPUT_LINE_IRQ0, interrupt ? ASSERT_LINE : CLEAR_LINE);
274	270	}
275	271	}
276	272
277	273
278		void bebox_set_irq_bit(running_machine &machine, unsigned int interrupt_bit, int val)
	274	void bebox_state::bebox_set_irq_bit(unsigned int interrupt_bit, int val)
279	275	{
280		bebox_state *state = machine.driver_data<bebox_state>();
281	276	static const char *const interrupt_names[32] =
282	277	{
283	278	NULL,
r29612	r29613
321	316	assert_always((interrupt_bit < ARRAY_LENGTH(interrupt_names)) && (interrupt_names[interrupt_bit] != NULL), "Raising invalid interrupt");
322	317
323	318	logerror("bebox_set_irq_bit(): pc[0]=0x%08x pc[1]=0x%08x %s interrupt #%u (%s)\n",
324		(unsigned) machine.device("ppc1")->safe_pc(),
325		(unsigned) machine.device("ppc2")->safe_pc(),
	319	(unsigned) machine().device("ppc1")->safe_pc(),
	320	(unsigned) machine().device("ppc2")->safe_pc(),
326	321	val ? "Asserting" : "Clearing",
327	322	interrupt_bit, interrupt_names[interrupt_bit]);
328	323	}
329	324
330		old_interrupts = state->m_interrupts;
	325	old_interrupts = m_interrupts;
331	326	if (val)
332		state->m_interrupts |= 1 << interrupt_bit;
	327	m_interrupts |= 1 << interrupt_bit;
333	328	else
334		state->m_interrupts &= ~(1 << interrupt_bit);
	329	m_interrupts &= ~(1 << interrupt_bit);
335	330
336	331	/* if interrupt values have changed, update the lines */
337		if (state->m_interrupts != old_interrupts)
338		bebox_update_interrupts(machine);
	332	if (m_interrupts != old_interrupts)
	333	bebox_update_interrupts();
339	334	}
340	335
341	336
r29612	r29613
394	389
395	390	WRITE_LINE_MEMBER( bebox_state::fdc_interrupt )
396	391	{
397		bebox_set_irq_bit(machine(), 13, state);
	392	bebox_set_irq_bit(13, state);
398	393	m_pic8259_1->ir6_w(state);
399	394	}
400	395
r29612	r29613
408	403	{
409	404	UINT32 result;
410	405	result = m_pic8259_1->acknowledge();
411		bebox_set_irq_bit(space.machine(), 5, 0);   /* HACK */
	406	bebox_set_irq_bit(5, 0);   /* HACK */
412	407	return ((UINT64) result) << 56;
413	408	}
414	409
r29612	r29613
421	416
422	417	WRITE_LINE_MEMBER(bebox_state::bebox_pic8259_master_set_int_line)
423	418	{
424		bebox_set_irq_bit(machine(), 5, state);
	419	bebox_set_irq_bit(5, state);
425	420	}
426	421
427	422	WRITE_LINE_MEMBER(bebox_state::bebox_pic8259_slave_set_int_line)
r29612	r29613
443	438
444	439	WRITE_LINE_MEMBER(bebox_state::bebox_ide_interrupt)
445	440	{
446		bebox_set_irq_bit(machine(), 7, state);
	441	bebox_set_irq_bit(7, state);
447	442	m_pic8259_1->ir6_w(state);
448	443	}
449	444

trunk/src/mess/includes/bebox.h

r29612	r29613
105	105	DECLARE_WRITE_LINE_MEMBER( fdc_interrupt );
106	106	DECLARE_FLOPPY_FORMATS( floppy_formats );
107	107
	108	LSI53C810_FETCH_CB(scsi_fetch);
	109	LSI53C810_IRQ_CB(scsi_irq_callback);
	110	LSI53C810_DMA_CB(scsi_dma_callback);
	111
	112	void bebox_set_irq_bit(unsigned int interrupt_bit, int val);
	113	void bebox_update_interrupts();
	114
108	115	protected:
109	116	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
110	117	};
r29612	r29613
119	126	extern const ins8250_interface bebox_uart_inteface_2;
120	127	extern const ins8250_interface bebox_uart_inteface_3;
121	128
122		void bebox_set_irq_bit(running_machine &machine, unsigned int interrupt_bit, int val);
123
124	129	UINT32 scsi53c810_pci_read(device_t *busdevice, device_t *device, int function, int offset, UINT32 mem_mask);
125	130	void scsi53c810_pci_write(device_t *busdevice, device_t *device, int function, int offset, UINT32 data, UINT32 mem_mask);
126	131

trunk/src/mess/drivers/bebox.c

r29612	r29613
100	100	((x << 8) & 0xff0000) | \
101	101	((x << 24) & 0xff000000))
102	102
103		static UINT32 scsi53c810_fetch(running_machine &machine, UINT32 dsp)
	103	LSI53C810_FETCH_CB(bebox_state::scsi_fetch)
104	104	{
105		UINT32 result;
106		bebox_state *state = machine.driver_data<bebox_state>();
107		result = state->m_ppc1->space(AS_PROGRAM).read_dword(dsp & 0x7FFFFFFF);
	105	UINT32 result = m_ppc1->space(AS_PROGRAM).read_dword(dsp & 0x7FFFFFFF);
108	106	return BYTE_REVERSE32(result);
109	107	}
110	108
111	109
112		static void scsi53c810_irq_callback(running_machine &machine, int value)
	110	LSI53C810_IRQ_CB(bebox_state::scsi_irq_callback)
113	111	{
114		bebox_set_irq_bit(machine, 21, value);
	112	bebox_set_irq_bit(21, state);
115	113	}
116	114
117	115
118		static void scsi53c810_dma_callback(running_machine &machine, UINT32 src, UINT32 dst, int length, int byteswap)
	116	LSI53C810_DMA_CB(bebox_state::scsi_dma_callback)
119	117	{
120	118	}
121	119
122
123		static const struct LSI53C810interface lsi53c810_intf =
124		{
125		&scsi53c810_irq_callback,
126		&scsi53c810_dma_callback,
127		&scsi53c810_fetch,
128		};
129
130
131	120	FLOPPY_FORMATS_MEMBER( bebox_state::floppy_formats )
132	121	FLOPPY_PC_FORMAT
133	122	FLOPPY_FORMATS_END
r29612	r29613
150	139
151	140	WRITE_LINE_MEMBER(bebox_state::bebox_keyboard_interrupt)
152	141	{
153		bebox_set_irq_bit(machine(), 16, state);
	142	bebox_set_irq_bit(16, state);
154	143	m_pic8259_1->ir1_w(state);
155	144	}
156	145
r29612	r29613
202	191	MCFG_SCSIBUS_ADD("scsi")
203	192	MCFG_SCSIDEV_ADD("scsi:harddisk1", SCSIHD, SCSI_ID_0)
204	193	MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_3)
205		MCFG_LSI53C810_ADD( "scsi:lsi53c810", lsi53c810_intf)
	194	MCFG_DEVICE_ADD("scsi:lsi53c810", LSI53C810, 0)
	195	MCFG_LSI53C810_IRQ_CB(bebox_state, scsi_irq_callback)
	196	MCFG_LSI53C810_DMA_CB(bebox_state, scsi_dma_callback)
	197	MCFG_LSI53C810_FETCH_CB(bebox_state, scsi_fetch)
206	198
207	199	MCFG_IDE_CONTROLLER_ADD( "ide", ata_devices, "hdd", NULL, false ) /* FIXME */
208	200	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(bebox_state, bebox_ide_interrupt))

trunk/src/mame/drivers/model3.c

r29612	r29613
662	662	#include "includes/model3.h"
663	663
664	664
665		static void real3d_dma_callback(running_machine &machine, UINT32 src, UINT32 dst, int length, int byteswap);
666
667
668
669		static void update_irq_state(running_machine &machine)
	665	void model3_state::update_irq_state()
670	666	{
671		model3_state *state = machine.driver_data<model3_state>();
672		if ((state->m_irq_enable & state->m_irq_state) || state->m_scsi_irq_state)
	667	if ((m_irq_enable & m_irq_state) || m_scsi_irq_state)
673	668	{
674		//      printf("IRQ set: state %x enable %x scsi %x\n", state->m_irq_state, state->m_irq_enable, state->m_scsi_irq_state);
675		state->m_maincpu->set_input_line(PPC_IRQ, ASSERT_LINE);
676		state->m_scsi_irq_state = 0;
	669	//      printf("IRQ set: state %x enable %x scsi %x\n", m_irq_state, m_irq_enable, m_scsi_irq_state);
	670	m_maincpu->set_input_line(PPC_IRQ, ASSERT_LINE);
	671	m_scsi_irq_state = 0;
677	672	}
678	673	else
679	674	{
680		//      printf("IRQ clear: state %x enable %x scsi %x\n", state->m_irq_state, state->m_irq_enable, state->m_scsi_irq_state);
681		state->m_maincpu->set_input_line(PPC_IRQ, CLEAR_LINE);
	675	//      printf("IRQ clear: state %x enable %x scsi %x\n", m_irq_state, m_irq_enable, m_scsi_irq_state);
	676	m_maincpu->set_input_line(PPC_IRQ, CLEAR_LINE);
682	677	}
683	678	}
684	679
685		void model3_set_irq_line(running_machine &machine, UINT8 bit, int line)
	680	void model3_state::set_irq_line(UINT8 bit, int line)
686	681	{
687		model3_state *state = machine.driver_data<model3_state>();
688	682	if (line != CLEAR_LINE)
689		state->m_irq_state |= bit;
	683	m_irq_state |= bit;
690	684	else
691		state->m_irq_state &= ~bit;
692		update_irq_state(machine);
	685	m_irq_state &= ~bit;
	686	update_irq_state();
693	687	}
694	688
695	689
r29612	r29613
1056	1050	}
1057	1051	}
1058	1052
1059		static UINT32 scsi_fetch(running_machine &machine, UINT32 dsp)
	1053	LSI53C810_FETCH_CB(model3_state::scsi_fetch)
1060	1054	{
1061		model3_state *drvstate = machine.driver_data<model3_state>();
1062		address_space &space = drvstate->m_maincpu->space(AS_PROGRAM);
1063		UINT32 result;
1064		result = space.read_dword(dsp);
	1055	address_space &space = m_maincpu->space(AS_PROGRAM);
	1056	UINT32 result = space.read_dword(dsp);
1065	1057	return FLIPENDIAN_INT32(result);
1066	1058	}
1067	1059
1068		static void scsi_irq_callback(running_machine &machine, int state)
	1060	LSI53C810_IRQ_CB(model3_state::scsi_irq_callback)
1069	1061	{
1070		model3_state *drvstate = machine.driver_data<model3_state>();
1071		drvstate->m_scsi_irq_state = state;
1072		update_irq_state(machine);
	1062	m_scsi_irq_state = state;
	1063	update_irq_state();
1073	1064	}
1074	1065
1075	1066	/*****************************************************************************/
r29612	r29613
1112	1103	int length = FLIPENDIAN_INT32((UINT32)(data >> 32)) * 4;
1113	1104	if (m_dma_endian & 0x80)
1114	1105	{
1115		real3d_dma_callback(machine(), m_dma_source, m_dma_dest, length, 0);
	1106	real3d_dma_callback(m_dma_source, m_dma_dest, length, 0);
1116	1107	}
1117	1108	else
1118	1109	{
1119		real3d_dma_callback(machine(), m_dma_source, m_dma_dest, length, 1);
	1110	real3d_dma_callback(m_dma_source, m_dma_dest, length, 1);
1120	1111	}
1121	1112	m_dma_irq |= 0x01;
1122		scsi_irq_callback(machine(), 1);
	1113	scsi_irq_callback(1);
1123	1114	return;
1124	1115	}
1125	1116	else if(ACCESSING_BITS_16_23)
1126	1117	{
1127	1118	if(data & 0x10000) {
1128	1119	m_dma_irq &= ~0x1;
1129		scsi_irq_callback(machine(), 0);
	1120	scsi_irq_callback(0);
1130	1121	}
1131	1122	return;
1132	1123	}
r29612	r29613
1157	1148	logerror("real3d_dma_w: %08X, %08X%08X, %08X%08X", offset, (UINT32)(data >> 32), (UINT32)(data), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask));
1158	1149	}
1159	1150
1160		static void real3d_dma_callback(running_machine &machine, UINT32 src, UINT32 dst, int length, int byteswap)
	1151	LSI53C810_DMA_CB(model3_state::real3d_dma_callback)
1161	1152	{
1162		model3_state *drvstate = machine.driver_data<model3_state>();
1163		address_space &space = drvstate->m_maincpu->space(AS_PROGRAM);
1164	1153	switch(dst >> 24)
1165	1154	{
1166	1155	case 0x88:      /* Display List End Trigger */
1167		real3d_display_list_end(machine);
	1156	real3d_display_list_end();
1168	1157	break;
1169	1158	case 0x8c:      /* Display List RAM 2 */
1170		real3d_display_list2_dma(space, src, dst, length, byteswap);
	1159	real3d_display_list2_dma(src, dst, length, byteswap);
1171	1160	break;
1172	1161	case 0x8e:      /* Display List RAM 1 */
1173		real3d_display_list1_dma(space, src, dst, length, byteswap);
	1162	real3d_display_list1_dma(src, dst, length, byteswap);
1174	1163	break;
1175	1164	case 0x90:      /* VROM Texture Download */
1176		real3d_vrom_texture_dma(space, src, dst, length, byteswap);
	1165	real3d_vrom_texture_dma(src, dst, length, byteswap);
1177	1166	break;
1178	1167	case 0x94:      /* Texture FIFO */
1179		real3d_texture_fifo_dma(space, src, length, byteswap);
	1168	real3d_texture_fifo_dma(src, length, byteswap);
1180	1169	break;
1181	1170	case 0x98:      /* Polygon RAM */
1182		real3d_polygon_ram_dma(space, src, dst, length, byteswap);
	1171	real3d_polygon_ram_dma(src, dst, length, byteswap);
1183	1172	break;
1184	1173	case 0x9c:      /* Unknown */
1185	1174	break;
1186	1175	default:
1187		logerror("dma_callback: %08X, %08X, %d at %08X", src, dst, length, machine.device("maincpu")->safe_pc());
	1176	logerror("dma_callback: %08X, %08X, %d at %08X", src, dst, length, machine().device("maincpu")->safe_pc());
1188	1177	break;
1189	1178	}
1190	1179	}
1191	1180
1192	1181	/*****************************************************************************/
1193	1182
1194		static const struct LSI53C810interface lsi53c810_intf =
1195		{
1196		&scsi_irq_callback,
1197		&real3d_dma_callback,
1198		&scsi_fetch,
1199		};
1200
1201	1183	static void configure_fast_ram(running_machine &machine)
1202	1184	{
1203	1185	model3_state *state = machine.driver_data<model3_state>();
r29612	r29613
1212	1194	{
1213	1195	if (m_sound_irq_enable)
1214	1196	{
1215		model3_set_irq_line(machine(), 0x40, ASSERT_LINE);
	1197	set_irq_line(0x40, ASSERT_LINE);
1216	1198	}
1217	1199	}
1218	1200
r29612	r29613
1617	1599	{
1618	1600	case 0:
1619	1601	// clear the interrupt
1620		model3_set_irq_line(machine(), 0x40, CLEAR_LINE);
	1602	set_irq_line(0x40, CLEAR_LINE);
1621	1603
1622	1604	if (m_dsbz80 != NULL)
1623	1605	{
r29612	r29613
5395	5377	int scanline = param;
5396	5378
5397	5379	if (scanline == 384)
5398		model3_set_irq_line(machine(), 0x02, ASSERT_LINE);
	5380	set_irq_line(0x02, ASSERT_LINE);
5399	5381	else if(scanline == 0)
5400		model3_set_irq_line(machine(), 0x0d, ASSERT_LINE);
	5382	set_irq_line(0x0d, ASSERT_LINE);
5401	5383	}
5402	5384
5403	5385	static const powerpc_config model3_10 =
r29612	r29613
5457	5439	MCFG_SOUND_ROUTE(0, "rspeaker", 2.0)
5458	5440
5459	5441	MCFG_SCSIBUS_ADD("scsi")
5460		MCFG_LSI53C810_ADD( "scsi:lsi53c810", lsi53c810_intf)
	5442	MCFG_DEVICE_ADD("scsi:lsi53c810", LSI53C810, 0)
	5443	MCFG_LSI53C810_IRQ_CB(model3_state, scsi_irq_callback)
	5444	MCFG_LSI53C810_DMA_CB(model3_state, real3d_dma_callback)
	5445	MCFG_LSI53C810_FETCH_CB(model3_state, scsi_fetch)
5461	5446	MACHINE_CONFIG_END
5462	5447
5463	5448	static MACHINE_CONFIG_START( model3_15, model3_state )
r29612	r29613
5497	5482	MCFG_SOUND_ROUTE(0, "rspeaker", 2.0)
5498	5483
5499	5484	MCFG_SCSIBUS_ADD("scsi")
5500		MCFG_LSI53C810_ADD( "scsi:lsi53c810", lsi53c810_intf)
	5485	MCFG_DEVICE_ADD("scsi:lsi53c810", LSI53C810, 0)
	5486	MCFG_LSI53C810_IRQ_CB(model3_state, scsi_irq_callback)
	5487	MCFG_LSI53C810_DMA_CB(model3_state, real3d_dma_callback)
	5488	MCFG_LSI53C810_FETCH_CB(model3_state, scsi_fetch)
5501	5489	MACHINE_CONFIG_END
5502	5490
5503	5491	static MACHINE_CONFIG_DERIVED(scud, model3_15)

trunk/src/mame/includes/model3.h

r29612	r29613
214	214	TIMER_DEVICE_CALLBACK_MEMBER(model3_interrupt);
215	215	void model3_exit();
216	216	DECLARE_WRITE8_MEMBER(scsp_irq);
	217	LSI53C810_DMA_CB(real3d_dma_callback);
	218	LSI53C810_FETCH_CB(scsi_fetch);
	219	LSI53C810_IRQ_CB(scsi_irq_callback);
	220	void update_irq_state();
	221	void set_irq_line(UINT8 bit, int line);
	222	void real3d_display_list_end();
	223	void real3d_display_list1_dma(UINT32 src, UINT32 dst, int length, int byteswap);
	224	void real3d_display_list2_dma(UINT32 src, UINT32 dst, int length, int byteswap);
	225	void real3d_vrom_texture_dma(UINT32 src, UINT32 dst, int length, int byteswap);
	226	void real3d_texture_fifo_dma(UINT32 src, int length, int byteswap);
	227	void real3d_polygon_ram_dma(UINT32 src, UINT32 dst, int length, int byteswap);
217	228	};
218	229
219
220		/*----------- defined in drivers/model3.c -----------*/
221
222		void model3_set_irq_line(running_machine &machine, UINT8 bit, int state);
223
224
225	230	/*----------- defined in machine/model3.c -----------*/
226	231
227	232	void model3_machine_init(running_machine &machine, int step);
r29612	r29613
229	234	void model3_tap_write(running_machine &machine, int tck, int tms, int tdi, int trst);
230	235	void model3_tap_reset(running_machine &machine);
231	236
232
233		/*----------- defined in video/model3.c -----------*/
234
235		void real3d_display_list_end(running_machine &machine);
236		void real3d_display_list1_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap);
237		void real3d_display_list2_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap);
238		void real3d_vrom_texture_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap);
239		void real3d_texture_fifo_dma(address_space &space, UINT32 src, int length, int byteswap);
240		void real3d_polygon_ram_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap);

trunk/src/mame/video/model3.c

r29612	r29613
446	446	{
447	447	case 0x00/8:    logerror("vid_reg0: %08X%08X\n", (UINT32)(data>>32),(UINT32)(data)); m_vid_reg0 = data; break;
448	448	case 0x08/8:    break;      /* ??? */
449		case 0x10/8:    model3_set_irq_line(machine(), (data >> 56) & 0x0f, CLEAR_LINE); break;     /* VBL IRQ Ack */
	449	case 0x10/8:    set_irq_line((data >> 56) & 0x0f, CLEAR_LINE); break;     /* VBL IRQ Ack */
450	450
451	451	case 0x20/8:    m_layer_enable = (data >> 52);  break;
452	452
r29612	r29613
747	747	}
748	748	}
749	749
750		void real3d_display_list_end(running_machine &machine)
	750	void model3_state::real3d_display_list_end()
751	751	{
752		model3_state *state = machine.driver_data<model3_state>();
753	752	/* upload textures if there are any in the FIFO */
754		if (state->m_texture_fifo_pos > 0)
	753	if (m_texture_fifo_pos > 0)
755	754	{
756	755	int i = 0;
757		while(i < state->m_texture_fifo_pos)
	756	while (i < m_texture_fifo_pos)
758	757	{
759		int length = (state->m_texture_fifo[i] / 2) + 2;
760		UINT32 header = state->m_texture_fifo[i+1];
761		real3d_upload_texture(machine, header, &state->m_texture_fifo[i+2]);
	758	int length = (m_texture_fifo[i] / 2) + 2;
	759	UINT32 header = m_texture_fifo[i+1];
	760	real3d_upload_texture(machine(), header, &m_texture_fifo[i+2]);
762	761	i += length;
763	762	};
764	763	}
765		state->m_texture_fifo_pos = 0;
766		state->m_zbuffer.fill(0);
767		state->m_bitmap3d.fill(0x8000);
768		real3d_traverse_display_list(machine);
	764	m_texture_fifo_pos = 0;
	765	m_zbuffer.fill(0);
	766	m_bitmap3d.fill(0x8000);
	767	real3d_traverse_display_list(machine());
769	768	//state->m_real3d_display_list = 1;
770	769	}
771	770
772		void real3d_display_list1_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap)
	771	void model3_state::real3d_display_list1_dma(UINT32 src, UINT32 dst, int length, int byteswap)
773	772	{
774		model3_state *state = space.machine().driver_data<model3_state>();
775		int i;
	773	address_space &space = m_maincpu->space(AS_PROGRAM);
776	774	int d = (dst & 0xffffff) / 4;
777		for(i=0; i < length; i+=4) {
	775	for (int i = 0; i < length; i += 4)
	776	{
778	777	UINT32 w;
779	778	if (byteswap) {
780	779	w = BYTE_REVERSE32(space.read_dword(src));
781	780	} else {
782	781	w = space.read_dword(src);
783	782	}
784		state->m_display_list_ram[d++] = w;
	783	m_display_list_ram[d++] = w;
785	784	src += 4;
786	785	}
787	786	}
788	787
789		void real3d_display_list2_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap)
	788	void model3_state::real3d_display_list2_dma(UINT32 src, UINT32 dst, int length, int byteswap)
790	789	{
791		model3_state *state = space.machine().driver_data<model3_state>();
792		int i;
	790	address_space &space = m_maincpu->space(AS_PROGRAM);
793	791	int d = (dst & 0xffffff) / 4;
794		for(i=0; i < length; i+=4) {
	792	for (int i = 0; i < length; i += 4)
	793	{
795	794	UINT32 w;
796	795	if (byteswap) {
797	796	w = BYTE_REVERSE32(space.read_dword(src));
798	797	} else {
799	798	w = space.read_dword(src);
800	799	}
801		state->m_culling_ram[d++] = w;
	800	m_culling_ram[d++] = w;
802	801	src += 4;
803	802	}
804	803	}
805	804
806		void real3d_vrom_texture_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap)
	805	void model3_state::real3d_vrom_texture_dma(UINT32 src, UINT32 dst, int length, int byteswap)
807	806	{
808		model3_state *state = space.machine().driver_data<model3_state>();
	807	address_space &space = m_maincpu->space(AS_PROGRAM);
809	808	if((dst & 0xff) == 0) {
810	809	UINT32 address, header;
811	810
r29612	r29613
816	815	address = space.read_dword((src+0));
817	816	header = space.read_dword((src+4));
818	817	}
819		real3d_upload_texture(space.machine(), header, (UINT32*)&state->m_vrom[address]);
	818	real3d_upload_texture(space.machine(), header, (UINT32*)&m_vrom[address]);
820	819	}
821	820	}
822	821
823		void real3d_texture_fifo_dma(address_space &space, UINT32 src, int length, int byteswap)
	822	void model3_state::real3d_texture_fifo_dma(UINT32 src, int length, int byteswap)
824	823	{
825		model3_state *state = space.machine().driver_data<model3_state>();
826		int i;
827		for(i=0; i < length; i+=4) {
	824	address_space &space = m_maincpu->space(AS_PROGRAM);
	825	for (int i = 0; i < length; i += 4)
	826	{
828	827	UINT32 w;
829	828	if (byteswap) {
830	829	w = BYTE_REVERSE32(space.read_dword(src));
831	830	} else {
832	831	w = space.read_dword(src);
833	832	}
834		state->m_texture_fifo[state->m_texture_fifo_pos] = w;
835		state->m_texture_fifo_pos++;
	833	m_texture_fifo[m_texture_fifo_pos] = w;
	834	m_texture_fifo_pos++;
836	835	src += 4;
837	836	}
838	837	}
839	838
840		void real3d_polygon_ram_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap)
	839	void model3_state::real3d_polygon_ram_dma(UINT32 src, UINT32 dst, int length, int byteswap)
841	840	{
842		model3_state *state = space.machine().driver_data<model3_state>();
843		int i;
	841	address_space &space = m_maincpu->space(AS_PROGRAM);
844	842	int d = (dst & 0xffffff) / 4;
845		for(i=0; i < length; i+=4) {
	843	for (int i = 0; i < length; i += 4)
	844	{
846	845	UINT32 w;
847	846	if (byteswap) {
848	847	w = BYTE_REVERSE32(space.read_dword(src));
849	848	} else {
850	849	w = space.read_dword(src);
851	850	}
852		state->m_polygon_ram[d++] = w;
	851	m_polygon_ram[d++] = w;
853	852	src += 4;
854	853	}
855	854	}
856	855
857	856	WRITE64_MEMBER(model3_state::real3d_cmd_w)
858	857	{
859		real3d_display_list_end(machine());
	858	real3d_display_list_end();
860	859	}
861	860
862	861

trunk/src/emu/machine/53c810.c

r29612	r29613
9	9
10	10	UINT32 lsi53c810_device::FETCH()
11	11	{
12		UINT32 r = fetch(machine(), dsp);
	12	UINT32 r = m_fetch_cb(dsp);
13	13	dsp += 4;
14	14	return r;
15	15	}
r29612	r29613
26	26	int count;
27	27
28	28	count = dcmd & 0xffffff;
29		if(dma_callback != NULL) {
30		dma_callback(machine(), src, dst, count, 1);
31		}
	29	if (!m_dma_cb.isnull())
	30	m_dma_cb(src, dst, count, 1);
32	31	}
33	32
34	33	void lsi53c810_device::dmaop_interrupt()
r29612	r29613
41	40	istat |= 0x1;   /* DMA interrupt pending */
42	41	dstat |= 0x4;   /* SIR (SCRIPTS Interrupt Instruction Received) */
43	42
44		if(irq_callback != NULL) {
45		irq_callback(machine(), 1);
46		}
	43	if (!m_irq_cb.isnull())
	44	m_irq_cb(1);
	45
47	46	dma_icount = 0;
48	47	halted = 1;
49	48	}
r29612	r29613
59	58
60	59	// normal indirect
61	60	if (dcmd & 0x20000000)
62		address = fetch(machine(), address);
	61	address = m_fetch_cb(address);
63	62
64	63	// table indirect
65	64	if (dcmd & 0x10000000)
r29612	r29613
74	73	dsps += dsa;
75	74
76	75	logerror("Loading from table at %x\n", dsps);
77		count = fetch(machine(),dsps);
78		address = fetch(machine(),dsps+4);
	76	count = m_fetch_cb(dsps);
	77	address = m_fetch_cb(dsps + 4);
79	78	}
80	79
81	80	logerror("block move: address %x count %x phase %x\n", address, count, (dcmd>>24)&7);
r29612	r29613
428	427	return (dsa >> 24) & 0xff;
429	428	case 0x14:      /* ISTAT */
430	429	// clear the interrupt on service
431		if(irq_callback != NULL)
432		{
433		irq_callback(machine(), 0);
434		}
	430	if (!m_irq_cb.isnull())
	431	m_irq_cb(0);
435	432
436	433	return istat;
437	434	case 0x2c:      /* DSP [7-0] */
r29612	r29613
572	569
573	570	istat |= 0x3;   /* DMA interrupt pending */
574	571	dstat |= 0x8;   /* SSI (Single Step Interrupt) */
575		if(irq_callback != NULL) {
576		irq_callback(machine(), 1);
577		}
	572	if (!m_irq_cb.isnull())
	573	m_irq_cb(1);
578	574	}
579	575	else if(dcntl & 0x04 && !halted)    /* manual start DMA */
580	576	{
r29612	r29613
610	606
611	607	void lsi53c810_device::add_opcode(UINT8 op, UINT8 mask, opcode_handler_delegate handler)
612	608	{
613		int i;
614		for(i=0; i < 256; i++) {
615		if((i & mask) == op) {
	609	for (int i = 0; i < 256; i++)
	610	{
	611	if ((i & mask) == op)
	612	{
616	613	dma_opcode[i] = handler;
617	614	}
618	615	}
r29612	r29613
623	620	{
624	621	}
625	622
626		void lsi53c810_device::device_config_complete()
627		{
628		// inherit a copy of the static data
629		const LSI53C810interface *intf = reinterpret_cast<const LSI53C810interface *>(static_config());
630		if (intf != NULL)
631		{
632		*static_cast<LSI53C810interface *>(this) = *intf;
633		}
634		}
635
636	623	void lsi53c810_device::device_start()
637	624	{
638		int i;
639
640		for(i = 0; i < 256; i++)
	625	m_irq_cb.bind_relative_to(*owner());
	626	m_dma_cb.bind_relative_to(*owner());
	627	m_fetch_cb.bind_relative_to(*owner());
	628
	629	for (int i = 0; i < 256; i++)
641	630	{
642		dma_opcode[i] = opcode_handler_delegate(FUNC( lsi53c810_device::dmaop_invalid ), this);
	631	dma_opcode[i] = opcode_handler_delegate(FUNC(lsi53c810_device::dmaop_invalid), this);
643	632	}
644	633
645	634	add_opcode(0x00, 0xc0, opcode_handler_delegate(FUNC( lsi53c810_device::dmaop_block_move ), this));
r29612	r29613
662	651	memset(devices, 0, sizeof(devices));
663	652
664	653	// try to open the devices
665		for( device_t *device = owner()->first_subdevice(); device != NULL; device = device->next() )
	654	for (device_t *device = owner()->first_subdevice(); device != NULL; device = device->next())
666	655	{
667	656	scsihle_device *scsidev = dynamic_cast<scsihle_device *>(device);
668		if( scsidev != NULL )
	657	if (scsidev != NULL)
669	658	{
670	659	devices[scsidev->GetDeviceID()] = scsidev;
671	660	}
r29612	r29613
704	693
705	694	UINT32 lsi53c810_device::lsi53c810_dasm_fetch(UINT32 pc)
706	695	{
707		return fetch(machine(), pc);
	696	return m_fetch_cb(pc);
708	697	}
709	698
710	699	unsigned lsi53c810_device::lsi53c810_dasm(char *buf, UINT32 pc)

trunk/src/emu/machine/53c810.h

r29612	r29613
3	3
4	4	#include "machine/scsihle.h"
5	5
6		struct LSI53C810interface
7		{
8		void (*irq_callback)(running_machine &machine, int); /* IRQ callback */
9		void (*dma_callback)(running_machine &machine, UINT32, UINT32, int, int);   /* DMA callback */
10		UINT32 (*fetch)(running_machine &machine, UINT32 dsp);
11		};
	6	typedef device_delegate<void (int state)> lsi53c810_irq_delegate;
	7	#define LSI53C810_IRQ_CB(name)  void name(int state)
12	8
13		#define MCFG_LSI53C810_ADD( _tag, _config ) \
14		MCFG_DEVICE_ADD( _tag, LSI53C810, 0 ) \
15		MCFG_DEVICE_CONFIG(_config)
	9	typedef device_delegate<void (UINT32 src, UINT32 dst, int length, int byteswap)> lsi53c810_dma_delegate;
	10	#define LSI53C810_DMA_CB(name)  void name(UINT32 src, UINT32 dst, int length, int byteswap)
16	11
17		class lsi53c810_device : public device_t,
18		public LSI53C810interface
	12	typedef device_delegate<UINT32 (UINT32 dsp)> lsi53c810_fetch_delegate;
	13	#define LSI53C810_FETCH_CB(name)  UINT32 name(UINT32 dsp)
	14
	15
	16	class lsi53c810_device : public device_t
19	17	{
20	18	public:
21	19	// construction/destruction
22	20	lsi53c810_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
23	21
	22	static void set_irq_callback(device_t &device, lsi53c810_irq_delegate callback) { downcast<lsi53c810_device &>(device).m_irq_cb = callback; }
	23	static void set_dma_callback(device_t &device, lsi53c810_dma_delegate callback) { downcast<lsi53c810_device &>(device).m_dma_cb = callback; }
	24	static void set_fetch_callback(device_t &device, lsi53c810_fetch_delegate callback) { downcast<lsi53c810_device &>(device).m_fetch_cb = callback; }
	25
24	26	void lsi53c810_read_data(int bytes, UINT8 *pData);
25	27	void lsi53c810_write_data(int bytes, UINT8 *pData);
26	28
r29612	r29613
29	31
30	32	protected:
31	33	// device-level overrides
32		virtual void device_config_complete();
33	34	virtual void device_start();
34	35
35	36	private:
36	37	typedef delegate<void (void)> opcode_handler_delegate;
37	38	opcode_handler_delegate dma_opcode[256];
38	39
	40	lsi53c810_irq_delegate m_irq_cb;
	41	lsi53c810_dma_delegate m_dma_cb;
	42	lsi53c810_fetch_delegate m_fetch_cb;
	43
39	44	UINT32 FETCH();
40	45	void dmaop_invalid();
41	46	void dmaop_move_memory();
r29612	r29613
100	105	// device type definition
101	106	extern const device_type LSI53C810;
102	107
	108
	109	#define MCFG_LSI53C810_IRQ_CB(_class, _method) \
	110	lsi53c810_device::set_irq_callback(*device, lsi53c810_irq_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
	111
	112	#define MCFG_LSI53C810_DMA_CB(_class, _method) \
	113	lsi53c810_device::set_dma_callback(*device, lsi53c810_dma_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
	114
	115	#define MCFG_LSI53C810_FETCH_CB(_class, _method) \
	116	lsi53c810_device::set_fetch_callback(*device, lsi53c810_fetch_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
	117
103	118	#endif

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