trunk/src/emu/machine/8257dma.c
| r29554 | r29555 | |
| 60 | 60 | |
| 61 | 61 | i8257_device::i8257_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
| 62 | 62 | : device_t(mconfig, I8257, "DMA8257", tag, owner, clock, "i8257", __FILE__), |
| 63 | m_out_hrq_cb(*this), |
| 64 | m_out_tc_cb(*this), |
| 65 | m_out_mark_cb(*this), |
| 66 | m_in_memr_cb(*this), |
| 67 | m_out_memw_cb(*this), |
| 68 | m_in_ior_0_cb(*this), |
| 69 | m_in_ior_1_cb(*this), |
| 70 | m_in_ior_2_cb(*this), |
| 71 | m_in_ior_3_cb(*this), |
| 72 | m_out_iow_0_cb(*this), |
| 73 | m_out_iow_1_cb(*this), |
| 74 | m_out_iow_2_cb(*this), |
| 75 | m_out_iow_3_cb(*this), |
| 63 | 76 | m_mode(0), |
| 64 | 77 | m_rr(0), |
| 65 | 78 | m_msb(0), |
| r29554 | r29555 | |
| 72 | 85 | memset(m_rwmode, 0, sizeof(m_rwmode)); |
| 73 | 86 | } |
| 74 | 87 | |
| 75 | | |
| 76 | 88 | //------------------------------------------------- |
| 77 | | // device_config_complete - perform any |
| 78 | | // operations now that the configuration is |
| 79 | | // complete |
| 80 | | //------------------------------------------------- |
| 81 | | |
| 82 | | void i8257_device::device_config_complete() |
| 83 | | { |
| 84 | | // inherit a copy of the static data |
| 85 | | const i8257_interface *intf = reinterpret_cast<const i8257_interface *>(static_config()); |
| 86 | | if (intf != NULL) |
| 87 | | { |
| 88 | | *static_cast<i8257_interface *>(this) = *intf; |
| 89 | | } |
| 90 | | |
| 91 | | // or initialize to defaults if none provided |
| 92 | | else |
| 93 | | { |
| 94 | | memset(&m_out_hrq_cb, 0, sizeof(m_out_hrq_cb)); |
| 95 | | memset(&m_out_tc_cb, 0, sizeof(m_out_tc_cb)); |
| 96 | | memset(&m_out_mark_cb, 0, sizeof(m_out_mark_cb)); |
| 97 | | memset(&m_in_memr_cb, 0, sizeof(m_in_memr_cb)); |
| 98 | | memset(&m_out_memw_cb, 0, sizeof(m_out_memw_cb)); |
| 99 | | memset(&m_in_ior_cb[0], 0, sizeof(m_in_ior_cb[0])); |
| 100 | | memset(&m_in_ior_cb[1], 0, sizeof(m_in_ior_cb[1])); |
| 101 | | memset(&m_in_ior_cb[2], 0, sizeof(m_in_ior_cb[2])); |
| 102 | | memset(&m_in_ior_cb[3], 0, sizeof(m_in_ior_cb[3])); |
| 103 | | memset(&m_out_iow_cb[0], 0, sizeof(m_out_iow_cb[0])); |
| 104 | | memset(&m_out_iow_cb[1], 0, sizeof(m_out_iow_cb[1])); |
| 105 | | memset(&m_out_iow_cb[2], 0, sizeof(m_out_iow_cb[2])); |
| 106 | | memset(&m_out_iow_cb[3], 0, sizeof(m_out_iow_cb[3])); |
| 107 | | } |
| 108 | | } |
| 109 | | |
| 110 | | |
| 111 | | //------------------------------------------------- |
| 112 | 89 | // device_start - device-specific startup |
| 113 | 90 | //------------------------------------------------- |
| 114 | 91 | |
| r29554 | r29555 | |
| 118 | 95 | assert(this != NULL); |
| 119 | 96 | |
| 120 | 97 | /* resolve callbacks */ |
| 121 | | m_out_hrq_func.resolve(m_out_hrq_cb, *this); |
| 122 | | m_out_tc_func.resolve(m_out_tc_cb, *this); |
| 123 | | m_out_mark_func.resolve(m_out_mark_cb, *this); |
| 124 | | m_in_memr_func.resolve(m_in_memr_cb, *this); |
| 125 | | m_out_memw_func.resolve(m_out_memw_cb, *this); |
| 126 | | |
| 127 | | for (int i = 0; i < I8257_NUM_CHANNELS; i++) |
| 128 | | { |
| 129 | | m_in_ior_func[i].resolve(m_in_ior_cb[i], *this); |
| 130 | | m_out_iow_func[i].resolve(m_out_iow_cb[i], *this); |
| 131 | | } |
| 132 | | |
| 98 | m_out_hrq_cb.resolve_safe(); |
| 99 | m_out_tc_cb.resolve_safe(); |
| 100 | m_out_mark_cb.resolve_safe(); |
| 101 | m_in_memr_cb.resolve(); |
| 102 | m_out_memw_cb.resolve(); |
| 103 | m_in_ior_0_cb.resolve(); |
| 104 | m_in_ior_1_cb.resolve(); |
| 105 | m_in_ior_2_cb.resolve(); |
| 106 | m_in_ior_3_cb.resolve(); |
| 107 | m_out_iow_0_cb.resolve(); |
| 108 | m_out_iow_1_cb.resolve(); |
| 109 | m_out_iow_2_cb.resolve(); |
| 110 | m_out_iow_3_cb.resolve(); |
| 111 | |
| 133 | 112 | /* set initial values */ |
| 134 | 113 | m_timer = timer_alloc(TIMER_OPERATION); |
| 135 | 114 | m_msbflip_timer = timer_alloc(TIMER_MSBFLIP); |
| r29554 | r29555 | |
| 162 | 141 | int i8257_device::i8257_do_operation(int channel) |
| 163 | 142 | { |
| 164 | 143 | int done; |
| 165 | | UINT8 data; |
| 144 | UINT8 data = 0; |
| 166 | 145 | |
| 167 | 146 | UINT8 mode = m_rwmode[channel]; |
| 168 | 147 | if (m_count[channel] == 0x0000) |
| 169 | 148 | { |
| 170 | 149 | m_status |= (0x01 << channel); |
| 171 | 150 | |
| 172 | | m_out_tc_func(ASSERT_LINE); |
| 151 | m_out_tc_cb(ASSERT_LINE); |
| 173 | 152 | } |
| 174 | | switch(mode) { |
| 153 | |
| 154 | switch(mode) |
| 155 | { |
| 175 | 156 | case 1: |
| 176 | | if (!m_in_memr_func.isnull()) |
| 177 | | { |
| 178 | | data = m_in_memr_func(m_address[channel]); |
| 179 | | } |
| 157 | if (!m_in_memr_cb.isnull()) |
| 158 | data = m_in_memr_cb(m_address[channel]); |
| 180 | 159 | else |
| 181 | 160 | { |
| 182 | 161 | data = 0; |
| 183 | 162 | logerror("8257: No memory read function defined.\n"); |
| 184 | 163 | } |
| 185 | | if (!m_out_iow_func[channel].isnull()) |
| 164 | |
| 165 | switch (channel) |
| 186 | 166 | { |
| 187 | | m_out_iow_func[channel](m_address[channel], data); |
| 167 | case 0: |
| 168 | if (!m_out_iow_0_cb.isnull()) |
| 169 | m_out_iow_0_cb((offs_t)m_address[channel], data); |
| 170 | else |
| 171 | logerror("8257: No channel write function for channel %d defined.\n", channel); |
| 172 | break; |
| 173 | case 1: |
| 174 | if (!m_out_iow_1_cb.isnull()) |
| 175 | m_out_iow_1_cb((offs_t)m_address[channel], data); |
| 176 | else |
| 177 | logerror("8257: No channel write function for channel %d defined.\n", channel); |
| 178 | break; |
| 179 | case 2: |
| 180 | if (!m_out_iow_2_cb.isnull()) |
| 181 | m_out_iow_2_cb((offs_t)m_address[channel], data); |
| 182 | else |
| 183 | logerror("8257: No channel write function for channel %d defined.\n", channel); |
| 184 | break; |
| 185 | case 3: |
| 186 | if (!m_out_iow_3_cb.isnull()) |
| 187 | m_out_iow_3_cb((offs_t)m_address[channel], data); |
| 188 | else |
| 189 | logerror("8257: No channel write function for channel %d defined.\n", channel); |
| 190 | break; |
| 188 | 191 | } |
| 189 | | else |
| 190 | | { |
| 191 | | logerror("8257: No channel write function for channel %d defined.\n",channel); |
| 192 | | } |
| 193 | 192 | |
| 194 | 193 | m_address[channel]++; |
| 195 | 194 | m_count[channel]--; |
| r29554 | r29555 | |
| 197 | 196 | break; |
| 198 | 197 | |
| 199 | 198 | case 2: |
| 200 | | if (!m_in_ior_func[channel].isnull()) |
| 199 | switch (channel) |
| 201 | 200 | { |
| 202 | | data = m_in_ior_func[channel](m_address[channel]); |
| 201 | case 0: |
| 202 | if (!m_in_ior_0_cb.isnull()) |
| 203 | data = m_in_ior_0_cb((offs_t)m_address[channel]); |
| 204 | else |
| 205 | { |
| 206 | data = 0; |
| 207 | logerror("8257: No channel read function for channel %d defined.\n", channel); |
| 208 | } |
| 209 | break; |
| 210 | case 1: |
| 211 | if (!m_in_ior_1_cb.isnull()) |
| 212 | data = m_in_ior_1_cb((offs_t)m_address[channel]); |
| 213 | else |
| 214 | { |
| 215 | data = 0; |
| 216 | logerror("8257: No channel read function for channel %d defined.\n", channel); |
| 217 | } |
| 218 | break; |
| 219 | case 2: |
| 220 | if (!m_in_ior_2_cb.isnull()) |
| 221 | data = m_in_ior_2_cb((offs_t)m_address[channel]); |
| 222 | else |
| 223 | { |
| 224 | data = 0; |
| 225 | logerror("8257: No channel read function for channel %d defined.\n", channel); |
| 226 | } |
| 227 | break; |
| 228 | case 3: |
| 229 | if (!m_in_ior_3_cb.isnull()) |
| 230 | data = m_in_ior_3_cb((offs_t)m_address[channel]); |
| 231 | else |
| 232 | { |
| 233 | data = 0; |
| 234 | logerror("8257: No channel read function for channel %d defined.\n", channel); |
| 235 | } |
| 236 | break; |
| 203 | 237 | } |
| 204 | | else |
| 205 | | { |
| 206 | | data = 0; |
| 207 | | logerror("8257: No channel read function for channel %d defined.\n",channel); |
| 208 | | } |
| 209 | 238 | |
| 210 | | if (!m_out_memw_func.isnull()) |
| 211 | | { |
| 212 | | m_out_memw_func(m_address[channel], data); |
| 213 | | } |
| 239 | if (!m_out_memw_cb.isnull()) |
| 240 | m_out_memw_cb((offs_t)m_address[channel], data); |
| 214 | 241 | else |
| 215 | | { |
| 216 | 242 | logerror("8257: No memory write function defined.\n"); |
| 217 | | } |
| 243 | |
| 218 | 244 | m_address[channel]++; |
| 219 | 245 | m_count[channel]--; |
| 220 | | done = (m_count[channel] == 0xFFFF); |
| 246 | done = (m_count[channel] == 0xffff); |
| 221 | 247 | break; |
| 248 | |
| 222 | 249 | case 0: /* verify */ |
| 223 | 250 | m_address[channel]++; |
| 224 | 251 | m_count[channel]--; |
| 225 | | done = (m_count[channel] == 0xFFFF); |
| 252 | done = (m_count[channel] == 0xffff); |
| 226 | 253 | break; |
| 254 | |
| 227 | 255 | default: |
| 228 | 256 | fatalerror("i8257_do_operation: invalid mode!\n"); |
| 229 | 257 | break; |
| 230 | 258 | } |
| 259 | |
| 231 | 260 | if (done) |
| 232 | 261 | { |
| 233 | 262 | if ((channel==2) && DMA_MODE_AUTOLOAD(m_mode)) |
| r29554 | r29555 | |
| 238 | 267 | m_registers[5] = m_registers[7]; |
| 239 | 268 | } |
| 240 | 269 | |
| 241 | | m_out_tc_func(CLEAR_LINE); |
| 270 | m_out_tc_cb(CLEAR_LINE); |
| 242 | 271 | } |
| 243 | 272 | return done; |
| 244 | 273 | } |
| r29554 | r29555 | |
| 337 | 366 | } |
| 338 | 367 | |
| 339 | 368 | /* set the halt line */ |
| 340 | | m_out_hrq_func(pending_transfer ? ASSERT_LINE : CLEAR_LINE); |
| 369 | m_out_hrq_cb(pending_transfer ? ASSERT_LINE : CLEAR_LINE); |
| 341 | 370 | } |
| 342 | 371 | |
| 343 | 372 | |
trunk/src/emu/machine/8257dma.h
| r29554 | r29555 | |
| 40 | 40 | #include "emu.h" |
| 41 | 41 | |
| 42 | 42 | |
| 43 | #define I8257_NUM_CHANNELS (4) |
| 43 | 44 | |
| 45 | |
| 44 | 46 | /*************************************************************************** |
| 45 | 47 | DEVICE CONFIGURATION MACROS |
| 46 | 48 | ***************************************************************************/ |
| 47 | 49 | |
| 48 | | #define MCFG_I8257_ADD(_tag, _clock, _config) \ |
| 49 | | MCFG_DEVICE_ADD(_tag, I8257, _clock) \ |
| 50 | | MCFG_DEVICE_CONFIG(_config) |
| 50 | #define MCFG_I8257_OUT_HRQ_CB(_devcb) \ |
| 51 | devcb = &i8257_device::set_out_hrq_callback(*device, DEVCB2_##_devcb); |
| 51 | 52 | |
| 52 | | #define I8257_INTERFACE(_name) \ |
| 53 | | const i8257_interface (_name) = |
| 53 | #define MCFG_I8257_OUT_TC_CB(_devcb) \ |
| 54 | devcb = &i8257_device::set_out_tc_callback(*device, DEVCB2_##_devcb); |
| 54 | 55 | |
| 55 | | #define I8257_NUM_CHANNELS (4) |
| 56 | #define MCFG_I8257_OUT_MARK_CB(_devcb) \ |
| 57 | devcb = &i8257_device::set_out_mark_callback(*device, DEVCB2_##_devcb); |
| 56 | 58 | |
| 57 | 59 | |
| 58 | | /*************************************************************************** |
| 59 | | TYPE DEFINITIONS |
| 60 | | ***************************************************************************/ |
| 60 | #define MCFG_I8257_IN_MEMR_CB(_devcb) \ |
| 61 | devcb = &i8257_device::set_in_memr_callback(*device, DEVCB2_##_devcb); |
| 61 | 62 | |
| 63 | #define MCFG_I8257_OUT_MEMW_CB(_devcb) \ |
| 64 | devcb = &i8257_device::set_out_memw_callback(*device, DEVCB2_##_devcb); |
| 62 | 65 | |
| 63 | | // ======================> i8257_interface |
| 64 | 66 | |
| 65 | | struct i8257_interface |
| 66 | | { |
| 67 | | devcb_write_line m_out_hrq_cb; |
| 68 | | devcb_write_line m_out_tc_cb; |
| 69 | | devcb_write_line m_out_mark_cb; |
| 67 | #define MCFG_I8257_IN_IOR_0_CB(_devcb) \ |
| 68 | devcb = &i8257_device::set_in_ior_0_callback(*device, DEVCB2_##_devcb); |
| 70 | 69 | |
| 71 | | /* accessors to main memory */ |
| 72 | | devcb_read8 m_in_memr_cb; // TODO m_in_memr_cb[I8257_NUM_CHANNELS]; |
| 73 | | devcb_write8 m_out_memw_cb; // TODO m_out_memw_cb[I8257_NUM_CHANNELS]; |
| 70 | #define MCFG_I8257_IN_IOR_1_CB(_devcb) \ |
| 71 | devcb = &i8257_device::set_in_ior_1_callback(*device, DEVCB2_##_devcb); |
| 74 | 72 | |
| 75 | | /* channel accesors */ |
| 76 | | devcb_read8 m_in_ior_cb[I8257_NUM_CHANNELS]; |
| 77 | | devcb_write8 m_out_iow_cb[I8257_NUM_CHANNELS]; |
| 78 | | }; |
| 73 | #define MCFG_I8257_IN_IOR_2_CB(_devcb) \ |
| 74 | devcb = &i8257_device::set_in_ior_2_callback(*device, DEVCB2_##_devcb); |
| 79 | 75 | |
| 76 | #define MCFG_I8257_IN_IOR_3_CB(_devcb) \ |
| 77 | devcb = &i8257_device::set_in_ior_3_callback(*device, DEVCB2_##_devcb); |
| 80 | 78 | |
| 81 | 79 | |
| 80 | #define MCFG_I8257_OUT_IOW_0_CB(_devcb) \ |
| 81 | devcb = &i8257_device::set_out_iow_0_callback(*device, DEVCB2_##_devcb); |
| 82 | |
| 83 | #define MCFG_I8257_OUT_IOW_1_CB(_devcb) \ |
| 84 | devcb = &i8257_device::set_out_iow_1_callback(*device, DEVCB2_##_devcb); |
| 85 | |
| 86 | #define MCFG_I8257_OUT_IOW_2_CB(_devcb) \ |
| 87 | devcb = &i8257_device::set_out_iow_2_callback(*device, DEVCB2_##_devcb); |
| 88 | |
| 89 | #define MCFG_I8257_OUT_IOW_3_CB(_devcb) \ |
| 90 | devcb = &i8257_device::set_out_iow_3_callback(*device, DEVCB2_##_devcb); |
| 91 | |
| 92 | |
| 93 | /*************************************************************************** |
| 94 | TYPE DEFINITIONS |
| 95 | ***************************************************************************/ |
| 96 | |
| 97 | |
| 82 | 98 | // ======================> i8257_device |
| 83 | 99 | |
| 84 | | class i8257_device : public device_t, |
| 85 | | public i8257_interface |
| 100 | class i8257_device : public device_t |
| 86 | 101 | { |
| 87 | 102 | public: |
| 88 | 103 | // construction/destruction |
| 89 | 104 | i8257_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
| 90 | 105 | |
| 106 | template<class _Object> static devcb2_base &set_out_hrq_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_out_hrq_cb.set_callback(object); } |
| 107 | template<class _Object> static devcb2_base &set_out_tc_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_out_tc_cb.set_callback(object); } |
| 108 | template<class _Object> static devcb2_base &set_out_mark_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_out_mark_cb.set_callback(object); } |
| 109 | |
| 110 | template<class _Object> static devcb2_base &set_in_memr_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_in_memr_cb.set_callback(object); } |
| 111 | template<class _Object> static devcb2_base &set_out_memw_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_out_memw_cb.set_callback(object); } |
| 112 | |
| 113 | template<class _Object> static devcb2_base &set_in_ior_0_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_in_ior_0_cb.set_callback(object); } |
| 114 | template<class _Object> static devcb2_base &set_in_ior_1_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_in_ior_1_cb.set_callback(object); } |
| 115 | template<class _Object> static devcb2_base &set_in_ior_2_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_in_ior_2_cb.set_callback(object); } |
| 116 | template<class _Object> static devcb2_base &set_in_ior_3_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_in_ior_3_cb.set_callback(object); } |
| 117 | |
| 118 | template<class _Object> static devcb2_base &set_out_iow_0_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_out_iow_0_cb.set_callback(object); } |
| 119 | template<class _Object> static devcb2_base &set_out_iow_1_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_out_iow_1_cb.set_callback(object); } |
| 120 | template<class _Object> static devcb2_base &set_out_iow_2_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_out_iow_2_cb.set_callback(object); } |
| 121 | template<class _Object> static devcb2_base &set_out_iow_3_callback(device_t &device, _Object object) { return downcast<i8257_device &>(device).m_out_iow_3_cb.set_callback(object); } |
| 122 | |
| 91 | 123 | /* register access */ |
| 92 | 124 | DECLARE_READ8_MEMBER( i8257_r ); |
| 93 | 125 | DECLARE_WRITE8_MEMBER( i8257_w ); |
| r29554 | r29555 | |
| 107 | 139 | |
| 108 | 140 | protected: |
| 109 | 141 | // device-level overrides |
| 110 | | virtual void device_config_complete(); |
| 111 | 142 | virtual void device_start(); |
| 112 | 143 | virtual void device_reset(); |
| 113 | 144 | virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr); |
| r29554 | r29555 | |
| 121 | 152 | void i8257_update_status(); |
| 122 | 153 | void i8257_prepare_msb_flip(); |
| 123 | 154 | |
| 124 | | devcb_resolved_write_line m_out_hrq_func; |
| 125 | | devcb_resolved_write_line m_out_tc_func; |
| 126 | | devcb_resolved_write_line m_out_mark_func; |
| 127 | | devcb_resolved_read8 m_in_memr_func; |
| 128 | | devcb_resolved_write8 m_out_memw_func; |
| 129 | | devcb_resolved_read8 m_in_ior_func[I8257_NUM_CHANNELS]; |
| 130 | | devcb_resolved_write8 m_out_iow_func[I8257_NUM_CHANNELS]; |
| 155 | devcb2_write_line m_out_hrq_cb; |
| 156 | devcb2_write_line m_out_tc_cb; |
| 157 | devcb2_write_line m_out_mark_cb; |
| 131 | 158 | |
| 159 | /* accessors to main memory */ |
| 160 | devcb2_read8 m_in_memr_cb; |
| 161 | devcb2_write8 m_out_memw_cb; |
| 162 | |
| 163 | /* channel accesors */ |
| 164 | devcb2_read8 m_in_ior_0_cb; |
| 165 | devcb2_read8 m_in_ior_1_cb; |
| 166 | devcb2_read8 m_in_ior_2_cb; |
| 167 | devcb2_read8 m_in_ior_3_cb; |
| 168 | devcb2_write8 m_out_iow_0_cb; |
| 169 | devcb2_write8 m_out_iow_1_cb; |
| 170 | devcb2_write8 m_out_iow_2_cb; |
| 171 | devcb2_write8 m_out_iow_3_cb; |
| 172 | |
| 132 | 173 | emu_timer *m_timer; |
| 133 | 174 | emu_timer *m_msbflip_timer; |
| 134 | 175 | |
trunk/src/mess/drivers/unior.c
| r29554 | r29555 | |
| 393 | 393 | return m_p_vram[offset & 0x7ff]; |
| 394 | 394 | } |
| 395 | 395 | |
| 396 | | static I8257_INTERFACE( dma_intf ) |
| 397 | | { |
| 398 | | DEVCB_CPU_INPUT_LINE("maincpu", I8085_HALT), |
| 399 | | DEVCB_NULL, |
| 400 | | DEVCB_NULL, |
| 401 | | DEVCB_NULL, |
| 402 | | DEVCB_DEVICE_MEMBER("crtc", i8275_device, dack_w), |
| 403 | | { DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(unior_state, dma_r), DEVCB_NULL }, |
| 404 | | { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }, |
| 405 | | }; |
| 406 | | |
| 407 | 396 | WRITE8_MEMBER( unior_state::cpu_status_callback ) |
| 408 | 397 | { |
| 409 | 398 | m_dma->i8257_hlda_w(BIT(data, 3)); |
| r29554 | r29555 | |
| 462 | 451 | |
| 463 | 452 | MCFG_I8255_ADD( "ppi0", ppi0_intf ) |
| 464 | 453 | MCFG_I8255_ADD( "ppi1", ppi1_intf ) |
| 465 | | MCFG_I8257_ADD("dma", XTAL_20MHz / 9, dma_intf) // unknown clock |
| 454 | |
| 455 | MCFG_DEVICE_ADD("dma", I8257, XTAL_20MHz / 9) // unknown clock |
| 456 | MCFG_I8257_OUT_HRQ_CB(INPUTLINE("maincpu", I8085_HALT)) |
| 457 | MCFG_I8257_OUT_MEMW_CB(DEVWRITE8("crtc", i8275_device, dack_w)) |
| 458 | MCFG_I8257_IN_IOR_2_CB(READ8(unior_state, dma_r)) |
| 459 | |
| 466 | 460 | MCFG_I8275_ADD("crtc", crtc_intf) |
| 467 | 461 | MACHINE_CONFIG_END |
| 468 | 462 | |
trunk/src/mess/drivers/fanucspmg.c
| r29554 | r29555 | |
| 710 | 710 | return prog_space.write_byte(offset, data); |
| 711 | 711 | } |
| 712 | 712 | |
| 713 | | I8257_INTERFACE( fanucspmg_dma ) |
| 714 | | { |
| 715 | | DEVCB_NULL, |
| 716 | | DEVCB_NULL, |
| 717 | | DEVCB_NULL, |
| 718 | | DEVCB_DRIVER_MEMBER(fanucspmg_state, memory_read_byte), |
| 719 | | DEVCB_DRIVER_MEMBER(fanucspmg_state, memory_write_byte), |
| 720 | | { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }, |
| 721 | | { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL } |
| 722 | | }; |
| 723 | | |
| 724 | 713 | static MC6845_UPDATE_ROW( fanuc_update_row ) |
| 725 | 714 | { |
| 726 | 715 | fanucspmg_state *state = downcast<fanucspmg_state *>(device->owner()); |
| r29554 | r29555 | |
| 819 | 808 | MCFG_PIT8253_CLK1(XTAL_15MHz/12) |
| 820 | 809 | MCFG_PIT8253_CLK2(XTAL_15MHz/12) |
| 821 | 810 | |
| 822 | | MCFG_I8257_ADD(DMAC_TAG, XTAL_15MHz / 5, fanucspmg_dma) |
| 811 | MCFG_DEVICE_ADD(DMAC_TAG, I8257, XTAL_15MHz / 5) |
| 812 | MCFG_I8257_IN_MEMR_CB(READ8(fanucspmg_state, memory_read_byte)) |
| 813 | MCFG_I8257_OUT_MEMW_CB(WRITE8(fanucspmg_state, memory_write_byte)) |
| 823 | 814 | |
| 824 | 815 | MCFG_PIC8259_ADD(PIC0_TAG, INPUTLINE("maincpu", 0), VCC, NULL) |
| 825 | 816 | MCFG_PIC8259_ADD(PIC1_TAG, INPUTLINE("maincpu", 0), VCC, NULL) |
trunk/src/mess/drivers/pc8001.c
| r29554 | r29555 | |
| 444 | 444 | program.write_byte(offset, data); |
| 445 | 445 | } |
| 446 | 446 | |
| 447 | | static I8257_INTERFACE( dmac_intf ) |
| 448 | | { |
| 449 | | DEVCB_DRIVER_LINE_MEMBER(pc8001_state, hrq_w), |
| 450 | | DEVCB_NULL, |
| 451 | | DEVCB_NULL, |
| 452 | | DEVCB_NULL, |
| 453 | | DEVCB_DRIVER_MEMBER(pc8001_state, dma_mem_w), |
| 454 | | { DEVCB_DRIVER_MEMBER(pc8001_state, dma_io_r), DEVCB_DRIVER_MEMBER(pc8001_state, dma_io_r), DEVCB_DRIVER_MEMBER(pc8001_state, dma_io_r), DEVCB_DRIVER_MEMBER(pc8001_state, dma_io_r) }, |
| 455 | | { DEVCB_DRIVER_MEMBER(pc8001_state, dma_io_w), DEVCB_DRIVER_MEMBER(pc8001_state, dma_io_w), DEVCB_DRIVER_MEMBER(pc8001_state, dma_io_w), DEVCB_DRIVER_MEMBER(pc8001_state, dma_io_w) }, |
| 456 | | }; |
| 457 | 447 | |
| 458 | 448 | /* Machine Initialization */ |
| 459 | 449 | |
| r29554 | r29555 | |
| 545 | 535 | MCFG_DEVICE_ADD(I8251_TAG, I8251, 0) |
| 546 | 536 | |
| 547 | 537 | MCFG_I8255A_ADD(I8255A_TAG, ppi_intf) |
| 548 | | MCFG_I8257_ADD(I8257_TAG, 4000000, dmac_intf) |
| 538 | |
| 539 | MCFG_DEVICE_ADD(I8257_TAG, I8257, 4000000) |
| 540 | MCFG_I8257_OUT_HRQ_CB(WRITELINE(pc8001_state, hrq_w)) |
| 541 | MCFG_I8257_OUT_MEMW_CB(WRITE8(pc8001_state, dma_mem_w)) |
| 542 | MCFG_I8257_IN_IOR_0_CB(READ8(pc8001_state, dma_io_r)) |
| 543 | MCFG_I8257_IN_IOR_1_CB(READ8(pc8001_state, dma_io_r)) |
| 544 | MCFG_I8257_IN_IOR_2_CB(READ8(pc8001_state, dma_io_r)) |
| 545 | MCFG_I8257_IN_IOR_3_CB(READ8(pc8001_state, dma_io_r)) |
| 546 | MCFG_I8257_OUT_IOW_0_CB(WRITE8(pc8001_state, dma_io_w)) |
| 547 | MCFG_I8257_OUT_IOW_1_CB(WRITE8(pc8001_state, dma_io_w)) |
| 548 | MCFG_I8257_OUT_IOW_2_CB(WRITE8(pc8001_state, dma_io_w)) |
| 549 | MCFG_I8257_OUT_IOW_3_CB(WRITE8(pc8001_state, dma_io_w)) |
| 550 | |
| 549 | 551 | MCFG_UPD1990A_ADD(UPD1990A_TAG, XTAL_32_768kHz, NULL, NULL) |
| 550 | 552 | |
| 551 | 553 | MCFG_DEVICE_ADD(UPD3301_TAG, UPD3301, 14318180) |
| r29554 | r29555 | |
| 589 | 591 | MCFG_DEVICE_ADD(I8251_TAG, I8251, 0) |
| 590 | 592 | |
| 591 | 593 | MCFG_I8255A_ADD(I8255A_TAG, ppi_intf) |
| 592 | | MCFG_I8257_ADD(I8257_TAG, 4000000, dmac_intf) |
| 594 | |
| 595 | MCFG_DEVICE_ADD(I8257_TAG, I8257, 4000000) |
| 596 | MCFG_I8257_OUT_HRQ_CB(WRITELINE(pc8001_state, hrq_w)) |
| 597 | MCFG_I8257_OUT_MEMW_CB(WRITE8(pc8001_state, dma_mem_w)) |
| 598 | MCFG_I8257_IN_IOR_0_CB(READ8(pc8001_state, dma_io_r)) |
| 599 | MCFG_I8257_IN_IOR_1_CB(READ8(pc8001_state, dma_io_r)) |
| 600 | MCFG_I8257_IN_IOR_2_CB(READ8(pc8001_state, dma_io_r)) |
| 601 | MCFG_I8257_IN_IOR_3_CB(READ8(pc8001_state, dma_io_r)) |
| 602 | MCFG_I8257_OUT_IOW_0_CB(WRITE8(pc8001_state, dma_io_w)) |
| 603 | MCFG_I8257_OUT_IOW_1_CB(WRITE8(pc8001_state, dma_io_w)) |
| 604 | MCFG_I8257_OUT_IOW_2_CB(WRITE8(pc8001_state, dma_io_w)) |
| 605 | MCFG_I8257_OUT_IOW_3_CB(WRITE8(pc8001_state, dma_io_w)) |
| 606 | |
| 593 | 607 | MCFG_UPD1990A_ADD(UPD1990A_TAG, XTAL_32_768kHz, NULL, NULL) |
| 594 | 608 | |
| 595 | 609 | MCFG_DEVICE_ADD(UPD3301_TAG, UPD3301, 14318180) |
trunk/src/mame/drivers/dkong.c
| r29554 | r29555 | |
| 370 | 370 | DEVCB_NULL |
| 371 | 371 | }; |
| 372 | 372 | |
| 373 | | static I8257_INTERFACE( dk_dma ) |
| 374 | | { |
| 375 | | DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_HALT), |
| 376 | | DEVCB_NULL, |
| 377 | | DEVCB_NULL, |
| 378 | | DEVCB_DRIVER_MEMBER(dkong_state, memory_read_byte), |
| 379 | | DEVCB_DRIVER_MEMBER(dkong_state, memory_write_byte), |
| 380 | | { DEVCB_NULL, DEVCB_DRIVER_MEMBER(dkong_state,p8257_ctl_r), DEVCB_NULL, DEVCB_NULL }, |
| 381 | | { DEVCB_DRIVER_MEMBER(dkong_state,p8257_ctl_w), DEVCB_NULL, DEVCB_NULL, DEVCB_NULL } |
| 382 | | }; |
| 383 | | |
| 384 | | static I8257_INTERFACE( hb_dma ) |
| 385 | | { |
| 386 | | DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_HALT), |
| 387 | | DEVCB_NULL, |
| 388 | | DEVCB_NULL, |
| 389 | | DEVCB_DRIVER_MEMBER(dkong_state, hb_dma_read_byte), |
| 390 | | DEVCB_DRIVER_MEMBER(dkong_state, hb_dma_write_byte), |
| 391 | | { DEVCB_NULL, DEVCB_DRIVER_MEMBER(dkong_state,p8257_ctl_r), DEVCB_NULL, DEVCB_NULL }, |
| 392 | | { DEVCB_DRIVER_MEMBER(dkong_state,p8257_ctl_w), DEVCB_NULL, DEVCB_NULL, DEVCB_NULL } |
| 393 | | }; |
| 394 | | |
| 395 | 373 | /************************************* |
| 396 | 374 | * |
| 397 | 375 | * VBLANK and IRQ generation |
| r29554 | r29555 | |
| 1657 | 1635 | MCFG_MACHINE_START_OVERRIDE(dkong_state,dkong2b) |
| 1658 | 1636 | MCFG_MACHINE_RESET_OVERRIDE(dkong_state,dkong) |
| 1659 | 1637 | |
| 1660 | | MCFG_I8257_ADD("dma8257", CLOCK_1H, dk_dma) |
| 1638 | MCFG_DEVICE_ADD("dma8257", I8257, CLOCK_1H) |
| 1639 | MCFG_I8257_OUT_HRQ_CB(INPUTLINE("maincpu", INPUT_LINE_HALT)) |
| 1640 | MCFG_I8257_IN_MEMR_CB(READ8(dkong_state, memory_read_byte)) |
| 1641 | MCFG_I8257_OUT_MEMW_CB(WRITE8(dkong_state, memory_write_byte)) |
| 1642 | MCFG_I8257_IN_IOR_1_CB(READ8(dkong_state, p8257_ctl_r)) |
| 1643 | MCFG_I8257_OUT_IOW_0_CB(WRITE8(dkong_state, p8257_ctl_w)) |
| 1661 | 1644 | |
| 1662 | 1645 | /* video hardware */ |
| 1663 | 1646 | MCFG_SCREEN_ADD("screen", RASTER) |
| r29554 | r29555 | |
| 1784 | 1767 | MCFG_CPU_VBLANK_INT_DRIVER("screen", dkong_state, s2650_interrupt) |
| 1785 | 1768 | |
| 1786 | 1769 | MCFG_DEVICE_MODIFY("dma8257") |
| 1787 | | MCFG_DEVICE_CONFIG(hb_dma) |
| 1770 | MCFG_I8257_IN_MEMR_CB(READ8(dkong_state, hb_dma_read_byte)) |
| 1771 | MCFG_I8257_OUT_MEMW_CB(WRITE8(dkong_state, hb_dma_write_byte)) |
| 1788 | 1772 | |
| 1789 | 1773 | MCFG_MACHINE_START_OVERRIDE(dkong_state,s2650) |
| 1790 | 1774 | MACHINE_CONFIG_END |