Previous

199869 Revisions

Next

r29506 Wednesday 9th April, 2014 at 23:31:21 UTC by Nathan Woods
Merge branch 'master' of ssh://mess.org/mame into new_menus

[/branches/new_menus/hlsl]	bloom.fx
[/branches/new_menus/src/emu]	addrmap.c addrmap.h device.h diexec.c digfx.h dimemory.c memory.c sound.c sound.h tilemap.h
[/branches/new_menus/src/emu/bus/isa]	p1_hdc.c wdxt_gen.c
[/branches/new_menus/src/emu/bus/nes]	ggenie.c nes_slot.h
[/branches/new_menus/src/emu/bus/pce]	pce_slot.c pce_slot.h
[/branches/new_menus/src/emu/bus/sega8]	rom.c sega8_slot.c sega8_slot.h
[/branches/new_menus/src/emu/bus/snes]	sa1.c snes_slot.c snes_slot.h
[/branches/new_menus/src/emu/bus/x68k]	x68k_scsiext.c
[/branches/new_menus/src/emu/cpu/tms57002]	tms57002.c tms57002.h
[/branches/new_menus/src/emu/cpu/tms7000]	tms7000.c tms7000.h tms70op.inc
[/branches/new_menus/src/emu/debug]	debugcmd.c
[/branches/new_menus/src/emu/machine]	aakart.c aakart.h hd63450.c hd63450.h i8279.c i8279.h mb89352.c mb89352.h ncr539x.c ncr539x.h roc10937.c roc10937.h wd2010.c wd2010.h
[/branches/new_menus/src/emu/video]	crt9007.c
[/branches/new_menus/src/mame/audio]	namco52.c namco54.c taitosnd.c taitosnd.h
[/branches/new_menus/src/mame/drivers]	airbustr.c asuka.c backfire.c bfmsys85.c bishi.c boogwing.c cave.c cbuster.c cham24.c cninja.c crospang.c crshrace.c crystal.c darius.c darkseal.c dassault.c dblewing.c dbz.c deco156.c deco32.c dietgo.c djboy.c dreambal.c esd16.c exzisus.c f1gp.c famibox.c funkyjet.c galastrm.c galpanic.c globalfr.c gotcha.c groundfx.c gunbustr.c hvyunit.c icecold.c igspoker.c jpmimpct.c jpmsys5.c konamigx.c lemmings.c maygay1b.c maygay1bsw.c maygayv1.c metro.c mirage.c mlanding.c moo.c mpu3.c mpu4hw.c mpu4sw.c multigam.c namcona1.c namcos2.c ninjaw.c nmg5.c nmk16.c opwolf.c othunder.c pktgaldx.c playch10.c plygonet.c powerins.c proconn.c quizpani.c rainbow.c rastan.c rohga.c rungun.c sandscrp.c silvmil.c simpl156.c skylncr.c slapshot.c snowbros.c sshangha.c supbtime.c superchs.c suprslam.c taito_b.c taito_f2.c taito_h.c taito_l.c taito_o.c taito_x.c taito_z.c taitoair.c tceptor.c tmnt.c toaplan2.c topspeed.c tumbleb.c tumblep.c turbo.c undrfire.c vaportra.c volfied.c vsnes.c warriorb.c wgp.c xexex.c zn.c
[/branches/new_menus/src/mame/includes]	boogwing.h cbuster.h cninja.h dassault.h deco32.h dietgo.h esd16.h jpmimpct.h jpmsys5.h maygay1b.h namcona1.h pktgaldx.h playch10.h rohga.h simpl156.h sshangha.h taito_z.h vaportra.h vsnes.h
[/branches/new_menus/src/mame/machine]	archimds.c namco51.c namco51.h nmk112.c nmk112.h playch10.c vsnes.c
[/branches/new_menus/src/mame/video]	c45.c c45.h deco16ic.h decospr.c decospr.h k053936.c k053936.h k054338.c k054338.h kan_pand.c kan_pand.h namcona1.c pc080sn.c pc080sn.h pc090oj.c pc090oj.h playch10.c ppu2c0x.c ppu2c0x.h rohga.c tc0080vco.c tc0080vco.h tc0100scn.c tc0100scn.h tc0150rod.c tc0150rod.h tc0180vcu.c tc0180vcu.h tc0280grd.c tc0280grd.h tc0480scp.c tc0480scp.h toaplan_scu.c toaplan_scu.h tumbleb.c vrender0.c vrender0.h vsnes.c
[/branches/new_menus/src/mess/drivers]	a310.c cat.c digel804.c mac.c megadriv.c mmd1.c nes.c pdp1.c rainbow.c sdk85.c sdk86.c selz80.c sms.c tandy2k.c tx0.c vt100.c x68k.c z88.c
[/branches/new_menus/src/mess/includes]	sms.h tandy2k.h x68k.h z88.h
[/branches/new_menus/src/mess/machine]	megacd.c megacd.h sms.c upd65031.c upd65031.h
[/branches/new_menus/src/mess/video]	crt.c crt.h vtvideo.c vtvideo.h z88.c
[/branches/new_menus/src/osd/windows]	d3dhlsl.c d3dhlsl.h

branches/new_menus/hlsl/bloom.fx

r29505	r29506
143	143	{
144	144	float4 Position : POSITION;
145	145	float4 Color : COLOR0;
146		float2 TexCoord : TEXCOORD0;
	146	float4 TexCoord01 : TEXCOORD0;
	147	float4 TexCoord23 : TEXCOORD1;
	148	float4 TexCoord45 : TEXCOORD2;
	149	float4 TexCoord67 : TEXCOORD3;
	150	float4 TexCoord89 : TEXCOORD4;
	151	float2 TexCoordA : TEXCOORD5;
147	152	};
148	153
149	154	struct VS_INPUT
r29505	r29506
157	162	struct PS_INPUT
158	163	{
159	164	float4 Color : COLOR0;
160		float2 TexCoord : TEXCOORD0;
	165	float4 TexCoord01 : TEXCOORD0;
	166	float4 TexCoord23 : TEXCOORD1;
	167	float4 TexCoord45 : TEXCOORD2;
	168	float4 TexCoord67 : TEXCOORD3;
	169	float4 TexCoord89 : TEXCOORD4;
	170	float2 TexCoordA : TEXCOORD5;
161	171	};
162	172
163	173	//-----------------------------------------------------------------------------
r29505	r29506
165	175	//-----------------------------------------------------------------------------
166	176
167	177	uniform float2 TargetSize;
	178	uniform float4 Level01Size;
	179	uniform float4 Level23Size;
	180	uniform float4 Level45Size;
	181	uniform float4 Level67Size;
	182	uniform float4 Level89Size;
	183	uniform float2 LevelASize;
168	184
169	185	VS_OUTPUT vs_main(VS_INPUT Input)
170	186	{
r29505	r29506
176	192	Output.Position.xy -= float2(0.5f, 0.5f);
177	193	Output.Position.xy *= float2(2.0f, 2.0f);
178	194	Output.Color = Input.Color;
179		Output.TexCoord = (Input.Position.xy  + 0.5f) / TargetSize;
	195	Output.TexCoord01 = Input.Position.xyxy / TargetSize.xyxy - 0.5f / Level01Size;
	196	Output.TexCoord23 = Input.Position.xyxy / TargetSize.xyxy - 0.5f / Level23Size;
	197	Output.TexCoord45 = Input.Position.xyxy / TargetSize.xyxy - 0.5f / Level45Size;
	198	Output.TexCoord67 = Input.Position.xyxy / TargetSize.xyxy - 0.5f / Level67Size;
	199	Output.TexCoord89 = Input.Position.xyxy / TargetSize.xyxy - 0.5f / Level89Size;
	200	Output.TexCoordA = Input.Position.xy / TargetSize - 0.5f / LevelASize;
180	201
181	202	return Output;
182	203	}
r29505	r29506
191	212
192	213	float4 ps_main(PS_INPUT Input) : COLOR
193	214	{
194		float3 texel0 = tex2D(DiffuseSampler0, Input.TexCoord).rgb;
195		float3 texel1 = tex2D(DiffuseSampler1, Input.TexCoord).rgb;
196		float3 texel2 = tex2D(DiffuseSampler2, Input.TexCoord).rgb;
197		float3 texel3 = tex2D(DiffuseSampler3, Input.TexCoord).rgb;
198		float3 texel4 = tex2D(DiffuseSampler4, Input.TexCoord).rgb;
199		float3 texel5 = tex2D(DiffuseSampler5, Input.TexCoord).rgb;
200		float3 texel6 = tex2D(DiffuseSampler6, Input.TexCoord).rgb;
201		float3 texel7 = tex2D(DiffuseSampler7, Input.TexCoord).rgb;
202		float3 texel8 = tex2D(DiffuseSampler8, Input.TexCoord).rgb;
203		float3 texel9 = tex2D(DiffuseSampler9, Input.TexCoord).rgb;
204		float3 texelA = tex2D(DiffuseSamplerA, Input.TexCoord).rgb;
	215	float3 texel0 = tex2D(DiffuseSampler0, Input.TexCoord01.xy).rgb;
	216	float3 texel1 = tex2D(DiffuseSampler1, Input.TexCoord01.zw).rgb;
	217	float3 texel2 = tex2D(DiffuseSampler2, Input.TexCoord23.xy).rgb;
	218	float3 texel3 = tex2D(DiffuseSampler3, Input.TexCoord23.zw).rgb;
	219	float3 texel4 = tex2D(DiffuseSampler4, Input.TexCoord45.xy).rgb;
	220	float3 texel5 = tex2D(DiffuseSampler5, Input.TexCoord45.zw).rgb;
	221	float3 texel6 = tex2D(DiffuseSampler6, Input.TexCoord67.xy).rgb;
	222	float3 texel7 = tex2D(DiffuseSampler7, Input.TexCoord67.zw).rgb;
	223	float3 texel8 = tex2D(DiffuseSampler8, Input.TexCoord89.xy).rgb;
	224	float3 texel9 = tex2D(DiffuseSampler9, Input.TexCoord89.zw).rgb;
	225	float3 texelA = tex2D(DiffuseSamplerA, Input.TexCoordA).rgb;
205	226
206	227	texel0 = texel0 * Level0123Weight.x;
207	228	texel1 = texel1 * Level0123Weight.y;

branches/new_menus/src/mame/includes/esd16.h

r29505	r29506
69	69	virtual void machine_reset();
70	70	virtual void video_start();
71	71	UINT32 screen_update_hedpanic(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
72		static UINT16 hedpanic_pri_callback(UINT16 x);
	72	DECOSPR_PRIORITY_CB_MEMBER(hedpanic_pri_callback);
	73
73	74	required_device<cpu_device> m_maincpu;
74	75	required_device<cpu_device> m_audiocpu;
75	76	required_device<gfxdecode_device> m_gfxdecode;

branches/new_menus/src/mame/includes/maygay1b.h

r29505	r29506
8	8	#define M1_DUART_CLOCK  (XTAL_3_6864MHz)
9	9
10	10	#include "cpu/m6809/m6809.h"
	11	#include "machine/i8279.h"
	12
11	13	#include "video/awpvid.h"       //Fruit Machines Only
12	14	#include "machine/6821pia.h"
13	15	#include "machine/mc68681.h"
r29505	r29506
19	21	#include "sound/okim6376.h"
20	22	#include "machine/nvram.h"
21	23
22		struct i8279_state
23		{
24		UINT8       command;
25		UINT8       mode;
26		UINT8       prescale;
27		UINT8       inhibit;
28		UINT8       clear;
29		UINT8       ram[16];
30		UINT8       read_sensor;
31		UINT8       write_display;
32		UINT8       sense_address;
33		UINT8       sense_auto_inc;
34		UINT8       disp_address;
35		UINT8       disp_auto_inc;
36		};
37
38
39	24	class maygay1b_state : public driver_device
40	25	{
41	26	public:
r29505	r29506
43	28	: driver_device(mconfig, type, tag),
44	29	m_maincpu(*this, "maincpu"),
45	30	m_vfd(*this, "vfd"),
	31	m_ay(*this, "aysnd"),
46	32	m_msm6376(*this, "msm6376"),
47		m_duart68681(*this, "duart68681") {
48		m_NMIENABLE = 0;
49		}
	33	m_duart68681(*this, "duart68681"),
	34	m_sw1_port(*this, "SW1"),
	35	m_sw2_port(*this, "SW2"),
	36	m_s2_port(*this, "STROBE2"),
	37	m_s3_port(*this, "STROBE3"),
	38	m_s4_port(*this, "STROBE4"),
	39	m_s5_port(*this, "STROBE5"),
	40	m_s6_port(*this, "STROBE6"),
	41	m_s7_port(*this, "STROBE7")
	42	{}
50	43
51	44	required_device<cpu_device> m_maincpu;
52		optional_device<roc10937_t> m_vfd;
	45	optional_device<s16lf01_t> m_vfd;
	46	required_device<ay8910_device> m_ay;
53	47	optional_device<okim6376_device> m_msm6376;
54	48	required_device<mc68681_device> m_duart68681;
	49	required_ioport m_sw1_port;
	50	required_ioport m_sw2_port;
	51	required_ioport m_s2_port;
	52	required_ioport m_s3_port;
	53	required_ioport m_s4_port;
	54	required_ioport m_s5_port;
	55	required_ioport m_s6_port;
	56	required_ioport m_s7_port;
55	57
56	58	UINT8 m_lamppos;
	59	int m_lamp_strobe;
	60	int m_old_lamp_strobe;
	61	int m_lamp_strobe2;
	62	int m_old_lamp_strobe2;
57	63	int m_alpha_clock;
58	64	int m_RAMEN;
59	65	int m_ALARMEN;
r29505	r29506
65	71	TIMER_DEVICE_CALLBACK_MEMBER( maygay1b_nmitimer_callback );
66	72	UINT8 m_Lamps[256];
67	73	int m_optic_pattern;
68		i8279_state m_i8279[2];
69		DECLARE_READ8_MEMBER(m1_8279_r);
70		DECLARE_WRITE8_MEMBER(m1_8279_w);
71		DECLARE_READ8_MEMBER(m1_8279_2_r);
72		DECLARE_WRITE8_MEMBER(m1_8279_2_w);
	74	DECLARE_WRITE8_MEMBER(scanlines_w);
	75	DECLARE_WRITE8_MEMBER(lamp_data_w);
	76	DECLARE_WRITE8_MEMBER(lamp_data_2_w);
	77	DECLARE_READ8_MEMBER(kbd_r);
73	78	DECLARE_WRITE8_MEMBER(reel12_w);
74	79	DECLARE_WRITE8_MEMBER(reel34_w);
75	80	DECLARE_WRITE8_MEMBER(reel56_w);
r29505	r29506
78	83	DECLARE_READ8_MEMBER(latch_st_hi);
79	84	DECLARE_READ8_MEMBER(latch_st_lo);
80	85	DECLARE_WRITE8_MEMBER(m1ab_no_oki_w);
81		void m1_draw_lamps(int data,int strobe, int col);
82	86	DECLARE_WRITE8_MEMBER(m1_pia_porta_w);
83	87	DECLARE_WRITE8_MEMBER(m1_pia_portb_w);
	88	DECLARE_WRITE8_MEMBER(m1_lockout_w);
84	89	DECLARE_WRITE8_MEMBER(m1_meter_w);
85	90	DECLARE_READ8_MEMBER(m1_meter_r);
	91	DECLARE_READ8_MEMBER(m1_firq_clr_r);
86	92	DECLARE_READ8_MEMBER(m1_firq_trg_r);
87	93	DECLARE_WRITE_LINE_MEMBER(duart_irq_handler);
88	94	DECLARE_READ8_MEMBER(m1_duart_r);
89	95	DECLARE_DRIVER_INIT(m1);
90	96	virtual void machine_start();
91	97	virtual void machine_reset();
92		void update_outputs(i8279_state *chip, UINT16 which);
93	98	void m1_stepper_reset();
94	99	};

branches/new_menus/src/mame/includes/simpl156.h

r29505	r29506
38	38	required_device<palette_device> m_palette;
39	39	UINT16 *m_spriteram;
40	40	size_t m_spriteram_size;
41		int bank_callback(int bank);
	41	DECO16IC_BANK_CB_MEMBER(bank_callback);
	42	DECOSPR_PRIORITY_CB_MEMBER(pri_callback);
42	43
43	44	DECLARE_READ32_MEMBER(simpl156_inputs_read);
44	45	DECLARE_READ32_MEMBER(simpl156_palette_r);

branches/new_menus/src/mame/includes/cninja.h

r29505	r29506
92	92	TIMER_DEVICE_CALLBACK_MEMBER(interrupt_gen);
93	93	void cninjabl_draw_sprites( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect );
94	94
95		int cninja_bank_callback(int bank);
96		int robocop2_bank_callback(int bank);
97		int mutantf_1_bank_callback(int bank);
98		int mutantf_2_bank_callback(int bank);
	95	DECO16IC_BANK_CB_MEMBER(cninja_bank_callback);
	96	DECO16IC_BANK_CB_MEMBER(robocop2_bank_callback);
	97	DECO16IC_BANK_CB_MEMBER(mutantf_1_bank_callback);
	98	DECO16IC_BANK_CB_MEMBER(mutantf_2_bank_callback);
99	99
	100	DECOSPR_PRIORITY_CB_MEMBER(pri_callback);
	101
100	102	DECLARE_READ16_MEMBER( sshangha_protection_region_6_146_r );
101	103	DECLARE_WRITE16_MEMBER( sshangha_protection_region_6_146_w );
102	104	DECLARE_READ16_MEMBER( sshangha_protection_region_8_146_r );

branches/new_menus/src/mame/includes/dietgo.h

r29505	r29506
41	41	DECLARE_DRIVER_INIT(dietgo);
42	42	virtual void machine_start();
43	43	UINT32 screen_update_dietgo(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
44		int bank_callback(int bank);
	44	DECO16IC_BANK_CB_MEMBER(bank_callback);
45	45
46	46	DECLARE_READ16_MEMBER( dietgo_protection_region_0_104_r );
47	47	DECLARE_WRITE16_MEMBER( dietgo_protection_region_0_104_w );

branches/new_menus/src/mame/includes/jpmsys5.h

r29505	r29506
33	33	required_device<acia6850_device> m_acia6850_2;
34	34	required_device<upd7759_device> m_upd7759;
35	35	optional_device<tms34061_device> m_tms34061;
36		optional_device<roc10937_t> m_vfd;
	36	optional_device<s16lf01_t> m_vfd;
37	37	required_ioport m_direct_port;
38	38	optional_device<palette_device> m_palette;
39	39

branches/new_menus/src/mame/includes/namcona1.h

r29505	r29506
22	22	NAMCO_XDAY2
23	23	};
24	24
25		#define NAMCONA1_NUM_TILEMAPS 4
26	25
27
28	26	class namcona1_state : public driver_device
29	27	{
30	28	public:
r29505	r29506
37	35	m_screen(*this, "screen"),
38	36	m_palette(*this, "palette"),
39	37	m_c140(*this, "c140"),
40		m_videoram(*this,"videoram"),
41		m_spriteram(*this,"spriteram"),
42	38	m_workram(*this,"workram"),
43	39	m_vreg(*this,"vreg"),
44		m_scroll(*this,"scroll")
	40	m_paletteram(*this, "paletteram"),
	41	m_cgram(*this, "cgram"),
	42	m_videoram(*this,"videoram"),
	43	m_scroll(*this,"scroll"),
	44	m_spriteram(*this,"spriteram")
45	45	{ }
46	46
47	47	required_device<cpu_device> m_maincpu;
r29505	r29506
51	51	required_device<screen_device> m_screen;
52	52	required_device<palette_device> m_palette;
53	53	required_device<c140_device> m_c140;
54		required_shared_ptr<UINT16> m_videoram;
55		required_shared_ptr<UINT16> m_spriteram;
56	54	required_shared_ptr<UINT16> m_workram;
57	55	required_shared_ptr<UINT16> m_vreg;
	56	required_shared_ptr<UINT16> m_paletteram;
	57	required_shared_ptr<UINT16> m_cgram;
	58	required_shared_ptr<UINT16> m_videoram;
58	59	required_shared_ptr<UINT16> m_scroll;
	60	required_shared_ptr<UINT16> m_spriteram;
59	61
	62	// this has to be UINT8 to be in the right byte order for the tilemap system
	63	dynamic_array<UINT8> m_shaperam;
	64
60	65	UINT16 *m_mpBank0;
61	66	UINT16 *m_mpBank1;
62	67	int m_mEnableInterrupts;
r29505	r29506
68	73	UINT8 m_mcu_port5;
69	74	UINT8 m_mcu_port6;
70	75	UINT8 m_mcu_port8;
71		UINT16 *m_shaperam;
72		UINT16 *m_cgram;
73		tilemap_t *m_roz_tilemap;
74		int m_roz_palette;
75		tilemap_t *m_bg_tilemap[NAMCONA1_NUM_TILEMAPS];
76		int m_tilemap_palette_bank[NAMCONA1_NUM_TILEMAPS];
	76	tilemap_t *m_bg_tilemap[4+1];
77	77	int m_palette_is_dirty;
78		UINT8 m_mask_data[8];
79		UINT8 m_conv_data[9];
80	78
81	79
82	80	DECLARE_READ16_MEMBER(custom_key_r);
83	81	DECLARE_WRITE16_MEMBER(custom_key_w);
84		DECLARE_READ16_MEMBER(namcona1_vreg_r);
85	82	DECLARE_WRITE16_MEMBER(namcona1_vreg_w);
86	83	DECLARE_READ16_MEMBER(mcu_mailbox_r);
87	84	DECLARE_WRITE16_MEMBER(mcu_mailbox_w_68k);
r29505	r29506
106	103	void init_namcona1(int gametype);
107	104	void UpdatePalette(int offset);
108	105	DECLARE_WRITE16_MEMBER(namcona1_videoram_w);
109		DECLARE_READ16_MEMBER(namcona1_videoram_r);
110		DECLARE_READ16_MEMBER(namcona1_paletteram_r);
111	106	DECLARE_WRITE16_MEMBER(namcona1_paletteram_w);
112	107	DECLARE_READ16_MEMBER(namcona1_gfxram_r);
113	108	DECLARE_WRITE16_MEMBER(namcona1_gfxram_w);
r29505	r29506
142	137	TIMER_DEVICE_CALLBACK_MEMBER(mcu_interrupt);
143	138
144	139	private:
145		void tilemap_get_info(tile_data &tileinfo, int tile_index, const UINT16 *tilemap_videoram, int tilemap_color, bool use_4bpp_gfx);
	140	void tilemap_get_info(tile_data &tileinfo, int tile_index, const UINT16 *tilemap_videoram, bool use_4bpp_gfx);
146	141	};

branches/new_menus/src/mame/includes/rohga.h

r29505	r29506
69	69	DECLARE_DRIVER_INIT(nitrobal);
70	70	DECLARE_DRIVER_INIT(schmeisr);
71	71	DECLARE_DRIVER_INIT(rohga);
72		DECLARE_VIDEO_START(rohga);
73	72	DECLARE_VIDEO_START(wizdfire);
74		DECLARE_VIDEO_START(schmeisr);
75	73	UINT32 screen_update_rohga(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
76	74	UINT32 screen_update_wizdfire(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
77	75	UINT32 screen_update_nitrobal(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
78	76	void mixwizdfirelayer(bitmap_rgb32 &bitmap, const rectangle &cliprect, int gfxregion, UINT16 pri, UINT16 primask);
79		int bank_callback(int bank);
	77	DECO16IC_BANK_CB_MEMBER(bank_callback);
	78	DECOSPR_PRIORITY_CB_MEMBER(rohga_pri_callback);
	79	DECOSPR_COLOUR_CB_MEMBER(rohga_col_callback);
	80	DECOSPR_COLOUR_CB_MEMBER(schmeisr_col_callback);
80	81
81	82	READ16_MEMBER( nb_protection_region_0_146_r );
82	83	WRITE16_MEMBER( nb_protection_region_0_146_w );
83	84	READ16_MEMBER( wf_protection_region_0_104_r );
84	85	WRITE16_MEMBER( wf_protection_region_0_104_w );
85	86	};
86		/*----------- defined in video/rohga.c -----------*/
87		UINT16 rohga_pri_callback(UINT16 x);
88		UINT16 schmeisr_col_callback(UINT16 x);
89		UINT16 rohga_col_callback(UINT16 x);

branches/new_menus/src/mame/includes/vaportra.h

r29505	r29506
50	50	virtual void machine_reset();
51	51	UINT32 screen_update_vaportra(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
52	52	void update_24bitcol( int offset );
53		int bank_callback(int bank);
	53	DECO16IC_BANK_CB_MEMBER(bank_callback);
54	54	};

branches/new_menus/src/mame/includes/vsnes.h

r29505	r29506
128	128
129	129	DECLARE_READ8_MEMBER( vsnes_bootleg_z80_latch_r );
130	130	};
131
132		/*----------- defined in video/vsnes.c -----------*/
133		extern const ppu2c0x_interface vsnes_ppu_interface_1;
134		extern const ppu2c0x_interface vsnes_ppu_interface_2;

branches/new_menus/src/mame/includes/sshangha.h

r29505	r29506
45	45	optional_device<decospr_device> m_sprgen2;
46	46
47	47	int m_video_control;
48		int bank_callback(int bank);
	48	DECO16IC_BANK_CB_MEMBER(bank_callback);
49	49
50	50	DECLARE_READ16_MEMBER( sshangha_protection_region_8_146_r );
51	51	DECLARE_WRITE16_MEMBER( sshangha_protection_region_8_146_w );

branches/new_menus/src/mame/includes/jpmimpct.h

r29505	r29506
78	78	int m_slidesout;
79	79	int m_hopper[3];
80	80	int m_motor[3];
81		optional_device<roc10937_t> m_vfd;
	81	optional_device<s16lf01_t> m_vfd;
82	82	optional_shared_ptr<UINT16> m_vram;
83	83	struct bt477_t m_bt477;
84	84	DECLARE_READ16_MEMBER(duart_1_r);

branches/new_menus/src/mame/includes/deco32.h

r29505	r29506
168	168	UINT16 port_b_tattass(int unused);
169	169	void tattass_sound_cb( address_space &space, UINT16 data, UINT16 mem_mask );
170	170
171		int fghthist_bank_callback( int bank );
172		int captaven_bank_callback( int bank );
173		int tattass_bank_callback( int bank );
	171	DECO16IC_BANK_CB_MEMBER(fghthist_bank_callback);
	172	DECO16IC_BANK_CB_MEMBER(captaven_bank_callback);
	173	DECO16IC_BANK_CB_MEMBER(tattass_bank_callback);
	174	DECOSPR_PRIORITY_CB_MEMBER(captaven_pri_callback);
174	175	};
175	176
176	177	class dragngun_state : public deco32_state
r29505	r29506
206	207	void dragngun_draw_sprites( bitmap_rgb32 &bitmap, const rectangle &cliprect, const UINT32 *spritedata);
207	208	READ32_MEMBER( dragngun_unk_video_r );
208	209
209		int bank_1_callback( int bank );
210		int bank_2_callback( int bank );
	210	DECO16IC_BANK_CB_MEMBER(bank_1_callback);
	211	DECO16IC_BANK_CB_MEMBER(bank_2_callback);
211	212	};

branches/new_menus/src/mame/includes/dassault.h

r29505	r29506
70	70	virtual void video_start();
71	71	UINT32 screen_update_dassault(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
72	72	void mixdassaultlayer(bitmap_rgb32 &bitmap, bitmap_ind16* sprite_bitmap, const rectangle &cliprect, UINT16 pri, UINT16 primask, UINT16 penbase, UINT8 alpha);
73		int dassault_bank_callback( const int bank );
	73	DECO16IC_BANK_CB_MEMBER(bank_callback);
74	74	};

branches/new_menus/src/mame/includes/cbuster.h

r29505	r29506
57	57	virtual void video_start();
58	58	UINT32 screen_update_twocrude(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
59	59	void update_24bitcol( int offset );
60		int bank_callback(int bank);
	60	DECO16IC_BANK_CB_MEMBER(bank_callback);
61	61	};

branches/new_menus/src/mame/includes/playch10.h

r29505	r29506
142	142	void ppu_irq(int *ppu_regs);
143	143	void mapper9_latch(offs_t offset);
144	144	};
145
146		/*----------- defined in video/playch10.c -----------*/
147		extern const ppu2c0x_interface playch10_ppu_interface;

branches/new_menus/src/mame/includes/boogwing.h

r29505	r29506
64	64	DECLARE_READ16_MEMBER( boogwing_protection_region_0_104_r );
65	65	DECLARE_WRITE16_MEMBER( boogwing_protection_region_0_104_w );
66	66
67		int bank_callback(int bank);
68		int bank_callback2(int bank);
	67	DECO16IC_BANK_CB_MEMBER(bank_callback);
	68	DECO16IC_BANK_CB_MEMBER(bank_callback2);
69	69	};

branches/new_menus/src/mame/includes/pktgaldx.h

r29505	r29506
59	59	READ16_MEMBER( pktgaldx_protection_region_f_104_r );
60	60	WRITE16_MEMBER( pktgaldx_protection_region_f_104_w );
61	61
62		int bank_callback(int bank);
	62	DECO16IC_BANK_CB_MEMBER(bank_callback);
63	63	};

branches/new_menus/src/mame/includes/taito_z.h

r29505	r29506
65	65	optional_device<tc0110pcr_device> m_tc0110pcr;
66	66	optional_device<tc0220ioc_device> m_tc0220ioc;
67	67	optional_device<tc0510nio_device> m_tc0510nio;
68		required_device<tc0140syt_device> m_tc0140syt;
	68	optional_device<tc0140syt_device> m_tc0140syt;   // bshark & spacegun miss the CPUs which shall use TC0140
69	69	required_device<gfxdecode_device> m_gfxdecode;
70	70	required_device<palette_device> m_palette;
71	71

branches/new_menus/src/mame/video/kan_pand.c

r29505	r29506
55	55	kaneko_pandora_device::kaneko_pandora_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
56	56	: device_t(mconfig, KANEKO_PANDORA, "Kaneko Pandora - PX79C480FP-3", tag, owner, clock, "kaneko_pandora", __FILE__),
57	57	device_video_interface(mconfig, *this),
	58	m_gfx_region(0),
	59	m_xoffset(0),
	60	m_yoffset(0),
58	61	m_gfxdecode(*this),
59	62	m_palette(*this)
60	63	{
r29505	r29506
81	84	}
82	85
83	86	//-------------------------------------------------
84		//  device_config_complete - perform any
85		//  operations now that the configuration is
86		//  complete
87		//-------------------------------------------------
88
89		void kaneko_pandora_device::device_config_complete()
90		{
91		// inherit a copy of the static data
92		const kaneko_pandora_interface *intf = reinterpret_cast<const kaneko_pandora_interface *>(static_config());
93		if (intf != NULL)
94		*static_cast<kaneko_pandora_interface *>(this) = *intf;
95
96		// or initialize to defaults if none provided
97		else
98		{
99		m_gfx_region = 0;
100		m_xoffset = 0;
101		m_yoffset = 0;
102		}
103		}
104
105		//-------------------------------------------------
106	87	//  device_start - device-specific startup
107	88	//-------------------------------------------------
108	89

branches/new_menus/src/mame/video/kan_pand.h

r29505	r29506
13	13	TYPE DEFINITIONS
14	14	***************************************************************************/
15	15
16		struct kaneko_pandora_interface
17		{
18		UINT8      m_gfx_region;
19		int        m_xoffset;
20		int        m_yoffset;
21		};
22
23	16	class kaneko_pandora_device : public device_t,
24		public device_video_interface,
25		public kaneko_pandora_interface
	17	public device_video_interface
26	18	{
27	19	public:
28	20	kaneko_pandora_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
r29505	r29506
31	23	// static configuration
32	24	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
33	25	static void static_set_palette_tag(device_t &device, const char *tag);
34
	26	static void set_gfx_region(device_t &device, int gfxregion) { downcast<kaneko_pandora_device &>(device).m_gfx_region = gfxregion; }
	27	static void set_offsets(device_t &device, int x_offset, int y_offset)
	28	{
	29	kaneko_pandora_device &dev = downcast<kaneko_pandora_device &>(device);
	30	dev.m_xoffset = x_offset;
	31	dev.m_yoffset = y_offset;
	32	}
	33
35	34	DECLARE_WRITE8_MEMBER ( spriteram_w );
36	35	DECLARE_READ8_MEMBER( spriteram_r );
37	36	DECLARE_WRITE16_MEMBER( spriteram_LSB_w );
r29505	r29506
43	42
44	43	protected:
45	44	// device-level overrides
46		virtual void device_config_complete();
47	45	virtual void device_start();
48	46	virtual void device_reset();
49	47
r29505	r29506
55	53	bitmap_ind16    *m_sprites_bitmap; /* bitmap to render sprites to, Pandora seems to be frame'buffered' */
56	54	int             m_clear_bitmap;
57	55	int             m_bg_pen; // might work some other way..
	56	UINT8           m_gfx_region;
	57	int             m_xoffset;
	58	int             m_yoffset;
58	59	required_device<gfxdecode_device> m_gfxdecode;
59	60	required_device<palette_device> m_palette;
60	61	};
r29505	r29506
66	67	DEVICE CONFIGURATION MACROS
67	68	***************************************************************************/
68	69
69		#define MCFG_KANEKO_PANDORA_ADD(_tag, _interface) \
70		MCFG_DEVICE_ADD(_tag, KANEKO_PANDORA, 0) \
71		MCFG_DEVICE_CONFIG(_interface)
	70	#define MCFG_KANEKO_PANDORA_GFX_REGION(_region) \
	71	kaneko_pandora_device::set_gfx_region(*device, _region);
72	72
	73	#define MCFG_KANEKO_PANDORA_OFFSETS(_xoffs, _yoffs) \
	74	kaneko_pandora_device::set_offsets(*device, _xoffs, _yoffs);
	75
73	76	#define MCFG_KANEKO_PANDORA_GFXDECODE(_gfxtag) \
74	77	kaneko_pandora_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
75	78

branches/new_menus/src/mame/video/pc090oj.c

r29505	r29506
71	71	*****************************************************************************/
72	72
73	73
74
75	74	const device_type PC090OJ = &device_creator<pc090oj_device>;
76	75
77	76	pc090oj_device::pc090oj_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
r29505	r29506
80	79	m_sprite_ctrl(0),
81	80	m_ram(NULL),
82	81	m_ram_buffered(0),
	82	m_gfxnum(0),
	83	m_x_offset(0),
	84	m_y_offset(0),
	85	m_use_buffer(0),
83	86	m_gfxdecode(*this),
84	87	m_palette(*this)
85	88	{
r29505	r29506
106	109	}
107	110
108	111	//-------------------------------------------------
109		//  device_config_complete - perform any
110		//  operations now that the configuration is
111		//  complete
112		//-------------------------------------------------
113
114		void pc090oj_device::device_config_complete()
115		{
116		// inherit a copy of the static data
117		const pc090oj_interface *intf = reinterpret_cast<const pc090oj_interface *>(static_config());
118		if (intf != NULL)
119		*static_cast<pc090oj_interface *>(this) = *intf;
120
121		// or initialize to defaults if none provided
122		else
123		{
124		}
125		}
126
127		//-------------------------------------------------
128	112	//  device_start - device-specific startup
129	113	//-------------------------------------------------
130	114

branches/new_menus/src/mame/video/pc090oj.h

r29505	r29506
1		#ifndef _PC090OJ_H_
2		#define _PC090OJ_H_
	1	#ifndef __PC090OJ_H__
	2	#define __PC090OJ_H__
3	3
4		struct pc090oj_interface
	4	class pc090oj_device : public device_t
5	5	{
6		int                m_gfxnum;
7
8		int                m_x_offset, m_y_offset;
9		int                m_use_buffer;
10		};
11
12		class pc090oj_device : public device_t,
13		public pc090oj_interface
14		{
15	6	public:
16	7	pc090oj_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
17	8	~pc090oj_device() {}
r29505	r29506
19	10	// static configuration
20	11	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
21	12	static void static_set_palette_tag(device_t &device, const char *tag);
22
	13	static void set_gfx_region(device_t &device, int gfxregion) { downcast<pc090oj_device &>(device).m_gfxnum = gfxregion; }
	14	static void set_usebuffer(device_t &device, int use_buf) { downcast<pc090oj_device &>(device).m_use_buffer = use_buf; }
	15	static void set_offsets(device_t &device, int x_offset, int y_offset)
	16	{
	17	pc090oj_device &dev = downcast<pc090oj_device &>(device);
	18	dev.m_x_offset = x_offset;
	19	dev.m_y_offset = y_offset;
	20	}
	21
23	22	DECLARE_READ16_MEMBER( word_r );
24	23	DECLARE_WRITE16_MEMBER( word_w );
25	24
r29505	r29506
29	28
30	29	protected:
31	30	// device-level overrides
32		virtual void device_config_complete();
33	31	virtual void device_start();
34	32	virtual void device_reset();
35	33
r29505	r29506
49	47
50	48	UINT16 *   m_ram;
51	49	UINT16 *   m_ram_buffered;
	50
	51	int        m_gfxnum;
	52	int        m_x_offset, m_y_offset;
	53	int        m_use_buffer;
	54
52	55	required_device<gfxdecode_device> m_gfxdecode;
53	56	required_device<palette_device> m_palette;
54	57	};
55	58
56	59	extern const device_type PC090OJ;
57	60
58		#define MCFG_PC090OJ_ADD(_tag, _interface) \
59		MCFG_DEVICE_ADD(_tag, PC090OJ, 0) \
60		MCFG_DEVICE_CONFIG(_interface)
61	61
	62	#define MCFG_PC090OJ_GFX_REGION(_region) \
	63	pc090oj_device::set_gfx_region(*device, _region);
	64
	65	#define MCFG_PC090OJ_OFFSETS(_xoffs, _yoffs) \
	66	pc090oj_device::set_offsets(*device, _xoffs, _yoffs);
	67
	68	#define MCFG_PC090OJ_USEBUFFER(_use_buf) \
	69	pc090oj_device::set_usebuffer(*device, _use_buf);
	70
62	71	#define MCFG_PC090OJ_GFXDECODE(_gfxtag) \
63	72	pc090oj_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
64	73

branches/new_menus/src/mame/video/tumbleb.c

r29505	r29506
291	291	else
292	292	m_pf1_alt_tilemap->draw(screen, bitmap, cliprect, 0, 0);
293	293
294		machine().device<decospr_device>("spritegen")->draw_sprites(bitmap, cliprect, m_spriteram, m_spriteram.bytes()/2);
	294	m_sprgen->draw_sprites(bitmap, cliprect, m_spriteram, m_spriteram.bytes()/2);
295	295	}
296	296
297	297	UINT32 tumbleb_state::screen_update_tumblepb(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)

branches/new_menus/src/mame/video/tc0100scn.c

r29505	r29506
141	141	m_bg1_colbank(0),
142	142	m_tx_colbank(0),
143	143	m_dblwidth(0),
	144	m_gfxnum(0),
	145	m_txnum(0),
	146	m_x_offset(0),
	147	m_y_offset(0),
	148	m_flip_xoffs(0),
	149	m_flip_yoffs(0),
	150	m_flip_text_xoffs(0),
	151	m_flip_text_yoffs(0),
	152	m_multiscrn_xoffs(0),
	153	m_multiscrn_hack(0),
144	154	m_gfxdecode(*this),
145	155	m_palette(*this)
146	156	{
r29505	r29506
167	177	}
168	178
169	179	//-------------------------------------------------
170		//  device_config_complete - perform any
171		//  operations now that the configuration is
172		//  complete
173		//-------------------------------------------------
174
175		void tc0100scn_device::device_config_complete()
176		{
177		// inherit a copy of the static data
178		const tc0100scn_interface *intf = reinterpret_cast<const tc0100scn_interface *>(static_config());
179		if (intf != NULL)
180		*static_cast<tc0100scn_interface *>(this) = *intf;
181
182		// or initialize to defaults if none provided
183		else
184		{
185		}
186		}
187
188		//-------------------------------------------------
189	180	//  device_start - device-specific startup
190	181	//-------------------------------------------------
191	182
r29505	r29506
300	291
301	292	void tc0100scn_device::device_reset()
302	293	{
303		int i;
304
305	294	m_dblwidth = 0;
306	295	m_colbank = 0;
307	296	m_gfxbank = 0; /* Mjnquest uniquely banks tiles */
308	297
309		for (i = 0; i < 8; i++)
	298	for (int i = 0; i < 8; i++)
310	299	m_ctrl[i] = 0;
311	300	}
312	301

branches/new_menus/src/mame/video/tc0280grd.c

r29505	r29506
47	47
48	48
49	49	//-------------------------------------------------
50		//  device_config_complete - perform any
51		//  operations now that the configuration is
52		//  complete
53		//-------------------------------------------------
54
55		void tc0280grd_device::device_config_complete()
56		{
57		// inherit a copy of the static data
58		const tc0280grd_interface *intf = reinterpret_cast<const tc0280grd_interface *>(static_config());
59		if (intf != NULL)
60		*static_cast<tc0280grd_interface *>(this) = *intf;
61
62		// or initialize to defaults if none provided
63		else
64		{
65		}
66		}
67
68		//-------------------------------------------------
69	50	//  device_start - device-specific startup
70	51	//-------------------------------------------------
71	52

branches/new_menus/src/mame/video/tc0100scn.h

r29505	r29506
1		#ifndef _TC0100SCN_H_
2		#define _TC0100SCN_H_
	1	#ifndef __TC0100SCN_H__
	2	#define __TC0100SCN_H__
3	3
4		struct tc0100scn_interface
	4	class tc0100scn_device : public device_t
5	5	{
6		int                m_gfxnum;
7		int                m_txnum;
8
9		int                m_x_offset, m_y_offset;
10		int                m_flip_xoffs, m_flip_yoffs;
11		int                m_flip_text_xoffs, m_flip_text_yoffs;
12
13		int                m_multiscrn_xoffs;
14		int                m_multiscrn_hack;
15		};
16
17		class tc0100scn_device : public device_t,
18		public tc0100scn_interface
19		{
20	6	public:
21	7	tc0100scn_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
22	8	~tc0100scn_device() {}
r29505	r29506
24	10	// static configuration
25	11	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
26	12	static void static_set_palette_tag(device_t &device, const char *tag);
27
	13	static void set_gfx_region(device_t &device, int gfxregion) { downcast<tc0100scn_device &>(device).m_gfxnum = gfxregion; }
	14	static void set_tx_region(device_t &device, int txregion) { downcast<tc0100scn_device &>(device).m_txnum = txregion; }
	15	static void set_multiscr_xoffs(device_t &device, int xoffs) { downcast<tc0100scn_device &>(device).m_multiscrn_xoffs = xoffs; }
	16	static void set_multiscr_hack(device_t &device, int hack) { downcast<tc0100scn_device &>(device).m_multiscrn_hack = hack; }
	17	static void set_offsets(device_t &device, int x_offset, int y_offset)
	18	{
	19	tc0100scn_device &dev = downcast<tc0100scn_device &>(device);
	20	dev.m_x_offset = x_offset;
	21	dev.m_y_offset = y_offset;
	22	}
	23	static void set_offsets_flip(device_t &device, int x_offset, int y_offset)
	24	{
	25	tc0100scn_device &dev = downcast<tc0100scn_device &>(device);
	26	dev.m_flip_xoffs = x_offset;
	27	dev.m_flip_yoffs = y_offset;
	28	}
	29	static void set_offsets_fliptx(device_t &device, int x_offset, int y_offset)
	30	{
	31	tc0100scn_device &dev = downcast<tc0100scn_device &>(device);
	32	dev.m_flip_text_xoffs = x_offset;
	33	dev.m_flip_text_yoffs = y_offset;
	34	}
	35
28	36	#define TC0100SCN_SINGLE_VDU    1024
29	37
30	38	/* Function to set separate color banks for the three tilemapped layers.
r29505	r29506
63	71
64	72	protected:
65	73	// device-level overrides
66		virtual void device_config_complete();
67	74	virtual void device_start();
68	75	virtual void device_reset();
69	76
r29505	r29506
90	97	INT32        m_bg0_colbank, m_bg1_colbank, m_tx_colbank;
91	98	int          m_dblwidth;
92	99
	100	int          m_gfxnum;
	101	int          m_txnum;
	102	int          m_x_offset, m_y_offset;
	103	int          m_flip_xoffs, m_flip_yoffs;
	104	int          m_flip_text_xoffs, m_flip_text_yoffs;
	105	int          m_multiscrn_xoffs;
	106	int          m_multiscrn_hack;
	107
93	108	required_device<gfxdecode_device> m_gfxdecode;
94	109	required_device<palette_device> m_palette;
95	110
r29505	r29506
110	125	extern const device_type TC0100SCN;
111	126
112	127
113		#define MCFG_TC0100SCN_ADD(_tag, _interface) \
114		MCFG_DEVICE_ADD(_tag, TC0100SCN, 0) \
115		MCFG_DEVICE_CONFIG(_interface)
	128	#define MCFG_TC0100SCN_GFX_REGION(_region) \
	129	tc0100scn_device::set_gfx_region(*device, _region);
116	130
	131	#define MCFG_TC0100SCN_TX_REGION(_region) \
	132	tc0100scn_device::set_tx_region(*device, _region);
	133
	134	#define MCFG_TC0100SCN_OFFSETS(_xoffs, _yoffs) \
	135	tc0100scn_device::set_offsets(*device, _xoffs, _yoffs);
	136
	137	#define MCFG_TC0100SCN_OFFSETS_FLIP(_xoffs, _yoffs) \
	138	tc0100scn_device::set_offsets_flip(*device, _xoffs, _yoffs);
	139
	140	#define MCFG_TC0100SCN_OFFSETS_FLIPTX(_xoffs, _yoffs) \
	141	tc0100scn_device::set_offsets_fliptx(*device, _xoffs, _yoffs);
	142
	143	#define MCFG_TC0100SCN_MULTISCR_XOFFS(_xoffs) \
	144	tc0100scn_device::set_multiscr_xoffs(*device, _xoffs);
	145
	146	#define MCFG_TC0100SCN_MULTISCR_HACK(_hack) \
	147	tc0100scn_device::set_multiscr_hack(*device, _hack);
	148
117	149	#define MCFG_TC0100SCN_GFXDECODE(_gfxtag) \
118	150	tc0100scn_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
119	151

branches/new_menus/src/mame/video/tc0280grd.h

r29505	r29506
1		#ifndef _TC0280GRD_H_
2		#define _TC0280GRD_H_
	1	#ifndef __TC0280GRD_H__
	2	#define __TC0280GRD_H__
3	3
4		struct tc0280grd_interface
	4	class tc0280grd_device : public device_t
5	5	{
6		int                m_gfxnum;
7		};
8
9		class tc0280grd_device : public device_t,
10		public tc0280grd_interface
11		{
12	6	public:
13	7	tc0280grd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
14	8	~tc0280grd_device() {}
15	9
16	10	// static configuration
17	11	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
	12	static void set_gfx_region(device_t &device, int gfxregion) { downcast<tc0280grd_device &>(device).m_gfxnum = gfxregion; }
18	13
19	14	DECLARE_READ16_MEMBER( tc0280grd_word_r );
20	15	DECLARE_WRITE16_MEMBER( tc0280grd_word_w );
r29505	r29506
30	25
31	26	protected:
32	27	// device-level overrides
33		virtual void device_config_complete();
34	28	virtual void device_start();
35	29	virtual void device_reset();
36	30
r29505	r29506
42	36
43	37	UINT16         m_ctrl[8];
44	38	int            m_base_color;
	39	int            m_gfxnum;
45	40	required_device<gfxdecode_device> m_gfxdecode;
46	41
47	42	TILE_GET_INFO_MEMBER(tc0280grd_get_tile_info);
r29505	r29506
60	55	MCFG_DEVICE_ADD(_tag, TC0430GRW, 0) \
61	56	MCFG_DEVICE_CONFIG(_interface)
62	57
	58	#define MCFG_TC0280GRD_GFX_REGION(_region) \
	59	tc0280grd_device::set_gfx_region(*device, _region);
	60
	61	#define MCFG_TC0430GRW_GFX_REGION(_region) \
	62	tc0280grd_device::set_gfx_region(*device, _region);
	63
63	64	#define MCFG_TC0280GRD_GFXDECODE(_gfxtag) \
64	65	tc0280grd_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
65	66

branches/new_menus/src/mame/video/ppu2c0x.c

r29505	r29506
111	111
112	112	void ppu2c0x_device::device_config_complete()
113	113	{
114		const ppu2c0x_interface *config = reinterpret_cast<const ppu2c0x_interface *>(static_config());
115		assert(config);
116
117	114	/* reset the callbacks */
118	115	m_latch = ppu2c0x_latch_delegate();
119	116	m_scanline_callback_proc = ppu2c0x_scanline_delegate();
120	117	m_hblank_callback_proc = ppu2c0x_hblank_delegate();
121	118	m_vidaccess_callback_proc = ppu2c0x_vidaccess_delegate();
122
123		m_color_base = config->color_base;
124
125		m_cpu_tag = config->cpu_tag;
126	119	}
127	120
128	121	ppu2c0x_device::ppu2c0x_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
r29505	r29506
130	123	device_memory_interface(mconfig, *this),
131	124	device_video_interface(mconfig, *this),
132	125	m_space_config("videoram", ENDIANNESS_LITTLE, 8, 17, 0, NULL, *ADDRESS_MAP_NAME(ppu2c0x)),
	126	m_cpu(*this),
133	127	m_scanline(0),  // reset the scanline count
134	128	m_refresh_data(0),
135	129	m_refresh_latch(0),
r29505	r29506
142	136	m_tile_page(0),
143	137	m_sprite_page(0),
144	138	m_back_color(0),
	139	m_color_base(0),
145	140	m_scan_scale(1), // set the scan scale (this is for dual monitor vertical setups)
146	141	m_tilecount(0),
147	142	m_draw_phase(0)
r29505	r29506
210	205
211	206	void ppu2c0x_device::device_start()
212	207	{
213		m_cpu = machine().device<cpu_device>( m_cpu_tag );
214
215		assert(m_cpu);
216
217	208	// bind our handler
218	209	m_nmi_callback_proc.bind_relative_to(*owner());
219	210

branches/new_menus/src/mame/video/ppu2c0x.h

r29505	r29506
83	83	//  INTERFACE CONFIGURATION MACROS
84	84	///*************************************************************************
85	85
86		#define MCFG_PPU2C0X_ADD(_tag, _type, _intrf)   \
87		MCFG_DEVICE_ADD(_tag, _type, 0) \
88		MCFG_DEVICE_CONFIG(_intrf)
	86	#define MCFG_PPU2C0X_ADD(_tag, _type)   \
	87	MCFG_DEVICE_ADD(_tag, _type, 0)
89	88
90		#define MCFG_PPU2C02_ADD(_tag, _intrf)   \
91		MCFG_PPU2C0X_ADD(_tag, PPU_2C02, _intrf)
92		#define MCFG_PPU2C03B_ADD(_tag, _intrf)   \
93		MCFG_PPU2C0X_ADD(_tag, PPU_2C03B, _intrf)
94		#define MCFG_PPU2C04_ADD(_tag, _intrf)   \
95		MCFG_PPU2C0X_ADD(_tag, PPU_2C04, _intrf)
96		#define MCFG_PPU2C07_ADD(_tag, _intrf)   \
97		MCFG_PPU2C0X_ADD(_tag, PPU_2C07, _intrf)
98		#define MCFG_PPU2C05_01_ADD(_tag, _intrf)   \
99		MCFG_PPU2C0X_ADD(_tag, PPU_2C05_01, _intrf)
100		#define MCFG_PPU2C05_02_ADD(_tag, _intrf)   \
101		MCFG_PPU2C0X_ADD(_tag, PPU_2C05_02, _intrf)
102		#define MCFG_PPU2C05_03_ADD(_tag, _intrf)   \
103		MCFG_PPU2C0X_ADD(_tag, PPU_2C05_03, _intrf)
104		#define MCFG_PPU2C05_04_ADD(_tag, _intrf)   \
105		MCFG_PPU2C0X_ADD(_tag, PPU_2C05_04, _intrf)
	89	#define MCFG_PPU2C02_ADD(_tag)   \
	90	MCFG_PPU2C0X_ADD(_tag, PPU_2C02)
	91	#define MCFG_PPU2C03B_ADD(_tag)   \
	92	MCFG_PPU2C0X_ADD(_tag, PPU_2C03B)
	93	#define MCFG_PPU2C04_ADD(_tag)   \
	94	MCFG_PPU2C0X_ADD(_tag, PPU_2C04)
	95	#define MCFG_PPU2C07_ADD(_tag)   \
	96	MCFG_PPU2C0X_ADD(_tag, PPU_2C07)
	97	#define MCFG_PPU2C05_01_ADD(_tag)   \
	98	MCFG_PPU2C0X_ADD(_tag, PPU_2C05_01)
	99	#define MCFG_PPU2C05_02_ADD(_tag)   \
	100	MCFG_PPU2C0X_ADD(_tag, PPU_2C05_02)
	101	#define MCFG_PPU2C05_03_ADD(_tag)   \
	102	MCFG_PPU2C0X_ADD(_tag, PPU_2C05_03)
	103	#define MCFG_PPU2C05_04_ADD(_tag)   \
	104	MCFG_PPU2C0X_ADD(_tag, PPU_2C05_04)
106	105
107	106	#define MCFG_PPU2C0X_SET_SCREEN MCFG_VIDEO_SET_SCREEN
108	107
109		#define MCFG_PPU2C0X_SET_NMI( _class, _method) \
	108	#define MCFG_PPU2C0X_CPU(_tag) \
	109	ppu2c0x_device::set_cpu_tag(*device, "^"_tag);
	110
	111	#define MCFG_PPU2C0X_COLORBASE(_color) \
	112	ppu2c0x_device::set_color_base(*device, _color);
	113
	114	#define MCFG_PPU2C0X_SET_NMI(_class, _method) \
110	115	ppu2c0x_device::set_nmi_delegate(*device, ppu2c0x_nmi_delegate(&_class::_method, #_class "::" #_method, NULL, (_class *)0));
111	116
	117
112	118	///*************************************************************************
113	119	//  TYPE DEFINITIONS
114	120	///*************************************************************************
r29505	r29506
119	125	typedef device_delegate<void (offs_t offset)> ppu2c0x_latch_delegate;
120	126
121	127
122		// ======================> ppu2c0x_interface
123
124		struct ppu2c0x_interface
125		{
126		const char        *cpu_tag;
127		int               gfx_layout_number;        /* gfx layout number used by each chip */
128		int               color_base;               /* color base to use per ppu */
129		int               mirroring;                /* mirroring options (PPU_MIRROR_* flag) */
130		};
131
132
133	128	// ======================> ppu2c0x_device
134	129
135	130	class ppu2c0x_device :  public device_t,
136	131	public device_memory_interface,
137		public device_video_interface,
138		public ppu2c0x_interface
	132	public device_video_interface
139	133	{
140	134	public:
141	135	// construction/destruction
r29505	r29506
154	148	// address space configurations
155	149	const address_space_config      m_space_config;
156	150
	151	static void set_cpu_tag(device_t &device, const char *tag) { downcast<ppu2c0x_device &>(device).m_cpu.set_tag(tag); }
	152	static void set_color_base(device_t &device, int colorbase) { downcast<ppu2c0x_device &>(device).m_color_base = colorbase; }
	153	static void set_nmi_delegate(device_t &device, ppu2c0x_nmi_delegate cb);
157	154
158	155	/* routines */
159	156	void init_palette( palette_device &palette, int first_entry );
r29505	r29506
173	170	void set_scanline_callback( ppu2c0x_scanline_delegate cb ) { m_scanline_callback_proc = cb; m_scanline_callback_proc.bind_relative_to(*owner()); };
174	171	void set_hblank_callback( ppu2c0x_hblank_delegate cb ) { m_hblank_callback_proc = cb; m_hblank_callback_proc.bind_relative_to(*owner()); };
175	172	void set_vidaccess_callback( ppu2c0x_vidaccess_delegate cb ) { m_vidaccess_callback_proc = cb; m_vidaccess_callback_proc.bind_relative_to(*owner()); };
176		static void set_nmi_delegate(device_t &device,ppu2c0x_nmi_delegate cb);
177	173	void set_scanlines_per_frame( int scanlines ) { m_scanlines_per_frame = scanlines; };
178	174
179	175	// MMC5 has to be able to check this
r29505	r29506
186	182
187	183	//  void update_screen(bitmap_t &bitmap, const rectangle &cliprect);
188	184
189		cpu_device                  *m_cpu;
	185	required_device<cpu_device> m_cpu;
	186
190	187	bitmap_ind16                *m_bitmap;          /* target bitmap */
191	188	UINT8                       *m_spriteram;           /* sprite ram */
192	189	pen_t                       *m_colortable;          /* color table modified at run time */
r29505	r29506
222	219	emu_timer                   *m_nmi_timer;           /* NMI timer */
223	220	emu_timer                   *m_scanline_timer;      /* scanline timer */
224	221
225		const char        *m_cpu_tag;
226
227	222	private:
228	223	static const device_timer_id TIMER_HBLANK = 0;
229	224	static const device_timer_id TIMER_NMI = 1;

branches/new_menus/src/mame/video/rohga.c

r29505	r29506
15	15	m_spriteram->copy();
16	16	}
17	17
18		VIDEO_START_MEMBER(rohga_state,rohga)
19		{
20		m_sprgen1->set_col_callback(rohga_col_callback);
21		m_sprgen1->set_pri_callback(rohga_pri_callback);
22		}
23
24		VIDEO_START_MEMBER(rohga_state,schmeisr)
25		{
26		VIDEO_START_CALL_MEMBER( rohga );
27		// wire mods on pcb..
28		m_sprgen1->set_col_callback(schmeisr_col_callback);
29		}
30
31
32		UINT16 rohga_pri_callback(UINT16 x)
33		{
34		switch (x & 0x6000)
35		{
36		case 0x0000: return 0;
37		case 0x4000: return 0xf0;
38		case 0x6000: return 0xf0 | 0xcc;
39		case 0x2000: return 0;//0xf0|0xcc; /* Perhaps 0xf0|0xcc|0xaa (Sprite under bottom layer) */
40		}
41
42		return 0;
43		}
44
45		UINT16 schmeisr_col_callback(UINT16 x)
46		{
47		UINT16 colour = ((x >> 9) & 0xf) << 2;
48		if (x & 0x8000)
49		colour++;
50
51		return colour;
52		}
53
54		UINT16 rohga_col_callback(UINT16 x)
55		{
56		return (x >> 9) & 0xf;
57		}
58
59
60
61	18	/******************************************************************************/
62	19
63	20	UINT32 rohga_state::screen_update_rohga(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
r29505	r29506
125	82	bitmap_ind16* sprite_bitmap;
126	83	int penbase;
127	84
128		sprite_bitmap = &machine().device<decospr_device>("spritegen2")->get_sprite_temp_bitmap();
	85	sprite_bitmap = &m_sprgen2->get_sprite_temp_bitmap();
129	86	penbase = 0x600;
130	87
131	88	UINT16* srcline;

branches/new_menus/src/mame/video/k054338.c

r29505	r29506
1	1
2	2	#include "emu.h"
3	3	#include "k054338.h"
4		#include "k055555.h"
5	4
6	5
7	6	#define VERBOSE 0
r29505	r29506
237	236
238	237	k054338_device::k054338_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
239	238	: device_t(mconfig, K054338, "Konami 054338", tag, owner, clock, "k054338", __FILE__),
240		device_video_interface(mconfig, *this)
	239	device_video_interface(mconfig, *this),
	240	m_alpha_inv(0),
	241	m_k055555_tag("")
241	242	//m_regs[32],
242	243	//m_shd_rgb[9],
243	244	{
244	245	}
245	246
246	247	//-------------------------------------------------
247		//  device_config_complete - perform any
248		//  operations now that the configuration is
249		//  complete
250		//-------------------------------------------------
251
252		void k054338_device::device_config_complete()
253		{
254		// inherit a copy of the static data
255		const k054338_interface *intf = reinterpret_cast<const k054338_interface *>(static_config());
256		if (intf != NULL)
257		*static_cast<k054338_interface *>(this) = *intf;
258
259		// or initialize to defaults if none provided
260		else
261		{
262		m_alpha_inv = 0;
263		m_k055555_tag = "";
264		};
265		}
266
267		//-------------------------------------------------
268	248	//  device_start - device-specific startup
269	249	//-------------------------------------------------
270	250

branches/new_menus/src/mame/video/k054338.h

r29505	r29506
1
2	1	#pragma once
3	2	#ifndef __K054338_H__
4	3	#define __K054338_H__
5	4
6	5	#include "k055555.h"
7	6
8		#define MCFG_K054338_ADD(_tag, _interface) \
9		MCFG_DEVICE_ADD(_tag, K054338, 0) \
10		MCFG_DEVICE_CONFIG(_interface)
11	7
12
13
14	8	/* K054338 mixer/alpha blender */
15	9	void K054338_vh_start(running_machine &machine, k055555_device* k055555);
16	10	DECLARE_WRITE16_HANDLER( K054338_word_w ); // "CLCT" registers
r29505	r29506
38	32	#define K338_CTL_CLIPSL     0x20
39	33
40	34
41		struct k054338_interface
42		{
43		int                m_alpha_inv;
44		const char         *m_k055555_tag;
45		};
46
47
48	35	class k054338_device : public device_t,
49		public device_video_interface,
50		public k054338_interface
	36	public device_video_interface
51	37	{
52	38	public:
53	39	k054338_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
54	40	~k054338_device() {}
55	41
	42	// static configuration
	43	static void set_mixer_tag(device_t &device, const char  *tag) { downcast<k054338_device &>(device).m_k055555_tag = tag; }
	44	static void set_yinvert(device_t &device, int alpha_inv) { downcast<k054338_device &>(device).m_alpha_inv = alpha_inv; }
	45
56	46	DECLARE_WRITE16_MEMBER( word_w ); // "CLCT" registers
57	47	DECLARE_WRITE32_MEMBER( long_w );
58	48
r29505	r29506
68	58
69	59	protected:
70	60	// device-level overrides
71		virtual void device_config_complete();
72	61	virtual void device_start();
73	62	virtual void device_reset();
74	63
75	64	private:
76	65	// internal state
77		UINT16    m_regs[32];
78		int       m_shd_rgb[9];
	66	UINT16      m_regs[32];
	67	int         m_shd_rgb[9];
	68	int         m_alpha_inv;
	69	const char  *m_k055555_tag;
79	70
80	71	k055555_device *m_k055555;  /* used to fill BG color */
81	72	};
82	73
83	74	extern const device_type K054338;
84	75
	76
	77	#define MCFG_K054338_MIXER(_tag) \
	78	k054338_device::set_mixer_tag(*device, _tag);
	79
	80	#define MCFG_K054338_ALPHAINV(_alphainv) \
	81	k054338_device::set_alpha_invert(*device, _alphainv);
	82
	83
85	84	#endif

branches/new_menus/src/mame/video/namcona1.c

r29505	r29506
14	14	tile_data &tileinfo,
15	15	int tile_index,
16	16	const UINT16 *tilemap_videoram,
17		int tilemap_color,
18	17	bool use_4bpp_gfx )
19	18	{
20	19	UINT16 *source;
21	20
22	21	int data = tilemap_videoram[tile_index];
23	22	int tile = data&0xfff;
24		int gfx;
	23	int gfx = use_4bpp_gfx ? 1 : 0;
	24	int color = use_4bpp_gfx ? (data & 0x7000)>>12 : 0;
25	25
26		if( use_4bpp_gfx )
27		{
28		gfx = 1;
29		tilemap_color *= 0x10;
30		tilemap_color += (data & 0x7000)>>12;
31		}
32		else
33		{
34		gfx = 0;
35		}
36
37	26	if( data & 0x8000 )
38	27	{
39		SET_TILE_INFO_MEMBER(gfx,tile,tilemap_color,TILE_FORCE_LAYER0 );
	28	SET_TILE_INFO_MEMBER(gfx,tile,color,TILE_FORCE_LAYER0 );
40	29	}
41	30	else
42	31	{
43		SET_TILE_INFO_MEMBER(gfx,tile,tilemap_color,0 );
44		if (ENDIANNESS_NATIVE == ENDIANNESS_BIG)
45		tileinfo.mask_data = (UINT8 *)(m_shaperam+4*tile);
46		else
47		{
48		UINT8 *mask_data = m_mask_data;
49		source = m_shaperam+4*tile;
50		mask_data[0] = source[0]>>8;
51		mask_data[1] = source[0]&0xff;
52		mask_data[2] = source[1]>>8;
53		mask_data[3] = source[1]&0xff;
54		mask_data[4] = source[2]>>8;
55		mask_data[5] = source[2]&0xff;
56		mask_data[6] = source[3]>>8;
57		mask_data[7] = source[3]&0xff;
58		tileinfo.mask_data = mask_data;
59		}
	32	SET_TILE_INFO_MEMBER(gfx,tile,color,0 );
	33	tileinfo.mask_data = &m_shaperam[tile*8];
60	34	}
61	35	} /* tilemap_get_info */
62	36
63	37	TILE_GET_INFO_MEMBER(namcona1_state::tilemap_get_info0)
64	38	{
65	39	UINT16 *videoram = m_videoram;
66		tilemap_get_info(tileinfo,tile_index,0*0x1000+videoram,m_tilemap_palette_bank[0],m_vreg[0xbc/2]&1);
	40	tilemap_get_info(tileinfo,tile_index,0*0x1000+videoram,m_vreg[0xbc/2]&1);
67	41	}
68	42
69	43	TILE_GET_INFO_MEMBER(namcona1_state::tilemap_get_info1)
70	44	{
71	45	UINT16 *videoram = m_videoram;
72		tilemap_get_info(tileinfo,tile_index,1*0x1000+videoram,m_tilemap_palette_bank[1],m_vreg[0xbc/2]&2);
	46	tilemap_get_info(tileinfo,tile_index,1*0x1000+videoram,m_vreg[0xbc/2]&2);
73	47	}
74	48
75	49	TILE_GET_INFO_MEMBER(namcona1_state::tilemap_get_info2)
76	50	{
77	51	UINT16 *videoram = m_videoram;
78		tilemap_get_info(tileinfo,tile_index,2*0x1000+videoram,m_tilemap_palette_bank[2],m_vreg[0xbc/2]&4);
	52	tilemap_get_info(tileinfo,tile_index,2*0x1000+videoram,m_vreg[0xbc/2]&4);
79	53	}
80	54
81	55	TILE_GET_INFO_MEMBER(namcona1_state::tilemap_get_info3)
82	56	{
83	57	UINT16 *videoram = m_videoram;
84		tilemap_get_info(tileinfo,tile_index,3*0x1000+videoram,m_tilemap_palette_bank[3],m_vreg[0xbc/2]&8);
	58	tilemap_get_info(tileinfo,tile_index,3*0x1000+videoram,m_vreg[0xbc/2]&8);
85	59	}
86	60
87	61	TILE_GET_INFO_MEMBER(namcona1_state::roz_get_info)
88	62	{
89		UINT16 *videoram = m_videoram;
90	63	/* each logical tile is constructed from 4*4 normal tiles */
91		int tilemap_color = m_roz_palette;
92	64	int use_4bpp_gfx = m_vreg[0xbc/2]&16; /* ? */
93	65	int c = tile_index%0x40;
94	66	int r = tile_index/0x40;
95		int data = videoram[0x8000/2+(r/4)*0x40+c/4]&0xfbf; /* mask out bit 0x40 - patch for Emeraldia Japan */
	67	int data = m_videoram[0x8000/2+(r/4)*0x40+c/4]&0xfbf; /* mask out bit 0x40 - patch for Emeraldia Japan */
96	68	int tile = (data+(c%4)+(r%4)*0x40)&0xfff;
97		int gfx = use_4bpp_gfx;
98		if( use_4bpp_gfx )
99		{
100		tilemap_color *= 0x10;
101		tilemap_color += (data & 0x7000)>>12;
102		}
	69	int gfx = use_4bpp_gfx ? 1 : 0;
	70	int color = use_4bpp_gfx ? (data & 0x7000)>>12 : 0;
	71
103	72	if( data & 0x8000 )
104	73	{
105		SET_TILE_INFO_MEMBER(gfx,tile,tilemap_color,TILE_FORCE_LAYER0 );
	74	SET_TILE_INFO_MEMBER(gfx,tile,color,TILE_FORCE_LAYER0 );
106	75	}
107	76	else
108	77	{
109		UINT8 *mask_data = (UINT8 *)(m_shaperam+4*tile);
110
111		if (ENDIANNESS_NATIVE == ENDIANNESS_LITTLE)
112		{
113		UINT16 *source = (UINT16 *)mask_data;
114		UINT8 *conv_data = m_conv_data;
115		conv_data[0] = source[0]>>8;
116		conv_data[1] = source[0]&0xff;
117		conv_data[2] = source[1]>>8;
118		conv_data[3] = source[1]&0xff;
119		conv_data[4] = source[2]>>8;
120		conv_data[5] = source[2]&0xff;
121		conv_data[6] = source[3]>>8;
122		conv_data[7] = source[3]&0xff;
123		mask_data = conv_data;
124		}
125		SET_TILE_INFO_MEMBER(gfx,tile,tilemap_color,0 );
126		tileinfo.mask_data = mask_data;
	78	SET_TILE_INFO_MEMBER(gfx,tile,color,0 );
	79	tileinfo.mask_data = &m_shaperam[tile*8];
127	80	}
128	81	} /* roz_get_info */
129	82
r29505	r29506
135	88	COMBINE_DATA( &videoram[offset] );
136	89	if( offset<0x8000/2 )
137	90	{
138		m_bg_tilemap[offset/0x1000]->mark_tile_dirty(offset&0xfff );
	91	m_bg_tilemap[offset/0x1000]->mark_tile_dirty(offset&0xfff);
139	92	}
140	93	else if( offset<0xa000/2 )
141	94	{
142		m_roz_tilemap ->mark_all_dirty();
	95	m_bg_tilemap[4]->mark_all_dirty();
143	96	}
144	97	} /* namcona1_videoram_w */
145	98
146		READ16_MEMBER(namcona1_state::namcona1_videoram_r)
147		{
148		UINT16 *videoram = m_videoram;
149		return videoram[offset];
150		} /* namcona1_videoram_r */
151
152	99	/*************************************************************************/
153	100
154	101	void namcona1_state::UpdatePalette( int offset )
155	102	{
156		UINT16 data = m_generic_paletteram_16[offset]; /* -RRRRRGG GGGBBBBB */
	103	UINT16 data = m_paletteram[offset]; /* -RRRRRGG GGGBBBBB */
157	104	/**
158	105	* sprites can be configured to use an alternate interpretation of palette ram
159	106	* (used in-game in Emeraldia)
r29505	r29506
168	115	m_palette->set_pen_color(offset, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
169	116	} /* namcona1_paletteram_w */
170	117
171		READ16_MEMBER(namcona1_state::namcona1_paletteram_r)
172		{
173		return m_generic_paletteram_16[offset];
174		} /* namcona1_paletteram_r */
175
176	118	WRITE16_MEMBER(namcona1_state::namcona1_paletteram_w)
177	119	{
178		COMBINE_DATA( &m_generic_paletteram_16[offset] );
	120	COMBINE_DATA( &m_paletteram[offset] );
179	121	if( m_vreg[0x8e/2] )
180	122	{ /* graphics enabled; update palette immediately */
181	123	UpdatePalette( offset );
r29505	r29506
186	128	}
187	129	}
188	130
189		/*************************************************************************/
190	131
191		static const gfx_layout shape_layout =
192		{
193		8,8,
194		0x1000,
195		1,
196		{ 0 },
197		{ STEP8(0, 1) },
198		{ STEP8(0, 8) },
199		8*8
200		}; /* shape_layout */
201
202		static const gfx_layout cg_layout_8bpp =
203		{
204		8,8,
205		0x1000,
206		8, /* 8BPP */
207		{ 0,1,2,3,4,5,6,7 },
208		{ STEP8(0, 8) },
209		{ STEP8(0, 8*8) },
210		8*8*8
211		}; /* cg_layout_8bpp */
212
213		static const gfx_layout cg_layout_4bpp =
214		{
215		8,8,
216		0x1000,
217		4, /* 4BPP */
218		{ 4,5,6,7 },
219		{ STEP8(0, 8) },
220		{ STEP8(0, 8*8) },
221		8*8*8
222		}; /* cg_layout_4bpp */
223
224	132	READ16_MEMBER(namcona1_state::namcona1_gfxram_r)
225	133	{
226	134	UINT16 type = m_vreg[0x0c/2];
r29505	r29506
228	136	{
229	137	if( offset<0x4000 )
230	138	{
231		return m_shaperam[offset];
	139	offset *= 2;
	140	return (m_shaperam[offset] << 8) | m_shaperam[offset+1];
232	141	}
233	142	}
234	143	else if( type == 0x02 )
r29505	r29506
247	156	{
248	157	if( offset<0x4000 )
249	158	{
250		old_word = m_shaperam[offset];
251		COMBINE_DATA( &m_shaperam[offset] );
252		if( m_shaperam[offset]!=old_word )
253		m_gfxdecode->gfx(2)->mark_dirty(offset/4);
	159	offset *= 2;
	160	if (ACCESSING_BITS_8_15)
	161	m_shaperam[offset] = data >> 8;
	162	if (ACCESSING_BITS_0_7)
	163	m_shaperam[offset+1] = data;
	164	m_gfxdecode->gfx(2)->mark_dirty(offset/8);
254	165	}
255	166	}
256	167	else if( type == 0x02 )
r29505	r29506
265	176	}
266	177	} /* namcona1_gfxram_w */
267	178
268		static void UpdateGfx(running_machine &machine)
269		{
270		} /* UpdateGfx */
271
272	179	void namcona1_state::video_start()
273	180	{
274		m_roz_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::roz_get_info),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
275		m_roz_palette = -1;
276
277		for( int i=0; i<NAMCONA1_NUM_TILEMAPS; i++ )
278		{
279		m_tilemap_palette_bank[i] = -1;
280		}
281
	181	// normal tilemaps
282	182	m_bg_tilemap[0] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info0),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
283	183	m_bg_tilemap[1] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info1),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
284	184	m_bg_tilemap[2] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info2),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
285	185	m_bg_tilemap[3] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info3),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
286	186
287		m_shaperam           = auto_alloc_array_clear(machine(), UINT16, 0x2000*4/2 );
288		m_cgram              = auto_alloc_array_clear(machine(), UINT16, 0x1000*0x40/2 );
	187	// roz tilemap
	188	m_bg_tilemap[4] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::roz_get_info),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
289	189
290		m_gfxdecode->set_gfx(0, global_alloc( gfx_element(m_palette, cg_layout_8bpp, (UINT8 *)m_cgram, NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries()/256, 0 )));
291		m_gfxdecode->set_gfx(1, global_alloc( gfx_element(m_palette, cg_layout_4bpp, (UINT8 *)m_cgram, NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries()/16, 0 )));
292		m_gfxdecode->set_gfx(2, global_alloc( gfx_element(m_palette, shape_layout, (UINT8 *)m_shaperam, NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries()/2, 0 )));
	190	m_shaperam.resize(0x8000);
293	191
	192	m_gfxdecode->gfx(2)->set_source(m_shaperam);
294	193	} /* namcona1_vh_start */
295	194
296	195	/*************************************************************************/
r29505	r29506
537	436
538	437	void namcona1_state::draw_background(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int which, int primask )
539	438	{
540		UINT16 *videoram = m_videoram;
541		/*          scrollx lineselect
542		*  tmap0   ffe000  ffe200
543		*  tmap1   ffe400  ffe600
544		*  tmap2   ffe800  ffea00
545		*  tmap3   ffec00  ffee00
546		*/
547		int xadjust = 0x3a - which*2;
548		const UINT16 *scroll = m_scroll+0x200*which;
549		int line;
550		UINT16 xdata, ydata;
551		int scrollx, scrolly;
552		rectangle clip;
553		const pen_t *paldata;
554		gfx_element *pGfx;
555
556		pGfx = m_gfxdecode->gfx(0);
557		assert(which >= 0 && which < ARRAY_LENGTH(m_tilemap_palette_bank));
558		paldata = &m_palette->pen(pGfx->colorbase() + pGfx->granularity() * m_tilemap_palette_bank[which]);
559
560		/* draw one scanline at a time */
561		clip.min_x = cliprect.min_x;
562		clip.max_x = cliprect.max_x;
563		scrollx = 0;
564		scrolly = 0;
565		for( line=0; line<256; line++ )
	439	if(which == 4)
566	440	{
567		clip.min_y = line;
568		clip.max_y = line;
569		xdata = scroll[line];
570		if( xdata )
571		{
572		/* screenwise linescroll */
573		scrollx = xadjust+xdata;
574		}
575		ydata = scroll[line+0x100];
576		if( ydata&0x4000 )
577		{
578		/* line select: dword offset from 0xff000 or tilemap source line */
579		scrolly = (ydata - line)&0x1ff;
580		}
	441	/* draw the roz tilemap all at once */
	442	int incxx = ((INT16)m_vreg[0xc0/2])<<8;
	443	int incxy = ((INT16)m_vreg[0xc2/2])<<8;
	444	int incyx = ((INT16)m_vreg[0xc4/2])<<8;
	445	int incyy = ((INT16)m_vreg[0xc6/2])<<8;
	446	INT16 xoffset = m_vreg[0xc8/2];
	447	INT16 yoffset = m_vreg[0xca/2];
	448	int dx = 46; /* horizontal adjust */
	449	int dy = -8; /* vertical adjust */
	450	UINT32 startx = (xoffset<<12)+incxx*dx+incyx*dy;
	451	UINT32 starty = (yoffset<<12)+incxy*dx+incyy*dy;
	452	m_bg_tilemap[4]->draw_roz(screen, bitmap, cliprect,
	453	startx, starty, incxx, incxy, incyx, incyy, 0, 0, primask, 0);
	454	}
	455	else
	456	{
	457	/* draw one scanline at a time */
	458	/*          scrollx lineselect
	459	*  tmap0   ffe000  ffe200
	460	*  tmap1   ffe400  ffe600
	461	*  tmap2   ffe800  ffea00
	462	*  tmap3   ffec00  ffee00
	463	*/
	464	const UINT16 *scroll = &m_scroll[which * 0x400/2];
	465	const pen_t *paldata = &m_palette->pen(m_bg_tilemap[which]->palette_offset());
	466	rectangle clip = cliprect;
	467	int xadjust = 0x3a - which*2;
	468	int scrollx = 0;
	469	int scrolly = 0;
581	470
582		if (line >= cliprect.min_y && line <= cliprect.max_y)
	471	for( int line = 0; line < 256; line++ )
583	472	{
584		if( xdata == 0xc001 )
	473	clip.min_y = line;
	474	clip.max_y = line;
	475	int xdata = scroll[line];
	476	int ydata = scroll[line + 0x200/2];
	477
	478	if( xdata )
585	479	{
586		/* This is a simplification, but produces the correct behavior for the only game that uses this
587		* feature, Numan Athletics.
588		*/
589		draw_pixel_line(
590		&bitmap.pix16(line),
591		&screen.priority().pix8(line),
592		videoram + ydata + 25,
593		paldata );
	480	/* screenwise linescroll */
	481	scrollx = xadjust+xdata;
594	482	}
595		else
	483
	484	if( ydata&0x4000 )
596	485	{
597		if(which == NAMCONA1_NUM_TILEMAPS )
	486	/* line select: dword offset from 0xff000 or tilemap source line */
	487	scrolly = (ydata - line)&0x1ff;
	488	}
	489
	490	if (line >= cliprect.min_y && line <= cliprect.max_y)
	491	{
	492	if( xdata == 0xc001 )
598	493	{
599		int incxx = ((INT16)m_vreg[0xc0/2])<<8;
600		int incxy = ((INT16)m_vreg[0xc2/2])<<8;
601		int incyx = ((INT16)m_vreg[0xc4/2])<<8;
602		int incyy = ((INT16)m_vreg[0xc6/2])<<8;
603		INT16 xoffset = m_vreg[0xc8/2];
604		INT16 yoffset = m_vreg[0xca/2];
605		int dx = 46; /* horizontal adjust */
606		int dy = -8; /* vertical adjust */
607		UINT32 startx = (xoffset<<12)+incxx*dx+incyx*dy;
608		UINT32 starty = (yoffset<<12)+incxy*dx+incyy*dy;
609		m_roz_tilemap->draw_roz(screen, bitmap, clip,
610		startx, starty, incxx, incxy, incyx, incyy, 0, 0, primask, 0);
	494	/* This is a simplification, but produces the correct behavior for the only game that uses this
	495	* feature, Numan Athletics.
	496	*/
	497	draw_pixel_line(&bitmap.pix16(line),
	498	&screen.priority().pix8(line),
	499	m_videoram + ydata + 25,
	500	paldata );
611	501	}
612	502	else
613	503	{
r29505	r29506
638	528	}
639	529	m_palette_is_dirty = 0;
640	530	}
641		UpdateGfx(machine());
642		for( which=0; which<NAMCONA1_NUM_TILEMAPS; which++ )
643		{
644		int tilemap_color = m_vreg[0xb0/2+(which&3)]&0xf;
645		if( tilemap_color!=m_tilemap_palette_bank[which] )
646		{
647		m_bg_tilemap[which] ->mark_all_dirty();
648		m_tilemap_palette_bank[which] = tilemap_color;
649		}
650		} /* next tilemap */
651	531
652		{ /* ROZ tilemap */
653		int color = m_vreg[0xba/2]&0xf;
654		if( color != m_roz_palette )
655		{
656		m_roz_tilemap ->mark_all_dirty();
657		m_roz_palette = color;
658		}
659		}
	532	for( which=0; which < 4; which++ )
	533	m_bg_tilemap[which]->set_palette_offset((m_vreg[0xb0/2 + which] & 0xf) * 256);
660	534
	535	m_bg_tilemap[4]->set_palette_offset((m_vreg[0xba/2] & 0xf) * 256);
	536
661	537	screen.priority().fill(0, cliprect );
662	538
663	539	bitmap.fill(0xff, cliprect ); /* background color? */

branches/new_menus/src/mame/video/vsnes.c

r29505	r29506
5	5
6	6	PALETTE_INIT_MEMBER(vsnes_state,vsnes)
7	7	{
8		ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu1");
9		ppu->init_palette_rgb(palette, 0 );
	8	m_ppu1->init_palette_rgb(palette, 0);
10	9	}
11	10
12	11	PALETTE_INIT_MEMBER(vsnes_state,vsdual)
13	12	{
14		ppu2c0x_device *ppu1 = machine().device<ppu2c0x_device>("ppu1");
15		ppu2c0x_device *ppu2 = machine().device<ppu2c0x_device>("ppu2");
16		ppu1->init_palette_rgb(palette, 0 );
17		ppu2->init_palette_rgb(palette, 8*4*16 );
	13	m_ppu1->init_palette_rgb(palette, 0);
	14	m_ppu2->init_palette_rgb(palette, 8 * 4 * 16);
18	15	}
19	16
20	17	void vsnes_state::ppu_irq_1(int *ppu_regs)
21	18	{
22		m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE );
	19	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
23	20	}
24	21
25	22	void vsnes_state::ppu_irq_2(int *ppu_regs)
26	23	{
27		m_subcpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE );
	24	m_subcpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
28	25	}
29	26
30		/* our ppu interface                                            */
31		const ppu2c0x_interface vsnes_ppu_interface_1 =
32		{
33		"maincpu",
34		0,                  /* gfxlayout num */
35		0,                  /* color base */
36		PPU_MIRROR_NONE     /* mirroring */
37		};
38
39		/* our ppu interface for dual games                             */
40		const ppu2c0x_interface vsnes_ppu_interface_2 =
41		{
42		"sub",
43		1,                  /* gfxlayout num */
44		512,                /* color base */
45		PPU_MIRROR_NONE     /* mirroring */
46		};
47
48	27	VIDEO_START_MEMBER(vsnes_state,vsnes )
49	28	{
50	29	}
r29505	r29506
58	37	Display refresh
59	38
60	39	***************************************************************************/
	40
61	41	UINT32 vsnes_state::screen_update_vsnes(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
62	42	{
63	43	/* render the ppu */
64		ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu1");
65		ppu->render(bitmap, 0, 0, 0, 0);
	44	m_ppu1->render(bitmap, 0, 0, 0, 0);
66	45	return 0;
67	46	}
68	47
69	48	UINT32 vsnes_state::screen_update_vsnes_bottom(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
70	49	{
71		ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu2");
72		ppu->render(bitmap, 0, 0, 0, 0);
	50	m_ppu2->render(bitmap, 0, 0, 0, 0);
73	51	return 0;
74	52	}

branches/new_menus/src/mame/video/tc0480scp.c

r29505	r29506
151	151	//m_bgscrolly[4](NULL),
152	152	m_pri_reg(0),
153	153	m_dblwidth(0),
154		m_x_offs(0),
	154	m_gfxnum(0),
	155	m_txnum(0),
	156	m_x_offset(0),
	157	m_y_offset(0),
	158	m_text_xoffs(0),
	159	m_text_yoffs(0),
	160	m_flip_xoffs(0),
	161	m_flip_yoffs(0),
	162	m_col_base(0),
155	163	m_gfxdecode(*this),
156	164	m_palette(*this)
157	165	{
r29505	r29506
178	186	}
179	187
180	188	//-------------------------------------------------
181		//  device_config_complete - perform any
182		//  operations now that the configuration is
183		//  complete
184		//-------------------------------------------------
185
186		void tc0480scp_device::device_config_complete()
187		{
188		// inherit a copy of the static data
189		const tc0480scp_interface *intf = reinterpret_cast<const tc0480scp_interface *>(static_config());
190		if (intf != NULL)
191		*static_cast<tc0480scp_interface *>(this) = *intf;
192
193		// or initialize to defaults if none provided
194		else
195		{
196		}
197		}
198
199		//-------------------------------------------------
200	189	//  device_start - device-specific startup
201	190	//-------------------------------------------------
202	191
r29505	r29506
205	194	if(!m_gfxdecode->started())
206	195	throw device_missing_dependencies();
207	196
208		int i, xd, yd;
	197	int xd, yd;
209	198
210		m_x_offs = m_x_offset + m_pixels;
211
212
213	199	static const gfx_layout tc0480scp_charlayout =
214	200	{
215	201	8,8,    /* 8*8 characters */
r29505	r29506
236	222	m_tilemap[3][1] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(tc0480scp_device::get_bg3_tile_info),this), TILEMAP_SCAN_ROWS, 16, 16, 64, 32);
237	223	m_tilemap[4][1] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(tc0480scp_device::get_tx_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 64, 64);
238	224
239		for (i = 0; i < 2; i++)
	225	for (int i = 0; i < 2; i++)
240	226	{
241	227	m_tilemap[0][i]->set_transparent_pen(0);
242	228	m_tilemap[1][i]->set_transparent_pen(0);
r29505	r29506
245	231	m_tilemap[4][i]->set_transparent_pen(0);
246	232	}
247	233
248		xd = -m_x_offs;
	234	xd = -m_x_offset;
249	235	yd =  m_y_offset;
250	236
251	237	/* Metalb and Deadconx have minor screenflip issues: blue planet
r29505	r29506
280	266	m_tilemap[4][1]->set_scrolldx(xd - 3, 317 - xd);   /* text layer */
281	267	m_tilemap[4][1]->set_scrolldy(yd,     256 - yd);   /* text layer */
282	268
283		for (i = 0; i < 2; i++)
	269	for (int i = 0; i < 2; i++)
284	270	{
285	271	/* Both sets of bg tilemaps scrollable per pixel row */
286	272	m_tilemap[0][i]->set_scroll_rows(512);
r29505	r29506
308	294
309	295	void tc0480scp_device::device_reset()
310	296	{
311		int i;
312
313	297	m_dblwidth = 0;
314	298
315		for (i = 0; i < 0x18; i++)
	299	for (int i = 0; i < 0x18; i++)
316	300	m_ctrl[i] = 0;
317	301
318	302	}
r29505	r29506
733	717	if (!flip)
734	718	{
735	719	sx = ((m_bgscrollx[layer] + 15 + layer * 4) << 16) + ((255 - (m_ctrl[0x10 + layer] & 0xff)) << 8);
736		sx += (m_x_offs - 15 - layer * 4) * zoomx;
	720	sx += (m_x_offset - 15 - layer * 4) * zoomx;
737	721
738	722	y_index = (m_bgscrolly[layer] << 16) + ((m_ctrl[0x14 + layer] & 0xff) << 8);
739	723	y_index -= (m_y_offset - min_y) * zoomy;
r29505	r29506
741	725	else    /* TC0480SCP tiles flipscreen */
742	726	{
743	727	sx = ((-m_bgscrollx[layer] + 15 + layer * 4 + m_flip_xoffs ) << 16) + ((255-(m_ctrl[0x10 + layer] & 0xff)) << 8);
744		sx += (m_x_offs - 15 - layer * 4) * zoomx;
	728	sx += (m_x_offset - 15 - layer * 4) * zoomx;
745	729
746	730	y_index = ((-m_bgscrolly[layer] + m_flip_yoffs) << 16) + ((m_ctrl[0x14 + layer] & 0xff) << 8);
747	731	y_index -= (m_y_offset - min_y) * zoomy;
r29505	r29506
875	859	if (!flipscreen)
876	860	{
877	861	sx = ((m_bgscrollx[layer] + 15 + layer * 4) << 16) + ((255-(m_ctrl[0x10 + layer] & 0xff)) << 8);
878		sx += (m_x_offs - 15 - layer * 4) * zoomx;
	862	sx += (m_x_offset - 15 - layer * 4) * zoomx;
879	863
880	864	y_index = (m_bgscrolly[layer] << 16) + ((m_ctrl[0x14 + layer] & 0xff) << 8);
881	865	y_index -= (m_y_offset - min_y) * zoomy;
r29505	r29506
883	867	else    /* TC0480SCP tiles flipscreen */
884	868	{
885	869	sx = ((-m_bgscrollx[layer] + 15 + layer * 4 + m_flip_xoffs ) << 16) + ((255 - (m_ctrl[0x10 + layer] & 0xff)) << 8);
886		sx += (m_x_offs - 15 - layer * 4) * zoomx;
	870	sx += (m_x_offset - 15 - layer * 4) * zoomx;
887	871
888	872	y_index = ((-m_bgscrolly[layer] + m_flip_yoffs) << 16) + ((m_ctrl[0x14 + layer] & 0xff) << 8);
889	873	y_index -= (m_y_offset - min_y) * zoomy;
r29505	r29506
915	899	x_index = sx - ((m_bgscroll_ram[layer][row_index] << 16)) - ((m_bgscroll_ram[layer][row_index + 0x800] << 8) & 0xffff);
916	900
917	901	/* flawed calc ?? */
918		x_index -= (m_x_offs - 0x1f + layer * 4) * ((row_zoom & 0xff) << 8);
	902	x_index -= (m_x_offset - 0x1f + layer * 4) * ((row_zoom & 0xff) << 8);
919	903
920	904	/* We used to kludge 270 multiply factor, before adjusting x_index instead */
921	905

branches/new_menus/src/mame/video/tc0480scp.h

r29505	r29506
1	1	#ifndef __TC0480SCP_H__
2	2	#define __TC0480SCP_H__
3	3
4		struct tc0480scp_interface
	4	class tc0480scp_device : public device_t
5	5	{
6		int                m_gfxnum;
7		int                m_txnum;
8
9		int                m_pixels;
10
11		int                m_x_offset, m_y_offset;
12		int                m_text_xoffs, m_text_yoffs;
13		int                m_flip_xoffs, m_flip_yoffs;
14
15		int                m_col_base;
16		};
17
18		class tc0480scp_device : public device_t,
19		public tc0480scp_interface
20		{
21	6	public:
22	7	tc0480scp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
23	8	~tc0480scp_device() {}
r29505	r29506
25	10	// static configuration
26	11	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
27	12	static void static_set_palette_tag(device_t &device, const char *tag);
28
	13	static void set_gfx_region(device_t &device, int gfxregion) { downcast<tc0480scp_device &>(device).m_gfxnum = gfxregion; }
	14	static void set_tx_region(device_t &device, int txregion) { downcast<tc0480scp_device &>(device).m_txnum = txregion; }
	15	static void set_col_base(device_t &device, int col) { downcast<tc0480scp_device &>(device).m_col_base = col; }
	16	static void set_offsets(device_t &device, int x_offset, int y_offset)
	17	{
	18	tc0480scp_device &dev = downcast<tc0480scp_device &>(device);
	19	dev.m_x_offset = x_offset;
	20	dev.m_y_offset = y_offset;
	21	}
	22	static void set_offsets_tx(device_t &device, int x_offset, int y_offset)
	23	{
	24	tc0480scp_device &dev = downcast<tc0480scp_device &>(device);
	25	dev.m_text_xoffs = x_offset;
	26	dev.m_text_yoffs = y_offset;
	27	}
	28	static void set_offsets_flip(device_t &device, int x_offset, int y_offset)
	29	{
	30	tc0480scp_device &dev = downcast<tc0480scp_device &>(device);
	31	dev.m_flip_xoffs = x_offset;
	32	dev.m_flip_yoffs = y_offset;
	33	}
	34
29	35	/* When writing a driver, pass zero for the text and flip offsets initially:
30	36	then tweak them once you have the 4 bg layer positions correct. Col_base
31	37	may be needed when tilemaps use a palette area from sprites. */
r29505	r29506
56	62
57	63	protected:
58	64	// device-level overrides
59		virtual void device_config_complete();
60	65	virtual void device_start();
61	66	virtual void device_reset();
62	67
r29505	r29506
76	81	int              m_pri_reg;
77	82
78	83	/* We keep two tilemaps for each of the 5 actual tilemaps: one at standard width, one double */
79		tilemap_t         *m_tilemap[5][2];
80		INT32           m_dblwidth;
81		int             m_x_offs;
	84	tilemap_t        *m_tilemap[5][2];
	85	INT32            m_dblwidth;
82	86
	87	int              m_gfxnum;
	88	int              m_txnum;
	89	int              m_x_offset, m_y_offset;
	90	int              m_text_xoffs, m_text_yoffs;
	91	int              m_flip_xoffs, m_flip_yoffs;
	92
	93	int              m_col_base;
	94
83	95	required_device<gfxdecode_device> m_gfxdecode;
84	96	required_device<palette_device> m_palette;
85	97
r29505	r29506
100	112
101	113	extern const device_type TC0480SCP;
102	114
103		#define MCFG_TC0480SCP_ADD(_tag, _interface) \
104		MCFG_DEVICE_ADD(_tag, TC0480SCP, 0) \
105		MCFG_DEVICE_CONFIG(_interface)
106	115
	116	#define MCFG_TC0480SCP_GFX_REGION(_region) \
	117	tc0480scp_device::set_gfx_region(*device, _region);
	118
	119	#define MCFG_TC0480SCP_TX_REGION(_region) \
	120	tc0480scp_device::set_tx_region(*device, _region);
	121
	122	#define MCFG_TC0480SCP_OFFSETS(_xoffs, _yoffs) \
	123	tc0480scp_device::set_offsets(*device, _xoffs, _yoffs);
	124
	125	#define MCFG_TC0480SCP_OFFSETS_TX(_xoffs, _yoffs) \
	126	tc0480scp_device::set_offsets_tx(*device, _xoffs, _yoffs);
	127
	128	#define MCFG_TC0480SCP_OFFSETS_FLIP(_xoffs, _yoffs) \
	129	tc0480scp_device::set_offsets_flip(*device, _xoffs, _yoffs);
	130
	131	#define MCFG_TC0480SCP_COL_BASE(_col) \
	132	tc0480scp_device::set_col_base(*device, _col);
	133
107	134	#define MCFG_TC0480SCP_GFXDECODE(_gfxtag) \
108	135	tc0480scp_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
109	136

branches/new_menus/src/mame/video/tc0150rod.c

r29505	r29506
11	11
12	12	#define TC0150ROD_RAM_SIZE 0x2000
13	13
14
15
16	14	const device_type TC0150ROD = &device_creator<tc0150rod_device>;
17	15
18	16	tc0150rod_device::tc0150rod_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
r29505	r29506
22	20	}
23	21
24	22	//-------------------------------------------------
25		//  device_config_complete - perform any
26		//  operations now that the configuration is
27		//  complete
28		//-------------------------------------------------
29
30		void tc0150rod_device::device_config_complete()
31		{
32		// inherit a copy of the static data
33		const tc0150rod_interface *intf = reinterpret_cast<const tc0150rod_interface *>(static_config());
34		if (intf != NULL)
35		*static_cast<tc0150rod_interface *>(this) = *intf;
36
37		// or initialize to defaults if none provided
38		else
39		{
40		}
41		}
42
43		//-------------------------------------------------
44	23	//  device_start - device-specific startup
45	24	//-------------------------------------------------
46	25
47	26	void tc0150rod_device::device_start()
48	27	{
49	28	m_ram = auto_alloc_array_clear(machine(), UINT16, TC0150ROD_RAM_SIZE / 2);
50
51	29	save_pointer(NAME(m_ram), TC0150ROD_RAM_SIZE / 2);
	30
	31	m_roadgfx = (UINT16 *)machine().root_device().memregion(m_gfx_region)->base();
	32	assert(m_roadgfx);
52	33	}
53	34
54	35
r29505	r29506
240	221	UINT16 roada_line[512], roadb_line[512];
241	222	UINT16 *dst16;
242	223	UINT16 *roada, *roadb;
243		UINT16 *roadgfx = (UINT16 *)machine().root_device().memregion(m_gfx_region)->base();
244	224
245	225	UINT16 pixel, color, gfx_word;
246	226	UINT16 roada_clipl, roada_clipr, roada_bodyctrl;
r29505	r29506
434	414	{
435	415	if (road_gfx_tilenum)   /* fixes Nightstr round C */
436	416	{
437		gfx_word = roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
	417	gfx_word = m_roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
438	418	pixel = ((gfx_word >> (7 - (x_index % 8) + 8)) & 0x1) * 2 + ((gfx_word >> (7 - (x_index % 8))) & 0x1);
439	419
440	420	if ((pixel) || !(road_trans))
r29505	r29506
485	465	{
486	466	for (i = left_edge; i >= 0; i--)
487	467	{
488		gfx_word = roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
	468	gfx_word = m_roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
489	469	pixel = ((gfx_word >> (7 - (x_index % 8) + 8)) & 0x1) * 2 + ((gfx_word >> (7 - (x_index % 8))) & 0x1);
490	470
491	471	pixpri = (pixel == 0) ? (0) : (pri);    /* off edge has low priority */
r29505	r29506
528	508	{
529	509	for (i = right_edge; i < screen_width; i++)
530	510	{
531		gfx_word = roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
	511	gfx_word = m_roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
532	512	pixel = ((gfx_word >> (7 - (x_index % 8) + 8)) & 0x1) * 2 + ((gfx_word >> (7 - (x_index % 8))) & 0x1);
533	513
534	514	pixpri = (pixel == 0) ? (0) : (pri);    /* off edge has low priority */
r29505	r29506
642	622	{
643	623	for (i = begin; i < end; i++)
644	624	{
645		gfx_word = roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
	625	gfx_word = m_roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
646	626	pixel = ((gfx_word >> (7 - (x_index % 8) + 8)) & 0x1) * 2 + ((gfx_word >> (7 - (x_index % 8))) & 0x1);
647	627
648	628	if ((pixel) || !(road_trans))
r29505	r29506
692	672	{
693	673	for (i = left_edge; i >= 0; i--)
694	674	{
695		gfx_word = roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
	675	gfx_word = m_roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
696	676	pixel = ((gfx_word >> (7 - (x_index % 8) + 8)) & 0x1) * 2 + ((gfx_word >> (7 - (x_index % 8))) & 0x1);
697	677
698	678	pixpri = (pixel == 0) ? (0) : (pri);    /* off edge has low priority */
r29505	r29506
735	715	{
736	716	for (i = right_edge; i < screen_width; i++)
737	717	{
738		gfx_word = roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
	718	gfx_word = m_roadgfx[(road_gfx_tilenum << 8) + (x_index >> 3)];
739	719	pixel = ((gfx_word >> (7 - (x_index % 8) + 8)) & 0x1) * 2 + ((gfx_word >> (7 - (x_index % 8))) & 0x1);
740	720
741	721	pixpri = (pixel == 0) ? (0) : (pri);    /* off edge has low priority */

branches/new_menus/src/mame/video/tc0150rod.h

r29505	r29506
1	1	#ifndef __TC0150ROD_H__
2	2	#define __TC0150ROD_H__
3	3
4		struct tc0150rod_interface
	4	class tc0150rod_device : public device_t
5	5	{
6		const char      *m_gfx_region;    /* gfx region for the road */
7		};
8
9		class tc0150rod_device : public device_t,
10		public tc0150rod_interface
11		{
12	6	public:
13	7	tc0150rod_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
14	8	~tc0150rod_device() {}
15	9
	10	static void set_gfx_tag(device_t &device, const char *tag) { downcast<tc0150rod_device &>(device).m_gfx_region = tag; }
	11
16	12	DECLARE_READ16_MEMBER( word_r );
17	13	DECLARE_WRITE16_MEMBER( word_w );
18	14	void draw(bitmap_ind16 &bitmap, const rectangle &cliprect, int y_offs, int palette_offs, int type, int road_trans, bitmap_ind8 &priority_bitmap, UINT32 low_priority, UINT32 high_priority);
19	15
20	16	protected:
21	17	// device-level overrides
22		virtual void device_config_complete();
23	18	virtual void device_start();
24	19
25	20	private:
26	21	// internal state
27	22	UINT16 *        m_ram;
	23	const char      *m_gfx_region;    /* gfx region for the road */
	24	UINT16 *        m_roadgfx;
28	25	};
29	26
30	27	extern const device_type TC0150ROD;
31	28
32		#define MCFG_TC0150ROD_ADD(_tag, _interface) \
33		MCFG_DEVICE_ADD(_tag, TC0150ROD, 0) \
34		MCFG_DEVICE_CONFIG(_interface)
35	29
	30	#define MCFG_TC0150ROD_GFXTAG(_tag) \
	31	tc0150rod_device::set_gfx_tag(*device, _tag);
	32
36	33	#endif

branches/new_menus/src/mame/video/c45.c

r29505	r29506
46	46	const device_type NAMCO_C45_ROAD = &device_creator<namco_c45_road_device>;
47	47
48	48
49		const gfx_layout namco_c45_road_device::s_tile_layout =
	49	const gfx_layout namco_c45_road_device::tilelayout =
50	50	{
51	51	ROAD_TILE_SIZE, ROAD_TILE_SIZE,
52		ROAD_TILE_COUNT_MAX,
	52	RGN_FRAC(1,1),
53	53	2,
54	54	{ 0, 8 },
55		{// x offset
56		0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
57		0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17
58		},
59		{// y offset
60		0x000,0x020,0x040,0x060,0x080,0x0a0,0x0c0,0x0e0,
61		0x100,0x120,0x140,0x160,0x180,0x1a0,0x1c0,0x1e0
62		},
	55	{ STEP8(0, 1), STEP8(16, 1) },
	56	{ STEP16(0, 32) },
63	57	0x200 // offset to next tile
64	58	};
65	59
	60
	61	GFXDECODE_MEMBER( namco_c45_road_device::gfxinfo )
	62	GFXDECODE_DEVICE_RAM( "tileram", 0, tilelayout, 0xf00, 64 )
	63	GFXDECODE_END
	64
	65
	66	DEVICE_ADDRESS_MAP_START(map, 16, namco_c45_road_device)
	67	AM_RANGE(0x00000, 0x0ffff) AM_RAM_WRITE(tilemap_w) AM_SHARE("tmapram")
	68	AM_RANGE(0x10000, 0x1f9ff) AM_RAM_WRITE(tileram_w) AM_SHARE("tileram")
	69	AM_RANGE(0x1fa00, 0x1ffff) AM_RAM AM_SHARE("lineram")
	70	ADDRESS_MAP_END
	71
	72
66	73	//-------------------------------------------------
67	74	//  namco_c45_road_device -- constructor
68	75	//-------------------------------------------------
69	76
70	77	namco_c45_road_device::namco_c45_road_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
71	78	: device_t(mconfig, NAMCO_C45_ROAD, "Namco C45 Road", tag, owner, clock, "namco_c45_road", __FILE__),
72		m_transparent_color(~0),
73		m_tilemap(NULL),
74		m_gfxdecode(*this, "gfxdecode"),
75		m_palette(*this)
	79	device_gfx_interface(mconfig, *this, gfxinfo),
	80	device_memory_interface(mconfig, *this),
	81	m_space_config("c45", ENDIANNESS_BIG, 16, 17, 0, address_map_delegate(FUNC(namco_c45_road_device::map), this)),
	82	m_tmapram(*this, "tmapram"),
	83	m_tileram(*this, "tileram"),
	84	m_lineram(*this, "lineram"),
	85	m_transparent_color(~0)
76	86	{
77	87	}
78	88
	89
	90
	91	// We need these trampolines for now because uplift_submaps()
	92	// can't deal with address maps that contain RAM.
	93	// We need to explicitly use device_memory_interface::space()
	94	// because read/write handlers have a parameter called 'space'
	95
79	96	//-------------------------------------------------
80		//  read -- read from RAM
	97	//  read -- CPU read from our address space
81	98	//-------------------------------------------------
82	99
83	100	READ16_MEMBER( namco_c45_road_device::read )
84	101	{
85		return m_ram[offset];
	102	return device_memory_interface::space().read_word(offset*2);
86	103	}
87	104
88	105
89	106	//-------------------------------------------------
90		//  write -- write to RAM
	107	//  write -- CPU write to our address space
91	108	//-------------------------------------------------
92	109
93	110	WRITE16_MEMBER( namco_c45_road_device::write )
94	111	{
95		COMBINE_DATA(&m_ram[offset]);
	112	device_memory_interface::space().write_word(offset*2, data, mem_mask);
	113	}
96	114
97		// first half maps to the tilemap
98		if (offset < 0x10000/2)
99		m_tilemap->mark_tile_dirty(offset);
100	115
101		// second half maps to the gfx elements
102		else
103		{
104		offset -= 0x10000/2;
105		m_gfxdecode->gfx(0)->mark_dirty(offset / WORDS_PER_ROAD_TILE);
106		}
	116	//-------------------------------------------------
	117	//  tilemap_w -- write to tilemap RAM
	118	//-------------------------------------------------
	119
	120	WRITE16_MEMBER( namco_c45_road_device::tilemap_w )
	121	{
	122	COMBINE_DATA(&m_tmapram[offset]);
	123	m_tilemap->mark_tile_dirty(offset);
107	124	}
108	125
109	126
110	127	//-------------------------------------------------
	128	//  tileram_w -- write to tile RAM
	129	//-------------------------------------------------
	130
	131	WRITE16_MEMBER( namco_c45_road_device::tileram_w )
	132	{
	133	COMBINE_DATA(&m_tileram[offset]);
	134	gfx(0)->mark_dirty(offset / WORDS_PER_ROAD_TILE);
	135	}
	136
	137
	138	//-------------------------------------------------
111	139	//  draw -- render to the target bitmap
112	140	//-------------------------------------------------
113	141
114	142	void namco_c45_road_device::draw(bitmap_ind16 &bitmap, const rectangle &cliprect, int pri)
115	143	{
116		const UINT8 *clut = (const UINT8 *)memregion("clut")->base();
117	144	bitmap_ind16 &source_bitmap = m_tilemap->pixmap();
118		unsigned yscroll = m_ram[0x1fdfe/2];
	145	unsigned yscroll = m_lineram[0x3fe/2];
119	146
120	147	// loop over scanlines
121	148	for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
122	149	{
123	150	// skip if we are not the right priority
124		int screenx = m_ram[0x1fa00/2 + y + 15];
	151	int screenx = m_lineram[y + 15];
125	152	if (pri != ((screenx & 0xf000) >> 12))
126	153	continue;
127	154
128	155	// skip if we don't have a valid zoom factor
129		unsigned zoomx = m_ram[0x1fe00/2 + y + 15] & 0x3ff;
	156	unsigned zoomx = m_lineram[0x400/2 + y + 15] & 0x3ff;
130	157	if (zoomx == 0)
131	158	continue;
132	159
133	160	// skip if we don't have a valid source increment
134		unsigned sourcey = m_ram[0x1fc00/2 + y + 15] + yscroll;
	161	unsigned sourcey = m_lineram[0x200/2 + y + 15] + yscroll;
135	162	const UINT16 *source_gfx = &source_bitmap.pix(sourcey & (ROAD_TILEMAP_HEIGHT - 1));
136	163	unsigned dsourcex = (ROAD_TILEMAP_WIDTH << 16) / zoomx;
137	164	if (dsourcex == 0)
r29505	r29506
171	198	while (numpixels-- > 0)
172	199	{
173	200	int pen = source_gfx[sourcex >> 16];
174		if (m_palette->pen_indirect(pen) != m_transparent_color)
	201	if (palette()->pen_indirect(pen) != m_transparent_color)
175	202	{
176		if (clut != NULL)
177		pen = (pen & ~0xff) | clut[pen & 0xff];
	203	if (m_clut != NULL)
	204	pen = (pen & ~0xff) | m_clut[pen & 0xff];
178	205	dest[screenx] = pen;
179	206	}
180	207	screenx++;
r29505	r29506
186	213	while (numpixels-- > 0)
187	214	{
188	215	int pen = source_gfx[sourcex >> 16];
189		if (clut != NULL)
190		pen = (pen & ~0xff) | clut[pen & 0xff];
	216	if (m_clut != NULL)
	217	pen = (pen & ~0xff) | m_clut[pen & 0xff];
191	218	dest[screenx++] = pen;
192	219	sourcex += dsourcex;
193	220	}
r29505	r29506
202	229
203	230	void namco_c45_road_device::device_start()
204	231	{
205		if(!m_gfxdecode->started())
206		throw device_missing_dependencies();
	232	m_clut = memregion("clut")->base();
207	233
208		// create a gfx_element describing the road graphics
209		m_gfxdecode->set_gfx(0, global_alloc(gfx_element(m_palette, s_tile_layout, 0x10000 + (UINT8 *)&m_ram[0], NATIVE_ENDIAN_VALUE_LE_BE(8,0), 0x3f, 0xf00)));
210
211	234	// create a tilemap for the road
212		m_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namco_c45_road_device::get_road_info), this),
	235	m_tilemap = &machine().tilemap().create(*this, tilemap_get_info_delegate(FUNC(namco_c45_road_device::get_road_info), this),
213	236	TILEMAP_SCAN_ROWS, ROAD_TILE_SIZE, ROAD_TILE_SIZE, ROAD_COLS, ROAD_ROWS);
214	237	}
215	238
216		MACHINE_CONFIG_FRAGMENT( namco_c45_road )
217		MCFG_GFXDECODE_ADD("gfxdecode", "^palette", empty) // FIXME
218		MACHINE_CONFIG_END
219		//-------------------------------------------------
220		//  device_mconfig_additions - return a pointer to
221		//  the device's machine fragment
222		//-------------------------------------------------
223	239
224		machine_config_constructor namco_c45_road_device::device_mconfig_additions() const
225		{
226		return MACHINE_CONFIG_NAME( namco_c45_road );
227		}
228
229	240	//-------------------------------------------------
230		//  device_stop -- device shutdown
	241	//  memory_space_config - return a description of
	242	//  any address spaces owned by this device
231	243	//-------------------------------------------------
232	244
233		void namco_c45_road_device::device_stop()
	245	const address_space_config *namco_c45_road_device::memory_space_config(address_spacenum spacenum) const
234	246	{
	247	return (spacenum == AS_0) ? &m_space_config : NULL;
235	248	}
236	249
237	250
r29505	r29506
243	256	{
244	257	// ------xx xxxxxxxx tile number
245	258	// xxxxxx-- -------- palette select
246		UINT16 data = m_ram[tile_index];
	259	UINT16 data = m_tmapram[tile_index];
247	260	int tile = data & 0x3ff;
248	261	int color = data >> 10;
249	262	SET_TILE_INFO_MEMBER(0, tile, color, 0);
250	263	}
251
252		//-------------------------------------------------
253		//  static_set_palette_tag: Set the tag of the
254		//  palette device
255		//-------------------------------------------------
256
257		void namco_c45_road_device::static_set_palette_tag(device_t &device, const char *tag)
258		{
259		downcast<namco_c45_road_device &>(device).m_palette.set_tag(tag);
260		}

branches/new_menus/src/mame/video/tc0180vcu.c

r29505	r29506
19	19	//m_tx_rambank(0),
20	20	m_framebuffer_page(0),
21	21	m_video_control(0),
	22	m_bg_color_base(0),
	23	m_fg_color_base(0),
	24	m_tx_color_base(0),
22	25	m_gfxdecode(*this)
23	26	{
24	27	}
r29505	r29506
33	36	downcast<tc0180vcu_device &>(device).m_gfxdecode.set_tag(tag);
34	37	}
35	38
36
37	39	//-------------------------------------------------
38		//  device_config_complete - perform any
39		//  operations now that the configuration is
40		//  complete
41		//-------------------------------------------------
42
43		void tc0180vcu_device::device_config_complete()
44		{
45		// inherit a copy of the static data
46		const tc0180vcu_interface *intf = reinterpret_cast<const tc0180vcu_interface *>(static_config());
47		if (intf != NULL)
48		*static_cast<tc0180vcu_interface *>(this) = *intf;
49
50		// or initialize to defaults if none provided
51		else
52		{
53		}
54		}
55
56		//-------------------------------------------------
57	40	//  device_start - device-specific startup
58	41	//-------------------------------------------------
59	42

branches/new_menus/src/mame/video/c45.h

r29505	r29506
11	11	#define MCFG_NAMCO_C45_ROAD_ADD(_tag) \
12	12	MCFG_DEVICE_ADD(_tag, NAMCO_C45_ROAD, 0)
13	13
14		#define MCFG_NAMCO_C45_ROAD_PALETTE(_palette_tag) \
15		namco_c45_road_device::static_set_palette_tag(*device, "^" _palette_tag);
16	14
17
18	15	//**************************************************************************
19	16	//  TYPE DEFINITIONS
20	17	//**************************************************************************
r29505	r29506
22	19
23	20	// ======================> namco_c45_road_device
24	21
25		class namco_c45_road_device : public device_t
	22	class namco_c45_road_device : public device_t, public device_gfx_interface, public device_memory_interface
26	23	{
27	24	// constants
28	25	static const int ROAD_COLS = 64;
r29505	r29506
30	27	static const int ROAD_TILE_SIZE = 16;
31	28	static const int ROAD_TILEMAP_WIDTH = ROAD_TILE_SIZE * ROAD_COLS;
32	29	static const int ROAD_TILEMAP_HEIGHT = ROAD_TILE_SIZE * ROAD_ROWS;
33		static const int ROAD_TILE_COUNT_MAX = 0xfa00 / 0x40; // 0x3e8
34	30	static const int WORDS_PER_ROAD_TILE = 0x40/2;
	31	static const gfx_layout tilelayout;
35	32
36	33	public:
37	34	// construction/destruction
38	35	namco_c45_road_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
39	36
40		static void static_set_palette_tag(device_t &device, const char *tag);
	37	DECLARE_ADDRESS_MAP(map, 16);
41	38
42	39	// read/write handlers
43	40	DECLARE_READ16_MEMBER( read );
44	41	DECLARE_WRITE16_MEMBER( write );
45	42
46		// optional information overrides
47		virtual machine_config_constructor device_mconfig_additions() const;
48
49	43	// C45 Land (Road) Emulation
50	44	void set_transparent_color(pen_t pen) { m_transparent_color = pen; }
51	45	void draw(bitmap_ind16 &bitmap, const rectangle &cliprect, int pri);
r29505	r29506
53	47	protected:
54	48	// device-level overrides
55	49	virtual void device_start();
56		virtual void device_stop();
	50	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
57	51
	52	private:
58	53	// internal helpers
	54	DECLARE_GFXDECODE_MEMBER(gfxinfo);
	55	DECLARE_WRITE16_MEMBER( tilemap_w );
	56	DECLARE_WRITE16_MEMBER( tileram_w );
59	57	TILE_GET_INFO_MEMBER( get_road_info );
60	58
61	59	// internal state
62		pen_t           m_transparent_color;
63		tilemap_t *     m_tilemap;
64		UINT16          m_ram[0x20000/2]; // at 0x880000 in Final Lap; at 0xa00000 in Lucky&Wild
65
66		static const gfx_layout s_tile_layout;
67		required_device<gfxdecode_device> m_gfxdecode;
68		required_device<palette_device> m_palette;
	60	address_space_config        m_space_config;
	61	required_shared_ptr<UINT16> m_tmapram;
	62	required_shared_ptr<UINT16> m_tileram;
	63	required_shared_ptr<UINT16> m_lineram;
	64	UINT8 *                     m_clut;
	65	tilemap_t *                 m_tilemap;
	66	pen_t                       m_transparent_color;
69	67	};
70	68
71	69

branches/new_menus/src/mame/video/tc0180vcu.h

r29505	r29506
1		#ifndef _TC0180VCU_H_
2		#define _TC0180VCU_H_
	1	#ifndef __TC0180VCU_H__
	2	#define __TC0180VCU_H__
3	3
4		struct tc0180vcu_interface
	4	class tc0180vcu_device : public device_t
5	5	{
6		int            m_bg_color_base;
7		int            m_fg_color_base;
8		int            m_tx_color_base;
9		};
10
11		class tc0180vcu_device : public device_t,
12		public tc0180vcu_interface
13		{
14	6	public:
15	7	tc0180vcu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
16	8	~tc0180vcu_device() {}
17	9
18	10	// static configuration
19	11	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
	12	static void set_bg_colorbase(device_t &device, int color) { downcast<tc0180vcu_device &>(device).m_bg_color_base = color; }
	13	static void set_fg_colorbase(device_t &device, int color) { downcast<tc0180vcu_device &>(device).m_fg_color_base = color; }
	14	static void set_tx_colorbase(device_t &device, int color) { downcast<tc0180vcu_device &>(device).m_tx_color_base = color; }
20	15
21	16	DECLARE_READ8_MEMBER( get_fb_page );
22	17	DECLARE_WRITE8_MEMBER( set_fb_page );
r29505	r29506
31	26
32	27	protected:
33	28	// device-level overrides
34		virtual void device_config_complete();
35	29	virtual void device_start();
36	30	virtual void device_reset();
37	31
38		private:
	32	private:
39	33	// internal state
40	34	UINT16         m_ctrl[0x10];
41	35
r29505	r29506
47	41	UINT16         m_bg_rambank[2], m_fg_rambank[2], m_tx_rambank;
48	42	UINT8          m_framebuffer_page;
49	43	UINT8          m_video_control;
	44
	45	int            m_bg_color_base;
	46	int            m_fg_color_base;
	47	int            m_tx_color_base;
	48
50	49	required_device<gfxdecode_device> m_gfxdecode;
51	50
52	51	TILE_GET_INFO_MEMBER(get_bg_tile_info);
r29505	r29506
58	57
59	58	extern const device_type TC0180VCU;
60	59
61		#define MCFG_TC0180VCU_ADD(_tag, _interface) \
62		MCFG_DEVICE_ADD(_tag, TC0180VCU, 0) \
63		MCFG_DEVICE_CONFIG(_interface)
	60	#define MCFG_TC0180VCU_BG_COLORBASE(_color) \
	61	tc0180vcu_device::set_bg_colorbase(*device, _color);
64	62
	63	#define MCFG_TC0180VCU_FG_COLORBASE(_color) \
	64	tc0180vcu_device::set_fg_colorbase(*device, _color);
	65
	66	#define MCFG_TC0180VCU_TX_COLORBASE(_color) \
	67	tc0180vcu_device::set_tx_colorbase(*device, _color);
	68
65	69	#define MCFG_TC0180VCU_GFXDECODE(_gfxtag) \
66	70	tc0180vcu_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
	71
67	72	#endif

branches/new_menus/src/mame/video/toaplan_scu.c

r29505	r29506
10	10
11	11	const device_type TOAPLAN_SCU = &device_creator<toaplan_scu_device>;
12	12
13		static const gfx_layout spritelayout =
	13	const gfx_layout toaplan_scu_device::spritelayout =
14	14	{
15	15	16,16,          /* 16*16 sprites */
16	16	RGN_FRAC(1,4),
r29505	r29506
21	21	16*16
22	22	};
23	23
24		static GFXDECODE_START( toaplan_scu )
	24	GFXDECODE_MEMBER( toaplan_scu_device::gfxinfo )
25	25	GFXDECODE_DEVICE( DEVICE_SELF, 0, spritelayout, 0, 64 )
26	26	GFXDECODE_END
27	27
28	28
29	29	toaplan_scu_device::toaplan_scu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
30	30	: device_t(mconfig, TOAPLAN_SCU, "toaplan_scu_device", tag, owner, clock, "toaplan_scu", __FILE__),
31		device_gfx_interface(mconfig, *this, GFXDECODE_NAME( toaplan_scu ))
	31	device_gfx_interface(mconfig, *this, gfxinfo )
32	32	{
33	33	}
34	34

branches/new_menus/src/mame/video/toaplan_scu.h

r29505	r29506
4	4
5	5	class toaplan_scu_device : public device_t, public device_gfx_interface
6	6	{
	7	static const gfx_layout spritelayout;
	8	DECLARE_GFXDECODE_MEMBER(gfxinfo);
	9
7	10	public:
8	11	toaplan_scu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
9	12

branches/new_menus/src/mame/video/pc080sn.c

r29505	r29506
52	52	pc080sn_device::pc080sn_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
53	53	: device_t(mconfig, PC080SN, "Taito PC080SN", tag, owner, clock, "pc080sn", __FILE__),
54	54	m_ram(NULL),
	55	m_gfxnum(0),
	56	m_x_offset(0),
	57	m_y_offset(0),
	58	m_y_invert(0),
	59	m_dblwidth(0),
55	60	m_gfxdecode(*this),
56	61	m_palette(*this)
57	62	//m_bg_ram[0](NULL),
r29505	r29506
82	87	}
83	88
84	89	//-------------------------------------------------
85		//  device_config_complete - perform any
86		//  operations now that the configuration is
87		//  complete
88		//-------------------------------------------------
89
90		void pc080sn_device::device_config_complete()
91		{
92		// inherit a copy of the static data
93		const pc080sn_interface *intf = reinterpret_cast<const pc080sn_interface *>(static_config());
94		if (intf != NULL)
95		*static_cast<pc080sn_interface *>(this) = *intf;
96
97		// or initialize to defaults if none provided
98		else
99		{
100		}
101		}
102
103		//-------------------------------------------------
104	90	//  device_start - device-specific startup
105	91	//-------------------------------------------------
106	92

branches/new_menus/src/mame/video/pc080sn.h

r29505	r29506
1	1	#ifndef __PC080SN_H__
2	2	#define __PC080SN_H__
3	3
4		struct pc080sn_interface
	4	class pc080sn_device : public device_t
5	5	{
6		int                m_gfxnum;
7
8		int                m_x_offset, m_y_offset;
9		int                m_y_invert;
10		int                m_dblwidth;
11		};
12
13		class pc080sn_device : public device_t,
14		public pc080sn_interface
15		{
16	6	public:
17	7	pc080sn_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
18	8	~pc080sn_device() {}
r29505	r29506
20	10	// static configuration
21	11	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
22	12	static void static_set_palette_tag(device_t &device, const char *tag);
23
	13	static void set_gfx_region(device_t &device, int gfxregion) { downcast<pc080sn_device &>(device).m_gfxnum = gfxregion; }
	14	static void set_yinvert(device_t &device, int y_inv) { downcast<pc080sn_device &>(device).m_y_invert = y_inv; }
	15	static void set_dblwidth(device_t &device, int dblwidth) { downcast<pc080sn_device &>(device).m_dblwidth = dblwidth; }
	16	static void set_offsets(device_t &device, int x_offset, int y_offset)
	17	{
	18	pc080sn_device &dev = downcast<pc080sn_device &>(device);
	19	dev.m_x_offset = x_offset;
	20	dev.m_y_offset = y_offset;
	21	}
	22
24	23	DECLARE_READ16_MEMBER( word_r );
25	24	DECLARE_WRITE16_MEMBER( word_w );
26	25	DECLARE_WRITE16_MEMBER( xscroll_word_w );
r29505	r29506
48	47
49	48	protected:
50	49	// device-level overrides
51		virtual void device_config_complete();
52	50	virtual void device_start();
53	51
54	52	private:
r29505	r29506
62	60	int            m_bgscrollx[2], m_bgscrolly[2];
63	61
64	62	tilemap_t      *m_tilemap[2];
	63
	64	int            m_gfxnum;
	65	int            m_x_offset, m_y_offset;
	66	int            m_y_invert;
	67	int            m_dblwidth;
	68
65	69	required_device<gfxdecode_device> m_gfxdecode;
66	70	required_device<palette_device> m_palette;
67	71	};
68	72
69	73	extern const device_type PC080SN;
70	74
71		#define MCFG_PC080SN_ADD(_tag, _interface) \
72		MCFG_DEVICE_ADD(_tag, PC080SN, 0) \
73		MCFG_DEVICE_CONFIG(_interface)
74	75
	76	#define MCFG_PC080SN_GFX_REGION(_region) \
	77	pc080sn_device::set_gfx_region(*device, _region);
	78
	79	#define MCFG_PC080SN_OFFSETS(_xoffs, _yoffs) \
	80	pc080sn_device::set_offsets(*device, _xoffs, _yoffs);
	81
	82	#define MCFG_PC080SN_YINVERT(_yinv) \
	83	pc080sn_device::set_yinvert(*device, _yinv);
	84
	85	#define MCFG_PC080SN_DBLWIDTH(_dbl) \
	86	pc080sn_device::set_dblwidth(*device, _dbl);
	87
75	88	#define MCFG_PC080SN_GFXDECODE(_gfxtag) \
76	89	pc080sn_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
77	90

branches/new_menus/src/mame/video/decospr.c

r29505	r29506
131	131	#include "emu.h"
132	132	#include "decospr.h"
133	133
134		UINT16 decospr_default_colour_callback(UINT16 col)
	134	DECOSPR_COLOUR_CB_MEMBER(decospr_device::default_col_cb)
135	135	{
136	136	return (col >> 9) & 0x1f;
137	137	}
r29505	r29506
143	143	//  printf("decospr_device::set_gfx_region()\n");
144	144	}
145	145
146		void decospr_device::set_pri_callback(device_t &device, decospr_priority_callback_func callback)
147		{
148		decospr_device &dev = downcast<decospr_device &>(device);
149		dev.m_pricallback = callback;
150		}
151
152		void decospr_device::set_col_callback(device_t &device, decospr_colour_callback_func callback)
153		{
154		decospr_device &dev = downcast<decospr_device &>(device);
155		dev.m_colcallback = callback;
156		}
157
158
159
160	146	const device_type DECO_SPRITE = &device_creator<decospr_device>;
161	147
162	148	decospr_device::decospr_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
163	149	: device_t(mconfig, DECO_SPRITE, "decospr_device", tag, owner, clock, "decospr", __FILE__),
164	150	device_video_interface(mconfig, *this),
165	151	m_gfxregion(0),
166		m_pricallback(NULL),
167		m_colcallback(decospr_default_colour_callback),
168	152	m_is_bootleg(false),
169	153	m_x_offset(0),
170	154	m_y_offset(0),
r29505	r29506
173	157	m_gfxdecode(*this),
174	158	m_palette(*this)
175	159	{
	160	// default color callback
	161	m_col_cb =  decospr_col_cb_delegate(FUNC(decospr_device::default_col_cb), this);
176	162	}
177	163
178	164	//-------------------------------------------------
r29505	r29506
187	173
188	174	void decospr_device::device_start()
189	175	{
190		//  printf("decospr_device::device_start()\n");
	176	m_pri_cb.bind_relative_to(*owner());
	177	m_col_cb.bind_relative_to(*owner());
	178
191	179	m_alt_format = 0;
192	180	m_pixmask = 0xf;
193	181	m_raw_shift = 4; // set to 8 on tattass / nslashers for the custom mixing (because they have 5bpp sprites, and shifting by 4 isn't good enough)
r29505	r29506
203	191	m_screen->register_screen_bitmap(m_sprite_bitmap);
204	192	}
205	193
206		void decospr_device::set_pri_callback(decospr_priority_callback_func callback)
207		{
208		m_pricallback = callback;
209		}
210
211		void decospr_device::set_col_callback(decospr_priority_callback_func callback)
212		{
213		m_colcallback = callback;
214		}
215
216
217	194	template<class _BitmapClass>
218	195	void decospr_device::draw_sprites_common(_BitmapClass &bitmap, const rectangle &cliprect, UINT16* spriteram, int sizewords, bool invert_flip )
219	196	{
220	197	//printf("cliprect %04x, %04x\n", cliprect.min_y, cliprect.max_y);
221	198
222		if (m_sprite_bitmap.valid() && m_pricallback)
223		fatalerror("m_sprite_bitmap && m_pricallback is invalid\n");
	199	if (m_sprite_bitmap.valid() && !m_pri_cb.isnull())
	200	fatalerror("m_sprite_bitmap && m_pri_cb is invalid\n");
224	201
225	202	if (m_sprite_bitmap.valid())
226	203	m_sprite_bitmap.fill(0, cliprect);
r29505	r29506
234	211	flipscreen = !flipscreen;
235	212
236	213
237		if (m_pricallback)
	214	if (!m_pri_cb.isnull())
238	215	{
239	216	offs = sizewords-4;
240	217	end = -4;
r29505	r29506
265	242
266	243	if (!m_sprite_bitmap.valid())
267	244	{
268		colour = m_colcallback(x);
	245	colour = m_col_cb(x);
269	246	}
270	247	else
271	248	{
r29505	r29506
274	251	}
275	252
276	253
277		if (m_pricallback)
278		pri = m_pricallback(x);
	254	if (!m_pri_cb.isnull())
	255	pri = m_pri_cb(x);
279	256	else
280	257	pri = 0;
281	258
r29505	r29506
355	332	{
356	333	if ((ypos<=cliprect.max_y) && (ypos>=(cliprect.min_y)-16))
357	334	{
358		if (m_pricallback)
	335	if (!m_pri_cb.isnull())
359	336	m_gfxdecode->gfx(m_gfxregion)->prio_transpen(bitmap,cliprect,
360	337	sprite - multi * inc,
361	338	colour,
r29505	r29506
374	351	// double wing uses this flag
375	352	if (w)
376	353	{
377		if (m_pricallback)
	354	if (!m_pri_cb.isnull())
378	355	m_gfxdecode->gfx(m_gfxregion)->prio_transpen(bitmap,cliprect,
379	356	(sprite - multi * inc)-mult2,
380	357	colour,
r29505	r29506
423	400	sprite = spriteram[offs+3] & 0xffff;
424	401
425	402
426		if (m_pricallback)
427		pri = m_pricallback(spriteram[offs+2]&0x00ff);
	403	if (!m_pri_cb.isnull())
	404	pri = m_pri_cb(spriteram[offs+2]&0x00ff);
428	405	else
429	406	pri = 0;
430	407
r29505	r29506
474	451	{
475	452	if(!m_sprite_bitmap.valid())
476	453	{
477		if (m_pricallback)
	454	if (!m_pri_cb.isnull())
478	455	{
479	456	ypos = y + mult2 * (h-yy);
480	457

branches/new_menus/src/mame/video/decospr.h

r29505	r29506
1	1
2		typedef UINT16 (*decospr_priority_callback_func)(UINT16 pri);
3		typedef UINT16 (*decospr_colour_callback_func)(UINT16 col);
	2	typedef device_delegate<UINT16 (UINT16 pri)> decospr_pri_cb_delegate;
	3	typedef device_delegate<UINT16 (UINT16 col)> decospr_col_cb_delegate;
4	4
	5
	6	// function definition for a callback
	7	#define DECOSPR_PRIORITY_CB_MEMBER(_name)   UINT16 _name(UINT16 pri)
	8	#define DECOSPR_COLOUR_CB_MEMBER(_name)     UINT16 _name(UINT16 col)
	9
	10
5	11	class decospr_device : public device_t,
6	12	public device_video_interface
7	13	{
r29505	r29506
12	18	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
13	19	static void static_set_palette_tag(device_t &device, const char *tag);
14	20	static void set_gfx_region(device_t &device, int gfxregion);
15		static void set_pri_callback(device_t &device, decospr_priority_callback_func callback);
16		static void set_col_callback(device_t &device, decospr_colour_callback_func callback);
17
18		static void set_is_bootleg(device_t &device, bool is_bootleg)
19		{
20		decospr_device &dev = downcast<decospr_device &>(device);
21		dev.m_is_bootleg = is_bootleg;
22		}
23
	21	static void set_pri_callback(device_t &device, decospr_pri_cb_delegate callback) { downcast<decospr_device &>(device).m_pri_cb = callback; }
	22	static void set_col_callback(device_t &device, decospr_col_cb_delegate callback) { downcast<decospr_device &>(device).m_col_cb = callback; }
	23	static void set_is_bootleg(device_t &device, bool is_bootleg) { downcast<decospr_device &>(device).m_is_bootleg = is_bootleg; }
	24	static void set_flipallx(device_t &device, int flipallx) { downcast<decospr_device &>(device).m_flipallx = flipallx; }
	25	static void set_transpen(device_t &device, int transpen) { downcast<decospr_device &>(device).m_transpen = transpen; }
24	26	static void set_offsets(device_t &device, int x_offset, int y_offset)
25	27	{
26	28	decospr_device &dev = downcast<decospr_device &>(device);
r29505	r29506
28	30	dev.m_y_offset = y_offset;
29	31	}
30	32
31		static void set_flipallx(device_t &device, int flipallx)
32		{
33		decospr_device &dev = downcast<decospr_device &>(device);
34		dev.m_flipallx = flipallx;
35		}
36
37		static void set_transpen(device_t &device, int transpen)
38		{
39		decospr_device &dev = downcast<decospr_device &>(device);
40		dev.m_transpen = transpen;
41		}
42
43
44	33	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16* spriteram, int sizewords, bool invert_flip = false );
45	34	void draw_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT16* spriteram, int sizewords, bool invert_flip = false );
46		void set_pri_callback(decospr_priority_callback_func callback);
47		void set_col_callback(decospr_colour_callback_func callback);
48		void set_gfxregion(int region) { m_gfxregion = region; };
49	35	void set_alt_format(bool alt) { m_alt_format = alt; };
50	36	void set_pix_mix_mask(UINT16 mask) { m_pixmask = mask; };
51	37	void set_pix_raw_shift(UINT16 shift) { m_raw_shift = shift; };
52		void set_is_bootleg(bool is_bootleg) { m_is_bootleg = is_bootleg; };
53		void set_offsets(int x_offset, int y_offset) { m_x_offset = x_offset; m_y_offset = y_offset; };
54		void set_flipallx(int flipallx) { m_flipallx = flipallx; };
55		void set_transpen(int transpen) { m_transpen = transpen; };
56	38
57	39	void alloc_sprite_bitmap();
58	40	void inefficient_copy_sprite_bitmap(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT16 pri, UINT16 priority_mask, UINT16 colbase, UINT16 palmask, UINT8 alpha = 0xff);
59	41	bitmap_ind16& get_sprite_temp_bitmap() { assert(m_sprite_bitmap.valid()); return m_sprite_bitmap; };
60	42
	43	DECOSPR_PRIORITY_CB_MEMBER(default_col_cb);
	44
61	45	protected:
62	46	virtual void device_start();
63	47	virtual void device_reset();
64		UINT8                       m_gfxregion;
65		decospr_priority_callback_func m_pricallback;
66		decospr_colour_callback_func m_colcallback;
	48	UINT8 m_gfxregion;
	49	decospr_pri_cb_delegate m_pri_cb;
	50	decospr_col_cb_delegate m_col_cb;
67	51	bitmap_ind16 m_sprite_bitmap;// optional sprite bitmap (should be INDEXED16)
68	52	bool m_alt_format;
69	53	UINT16 m_pixmask;
r29505	r29506
84	68
85	69	extern const device_type DECO_SPRITE;
86	70
	71	#define MCFG_DECO_SPRITE_GFX_REGION(_region) \
	72	decospr_device::set_gfx_region(*device, _region);
	73
	74	#define MCFG_DECO_SPRITE_PRIORITY_CB(_class, _method) \
	75	decospr_device::set_pri_callback(*device, decospr_pri_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
	76
	77	#define MCFG_DECO_SPRITE_COLOUR_CB(_class, _method) \
	78	decospr_device::set_col_callback(*device, decospr_col_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
	79
	80	#define MCFG_DECO_SPRITE_ISBOOTLEG(_boot) \
	81	decospr_device::set_is_bootleg(*device, _boot);
	82
	83	#define MCFG_DECO_SPRITE_FLIPALLX(_flip) \
	84	decospr_device::set_flipallx(*device, _flip);
	85
	86	#define MCFG_DECO_SPRITE_TRANSPEN(_pen) \
	87	decospr_device::set_transpen(*device, _pen);
	88
	89	#define MCFG_DECO_SPRITE_OFFSETS(_xoffs, _yoffs) \
	90	decospr_device::set_offsets(*device, _xoffs, _yoffs);
	91
87	92	#define MCFG_DECO_SPRITE_GFXDECODE(_gfxtag) \
88	93	decospr_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
89	94

branches/new_menus/src/mame/video/deco16ic.h

r29505	r29506
206	206	#define MCFG_DECO16IC_PALETTE(_palette_tag) \
207	207	deco16ic_device::static_set_palette_tag(*device, "^" _palette_tag);
208	208
	209	// function definition for a callback
	210	#define DECO16IC_BANK_CB_MEMBER(_name)     int _name(int bank)
	211
209	212	#endif

branches/new_menus/src/mame/video/k053936.c

r29505	r29506
220	220
221	221
222	222
223
224
225
226	223	/***************************************************************************/
227	224	/*                                                                         */
228	225	/*                                 053936                                  */
r29505	r29506
234	231	k053936_device::k053936_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
235	232	: device_t(mconfig, K053936, "Konami 053936", tag, owner, clock, "k053936", __FILE__),
236	233	m_ctrl(NULL),
237		m_linectrl(NULL)
	234	m_linectrl(NULL),
	235	m_wrap(0),
	236	m_xoff(0),
	237	m_yoff(0)
238	238	{
239	239	}
240	240
241	241	//-------------------------------------------------
242		//  device_config_complete - perform any
243		//  operations now that the configuration is
244		//  complete
245		//-------------------------------------------------
246
247		void k053936_device::device_config_complete()
248		{
249		// inherit a copy of the static data
250		const k053936_interface *intf = reinterpret_cast<const k053936_interface *>(static_config());
251		if (intf != NULL)
252		*static_cast<k053936_interface *>(this) = *intf;
253
254		// or initialize to defaults if none provided
255		else
256		{
257		m_wrap = 0;
258		m_xoff = 0;
259		m_yoff = 0;
260		}
261		}
262
263		//-------------------------------------------------
264	242	//  device_start - device-specific startup
265	243	//-------------------------------------------------
266	244

branches/new_menus/src/mame/video/k053936.h

r29505	r29506
3	3	#define __K053936_H__
4	4
5	5
6		/* */
7
8
9		#define MCFG_K053936_ADD(_tag, _interface) \
10		MCFG_DEVICE_ADD(_tag, K053936, 0) \
11		MCFG_DEVICE_CONFIG(_interface)
12
13
14
15	6	void K053936_0_zoom_draw(screen_device &screen, bitmap_ind16 &bitmap,const rectangle &cliprect,tilemap_t *tmap,int flags,UINT32 priority, int glfgreat_hack);
16	7	void K053936_wraparound_enable(int chip, int status);
17	8	void K053936_set_offset(int chip, int xoffs, int yoffs);
r29505	r29506
23	14	void K053936GP_0_zoom_draw(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect, tilemap_t *tmap, int tilebpp, int blend, int alpha, int pixeldouble_output, UINT16* temp_m_k053936_0_ctrl_16, UINT16* temp_m_k053936_0_linectrl_16, UINT16* temp_m_k053936_0_ctrl, UINT16* temp_m_k053936_0_linectrl, palette_device *palette);
24	15
25	16
26
27
28		struct k053936_interface
	17	class k053936_device : public device_t
29	18	{
30		int                m_wrap, m_xoff, m_yoff;
31		};
32
33
34
35		class k053936_device : public device_t,
36		public k053936_interface
37		{
38	19	public:
39	20	k053936_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
40	21	~k053936_device() {}
41	22
	23	// static configuration
	24	static void set_wrap(device_t &device, int wrap) { downcast<k053936_device &>(device).m_wrap = wrap; }
	25	static void set_offsets(device_t &device, int x_offset, int y_offset)
	26	{
	27	k053936_device &dev = downcast<k053936_device &>(device);
	28	dev.m_xoff = x_offset;
	29	dev.m_yoff = y_offset;
	30	}
	31
42	32	DECLARE_WRITE16_MEMBER( ctrl_w );
43	33	DECLARE_READ16_MEMBER( ctrl_r );
44	34	DECLARE_WRITE16_MEMBER( linectrl_w );
r29505	r29506
49	39
50	40	protected:
51	41	// device-level overrides
52		virtual void device_config_complete();
53	42	virtual void device_start();
54	43	virtual void device_reset();
55	44
r29505	r29506
57	46	// internal state
58	47	UINT16    *m_ctrl;
59	48	UINT16    *m_linectrl;
	49	int       m_wrap, m_xoff, m_yoff;
60	50	};
61	51
62	52	extern const device_type K053936;
63	53
	54	#define MCFG_K053936_WRAP(_wrap) \
	55	k053936_device::set_wrap(*device, _wrap);
64	56
	57	#define MCFG_K053936_OFFSETS(_xoffs, _yoffs) \
	58	k053936_device::set_offsets(*device, _xoffs, _yoffs);
65	59
66
67	60	#endif

branches/new_menus/src/mame/video/tc0080vco.c

r29505	r29506
95	95	m_bg1_scrollx(0),
96	96	m_bg1_scrolly(0),
97	97	m_flipscreen(0),
	98	m_gfxnum(0),
	99	m_txnum(0),
	100	m_bg_xoffs(0),
	101	m_bg_yoffs(0),
	102	m_bg_flip_yoffs(0),
	103	m_has_fg0(1),
98	104	m_gfxdecode(*this),
99	105	m_palette(*this)
100	106	{
r29505	r29506
121	127	}
122	128
123	129	//-------------------------------------------------
124		//  device_config_complete - perform any
125		//  operations now that the configuration is
126		//  complete
127		//-------------------------------------------------
128
129		void tc0080vco_device::device_config_complete()
130		{
131		// inherit a copy of the static data
132		const tc0080vco_interface *intf = reinterpret_cast<const tc0080vco_interface *>(static_config());
133		if (intf != NULL)
134		*static_cast<tc0080vco_interface *>(this) = *intf;
135
136		// or initialize to defaults if none provided
137		else
138		{
139		}
140		}
141
142		//-------------------------------------------------
143	130	//  device_start - device-specific startup
144	131	//-------------------------------------------------
145	132

branches/new_menus/src/mame/video/tc0080vco.h

r29505	r29506
1	1	#ifndef __TC0080VCO_H__
2	2	#define __TC0080VCO_H__
3	3
4		struct tc0080vco_interface
	4	class tc0080vco_device : public device_t
5	5	{
6		int                m_gfxnum;
7		int                m_txnum;
8
9		int                m_bg_xoffs, m_bg_yoffs;
10		int                m_bg_flip_yoffs;
11
12		int                m_has_fg0; /* for debug */
13		};
14
15		class tc0080vco_device : public device_t,
16		public tc0080vco_interface
17		{
18	6	public:
19	7	tc0080vco_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
20	8	~tc0080vco_device() {}
r29505	r29506
22	10	// static configuration
23	11	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
24	12	static void static_set_palette_tag(device_t &device, const char *tag);
25
	13	static void set_gfx_region(device_t &device, int gfxnum) { downcast<tc0080vco_device &>(device).m_gfxnum = gfxnum; }
	14	static void set_tx_region(device_t &device, int txnum) { downcast<tc0080vco_device &>(device).m_txnum = txnum; }
	15	static void set_offsets(device_t &device, int x_offset, int y_offset)
	16	{
	17	tc0080vco_device &dev = downcast<tc0080vco_device &>(device);
	18	dev.m_bg_xoffs = x_offset;
	19	dev.m_bg_yoffs = y_offset;
	20	}
	21	static void set_bgflip_yoffs(device_t &device, int offs) { downcast<tc0080vco_device &>(device).m_bg_flip_yoffs = offs; }
	22
26	23	DECLARE_READ16_MEMBER( word_r );
27	24	DECLARE_WRITE16_MEMBER( word_w );
28	25
29	26	void tilemap_update();
30	27	void tilemap_draw(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int layer, int flags, UINT32 priority);
	28	void set_fg0_debug(bool debug) { m_has_fg0 = debug ? 0 : 1; }
31	29
32	30	DECLARE_READ16_MEMBER( cram_0_r );
33	31	DECLARE_READ16_MEMBER( cram_1_r );
r29505	r29506
37	35	READ_LINE_MEMBER( flipscreen_r );
38	36	void postload();
39	37
40		protected:
	38	protected:
41	39	// device-level overrides
42		virtual void device_config_complete();
43	40	virtual void device_start();
44	41
45		private:
	42	private:
46	43	// internal state
47	44	UINT16 *       m_ram;
48	45	UINT16 *       m_bg0_ram_0;
r29505	r29506
54	51	UINT16 *       m_char_ram;
55	52	UINT16 *       m_bgscroll_ram;
56	53
57		/* FIXME: This sprite related stuff still needs to be accessed in
58		video/taito_h */
	54	/* FIXME: This sprite related stuff still needs to be accessed in video/taito_h */
59	55	UINT16 *       m_chain_ram_0;
60	56	UINT16 *       m_chain_ram_1;
61	57	UINT16 *       m_spriteram;
r29505	r29506
66	62	UINT16         m_bg1_scrollx;
67	63	UINT16         m_bg1_scrolly;
68	64
69		tilemap_t        *m_tilemap[3];
	65	tilemap_t      *m_tilemap[3];
70	66
71	67	INT32          m_flipscreen;
	68
	69	int            m_gfxnum;
	70	int            m_txnum;
	71	int            m_bg_xoffs, m_bg_yoffs;
	72	int            m_bg_flip_yoffs;
	73	int            m_has_fg0; // for debug, it can be enabled with set_fg0_debug(true)
	74
72	75	required_device<gfxdecode_device> m_gfxdecode;
73	76	required_device<palette_device> m_palette;
74	77
r29505	r29506
81	84
82	85	extern const device_type TC0080VCO;
83	86
84		#define MCFG_TC0080VCO_ADD(_tag, _interface) \
85		MCFG_DEVICE_ADD(_tag, TC0080VCO, 0) \
86		MCFG_DEVICE_CONFIG(_interface)
	87	#define MCFG_TC0080VCO_GFX_REGION(_region) \
	88	tc0080vco_device::set_gfx_region(*device, _region);
87	89
	90	#define MCFG_TC0080VCO_TX_REGION(_region) \
	91	tc0080vco_device::set_tx_region(*device, _region);
	92
	93	#define MCFG_TC0080VCO_OFFSETS(_xoffs, _yoffs) \
	94	tc0080vco_device::set_offsets(*device, _xoffs, _yoffs);
	95
	96	#define MCFG_TC0080VCO_BGFLIP_OFFS(_offs) \
	97	tc0080vco_device::set_bgflip_yoffs(*device, _offs);
	98
88	99	#define MCFG_TC0080VCO_GFXDECODE(_gfxtag) \
89	100	tc0080vco_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
90	101

branches/new_menus/src/mame/video/vrender0.c

r29505	r29506
24	24	const device_type VIDEO_VRENDER0 = &device_creator<vr0video_device>;
25	25
26	26	vr0video_device::vr0video_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
27		: device_t(mconfig, VIDEO_VRENDER0, "VRender0 Video", tag, owner, clock, "vr0video", __FILE__)
	27	: device_t(mconfig, VIDEO_VRENDER0, "VRender0 Video", tag, owner, clock, "vr0video", __FILE__),
	28	m_cpu(*this)
28	29	{
29	30	}
30	31
31	32	//-------------------------------------------------
32		//  device_config_complete - perform any
33		//  operations now that the configuration is
34		//  complete
35		//-------------------------------------------------
36
37		void vr0video_device::device_config_complete()
38		{
39		// inherit a copy of the static data
40		const vr0video_interface *intf = reinterpret_cast<const vr0video_interface *>(static_config());
41		if (intf != NULL)
42		*static_cast<vr0video_interface *>(this) = *intf;
43
44		// or initialize to defaults if none provided
45		else
46		{
47		m_cpu_tag = "";
48		}
49		}
50
51		//-------------------------------------------------
52	33	//  device_start - device-specific startup
53	34	//-------------------------------------------------
54	35
55	36	void vr0video_device::device_start()
56	37	{
57		m_cpu = machine().device(m_cpu_tag);
58
59	38	save_item(NAME(m_InternalPalette));
60	39	save_item(NAME(m_LastPalUpdate));
61	40
r29505	r29506
418	397	//Returns TRUE if the operation was a flip (sync or async)
419	398	int vr0video_device::vrender0_ProcessPacket(UINT32 PacketPtr, UINT16 *Dest, UINT8 *TEXTURE)
420	399	{
421		address_space &space = m_cpu->memory().space(AS_PROGRAM);
	400	address_space &space = m_cpu->space(AS_PROGRAM);
422	401	UINT32 Dx = Packet(1) & 0x3ff;
423	402	UINT32 Dy = Packet(2) & 0x1ff;
424	403	UINT32 Endx = Packet(3) & 0x3ff;

branches/new_menus/src/mame/video/vrender0.h

r29505	r29506
6	6	TYPE DEFINITIONS
7	7	***************************************************************************/
8	8
9		struct vr0video_interface
10		{
11		const char *m_cpu_tag;
12		};
13
14	9	struct RenderStateInfo
15	10	{
16	11	UINT32 Tx;
r29505	r29506
35	30	UINT32 Height;
36	31	};
37	32
38
39		class vr0video_device : public device_t,
40		vr0video_interface
	33	class vr0video_device : public device_t
41	34	{
42	35	public:
43	36	vr0video_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
r29505	r29506
45	38
46	39	int vrender0_ProcessPacket(UINT32 PacketPtr, UINT16 *Dest, UINT8 *TEXTURE);
47	40
	41	static void set_cpu_tag(device_t &device, const char *tag) { downcast<vr0video_device &>(device).m_cpu.set_tag(tag); }
	42
48	43	protected:
49	44	// device-level overrides
50		virtual void device_config_complete();
51	45	virtual void device_start();
52	46	virtual void device_reset();
53	47
54	48	private:
55	49	// internal state
56		device_t *m_cpu;
	50	required_device<cpu_device> m_cpu;
57	51
58	52	UINT16 m_InternalPalette[256];
59	53	UINT32 m_LastPalUpdate;
r29505	r29506
66	60	extern const device_type VIDEO_VRENDER0;
67	61
68	62
69		#define MCFG_VIDEO_VRENDER0_ADD(_tag, _interface) \
70		MCFG_DEVICE_ADD(_tag, VIDEO_VRENDER0, 0) \
71		MCFG_DEVICE_CONFIG(_interface)
	63	#define MCFG_VIDEO_VRENDER0_CPU(_tag) \
	64	vr0video_device::set_cpu_tag(*device, "^"_tag);
72	65
73	66	#endif /* __VR0VIDEO_H__ */

branches/new_menus/src/mame/video/playch10.c

r29505	r29506
17	17	PALETTE_INIT_MEMBER(playch10_state, playch10)
18	18	{
19	19	const UINT8 *color_prom = memregion("proms")->base();
20		ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
21		int i;
22	20
23		for (i = 0; i < 256; i++)
	21	for (int i = 0; i < 256; i++)
24	22	{
25	23	int bit0, bit1, bit2, bit3, r, g, b;
26	24
r29505	r29506
55	53	color_prom++;
56	54	}
57	55
58		ppu->init_palette_rgb(palette, 256);
	56	m_ppu->init_palette_rgb(palette, 256);
59	57	}
60	58
61	59	void playch10_state::ppu_irq(int *ppu_regs)
r29505	r29506
64	62	m_pc10_int_detect = 1;
65	63	}
66	64
67		/* our ppu interface                                           */
68		/* things like mirroring and whether to use vrom or vram       */
69		/* can be set by calling 'ppu2c0x_override_hardware_options'   */
70
71		const ppu2c0x_interface playch10_ppu_interface =
72		{
73		"cart",
74		1,                  /* gfxlayout num */
75		256,                /* color base */
76		PPU_MIRROR_NONE     /* mirroring */
77		};
78
79	65	TILE_GET_INFO_MEMBER(playch10_state::get_bg_tile_info)
80	66	{
81	67	UINT8 *videoram = m_videoram;
r29505	r29506
112	98
113	99	UINT32 playch10_state::screen_update_playch10_single(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
114	100	{
115		ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
116
117	101	rectangle top_monitor = screen.visible_area();
118	102
119		top_monitor.max_y = ( top_monitor.max_y - top_monitor.min_y ) / 2;
	103	top_monitor.max_y = (top_monitor.max_y - top_monitor.min_y) / 2;
120	104
121		if(m_pc10_dispmask_old != m_pc10_dispmask)
	105	if (m_pc10_dispmask_old != m_pc10_dispmask)
122	106	{
123	107	m_pc10_dispmask_old = m_pc10_dispmask;
124	108
125		if(m_pc10_dispmask)
	109	if (m_pc10_dispmask)
126	110	m_pc10_game_mode ^= 1;
127	111	}
128	112
129		if ( m_pc10_game_mode )
	113	if (m_pc10_game_mode)
130	114	/* render the ppu */
131		ppu->render(bitmap, 0, 0, 0, 0 );
	115	m_ppu->render(bitmap, 0, 0, 0, 0);
132	116	else
133	117	{
134	118	/* When the bios is accessing vram, the video circuitry can't access it */
135		if ( !m_pc10_sdcs )
	119	if (!m_pc10_sdcs)
136	120	m_bg_tilemap->draw(screen, bitmap, top_monitor, 0, 0);
137	121	}
138	122	return 0;
r29505	r29506
140	124
141	125	UINT32 playch10_state::screen_update_playch10_top(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
142	126	{
143		ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
144
145	127	/* Single Monitor version */
146	128	if (m_pc10_bios != 1)
147	129	return screen_update_playch10_single(screen, bitmap, cliprect);
148	130
149	131	if (!m_pc10_dispmask)
150	132	/* render the ppu */
151		ppu->render(bitmap, 0, 0, 0, 0);
	133	m_ppu->render(bitmap, 0, 0, 0, 0);
152	134	else
153	135	bitmap.fill(0, cliprect);
154	136
r29505	r29506
162	144	return screen_update_playch10_single(screen, bitmap, cliprect);
163	145
164	146	/* When the bios is accessing vram, the video circuitry can't access it */
165
166		if ( !m_pc10_sdcs )
	147	if (!m_pc10_sdcs)
167	148	m_bg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
168	149	else
169	150	bitmap.fill(0, cliprect);

branches/new_menus/src/mame/drivers/konamigx.c

r29505	r29506
1077	1077	/**********************************************************************************/
1078	1078	/* Sound handling */
1079	1079
1080		INTERRUPT_GEN_MEMBER(konamigx_state::tms_sync)
1081		{
1082		// DASP is synced to the LRCLK of one of the K054539s
1083		if (m_sound_ctrl & 0x20)
1084		m_dasp->sync_w(1);
1085		}
1086
1087	1080	READ16_MEMBER(konamigx_state::tms57002_data_word_r)
1088	1081	{
1089	1082	return m_dasp->data_r(space, 0);
r29505	r29506
1617	1610
1618	1611	MCFG_CPU_ADD("dasp", TMS57002, 24000000/2)
1619	1612	MCFG_CPU_DATA_MAP(gxtmsmap)
1620		MCFG_CPU_PERIODIC_INT_DRIVER(konamigx_state, tms_sync, 48000)
1621	1613
1622	1614	MCFG_QUANTUM_TIME(attotime::from_hz(6000))
1623	1615
r29505	r29506
1658	1650	/* sound hardware */
1659	1651	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1660	1652
	1653	MCFG_DEVICE_MODIFY("dasp")
	1654	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
	1655	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
	1656
1661	1657	MCFG_K056800_ADD("k056800", XTAL_18_432MHz)
1662	1658	MCFG_K056800_INT_HANDLER(INPUTLINE("soundcpu", M68K_IRQ_1))
1663	1659
1664	1660	MCFG_K054539_ADD("k054539_1", XTAL_18_432MHz, k054539_config)
1665	1661	MCFG_K054539_TIMER_HANDLER(WRITELINE(konamigx_state, k054539_irq_gen))
1666
	1662	MCFG_SOUND_ROUTE_EX(0, "dasp", 0.9, 0)
	1663	MCFG_SOUND_ROUTE_EX(1, "dasp", 0.9, 1)
1667	1664	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
1668	1665	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
1669	1666
1670	1667	MCFG_K054539_ADD("k054539_2", XTAL_18_432MHz, k054539_config)
	1668	MCFG_SOUND_ROUTE_EX(0, "dasp", 0.9, 2)
	1669	MCFG_SOUND_ROUTE_EX(1, "dasp", 0.9, 3)
1671	1670	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
1672	1671	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
1673	1672	MACHINE_CONFIG_END

branches/new_menus/src/mame/drivers/vsnes.c

r29505	r29506
1728	1728	MCFG_PALETTE_INIT_OWNER(vsnes_state,vsnes)
1729	1729	MCFG_VIDEO_START_OVERRIDE(vsnes_state,vsnes)
1730	1730
1731		MCFG_PPU2C04_ADD("ppu1", vsnes_ppu_interface_1)
	1731	MCFG_PPU2C04_ADD("ppu1")
1732	1732	MCFG_PPU2C0X_SET_SCREEN("screen1")
	1733	MCFG_PPU2C0X_CPU("maincpu")
1733	1734	MCFG_PPU2C0X_SET_NMI(vsnes_state, ppu_irq_1)
1734	1735
1735	1736	/* sound hardware */
r29505	r29506
1746	1747	static MACHINE_CONFIG_DERIVED( jajamaru, vsnes )
1747	1748
1748	1749	MCFG_DEVICE_REMOVE( "ppu1" )
1749		MCFG_PPU2C05_01_ADD("ppu1", vsnes_ppu_interface_1)
	1750	MCFG_PPU2C05_01_ADD("ppu1")
1750	1751	MCFG_PPU2C0X_SET_SCREEN("screen1")
	1752	MCFG_PPU2C0X_CPU("maincpu")
1751	1753	MCFG_PPU2C0X_SET_NMI(vsnes_state, ppu_irq_1)
1752	1754	MACHINE_CONFIG_END
1753	1755
1754	1756	static MACHINE_CONFIG_DERIVED( mightybj, vsnes )
1755	1757
1756	1758	MCFG_DEVICE_REMOVE( "ppu1" )
1757		MCFG_PPU2C05_02_ADD("ppu1", vsnes_ppu_interface_1)
	1759	MCFG_PPU2C05_02_ADD("ppu1")
1758	1760	MCFG_PPU2C0X_SET_SCREEN("screen1")
	1761	MCFG_PPU2C0X_CPU("maincpu")
1759	1762	MCFG_PPU2C0X_SET_NMI(vsnes_state, ppu_irq_1)
1760	1763	MACHINE_CONFIG_END
1761	1764
1762	1765	static MACHINE_CONFIG_DERIVED( vsgshoe, vsnes )
1763	1766
1764	1767	MCFG_DEVICE_REMOVE( "ppu1" )
1765		MCFG_PPU2C05_03_ADD("ppu1", vsnes_ppu_interface_1)
	1768	MCFG_PPU2C05_03_ADD("ppu1")
1766	1769	MCFG_PPU2C0X_SET_SCREEN("screen1")
	1770	MCFG_PPU2C0X_CPU("maincpu")
1767	1771	MCFG_PPU2C0X_SET_NMI(vsnes_state, ppu_irq_1)
1768	1772	MACHINE_CONFIG_END
1769	1773
1770	1774	static MACHINE_CONFIG_DERIVED( topgun, vsnes )
1771	1775
1772	1776	MCFG_DEVICE_REMOVE( "ppu1" )
1773		MCFG_PPU2C05_04_ADD("ppu1", vsnes_ppu_interface_1)
	1777	MCFG_PPU2C05_04_ADD("ppu1")
1774	1778	MCFG_PPU2C0X_SET_SCREEN("screen1")
	1779	MCFG_PPU2C0X_CPU("maincpu")
1775	1780	MCFG_PPU2C0X_SET_NMI(vsnes_state, ppu_irq_1)
1776	1781	MACHINE_CONFIG_END
1777	1782
r29505	r29506
1809	1814
1810	1815	MCFG_VIDEO_START_OVERRIDE(vsnes_state,vsdual)
1811	1816
1812		MCFG_PPU2C04_ADD("ppu1", vsnes_ppu_interface_1)
	1817	MCFG_PPU2C04_ADD("ppu1")
1813	1818	MCFG_PPU2C0X_SET_SCREEN("screen1")
	1819	MCFG_PPU2C0X_CPU("maincpu")
1814	1820	MCFG_PPU2C0X_SET_NMI(vsnes_state, ppu_irq_1)
1815		MCFG_PPU2C04_ADD("ppu2", vsnes_ppu_interface_2)
	1821
	1822	MCFG_PPU2C04_ADD("ppu2")
1816	1823	MCFG_PPU2C0X_SET_SCREEN("screen2")
	1824	MCFG_PPU2C0X_CPU("sub")
	1825	MCFG_PPU2C0X_COLORBASE(512)
1817	1826	MCFG_PPU2C0X_SET_NMI(vsnes_state, ppu_irq_2)
1818	1827
1819	1828	/* sound hardware */
r29505	r29506
1848	1857	MCFG_CPU_PROGRAM_MAP(vsnes_bootleg_z80_map)
1849	1858	MCFG_CPU_VBLANK_INT_DRIVER("screen1", vsnes_state,  irq0_line_hold)
1850	1859
1851
1852
1853	1860	/* video hardware */
1854	1861	MCFG_SCREEN_ADD("screen1", RASTER)
1855	1862	MCFG_SCREEN_REFRESH_RATE(60)
r29505	r29506
1863	1870	MCFG_PALETTE_INIT_OWNER(vsnes_state,vsnes)
1864	1871	MCFG_VIDEO_START_OVERRIDE(vsnes_state,vsnes)
1865	1872
1866		MCFG_PPU2C04_ADD("ppu1", vsnes_ppu_interface_1)
	1873	MCFG_PPU2C04_ADD("ppu1")
	1874	MCFG_PPU2C0X_CPU("maincpu")
1867	1875	MCFG_PPU2C0X_SET_SCREEN("screen1")
1868	1876	MCFG_PPU2C0X_SET_NMI(vsnes_state, ppu_irq_1)
1869	1877

branches/new_menus/src/mame/drivers/sandscrp.c

r29505	r29506
480	480	};
481	481
482	482
483		static const kaneko_pandora_interface sandscrp_pandora_config =
484		{
485		0,  /* gfx_region */
486		0, 0    /* x_offs, y_offs */
487		};
488
489	483	static MACHINE_CONFIG_START( sandscrp, sandscrp_state )
490	484
491	485	/* basic machine hardware */
r29505	r29506
499	493
500	494	MCFG_WATCHDOG_TIME_INIT(attotime::from_seconds(3))  /* a guess, and certainly wrong */
501	495
502
503	496	/* video hardware */
504	497	MCFG_SCREEN_ADD("screen", RASTER)
505	498	MCFG_SCREEN_REFRESH_RATE(60)
r29505	r29506
522	515	MCFG_DEVICE_ADD("calc1_mcu", KANEKO_HIT, 0)
523	516	kaneko_hit_device::set_type(*device, 0);
524	517
525		MCFG_KANEKO_PANDORA_ADD("pandora", sandscrp_pandora_config)
	518	MCFG_DEVICE_ADD("pandora", KANEKO_PANDORA, 0)
526	519	MCFG_KANEKO_PANDORA_GFXDECODE("gfxdecode")
527	520	MCFG_KANEKO_PANDORA_PALETTE("palette")
528	521

branches/new_menus/src/mame/drivers/tceptor.c

r29505	r29506
387	387	MCFG_DEFAULT_LAYOUT(layout_horizont)
388	388
389	389	MCFG_NAMCO_C45_ROAD_ADD("c45_road")
390		MCFG_NAMCO_C45_ROAD_PALETTE("palette")
	390	MCFG_GFX_PALETTE("palette")
391	391
392	392	MCFG_SCREEN_ADD("2dscreen", RASTER)
393	393	MCFG_SCREEN_REFRESH_RATE(60.606060)

branches/new_menus/src/mame/drivers/pktgaldx.c

r29505	r29506
303	303	GFXDECODE_END
304	304
305	305
306		int pktgaldx_state::bank_callback( int bank )
	306	DECO16IC_BANK_CB_MEMBER(pktgaldx_state::bank_callback)
307	307	{
308	308	return ((bank >> 4) & 0x7) * 0x1000;
309	309	}
r29505	r29506
355	355	MCFG_DECO16IC_PALETTE("palette")
356	356
357	357	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
358		decospr_device::set_gfx_region(*device, 2);
	358	MCFG_DECO_SPRITE_GFX_REGION(2)
359	359	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
360	360	MCFG_DECO_SPRITE_PALETTE("palette")
361	361

branches/new_menus/src/mame/drivers/moo.c

r29505	r29506
541	541	moo_sprite_callback
542	542	};
543	543
544		static const k054338_interface moo_k054338_intf =
545		{
546		0,
547		"none"
548		};
549
550	544	static k054539_interface k054539_config;
551	545
552	546	static MACHINE_CONFIG_START( moo, moo_state )
r29505	r29506
590	584	MCFG_K056832_ADD("k056832", moo_k056832_intf)
591	585	MCFG_K056832_GFXDECODE("gfxdecode")
592	586	MCFG_K056832_PALETTE("palette")
	587
593	588	MCFG_K053251_ADD("k053251")
594		MCFG_K054338_ADD("k054338", moo_k054338_intf)
595	589
	590	MCFG_DEVICE_ADD("k054338", K054338, 0)
	591
596	592	/* sound hardware */
597	593	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
598	594
r29505	r29506
640	636	MCFG_K056832_ADD("k056832", moo_k056832_intf)
641	637	MCFG_K056832_GFXDECODE("gfxdecode")
642	638	MCFG_K056832_PALETTE("palette")
	639
643	640	MCFG_K053251_ADD("k053251")
644		MCFG_K054338_ADD("k054338", moo_k054338_intf)
645	641
	642	MCFG_DEVICE_ADD("k054338", K054338, 0)
	643
646	644	/* sound hardware */
647	645	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
648	646

branches/new_menus/src/mame/drivers/crshrace.c

r29505	r29506
406	406	m_audiocpu->set_input_line(0, state ? ASSERT_LINE : CLEAR_LINE);
407	407	}
408	408
409		static const k053936_interface crshrace_k053936_intf =
410		{
411		1, -48, -21 /* wrap, xoff, yoff */
412		};
413
414
415	409	void crshrace_state::machine_start()
416	410	{
417	411	m_z80bank->configure_entries(0, 4, memregion("audiocpu")->base() + 0x10000, 0x8000);
r29505	r29506
464	458	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
465	459	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram2")
466	460
467		MCFG_K053936_ADD("k053936", crshrace_k053936_intf)
	461	MCFG_DEVICE_ADD("k053936", K053936, 0)
	462	MCFG_K053936_WRAP(1)
	463	MCFG_K053936_OFFSETS(-48, -21)
468	464
469
470	465	/* sound hardware */
471	466	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
472	467

branches/new_menus/src/mame/drivers/airbustr.c

r29505	r29506
589	589
590	590	/* Machine Driver */
591	591
592		static const kaneko_pandora_interface airbustr_pandora_config =
593		{
594		1,  /* gfx_region */
595		0, 0    /* x_offs, y_offs */
596		};
597
598	592	static MACHINE_CONFIG_START( airbustr, airbustr_state )
599	593
600	594	/* basic machine hardware */
r29505	r29506
631	625	MCFG_PALETTE_ADD("palette", 768)
632	626	MCFG_PALETTE_FORMAT(xGGGGGRRRRRBBBBB)
633	627
634		MCFG_KANEKO_PANDORA_ADD("pandora", airbustr_pandora_config)
	628	MCFG_DEVICE_ADD("pandora", KANEKO_PANDORA, 0)
	629	MCFG_KANEKO_PANDORA_GFX_REGION(1)
635	630	MCFG_KANEKO_PANDORA_GFXDECODE("gfxdecode")
636	631	MCFG_KANEKO_PANDORA_PALETTE("palette")
637	632

branches/new_menus/src/mame/drivers/deco32.c

r29505	r29506
1645	1645	device.execute().set_input_line(ARM_IRQ_LINE, HOLD_LINE);
1646	1646	}
1647	1647
1648		UINT16 captaven_pri_callback(UINT16 x)
	1648	DECOSPR_PRIORITY_CB_MEMBER(deco32_state::captaven_pri_callback)
1649	1649	{
1650		if ((x&0x60)==0x00)
	1650	if ((pri & 0x60) == 0x00)
1651	1651	{
1652	1652	return 0; // above everything
1653	1653	}
1654		else if ((x&0x60)==0x20)
	1654	else if ((pri & 0x60) == 0x20)
1655	1655	{
1656	1656	return 0xfff0; // above the 2nd playfield
1657	1657	}
1658		else if ((x&0x60)==0x40)
	1658	else if ((pri & 0x60) == 0x40)
1659	1659	{
1660	1660	return 0xfffc; // above the 1st playfield
1661	1661	}
r29505	r29506
1665	1665	}
1666	1666	}
1667	1667
1668		int deco32_state::captaven_bank_callback( int bank )
	1668	DECO16IC_BANK_CB_MEMBER(deco32_state::captaven_bank_callback)
1669	1669	{
1670	1670	bank = bank >> 4;
1671	1671	bank = (bank & 2) >> 1;
r29505	r29506
1729	1729	MCFG_DECO16IC_PALETTE("palette")
1730	1730
1731	1731	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
1732		decospr_device::set_gfx_region(*device, 3);
1733		decospr_device::set_pri_callback(*device, captaven_pri_callback);
	1732	MCFG_DECO_SPRITE_GFX_REGION(3)
	1733	MCFG_DECO_SPRITE_PRIORITY_CB(deco32_state, captaven_pri_callback)
1734	1734	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1735	1735	MCFG_DECO_SPRITE_PALETTE("palette")
1736	1736
r29505	r29506
1773	1773	return machine().root_device().ioport(":IN1")->read();
1774	1774	}
1775	1775
1776		int deco32_state::fghthist_bank_callback( int bank )
	1776	DECO16IC_BANK_CB_MEMBER(deco32_state::fghthist_bank_callback)
1777	1777	{
1778	1778	bank = bank >> 4;
1779	1779	bank = (bank & 1) | ((bank & 4) >> 1) | ((bank & 2) << 1);
r29505	r29506
1835	1835	MCFG_DECO16IC_PALETTE("palette")
1836	1836
1837	1837	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
1838		decospr_device::set_gfx_region(*device, 3);
	1838	MCFG_DECO_SPRITE_GFX_REGION(3)
1839	1839	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1840	1840	MCFG_DECO_SPRITE_PALETTE("palette")
1841	1841
r29505	r29506
1921	1921	MCFG_DECO16IC_PALETTE("palette")
1922	1922
1923	1923	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
1924		decospr_device::set_gfx_region(*device, 3);
	1924	MCFG_DECO_SPRITE_GFX_REGION(3)
1925	1925	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1926	1926	MCFG_DECO_SPRITE_PALETTE("palette")
1927	1927
r29505	r29506
1953	1953	MACHINE_CONFIG_END
1954	1954
1955	1955
1956		int dragngun_state::bank_1_callback( int bank )
	1956	DECO16IC_BANK_CB_MEMBER(dragngun_state::bank_1_callback)
1957	1957	{
1958	1958	bank = bank >> 4;
1959	1959	return bank * 0x1000;
1960	1960	}
1961	1961
1962	1962
1963		int dragngun_state::bank_2_callback( int bank )
	1963	DECO16IC_BANK_CB_MEMBER(dragngun_state::bank_2_callback)
1964	1964	{
1965	1965	bank = bank >> 5;
1966	1966	return bank * 0x1000;
r29505	r29506
2171	2171	MACHINE_CONFIG_END
2172	2172
2173	2173
2174		int deco32_state::tattass_bank_callback( int bank )
	2174	DECO16IC_BANK_CB_MEMBER(deco32_state::tattass_bank_callback)
2175	2175	{
2176	2176	bank = bank >> 4;
2177	2177	return bank * 0x1000;
r29505	r29506
2225	2225	MCFG_DECO16IC_PALETTE("palette")
2226	2226
2227	2227	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
2228		decospr_device::set_gfx_region(*device, 3);
	2228	MCFG_DECO_SPRITE_GFX_REGION(3)
2229	2229	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2230	2230	MCFG_DECO_SPRITE_PALETTE("palette")
2231	2231
2232	2232	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
2233		decospr_device::set_gfx_region(*device, 4);
	2233	MCFG_DECO_SPRITE_GFX_REGION(4)
2234	2234	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2235	2235	MCFG_DECO_SPRITE_PALETTE("palette")
2236	2236
r29505	r29506
2302	2302	MCFG_DECO16IC_PALETTE("palette")
2303	2303
2304	2304	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
2305		decospr_device::set_gfx_region(*device, 3);
	2305	MCFG_DECO_SPRITE_GFX_REGION(3)
2306	2306	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2307	2307	MCFG_DECO_SPRITE_PALETTE("palette")
2308	2308
2309	2309	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
2310		decospr_device::set_gfx_region(*device, 4);
	2310	MCFG_DECO_SPRITE_GFX_REGION(4)
2311	2311	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2312	2312	MCFG_DECO_SPRITE_PALETTE("palette")
2313	2313

branches/new_menus/src/mame/drivers/crospang.c

r29505	r29506
361	361
362	362
363	363	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
364		decospr_device::set_gfx_region(*device, 0);
365		decospr_device::set_is_bootleg(*device, true);
366		decospr_device::set_offsets(*device, 5,7);
	364	MCFG_DECO_SPRITE_GFX_REGION(0)
	365	MCFG_DECO_SPRITE_ISBOOTLEG(true)
	366	MCFG_DECO_SPRITE_OFFSETS(5, 7)
367	367	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
368	368	MCFG_DECO_SPRITE_PALETTE("palette")
369	369

branches/new_menus/src/mame/drivers/deco156.c

r29505	r29506
65	65	INTERRUPT_GEN_MEMBER(deco32_vbl_interrupt);
66	66	void descramble_sound( const char *tag );
67	67	DECLARE_WRITE_LINE_MEMBER(sound_irq_gen);
68		int bank_callback(int bank);
	68	DECO16IC_BANK_CB_MEMBER(bank_callback);
	69	DECOSPR_PRIORITY_CB_MEMBER(pri_callback);
69	70	};
70	71
71	72
r29505	r29506
322	323	device.execute().set_input_line(ARM_IRQ_LINE, HOLD_LINE);
323	324	}
324	325
325		int deco156_state::bank_callback(int bank)
	326	DECO16IC_BANK_CB_MEMBER(deco156_state::bank_callback)
326	327	{
327	328	return ((bank >> 4) & 0x7) * 0x1000;
328	329	}
329	330
330		UINT16 deco156_pri_callback(UINT16 x)
	331	DECOSPR_PRIORITY_CB_MEMBER(deco156_state::pri_callback)
331	332	{
332		switch (x & 0xc000)
	333	switch (pri & 0xc000)
333	334	{
334	335	case 0x0000: return 0;
335	336	case 0x4000: return 0xf0;
r29505	r29506
340	341	return 0;
341	342	}
342	343
343
344	344	static MACHINE_CONFIG_START( hvysmsh, deco156_state )
345	345
346	346	/* basic machine hardware */
r29505	r29506
377	377	MCFG_DECO16IC_PALETTE("palette")
378	378
379	379	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
380		decospr_device::set_gfx_region(*device, 2);
381		decospr_device::set_pri_callback(*device, deco156_pri_callback);
	380	MCFG_DECO_SPRITE_GFX_REGION(2)
	381	MCFG_DECO_SPRITE_PRIORITY_CB(deco156_state, pri_callback)
382	382	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
383	383	MCFG_DECO_SPRITE_PALETTE("palette")
384	384
r29505	r29506
430	430	MCFG_DECO16IC_PALETTE("palette")
431	431
432	432	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
433		decospr_device::set_gfx_region(*device, 2);
434		decospr_device::set_pri_callback(*device, deco156_pri_callback);
	433	MCFG_DECO_SPRITE_GFX_REGION(2)
	434	MCFG_DECO_SPRITE_PRIORITY_CB(deco156_state, pri_callback)
435	435	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
436	436	MCFG_DECO_SPRITE_PALETTE("palette")
437	437

branches/new_menus/src/mame/drivers/taito_h.c

r29505	r29506
243	243	AM_RANGE(0x100000, 0x10ffff) AM_MIRROR(0x010000) AM_RAM AM_SHARE("m68000_mainram")
244	244	AM_RANGE(0x200000, 0x200001) AM_READ8(syvalion_input_bypass_r, 0x00ff) AM_DEVWRITE8("tc0220ioc", tc0220ioc_device, portreg_w, 0x00ff)
245	245	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, port_r, port_w, 0x00ff)
246		AM_RANGE(0x300000, 0x300001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
247		AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	246	AM_RANGE(0x300000, 0x300001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	247	AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
248	248	AM_RANGE(0x400000, 0x420fff) AM_DEVREADWRITE("tc0080vco", tc0080vco_device, word_r, word_w)
249	249	AM_RANGE(0x500800, 0x500fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
250	250	ADDRESS_MAP_END
r29505	r29506
254	254	AM_RANGE(0x100000, 0x10ffff) AM_MIRROR(0x010000) AM_RAM AM_SHARE("m68000_mainram")
255	255	AM_RANGE(0x200000, 0x200001) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, portreg_r, portreg_w, 0x00ff)
256	256	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, port_r, port_w, 0x00ff)
257		AM_RANGE(0x300000, 0x300001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
258		AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	257	AM_RANGE(0x300000, 0x300001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	258	AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
259	259	AM_RANGE(0x400000, 0x420fff) AM_DEVREADWRITE("tc0080vco", tc0080vco_device, word_r, word_w)
260	260	AM_RANGE(0x500800, 0x500fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
261	261	ADDRESS_MAP_END
r29505	r29506
263	263	static ADDRESS_MAP_START( tetristh_map, AS_PROGRAM, 16, taitoh_state )
264	264	AM_RANGE(0x000000, 0x03ffff) AM_ROM
265	265	AM_RANGE(0x100000, 0x10ffff) AM_MIRROR(0x010000) AM_RAM AM_SHARE("m68000_mainram")
266		AM_RANGE(0x200000, 0x200001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
267		AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	266	AM_RANGE(0x200000, 0x200001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	267	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
268	268	AM_RANGE(0x300000, 0x300001) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, portreg_r, portreg_w, 0x00ff)
269	269	AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, port_r, port_w, 0x00ff)
270	270	AM_RANGE(0x400000, 0x420fff) AM_DEVREADWRITE("tc0080vco", tc0080vco_device, word_r, word_w)
r29505	r29506
275	275	AM_RANGE(0x000000, 0x05ffff) AM_ROM
276	276	AM_RANGE(0x100000, 0x10ffff) AM_MIRROR(0x010000) AM_RAM AM_SHARE("m68000_mainram")
277	277	AM_RANGE(0x200000, 0x20000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
278		AM_RANGE(0x300000, 0x300001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
279		AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	278	AM_RANGE(0x300000, 0x300001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	279	AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
280	280	AM_RANGE(0x400000, 0x420fff) AM_DEVREADWRITE("tc0080vco", tc0080vco_device, word_r, word_w)
281	281	AM_RANGE(0x500800, 0x500fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
282	282	AM_RANGE(0x600000, 0x600001) AM_WRITENOP    /* ?? writes zero once per frame */
r29505	r29506
288	288	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
289	289	AM_RANGE(0xc000, 0xdfff) AM_RAM
290	290	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
291		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
292		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	291	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	292	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
293	293	AM_RANGE(0xe400, 0xe403) AM_WRITENOP        /* pan control */
294	294	AM_RANGE(0xea00, 0xea00) AM_READNOP
295	295	AM_RANGE(0xee00, 0xee00) AM_WRITENOP        /* ? */
r29505	r29506
646	646	}
647	647
648	648
649		static const tc0080vco_interface syvalion_tc0080vco_intf =
650		{
651		0, 1,   /* gfxnum, txnum */
652		1, 1, -2,
653		1
654		};
655
656		static const tc0080vco_interface recordbr_tc0080vco_intf =
657		{
658		0, 1,   /* gfxnum, txnum */
659		1, 1, -2,
660		0
661		};
662
663		static const tc0140syt_interface taitoh_tc0140syt_intf =
664		{
665		"maincpu", "audiocpu"
666		};
667
668	649	static MACHINE_CONFIG_START( syvalion, taitoh_state )
669	650
670	651	/* basic machine hardware */
r29505	r29506
698	679	MCFG_PALETTE_ADD("palette", 33*16)
699	680	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
700	681
701		MCFG_TC0080VCO_ADD("tc0080vco", syvalion_tc0080vco_intf)
	682	MCFG_DEVICE_ADD("tc0080vco", TC0080VCO, 0)
	683	MCFG_TC0080VCO_GFX_REGION(0)
	684	MCFG_TC0080VCO_TX_REGION(1)
	685	MCFG_TC0080VCO_OFFSETS(1, 1)
	686	MCFG_TC0080VCO_BGFLIP_OFFS(-2)
702	687	MCFG_TC0080VCO_GFXDECODE("gfxdecode")
703	688	MCFG_TC0080VCO_PALETTE("palette")
704	689
r29505	r29506
711	696	MCFG_SOUND_ROUTE(1, "mono", 1.0)
712	697	MCFG_SOUND_ROUTE(2, "mono", 1.0)
713	698
714		MCFG_TC0140SYT_ADD("tc0140syt", taitoh_tc0140syt_intf)
	699	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	700	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	701	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
715	702	MACHINE_CONFIG_END
716	703
717	704
r29505	r29506
748	735	MCFG_PALETTE_ADD("palette", 32*16)
749	736	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
750	737
751		MCFG_TC0080VCO_ADD("tc0080vco", recordbr_tc0080vco_intf)
	738	MCFG_DEVICE_ADD("tc0080vco", TC0080VCO, 0)
	739	MCFG_TC0080VCO_GFX_REGION(0)
	740	MCFG_TC0080VCO_TX_REGION(1)
	741	MCFG_TC0080VCO_OFFSETS(1, 1)
	742	MCFG_TC0080VCO_BGFLIP_OFFS(-2)
752	743	MCFG_TC0080VCO_GFXDECODE("gfxdecode")
753	744	MCFG_TC0080VCO_PALETTE("palette")
754	745
r29505	r29506
761	752	MCFG_SOUND_ROUTE(1, "mono", 1.0)
762	753	MCFG_SOUND_ROUTE(2, "mono", 1.0)
763	754
764		MCFG_TC0140SYT_ADD("tc0140syt", taitoh_tc0140syt_intf)
	755	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	756	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	757	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
765	758	MACHINE_CONFIG_END
766	759
767	760
r29505	r29506
806	799	MCFG_PALETTE_ADD("palette", 33*16)
807	800	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
808	801
809		MCFG_TC0080VCO_ADD("tc0080vco", recordbr_tc0080vco_intf)
	802	MCFG_DEVICE_ADD("tc0080vco", TC0080VCO, 0)
	803	MCFG_TC0080VCO_GFX_REGION(0)
	804	MCFG_TC0080VCO_TX_REGION(1)
	805	MCFG_TC0080VCO_OFFSETS(1, 1)
	806	MCFG_TC0080VCO_BGFLIP_OFFS(-2)
810	807	MCFG_TC0080VCO_GFXDECODE("gfxdecode")
811	808	MCFG_TC0080VCO_PALETTE("palette")
812	809
r29505	r29506
819	816	MCFG_SOUND_ROUTE(1, "mono", 1.0)
820	817	MCFG_SOUND_ROUTE(2, "mono", 1.0)
821	818
822		MCFG_TC0140SYT_ADD("tc0140syt", taitoh_tc0140syt_intf)
	819	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	820	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	821	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
823	822	MACHINE_CONFIG_END
824	823
825	824

branches/new_menus/src/mame/drivers/snowbros.c

r29505	r29506
1509	1509	m_hyperpac_ram[0x2000/2 + i] = PROTDATA[i];
1510	1510	}
1511	1511
1512		static const kaneko_pandora_interface snowbros_pandora_config =
1513		{
1514		0,  /* gfx_region */
1515		0, 0    /* x_offs, y_offs */
1516		};
1517
1518	1512	static MACHINE_CONFIG_START( snowbros, snowbros_state )
1519	1513
1520	1514	/* basic machine hardware */
r29505	r29506
1540	1534	MCFG_PALETTE_ADD("palette", 256)
1541	1535	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
1542	1536
1543		MCFG_KANEKO_PANDORA_ADD("pandora", snowbros_pandora_config)
	1537	MCFG_DEVICE_ADD("pandora", KANEKO_PANDORA, 0)
1544	1538	MCFG_KANEKO_PANDORA_GFXDECODE("gfxdecode")
1545	1539	MCFG_KANEKO_PANDORA_PALETTE("palette")
1546	1540

branches/new_menus/src/mame/drivers/dblewing.c

r29505	r29506
113	113	virtual void machine_reset();
114	114	UINT32 screen_update_dblewing(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
115	115
116		int bank_callback(int bank);
	116	DECO16IC_BANK_CB_MEMBER(bank_callback);
	117	DECOSPR_PRIORITY_CB_MEMBER(pri_callback);
117	118	void dblewing_sound_cb( address_space &space, UINT16 data, UINT16 mem_mask );
118	119
119	120	READ16_MEMBER( wf_protection_region_0_104_r );
120	121	WRITE16_MEMBER( wf_protection_region_0_104_w );
121	122	};
122	123
123		UINT16 dblwings_pri_callback(UINT16 x)
124		{
125		return 0; // sprites always on top?
126		}
127	124
128
129
130	125	UINT32 dblewing_state::screen_update_dblewing(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
131	126	{
132	127	address_space &space = generic_space();
r29505	r29506
332	327	m_audiocpu->set_input_line(0, (m_sound_irq != 0) ? ASSERT_LINE : CLEAR_LINE);
333	328	}
334	329
335		int dblewing_state::bank_callback( int bank )
	330	DECO16IC_BANK_CB_MEMBER(dblewing_state::bank_callback)
336	331	{
337	332	return ((bank >> 4) & 0x7) * 0x1000;
338	333	}
339	334
	335	DECOSPR_PRIORITY_CB_MEMBER(dblewing_state::pri_callback)
	336	{
	337	return 0; // sprites always on top?
	338	}
	339
	340
340	341	void dblewing_state::machine_start()
341	342	{
342	343	save_item(NAME(m_sound_irq));
r29505	r29506
398	399	MCFG_DECO16IC_PALETTE("palette")
399	400
400	401	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
401		decospr_device::set_gfx_region(*device, 2);
402		decospr_device::set_pri_callback(*device, dblwings_pri_callback);
	402	MCFG_DECO_SPRITE_GFX_REGION(2)
	403	MCFG_DECO_SPRITE_PRIORITY_CB(dblewing_state, pri_callback)
403	404	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
404	405	MCFG_DECO_SPRITE_PALETTE("palette")
405	406

branches/new_menus/src/mame/drivers/powerins.c

r29505	r29506
328	328	DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL,
329	329	};
330	330
331		static const nmk112_interface powerins_nmk112_intf =
332		{
333		"oki1", "oki2", 0
334		};
335
336
337	331	static MACHINE_CONFIG_START( powerins, powerins_state )
338	332
339	333	/* basic machine hardware */
r29505	r29506
374	368	MCFG_YM2203_AY8910_INTF(&ay8910_config)
375	369	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 2.0)
376	370
377		MCFG_NMK112_ADD("nmk112", powerins_nmk112_intf)
	371	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	372	MCFG_NMK112_ROM0("oki1")
	373	MCFG_NMK112_ROM1("oki2")
378	374	MACHINE_CONFIG_END
379	375
380	376	static MACHINE_CONFIG_DERIVED( powerina, powerins )

branches/new_menus/src/mame/drivers/tumbleb.c

r29505	r29506
2060	2060	MCFG_SCREEN_PALETTE("palette")
2061	2061
2062	2062	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
2063		decospr_device::set_gfx_region(*device, 3);
2064		decospr_device::set_is_bootleg(*device, true);
	2063	MCFG_DECO_SPRITE_GFX_REGION(3)
	2064	MCFG_DECO_SPRITE_ISBOOTLEG(true)
2065	2065	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2066	2066	MCFG_DECO_SPRITE_PALETTE("palette")
2067	2067
r29505	r29506
2099	2099	MCFG_SCREEN_PALETTE("palette")
2100	2100
2101	2101	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
2102		decospr_device::set_gfx_region(*device, 3);
2103		decospr_device::set_is_bootleg(*device, true);
	2102	MCFG_DECO_SPRITE_GFX_REGION(3)
	2103	MCFG_DECO_SPRITE_ISBOOTLEG(true)
2104	2104	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2105	2105	MCFG_DECO_SPRITE_PALETTE("palette")
2106	2106
r29505	r29506
2141	2141	MCFG_SCREEN_PALETTE("palette")
2142	2142
2143	2143	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
2144		decospr_device::set_gfx_region(*device, 3);
2145		decospr_device::set_is_bootleg(*device, true);
	2144	MCFG_DECO_SPRITE_GFX_REGION(3)
	2145	MCFG_DECO_SPRITE_ISBOOTLEG(true)
2146	2146	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2147	2147	MCFG_DECO_SPRITE_PALETTE("palette")
2148	2148
r29505	r29506
2179	2179	MCFG_SCREEN_PALETTE("palette")
2180	2180
2181	2181	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
2182		decospr_device::set_gfx_region(*device, 3);
2183		decospr_device::set_is_bootleg(*device, true);
2184		decospr_device::set_transpen(*device, 15);
	2182	MCFG_DECO_SPRITE_GFX_REGION(3)
	2183	MCFG_DECO_SPRITE_ISBOOTLEG(true)
	2184	MCFG_DECO_SPRITE_TRANSPEN(15)
2185	2185	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2186	2186	MCFG_DECO_SPRITE_PALETTE("palette")
2187	2187
r29505	r29506
2240	2240	MCFG_SCREEN_PALETTE("palette")
2241	2241
2242	2242	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
2243		decospr_device::set_gfx_region(*device, 3);
2244		decospr_device::set_is_bootleg(*device, true);
	2243	MCFG_DECO_SPRITE_GFX_REGION(3)
	2244	MCFG_DECO_SPRITE_ISBOOTLEG(true)
2245	2245	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2246	2246	MCFG_DECO_SPRITE_PALETTE("palette")
2247	2247
r29505	r29506
2351	2351	MCFG_SCREEN_PALETTE("palette")
2352	2352
2353	2353	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
2354		decospr_device::set_gfx_region(*device, 3);
2355		decospr_device::set_is_bootleg(*device, true);
	2354	MCFG_DECO_SPRITE_GFX_REGION(3)
	2355	MCFG_DECO_SPRITE_ISBOOTLEG(true)
2356	2356	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2357	2357	MCFG_DECO_SPRITE_PALETTE("palette")
2358	2358
r29505	r29506
2390	2390	MCFG_SCREEN_PALETTE("palette")
2391	2391
2392	2392	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
2393		decospr_device::set_gfx_region(*device, 3);
2394		decospr_device::set_is_bootleg(*device, true);
	2393	MCFG_DECO_SPRITE_GFX_REGION(3)
	2394	MCFG_DECO_SPRITE_ISBOOTLEG(true)
2395	2395	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
2396	2396	MCFG_DECO_SPRITE_PALETTE("palette")
2397	2397

branches/new_menus/src/mame/drivers/darius.c

r29505	r29506
172	172	switch (offset)
173	173	{
174	174	case 0x01:
175		return (m_tc0140syt->tc0140syt_comm_r(space, 0) & 0xff);    /* sound interface read */
	175	return (m_tc0140syt->master_comm_r(space, 0) & 0xff);    /* sound interface read */
176	176
177	177	case 0x04:
178	178	return ioport("P1")->read();
r29505	r29506
201	201	{
202	202	case 0x00:  /* sound interface write */
203	203
204		m_tc0140syt->tc0140syt_port_w(space, 0, data & 0xff);
	204	m_tc0140syt->master_port_w(space, 0, data & 0xff);
205	205	return;
206	206
207	207	case 0x01:  /* sound interface write */
208	208
209		m_tc0140syt->tc0140syt_comm_w(space, 0, data & 0xff);
	209	m_tc0140syt->master_comm_w(space, 0, data & 0xff);
210	210	return;
211	211
212	212	case 0x28:  /* unknown, written by both cpus - always 0? */
r29505	r29506
464	464	AM_RANGE(0x8000, 0x8fff) AM_RAM
465	465	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ym1", ym2203_device, read, write)
466	466	AM_RANGE(0xa000, 0xa001) AM_DEVREADWRITE("ym2", ym2203_device, read, write)
467		AM_RANGE(0xb000, 0xb000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
468		AM_RANGE(0xb001, 0xb001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	467	AM_RANGE(0xb000, 0xb000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	468	AM_RANGE(0xb001, 0xb001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
469	469	AM_RANGE(0xc000, 0xc000) AM_WRITE(darius_fm0_pan)
470	470	AM_RANGE(0xc400, 0xc400) AM_WRITE(darius_fm1_pan)
471	471	AM_RANGE(0xc800, 0xc800) AM_WRITE(darius_psg0_pan)
r29505	r29506
784	784	MACHINE DRIVERS
785	785	***********************************************************/
786	786
787		static const pc080sn_interface darius_pc080sn_intf =
788		{
789		1,   /* gfxnum */
790		-16, 8, 0, 1    /* x_offset, y_offset, y_invert, dblwidth */
791		};
792
793		static const tc0140syt_interface darius_tc0140syt_intf =
794		{
795		"maincpu", "audiocpu"
796		};
797
798	787	void darius_state::darius_postload()
799	788	{
800	789	parse_control();
r29505	r29506
896	885	MCFG_SCREEN_UPDATE_DRIVER(darius_state, screen_update_darius_right)
897	886	MCFG_SCREEN_PALETTE("palette")
898	887
899
900		MCFG_PC080SN_ADD("pc080sn", darius_pc080sn_intf)
	888	MCFG_DEVICE_ADD("pc080sn", PC080SN, 0)
	889	MCFG_PC080SN_GFX_REGION(1)
	890	MCFG_PC080SN_OFFSETS(-16, 8)
	891	MCFG_PC080SN_YINVERT(0)
	892	MCFG_PC080SN_DBLWIDTH(1)
901	893	MCFG_PC080SN_GFXDECODE("gfxdecode")
902	894	MCFG_PC080SN_PALETTE("palette")
903	895
r29505	r29506
972	964	MCFG_FILTER_VOLUME_ADD("msm5205.r", 0)
973	965	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
974	966
975		MCFG_TC0140SYT_ADD("tc0140syt", darius_tc0140syt_intf)
	967	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	968	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	969	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
976	970	MACHINE_CONFIG_END
977	971
978	972

branches/new_menus/src/mame/drivers/darkseal.c

r29505	r29506
273	273	MCFG_DECO16IC_PALETTE("palette")
274	274
275	275	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
276		decospr_device::set_gfx_region(*device, 4);
	276	MCFG_DECO_SPRITE_GFX_REGION(4)
277	277	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
278	278	MCFG_DECO_SPRITE_PALETTE("palette")
279	279

branches/new_menus/src/mame/drivers/dbz.c

r29505	r29506
307	307	dbz_sprite_callback
308	308	};
309	309
310		/* both k053936 use the same wrap/offs */
311		static const k053936_interface dbz_k053936_intf =
312		{
313		1, -46, -16
314		};
315
316	310	WRITE_LINE_MEMBER(dbz_state::dbz_irq2_ack_w)
317	311	{
318	312	m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
r29505	r29506
370	364	MCFG_K056832_ADD("k056832", dbz_k056832_intf)
371	365	MCFG_K056832_GFXDECODE("gfxdecode")
372	366	MCFG_K056832_PALETTE("palette")
	367
373	368	MCFG_K053246_ADD("k053246", dbz_k053246_intf)
374	369	MCFG_K053246_GFXDECODE("gfxdecode")
375	370	MCFG_K053246_PALETTE("palette")
	371
376	372	MCFG_K053251_ADD("k053251")
377		MCFG_K053936_ADD("k053936_1", dbz_k053936_intf)
378		MCFG_K053936_ADD("k053936_2", dbz_k053936_intf)
	373
	374	MCFG_DEVICE_ADD("k053936_1", K053936, 0)
	375	MCFG_K053936_WRAP(1)
	376	MCFG_K053936_OFFSETS(-46, -16)
	377
	378	MCFG_DEVICE_ADD("k053936_2", K053936, 0)
	379	MCFG_K053936_WRAP(1)
	380	MCFG_K053936_OFFSETS(-46, -16)
	381
379	382	MCFG_DEVICE_ADD("k053252", K053252, 16000000/2)
380	383	MCFG_K053252_INT1_ACK_CB(WRITELINE(dbz_state, dbz_irq2_ack_w))
381	384

branches/new_menus/src/mame/drivers/vaportra.c

r29505	r29506
196	196
197	197	/******************************************************************************/
198	198
199		int vaportra_state::bank_callback( int bank )
	199	DECO16IC_BANK_CB_MEMBER(vaportra_state::bank_callback)
200	200	{
201	201	return ((bank >> 4) & 0x7) * 0x1000;
202	202	}

branches/new_menus/src/mame/drivers/icecold.c

r29505	r29506
327	327	}
328	328	}
329	329
330		static I8279_INTERFACE( icecold_i8279_intf )
331		{
332		DEVCB_DEVICE_LINE_MEMBER("pia0", pia6821_device, cb1_w), // irq
333		DEVCB_DRIVER_MEMBER(icecold_state, scanlines_w),    // scan SL lines
334		DEVCB_DRIVER_MEMBER(icecold_state, digit_w),        // display A&B
335		DEVCB_NULL,                                         // BD
336		DEVCB_DRIVER_MEMBER(icecold_state, kbd_r),          // kbd RL lines
337		DEVCB_NULL,                                         // Shift key
338		DEVCB_NULL                                          // Ctrl-Strobe line
339		};
340
341	330	static const ay8910_interface icecold_ay8910_0_intf =
342	331	{
343	332	AY8910_LEGACY_OUTPUT,
r29505	r29506
382	371	MCFG_PIA_IRQA_HANDLER(DEVWRITELINE("maincpu", m6809_device, irq_line))
383	372	MCFG_PIA_IRQB_HANDLER(DEVWRITELINE("maincpu", m6809_device, irq_line))
384	373
385		MCFG_I8279_ADD("i8279", XTAL_6MHz/4, icecold_i8279_intf)
386
	374	MCFG_DEVICE_ADD("i8279", I8279, XTAL_6MHz/4)
	375	MCFG_I8279_OUT_IRQ_CB(DEVWRITELINE("pia0", pia6821_device, cb1_w)) // irq
	376	MCFG_I8279_OUT_SL_CB(WRITE8(icecold_state, scanlines_w))       // scan SL lines
	377	MCFG_I8279_OUT_DISP_CB(WRITE8(icecold_state, digit_w))         // display A&B
	378	MCFG_I8279_IN_RL_CB(READ8(icecold_state, kbd_r))               // kbd RL lines
	379
387	380	// 30Hz signal from CH-C of ay0
388	381	MCFG_TIMER_DRIVER_ADD_PERIODIC("sint_timer", icecold_state, icecold_sint_timer, attotime::from_hz(30))
389	382

branches/new_menus/src/mame/drivers/taito_l.c

r29505	r29506
660	660	AM_RANGE(0x0000, 0x7fff) AM_ROM
661	661	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank6")
662	662	AM_RANGE(0xc000, 0xc000) AM_WRITE(rombank2switch_w)
663		AM_RANGE(0xc800, 0xc800) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_port_w)
664		AM_RANGE(0xc801, 0xc801) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w)
	663	AM_RANGE(0xc800, 0xc800) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, master_port_w)
	664	AM_RANGE(0xc801, 0xc801) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w)
665	665	AM_RANGE(0xd000, 0xd000) AM_READ_PORT("DSWA") AM_WRITENOP   // Direct copy of input port 0
666	666	AM_RANGE(0xd001, 0xd001) AM_READ_PORT("DSWB")
667	667	AM_RANGE(0xd002, 0xd002) AM_READ_PORT("IN0")
r29505	r29506
676	676	AM_RANGE(0x0000, 0x3fff) AM_ROM
677	677	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank7")
678	678	AM_RANGE(0x8000, 0x9fff) AM_RAM
679		AM_RANGE(0xe000, 0xe000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
680		AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	679	AM_RANGE(0xe000, 0xe000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	680	AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
681	681	AM_RANGE(0xf000, 0xf001) AM_DEVREADWRITE("ymsnd", ym2203_device, read, write)
682	682	ADDRESS_MAP_END
683	683
r29505	r29506
687	687	AM_RANGE(0x8000, 0x87ff) AM_RAM AM_SHARE("share1")
688	688	AM_RANGE(0x8800, 0x8800) AM_READWRITE(mux_r, mux_w)
689	689	AM_RANGE(0x8801, 0x8801) AM_WRITE(mux_ctrl_w) AM_READNOP    // Watchdog or interrupt ack (value ignored)
690		AM_RANGE(0x8c00, 0x8c00) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_port_w)
691		AM_RANGE(0x8c01, 0x8c01) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w)
	690	AM_RANGE(0x8c00, 0x8c00) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, master_port_w)
	691	AM_RANGE(0x8c01, 0x8c01) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w)
692	692	AM_RANGE(0xa000, 0xbfff) AM_RAM
693	693	ADDRESS_MAP_END
694	694
r29505	r29506
712	712	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank7")
713	713	AM_RANGE(0xc000, 0xdfff) AM_RAM
714	714	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
715		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
716		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	715	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	716	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
717	717	AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
718	718	AM_RANGE(0xe600, 0xe600) AM_WRITENOP /* ? */
719	719	AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
r29505	r29506
739	739	AM_RANGE(0xe004, 0xe004) AM_WRITE(control2_w)
740	740	AM_RANGE(0xe007, 0xe007) AM_READ_PORT("IN2")
741	741	AM_RANGE(0xe008, 0xe00f) AM_READNOP
742		AM_RANGE(0xe800, 0xe800) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_port_w)
743		AM_RANGE(0xe801, 0xe801) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w)
	742	AM_RANGE(0xe800, 0xe800) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, master_port_w)
	743	AM_RANGE(0xe801, 0xe801) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w)
744	744	AM_RANGE(0xf000, 0xf000) AM_READWRITE(rombank2switch_r, rombank2switch_w)
745	745	ADDRESS_MAP_END
746	746
r29505	r29506
749	749	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank7")
750	750	AM_RANGE(0x8000, 0x8fff) AM_RAM
751	751	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2203_device, read, write)
752		AM_RANGE(0xa000, 0xa000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
753		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	752	AM_RANGE(0xa000, 0xa000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	753	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
754	754	AM_RANGE(0xb000, 0xb000) AM_WRITE(champwr_msm5205_hi_w)
755	755	AM_RANGE(0xc000, 0xc000) AM_WRITE(champwr_msm5205_lo_w)
756	756	AM_RANGE(0xd000, 0xd000) AM_WRITE(champwr_msm5205_start_w)
r29505	r29506
1782	1782	};
1783	1783
1784	1784
1785		static const tc0140syt_interface taitol_tc0140syt_intf =
1786		{
1787		"slave", "audiocpu"
1788		};
1789
1790
1791	1785	static MACHINE_CONFIG_START( fhawk, taitol_state )
1792	1786
1793	1787	/* basic machine hardware */
r29505	r29506
1833	1827	MCFG_SOUND_ROUTE(2, "mono", 0.20)
1834	1828	MCFG_SOUND_ROUTE(3, "mono", 0.80)
1835	1829
1836		MCFG_TC0140SYT_ADD("tc0140syt", taitol_tc0140syt_intf)
	1830	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	1831	MCFG_TC0140SYT_MASTER_CPU("slave")
	1832	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
1837	1833	MACHINE_CONFIG_END
1838	1834
1839	1835
r29505	r29506
1926	1922	MCFG_SOUND_ROUTE(1, "mono", 0.20)
1927	1923	MCFG_SOUND_ROUTE(2, "mono", 0.20)
1928	1924	MCFG_SOUND_ROUTE(3, "mono", 0.80)
1929
1930		MCFG_TC0140SYT_ADD("tc0140syt", taitol_tc0140syt_intf)
1931	1925	MACHINE_CONFIG_END
1932	1926
1933	1927
r29505	r29506
1974	1968	MCFG_SOUND_ROUTE(1, "mono", 0.20)
1975	1969	MCFG_SOUND_ROUTE(2, "mono", 0.20)
1976	1970	MCFG_SOUND_ROUTE(3, "mono", 0.80)
1977
1978		MCFG_TC0140SYT_ADD("tc0140syt", taitol_tc0140syt_intf)
1979	1971	MACHINE_CONFIG_END
1980	1972
1981	1973
r29505	r29506
2067	2059	MCFG_SOUND_ROUTE(1, "mono", 0.25)
2068	2060	MCFG_SOUND_ROUTE(2, "mono", 0.25)
2069	2061	MCFG_SOUND_ROUTE(3, "mono", 0.80)
2070
2071		MCFG_TC0140SYT_ADD("tc0140syt", taitol_tc0140syt_intf)
2072	2062	MACHINE_CONFIG_END
2073	2063
2074	2064	#ifdef UNUSED_CODE

branches/new_menus/src/mame/drivers/sshangha.c

r29505	r29506
379	379	DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL
380	380	};
381	381
382		int sshangha_state::bank_callback( int bank )
	382	DECO16IC_BANK_CB_MEMBER(sshangha_state::bank_callback)
383	383	{
384	384	return (bank >> 4) * 0x1000;
385	385	}
r29505	r29506
424	424	MCFG_DECO16IC_PALETTE("palette")
425	425
426	426	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
427		decospr_device::set_gfx_region(*device, 2);
	427	MCFG_DECO_SPRITE_GFX_REGION(2)
428	428	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
429	429	MCFG_DECO_SPRITE_PALETTE("palette")
430	430
431	431	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
432		decospr_device::set_gfx_region(*device, 2);
	432	MCFG_DECO_SPRITE_GFX_REGION(2)
433	433	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
434	434	MCFG_DECO_SPRITE_PALETTE("palette")
435	435

branches/new_menus/src/mame/drivers/jpmimpct.c

r29505	r29506
1350	1350	MCFG_CPU_PROGRAM_MAP(awp68k_program_map)
1351	1351
1352	1352	MCFG_QUANTUM_TIME(attotime::from_hz(30000))
1353		MCFG_ROC10937_ADD("vfd",0,RIGHT_TO_LEFT)
	1353	MCFG_S16LF01_ADD("vfd",0)
1354	1354
1355	1355	MCFG_MACHINE_START_OVERRIDE(jpmimpct_state,impctawp)
1356	1356	MCFG_MACHINE_RESET_OVERRIDE(jpmimpct_state,impctawp)

branches/new_menus/src/mame/drivers/silvmil.c

r29505	r29506
329	329
330	330
331	331	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
332		decospr_device::set_gfx_region(*device, 0);
333		decospr_device::set_is_bootleg(*device, true);
334		decospr_device::set_offsets(*device, 5,7);
	332	MCFG_DECO_SPRITE_GFX_REGION(0)
	333	MCFG_DECO_SPRITE_ISBOOTLEG(true)
	334	MCFG_DECO_SPRITE_OFFSETS(5, 7)
335	335	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
336	336	MCFG_DECO_SPRITE_PALETTE("palette")
337	337

branches/new_menus/src/mame/drivers/maygay1bsw.c

r29505	r29506
2	2
3	3	/*
4	4	the MSM6376 is on the ROM board, so some games might not have it
5		the YM2149F is on the MAIN board
	5	the YM2149F is on the MAIN board, but it seems very rarely used for sound.
	6
	7	On various PCBs, I've seen the AY slot filled with AY8913's, 8910's,
	8	YM2419s and even AY8930s.
6	9
7	10	some of the sound roms we have look more like uPD7749 ones? did some
8	11	ROM boards use that instead?

branches/new_menus/src/mame/drivers/toaplan2.c

r29505	r29506
3933	3933	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
3934	3934	MACHINE_CONFIG_END
3935	3935
3936
3937		static const nmk112_interface bgaregga_nmk112_intf =
3938		{
3939		"oki", NULL, 0
3940		};
3941
3942		static const nmk112_interface batrider_nmk112_intf =
3943		{
3944		"oki1", "oki2", 0
3945		};
3946
3947
3948	3936	static MACHINE_CONFIG_START( bgaregga, toaplan2_state )
3949	3937
3950	3938	/* basic machine hardware */
r29505	r29506
3990	3978	MCFG_OKIM6295_ADD("oki", XTAL_32MHz/16, OKIM6295_PIN7_HIGH)
3991	3979	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
3992	3980
3993		MCFG_NMK112_ADD("nmk112", bgaregga_nmk112_intf)
	3981	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	3982	MCFG_NMK112_ROM0("oki")
3994	3983	MACHINE_CONFIG_END
3995	3984
3996	3985
r29505	r29506
4049	4038	MCFG_OKIM6295_ADD("oki2", XTAL_32MHz/10, OKIM6295_PIN7_LOW)
4050	4039	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
4051	4040
4052		MCFG_NMK112_ADD("nmk112", batrider_nmk112_intf)
	4041	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	4042	MCFG_NMK112_ROM0("oki1")
	4043	MCFG_NMK112_ROM1("oki2")
4053	4044	MACHINE_CONFIG_END
4054	4045
4055	4046

branches/new_menus/src/mame/drivers/rainbow.c

r29505	r29506
351	351	AM_RANGE(0x3a0000, 0x3a0001) AM_WRITE(rbisland_spritectrl_w)
352	352	AM_RANGE(0x3b0000, 0x3b0003) AM_READ_PORT("DSWB")
353	353	AM_RANGE(0x3c0000, 0x3c0003) AM_WRITENOP        /* written very often, watchdog? */
354		AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
355		AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r,tc0140syt_comm_w, 0x00ff)
	354	AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	355	AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
356	356	AM_RANGE(0x800000, 0x8007ff) AM_READWRITE(rbisland_cchip_ram_r,rbisland_cchip_ram_w)
357	357	AM_RANGE(0x800802, 0x800803) AM_READWRITE(rbisland_cchip_ctrl_r,rbisland_cchip_ctrl_w)
358	358	AM_RANGE(0x800c00, 0x800c01) AM_WRITE(rbisland_cchip_bank_w)
r29505	r29506
410	410	AM_RANGE(0x8000, 0x8fff) AM_RAM
411	411	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_device,read,write)
412	412	AM_RANGE(0x9002, 0x9100) AM_READNOP
413		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
414		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	413	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	414	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
415	415	ADDRESS_MAP_END
416	416
417	417	static ADDRESS_MAP_START( jumping_sound_map, AS_PROGRAM, 8, rbisland_state )
r29505	r29506
619	619	MACHINE DRIVERS
620	620	***********************************************************/
621	621
622		static const pc080sn_interface rbisland_pc080sn_intf =
623		{
624		1,   /* gfxnum */
625		0, 0, 0, 0  /* x_offset, y_offset, y_invert, dblwidth */
626		};
627
628		static const pc080sn_interface jumping_pc080sn_intf =
629		{
630		1,   /* gfxnum */
631		0, 0, 1, 0  /* x_offset, y_offset, y_invert, dblwidth */
632		};
633
634		static const pc090oj_interface rbisland_pc090oj_intf =
635		{
636		0, 0, 0, 0
637		};
638
639		static const tc0140syt_interface rbisland_tc0140syt_intf =
640		{
641		"maincpu", "audiocpu"
642		};
643
644	622	void rbisland_state::machine_start()
645	623	{
646	624	}
r29505	r29506
671	649	MCFG_PALETTE_ADD("palette", 8192)
672	650	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
673	651
674		MCFG_PC080SN_ADD("pc080sn", rbisland_pc080sn_intf)
	652	MCFG_DEVICE_ADD("pc080sn", PC080SN, 0)
	653	MCFG_PC080SN_GFX_REGION(1)
675	654	MCFG_PC080SN_GFXDECODE("gfxdecode")
676	655	MCFG_PC080SN_PALETTE("palette")
677		MCFG_PC090OJ_ADD("pc090oj", rbisland_pc090oj_intf)
	656
	657	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
678	658	MCFG_PC090OJ_GFXDECODE("gfxdecode")
679	659	MCFG_PC090OJ_PALETTE("palette")
680	660
r29505	r29506
687	667	MCFG_SOUND_ROUTE(0, "mono", 0.50)
688	668	MCFG_SOUND_ROUTE(1, "mono", 0.50)
689	669
690		MCFG_TC0140SYT_ADD("tc0140syt", rbisland_tc0140syt_intf)
	670	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	671	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	672	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
691	673	MACHINE_CONFIG_END
692	674
693	675
r29505	r29506
720	702
721	703	MCFG_VIDEO_START_OVERRIDE(rbisland_state,jumping)
722	704
723		MCFG_PC080SN_ADD("pc080sn", jumping_pc080sn_intf)
	705	MCFG_DEVICE_ADD("pc080sn", PC080SN, 0)
	706	MCFG_PC080SN_GFX_REGION(1)
	707	MCFG_PC080SN_YINVERT(1)
724	708	MCFG_PC080SN_GFXDECODE("gfxdecode")
725	709	MCFG_PC080SN_PALETTE("palette")
726	710

branches/new_menus/src/mame/drivers/crystal.c

r29505	r29506
900	900	0x04800000
901	901	};
902	902
903		static const vr0video_interface vr0video_config =
904		{
905		"maincpu"
906		};
907
908	903	static MACHINE_CONFIG_START( crystal, crystal_state )
909	904
910	905	MCFG_CPU_ADD("maincpu", SE3208, 43000000)
911	906	MCFG_CPU_PROGRAM_MAP(crystal_mem)
912	907	MCFG_CPU_VBLANK_INT_DRIVER("screen", crystal_state,  crystal_interrupt)
913	908
914
915	909	MCFG_NVRAM_ADD_0FILL("nvram")
916	910
917	911	MCFG_SCREEN_ADD("screen", RASTER)
r29505	r29506
923	917	MCFG_SCREEN_VBLANK_DRIVER(crystal_state, screen_eof_crystal)
924	918	MCFG_SCREEN_PALETTE("palette")
925	919
926		MCFG_VIDEO_VRENDER0_ADD("vr0", vr0video_config)
	920	MCFG_DEVICE_ADD("vr0", VIDEO_VRENDER0, 0)
	921	MCFG_VIDEO_VRENDER0_CPU("maincpu")
927	922
928	923	MCFG_PALETTE_ADD_RRRRRGGGGGGBBBBB("palette")
929	924
r29505	r29506
1144	1139	}
1145	1140
1146	1141
1147
1148
1149	1142	GAME( 2001, crysbios,        0, crystal,  crystal, driver_device,         0, ROT0, "BrezzaSoft", "Crystal System BIOS", GAME_IS_BIOS_ROOT )
1150	1143	GAME( 2001, crysking, crysbios, crystal,  crystal, crystal_state,  crysking, ROT0, "BrezzaSoft", "The Crystal of Kings", 0 )
1151	1144	GAME( 2001, evosocc,  crysbios, crystal,  crystal, crystal_state,  evosocc,  ROT0, "Evoga", "Evolution Soccer", 0 )

branches/new_menus/src/mame/drivers/famibox.c

r29505	r29506
526	526	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
527	527	}
528	528
529		/* our ppu interface                                            */
530		static const ppu2c0x_interface ppu_interface =
531		{
532		"maincpu",
533		0,                  /* gfxlayout num */
534		0,                  /* color base */
535		PPU_MIRROR_NONE     /* mirroring */
536		};
537
538	529	void famibox_state::video_start()
539	530	{
540	531	}
r29505	r29506
596	587	MCFG_PALETTE_ADD("palette", 8*4*16)
597	588	MCFG_PALETTE_INIT_OWNER(famibox_state, famibox)
598	589
599
600		MCFG_PPU2C04_ADD("ppu", ppu_interface)
	590	MCFG_PPU2C04_ADD("ppu")
	591	MCFG_PPU2C0X_CPU("maincpu")
601	592	MCFG_PPU2C0X_SET_NMI(famibox_state, ppu_irq)
602	593
603	594	/* sound hardware */

branches/new_menus/src/mame/drivers/cninja.c

r29505	r29506
785	785
786	786	/**********************************************************************************/
787	787
788		int cninja_state::cninja_bank_callback( int bank )
	788	DECO16IC_BANK_CB_MEMBER(cninja_state::cninja_bank_callback)
789	789	{
790	790	if ((bank >> 4) & 0xf)
791	791	return 0x0000; /* Only 2 banks */
792	792	return 0x1000;
793	793	}
794	794
795		int cninja_state::robocop2_bank_callback( int bank )
	795	DECO16IC_BANK_CB_MEMBER(cninja_state::robocop2_bank_callback)
796	796	{
797	797	return (bank & 0x30) << 8;
798	798	}
799	799
800		int cninja_state::mutantf_1_bank_callback( int bank )
	800	DECO16IC_BANK_CB_MEMBER(cninja_state::mutantf_1_bank_callback)
801	801	{
802	802	return ((bank >> 4) & 0x3) << 12;
803	803	}
804	804
805		int cninja_state::mutantf_2_bank_callback( int bank )
	805	DECO16IC_BANK_CB_MEMBER(cninja_state::mutantf_2_bank_callback)
806	806	{
807	807	return ((bank >> 5) & 0x1) << 14;
808	808	}
809	809
810	810
811		void cninja_state::machine_start()
	811	DECOSPR_PRIORITY_CB_MEMBER(cninja_state::pri_callback)
812	812	{
813		save_item(NAME(m_scanline));
814		save_item(NAME(m_irq_mask));
815		}
816
817		void cninja_state::machine_reset()
818		{
819		m_scanline = 0;
820		m_irq_mask = 0;
821		}
822
823
824		UINT16 cninja_pri_callback(UINT16 x)
825		{
826	813	/* Sprite/playfield priority */
827		switch (x & 0xc000)
	814	switch (pri & 0xc000)
828	815	{
829	816	case 0x0000: return 0;
830	817	case 0x4000: return 0xf0;
831	818	case 0x8000: return 0xf0 | 0xcc;
832	819	case 0xc000: return 0xf0 | 0xcc; /* Perhaps 0xf0|0xcc|0xaa (Sprite under bottom layer) */
833	820	}
834
	821
835	822	return 0;
836	823	}
837	824
838	825
	826	void cninja_state::machine_start()
	827	{
	828	save_item(NAME(m_scanline));
	829	save_item(NAME(m_irq_mask));
	830	}
	831
	832	void cninja_state::machine_reset()
	833	{
	834	m_scanline = 0;
	835	m_irq_mask = 0;
	836	}
	837
839	838	static MACHINE_CONFIG_START( cninja, cninja_state )
840	839
841	840	/* basic machine hardware */
r29505	r29506
896	895	MCFG_DECO16IC_PALETTE("palette")
897	896
898	897	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
899		decospr_device::set_gfx_region(*device, 3);
900		decospr_device::set_pri_callback(*device, cninja_pri_callback);
	898	MCFG_DECO_SPRITE_GFX_REGION(3)
	899	MCFG_DECO_SPRITE_PRIORITY_CB(cninja_state, pri_callback)
901	900	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
902	901	MCFG_DECO_SPRITE_PALETTE("palette")
903	902
r29505	r29506
986	985	MCFG_DECO16IC_PALETTE("palette")
987	986
988	987	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
989		decospr_device::set_gfx_region(*device, 3);
990		decospr_device::set_pri_callback(*device, cninja_pri_callback);
	988	MCFG_DECO_SPRITE_GFX_REGION(3)
	989	MCFG_DECO_SPRITE_PRIORITY_CB(cninja_state, pri_callback)
991	990	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
992	991	MCFG_DECO_SPRITE_PALETTE("palette")
993	992
r29505	r29506
1143	1142	MCFG_DECO16IC_PALETTE("palette")
1144	1143
1145	1144	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
1146		decospr_device::set_gfx_region(*device, 3);
1147		decospr_device::set_pri_callback(*device, cninja_pri_callback);
	1145	MCFG_DECO_SPRITE_GFX_REGION(3)
	1146	MCFG_DECO_SPRITE_PRIORITY_CB(cninja_state, pri_callback)
1148	1147	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1149	1148	MCFG_DECO_SPRITE_PALETTE("palette")
1150	1149
r29505	r29506
1231	1230	MCFG_DECO16IC_PALETTE("palette")
1232	1231
1233	1232	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
1234		decospr_device::set_gfx_region(*device, 3);
1235		decospr_device::set_pri_callback(*device, cninja_pri_callback);
	1233	MCFG_DECO_SPRITE_GFX_REGION(3)
	1234	MCFG_DECO_SPRITE_PRIORITY_CB(cninja_state, pri_callback)
1236	1235	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1237	1236	MCFG_DECO_SPRITE_PALETTE("palette")
1238	1237
r29505	r29506
1325	1324	MCFG_DECO16IC_PALETTE("palette")
1326	1325
1327	1326	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
1328		decospr_device::set_gfx_region(*device, 3);
	1327	MCFG_DECO_SPRITE_GFX_REGION(3)
1329	1328	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1330	1329	MCFG_DECO_SPRITE_PALETTE("palette")
1331	1330
1332	1331	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
1333		decospr_device::set_gfx_region(*device, 4);
	1332	MCFG_DECO_SPRITE_GFX_REGION(4)
1334	1333	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1335	1334	MCFG_DECO_SPRITE_PALETTE("palette")
1336	1335

branches/new_menus/src/mame/drivers/taitoair.c

r29505	r29506
403	403	AM_RANGE(0xa00000, 0xa00007) AM_READ(stick_input_r)
404	404	AM_RANGE(0xa00100, 0xa00107) AM_READ(stick2_input_r)
405	405	AM_RANGE(0xa00200, 0xa0020f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff) /* other I/O */
406		AM_RANGE(0xa80000, 0xa80001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
407		AM_RANGE(0xa80002, 0xa80003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	406	AM_RANGE(0xa80000, 0xa80001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	407	AM_RANGE(0xa80002, 0xa80003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
408	408	AM_RANGE(0xb00000, 0xb007ff) AM_RAM                     /* "power common ram" (mecha drive) */
409	409	ADDRESS_MAP_END
410	410
r29505	r29506
415	415	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
416	416	AM_RANGE(0xc000, 0xdfff) AM_RAM
417	417	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
418		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
419		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	418	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	419	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
420	420	AM_RANGE(0xe400, 0xe403) AM_WRITENOP        /* pan control */
421	421	AM_RANGE(0xea00, 0xea00) AM_READNOP
422	422	AM_RANGE(0xee00, 0xee00) AM_WRITENOP        /* ? */
r29505	r29506
638	638	MACHINE DRIVERS
639	639	************************************************************/
640	640
641		static const tc0080vco_interface airsys_tc0080vco_intf =
642		{
643		0, 1,   /* gfxnum, txnum */
644		1, 1, -2,
645		0
646		};
647
648		static const tc0140syt_interface airsys_tc0140syt_intf =
649		{
650		"maincpu", "audiocpu"
651		};
652
653	641	void taitoair_state::machine_start()
654	642	{
655	643	UINT8 *ROM = memregion("audiocpu")->base();
r29505	r29506
721	709
722	710	MCFG_PALETTE_ADD_INIT_BLACK("palette", 512*16+512*16)
723	711
724		MCFG_TC0080VCO_ADD("tc0080vco", airsys_tc0080vco_intf)
	712	MCFG_DEVICE_ADD("tc0080vco", TC0080VCO, 0)
	713	MCFG_TC0080VCO_GFX_REGION(0)
	714	MCFG_TC0080VCO_TX_REGION(1)
	715	MCFG_TC0080VCO_OFFSETS(1, 1)
	716	MCFG_TC0080VCO_BGFLIP_OFFS(-2)
725	717	MCFG_TC0080VCO_GFXDECODE("gfxdecode")
726	718	MCFG_TC0080VCO_PALETTE("palette")
727	719
r29505	r29506
734	726	MCFG_SOUND_ROUTE(1, "mono", 0.60)
735	727	MCFG_SOUND_ROUTE(2, "mono", 0.60)
736	728
737		MCFG_TC0140SYT_ADD("tc0140syt", airsys_tc0140syt_intf)
	729	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	730	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	731	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
738	732	MACHINE_CONFIG_END
739	733
740	734

branches/new_menus/src/mame/drivers/maygayv1.c

r29505	r29506
128	128	#include "cpu/m68000/m68000.h"
129	129	#include "video/awpvid.h"
130	130	#include "cpu/mcs51/mcs51.h"
	131	#include "machine/i8279.h"
131	132	#include "machine/6821pia.h"
132	133	#include "machine/mc68681.h"
133	134	#include "sound/2413intf.h"
r29505	r29506
202	203	};
203	204
204	205
205		struct i8279_t
206		{
207		UINT8   command;
208		UINT8   mode;
209		UINT8   prescale;
210		UINT8   inhibit;
211		UINT8   clear;
212		UINT8   fifo[8];
213		UINT8   ram[16];
214		};
215
216	206	class maygayv1_state : public driver_device
217	207	{
218	208	public:
r29505	r29506
230	220	required_device<mc68681_device> m_duart68681;
231	221	required_device<palette_device> m_palette;
232	222
	223	int m_lamp_strobe;
	224	int m_old_lamp_strobe;
233	225	int m_vsync_latch_preset;
234	226	UINT8 m_p1;
235	227	UINT8 m_p3;
236	228	int m_d68681_val;
237	229	i82716_t m_i82716;
238		i8279_t m_i8279;
239	230	DECLARE_WRITE16_MEMBER(i82716_w);
240	231	DECLARE_READ16_MEMBER(i82716_r);
241	232	DECLARE_WRITE16_MEMBER(write_odd);
242	233	DECLARE_READ16_MEMBER(read_odd);
243		DECLARE_READ16_MEMBER(maygay_8279_r);
244		DECLARE_WRITE16_MEMBER(maygay_8279_w);
245	234	DECLARE_WRITE16_MEMBER(vsync_int_ctrl);
246	235	DECLARE_READ8_MEMBER(mcu_r);
247	236	DECLARE_WRITE8_MEMBER(mcu_w);
248	237	DECLARE_READ8_MEMBER(b_read);
249	238	DECLARE_WRITE8_MEMBER(b_writ);
	239	DECLARE_WRITE8_MEMBER(strobe_w);
	240	DECLARE_WRITE8_MEMBER(lamp_data_w);
	241	DECLARE_READ8_MEMBER(kbd_r);
250	242	DECLARE_DRIVER_INIT(screenpl);
251	243	virtual void machine_start();
252	244	virtual void machine_reset();
r29505	r29506
506	498	return 0;
507	499	}
508	500
	501	/*************************************
	502	*
	503	*  8279 display/keyboard driver
	504	*
	505	*************************************/
509	506
510		/* TODO */
511		static void update_outputs(i8279_t &i8279, UINT16 which)
	507	WRITE8_MEMBER( maygayv1_state::strobe_w )
512	508	{
513		int i;
514
515		/* update the items in the bitmask */
516		for (i = 0; i < 16; i++)
517		if (which & (1 << i))
518		{
519		/*
520		int val;
521
522		val = i8279.ram[i] & 0xff;
523
524		val = i8279.ram[i] & 0x0f;
525		if (i8279.inhibit & 0x01)
526		val = i8279.clear & 0x0f;
527
528		if(val) printf("%x\n", val);
529
530		val = i8279.ram[i] >> 4;
531		if (i8279.inhibit & 0x02)
532		val = i8279.clear >> 4;
533
534		if(val) printf("%x\n", val);
535		*/
536		}
	509	m_lamp_strobe = data;
537	510	}
538	511
539		READ16_MEMBER(maygayv1_state::maygay_8279_r)
	512	WRITE8_MEMBER( maygayv1_state::lamp_data_w )
540	513	{
541		i8279_t &i8279 = m_i8279;
542		static const char *const portnames[] = { "STROBE1","STROBE2","STROBE3","STROBE4","STROBE5","STROBE6","STROBE7","STROBE8" };
543		UINT8 result = 0xff;
544		UINT8 addr;
545
546		/* read data */
547		if ((offset & 1) == 0)
	514	//The two A/B ports are merged back into one, to make one row of 8 lamps.
	515
	516	if (m_old_lamp_strobe != m_lamp_strobe)
548	517	{
549		switch (i8279.command & 0xe0)
550		{
551		/* read sensor RAM */
552		case 0x40:
553		addr = i8279.command & 0x07;
	518	// Because of the nature of the lamping circuit, there is an element of persistance
	519	// As a consequence, the lamp column data can change before the input strobe without
	520	// causing the relevant lamps to black out.
554	521
555		result = ioport(portnames[addr])->read();
556
557		/* handle autoincrement */
558		if (i8279.command & 0x10)
559		i8279.command = (i8279.command & 0xf0) | ((addr + 1) & 0x0f);
560
561		break;
562
563		/* read display RAM */
564		case 0x60:
565
566		/* set the value of the corresponding outputs */
567		addr = i8279.command & 0x0f;
568		result = i8279.ram[addr];
569
570		/* handle autoincrement */
571		if (i8279.command & 0x10)
572		i8279.command = (i8279.command & 0xf0) | ((addr + 1) & 0x0f);
573		break;
	522	for (int i = 0; i < 8; i++)
	523	{
	524	output_set_lamp_value((8*m_lamp_strobe)+i, ((data  & (1 << i)) !=0));
574	525	}
	526	m_old_lamp_strobe = m_lamp_strobe;
575	527	}
576		/* read status word */
577		else
578		{
579		printf("read 0xfc%02x\n", offset);
580		result = 0x10;
581		}
582		return result;
	528
583	529	}
584	530
585
586		WRITE16_MEMBER(maygayv1_state::maygay_8279_w)
	531	READ8_MEMBER( maygayv1_state::kbd_r )
587	532	{
588		i8279_t &i8279 = m_i8279;
589		UINT8 addr;
	533	static const char *const portnames[] = { "STROBE1","STROBE2","STROBE3","STROBE4","STROBE5","STROBE6","STROBE7","STROBE8" };
590	534
591		data >>= 8;
592
593		/* write data */
594		if ((offset & 1) == 0)
595		{
596		switch (i8279.command & 0xe0)
597		{
598		/* write display RAM */
599		case 0x80:
600
601		/* set the value of the corresponding outputs */
602		addr = i8279.command & 0x0f;
603		if (!(i8279.inhibit & 0x04))
604		i8279.ram[addr] = (i8279.ram[addr] & 0xf0) | (data & 0x0f);
605		if (!(i8279.inhibit & 0x08))
606		i8279.ram[addr] = (i8279.ram[addr] & 0x0f) | (data & 0xf0);
607		update_outputs(i8279, 1 << addr);
608
609		/* handle autoincrement */
610		if (i8279.command & 0x10)
611		i8279.command = (i8279.command & 0xf0) | ((addr + 1) & 0x0f);
612		break;
613		}
614		}
615
616		/* write command */
617		else
618		{
619		i8279.command = data;
620
621		switch (data & 0xe0)
622		{
623		/* command 0: set mode */
624		/*
625		Display modes:
626
627		00 = 8 x 8-bit character display -- left entry
628		01 = 16 x 8-bit character display -- left entry
629		10 = 8 x 8-bit character display -- right entry
630		11 = 16 x 8-bit character display -- right entry
631
632		Keyboard modes:
633
634		000 = Encoded scan keyboard -- 2 key lockout
635		001 = Decoded scan keyboard -- 2 key lockout
636		010 = Encoded scan keyboard -- N-key rollover
637		011 = Decoded scan keyboard -- N-key rollover
638		100 = Encoded scan sensor matrix
639		101 = Decoded scan sensor matrix
640		110 = Strobed input, encoded display scan
641		111 = Strobed input, decoded display scan
642		*/
643		case 0x00:
644		logerror("8279: display mode = %d, keyboard mode = %d\n", (data >> 3) & 3, data & 7);
645		i8279.mode = data & 0x1f;
646		break;
647
648		/* command 1: program clock */
649		case 0x20:
650		logerror("8279: clock prescaler set to %02X\n", data & 0x1f);
651		i8279.prescale = data & 0x1f;
652		break;
653
654		/* command 2: read FIFO/sensor RAM */
655		/* command 3: read display RAM */
656		/* command 4: write display RAM */
657		case 0x40:
658		case 0x60:
659		case 0x80:
660		break;
661
662		/* command 5: display write inhibit/blanking */
663		case 0xa0:
664		i8279.inhibit = data & 0x0f;
665		update_outputs(i8279, ~0);
666		logerror("8279: clock prescaler set to %02X\n", data & 0x1f);
667		break;
668
669		/* command 6: clear */
670		case 0xc0:
671		i8279.clear = (data & 0x08) ? ((data & 0x04) ? 0xff : 0x20) : 0x00;
672		if (data & 0x11)
673		memset(i8279.ram, i8279.clear, sizeof(i8279.ram));
674		break;
675
676		/* command 7: end interrupt/error mode set */
677		case 0xe0:
678		break;
679		}
680		}
	535	return ioport(portnames[m_lamp_strobe&0x07])->read();
681	536	}
682	537
	538	/*
	539	static I8279_INTERFACE( v1_i8279_intf )
	540	{
	541	DEVCB_NULL,                                     // irq
	542	DEVCB_DRIVER_MEMBER(maygayv1_state, strobe_w),  // scan SL lines
	543	DEVCB_DRIVER_MEMBER(maygayv1_state, lamp_data_w),      // display A&B
	544	DEVCB_NULL,                                     // BD
	545	DEVCB_DRIVER_MEMBER(maygayv1_state,kbd_r),      // kbd RL lines
	546	DEVCB_NULL,                                     // Shift key
	547	DEVCB_NULL                                      // Ctrl-Strobe line
	548	};
	549	*/
683	550
	551
684	552	WRITE16_MEMBER(maygayv1_state::vsync_int_ctrl)
685	553	{
686	554	m_vsync_latch_preset = data & 0x0100;
r29505	r29506
694	562	AM_RANGE(0x000000, 0x07ffff) AM_ROM
695	563	AM_RANGE(0x080000, 0x083fff) AM_RAM AM_SHARE("nvram")
696	564	AM_RANGE(0x100000, 0x17ffff) AM_ROM AM_REGION("maincpu", 0x80000)
697		AM_RANGE(0x820000, 0x820003) AM_READWRITE(maygay_8279_r, maygay_8279_w)
	565	AM_RANGE(0x820000, 0x820001) AM_DEVREADWRITE8("i8279", i8279_device, data_r, data_w ,0xff)
	566	AM_RANGE(0x820002, 0x820003) AM_DEVREADWRITE8("i8279", i8279_device, status_r, cmd_w,0xff)
698	567	AM_RANGE(0x800000, 0x800003) AM_DEVWRITE8("ymsnd", ym2413_device, write, 0xff00)
699	568	AM_RANGE(0x860000, 0x86000d) AM_READWRITE(read_odd, write_odd)
700	569	AM_RANGE(0x86000e, 0x86000f) AM_WRITE(vsync_int_ctrl)
r29505	r29506
1041	910	MCFG_MC68681_IRQ_CALLBACK(WRITELINE(maygayv1_state, duart_irq_handler))
1042	911	MCFG_MC68681_A_TX_CALLBACK(WRITELINE(maygayv1_state, duart_txa))
1043	912
	913	MCFG_DEVICE_ADD("i8279", I8279, MASTER_CLOCK/4)    // unknown clock
	914	//   MCFG_I8279_ADD("i8279", MASTER_CLOCK/4, v1_i8279_intf)    // unknown clock
	915
1044	916	MCFG_SPEAKER_STANDARD_MONO("mono")
1045	917
1046	918	MCFG_SOUND_ADD("ymsnd",YM2413, MASTER_CLOCK / 4)

branches/new_menus/src/mame/drivers/volfied.c

r29505	r29506
70	70	AM_RANGE(0x600000, 0x600001) AM_WRITE(volfied_video_mask_w)
71	71	AM_RANGE(0x700000, 0x700001) AM_WRITE(volfied_sprite_ctrl_w)
72	72	AM_RANGE(0xd00000, 0xd00001) AM_READWRITE(volfied_video_ctrl_r, volfied_video_ctrl_w)
73		AM_RANGE(0xe00000, 0xe00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
74		AM_RANGE(0xe00002, 0xe00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	73	AM_RANGE(0xe00000, 0xe00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	74	AM_RANGE(0xe00002, 0xe00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
75	75	AM_RANGE(0xf00000, 0xf007ff) AM_READWRITE(volfied_cchip_ram_r, volfied_cchip_ram_w)
76	76	AM_RANGE(0xf00802, 0xf00803) AM_READWRITE(volfied_cchip_ctrl_r, volfied_cchip_ctrl_w)
77	77	AM_RANGE(0xf00c00, 0xf00c01) AM_WRITE(volfied_cchip_bank_w)
r29505	r29506
80	80	static ADDRESS_MAP_START( z80_map, AS_PROGRAM, 8, volfied_state )
81	81	AM_RANGE(0x0000, 0x7fff) AM_ROM
82	82	AM_RANGE(0x8000, 0x87ff) AM_RAM
83		AM_RANGE(0x8800, 0x8800) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
84		AM_RANGE(0x8801, 0x8801) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	83	AM_RANGE(0x8800, 0x8800) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	84	AM_RANGE(0x8801, 0x8801) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
85	85	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2203_device, read, write)
86	86	AM_RANGE(0x9800, 0x9800) AM_WRITENOP    /* ? */
87	87	ADDRESS_MAP_END
r29505	r29506
235	235	volfied_cchip_reset();
236	236	}
237	237
238		static const pc090oj_interface volfied_pc090oj_intf =
239		{
240		0, 0, 0, 0
241		};
242
243		static const tc0140syt_interface volfied_tc0140syt_intf =
244		{
245		"maincpu", "audiocpu"
246		};
247
248	238	static MACHINE_CONFIG_START( volfied, volfied_state )
249	239
250	240	/* basic machine hardware */
r29505	r29506
271	261	MCFG_PALETTE_ADD("palette", 8192)
272	262	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
273	263
274		MCFG_PC090OJ_ADD("pc090oj", volfied_pc090oj_intf)
	264	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
275	265	MCFG_PC090OJ_GFXDECODE("gfxdecode")
276	266	MCFG_PC090OJ_PALETTE("palette")
277	267
r29505	r29506
286	276	MCFG_SOUND_ROUTE(2, "mono", 0.15)
287	277	MCFG_SOUND_ROUTE(3, "mono", 0.60)
288	278
289		MCFG_TC0140SYT_ADD("tc0140syt", volfied_tc0140syt_intf)
	279	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	280	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	281	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
290	282	MACHINE_CONFIG_END
291	283
292	284

branches/new_menus/src/mame/drivers/esd16.c

r29505	r29506
592	592	m_tilemap0_color = 0;
593	593	}
594	594
595		UINT16 esd16_state::hedpanic_pri_callback(UINT16 x)
	595	DECOSPR_PRIORITY_CB_MEMBER(esd16_state::hedpanic_pri_callback)
596	596	{
597		if (x & 0x8000)
	597	if (pri & 0x8000)
598	598	return 0xfffe; // under "tilemap 1"
599	599	else
600	600	return 0; // above everything
r29505	r29506
623	623	MCFG_SCREEN_PALETTE("palette")
624	624
625	625	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
626		decospr_device::set_gfx_region(*device, 0);
627		decospr_device::set_is_bootleg(*device, true);
628		decospr_device::set_pri_callback(*device, esd16_state::hedpanic_pri_callback);
629		decospr_device::set_flipallx(*device, 1);
	626	MCFG_DECO_SPRITE_GFX_REGION(0)
	627	MCFG_DECO_SPRITE_ISBOOTLEG(true)
	628	MCFG_DECO_SPRITE_PRIORITY_CB(esd16_state, hedpanic_pri_callback)
	629	MCFG_DECO_SPRITE_FLIPALLX(1)
630	630	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
631	631	MCFG_DECO_SPRITE_PALETTE("palette")
632	632
r29505	r29506
679	679
680	680	static MACHINE_CONFIG_DERIVED( hedpanic, hedpanio )
681	681	MCFG_DEVICE_MODIFY("spritegen")
682		decospr_device::set_offsets(*device, -0x18,-0x100);
	682	MCFG_DECO_SPRITE_OFFSETS(-0x18, -0x100)
683	683	MACHINE_CONFIG_END
684	684
685	685	/* ESD 08-26-1999 PCBs with different memory maps */

branches/new_menus/src/mame/drivers/superchs.c

r29505	r29506
312	312	MACHINE DRIVERS
313	313	***********************************************************/
314	314
315		static const tc0480scp_interface superchs_tc0480scp_intf =
316		{
317		1, 2,       /* gfxnum, txnum */
318		0,          /* pixels */
319		0x20, 0x08, /* x_offset, y_offset */
320		-1, 0,      /* text_xoff, text_yoff */
321		0, 0,       /* flip_xoff, flip_yoff */
322		0           /* col_base */
323		};
324
325	315	static MACHINE_CONFIG_START( superchs, superchs_state )
326	316
327	317	/* basic machine hardware */
r29505	r29506
349	339	MCFG_GFXDECODE_ADD("gfxdecode", "palette", superchs)
350	340	MCFG_PALETTE_ADD("palette", 8192)
351	341
352
353		MCFG_TC0480SCP_ADD("tc0480scp", superchs_tc0480scp_intf)
	342	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	343	MCFG_TC0480SCP_GFX_REGION(1)
	344	MCFG_TC0480SCP_TX_REGION(2)
	345	MCFG_TC0480SCP_OFFSETS(0x20, 0x08)
	346	MCFG_TC0480SCP_OFFSETS_TX(-1, 0)
354	347	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
355	348	MCFG_TC0480SCP_PALETTE("palette")
356	349

branches/new_menus/src/mame/drivers/xexex.c

r29505	r29506
460	460	ym_set_mixing
461	461	};
462	462
463		static const k054338_interface xexex_k054338_intf =
464		{
465		0,
466		"none"
467		};
468
469	463	static const k056832_interface xexex_k056832_intf =
470	464	{
471	465	"gfx1", 0,
r29505	r29506
570	564	MCFG_K053246_PALETTE("palette")
571	565	MCFG_K053250_ADD("k053250", "palette", "screen", -5, -16)
572	566	MCFG_K053251_ADD("k053251")
	567
573	568	MCFG_DEVICE_ADD("k053252", K053252, XTAL_32MHz/4)
574		MCFG_K054338_ADD("k054338", xexex_k054338_intf)
575	569
	570	MCFG_DEVICE_ADD("k054338", K054338, 0)
	571
576	572	/* sound hardware */
577	573	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
578	574

branches/new_menus/src/mame/drivers/skylncr.c

r29505	r29506
1133	1133	1x HM6116LP-4
1134	1134	5x HM6116L-120
1135	1135
1136		One extra ROM (u48) is blank.
1137		Sure is the one that store the palette at offset $C000,
1138		among the missing graphics.
	1136	Unfortunately, one extra ROM (u48) is blank.
	1137	Seems to be the one that store the palette at offset $C000.
1139	1138
1140		Also graphics ROMs are half the standard size and
1141		they lack of at least 4 extra big girl pictures.
1142
1143	1139	BP 170 to see the palette registers...
1144	1140
1145	1141	*/
r29505	r29506
1148	1144	ROM_LOAD( "27256.u15",    0x0000, 0x8000, CRC(a5da4f92) SHA1(82ac70bd379649f130db017aa226d0247db0f3cd) )
1149	1145	ROM_LOAD( "unknown.u48",  0x8000, 0x8000, BAD_DUMP CRC(9f4c02e3) SHA1(05975184130ea7dd3bb5d32eff77b585bd53e6b5) )   // palette borrowed from other game
1150	1146
1151		ROM_REGION( 0x40000, "gfx1", 0 )    // All ROMs are 28-pins mask ROMs dumped as 27512. Should be dumped as Fujitsu MB831000 or TC531000 (mask ROM).
1152		ROM_LOAD16_BYTE( "bor_dun_4.u23", 0x00000, 0x10000, BAD_DUMP CRC(82c9db19) SHA1(3611fb59bb7c962c7fabe7a29fa72b632fa69bed) )
1153		ROM_LOAD16_BYTE( "bor_dun_2.u25", 0x00001, 0x10000, BAD_DUMP CRC(42ee9b7a) SHA1(b39f677f58072ea7dcd7f49208be1a7b70bdc5e5) )
1154		ROM_LOAD16_BYTE( "bor_dun_3.u24", 0x20000, 0x10000, BAD_DUMP CRC(6d70879b) SHA1(83cbe67cda95e5f3d95065015f6b1b2044b88989) )
1155		ROM_LOAD16_BYTE( "bor_dun_1.u26", 0x20001, 0x10000, BAD_DUMP CRC(1b8b84ac) SHA1(b914bad0b1fb58cf581d1227e8127c6afb906fb7) )
	1147	ROM_REGION( 0x80000, "gfx1", 0 )    // All ROMs are 28-pins mask ROMs dumped as Fujitsu MB831000 or TC531000 (mask ROM).
	1148	ROM_LOAD16_BYTE( "bor_dun_4.u23", 0x00000, 0x20000, CRC(d0d0ead1) SHA1(00bfe691cb9020c5d7e21d80a1e059ea2155aad8) )
	1149	ROM_LOAD16_BYTE( "bor_dun_2.u25", 0x00001, 0x20000, CRC(2b0f07b5) SHA1(9bcde623e53697c4b68d2f083f6254596aee64eb) )
	1150	ROM_LOAD16_BYTE( "bor_dun_3.u24", 0x40000, 0x20000, CRC(3c7da3f1) SHA1(8098b33a779fb697984b97f2d7edb9874e6e19d9) )
	1151	ROM_LOAD16_BYTE( "bor_dun_1.u26", 0x40001, 0x20000, CRC(36efdca6) SHA1(e614fbba77e5c7a1e7a1d2970b4f945ee0468196) )
1156	1152
1157		ROM_REGION( 0x40000, "gfx2", 0 )    // All ROMs are 28-pins mask ROMs dumped as 27512. Should be dumped as Fujitsu MB831000 or TC531000 (mask ROM).
1158		ROM_LOAD16_BYTE( "bor_dun_8.u19", 0x00000, 0x10000, BAD_DUMP CRC(daf651a7) SHA1(d4e472aa90aa2b52c997b2f2272007b139e3cbc2) )
1159		ROM_LOAD16_BYTE( "bor_dun_6.u21", 0x00001, 0x10000, BAD_DUMP CRC(1d88bc70) SHA1(49246d96a4ce2b8e9b10e928d7dd13973feac883) )
1160		ROM_LOAD16_BYTE( "bor_dun_7.u20", 0x20000, 0x10000, BAD_DUMP CRC(7e28ba2f) SHA1(ac8d4e95efce87456f569a71650bd7afcb59095e) )
1161		ROM_LOAD16_BYTE( "bor_dun_5.u22", 0x20001, 0x10000, BAD_DUMP CRC(52f98575) SHA1(b786c441d5ef47ff4cb50835c6ac6889cb169c6e) )
	1153	ROM_REGION( 0x80000, "gfx2", 0 )    // All ROMs are 28-pins mask ROMs dumped as Fujitsu MB831000 or TC531000 (mask ROM).
	1154	ROM_LOAD16_BYTE( "bor_dun_8.u19", 0x00000, 0x20000, CRC(adf0b7ce) SHA1(41d9fb16eb20e1fd2960117b7e4ea23a97b88961) )
	1155	ROM_LOAD16_BYTE( "bor_dun_6.u21", 0x00001, 0x20000, CRC(37be2cbe) SHA1(78acda58aab605cb992c3b9fbaf18d38f768ed1a) )
	1156	ROM_LOAD16_BYTE( "bor_dun_7.u20", 0x40000, 0x20000, CRC(43908665) SHA1(41b9cee0723d9da6934ab7934012fb1625a8f080) )
	1157	ROM_LOAD16_BYTE( "bor_dun_5.u22", 0x40001, 0x20000, CRC(ca17a632) SHA1(d491310ccdbe9b59a1e607f9254646f20700d79d) )
1162	1158	ROM_END
1163	1159
1164	1160

branches/new_menus/src/mame/drivers/slapshot.c

r29505	r29506
257	257	WRITE16_MEMBER(slapshot_state::slapshot_msb_sound_w)
258	258	{
259	259	if (offset == 0)
260		m_tc0140syt->tc0140syt_port_w(space, 0, (data >> 8) & 0xff);
	260	m_tc0140syt->master_port_w(space, 0, (data >> 8) & 0xff);
261	261	else if (offset == 1)
262		m_tc0140syt->tc0140syt_comm_w(space, 0, (data >> 8) & 0xff);
	262	m_tc0140syt->master_comm_w(space, 0, (data >> 8) & 0xff);
263	263
264	264	#ifdef MAME_DEBUG
265	265	if (data & 0xff)
r29505	r29506
270	270	READ16_MEMBER(slapshot_state::slapshot_msb_sound_r)
271	271	{
272	272	if (offset == 1)
273		return ((m_tc0140syt->tc0140syt_comm_r(space, 0) & 0xff) << 8);
	273	return ((m_tc0140syt->master_comm_r(space, 0) & 0xff) << 8);
274	274	else
275	275	return 0;
276	276	}
r29505	r29506
319	319	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank10")
320	320	AM_RANGE(0xc000, 0xdfff) AM_RAM
321	321	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
322		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
323		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	322	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	323	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
324	324	AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
325	325	AM_RANGE(0xea00, 0xea00) AM_READNOP
326	326	AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
r29505	r29506
491	491	MACHINE DRIVERS
492	492	***********************************************************/
493	493
494		static const tc0480scp_interface slapshot_tc0480scp_intf =
495		{
496		1, 2,       /* gfxnum, txnum */
497		3,      /* pixels */
498		30, 9,      /* x_offset, y_offset */
499		-1, 1,      /* text_xoff, text_yoff */
500		0, 2,       /* flip_xoff, flip_yoff */
501		256     /* col_base */
502		};
503
504		static const tc0140syt_interface slapshot_tc0140syt_intf =
505		{
506		"maincpu", "audiocpu"
507		};
508
509	494	void slapshot_state::machine_start()
510	495	{
511	496	membank("bank10")->configure_entries(0, 4, memregion("audiocpu")->base() + 0xc000, 0x4000);
r29505	r29506
547	532	MCFG_GFXDECODE_ADD("gfxdecode", "palette", slapshot)
548	533	MCFG_PALETTE_ADD("palette", 8192)
549	534
550
551		MCFG_TC0480SCP_ADD("tc0480scp", slapshot_tc0480scp_intf)
	535	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	536	MCFG_TC0480SCP_GFX_REGION(1)
	537	MCFG_TC0480SCP_TX_REGION(2)
	538	MCFG_TC0480SCP_OFFSETS(30 + 3, 9)
	539	MCFG_TC0480SCP_OFFSETS_TX(-1, -1)
	540	MCFG_TC0480SCP_OFFSETS_FLIP(0, 2)
	541	MCFG_TC0480SCP_COL_BASE(256)
552	542	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
553	543	MCFG_TC0480SCP_PALETTE("palette")
	544
554	545	MCFG_TC0360PRI_ADD("tc0360pri")
555	546
556	547	/* sound hardware */
r29505	r29506
565	556
566	557	MCFG_MK48T08_ADD( "mk48t08" )
567	558
568		MCFG_TC0140SYT_ADD("tc0140syt", slapshot_tc0140syt_intf)
	559	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	560	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	561	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
569	562	MACHINE_CONFIG_END
570	563
571	564	static MACHINE_CONFIG_START( opwolf3, slapshot_state )
r29505	r29506
599	592	MCFG_GFXDECODE_ADD("gfxdecode", "palette", slapshot)
600	593	MCFG_PALETTE_ADD("palette", 8192)
601	594
602
603		MCFG_TC0480SCP_ADD("tc0480scp", slapshot_tc0480scp_intf)
	595	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	596	MCFG_TC0480SCP_GFX_REGION(1)
	597	MCFG_TC0480SCP_TX_REGION(2)
	598	MCFG_TC0480SCP_OFFSETS(30 + 3, 9)
	599	MCFG_TC0480SCP_OFFSETS_TX(-1, -1)
	600	MCFG_TC0480SCP_OFFSETS_FLIP(0, 2)
	601	MCFG_TC0480SCP_COL_BASE(256)
604	602	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
605	603	MCFG_TC0480SCP_PALETTE("palette")
	604
606	605	MCFG_TC0360PRI_ADD("tc0360pri")
607	606
608	607	/* sound hardware */
r29505	r29506
617	616
618	617	MCFG_MK48T08_ADD( "mk48t08" )
619	618
620		MCFG_TC0140SYT_ADD("tc0140syt", slapshot_tc0140syt_intf)
	619	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	620	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	621	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
621	622	MACHINE_CONFIG_END
622	623
623	624	/***************************************************************************

branches/new_menus/src/mame/drivers/gotcha.c

r29505	r29506
281	281
282	282
283	283	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
284		decospr_device::set_gfx_region(*device, 1);
285		decospr_device::set_is_bootleg(*device, true);
286		decospr_device::set_offsets(*device, 5,-1); // aligned to 2nd instruction screen in attract
	284	MCFG_DECO_SPRITE_GFX_REGION(1)
	285	MCFG_DECO_SPRITE_ISBOOTLEG(true)
	286	MCFG_DECO_SPRITE_OFFSETS(5, -1) // aligned to 2nd instruction screen in attract
287	287	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
288	288	MCFG_DECO_SPRITE_PALETTE("palette")
289	289

branches/new_menus/src/mame/drivers/dassault.c

r29505	r29506
450	450
451	451	/**********************************************************************************/
452	452
453		int dassault_state::dassault_bank_callback( const int bank )
	453	DECO16IC_BANK_CB_MEMBER(dassault_state::bank_callback)
454	454	{
455	455	return ((bank >> 4) & 0xf) << 12;
456	456	}
r29505	r29506
499	499	MCFG_DECO16IC_PF2_COL_BANK(16)
500	500	MCFG_DECO16IC_PF1_COL_MASK(0x0f)
501	501	MCFG_DECO16IC_PF2_COL_MASK(0x0f)
502		MCFG_DECO16IC_BANK1_CB(dassault_state, dassault_bank_callback)
503		MCFG_DECO16IC_BANK2_CB(dassault_state, dassault_bank_callback)
	502	MCFG_DECO16IC_BANK1_CB(dassault_state, bank_callback)
	503	MCFG_DECO16IC_BANK2_CB(dassault_state, bank_callback)
504	504	MCFG_DECO16IC_PF12_8X8_BANK(0)
505	505	MCFG_DECO16IC_PF12_16X16_BANK(1)
506	506
r29505	r29506
516	516	MCFG_DECO16IC_PF2_COL_BANK(16)
517	517	MCFG_DECO16IC_PF1_COL_MASK(0x0f)
518	518	MCFG_DECO16IC_PF2_COL_MASK(0x0f)
519		MCFG_DECO16IC_BANK1_CB(dassault_state, dassault_bank_callback)
520		MCFG_DECO16IC_BANK2_CB(dassault_state, dassault_bank_callback)
	519	MCFG_DECO16IC_BANK1_CB(dassault_state, bank_callback)
	520	MCFG_DECO16IC_BANK2_CB(dassault_state, bank_callback)
521	521	MCFG_DECO16IC_PF12_8X8_BANK(0)
522	522	MCFG_DECO16IC_PF12_16X16_BANK(2)
523	523
r29505	r29506
525	525	MCFG_DECO16IC_PALETTE("palette")
526	526
527	527	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
528		decospr_device::set_gfx_region(*device, 3);
	528	MCFG_DECO_SPRITE_GFX_REGION(3)
529	529	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
530	530	MCFG_DECO_SPRITE_PALETTE("palette")
531	531
532	532	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
533		decospr_device::set_gfx_region(*device, 4);
	533	MCFG_DECO_SPRITE_GFX_REGION(4)
534	534	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
535	535	MCFG_DECO_SPRITE_PALETTE("palette")
536	536

branches/new_menus/src/mame/drivers/supbtime.c

r29505	r29506
350	350	MCFG_DECO16IC_PALETTE("palette")
351	351
352	352	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
353		decospr_device::set_gfx_region(*device, 2);
	353	MCFG_DECO_SPRITE_GFX_REGION(2)
354	354	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
355	355	MCFG_DECO_SPRITE_PALETTE("palette")
356	356
r29505	r29506
406	406	MCFG_DECO16IC_PALETTE("palette")
407	407
408	408	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
409		decospr_device::set_gfx_region(*device, 2);
	409	MCFG_DECO_SPRITE_GFX_REGION(2)
410	410	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
411	411	MCFG_DECO_SPRITE_PALETTE("palette")
412	412

branches/new_menus/src/mame/drivers/topspeed.c

r29505	r29506
369	369	AM_RANGE(0x400000, 0x40ffff) AM_RAM AM_SHARE("sharedram")
370	370	AM_RANGE(0x500000, 0x503fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
371	371	AM_RANGE(0x600002, 0x600003) AM_WRITE(cpua_ctrl_w)
372		AM_RANGE(0x7e0000, 0x7e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
373		AM_RANGE(0x7e0002, 0x7e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	372	AM_RANGE(0x7e0000, 0x7e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	373	AM_RANGE(0x7e0002, 0x7e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
374	374	AM_RANGE(0x800000, 0x8003ff) AM_RAM AM_SHARE("raster_ctrl")
375	375	AM_RANGE(0x800400, 0x80ffff) AM_RAM
376	376	AM_RANGE(0x880000, 0x880007) AM_WRITENOP // Lamps/outputs?
r29505	r29506
402	402	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("sndbank")
403	403	AM_RANGE(0x8000, 0x8fff) AM_RAM
404	404	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
405		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
406		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	405	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	406	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
407	407	AM_RANGE(0xb000, 0xcfff) AM_WRITE(msm5205_command_w)
408	408	AM_RANGE(0xd000, 0xdfff) AM_WRITE(volume_w)
409	409	ADDRESS_MAP_END
r29505	r29506
525	525	DEVICES
526	526	***********************************************************/
527	527
528		static const pc080sn_interface pc080sn_intf =
529		{
530		1,          // gfxnum
531		0, 8, 0, 0  // x_offset, y_offset, y_invert, dblwidth
532		};
533
534		static const tc0140syt_interface tc0140syt_intf =
535		{
536		"maincpu", "audiocpu"
537		};
538
539	528	static Z80CTC_INTERFACE( ctc_intf )
540	529	{
541	530	DEVCB_NULL, // Interrupt handler
r29505	r29506
595	584	MCFG_CPU_IO_MAP(z80_io)
596	585
597	586	MCFG_Z80CTC_ADD("ctc", XTAL_16MHz / 4, ctc_intf)
598		MCFG_PC080SN_ADD("pc080sn_1", pc080sn_intf)
	587
	588	MCFG_DEVICE_ADD("pc080sn_1", PC080SN, 0)
	589	MCFG_PC080SN_GFX_REGION(1)
	590	MCFG_PC080SN_OFFSETS(0, 8)
599	591	MCFG_PC080SN_GFXDECODE("gfxdecode")
600	592	MCFG_PC080SN_PALETTE("palette")
601		MCFG_PC080SN_ADD("pc080sn_2", pc080sn_intf)
	593
	594	MCFG_DEVICE_ADD("pc080sn_2", PC080SN, 0)
	595	MCFG_PC080SN_GFX_REGION(1)
	596	MCFG_PC080SN_OFFSETS(0, 8)
602	597	MCFG_PC080SN_GFXDECODE("gfxdecode")
603	598	MCFG_PC080SN_PALETTE("palette")
604		MCFG_TC0140SYT_ADD("tc0140syt", tc0140syt_intf)
	599
	600	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	601	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	602	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
	603
605	604	MCFG_DEVICE_ADD("tc0220ioc", TC0220IOC, 0)
606	605	MCFG_TC0220IOC_READ_0_CB(IOPORT("DSWA"))
607	606	MCFG_TC0220IOC_READ_1_CB(IOPORT("DSWB"))

branches/new_menus/src/mame/drivers/turbo.c

r29505	r29506
454	454	output_set_digit_value(m_i8279_scanlines * 2 + 1, ls48_map[(data>>4) & 0x0f]);
455	455	}
456	456
457
458		static I8279_INTERFACE( turbo_i8279_intf )
459		{
460		DEVCB_NULL,                                     // irq
461		DEVCB_DRIVER_MEMBER(turbo_state, scanlines_w),  // scan SL lines
462		DEVCB_DRIVER_MEMBER(turbo_state, digit_w),      // display A&B
463		DEVCB_NULL,                                     // BD
464		DEVCB_INPUT_PORT("DSW1"),                       // kbd RL lines
465		DEVCB_NULL,                                     // Shift key
466		DEVCB_NULL                                      // Ctrl-Strobe line
467		};
468
469
470
471	457	/*************************************
472	458	*
473	459	*  Misc Turbo inputs/outputs
r29505	r29506
936	922	MCFG_I8255_ADD( "i8255_2", turbo_8255_intf_2 )
937	923	MCFG_I8255_ADD( "i8255_3", turbo_8255_intf_3 )
938	924
939		MCFG_I8279_ADD("i8279", MASTER_CLOCK/4, turbo_i8279_intf)    // unknown clock
940
	925	MCFG_DEVICE_ADD("i8279", I8279, MASTER_CLOCK/4)    // unknown clock
	926	MCFG_I8279_OUT_SL_CB(WRITE8(turbo_state, scanlines_w))     // scan SL lines
	927	MCFG_I8279_OUT_DISP_CB(WRITE8(turbo_state, digit_w))      // display A&B
	928	MCFG_I8279_IN_RL_CB(IOPORT("DSW1"))                       // kbd RL lines
	929
941	930	/* video hardware */
942	931	MCFG_GFXDECODE_ADD("gfxdecode", "palette", turbo)
943	932	MCFG_PALETTE_ADD("palette", 256)
r29505	r29506
966	955	MCFG_I8255_ADD( "i8255_0", subroc3d_8255_intf_0 )
967	956	MCFG_I8255_ADD( "i8255_1", subroc3d_8255_intf_1 )
968	957
969		MCFG_I8279_ADD("i8279", MASTER_CLOCK/4, turbo_i8279_intf)    // unknown clock
	958	MCFG_DEVICE_ADD("i8279", I8279, MASTER_CLOCK/4)    // unknown clock
	959	MCFG_I8279_OUT_SL_CB(WRITE8(turbo_state, scanlines_w))     // scan SL lines
	960	MCFG_I8279_OUT_DISP_CB(WRITE8(turbo_state, digit_w))      // display A&B
	961	MCFG_I8279_IN_RL_CB(IOPORT("DSW1"))                       // kbd RL lines
970	962
971	963	/* video hardware */
972	964	MCFG_GFXDECODE_ADD("gfxdecode", "palette", turbo)
r29505	r29506
1003	995	MCFG_I8255_ADD( "i8255_0", buckrog_8255_intf_0 )
1004	996	MCFG_I8255_ADD( "i8255_1", buckrog_8255_intf_1 )
1005	997
1006		MCFG_I8279_ADD("i8279", MASTER_CLOCK/4, turbo_i8279_intf)    // unknown clock
	998	MCFG_DEVICE_ADD("i8279", I8279, MASTER_CLOCK/4)    // unknown clock
	999	MCFG_I8279_OUT_SL_CB(WRITE8(turbo_state, scanlines_w))     // scan SL lines
	1000	MCFG_I8279_OUT_DISP_CB(WRITE8(turbo_state, digit_w))      // display A&B
	1001	MCFG_I8279_IN_RL_CB(IOPORT("DSW1"))                       // kbd RL lines
1007	1002
1008	1003	/* video hardware */
1009	1004	MCFG_GFXDECODE_ADD("gfxdecode", "palette", turbo)

branches/new_menus/src/mame/drivers/rohga.c

r29505	r29506
759	759
760	760	/**********************************************************************************/
761	761
762		int rohga_state::bank_callback( int bank )
	762	DECO16IC_BANK_CB_MEMBER(rohga_state::bank_callback)
763	763	{
764	764	return ((bank >> 4) & 0x3) << 12;
765	765	}
766	766
	767	DECOSPR_PRIORITY_CB_MEMBER(rohga_state::rohga_pri_callback)
	768	{
	769	switch (pri & 0x6000)
	770	{
	771	case 0x0000: return 0;
	772	case 0x4000: return 0xf0;
	773	case 0x6000: return 0xf0 | 0xcc;
	774	case 0x2000: return 0;//0xf0|0xcc; /* Perhaps 0xf0|0xcc|0xaa (Sprite under bottom layer) */
	775	}
	776
	777	return 0;
	778	}
	779
	780	DECOSPR_COLOUR_CB_MEMBER(rohga_state::rohga_col_callback)
	781	{
	782	return (col >> 9) & 0xf;
	783	}
	784
	785	DECOSPR_COLOUR_CB_MEMBER(rohga_state::schmeisr_col_callback)
	786	{
	787	UINT16 colour = ((col >> 9) & 0xf) << 2;
	788	if (col & 0x8000)
	789	colour++;
	790
	791	return colour;
	792	}
	793
767	794	static MACHINE_CONFIG_START( rohga, rohga_state )
768	795
769	796	/* basic machine hardware */
r29505	r29506
788	815	MCFG_GFXDECODE_ADD("gfxdecode", "palette", rohga)
789	816	MCFG_PALETTE_ADD("palette", 2048)
790	817
791		MCFG_VIDEO_START_OVERRIDE(rohga_state,rohga)
792
793	818	MCFG_DECOCOMN_ADD("deco_common")
794	819	MCFG_DECOCOMN_PALETTE("palette")
795	820
r29505	r29506
826	851	MCFG_DECO16IC_PALETTE("palette")
827	852
828	853	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
829		decospr_device::set_gfx_region(*device, 3);
	854	MCFG_DECO_SPRITE_PRIORITY_CB(rohga_state, rohga_pri_callback)
	855	MCFG_DECO_SPRITE_COLOUR_CB(rohga_state, rohga_col_callback)
	856	MCFG_DECO_SPRITE_GFX_REGION(3)
830	857	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
831	858	MCFG_DECO_SPRITE_PALETTE("palette")
832	859
r29505	r29506
910	937	MCFG_DECO16IC_PALETTE("palette")
911	938
912	939	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
913		decospr_device::set_gfx_region(*device, 3);
	940	MCFG_DECO_SPRITE_GFX_REGION(3)
914	941	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
915	942	MCFG_DECO_SPRITE_PALETTE("palette")
916	943
917	944	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
918		decospr_device::set_gfx_region(*device, 4);
	945	MCFG_DECO_SPRITE_GFX_REGION(4)
919	946	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
920	947	MCFG_DECO_SPRITE_PALETTE("palette")
921	948
922	949	MCFG_DECO104_ADD("ioprot104")
923	950	MCFG_DECO146_SET_INTERFACE_SCRAMBLE_REVERSE
924	951
925		MCFG_VIDEO_START_OVERRIDE(rohga_state,wizdfire)
	952	MCFG_VIDEO_START_OVERRIDE(rohga_state, wizdfire)
926	953
927	954	/* sound hardware */
928	955	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r29505	r29506
1002	1029	MCFG_DECO16IC_PALETTE("palette")
1003	1030
1004	1031	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
1005		decospr_device::set_gfx_region(*device, 3);
	1032	MCFG_DECO_SPRITE_GFX_REGION(3)
1006	1033	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1007	1034	MCFG_DECO_SPRITE_PALETTE("palette")
1008	1035
1009	1036	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
1010		decospr_device::set_gfx_region(*device, 4);
	1037	MCFG_DECO_SPRITE_GFX_REGION(4)
1011	1038	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1012	1039	MCFG_DECO_SPRITE_PALETTE("palette")
1013	1040
1014		MCFG_VIDEO_START_OVERRIDE(rohga_state,wizdfire)
	1041	MCFG_VIDEO_START_OVERRIDE(rohga_state, wizdfire)
1015	1042
1016	1043	MCFG_DECO146_ADD("ioprot")
1017	1044	MCFG_DECO146_SET_INTERFACE_SCRAMBLE_REVERSE
r29505	r29506
1060	1087	MCFG_GFXDECODE_ADD("gfxdecode", "palette", schmeisr)
1061	1088	MCFG_PALETTE_ADD("palette", 2048)
1062	1089
1063		MCFG_VIDEO_START_OVERRIDE(rohga_state,schmeisr)
1064
1065	1090	MCFG_DECOCOMN_ADD("deco_common")
1066	1091	MCFG_DECOCOMN_PALETTE("palette")
1067	1092
r29505	r29506
1098	1123	MCFG_DECO16IC_PALETTE("palette")
1099	1124
1100	1125	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
1101		decospr_device::set_gfx_region(*device, 3);
	1126	MCFG_DECO_SPRITE_PRIORITY_CB(rohga_state, rohga_pri_callback)
	1127	MCFG_DECO_SPRITE_COLOUR_CB(rohga_state, schmeisr_col_callback)   // wire mods on pcb...
	1128	MCFG_DECO_SPRITE_GFX_REGION(3)
1102	1129	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1103	1130	MCFG_DECO_SPRITE_PALETTE("palette")
1104	1131

branches/new_menus/src/mame/drivers/cham24.c

r29505	r29506
291	291	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
292	292	}
293	293
294		/* our ppu interface                                            */
295		static const ppu2c0x_interface ppu_interface =
296		{
297		"maincpu",
298		0,                  /* gfxlayout num */
299		0,                  /* color base */
300		PPU_MIRROR_NONE     /* mirroring */
301		};
302
303	294	void cham24_state::video_start()
304	295	{
305	296	}
r29505	r29506
362	353	MCFG_PALETTE_ADD("palette", 8*4*16)
363	354	MCFG_PALETTE_INIT_OWNER(cham24_state, cham24)
364	355
365		MCFG_PPU2C04_ADD("ppu", ppu_interface)
	356	MCFG_PPU2C04_ADD("ppu")
	357	MCFG_PPU2C0X_CPU("maincpu")
366	358	MCFG_PPU2C0X_SET_NMI(cham24_state, ppu_irq)
367	359
368	360	/* sound hardware */

branches/new_menus/src/mame/drivers/mpu3.c

r29505	r29506
84	84	MOD4- Some modifications on the PCB that didnt work, so field engineers reverted them to MOD3.
85	85	MOD5- board revision with bigger RAM and reset sensitivity circuit added on the PCB.
86	86
87		MOD6- adaption of the PCB to use small daughter card with 6116 RAM
	87	MOD6- adaptation of the PCB to use small daughter card with 6116 RAM
88	88
89	89	Collectors have gone further with zero power RAM and the like, but these are the ones out in the wild.
90	90
r29505	r29506
850	850	MCFG_CPU_ADD("maincpu", M6808, MPU3_MASTER_CLOCK)///4)
851	851	MCFG_CPU_PROGRAM_MAP(mpu3_basemap)
852	852
853		MCFG_MSC1937_ADD("vfd",0,LEFT_TO_RIGHT)
	853	MCFG_MSC1937_ADD("vfd",0)
854	854
855	855	MCFG_TIMER_DRIVER_ADD_PERIODIC("50hz", mpu3_state, gen_50hz, attotime::from_hz(100))
856	856	MCFG_TIMER_DRIVER_ADD_PERIODIC("555_ic10", mpu3_state, ic10_callback, PERIOD_OF_555_ASTABLE(10000,1000,0.0000001))

branches/new_menus/src/mame/drivers/boogwing.c

r29505	r29506
296	296	}
297	297
298	298
299		int boogwing_state::bank_callback( int bank )
	299	DECO16IC_BANK_CB_MEMBER(boogwing_state::bank_callback)
300	300	{
301	301	return ((bank >> 4) & 0x7) * 0x1000;
302	302	}
303	303
304		int boogwing_state::bank_callback2( int bank )
	304	DECO16IC_BANK_CB_MEMBER(boogwing_state::bank_callback2)
305	305	{
306	306	int offset = ((bank >> 4) & 0x7) * 0x1000;
307	307	if ((bank & 0xf) == 0xa)
r29505	r29506
371	371	MCFG_DECO16IC_PALETTE("palette")
372	372
373	373	MCFG_DEVICE_ADD("spritegen1", DECO_SPRITE, 0)
374		decospr_device::set_gfx_region(*device, 3);
	374	MCFG_DECO_SPRITE_GFX_REGION(3)
375	375	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
376	376	MCFG_DECO_SPRITE_PALETTE("palette")
377	377
378	378	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
379		decospr_device::set_gfx_region(*device, 4);
	379	MCFG_DECO_SPRITE_GFX_REGION(4)
380	380	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
381	381	MCFG_DECO_SPRITE_PALETTE("palette")
382	382

branches/new_menus/src/mame/drivers/mpu4hw.c

r29505	r29506
2633	2633	MACHINE_CONFIG_FRAGMENT( mpu4_common )
2634	2634	MCFG_TIMER_DRIVER_ADD_PERIODIC("50hz", mpu4_state, gen_50hz, attotime::from_hz(100))
2635	2635
2636		MCFG_MSC1937_ADD("vfd",0,LEFT_TO_RIGHT)
	2636	MCFG_MSC1937_ADD("vfd",0)
2637	2637	/* 6840 PTM */
2638	2638	MCFG_PTM6840_ADD("ptm_ic2", ptm_ic2_intf)
2639	2639

branches/new_menus/src/mame/drivers/rungun.c

r29505	r29506
330	330	};
331	331
332	332
333		static const k053936_interface rng_k053936_intf =
334		{
335		0, 34, 9
336		};
337
338	333	static const k053247_interface rng_k055673_intf =
339	334	{
340	335	"gfx2", 1,
r29505	r29506
398	393	MCFG_PALETTE_ENABLE_SHADOWS()
399	394	MCFG_PALETTE_ENABLE_HILIGHTS()
400	395
401		MCFG_K053936_ADD("k053936", rng_k053936_intf)
	396	MCFG_DEVICE_ADD("k053936", K053936, 0)
	397	MCFG_K053936_OFFSETS(34, 9)
	398
402	399	MCFG_K055673_ADD("k055673", rng_k055673_intf)
403	400	MCFG_K055673_GFXDECODE("gfxdecode")
404	401	MCFG_K055673_PALETTE("palette")

branches/new_menus/src/mame/drivers/mpu4sw.c

r29505	r29506
990	990	GAME_CUSTOM( 199?, m4eaw__bv, m4eaw,  "eun01r.p1",                0x0000, 0x010000, CRC(15b8eb9e) SHA1(e4babaf526e6dd45bb4b7f7441a08cfbec12c661), "Barcrest","Everyone's A Winner (Barcrest) (MPU4) (set 95)" )
991	991	GAME_CUSTOM( 199?, m4eaw__bw, m4eaw,  "eun01s.p1",                0x0000, 0x010000, CRC(d0b49fc6) SHA1(4062d9763010d42666660e383e52818d572b61b9), "Barcrest","Everyone's A Winner (Barcrest) (MPU4) (set 96)" )
992	992	GAME_CUSTOM( 199?, m4eaw__bx, m4eaw,  "eun01y.p1",                0x0000, 0x010000, CRC(88d3c370) SHA1(6c3839a9c89ae67f80ab932ec70ebaf1240de9bb), "Barcrest","Everyone's A Winner (Barcrest) (MPU4) (set 97)" )
993		GAME_CUSTOM( 199?, m4eaw__bz, m4eaw,  "everyones a winner v2-5p", 0x0000, 0x008000, CRC(eb8f2fc5) SHA1(0d3614bd5ff561d17bef0d1e620f2f812b8fed5b), "Barcrest","Everyone's A Winner (Barcrest) (MPU4) (set 99)" )
994	993
	994	ROM_START( m4eaw__bz ) \
	995	ROM_REGION( 0x010000, "maincpu", 0 )
	996	ROM_LOAD( "everyones a winner v2-5p", 0x8000, 0x008000, CRC(eb8f2fc5) SHA1(0d3614bd5ff561d17bef0d1e620f2f812b8fed5b))
	997	M4EAW_EXTRA_ROMS
	998	ROM_END
995	999
	1000	GAME(199?, m4eaw__bz, m4eaw ,mod4oki ,mpu4 , mpu4_state,m4_showstring ,ROT0,"Barcrest","Everyone's A Winner (Barcrest) (MPU4) (set 99)",GAME_FLAGS )
	1001
996	1002	#define M4WTA_EXTRA_ROMS \
997	1003	ROM_REGION( 0x48, "fakechr", 0 ) \
998	1004	ROM_LOAD( "wn5s.chr", 0x0000, 0x000048, CRC(b90e5068) SHA1(14c57dcd7242104eb48a9be36192170b97bc5110) ) \

branches/new_menus/src/mame/drivers/taito_f2.c

r29505	r29506
689	689	AM_RANGE(0x100000, 0x10ffff) AM_RAM
690	690	AM_RANGE(0x200000, 0x200007) AM_DEVREADWRITE("tc0110pcr", tc0110pcr_device, word_r, word_w)    /* palette */
691	691	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
692		AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
693		AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	692	AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	693	AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
694	694	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
695	695	AM_RANGE(0x810000, 0x81ffff) AM_WRITENOP   /* error in game init code ? */
696	696	AM_RANGE(0x820000, 0x82000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
r29505	r29506
703	703	AM_RANGE(0x100000, 0x10ffff) AM_RAM
704	704	AM_RANGE(0x200000, 0x201fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
705	705	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
706		AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
707		AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	706	AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	707	AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
708	708	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
709	709	AM_RANGE(0x820000, 0x82000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
710	710	AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
715	715
716	716	static ADDRESS_MAP_START( megab_map, AS_PROGRAM, 16, taitof2_state )
717	717	AM_RANGE(0x000000, 0x07ffff) AM_ROM
718		AM_RANGE(0x100000, 0x100001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
719		AM_RANGE(0x100002, 0x100003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	718	AM_RANGE(0x100000, 0x100001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	719	AM_RANGE(0x100002, 0x100003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
720	720	AM_RANGE(0x120000, 0x12000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
721	721	AM_RANGE(0x180000, 0x180fff) AM_READWRITE(cchip2_word_r, cchip2_word_w) AM_SHARE("cchip2_ram")
722	722	AM_RANGE(0x200000, 0x20ffff) AM_RAM
r29505	r29506
732	732	AM_RANGE(0x000000, 0x07ffff) AM_ROM
733	733	AM_RANGE(0x100000, 0x101fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
734	734	AM_RANGE(0x200000, 0x20000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
735		AM_RANGE(0x220000, 0x220001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
736		AM_RANGE(0x220002, 0x220003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	735	AM_RANGE(0x220000, 0x220001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	736	AM_RANGE(0x220002, 0x220003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
737	737	AM_RANGE(0x300000, 0x30ffff) AM_RAM
738	738	AM_RANGE(0x400000, 0x40ffff) AM_DEVREADWRITE("tc0100scn_1", tc0100scn_device, word_r, word_w)  /* tilemaps */
739	739	AM_RANGE(0x420000, 0x42000f) AM_DEVREADWRITE("tc0100scn_1", tc0100scn_device, ctrl_word_r, ctrl_word_w)
r29505	r29506
749	749	AM_RANGE(0x200000, 0x201fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
750	750	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
751	751	AM_RANGE(0x300018, 0x30001f) AM_READ(cameltry_paddle_r)
752		AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
753		AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	752	AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	753	AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
754	754	AM_RANGE(0x800000, 0x813fff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
755	755	AM_RANGE(0x820000, 0x82000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
756	756	AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
764	764	AM_RANGE(0x100000, 0x10ffff) AM_RAM
765	765	AM_RANGE(0x200000, 0x200007) AM_DEVREADWRITE("tc0110pcr", tc0110pcr_device, word_r, word_w)    /* palette */
766	766	AM_RANGE(0x500000, 0x50000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
767		AM_RANGE(0x600000, 0x600001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
768		AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	767	AM_RANGE(0x600000, 0x600001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	768	AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
769	769	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
770	770	AM_RANGE(0x820000, 0x82000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
771	771	AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
777	777	AM_RANGE(0x100000, 0x10ffff) AM_RAM
778	778	AM_RANGE(0x200000, 0x201fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
779	779	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
780		AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
781		AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	780	AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	781	AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
782	782	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
783	783	AM_RANGE(0x820000, 0x82000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
784	784	AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
797	797	AM_RANGE(0x580000, 0x580001) AM_READ_PORT("DSWA")
798	798	AM_RANGE(0x580002, 0x580003) AM_READ_PORT("IN1")
799	799	AM_RANGE(0x580004, 0x580005) AM_READ_PORT("IN2")
800		AM_RANGE(0x600000, 0x600001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
801		AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	800	AM_RANGE(0x600000, 0x600001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	801	AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
802	802	AM_RANGE(0x680000, 0x680001) AM_WRITENOP   /* ??? */
803	803	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
804	804	AM_RANGE(0x810000, 0x81ffff) AM_WRITENOP   /* error in init code ? */
r29505	r29506
811	811	AM_RANGE(0x100000, 0x10000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_r, halfword_w)
812	812	AM_RANGE(0x200000, 0x20ffff) AM_RAM
813	813	AM_RANGE(0x300000, 0x301fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
814		AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
815		AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	814	AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	815	AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
816	816	//  AM_RANGE(0x500000, 0x500001) AM_WRITENOP   /* ?? */
817	817	AM_RANGE(0x600000, 0x60ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps (not used) */
818	818	AM_RANGE(0x620000, 0x62000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
r29505	r29506
824	824	AM_RANGE(0x100000, 0x10ffff) AM_RAM
825	825	AM_RANGE(0x200000, 0x201fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
826	826	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_wordswap_r, halfword_wordswap_w)
827		AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
828		AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	827	AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	828	AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
829	829	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
830	830	AM_RANGE(0x820000, 0x82000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
831	831	AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
844	844	AM_RANGE(0x320002, 0x320003) AM_READ_PORT("IN1")
845	845	AM_RANGE(0x320004, 0x320005) AM_READ_PORT("IN2")
846	846	AM_RANGE(0x340000, 0x340001) AM_WRITE(watchdog_reset16_w)
847		AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
848		AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	847	AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	848	AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
849	849	AM_RANGE(0x500000, 0x50000f) AM_WRITE(taitof2_spritebank_w)
850	850	AM_RANGE(0x504000, 0x504001) AM_WRITENOP    /* unknown... various values */
851	851	AM_RANGE(0x508000, 0x50800f) AM_READ_PORT("IN3")
r29505	r29506
866	866	AM_RANGE(0x320000, 0x320001) AM_WRITE(mjnquest_inputselect_w)
867	867	AM_RANGE(0x330000, 0x330001) AM_WRITENOP   /* watchdog ? */
868	868	AM_RANGE(0x350000, 0x350001) AM_WRITENOP   /* watchdog ? */
869		AM_RANGE(0x360000, 0x360001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
870		AM_RANGE(0x360002, 0x360003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	869	AM_RANGE(0x360000, 0x360001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	870	AM_RANGE(0x360002, 0x360003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
871	871	AM_RANGE(0x380000, 0x380001) AM_DEVWRITE("tc0100scn", tc0100scn_device, gfxbank_w)   /* scr gfx bank select */
872	872	AM_RANGE(0x400000, 0x40ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
873	873	AM_RANGE(0x420000, 0x42000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
r29505	r29506
892	892	AM_RANGE(0x70000e, 0x70000f) AM_READ_PORT("IN3")
893	893	AM_RANGE(0x700010, 0x700011) AM_READ_PORT("IN4")
894	894	AM_RANGE(0x800000, 0x800001) AM_WRITE(watchdog_reset16_w)   /* ??? */
895		AM_RANGE(0xa00000, 0xa00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
896		AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	895	AM_RANGE(0xa00000, 0xa00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	896	AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
897	897	ADDRESS_MAP_END
898	898
899	899	static ADDRESS_MAP_START( koshien_map, AS_PROGRAM, 16, taitof2_state )
r29505	r29506
901	901	AM_RANGE(0x100000, 0x10ffff) AM_RAM
902	902	AM_RANGE(0x200000, 0x201fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
903	903	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_r, halfword_w)
904		AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
905		AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	904	AM_RANGE(0x320000, 0x320001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	905	AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
906	906	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
907	907	AM_RANGE(0x820000, 0x82000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
908	908	AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
913	913	static ADDRESS_MAP_START( yuyugogo_map, AS_PROGRAM, 16, taitof2_state )
914	914	AM_RANGE(0x000000, 0x03ffff) AM_ROM
915	915	AM_RANGE(0x200000, 0x20000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_r, halfword_w)
916		AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
917		AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	916	AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	917	AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
918	918	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
919	919	AM_RANGE(0x820000, 0x82000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
920	920	AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
931	931	AM_RANGE(0x300000, 0x30000f) AM_READ(ninjak_input_r)
932	932	AM_RANGE(0x30000e, 0x30000f) AM_WRITE(ninjak_coin_word_w)
933	933	AM_RANGE(0x380000, 0x380001) AM_WRITE(watchdog_reset16_w)   /* ??? */
934		AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
935		AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	934	AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	935	AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
936	936	AM_RANGE(0x600000, 0x60000f) AM_WRITE(taitof2_spritebank_w)
937	937	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
938	938	AM_RANGE(0x820000, 0x82000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
r29505	r29506
951	951	AM_RANGE(0x320002, 0x320003) AM_READ_PORT("IN1")
952	952	AM_RANGE(0x320004, 0x320005) AM_READ_PORT("IN2")
953	953	AM_RANGE(0x340000, 0x340001) AM_WRITE(watchdog_reset16_w)   /* NOT VERIFIED */
954		AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
955		AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	954	AM_RANGE(0x400000, 0x400001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	955	AM_RANGE(0x400002, 0x400003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
956	956	AM_RANGE(0x500000, 0x50000f) AM_WRITE(taitof2_spritebank_w)
957	957	AM_RANGE(0x504000, 0x504001) AM_WRITENOP    /* unknown... various values */
958	958	AM_RANGE(0x800000, 0x80ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
r29505	r29506
964	964	static ADDRESS_MAP_START( qzquest_map, AS_PROGRAM, 16, taitof2_state )
965	965	AM_RANGE(0x000000, 0x17ffff) AM_ROM
966	966	AM_RANGE(0x200000, 0x20000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_r, halfword_w)
967		AM_RANGE(0x300000, 0x300001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
968		AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	967	AM_RANGE(0x300000, 0x300001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	968	AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
969	969	AM_RANGE(0x400000, 0x401fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
970	970	AM_RANGE(0x500000, 0x50ffff) AM_RAM
971	971	AM_RANGE(0x600000, 0x60ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
975	975
976	976	static ADDRESS_MAP_START( pulirula_map, AS_PROGRAM, 16, taitof2_state )
977	977	AM_RANGE(0x000000, 0x0bffff) AM_ROM
978		AM_RANGE(0x200000, 0x200001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
979		AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	978	AM_RANGE(0x200000, 0x200001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	979	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
980	980	AM_RANGE(0x300000, 0x30ffff) AM_RAM
981	981	AM_RANGE(0x400000, 0x401fff) AM_DEVREADWRITE("tc0430grw", tc0280grd_device, tc0430grw_word_r, tc0430grw_word_w)    /* ROZ tilemap */
982	982	AM_RANGE(0x402000, 0x40200f) AM_DEVWRITE("tc0430grw", tc0280grd_device, tc0430grw_ctrl_word_w)
r29505	r29506
1000	1000	AM_RANGE(0x600000, 0x60001f) AM_DEVWRITE8("tc0360pri", tc0360pri_device, write, 0x00ff)
1001	1001	AM_RANGE(0x700000, 0x703fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
1002	1002	AM_RANGE(0x800000, 0x80000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_wordswap_r, halfword_wordswap_w)
1003		AM_RANGE(0x900000, 0x900001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
1004		AM_RANGE(0x900002, 0x900003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	1003	AM_RANGE(0x900000, 0x900001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	1004	AM_RANGE(0x900002, 0x900003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
1005	1005	//  AM_RANGE(0xa00000, 0xa00001) AM_WRITENOP   /* ??? */
1006	1006	ADDRESS_MAP_END
1007	1007
1008	1008	static ADDRESS_MAP_START( qzchikyu_map, AS_PROGRAM, 16, taitof2_state )
1009	1009	AM_RANGE(0x000000, 0x17ffff) AM_ROM
1010	1010	AM_RANGE(0x200000, 0x20000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_r, halfword_w)
1011		AM_RANGE(0x300000, 0x300001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
1012		AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	1011	AM_RANGE(0x300000, 0x300001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	1012	AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
1013	1013	AM_RANGE(0x400000, 0x401fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
1014	1014	AM_RANGE(0x500000, 0x50ffff) AM_RAM
1015	1015	AM_RANGE(0x600000, 0x60ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
1025	1025	AM_RANGE(0x520000, 0x52000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
1026	1026	AM_RANGE(0x600000, 0x601fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
1027	1027	//  AM_RANGE(0x700000, 0x70000b) AM_READ(yesnoj_unknown_r)   /* what's this? */
1028		AM_RANGE(0x800000, 0x800001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
1029		AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	1028	AM_RANGE(0x800000, 0x800001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	1029	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
1030	1030	AM_RANGE(0x900002, 0x900003) AM_WRITENOP   /* lots of similar writes */
1031	1031	AM_RANGE(0xa00000, 0xa00001) AM_READ_PORT("IN0")
1032	1032	AM_RANGE(0xa00002, 0xa00003) AM_READ_PORT("IN1")
r29505	r29506
1053	1053	AM_RANGE(0x70000a, 0x70000b) AM_READ_PORT("IN0")
1054	1054	AM_RANGE(0x70000c, 0x70000d) AM_READ_PORT("IN1")
1055	1055	AM_RANGE(0x800000, 0x800001) AM_WRITE(watchdog_reset16_w)   /* ??? */
1056		AM_RANGE(0xa00000, 0xa00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
1057		AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	1056	AM_RANGE(0xa00000, 0xa00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	1057	AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
1058	1058	ADDRESS_MAP_END
1059	1059
1060	1060	static ADDRESS_MAP_START( dinorex_map, AS_PROGRAM, 16, taitof2_state )
r29505	r29506
1067	1067	AM_RANGE(0x800000, 0x80ffff) AM_RAM AM_SHARE("spriteram")
1068	1068	AM_RANGE(0x900000, 0x90ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
1069	1069	AM_RANGE(0x920000, 0x92000f) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, ctrl_word_r, ctrl_word_w)
1070		AM_RANGE(0xa00000, 0xa00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
1071		AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	1070	AM_RANGE(0xa00000, 0xa00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	1071	AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
1072	1072	AM_RANGE(0xb00000, 0xb00001) AM_WRITENOP   /* watchdog? */
1073	1073	ADDRESS_MAP_END
1074	1074
1075	1075	static ADDRESS_MAP_START( qjinsei_map, AS_PROGRAM, 16, taitof2_state )
1076	1076	AM_RANGE(0x000000, 0x1fffff) AM_ROM
1077		AM_RANGE(0x200000, 0x200001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
1078		AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	1077	AM_RANGE(0x200000, 0x200001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	1078	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
1079	1079	AM_RANGE(0x300000, 0x30ffff) AM_RAM
1080	1080	AM_RANGE(0x500000, 0x500001) AM_WRITENOP   /* watchdog ? */
1081	1081	AM_RANGE(0x600000, 0x603fff) AM_WRITE(taitof2_sprite_extension_w) AM_SHARE("sprite_ext")
r29505	r29506
1092	1092	AM_RANGE(0x100000, 0x10ffff) AM_RAM
1093	1093	//  AM_RANGE(0x200000, 0x200001) AM_WRITENOP   /* unknown */
1094	1094	AM_RANGE(0x300000, 0x3fffff) AM_ROM AM_REGION("extra", 0)   /* extra data rom */
1095		AM_RANGE(0x500000, 0x500001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
1096		AM_RANGE(0x500002, 0x500003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	1095	AM_RANGE(0x500000, 0x500001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	1096	AM_RANGE(0x500002, 0x500003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
1097	1097	AM_RANGE(0x600000, 0x603fff) AM_WRITE(taitof2_sprite_extension_w) AM_SHARE("sprite_ext")
1098	1098	AM_RANGE(0x700000, 0x701fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
1099	1099	AM_RANGE(0x800000, 0x80ffff) AM_RAM AM_SHARE("spriteram")
r29505	r29506
1113	1113	AM_RANGE(0x600000, 0x67ffff) AM_ROM AM_REGION("extra", 0)   /* extra data rom */
1114	1114	AM_RANGE(0x700000, 0x70000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_r, halfword_w)
1115	1115	AM_RANGE(0x900000, 0x90001f) AM_DEVWRITE8("tc0360pri", tc0360pri_device, write, 0x00ff)  /* ?? */
1116		AM_RANGE(0xa00000, 0xa00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
1117		AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	1116	AM_RANGE(0xa00000, 0xa00001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	1117	AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
1118	1118	AM_RANGE(0xb00000, 0xb017ff) AM_WRITE(taitof2_sprite_extension_w) AM_SHARE("sprite_ext")
1119	1119	ADDRESS_MAP_END
1120	1120
1121	1121	static ADDRESS_MAP_START( driftout_map, AS_PROGRAM, 16, taitof2_state )
1122	1122	AM_RANGE(0x000000, 0x0fffff) AM_ROM
1123		AM_RANGE(0x200000, 0x200001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
1124		AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	1123	AM_RANGE(0x200000, 0x200001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	1124	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
1125	1125	AM_RANGE(0x300000, 0x30ffff) AM_RAM
1126	1126	AM_RANGE(0x400000, 0x401fff) AM_DEVREADWRITE("tc0430grw", tc0280grd_device, tc0430grw_word_r, tc0430grw_word_w)    /* ROZ tilemap */
1127	1127	AM_RANGE(0x402000, 0x40200f) AM_DEVWRITE("tc0430grw", tc0280grd_device, tc0430grw_ctrl_word_w)
r29505	r29506
1160	1160	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank2")
1161	1161	AM_RANGE(0xc000, 0xdfff) AM_RAM
1162	1162	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
1163		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
1164		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	1163	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	1164	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
1165	1165	AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
1166	1166	AM_RANGE(0xea00, 0xea00) AM_READNOP
1167	1167	AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
r29505	r29506
1176	1176	AM_RANGE(0x0000, 0x7fff) AM_ROM     // I can't see a bank control, but there ARE some bytes past 0x8000
1177	1177	AM_RANGE(0x8000, 0x8fff) AM_RAM
1178	1178	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2203_device, read, write)
1179		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
1180		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	1179	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	1180	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
1181	1181	//  AM_RANGE(0xb000, 0xb000) AM_WRITE(unknown_w)    // probably controlling sample player?
1182	1182	AM_RANGE(0xb000, 0xb001) AM_MIRROR(0x0001) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1183	1183	ADDRESS_MAP_END
r29505	r29506
2833	2833	MACHINE DRIVERS
2834	2834	***********************************************************/
2835	2835
2836		static const tc0100scn_interface taitof2_tc0100scn_intf =
2837		{
2838		1, 2,       /* gfxnum, txnum */
2839		0, 0,       /* x_offset, y_offset */
2840		0, 0,       /* flip_xoff, flip_yoff */
2841		0, 0,       /* flip_text_xoff, flip_text_yoff */
2842		0, 0
2843		};
2844
2845		static const tc0100scn_interface liquidk_tc0100scn_intf =
2846		{
2847		1, 2,       /* gfxnum, txnum */
2848		3, 0,       /* x_offset, y_offset */
2849		0, 0,       /* flip_xoff, flip_yoff */
2850		0, 0,       /* flip_text_xoff, flip_text_yoff */
2851		0, 0
2852		};
2853
2854		static const tc0100scn_interface dondokod_tc0100scn_intf =
2855		{
2856		1, 3,       /* gfxnum, txnum */
2857		3, 0,       /* x_offset, y_offset */
2858		0, 0,       /* flip_xoff, flip_yoff */
2859		0, 0,       /* flip_text_xoff, flip_text_yoff */
2860		0, 0
2861		};
2862
2863		static const tc0100scn_interface finalb_tc0100scn_intf =
2864		{
2865		1, 2,       /* gfxnum, txnum */
2866		1, 0,       /* x_offset, y_offset */
2867		0, 0,       /* flip_xoff, flip_yoff */
2868		0, 0,       /* flip_text_xoff, flip_text_yoff */
2869		0, 0
2870		};
2871
2872		#if 0
2873		static const tc0100scn_interface ninjak_tc0100scn_intf =
2874		{
2875		1, 2,       /* gfxnum, txnum */
2876		0, 0,       /* x_offset, y_offset */
2877		0, 0,       /* flip_xoff, flip_yoff */
2878		1, 2,       /* flip_text_xoff, flip_text_yoff */
2879		0, 0
2880		};
2881		#endif
2882
2883		static const tc0100scn_interface qzchikyu_tc0100scn_intf =
2884		{
2885		1, 2,       /* gfxnum, txnum */
2886		0, 0,       /* x_offset, y_offset */
2887		-4, 0,      /* flip_xoff, flip_yoff */
2888		-11, 0,     /* flip_text_xoff, flip_text_yoff */
2889		0, 0
2890		};
2891
2892		static const tc0100scn_interface solfigtr_tc0100scn_intf =
2893		{
2894		1, 2,       /* gfxnum, txnum */
2895		3, 0,       /* x_offset, y_offset */
2896		6, 0,       /* flip_xoff, flip_yoff */
2897		6, 0,       /* flip_text_xoff, flip_text_yoff */
2898		0, 0
2899		};
2900
2901		static const tc0100scn_interface koshien_tc0100scn_intf =
2902		{
2903		1, 2,       /* gfxnum, txnum */
2904		1, 0,       /* x_offset, y_offset */
2905		2, 0,       /* flip_xoff, flip_yoff */
2906		0, 0,       /* flip_text_xoff, flip_text_yoff */
2907		0, 0
2908		};
2909
2910		static const tc0100scn_interface thundfox_tc0100scn_intf_1 =
2911		{
2912		1, 3,       /* gfxnum, txnum */
2913		3, 0,       /* x_offset, y_offset */
2914		5, 0,       /* flip_xoff, flip_yoff */
2915		4, 1,       /* flip_text_xoff, flip_text_yoff */
2916		0, 0
2917		};
2918
2919		static const tc0100scn_interface thundfox_tc0100scn_intf_2 =
2920		{
2921		2, 4,       /* gfxnum, txnum */
2922		3, 0,       /* x_offset, y_offset */
2923		5, 0,       /* flip_xoff, flip_yoff */
2924		4, 1,       /* flip_text_xoff, flip_text_yoff */
2925		TC0100SCN_SINGLE_VDU, 1
2926		};
2927
2928		static const tc0480scp_interface footchmp_tc0480scp_intf =
2929		{
2930		1, 2,       /* gfxnum, txnum */
2931		3,      /* pixels */
2932		0x1d, 0x08,     /* x_offset, y_offset */
2933		-1, 0,      /* text_xoff, text_yoff */
2934		-1, 0,      /* flip_xoff, flip_yoff */
2935		0       /* col_base */
2936		};
2937
2938		static const tc0480scp_interface hthero_tc0480scp_intf =
2939		{
2940		1, 2,       /* gfxnum, txnum */
2941		3,      /* pixels */
2942		0x33, -0x04,        /* x_offset, y_offset */
2943		-1, 0,      /* text_xoff, text_yoff */
2944		-1, 0,      /* flip_xoff, flip_yoff */
2945		0       /* col_base */
2946		};
2947
2948		static const tc0480scp_interface deadconx_tc0480scp_intf =
2949		{
2950		1, 2,       /* gfxnum, txnum */
2951		3,      /* pixels */
2952		0x1e, 0x08,     /* x_offset, y_offset */
2953		-1, 0,      /* text_xoff, text_yoff */
2954		-1, 0,      /* flip_xoff, flip_yoff */
2955		0       /* col_base */
2956		};
2957
2958		static const tc0480scp_interface deadconxj_tc0480scp_intf =
2959		{
2960		1, 2,       /* gfxnum, txnum */
2961		3,      /* pixels */
2962		0x34, -0x05,        /* x_offset, y_offset */
2963		-1, 0,      /* text_xoff, text_yoff */
2964		-1, 0,      /* flip_xoff, flip_yoff */
2965		0       /* col_base */
2966		};
2967
2968		static const tc0480scp_interface metalb_tc0480scp_intf =
2969		{
2970		1, 2,       /* gfxnum, txnum */
2971		3,      /* pixels */
2972		0x32, -0x04,        /* x_offset, y_offset */
2973		1, 0,       /* text_xoff, text_yoff */
2974		-1, 0,      /* flip_xoff, flip_yoff */
2975		256     /* col_base */
2976		};
2977
2978
2979		static const tc0280grd_interface taitof2_tc0280grd_intf = { 2 };
2980		static const tc0280grd_interface taitof2_tc0430grw_intf = { 2 };
2981
2982		static const tc0140syt_interface taitof2_tc0140syt_intf =
2983		{
2984		"maincpu", "audiocpu"
2985		};
2986
2987	2836	MACHINE_START_MEMBER(taitof2_state,common)
2988	2837	{
2989	2838	}
r29505	r29506
3031	2880	MCFG_SOUND_ROUTE(1, "lspeaker",  1.0)
3032	2881	MCFG_SOUND_ROUTE(2, "rspeaker", 1.0)
3033	2882
3034		MCFG_TC0140SYT_ADD("tc0140syt", taitof2_tc0140syt_intf)
	2883	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2884	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2885	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3035	2886	MACHINE_CONFIG_END
3036	2887
3037	2888	static MACHINE_CONFIG_DERIVED( taito_f2_tc0220ioc, taito_f2 )
r29505	r29506
3073	2924	MCFG_SCREEN_MODIFY("screen")
3074	2925	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed)
3075	2926
3076		MCFG_TC0100SCN_ADD("tc0100scn", finalb_tc0100scn_intf)
	2927	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	2928	MCFG_TC0100SCN_GFX_REGION(1)
	2929	MCFG_TC0100SCN_TX_REGION(2)
	2930	MCFG_TC0100SCN_OFFSETS(1, 0)
3077	2931	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3078	2932	MCFG_TC0100SCN_PALETTE("palette")
3079	2933
r29505	r29506
3095	2949	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed)
3096	2950	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri_roz)
3097	2951
3098		MCFG_TC0100SCN_ADD("tc0100scn", dondokod_tc0100scn_intf)
	2952	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	2953	MCFG_TC0100SCN_GFX_REGION(1)
	2954	MCFG_TC0100SCN_TX_REGION(3)
	2955	MCFG_TC0100SCN_OFFSETS(3, 0)
3099	2956	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3100	2957	MCFG_TC0100SCN_PALETTE("palette")
3101	2958
3102		MCFG_TC0280GRD_ADD("tc0280grd", taitof2_tc0280grd_intf)
	2959	MCFG_DEVICE_ADD("tc0280grd", TC0280GRD, 0)
	2960	MCFG_TC0280GRD_GFX_REGION(2)
3103	2961	MCFG_TC0280GRD_GFXDECODE("gfxdecode");
	2962
3104	2963	MCFG_TC0360PRI_ADD("tc0360pri")
3105	2964	MACHINE_CONFIG_END
3106	2965
r29505	r29506
3116	2975	MCFG_SCREEN_MODIFY("screen")
3117	2976	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3118	2977
3119		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	2978	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	2979	MCFG_TC0100SCN_GFX_REGION(1)
	2980	MCFG_TC0100SCN_TX_REGION(2)
	2981	MCFG_TC0100SCN_OFFSETS(3, 0)
3120	2982	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3121	2983	MCFG_TC0100SCN_PALETTE("palette")
3122	2984
r29505	r29506
3137	2999	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_thundfox)
3138	3000	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed_thundfox)
3139	3001
3140		MCFG_TC0100SCN_ADD("tc0100scn_1", thundfox_tc0100scn_intf_1)
	3002	MCFG_DEVICE_ADD("tc0100scn_1", TC0100SCN, 0)
	3003	MCFG_TC0100SCN_GFX_REGION(1)
	3004	MCFG_TC0100SCN_TX_REGION(3)
	3005	MCFG_TC0100SCN_OFFSETS(3, 0)
	3006	MCFG_TC0100SCN_OFFSETS_FLIP(5, 0)
	3007	MCFG_TC0100SCN_OFFSETS_FLIPTX(4, 1)
3141	3008	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3142	3009	MCFG_TC0100SCN_PALETTE("palette")
3143	3010
3144		MCFG_TC0100SCN_ADD("tc0100scn_2", thundfox_tc0100scn_intf_2)
	3011	MCFG_DEVICE_ADD("tc0100scn_2", TC0100SCN, 0)
	3012	MCFG_TC0100SCN_GFX_REGION(2)
	3013	MCFG_TC0100SCN_TX_REGION(4)
	3014	MCFG_TC0100SCN_OFFSETS(3, 0)
	3015	MCFG_TC0100SCN_OFFSETS_FLIP(5, 0)
	3016	MCFG_TC0100SCN_OFFSETS_FLIPTX(4, 1)
	3017	MCFG_TC0100SCN_MULTISCR_XOFFS(TC0100SCN_SINGLE_VDU)
	3018	MCFG_TC0100SCN_MULTISCR_HACK(1)
3145	3019	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3146	3020	MCFG_TC0100SCN_PALETTE("palette")
3147	3021
r29505	r29506
3161	3035	MCFG_SCREEN_MODIFY("screen")
3162	3036	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri_roz)
3163	3037
3164		MCFG_TC0100SCN_ADD("tc0100scn", dondokod_tc0100scn_intf)
	3038	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3039	MCFG_TC0100SCN_GFX_REGION(1)
	3040	MCFG_TC0100SCN_TX_REGION(3)
	3041	MCFG_TC0100SCN_OFFSETS(3, 0)
3165	3042	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3166	3043	MCFG_TC0100SCN_PALETTE("palette")
3167	3044
3168		MCFG_TC0280GRD_ADD("tc0280grd", taitof2_tc0280grd_intf)
	3045	MCFG_DEVICE_ADD("tc0280grd", TC0280GRD, 0)
	3046	MCFG_TC0280GRD_GFX_REGION(2)
3169	3047	MCFG_TC0280GRD_GFXDECODE("gfxdecode");
	3048
3170	3049	MCFG_TC0360PRI_ADD("tc0360pri")
3171	3050	MACHINE_CONFIG_END
3172	3051
r29505	r29506
3182	3061	MCFG_SCREEN_MODIFY("screen")
3183	3062	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed)
3184	3063
3185		MCFG_TC0100SCN_ADD("tc0100scn", taitof2_tc0100scn_intf)
	3064	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3065	MCFG_TC0100SCN_GFX_REGION(1)
	3066	MCFG_TC0100SCN_TX_REGION(2)
3186	3067	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3187	3068	MCFG_TC0100SCN_PALETTE("palette")
3188	3069
r29505	r29506
3203	3084	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3204	3085	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed)
3205	3086
3206		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3087	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3088	MCFG_TC0100SCN_GFX_REGION(1)
	3089	MCFG_TC0100SCN_TX_REGION(2)
	3090	MCFG_TC0100SCN_OFFSETS(3, 0)
3207	3091	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3208	3092	MCFG_TC0100SCN_PALETTE("palette")
3209	3093
r29505	r29506
3222	3106	MCFG_SCREEN_MODIFY("screen")
3223	3107	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed)
3224	3108
3225		MCFG_TC0100SCN_ADD("tc0100scn", taitof2_tc0100scn_intf)
	3109	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3110	MCFG_TC0100SCN_GFX_REGION(1)
	3111	MCFG_TC0100SCN_TX_REGION(2)
3226	3112	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3227	3113	MCFG_TC0100SCN_PALETTE("palette")
3228	3114
r29505	r29506
3246	3132	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_ssi)
3247	3133	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed_thundfox)
3248	3134
3249		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3135	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3136	MCFG_TC0100SCN_GFX_REGION(1)
	3137	MCFG_TC0100SCN_TX_REGION(2)
	3138	MCFG_TC0100SCN_OFFSETS(3, 0)
3250	3139	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3251	3140	MCFG_TC0100SCN_PALETTE("palette")
3252	3141	MACHINE_CONFIG_END
r29505	r29506
3267	3156	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3268	3157	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed)
3269	3158
3270		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3159	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3160	MCFG_TC0100SCN_GFX_REGION(1)
	3161	MCFG_TC0100SCN_TX_REGION(2)
	3162	MCFG_TC0100SCN_OFFSETS(3, 0)
3271	3163	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3272	3164	MCFG_TC0100SCN_PALETTE("palette")
3273	3165
r29505	r29506
3286	3178	MCFG_SCREEN_MODIFY("screen")
3287	3179	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3288	3180
3289		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3181	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3182	MCFG_TC0100SCN_GFX_REGION(1)
	3183	MCFG_TC0100SCN_TX_REGION(2)
	3184	MCFG_TC0100SCN_OFFSETS(3, 0)
3290	3185	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3291	3186	MCFG_TC0100SCN_PALETTE("palette")
3292	3187
r29505	r29506
3303	3198	/* video hardware */
3304	3199	MCFG_VIDEO_START_OVERRIDE(taitof2_state,taitof2_mjnquest)
3305	3200
3306		MCFG_TC0100SCN_ADD("tc0100scn", taitof2_tc0100scn_intf)
	3201	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3202	MCFG_TC0100SCN_GFX_REGION(1)
	3203	MCFG_TC0100SCN_TX_REGION(2)
3307	3204	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3308	3205	MCFG_TC0100SCN_PALETTE("palette")
3309	3206
r29505	r29506
3325	3222	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_deadconx)
3326	3223	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_full_buffer_delayed)
3327	3224
3328		MCFG_TC0480SCP_ADD("tc0480scp", footchmp_tc0480scp_intf)
	3225	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	3226	MCFG_TC0480SCP_GFX_REGION(1)
	3227	MCFG_TC0480SCP_TX_REGION(2)
	3228	MCFG_TC0480SCP_OFFSETS(0x1d + 3, 0x08)
	3229	MCFG_TC0480SCP_OFFSETS_TX(-1, 0)
	3230	MCFG_TC0480SCP_OFFSETS_FLIP(-1, 0)
3329	3231	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
3330	3232	MCFG_TC0480SCP_PALETTE("palette")
3331	3233
r29505	r29506
3353	3255	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_full_buffer_delayed)
3354	3256
3355	3257	MCFG_TC0360PRI_ADD("tc0360pri")
3356		MCFG_TC0480SCP_ADD("tc0480scp", hthero_tc0480scp_intf)
	3258
	3259	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	3260	MCFG_TC0480SCP_GFX_REGION(1)
	3261	MCFG_TC0480SCP_TX_REGION(2)
	3262	MCFG_TC0480SCP_OFFSETS(0x33 + 3, -0x04)
	3263	MCFG_TC0480SCP_OFFSETS_TX(-1, 0)
	3264	MCFG_TC0480SCP_OFFSETS_FLIP(-1, 0)
3357	3265	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
3358	3266	MCFG_TC0480SCP_PALETTE("palette")
3359	3267	MACHINE_CONFIG_END
r29505	r29506
3372	3280	MCFG_SCREEN_MODIFY("screen")
3373	3281	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3374	3282
3375		MCFG_TC0100SCN_ADD("tc0100scn", koshien_tc0100scn_intf)
	3283	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3284	MCFG_TC0100SCN_GFX_REGION(1)
	3285	MCFG_TC0100SCN_TX_REGION(2)
	3286	MCFG_TC0100SCN_OFFSETS(1, 0)
	3287	MCFG_TC0100SCN_OFFSETS_FLIP(2, 0)
3376	3288	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3377	3289	MCFG_TC0100SCN_PALETTE("palette")
3378	3290
r29505	r29506
3395	3307	MCFG_SCREEN_MODIFY("screen")
3396	3308	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_yesnoj)
3397	3309
3398		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3310	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3311	MCFG_TC0100SCN_GFX_REGION(1)
	3312	MCFG_TC0100SCN_TX_REGION(2)
	3313	MCFG_TC0100SCN_OFFSETS(3, 0)
3399	3314	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3400	3315	MCFG_TC0100SCN_PALETTE("palette")
3401	3316	MACHINE_CONFIG_END
r29505	r29506
3412	3327	MCFG_SCREEN_MODIFY("screen")
3413	3328	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3414	3329
3415		MCFG_TC0100SCN_ADD("tc0100scn", finalb_tc0100scn_intf)
	3330	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3331	MCFG_TC0100SCN_GFX_REGION(1)
	3332	MCFG_TC0100SCN_TX_REGION(2)
	3333	MCFG_TC0100SCN_OFFSETS(1, 0)
3416	3334	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3417	3335	MCFG_TC0100SCN_PALETTE("palette")
3418	3336
r29505	r29506
3431	3349	MCFG_SCREEN_MODIFY("screen")
3432	3350	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3433	3351
3434		MCFG_TC0100SCN_ADD("tc0100scn", solfigtr_tc0100scn_intf)
	3352	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3353	MCFG_TC0100SCN_GFX_REGION(1)
	3354	MCFG_TC0100SCN_TX_REGION(2)
	3355	MCFG_TC0100SCN_OFFSETS(3, 0)
	3356	MCFG_TC0100SCN_OFFSETS_FLIP(6, 0)
	3357	MCFG_TC0100SCN_OFFSETS_FLIPTX(6, 0)
3435	3358	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3436	3359	MCFG_TC0100SCN_PALETTE("palette")
3437	3360
r29505	r29506
3449	3372	MCFG_SCREEN_MODIFY("screen")
3450	3373	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed)
3451	3374
3452		MCFG_TC0100SCN_ADD("tc0100scn", taitof2_tc0100scn_intf)
	3375	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3376	MCFG_TC0100SCN_GFX_REGION(1)
	3377	MCFG_TC0100SCN_TX_REGION(2)
3453	3378	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3454	3379	MCFG_TC0100SCN_PALETTE("palette")
3455	3380	MACHINE_CONFIG_END
r29505	r29506
3467	3392	MCFG_SCREEN_MODIFY("screen")
3468	3393	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri_roz)
3469	3394
3470		MCFG_TC0100SCN_ADD("tc0100scn", dondokod_tc0100scn_intf)
	3395	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3396	MCFG_TC0100SCN_GFX_REGION(1)
	3397	MCFG_TC0100SCN_TX_REGION(3)
	3398	MCFG_TC0100SCN_OFFSETS(3, 0)
3471	3399	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3472	3400	MCFG_TC0100SCN_PALETTE("palette")
3473	3401
3474		MCFG_TC0430GRW_ADD("tc0430grw", taitof2_tc0430grw_intf)
	3402	MCFG_DEVICE_ADD("tc0430grw", TC0430GRW, 0)
	3403	MCFG_TC0430GRW_GFX_REGION(2)
3475	3404	MCFG_TC0430GRW_GFXDECODE("gfxdecode")
	3405
3476	3406	MCFG_TC0360PRI_ADD("tc0360pri")
3477	3407	MACHINE_CONFIG_END
3478	3408
r29505	r29506
3492	3422	MCFG_SCREEN_MODIFY("screen")
3493	3423	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_metalb)
3494	3424
3495		MCFG_TC0480SCP_ADD("tc0480scp", metalb_tc0480scp_intf)
	3425	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	3426	MCFG_TC0480SCP_GFX_REGION(1)
	3427	MCFG_TC0480SCP_TX_REGION(2)
	3428	MCFG_TC0480SCP_OFFSETS(0x32 + 3, -0x04)
	3429	MCFG_TC0480SCP_OFFSETS_TX(1, 0)
	3430	MCFG_TC0480SCP_OFFSETS_FLIP(-1, 0)
	3431	MCFG_TC0480SCP_COL_BASE(256)
3496	3432	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
3497	3433	MCFG_TC0480SCP_PALETTE("palette")
3498	3434
r29505	r29506
3511	3447	MCFG_SCREEN_MODIFY("screen")
3512	3448	MCFG_SCREEN_VBLANK_DRIVER(taitof2_state, screen_eof_taitof2_partial_buffer_delayed_qzchikyu)
3513	3449
3514		MCFG_TC0100SCN_ADD("tc0100scn", qzchikyu_tc0100scn_intf)
	3450	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3451	MCFG_TC0100SCN_GFX_REGION(1)
	3452	MCFG_TC0100SCN_TX_REGION(2)
	3453	MCFG_TC0100SCN_OFFSETS(0, 0)
	3454	MCFG_TC0100SCN_OFFSETS_FLIP(-4, 0)
	3455	MCFG_TC0100SCN_OFFSETS_FLIPTX(-11, 0)
3515	3456	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3516	3457	MCFG_TC0100SCN_PALETTE("palette")
3517	3458	MACHINE_CONFIG_END
r29505	r29506
3529	3470	MCFG_SCREEN_MODIFY("screen")
3530	3471	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_yesnoj)
3531	3472
3532		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3473	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3474	MCFG_TC0100SCN_GFX_REGION(1)
	3475	MCFG_TC0100SCN_TX_REGION(2)
	3476	MCFG_TC0100SCN_OFFSETS(3, 0)
3533	3477	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3534	3478	MCFG_TC0100SCN_PALETTE("palette")
3535	3479	MACHINE_CONFIG_END
r29505	r29506
3547	3491	MCFG_SCREEN_MODIFY("screen")
3548	3492	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_deadconx)
3549	3493
3550		MCFG_TC0480SCP_ADD("tc0480scp", deadconx_tc0480scp_intf)
	3494	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	3495	MCFG_TC0480SCP_GFX_REGION(1)
	3496	MCFG_TC0480SCP_TX_REGION(2)
	3497	MCFG_TC0480SCP_OFFSETS(0x1e + 3, 0x08)
	3498	MCFG_TC0480SCP_OFFSETS_TX(-1, 0)
	3499	MCFG_TC0480SCP_OFFSETS_FLIP(-1, 0)
3551	3500	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
3552	3501	MCFG_TC0480SCP_PALETTE("palette")
3553	3502
r29505	r29506
3567	3516	MCFG_SCREEN_MODIFY("screen")
3568	3517	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_deadconx)
3569	3518
3570		MCFG_TC0480SCP_ADD("tc0480scp", deadconxj_tc0480scp_intf)
	3519	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	3520	MCFG_TC0480SCP_GFX_REGION(1)
	3521	MCFG_TC0480SCP_TX_REGION(2)
	3522	MCFG_TC0480SCP_OFFSETS(0x34 + 3, -0x05)
	3523	MCFG_TC0480SCP_OFFSETS_TX(-1, 0)
	3524	MCFG_TC0480SCP_OFFSETS_FLIP(-1, 0)
3571	3525	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
3572	3526	MCFG_TC0480SCP_PALETTE("palette")
3573	3527
r29505	r29506
3589	3543	MCFG_PALETTE_MODIFY("palette")
3590	3544	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3591	3545
3592		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3546	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3547	MCFG_TC0100SCN_GFX_REGION(1)
	3548	MCFG_TC0100SCN_TX_REGION(2)
	3549	MCFG_TC0100SCN_OFFSETS(3, 0)
3593	3550	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3594	3551	MCFG_TC0100SCN_PALETTE("palette")
3595	3552
r29505	r29506
3611	3568	MCFG_PALETTE_MODIFY("palette")
3612	3569	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3613	3570
3614		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3571	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3572	MCFG_TC0100SCN_GFX_REGION(1)
	3573	MCFG_TC0100SCN_TX_REGION(2)
	3574	MCFG_TC0100SCN_OFFSETS(3, 0)
3615	3575	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3616	3576	MCFG_TC0100SCN_PALETTE("palette")
3617	3577
r29505	r29506
3633	3593	MCFG_PALETTE_MODIFY("palette")
3634	3594	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3635	3595
3636		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3596	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3597	MCFG_TC0100SCN_GFX_REGION(1)
	3598	MCFG_TC0100SCN_TX_REGION(2)
	3599	MCFG_TC0100SCN_OFFSETS(3, 0)
3637	3600	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3638	3601	MCFG_TC0100SCN_PALETTE("palette")
3639	3602
r29505	r29506
3655	3618	MCFG_PALETTE_MODIFY("palette")
3656	3619	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3657	3620
3658		MCFG_TC0100SCN_ADD("tc0100scn", liquidk_tc0100scn_intf)
	3621	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3622	MCFG_TC0100SCN_GFX_REGION(1)
	3623	MCFG_TC0100SCN_TX_REGION(2)
	3624	MCFG_TC0100SCN_OFFSETS(3, 0)
3659	3625	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3660	3626	MCFG_TC0100SCN_PALETTE("palette")
3661	3627
r29505	r29506
3675	3641	MCFG_SCREEN_MODIFY("screen")
3676	3642	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri_roz)
3677	3643
3678		MCFG_TC0100SCN_ADD("tc0100scn", dondokod_tc0100scn_intf)
	3644	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3645	MCFG_TC0100SCN_GFX_REGION(1)
	3646	MCFG_TC0100SCN_TX_REGION(3)
	3647	MCFG_TC0100SCN_OFFSETS(3, 0)
3679	3648	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3680	3649	MCFG_TC0100SCN_PALETTE("palette")
3681	3650
3682		MCFG_TC0430GRW_ADD("tc0430grw", taitof2_tc0430grw_intf)
	3651	MCFG_DEVICE_ADD("tc0430grw", TC0430GRW, 0)
	3652	MCFG_TC0430GRW_GFX_REGION(2)
3683	3653	MCFG_TC0430GRW_GFXDECODE("gfxdecode")
	3654
3684	3655	MCFG_TC0360PRI_ADD("tc0360pri")
3685	3656	MACHINE_CONFIG_END
3686	3657
r29505	r29506
3720	3691
3721	3692	MCFG_VIDEO_START_OVERRIDE(taitof2_state,taitof2_dondokod)
3722	3693
3723		MCFG_TC0100SCN_ADD("tc0100scn", dondokod_tc0100scn_intf)
	3694	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3695	MCFG_TC0100SCN_GFX_REGION(1)
	3696	MCFG_TC0100SCN_TX_REGION(3)
	3697	MCFG_TC0100SCN_OFFSETS(3, 0)
3724	3698	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3725	3699	MCFG_TC0100SCN_PALETTE("palette")
3726	3700
3727		MCFG_TC0280GRD_ADD("tc0280grd", taitof2_tc0280grd_intf)
	3701	MCFG_DEVICE_ADD("tc0280grd", TC0280GRD, 0)
	3702	MCFG_TC0280GRD_GFX_REGION(2)
3728	3703	MCFG_TC0280GRD_GFXDECODE("gfxdecode");
	3704
3729	3705	MCFG_TC0360PRI_ADD("tc0360pri")
3730	3706
3731	3707	/* sound hardware */
r29505	r29506
3742	3718	MCFG_OKIM6295_ADD("oki", XTAL_4_224MHz/4, OKIM6295_PIN7_HIGH) /* verified on pcb */
3743	3719	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.10)
3744	3720
3745		MCFG_TC0140SYT_ADD("tc0140syt", taitof2_tc0140syt_intf)
	3721	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3722	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	3723	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3746	3724	MACHINE_CONFIG_END
3747	3725
3748	3726
r29505	r29506
3781	3759
3782	3760	MCFG_VIDEO_START_OVERRIDE(taitof2_state,taitof2_driftout)
3783	3761
3784		MCFG_TC0100SCN_ADD("tc0100scn", dondokod_tc0100scn_intf)
	3762	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3763	MCFG_TC0100SCN_GFX_REGION(1)
	3764	MCFG_TC0100SCN_TX_REGION(3)
	3765	MCFG_TC0100SCN_OFFSETS(3, 0)
3785	3766	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3786	3767	MCFG_TC0100SCN_PALETTE("palette")
3787	3768
3788		MCFG_TC0430GRW_ADD("tc0430grw", taitof2_tc0430grw_intf)
	3769	MCFG_DEVICE_ADD("tc0430grw", TC0430GRW, 0)
	3770	MCFG_TC0430GRW_GFX_REGION(2)
3789	3771	MCFG_TC0430GRW_GFXDECODE("gfxdecode")
	3772
3790	3773	MCFG_TC0360PRI_ADD("tc0360pri")
3791	3774
3792	3775	/* sound hardware */
r29505	r29506
3796	3779	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
3797	3780	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
3798	3781
3799		MCFG_TC0140SYT_ADD("tc0140syt", taitof2_tc0140syt_intf)
	3782	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3783	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	3784	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3800	3785	MACHINE_CONFIG_END
3801	3786
3802	3787

branches/new_menus/src/mame/drivers/djboy.c

r29505	r29506
501	501	m_maincpu->set_input_line_and_vector(0, HOLD_LINE, 0xff);
502	502	}
503	503
504		static const kaneko_pandora_interface djboy_pandora_config =
505		{
506		0,  /* gfx_region */
507		0, 0    /* x_offs, y_offs */
508		};
509
510
511	504	void djboy_state::machine_start()
512	505	{
513	506	UINT8 *MAIN = memregion("maincpu")->base();
r29505	r29506
584	577	MCFG_GFXDECODE_ADD("gfxdecode", "palette", djboy)
585	578	MCFG_PALETTE_ADD("palette", 0x200)
586	579
587		MCFG_KANEKO_PANDORA_ADD("pandora", djboy_pandora_config)
	580	MCFG_DEVICE_ADD("pandora", KANEKO_PANDORA, 0)
588	581	MCFG_KANEKO_PANDORA_GFXDECODE("gfxdecode")
589	582	MCFG_KANEKO_PANDORA_PALETTE("palette")
590	583

branches/new_menus/src/mame/drivers/groundfx.c

r29505	r29506
324	324	MACHINE DRIVERS
325	325	***********************************************************/
326	326
327		static const tc0100scn_interface groundfx_tc0100scn_intf =
328		{
329		2, 3,       /* gfxnum, txnum */
330		50, 8,      /* x_offset, y_offset */
331		0, 0,       /* flip_xoff, flip_yoff */
332		0, 0,       /* flip_text_xoff, flip_text_yoff */
333		0, 0
334		};
335
336		static const tc0480scp_interface groundfx_tc0480scp_intf =
337		{
338		1, 4,       /* gfxnum, txnum */
339		0,      /* pixels */
340		0x24, 0,        /* x_offset, y_offset */
341		-1, 0,      /* text_xoff, text_yoff */
342		0, 0,       /* flip_xoff, flip_yoff */
343		0       /* col_base */
344		};
345
346	327	INTERRUPT_GEN_MEMBER(groundfx_state::groundfx_interrupt)
347	328	{
348	329	m_frame_counter^=1;
r29505	r29506
370	351	MCFG_GFXDECODE_ADD("gfxdecode", "palette", groundfx)
371	352	MCFG_PALETTE_ADD("palette", 16384)
372	353
373
374		MCFG_TC0100SCN_ADD("tc0100scn", groundfx_tc0100scn_intf)
	354	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	355	MCFG_TC0100SCN_GFX_REGION(2)
	356	MCFG_TC0100SCN_TX_REGION(3)
	357	MCFG_TC0100SCN_OFFSETS(50, 8)
375	358	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
376	359	MCFG_TC0100SCN_PALETTE("palette")
377		MCFG_TC0480SCP_ADD("tc0480scp", groundfx_tc0480scp_intf)
	360
	361	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	362	MCFG_TC0480SCP_GFX_REGION(1)
	363	MCFG_TC0480SCP_TX_REGION(4)
	364	MCFG_TC0480SCP_OFFSETS(0x24, 0)
	365	MCFG_TC0480SCP_OFFSETS_TX(-1, 0)
378	366	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
379	367	MCFG_TC0480SCP_PALETTE("palette")
380	368

branches/new_menus/src/mame/drivers/multigam.c

r29505	r29506
1155	1155	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
1156	1156	}
1157	1157
1158		/* our ppu interface                                            */
1159		static const ppu2c0x_interface ppu_interface =
1160		{
1161		"maincpu",
1162		0,                  /* gfxlayout num */
1163		0,                  /* color base */
1164		PPU_MIRROR_NONE     /* mirroring */
1165		};
1166
1167	1158	void multigam_state::video_start()
1168	1159	{
1169	1160	}
r29505	r29506
1263	1254	MCFG_PALETTE_ADD("palette", 8*4*16)
1264	1255	MCFG_PALETTE_INIT_OWNER(multigam_state, multigam)
1265	1256
1266		MCFG_PPU2C04_ADD("ppu", ppu_interface)
	1257	MCFG_PPU2C04_ADD("ppu")
	1258	MCFG_PPU2C0X_CPU("maincpu")
1267	1259	MCFG_PPU2C0X_SET_NMI(multigam_state, ppu_irq)
1268	1260
1269	1261	/* sound hardware */

branches/new_menus/src/mame/drivers/cbuster.c

r29505	r29506
258	258
259	259	/******************************************************************************/
260	260
261		int cbuster_state::bank_callback( int bank )
	261	DECO16IC_BANK_CB_MEMBER(cbuster_state::bank_callback)
262	262	{
263	263	return ((bank >> 4) & 0x7) * 0x1000;
264	264	}
r29505	r29506
330	330	MCFG_DECO16IC_PALETTE("palette")
331	331
332	332	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
333		decospr_device::set_gfx_region(*device, 3);
	333	MCFG_DECO_SPRITE_GFX_REGION(3)
334	334	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
335	335	MCFG_DECO_SPRITE_PALETTE("palette")
336	336

branches/new_menus/src/mame/drivers/tmnt.c

r29505	r29506
2085	2085	thndrx2_sprite_callback
2086	2086	};
2087	2087
2088
2089		/* 053936 interfaces */
2090		static const k053936_interface glfgreat_k053936_interface =
2091		{
2092		1, 85, 0        /* wrap, xoff, yoff */
2093		};
2094
2095		static const k053936_interface prmrsocr_k053936_interface =
2096		{
2097		0, 85, 1        /* wrap, xoff, yoff */
2098		};
2099
2100
2101	2088	MACHINE_START_MEMBER(tmnt_state,common)
2102	2089	{
2103	2090	save_item(NAME(m_toggle));
r29505	r29506
2496	2483	MCFG_K053245_ADD("k053245", glfgreat_k05324x_intf)
2497	2484	MCFG_K053245_GFXDECODE("gfxdecode")
2498	2485	MCFG_K053245_PALETTE("palette")
2499		MCFG_K053936_ADD("k053936", glfgreat_k053936_interface)
	2486
	2487	MCFG_DEVICE_ADD("k053936", K053936, 0)
	2488	MCFG_K053936_WRAP(1)
	2489	MCFG_K053936_OFFSETS(85, 0)
	2490
2500	2491	MCFG_K053251_ADD("k053251")
2501	2492
2502	2493	/* sound hardware */
r29505	r29506
2562	2553	MCFG_K053245_ADD("k053245", prmrsocr_k05324x_intf)
2563	2554	MCFG_K053245_GFXDECODE("gfxdecode")
2564	2555	MCFG_K053245_PALETTE("palette")
2565		MCFG_K053936_ADD("k053936", prmrsocr_k053936_interface)
	2556
	2557	MCFG_DEVICE_ADD("k053936", K053936, 0)
	2558	MCFG_K053936_OFFSETS(85, 1)
	2559
2566	2560	MCFG_K053251_ADD("k053251")
2567	2561
2568	2562	/* sound hardware */

branches/new_menus/src/mame/drivers/backfire.c

r29505	r29506
96	96	UINT32 screen_update_backfire_right(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
97	97	INTERRUPT_GEN_MEMBER(deco32_vbl_interrupt);
98	98	void descramble_sound();
99		int bank_callback(int bank);
100
	99	DECO16IC_BANK_CB_MEMBER(bank_callback);
	100	DECOSPR_PRIORITY_CB_MEMBER(pri_callback);
	101
101	102	required_ioport m_io_in0;
102	103	required_ioport m_io_in1;
103	104	required_ioport m_io_in2;
r29505	r29506
447	448	}
448	449
449	450
450
451		int backfire_state::bank_callback( int bank )
	451	DECO16IC_BANK_CB_MEMBER(backfire_state::bank_callback)
452	452	{
453	453	//  mame_printf_debug("bank callback %04x\n",bank); // bit 1 gets set too?
454	454	bank = bank >> 4;
r29505	r29506
457	457	return bank * 0x1000;
458	458	}
459	459
460		void backfire_state::machine_start()
	460	DECOSPR_PRIORITY_CB_MEMBER(backfire_state::pri_callback)
461	461	{
462		}
463
464		UINT16 backfire_pri_callback(UINT16 x)
465		{
466		switch (x & 0xc000)
	462	switch (pri & 0xc000)
467	463	{
468	464	case 0x0000: return 0;    // numbers, people, cars when in the air, status display..
469	465	case 0x4000: return 0xf0; // cars most of the time
r29505	r29506
473	469	return 0;
474	470	}
475	471
	472	void backfire_state::machine_start()
	473	{
	474	}
	475
476	476	static MACHINE_CONFIG_START( backfire, backfire_state )
477	477
478	478	/* basic machine hardware */
r29505	r29506
540	540
541	541	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
542	542	MCFG_VIDEO_SET_SCREEN("lscreen")
543		decospr_device::set_gfx_region(*device, 4);
544		decospr_device::set_pri_callback(*device, backfire_pri_callback);
	543	MCFG_DECO_SPRITE_GFX_REGION(4)
	544	MCFG_DECO_SPRITE_PRIORITY_CB(backfire_state, pri_callback)
545	545	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
546	546	MCFG_DECO_SPRITE_PALETTE("palette")
547	547
548	548	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
549	549	MCFG_VIDEO_SET_SCREEN("rscreen")
550		decospr_device::set_gfx_region(*device, 5);
551		decospr_device::set_pri_callback(*device, backfire_pri_callback);
	550	MCFG_DECO_SPRITE_GFX_REGION(5)
	551	MCFG_DECO_SPRITE_PRIORITY_CB(backfire_state, pri_callback)
552	552	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
553	553	MCFG_DECO_SPRITE_PALETTE("palette")
554	554

branches/new_menus/src/mame/drivers/proconn.c

r29505	r29506
30	30	#include "sound/ay8910.h"
31	31	#include "video/awpvid.h"
32	32	#include "machine/roc10937.h"
	33	#include "machine/meters.h"
33	34
34	35	#include "proconn.lh"
35	36
r29505	r29506
50	51	m_ay(*this, "aysnd")
51	52	{ }
52	53
53		optional_device<roc10937_t> m_vfd;
	54	optional_device<s16lf01_t> m_vfd;
54	55
55	56	DECLARE_WRITE8_MEMBER( ay_w0 ) { m_ay->address_data_w(space, 0, data); }
56	57	DECLARE_WRITE8_MEMBER( ay_w1 ) { m_ay->address_data_w(space, 1, data); }
r29505	r29506
186	187	required_device<z80sio_device> m_z80sio;
187	188	required_device<ay8910_device> m_ay;
188	189	public:
	190	int m_meter;
189	191	DECLARE_DRIVER_INIT(proconn);
190	192	virtual void machine_reset();
	193	DECLARE_WRITE8_MEMBER(meter_w);
191	194	DECLARE_WRITE16_MEMBER(serial_transmit);
192	195	DECLARE_READ16_MEMBER(serial_receive);
193	196	};
r29505	r29506
343	346
344	347	READ16_MEMBER(proconn_state::serial_receive)
345	348	{
	349	logerror("proconn serial receive read %x",offset);
346	350	return -1;
347	351	}
348	352
r29505	r29506
357	361	DEVCB_DRIVER_MEMBER16(proconn_state,serial_receive)     /* receive handler */
358	362	};
359	363
	364	WRITE8_MEMBER(proconn_state::meter_w)
	365	{
	366	int i;
	367	for (i=0; i<8; i++)
	368	{
	369	if ( data & (1 << i) )
	370	{
	371	MechMtr_update(i, data & (1 << i) );
	372	m_meter = data;
	373	}
	374	}
	375	}
	376
360	377	static const ay8910_interface ay8910_config =
361	378	{
362	379	AY8910_LEGACY_OUTPUT,
363	380	AY8910_DEFAULT_LOADS,
364	381	DEVCB_NULL,
365		DEVCB_NULL
	382	DEVCB_NULL,
	383	DEVCB_DRIVER_MEMBER(proconn_state,meter_w),
366	384	};
367	385
368	386
r29505	r29506
383	401	MCFG_CPU_CONFIG(z80_daisy_chain)
384	402	MCFG_CPU_PROGRAM_MAP(proconn_map)
385	403	MCFG_CPU_IO_MAP(proconn_portmap)
386		MCFG_ROC10937_ADD("vfd",0,LEFT_TO_RIGHT)
	404	MCFG_S16LF01_ADD("vfd",0)
387	405
388	406	MCFG_Z80PIO_ADD( "z80pio_1", 4000000, pio_interface_1 ) /* ?? Mhz */
389	407	MCFG_Z80PIO_ADD( "z80pio_2", 4000000, pio_interface_2 ) /* ?? Mhz */

branches/new_menus/src/mame/drivers/taito_x.c

r29505	r29506
414	414	AM_RANGE(0x400000, 0x400001) AM_WRITENOP    /* written each frame at $3aa2, mostly 0x10 */
415	415	AM_RANGE(0x500000, 0x500007) AM_READ(superman_dsw_input_r)
416	416	AM_RANGE(0x600000, 0x600001) AM_WRITENOP    /* written each frame at $3ab0, mostly 0x10 */
417		AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
418		AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	417	AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	418	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
419	419	AM_RANGE(0x900000, 0x9007ff) AM_READWRITE(cchip1_ram_r, cchip1_ram_w)
420	420	AM_RANGE(0x900802, 0x900803) AM_READWRITE(cchip1_ctrl_r, cchip1_ctrl_w)
421	421	AM_RANGE(0x900c00, 0x900c01) AM_WRITE(cchip1_bank_w)
r29505	r29506
431	431	//  AM_RANGE(0x400000, 0x400001) AM_WRITENOP    /* written each frame at $2ac, values change */
432	432	AM_RANGE(0x500000, 0x50000f) AM_READ(superman_dsw_input_r)
433	433	//  AM_RANGE(0x600000, 0x600001) AM_WRITENOP    /* written each frame at $2a2, values change */
434		AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
435		AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	434	AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	435	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
436	436	AM_RANGE(0x900000, 0x90000f) AM_READWRITE(daisenpu_input_r, daisenpu_input_w)
437	437	AM_RANGE(0xb00000, 0xb00fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
438	438	AM_RANGE(0xd00000, 0xd005ff) AM_RAM AM_DEVREADWRITE("spritegen", seta001_device, spriteylow_r16, spriteylow_w16) // Sprites Y
r29505	r29506
446	446	AM_RANGE(0x400000, 0x400001) AM_WRITENOP    /* 0x1 written each frame at $d42, watchdog? */
447	447	AM_RANGE(0x500000, 0x500007) AM_READ(superman_dsw_input_r)
448	448	AM_RANGE(0x600000, 0x600001) AM_WRITENOP    /* 0x1 written each frame at $d3c, watchdog? */
449		AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
450		AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	449	AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	450	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
451	451	AM_RANGE(0x900000, 0x90000f) AM_READWRITE(daisenpu_input_r, daisenpu_input_w)
452	452	AM_RANGE(0xb00000, 0xb00fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
453	453	AM_RANGE(0xd00000, 0xd005ff) AM_RAM AM_DEVREADWRITE("spritegen", seta001_device, spriteylow_r16, spriteylow_w16) // Sprites Y
r29505	r29506
461	461	AM_RANGE(0x400000, 0x400001) AM_WRITENOP    /* 0x1 written each frame at $c56, watchdog? */
462	462	AM_RANGE(0x500000, 0x50000f) AM_READ(superman_dsw_input_r)
463	463	AM_RANGE(0x600000, 0x600001) AM_WRITENOP    /* 0x1 written each frame at $c4e, watchdog? */
464		AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
465		AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	464	AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	465	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
466	466	AM_RANGE(0x900000, 0x90000f) AM_READWRITE(daisenpu_input_r, daisenpu_input_w)
467	467	AM_RANGE(0xb00000, 0xb00fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
468	468	AM_RANGE(0xd00000, 0xd005ff) AM_RAM AM_DEVREADWRITE("spritegen", seta001_device, spriteylow_r16, spriteylow_w16) // Sprites Y
r29505	r29506
479	479	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank2")
480	480	AM_RANGE(0xc000, 0xdfff) AM_RAM
481	481	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
482		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
483		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	482	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	483	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
484	484	AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
485	485	AM_RANGE(0xea00, 0xea00) AM_READNOP
486	486	AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
r29505	r29506
493	493	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank2")
494	494	AM_RANGE(0xc000, 0xdfff) AM_RAM
495	495	AM_RANGE(0xe000, 0xe001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
496		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
497		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	496	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	497	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
498	498	AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
499	499	AM_RANGE(0xea00, 0xea00) AM_READNOP
500	500	AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
r29505	r29506
796	796	save_item(NAME(m_cc_port));
797	797	}
798	798
799		static const tc0140syt_interface taitox_tc0140syt_intf =
800		{
801		"maincpu", "audiocpu"
802		};
803
804
805	799	/**************************************************************************/
806	800
807	801	static MACHINE_CONFIG_START( superman, taitox_state )
r29505	r29506
847	841	MCFG_SOUND_ROUTE(1, "lspeaker",  1.0)
848	842	MCFG_SOUND_ROUTE(2, "rspeaker", 1.0)
849	843
850		MCFG_TC0140SYT_ADD("tc0140syt", taitox_tc0140syt_intf)
	844	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	845	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	846	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
851	847	MACHINE_CONFIG_END
852	848
853	849	static MACHINE_CONFIG_START( daisenpu, taitox_state )
r29505	r29506
891	887	MCFG_SOUND_ROUTE(0, "lspeaker", 0.45)
892	888	MCFG_SOUND_ROUTE(1, "rspeaker", 0.45)
893	889
894		MCFG_TC0140SYT_ADD("tc0140syt", taitox_tc0140syt_intf)
	890	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	891	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	892	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
895	893	MACHINE_CONFIG_END
896	894
897	895	static MACHINE_CONFIG_START( gigandes, taitox_state )
r29505	r29506
937	935	MCFG_SOUND_ROUTE(1, "lspeaker",  1.0)
938	936	MCFG_SOUND_ROUTE(2, "rspeaker", 1.0)
939	937
940		MCFG_TC0140SYT_ADD("tc0140syt", taitox_tc0140syt_intf)
	938	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	939	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	940	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
941	941	MACHINE_CONFIG_END
942	942
943	943	static MACHINE_CONFIG_START( ballbros, taitox_state )
r29505	r29506
983	983	MCFG_SOUND_ROUTE(1, "lspeaker",  1.0)
984	984	MCFG_SOUND_ROUTE(2, "rspeaker", 1.0)
985	985
986		MCFG_TC0140SYT_ADD("tc0140syt", taitox_tc0140syt_intf)
	986	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	987	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	988	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
987	989	MACHINE_CONFIG_END
988	990
989	991

branches/new_menus/src/mame/drivers/tumblep.c

r29505	r29506
314	314	MCFG_DECO16IC_PALETTE("palette")
315	315
316	316	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
317		decospr_device::set_gfx_region(*device, 2);
	317	MCFG_DECO_SPRITE_GFX_REGION(2)
318	318	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
319	319	MCFG_DECO_SPRITE_PALETTE("palette")
320	320

branches/new_menus/src/mame/drivers/maygay1b.c

r29505	r29506
68	68	3x trimmer
69	69
70	70
71		TODO: Convert to stock i8279 implementation, as currently inputs aren't read.
72		Fix meter reading (possibly related to above)
	71	TODO: I/O is generally a nightmare, probably needs a rebuild at the address level.
	72	Inputs need a sort out.
	73	Some games require dongles for security, need to figure this out.
73	74	******************************************************************************************/
74	75	#include "emu.h"
75	76	#include "includes/maygay1b.h"
76	77
77	78	#include "maygay1b.lh"
78	79
79
80		void maygay1b_state::m1_draw_lamps(int data,int strobe, int col)
81		{
82		int i;
83
84		for ( i = 0; i < 8; i++ )
85		{
86		m_lamppos = (strobe*8) + col + i;
87
88		if ((data>>i)&1)
89		m_Lamps[m_lamppos] = 1;
90		else
91		m_Lamps[m_lamppos] = 0;
92
93		output_set_lamp_value(m_lamppos, m_Lamps[m_lamppos]);
94		}
95		}
96
97
98		/*************************************
99		*
100		*  8279 display/keyboard driver
101		*
102		*************************************/
103
104		void maygay1b_state::update_outputs(i8279_state *chip, UINT16 which)
105		{
106		static const UINT8 ls48_map[16] =
107		{ 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7c,0x07,0x7f,0x67,0x58,0x4c,0x62,0x69,0x78,0x00 };
108		int i;
109
110		/* update the items in the bitmask */
111		for (i = 0; i < 16; i++)
112		if (which & (1 << i))
113		{
114		int val;
115
116		val = chip->ram[i] & 0x0f;
117		if (chip->inhibit & 0x01)
118		val = chip->clear & 0x0f;
119		output_set_digit_value(i * 2 + 0, ls48_map[val]);
120
121		val = chip->ram[i] >> 4;
122		if (chip->inhibit & 0x02)
123		val = chip->clear >> 4;
124		output_set_digit_value(i * 2 + 1, ls48_map[val]);
125		}
126		}
127
128		READ8_MEMBER(maygay1b_state::m1_8279_r)
129		{
130		i8279_state *chip = m_i8279 + 0;
131		static const char *const portnames[] = { "SW1","STROBE5","STROBE7","STROBE3","SW2","STROBE4","STROBE6","STROBE2" };
132		UINT8 result = 0xff;
133		UINT8 addr;
134
135		/* read data */
136		if ((offset & 1) == 0)
137		{
138		switch (chip->command & 0xe0)
139		{
140		/* read sensor RAM */
141		case 0x40:
142		addr = chip->command & 0x07;
143		result = ioport("SW1")->read();
144		/* handle autoincrement */
145		if (chip->command & 0x10)
146		chip->command = (chip->command & 0xf0) | ((addr + 1) & 0x0f);
147
148		break;
149
150
151		/* read display RAM */
152		case 0x60:
153
154		/* set the value of the corresponding outputs */
155		addr = chip->command & 0x0f;
156		result = chip->ram[addr];
157
158		/* handle autoincrement */
159		if (chip->command & 0x10)
160		chip->command = (chip->command & 0xf0) | ((addr + 1) & 0x0f);
161		break;
162		}
163		}
164
165		/* read status word */
166		else
167		{
168		if ( chip->read_sensor )
169		{
170		result = ioport(portnames[chip->sense_address])->read();
171		//          break
172		}
173		if ( chip->sense_auto_inc )
174		{
175		chip->sense_address = (chip->sense_address + 1 ) & 7;
176		}
177		else
178		{
179		result = chip->ram[chip->disp_address];
180		if ( chip->disp_auto_inc )
181		chip->disp_address++;
182		}
183		}
184		return result;
185		}
186
187		WRITE8_MEMBER(maygay1b_state::m1_8279_w)
188		{
189		i8279_state *chip = m_i8279 + 0;
190		UINT8 addr;
191
192		/* write data */
193		if ((offset & 1) == 0)
194		{
195		switch (chip->command & 0xe0)
196		{
197		/* write display RAM */
198		case 0x80:
199
200		/* set the value of the corresponding outputs */
201		addr = chip->command & 0x0f;
202		if (!(chip->inhibit & 0x04))
203		chip->ram[addr] = (chip->ram[addr] & 0xf0) | (data & 0x0f);
204		if (!(chip->inhibit & 0x08))
205		chip->ram[addr] = (chip->ram[addr] & 0x0f) | (data & 0xf0);
206		update_outputs(chip, 1 << addr);
207
208		/* handle autoincrement */
209		if (chip->command & 0x10)
210		chip->command = (chip->command & 0xf0) | ((addr + 1) & 0x0f);
211		break;
212		}
213		}
214
215		/* write command */
216		else
217		{
218		chip->command = data;
219
220		switch (data & 0xe0)
221		{
222		/* command 0: set mode */
223		/*
224		Display modes:
225
226		00 = 8 x 8-bit character display -- left entry
227		01 = 16 x 8-bit character display -- left entry
228		10 = 8 x 8-bit character display -- right entry
229		11 = 16 x 8-bit character display -- right entry
230
231		Keyboard modes:
232
233		000 = Encoded scan keyboard -- 2 key lockout
234		001 = Decoded scan keyboard -- 2 key lockout
235		010 = Encoded scan keyboard -- N-key rollover
236		011 = Decoded scan keyboard -- N-key rollover
237		100 = Encoded scan sensor matrix
238		101 = Decoded scan sensor matrix
239		110 = Strobed input, encoded display scan
240		111 = Strobed input, decoded display scan
241		*/
242		case 0x00:
243		logerror("8279A: display mode = %d, keyboard mode = %d\n", (data >> 3) & 3, data & 7);
244		chip->mode = data & 0x1f;
245		break;
246
247		/* command 1: program clock */
248		case 0x20:
249		logerror("8279A: clock prescaler set to %02X\n", data & 0x1f);
250		chip->prescale = data & 0x1f;
251		break;
252
253		/* command 2: read FIFO/sensor RAM */
254		case 0x40:
255		chip->sense_address = data & 0x07;
256		chip->sense_auto_inc = data & 0x10;
257		chip->read_sensor = 1;
258		break;
259		/* command 3: read display RAM */
260		case 0x60:
261		chip->disp_address = data & 0x0f;
262		chip->disp_auto_inc = data & 0x10;
263		chip->read_sensor = 0;
264		break;
265		/* command 4: write display RAM */
266		case 0x80:
267		chip->disp_address = data & 0x0f;
268		chip->disp_auto_inc = data & 0x10;
269		chip->write_display = 1;
270		break;
271
272		/* command 5: display write inhibit/blanking */
273		case 0xa0:
274		chip->inhibit = data & 0x0f;
275		update_outputs(chip, 0);
276		logerror("8279: clock prescaler set to %02X\n", data & 0x1f);
277		break;
278
279		break;
280
281		/* command 6: clear */
282		case 0xc0:
283		chip->clear = (data & 0x08) ? ((data & 0x04) ? 0xff : 0x20) : 0x00;
284		if (data & 0x11)
285		memset(chip->ram, chip->clear, sizeof(chip->ram));
286		break;
287
288		/* command 7: end interrupt/error mode set */
289		case 0xe0:
290		break;
291		}
292		}
293		if ( chip->write_display )
294		{  // Data
295		assert(chip->disp_address < ARRAY_LENGTH(chip->ram));
296		if ( chip->ram[chip->disp_address] != data )
297		{
298		m1_draw_lamps(chip->ram[chip->disp_address],chip->disp_address, 0);
299		}
300		chip->ram[chip->disp_address] = data;
301
302		if ( chip->disp_auto_inc )
303		chip->disp_address ++;
304		}
305		}
306
307		READ8_MEMBER(maygay1b_state::m1_8279_2_r)
308		{
309		i8279_state *chip = m_i8279 + 1;
310		UINT8 result = 0xff;
311		UINT8 addr;
312
313		/* read data */
314		if ((offset & 1) == 0)
315		{
316		switch (chip->command & 0xe0)
317		{
318		/* read sensor RAM */
319		case 0x40:
320		//result = ~ioport("DSW1")->read();  /* DSW 1 - inverted! */
321		break;
322
323		/* read display RAM */
324		case 0x60:
325
326		/* set the value of the corresponding outputs */
327		addr = chip->command & 0x0f;
328		result = chip->ram[addr];
329
330		/* handle autoincrement */
331		if (chip->command & 0x10)
332		chip->command = (chip->command & 0xf0) | ((addr + 1) & 0x0f);
333		break;
334		}
335		}
336
337		/* read status word */
338		else
339		{
340		logerror("read 0xfc%02x\n", offset);
341		result = 0x10;
342		}
343		return result;
344		}
345
346
347		WRITE8_MEMBER(maygay1b_state::m1_8279_2_w)
348		{
349		i8279_state *chip = m_i8279 + 1;
350		UINT8 addr;
351
352		/* write data */
353		if ((offset & 1) == 0)
354		{
355		switch (chip->command & 0xe0)
356		{
357		/* write display RAM */
358		case 0x80:
359
360		/* set the value of the corresponding outputs */
361		addr = chip->command & 0x0f;
362		if (!(chip->inhibit & 0x04))
363		chip->ram[addr] = (chip->ram[addr] & 0xf0) | (data & 0x0f);
364		if (!(chip->inhibit & 0x08))
365		chip->ram[addr] = (chip->ram[addr] & 0x0f) | (data & 0xf0);
366		update_outputs(chip, 1 << addr);
367
368		/* handle autoincrement */
369		if (chip->command & 0x10)
370		chip->command = (chip->command & 0xf0) | ((addr + 1) & 0x0f);
371		break;
372		}
373		}
374
375		/* write command */
376		else
377		{
378		chip->command = data;
379
380		switch (data & 0xe0)
381		{
382		/* command 0: set mode */
383		/*
384		Display modes:
385
386		00 = 8 x 8-bit character display -- left entry
387		01 = 16 x 8-bit character display -- left entry
388		10 = 8 x 8-bit character display -- right entry
389		11 = 16 x 8-bit character display -- right entry
390
391		Keyboard modes:
392
393		000 = Encoded scan keyboard -- 2 key lockout
394		001 = Decoded scan keyboard -- 2 key lockout
395		010 = Encoded scan keyboard -- N-key rollover
396		011 = Decoded scan keyboard -- N-key rollover
397		100 = Encoded scan sensor matrix
398		101 = Decoded scan sensor matrix
399		110 = Strobed input, encoded display scan
400		111 = Strobed input, decoded display scan
401		*/
402		case 0x00:
403		logerror("8279A: display mode = %d, keyboard mode = %d\n", (data >> 3) & 3, data & 7);
404		chip->mode = data & 0x1f;
405		break;
406
407		/* command 1: program clock */
408		case 0x20:
409		logerror("8279A: clock prescaler set to %02X\n", data & 0x1f);
410		chip->prescale = data & 0x1f;
411		break;
412
413		/* command 2: read FIFO/sensor RAM */
414		case 0x40:
415		chip->sense_address = data & 0x07;
416		chip->sense_auto_inc = data & 0x10;
417		chip->read_sensor = 1;
418		break;
419		/* command 3: read display RAM */
420		case 0x60:
421		chip->disp_address = data & 0x0f;
422		chip->disp_auto_inc = data & 0x10;
423		chip->read_sensor = 0;
424		break;
425		/* command 4: write display RAM */
426		case 0x80:
427		chip->disp_address = data & 0x0f;
428		chip->disp_auto_inc = data & 0x10;
429		chip->write_display = 1;
430		break;
431
432		/* command 5: display write inhibit/blanking */
433		case 0xa0:
434		break;
435
436		/* command 6: clear */
437		case 0xc0:
438		break;
439
440		/* command 7: end interrupt/error mode set */
441		case 0xe0:
442		break;
443		}
444		}
445		if ( chip->write_display )
446		{  // Data
447		if ( chip->ram[chip->disp_address] != data )
448		{
449		m1_draw_lamps(chip->ram[chip->disp_address],chip->disp_address, 128);
450		}
451		chip->ram[chip->disp_address] = data;
452		if ( chip->disp_auto_inc )
453		chip->disp_address ++;
454		}
455
456		}
457
458	80	///////////////////////////////////////////////////////////////////////////
459	81	// called if board is reset ///////////////////////////////////////////////
460	82	///////////////////////////////////////////////////////////////////////////
r29505	r29506
495	117	return i;
496	118	}
497	119
	120	READ8_MEMBER( maygay1b_state::m1_firq_clr_r )
	121	{
	122	static int i = 0xff;
	123	i ^= 0xff;
	124	m_maincpu->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
	125	LOG(("6809 firq clr\n"));
	126	return i;
	127	}
	128
498	129	// NMI is periodic? or triggered by a write?
499	130	TIMER_DEVICE_CALLBACK_MEMBER( maygay1b_state::maygay1b_nmitimer_callback )
500	131	{
r29505	r29506
784	415
785	416	READ8_MEMBER(maygay1b_state::m1_meter_r)
786	417	{
787		//ay8910_device *ay8910 = machine().device<ay8910_device>("aysnd");
788		//return ay8910->data_r(space, offset);
789
790		//TODO: Game should read the meter state through Port A of the AY chip, but our timings aren't good enough (?)
	418	//TODO: Can we just return the AY port A data?
791	419	return m_meter;
792	420	}
	421	WRITE8_MEMBER(maygay1b_state::m1_lockout_w)
	422	{
	423	int i;
	424	for (i=0; i<6; i++)
	425	{
	426	coin_lockout_w(machine(), i, data & (1 << i) );
	427	}
	428	}
793	429
794	430	static ADDRESS_MAP_START( m1_memmap, AS_PROGRAM, 8, maygay1b_state )
795	431	AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("nvram")
r29505	r29506
798	434	AM_RANGE(0x2010, 0x2010) AM_WRITE(reel34_w)
799	435	AM_RANGE(0x2020, 0x2020) AM_WRITE(reel56_w)
800	436
801		// there is actually an 8279 and an 8051..
802		AM_RANGE(0x2030, 0x2031) AM_READWRITE(m1_8279_r,m1_8279_w)
803		AM_RANGE(0x2040, 0x2041) AM_READWRITE(m1_8279_2_r,m1_8279_2_w)
	437	// there is actually an 8279 and an 8051 (which I guess is the MCU?).
	438	AM_RANGE(0x2030, 0x2030) AM_DEVREADWRITE("i8279", i8279_device, data_r, data_w )
	439	AM_RANGE(0x2031, 0x2031) AM_DEVREADWRITE("i8279", i8279_device, status_r, cmd_w)
	440
	441	//8051
	442	AM_RANGE(0x2040, 0x2040) AM_DEVREADWRITE("i8279_2", i8279_device, data_r, data_w )
	443	AM_RANGE(0x2041, 0x2041) AM_DEVREADWRITE("i8279_2", i8279_device, status_r, cmd_w)
804	444	//  AM_RANGE(0x2050, 0x2050)// SCAN on M1B
805	445
806	446	AM_RANGE(0x2070, 0x207f) AM_DEVREADWRITE("duart68681", mc68681_device, read, write )
r29505	r29506
817	457	AM_RANGE(0x2404, 0x2405) AM_READ(latch_st_lo)
818	458	AM_RANGE(0x2406, 0x2407) AM_READ(latch_st_hi)
819	459
	460	AM_RANGE(0x2410, 0x2410) AM_READ(m1_firq_clr_r)
	461
820	462	AM_RANGE(0x2412, 0x2412) AM_READ(m1_firq_trg_r) // firq, sample playback?
821	463
822	464	AM_RANGE(0x2420, 0x2421) AM_WRITE(latch_ch2_w ) // oki
r29505	r29506
831	473	DEVCB_NULL,
832	474	DEVCB_NULL,
833	475	DEVCB_DRIVER_MEMBER(maygay1b_state,m1_meter_w),
834		DEVCB_NULL,
	476	DEVCB_DRIVER_MEMBER(maygay1b_state,m1_lockout_w),
835	477	};
836	478
	479	/*************************************
	480	*
	481	*  8279 display/keyboard driver
	482	*
	483	*************************************/
	484
	485	WRITE8_MEMBER( maygay1b_state::scanlines_w )
	486	{
	487	m_lamp_strobe = data;
	488	}
	489
	490	WRITE8_MEMBER( maygay1b_state::lamp_data_w )
	491	{
	492	//The two A/B ports are merged back into one, to make one row of 8 lamps.
	493
	494	if (m_old_lamp_strobe != m_lamp_strobe)
	495	{
	496	// Because of the nature of the lamping circuit, there is an element of persistance
	497	// As a consequence, the lamp column data can change before the input strobe without
	498	// causing the relevant lamps to black out.
	499
	500	for (int i = 0; i < 8; i++)
	501	{
	502	output_set_lamp_value((8*m_lamp_strobe)+i, ((data  & (1 << i)) !=0));
	503	}
	504	m_old_lamp_strobe = m_lamp_strobe;
	505	}
	506
	507	}
	508
	509	READ8_MEMBER( maygay1b_state::kbd_r )
	510	{
	511	ioport_port * portnames[] = { m_sw1_port, m_s2_port, m_s3_port, m_s4_port, m_s5_port, m_s6_port, m_s7_port, m_sw2_port};
	512	return (portnames[m_lamp_strobe&0x07])->read();
	513	}
	514
	515	/*
	516	static I8279_INTERFACE( m1_i8279_intf )
	517	{
	518	DEVCB_NULL,                                     // irq
	519	DEVCB_DRIVER_MEMBER(maygay1b_state, scanlines_w),  // scan SL lines
	520	DEVCB_DRIVER_MEMBER(maygay1b_state, lamp_data_w),      // display A&B
	521	DEVCB_NULL,                                     // BD
	522	DEVCB_DRIVER_MEMBER(maygay1b_state,kbd_r),      // kbd RL lines
	523	DEVCB_NULL,                                     // Shift key
	524	DEVCB_NULL                                      // Ctrl-Strobe line
	525	};
	526	*/
	527
	528
	529
	530	WRITE8_MEMBER( maygay1b_state::lamp_data_2_w )
	531	{
	532	//The two A/B ports are merged back into one, to make one row of 8 lamps.
	533
	534	if (m_old_lamp_strobe2 != m_lamp_strobe2)
	535	{
	536	// Because of the nature of the lamping circuit, there is an element of persistance
	537	// As a consequence, the lamp column data can change before the input strobe without
	538	// causing the relevant lamps to black out.
	539
	540	for (int i = 0; i < 8; i++)
	541	{
	542	output_set_lamp_value((8*m_lamp_strobe)+i+128, ((data  & (1 << i)) !=0));
	543	}
	544	m_old_lamp_strobe2 = m_lamp_strobe2;
	545	}
	546
	547	}
	548
	549	/*
	550	static I8279_INTERFACE( m1_i8279_2_intf )
	551	{
	552	DEVCB_NULL,                                     // irq
	553	DEVCB_NULL,  // scan SL lines
	554	DEVCB_DRIVER_MEMBER(maygay1b_state, lamp_data_2_w),      // display A&B
	555	DEVCB_NULL,                                     // BD
	556	DEVCB_NULL,                                   // kbd RL lines
	557	DEVCB_NULL,                                     // Shift key
	558	DEVCB_NULL                                      // Ctrl-Strobe line
	559	};
	560	*/
	561
837	562	// machine driver for maygay m1 board /////////////////////////////////
838	563
839	564
r29505	r29506
851	576	MCFG_PIA_WRITEPA_HANDLER(WRITE8(maygay1b_state, m1_pia_porta_w))
852	577	MCFG_PIA_WRITEPB_HANDLER(WRITE8(maygay1b_state, m1_pia_portb_w))
853	578
854		MCFG_MSC1937_ADD("vfd",0,RIGHT_TO_LEFT)
	579	MCFG_S16LF01_ADD("vfd",0)
855	580	MCFG_SPEAKER_STANDARD_MONO("mono")
856	581	MCFG_SOUND_ADD("aysnd",YM2149, M1_MASTER_CLOCK)
857	582	MCFG_SOUND_CONFIG(ay8910_config)
r29505	r29506
863	588	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
864	589
865	590	MCFG_TIMER_DRIVER_ADD_PERIODIC("nmitimer", maygay1b_state, maygay1b_nmitimer_callback, attotime::from_hz(75)) // freq?
	591	MCFG_DEVICE_ADD("i8279", I8279, M1_MASTER_CLOCK/4)    // unknown clock
	592	MCFG_DEVICE_ADD("i8279_2", I8279, M1_MASTER_CLOCK/4)    // unknown clock
866	593
	594	//   MCFG_I8279_ADD("i8279", M1_MASTER_CLOCK/4, m1_i8279_intf)    // unknown clock
	595	//   MCFG_I8279_ADD("i8279_2", M1_MASTER_CLOCK/4, m1_i8279_2_intf)    // unknown clock
	596
867	597	MCFG_NVRAM_ADD_0FILL("nvram")
868	598
869	599	MCFG_DEFAULT_LAYOUT(layout_maygay1b)

branches/new_menus/src/mame/drivers/simpl156.c

r29505	r29506
387	387	}
388	388
389	389
390		int simpl156_state::bank_callback(int bank)
	390	DECO16IC_BANK_CB_MEMBER(simpl156_state::bank_callback)
391	391	{
392	392	return ((bank >> 4) & 0x7) * 0x1000;
393	393	}
394	394
395		UINT16 simpl156_pri_callback(UINT16 x)
	395	DECOSPR_PRIORITY_CB_MEMBER(simpl156_state::pri_callback)
396	396	{
397		switch (x & 0xc000)
	397	switch (pri & 0xc000)
398	398	{
399	399	case 0x0000: return 0;
400	400	case 0x4000: return 0xf0;
r29505	r29506
444	444	MCFG_DECO16IC_PALETTE("palette")
445	445
446	446	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
447		decospr_device::set_gfx_region(*device, 2);
448		decospr_device::set_pri_callback(*device, simpl156_pri_callback);
	447	MCFG_DECO_SPRITE_GFX_REGION(2)
	448	MCFG_DECO_SPRITE_PRIORITY_CB(simpl156_state, pri_callback)
449	449	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
450	450	MCFG_DECO_SPRITE_PALETTE("palette")
451	451

branches/new_menus/src/mame/drivers/namcos2.c

r29505	r29506
1862	1862	MCFG_VIDEO_START_OVERRIDE(namcos2_state, finallap)
1863	1863
1864	1864	MCFG_NAMCO_C45_ROAD_ADD("c45_road")
1865		MCFG_NAMCO_C45_ROAD_PALETTE("palette")
	1865	MCFG_GFX_PALETTE("palette")
1866	1866
1867	1867	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1868	1868
r29505	r29506
2020	2020	MCFG_VIDEO_START_OVERRIDE(namcos2_state, luckywld)
2021	2021
2022	2022	MCFG_NAMCO_C45_ROAD_ADD("c45_road")
2023		MCFG_NAMCO_C45_ROAD_PALETTE("palette")
	2023	MCFG_GFX_PALETTE("palette")
2024	2024
2025	2025	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
2026	2026

branches/new_menus/src/mame/drivers/exzisus.c

r29505	r29506
151	151	AM_RANGE(0xc000, 0xc5ff) AM_READWRITE(exzisus_objectram_0_r, exzisus_objectram_0_w) AM_SHARE("objectram0")
152	152	AM_RANGE(0xc600, 0xdfff) AM_READWRITE(exzisus_videoram_0_r, exzisus_videoram_0_w) AM_SHARE("videoram0")
153	153	AM_RANGE(0xe000, 0xefff) AM_RAM
154		AM_RANGE(0xf000, 0xf000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_port_w)
155		AM_RANGE(0xf001, 0xf001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w)
	154	AM_RANGE(0xf000, 0xf000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, master_port_w)
	155	AM_RANGE(0xf001, 0xf001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w)
156	156	AM_RANGE(0xf400, 0xf400) AM_READ_PORT("P1")
157	157	AM_RANGE(0xf400, 0xf400) AM_WRITE(exzisus_cpub_bankswitch_w)
158	158	AM_RANGE(0xf401, 0xf401) AM_READ_PORT("P2")
r29505	r29506
176	176	AM_RANGE(0x0000, 0x7fff) AM_ROM
177	177	AM_RANGE(0x8000, 0x8fff) AM_RAM
178	178	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
179		AM_RANGE(0xa000, 0xa000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
180		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	179	AM_RANGE(0xa000, 0xa000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	180	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
181	181	ADDRESS_MAP_END
182	182
183	183
r29505	r29506
252	252
253	253
254	254
255		static const tc0140syt_interface exzisus_tc0140syt_intf =
256		{
257		"cpub", "audiocpu"
258		};
259
260	255	/* All clocks are unconfirmed */
261	256	static MACHINE_CONFIG_START( exzisus, exzisus_state )
262	257
r29505	r29506
298	293	MCFG_SOUND_ROUTE(0, "mono", 0.50)
299	294	MCFG_SOUND_ROUTE(1, "mono", 0.50)
300	295
301		MCFG_TC0140SYT_ADD("tc0140syt", exzisus_tc0140syt_intf)
	296	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	297	MCFG_TC0140SYT_MASTER_CPU("cpub")
	298	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
302	299	MACHINE_CONFIG_END
303	300
304	301

branches/new_menus/src/mame/drivers/undrfire.c

r29505	r29506
696	696	device.execute().set_input_line(4, HOLD_LINE);
697	697	}
698	698
699		static const tc0100scn_interface undrfire_tc0100scn_intf =
700		{
701		2, 3,       /* gfxnum, txnum */
702		50, 8,      /* x_offset, y_offset */
703		0, 0,       /* flip_xoff, flip_yoff */
704		0, 0,       /* flip_text_xoff, flip_text_yoff */
705		0, 0
706		};
707
708		static const tc0480scp_interface undrfire_tc0480scp_intf =
709		{
710		1, 4,       /* gfxnum, txnum */
711		0,      /* pixels */
712		0x24, 0,        /* x_offset, y_offset */
713		-1, 0,      /* text_xoff, text_yoff */
714		0, 0,       /* flip_xoff, flip_yoff */
715		0       /* col_base */
716		};
717
718	699	static MACHINE_CONFIG_START( undrfire, undrfire_state )
719	700
720	701	/* basic machine hardware */
r29505	r29506
736	717	MCFG_GFXDECODE_ADD("gfxdecode", "palette", undrfire)
737	718	MCFG_PALETTE_ADD("palette", 16384)
738	719
739
740		MCFG_TC0100SCN_ADD("tc0100scn", undrfire_tc0100scn_intf)
	720	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	721	MCFG_TC0100SCN_GFX_REGION(2)
	722	MCFG_TC0100SCN_TX_REGION(3)
	723	MCFG_TC0100SCN_OFFSETS(50, 8)
741	724	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
742	725	MCFG_TC0100SCN_PALETTE("palette")
743		MCFG_TC0480SCP_ADD("tc0480scp", undrfire_tc0480scp_intf)
	726
	727	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	728	MCFG_TC0480SCP_GFX_REGION(1)
	729	MCFG_TC0480SCP_TX_REGION(4)
	730	MCFG_TC0480SCP_OFFSETS(0x24, 0)
	731	MCFG_TC0480SCP_OFFSETS_TX(-1, 0)
744	732	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
745	733	MCFG_TC0480SCP_PALETTE("palette")
746	734
r29505	r29506
776	764	MCFG_GFXDECODE_ADD("gfxdecode", "palette", cbombers)
777	765	MCFG_PALETTE_ADD("palette", 16384)
778	766
779
780		MCFG_TC0100SCN_ADD("tc0100scn", undrfire_tc0100scn_intf)
	767	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	768	MCFG_TC0100SCN_GFX_REGION(2)
	769	MCFG_TC0100SCN_TX_REGION(3)
	770	MCFG_TC0100SCN_OFFSETS(50, 8)
781	771	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
782	772	MCFG_TC0100SCN_PALETTE("palette")
783	773
784		MCFG_TC0480SCP_ADD("tc0480scp", undrfire_tc0480scp_intf)
	774	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	775	MCFG_TC0480SCP_GFX_REGION(1)
	776	MCFG_TC0480SCP_TX_REGION(4)
	777	MCFG_TC0480SCP_OFFSETS(0x24, 0)
	778	MCFG_TC0480SCP_OFFSETS_TX(-1, 0)
785	779	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
786	780	MCFG_TC0480SCP_PALETTE("palette")
787	781

branches/new_menus/src/mame/drivers/taito_z.c

r29505	r29506
1404	1404	WRITE16_MEMBER(taitoz_state::taitoz_sound_w)
1405	1405	{
1406	1406	if (offset == 0)
1407		m_tc0140syt->tc0140syt_port_w(space, 0, data & 0xff);
	1407	m_tc0140syt->master_port_w(space, 0, data & 0xff);
1408	1408	else if (offset == 1)
1409		m_tc0140syt->tc0140syt_comm_w(space, 0, data & 0xff);
	1409	m_tc0140syt->master_comm_w(space, 0, data & 0xff);
1410	1410
1411	1411	#ifdef MAME_DEBUG
1412	1412	//  if (data & 0xff00)
r29505	r29506
1422	1422	READ16_MEMBER(taitoz_state::taitoz_sound_r)
1423	1423	{
1424	1424	if (offset == 1)
1425		return (m_tc0140syt->tc0140syt_comm_r(space, 0) & 0xff);
	1425	return (m_tc0140syt->master_comm_r(space, 0) & 0xff);
1426	1426	else
1427	1427	return 0;
1428	1428	}
r29505	r29506
1431	1431	WRITE16_MEMBER(taitoz_state::taitoz_msb_sound_w)
1432	1432	{
1433	1433	if (offset == 0)
1434		m_tc0140syt->tc0140syt_port_w(0, (data >> 8) & 0xff);
	1434	m_tc0140syt->master_port_w(0, (data >> 8) & 0xff);
1435	1435	else if (offset == 1)
1436		m_tc0140syt->tc0140syt_comm_w(0, (data >> 8) & 0xff);
	1436	m_tc0140syt->master_comm_w(0, (data >> 8) & 0xff);
1437	1437
1438	1438	#ifdef MAME_DEBUG
1439	1439	if (data & 0xff)
r29505	r29506
1449	1449	READ16_MEMBER(taitoz_state::taitoz_msb_sound_r)
1450	1450	{
1451	1451	if (offset == 1)
1452		return ((m_tc0140syt->tc0140syt_comm_r(0) & 0xff) << 8);
	1452	return ((m_tc0140syt->master_comm_r(0) & 0xff) << 8);
1453	1453	else
1454	1454	return 0;
1455	1455	}
r29505	r29506
1733	1733	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank10")
1734	1734	AM_RANGE(0xc000, 0xdfff) AM_RAM
1735	1735	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
1736		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
1737		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	1736	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	1737	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
1738	1738	AM_RANGE(0xe400, 0xe403) AM_WRITE(taitoz_pancontrol) /* pan */
1739	1739	AM_RANGE(0xea00, 0xea00) AM_READNOP
1740	1740	AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
r29505	r29506
2955	2955
2956	2956	***********************************************************/
2957	2957
2958
2959		static const tc0100scn_interface taitoz_tc0100scn_intf =
2960		{
2961		1, 2,       /* gfxnum, txnum */
2962		0, 0,       /* x_offset, y_offset */
2963		0, 0,       /* flip_xoff, flip_yoff */
2964		0, 0,       /* flip_text_xoff, flip_text_yoff */
2965		0, 0
2966		};
2967
2968		static const tc0100scn_interface chasehq_tc0100scn_intf =
2969		{
2970		1, 3,       /* gfxnum, txnum */
2971		0, 0,       /* x_offset, y_offset */
2972		0, 0,       /* flip_xoff, flip_yoff */
2973		0, 0,       /* flip_text_xoff, flip_text_yoff */
2974		0, 0
2975		};
2976
2977		static const tc0100scn_interface spacegun_tc0100scn_intf =
2978		{
2979		1, 2,       /* gfxnum, txnum */
2980		4, 0,       /* x_offset, y_offset */
2981		0, 0,       /* flip_xoff, flip_yoff */
2982		0, 0,       /* flip_text_xoff, flip_text_yoff */
2983		0, 0
2984		};
2985
2986		static const tc0480scp_interface taitoz_tc0480scp_intf =
2987		{
2988		1, 2,       /* gfxnum, txnum */
2989		0,          /* pixels */
2990		0x1f, 0x08, /* x_offset, y_offset */
2991		0, 0,       /* text_xoff, text_yoff */
2992		0, 0,       /* flip_xoff, flip_yoff */
2993		0           /* col_base */
2994		};
2995
2996
2997		static const tc0150rod_interface taitoz_tc0150rod_intf = { "gfx3" };
2998
2999
3000		static const tc0140syt_interface taitoz_tc0140syt_intf =
3001		{
3002		"sub", "audiocpu"
3003		};
3004
3005
3006	2958	/***********************************************************
3007	2959	SAVE STATES
3008	2960	***********************************************************/
r29505	r29506
3084	3036
3085	3037	MCFG_VIDEO_START_OVERRIDE(taitoz_state,taitoz)
3086	3038
3087		MCFG_TC0100SCN_ADD("tc0100scn", taitoz_tc0100scn_intf)
	3039	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3040	MCFG_TC0100SCN_GFX_REGION(1)
	3041	MCFG_TC0100SCN_TX_REGION(2)
3088	3042	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3089	3043	MCFG_TC0100SCN_PALETTE("palette")
3090	3044
3091		MCFG_TC0150ROD_ADD("tc0150rod", taitoz_tc0150rod_intf)
	3045	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
	3046	MCFG_TC0150ROD_GFXTAG("gfx3")
	3047
3092	3048	MCFG_TC0110PCR_ADD("tc0110pcr")
3093	3049	MCFG_TC0110PCR_PALETTE("palette")
3094	3050
r29505	r29506
3114	3070	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3115	3071	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "front", 1.0)
3116	3072
3117		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
	3073	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3074	MCFG_TC0140SYT_MASTER_CPU("sub")
	3075	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3118	3076	MACHINE_CONFIG_END
3119	3077
3120	3078
r29505	r29506
3157	3115
3158	3116	MCFG_VIDEO_START_OVERRIDE(taitoz_state,taitoz)
3159	3117
3160		MCFG_TC0100SCN_ADD("tc0100scn", chasehq_tc0100scn_intf)
	3118	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3119	MCFG_TC0100SCN_GFX_REGION(1)
	3120	MCFG_TC0100SCN_TX_REGION(3)
3161	3121	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3162	3122	MCFG_TC0100SCN_PALETTE("palette")
3163	3123
3164		MCFG_TC0150ROD_ADD("tc0150rod", taitoz_tc0150rod_intf)
	3124	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
	3125	MCFG_TC0150ROD_GFXTAG("gfx3")
	3126
3165	3127	MCFG_TC0110PCR_ADD("tc0110pcr")
3166	3128	MCFG_TC0110PCR_PALETTE("palette")
3167	3129
r29505	r29506
3187	3149	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3188	3150	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "front", 1.0)
3189	3151
3190		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
	3152	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3153	MCFG_TC0140SYT_MASTER_CPU("sub")
	3154	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3191	3155	MACHINE_CONFIG_END
3192	3156
3193	3157
r29505	r29506
3232	3196
3233	3197	MCFG_VIDEO_START_OVERRIDE(taitoz_state,taitoz)
3234	3198
3235		MCFG_TC0100SCN_ADD("tc0100scn", taitoz_tc0100scn_intf)
	3199	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3200	MCFG_TC0100SCN_GFX_REGION(1)
	3201	MCFG_TC0100SCN_TX_REGION(2)
3236	3202	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3237	3203	MCFG_TC0100SCN_PALETTE("palette")
3238	3204
3239		MCFG_TC0150ROD_ADD("tc0150rod", taitoz_tc0150rod_intf)
	3205	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
	3206	MCFG_TC0150ROD_GFXTAG("gfx3")
	3207
3240	3208	MCFG_TC0110PCR_ADD("tc0110pcr")
3241	3209	MCFG_TC0110PCR_PALETTE("palette")
3242	3210
r29505	r29506
3261	3229	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3262	3230	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
3263	3231
3264		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
	3232	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3233	MCFG_TC0140SYT_MASTER_CPU("sub")
	3234	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3265	3235	MACHINE_CONFIG_END
3266	3236
3267	3237
r29505	r29506
3303	3273
3304	3274	MCFG_VIDEO_START_OVERRIDE(taitoz_state,taitoz)
3305	3275
3306		MCFG_TC0100SCN_ADD("tc0100scn", taitoz_tc0100scn_intf)
	3276	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3277	MCFG_TC0100SCN_GFX_REGION(1)
	3278	MCFG_TC0100SCN_TX_REGION(2)
3307	3279	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3308	3280	MCFG_TC0100SCN_PALETTE("palette")
3309	3281
3310		MCFG_TC0150ROD_ADD("tc0150rod", taitoz_tc0150rod_intf)
	3282	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
	3283	MCFG_TC0150ROD_GFXTAG("gfx3")
3311	3284
3312	3285	/* sound hardware */
3313	3286	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r29505	r29506
3329	3302	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
3330	3303	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3331	3304	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
3332
3333		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
3334	3305	MACHINE_CONFIG_END
3335	3306
3336	3307	static MACHINE_CONFIG_DERIVED( bsharkjjs, bshark )
r29505	r29506
3384	3355
3385	3356	MCFG_VIDEO_START_OVERRIDE(taitoz_state,taitoz)
3386	3357
3387		MCFG_TC0100SCN_ADD("tc0100scn", taitoz_tc0100scn_intf)
	3358	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3359	MCFG_TC0100SCN_GFX_REGION(1)
	3360	MCFG_TC0100SCN_TX_REGION(2)
3388	3361	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3389	3362	MCFG_TC0100SCN_PALETTE("palette")
3390	3363
3391		MCFG_TC0150ROD_ADD("tc0150rod", taitoz_tc0150rod_intf)
	3364	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
	3365	MCFG_TC0150ROD_GFXTAG("gfx3")
3392	3366
3393	3367	/* sound hardware */
3394	3368	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r29505	r29506
3411	3385	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3412	3386	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
3413	3387
3414		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
	3388	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3389	MCFG_TC0140SYT_MASTER_CPU("sub")
	3390	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3415	3391	MACHINE_CONFIG_END
3416	3392
3417	3393
r29505	r29506
3456	3432
3457	3433	MCFG_VIDEO_START_OVERRIDE(taitoz_state,taitoz)
3458	3434
3459		MCFG_TC0100SCN_ADD("tc0100scn", chasehq_tc0100scn_intf)
	3435	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3436	MCFG_TC0100SCN_GFX_REGION(1)
	3437	MCFG_TC0100SCN_TX_REGION(3)
3460	3438	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3461	3439	MCFG_TC0100SCN_PALETTE("palette")
3462	3440
3463		MCFG_TC0150ROD_ADD("tc0150rod", taitoz_tc0150rod_intf)
	3441	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
	3442	MCFG_TC0150ROD_GFXTAG("gfx3")
	3443
3464	3444	MCFG_TC0110PCR_ADD("tc0110pcr")
3465	3445	MCFG_TC0110PCR_PALETTE("palette")
3466	3446
r29505	r29506
3486	3466	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3487	3467	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "front", 1.0)
3488	3468
3489		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
	3469	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3470	MCFG_TC0140SYT_MASTER_CPU("sub")
	3471	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3490	3472	MACHINE_CONFIG_END
3491	3473
3492	3474
r29505	r29506
3531	3513
3532	3514	MCFG_VIDEO_START_OVERRIDE(taitoz_state,taitoz)
3533	3515
3534		MCFG_TC0100SCN_ADD("tc0100scn", taitoz_tc0100scn_intf)
	3516	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3517	MCFG_TC0100SCN_GFX_REGION(1)
	3518	MCFG_TC0100SCN_TX_REGION(2)
3535	3519	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3536	3520	MCFG_TC0100SCN_PALETTE("palette")
3537	3521
3538		MCFG_TC0150ROD_ADD("tc0150rod", taitoz_tc0150rod_intf)
	3522	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
	3523	MCFG_TC0150ROD_GFXTAG("gfx3")
	3524
3539	3525	MCFG_TC0110PCR_ADD("tc0110pcr")
3540	3526	MCFG_TC0110PCR_PALETTE("palette")
3541	3527
r29505	r29506
3560	3546	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3561	3547	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
3562	3548
3563		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
	3549	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3550	MCFG_TC0140SYT_MASTER_CPU("sub")
	3551	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3564	3552	MACHINE_CONFIG_END
3565	3553
3566	3554
r29505	r29506
3601	3589	MCFG_PALETTE_ADD("palette", 4096)
3602	3590	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
3603	3591
3604		MCFG_TC0100SCN_ADD("tc0100scn", spacegun_tc0100scn_intf)
	3592	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	3593	MCFG_TC0100SCN_GFX_REGION(1)
	3594	MCFG_TC0100SCN_TX_REGION(2)
	3595	MCFG_TC0100SCN_OFFSETS(4, 0)
3605	3596	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
3606	3597	MCFG_TC0100SCN_PALETTE("palette")
3607	3598
r29505	r29506
3628	3619	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
3629	3620	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3630	3621	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
3631
3632		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
3633	3622	MACHINE_CONFIG_END
3634	3623
3635	3624
r29505	r29506
3674	3663
3675	3664	MCFG_VIDEO_START_OVERRIDE(taitoz_state,taitoz)
3676	3665
3677		MCFG_TC0480SCP_ADD("tc0480scp", taitoz_tc0480scp_intf)
	3666	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	3667	MCFG_TC0480SCP_GFX_REGION(1)
	3668	MCFG_TC0480SCP_TX_REGION(2)
	3669	MCFG_TC0480SCP_OFFSETS(0x1f, 0x08)
3678	3670	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
3679	3671	MCFG_TC0480SCP_PALETTE("palette")
3680	3672
3681		MCFG_TC0150ROD_ADD("tc0150rod", taitoz_tc0150rod_intf)
	3673	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
	3674	MCFG_TC0150ROD_GFXTAG("gfx3")
3682	3675
3683	3676	/* sound hardware */
3684	3677	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r29505	r29506
3701	3694	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3702	3695	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
3703	3696
3704		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
	3697	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3698	MCFG_TC0140SYT_MASTER_CPU("sub")
	3699	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3705	3700	MACHINE_CONFIG_END
3706	3701
3707	3702
r29505	r29506
3745	3740	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
3746	3741	MCFG_VIDEO_START_OVERRIDE(taitoz_state,taitoz)
3747	3742
3748		MCFG_TC0480SCP_ADD("tc0480scp", taitoz_tc0480scp_intf)
	3743	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	3744	MCFG_TC0480SCP_GFX_REGION(1)
	3745	MCFG_TC0480SCP_TX_REGION(2)
	3746	MCFG_TC0480SCP_OFFSETS(0x1f, 0x08)
3749	3747	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
3750	3748	MCFG_TC0480SCP_PALETTE("palette")
3751	3749
3752		MCFG_TC0150ROD_ADD("tc0150rod", taitoz_tc0150rod_intf)
	3750	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
	3751	MCFG_TC0150ROD_GFXTAG("gfx3")
3753	3752
3754	3753	/* sound hardware */
3755	3754	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r29505	r29506
3772	3771	MCFG_FILTER_VOLUME_ADD("2610.2.l", 0)
3773	3772	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
3774	3773
3775		MCFG_TC0140SYT_ADD("tc0140syt", taitoz_tc0140syt_intf)
	3774	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	3775	MCFG_TC0140SYT_MASTER_CPU("sub")
	3776	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
3776	3777	MACHINE_CONFIG_END
3777	3778
3778	3779

branches/new_menus/src/mame/drivers/galpanic.c

r29505	r29506
545	545	GFXDECODE_END
546	546
547	547
548		static const kaneko_pandora_interface galpanic_pandora_config =
549		{
550		0,  /* gfx_region */
551		0, -16  /* x_offs, y_offs */
552		};
553
554
555	548	static MACHINE_CONFIG_START( galpanic, galpanic_state )
556	549
557	550	/* basic machine hardware */
r29505	r29506
573	566	MCFG_PALETTE_ADD("palette", 1024 + 32768)
574	567	MCFG_PALETTE_INIT_OWNER(galpanic_state,galpanic)
575	568
576		MCFG_KANEKO_PANDORA_ADD("pandora", galpanic_pandora_config)
	569	MCFG_DEVICE_ADD("pandora", KANEKO_PANDORA, 0)
	570	MCFG_KANEKO_PANDORA_OFFSETS(0, -16)
577	571	MCFG_KANEKO_PANDORA_GFXDECODE("gfxdecode")
578	572	MCFG_KANEKO_PANDORA_PALETTE("palette")
579	573
580	574	MCFG_DEVICE_ADD("calc1_mcu", KANEKO_HIT, 0)
581	575	kaneko_hit_device::set_type(*device, 0);
582	576
583
584
585
586	577	MCFG_VIDEO_START_OVERRIDE(galpanic_state,galpanic)
587	578
588	579	/* sound hardware */

branches/new_menus/src/mame/drivers/igspoker.c

r29505	r29506
1732	1732	static const gfx_layout charlayout2 =
1733	1733	{
1734	1734	8, 32,   /* 8*32 characters */
1735		RGN_FRAC(1, 3),
	1735	RGN_FRAC(1, 3*4),
1736	1736	6,      /* 6 bits per pixel */
1737	1737	{ RGN_FRAC(0,3)+8,RGN_FRAC(0,3)+0,
1738	1738	RGN_FRAC(1,3)+8,RGN_FRAC(1,3)+0,

branches/new_menus/src/mame/drivers/namcona1.c

r29505	r29506
293	293
294	294	/***************************************************************/
295	295
296		READ16_MEMBER(namcona1_state::namcona1_vreg_r)
297		{
298		return m_vreg[offset];
299		} /* namcona1_vreg_r */
300
301	296	int namcona1_state::transfer_dword( UINT32 dest, UINT32 source )
302	297	{
303	298	UINT16 data;
r29505	r29506
549	544	AM_RANGE(0xc00000, 0xdfffff) AM_ROM AM_REGION("maincpu", 0x080000)  /* code */
550	545	AM_RANGE(0xe00000, 0xe00fff) AM_DEVREADWRITE8("eeprom", eeprom_parallel_28xx_device, read, write, 0x00ff)
551	546	AM_RANGE(0xe40000, 0xe4000f) AM_READWRITE(custom_key_r, custom_key_w)
552		AM_RANGE(0xefff00, 0xefffff) AM_READWRITE(namcona1_vreg_r, namcona1_vreg_w) AM_SHARE("vreg")
553		AM_RANGE(0xf00000, 0xf01fff) AM_READWRITE(namcona1_paletteram_r, namcona1_paletteram_w) AM_SHARE("paletteram")
554		AM_RANGE(0xf40000, 0xf7ffff) AM_READWRITE(namcona1_gfxram_r, namcona1_gfxram_w)
555		AM_RANGE(0xff0000, 0xffbfff) AM_READWRITE(namcona1_videoram_r, namcona1_videoram_w) AM_SHARE("videoram")
	547	AM_RANGE(0xefff00, 0xefffff) AM_RAM_WRITE(namcona1_vreg_w) AM_SHARE("vreg")
	548	AM_RANGE(0xf00000, 0xf01fff) AM_RAM_WRITE(namcona1_paletteram_w) AM_SHARE("paletteram")
	549	AM_RANGE(0xf40000, 0xf7ffff) AM_READWRITE(namcona1_gfxram_r, namcona1_gfxram_w) AM_SHARE("cgram")
	550	AM_RANGE(0xff0000, 0xffbfff) AM_RAM_WRITE(namcona1_videoram_w) AM_SHARE("videoram")
556	551	AM_RANGE(0xffd000, 0xffdfff) AM_RAM /* unknown */
557	552	AM_RANGE(0xffe000, 0xffefff) AM_RAM AM_SHARE("scroll")      /* scroll registers */
558	553	AM_RANGE(0xfff000, 0xffffff) AM_RAM AM_SHARE("spriteram")           /* spriteram */
r29505	r29506
571	566	AM_RANGE(0xe00000, 0xe00fff) AM_DEVREADWRITE8("eeprom", eeprom_parallel_28xx_device, read, write, 0x00ff)
572	567	/* xday: additional battery-backed ram at 00E024FA? */
573	568	AM_RANGE(0xe40000, 0xe4000f) AM_READWRITE(custom_key_r, custom_key_w)
574		AM_RANGE(0xefff00, 0xefffff) AM_READWRITE(namcona1_vreg_r, namcona1_vreg_w) AM_SHARE("vreg")
575		AM_RANGE(0xf00000, 0xf01fff) AM_READWRITE(namcona1_paletteram_r, namcona1_paletteram_w) AM_SHARE("paletteram")
576		AM_RANGE(0xf40000, 0xf7ffff) AM_READWRITE(namcona1_gfxram_r, namcona1_gfxram_w)
577		AM_RANGE(0xff0000, 0xffbfff) AM_READWRITE(namcona1_videoram_r, namcona1_videoram_w) AM_SHARE("videoram")
	569	AM_RANGE(0xefff00, 0xefffff) AM_RAM_WRITE(namcona1_vreg_w) AM_SHARE("vreg")
	570	AM_RANGE(0xf00000, 0xf01fff) AM_RAM_WRITE(namcona1_paletteram_w) AM_SHARE("paletteram")
	571	AM_RANGE(0xf40000, 0xf7ffff) AM_READWRITE(namcona1_gfxram_r, namcona1_gfxram_w) AM_SHARE("cgram")
	572	AM_RANGE(0xff0000, 0xffbfff) AM_RAM_WRITE(namcona1_videoram_w) AM_SHARE("videoram")
578	573	AM_RANGE(0xffd000, 0xffdfff) AM_RAM /* unknown */
579	574	AM_RANGE(0xffe000, 0xffefff) AM_RAM AM_SHARE("scroll")      /* scroll registers */
580	575	AM_RANGE(0xfff000, 0xffffff) AM_RAM AM_SHARE("spriteram")           /* spriteram */
r29505	r29506
875	870
876	871	/***************************************************************************/
877	872
	873	static const gfx_layout cg_layout_8bpp =
	874	{
	875	8,8,
	876	RGN_FRAC(1,1),
	877	8, /* 8BPP */
	878	{ 0,1,2,3,4,5,6,7 },
	879	{ STEP8(0, 8) },
	880	{ STEP8(0, 8*8) },
	881	8*8*8
	882	};
	883
	884	static const gfx_layout cg_layout_4bpp =
	885	{
	886	8,8,
	887	RGN_FRAC(1,1),
	888	4, /* 4BPP */
	889	{ 4,5,6,7 },
	890	{ STEP8(0, 8) },
	891	{ STEP8(0, 8*8) },
	892	8*8*8
	893	};
	894
	895	static const gfx_layout shape_layout =
	896	{
	897	8,8,
	898	0x1000,
	899	1,
	900	{ 0 },
	901	{ STEP8(0, 1) },
	902	{ STEP8(0, 8) },
	903	8*8
	904	};
	905
	906	static GFXDECODE_START( namcona1 )
	907	GFXDECODE_RAM( "cgram", 0, cg_layout_8bpp, 0, 0x2000/256 )
	908	GFXDECODE_RAM( "cgram", 0, cg_layout_4bpp, 0, 0x2000/16  )
	909	GFXDECODE_RAM(  NULL,   0, shape_layout,   0, 0x2000/2   )
	910	GFXDECODE_END
	911
	912	/***************************************************************************/
	913
878	914	TIMER_DEVICE_CALLBACK_MEMBER(namcona1_state::namcona1_interrupt)
879	915	{
880	916	int scanline = param;
r29505	r29506
948	984
949	985	MCFG_PALETTE_ADD("palette", 0x2000)
950	986	MCFG_PALETTE_ENABLE_SHADOWS()
951		MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
	987	MCFG_GFXDECODE_ADD("gfxdecode", "palette", namcona1)
952	988
953	989	/* sound hardware */
954	990	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")

branches/new_menus/src/mame/drivers/asuka.c

r29505	r29506
320	320	AM_RANGE(0x3b0000, 0x3b0001) AM_READ_PORT("DSWB")
321	321	AM_RANGE(0x3c0000, 0x3c0001) AM_WRITE(watchdog_reset16_w)
322	322	AM_RANGE(0x3d0000, 0x3d0001) AM_READNOP
323		AM_RANGE(0x3e0000, 0x3e0001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
324		AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	323	AM_RANGE(0x3e0000, 0x3e0001) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	324	AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
325	325	AM_RANGE(0x800000, 0x8007ff) AM_READWRITE(bonzeadv_cchip_ram_r, bonzeadv_cchip_ram_w)
326	326	AM_RANGE(0x800802, 0x800803) AM_READWRITE(bonzeadv_cchip_ctrl_r, bonzeadv_cchip_ctrl_w)
327	327	AM_RANGE(0x800c00, 0x800c01) AM_WRITE(bonzeadv_cchip_bank_w)
r29505	r29506
336	336	AM_RANGE(0x1076f0, 0x1076f1) AM_READNOP /* Mofflott init does dummy reads here */
337	337	AM_RANGE(0x200000, 0x20000f) AM_DEVREADWRITE("tc0110pcr", tc0110pcr_device, word_r, step1_word_w)
338	338	AM_RANGE(0x3a0000, 0x3a0003) AM_WRITE(asuka_spritectrl_w)
339		AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
340		AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	339	AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	340	AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
341	341	AM_RANGE(0x400000, 0x40000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
342	342	AM_RANGE(0xc00000, 0xc0ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
343	343	AM_RANGE(0xc10000, 0xc103ff) AM_WRITENOP    /* error in Asuka init code */
r29505	r29506
348	348	static ADDRESS_MAP_START( cadash_map, AS_PROGRAM, 16, asuka_state )
349	349	AM_RANGE(0x000000, 0x07ffff) AM_ROM
350	350	AM_RANGE(0x080000, 0x080003) AM_WRITE(asuka_spritectrl_w)
351		AM_RANGE(0x0c0000, 0x0c0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
352		AM_RANGE(0x0c0002, 0x0c0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	351	AM_RANGE(0x0c0000, 0x0c0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	352	AM_RANGE(0x0c0002, 0x0c0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
353	353	AM_RANGE(0x100000, 0x107fff) AM_RAM
354	354	AM_RANGE(0x800000, 0x800fff) AM_READWRITE(cadash_share_r,cadash_share_w)    /* network ram */
355	355	AM_RANGE(0x900000, 0x90000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
r29505	r29506
366	366	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
367	367	AM_RANGE(0x400000, 0x40000f) AM_DEVREAD8("tc0220ioc", tc0220ioc_device, read, 0x00ff)   /* service mode mirror */
368	368	AM_RANGE(0x4a0000, 0x4a0003) AM_WRITE(asuka_spritectrl_w)
369		AM_RANGE(0x4e0000, 0x4e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
370		AM_RANGE(0x4e0002, 0x4e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	369	AM_RANGE(0x4e0000, 0x4e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	370	AM_RANGE(0x4e0002, 0x4e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
371	371	AM_RANGE(0xc00000, 0xc03fff) AM_DEVREADWRITE("pc090oj", pc090oj_device, word_r, word_w)  /* sprite ram */
372	372	AM_RANGE(0xc00000, 0xc0ffff) AM_DEVWRITE("tc0100scn", tc0100scn_device, word_w)
373	373	AM_RANGE(0xd00000, 0xd0ffff) AM_DEVREADWRITE("tc0100scn", tc0100scn_device, word_r, word_w)    /* tilemaps */
r29505	r29506
382	382	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
383	383	AM_RANGE(0xc000, 0xdfff) AM_RAM
384	384	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
385		AM_RANGE(0xe200, 0xe200) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
386		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	385	AM_RANGE(0xe200, 0xe200) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	386	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
387	387	AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
388	388	AM_RANGE(0xe600, 0xe600) AM_WRITENOP
389	389	AM_RANGE(0xee00, 0xee00) AM_WRITENOP
r29505	r29506
397	397	AM_RANGE(0x8000, 0x8fff) AM_RAM
398	398	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
399	399	//  AM_RANGE(0x9002, 0x9100) AM_READNOP
400		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
401		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	400	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	401	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
402	402	AM_RANGE(0xb000, 0xb000) AM_WRITE(asuka_msm5205_address_w)
403	403	AM_RANGE(0xc000, 0xc000) AM_WRITE(asuka_msm5205_start_w)
404	404	AM_RANGE(0xd000, 0xd000) AM_WRITE(asuka_msm5205_stop_w)
r29505	r29506
410	410	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
411	411	AM_RANGE(0x8000, 0x8fff) AM_RAM
412	412	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
413		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
414		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	413	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	414	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
415	415	ADDRESS_MAP_END
416	416
417	417	/*
r29505	r29506
778	778	MACHINE DRIVERS
779	779	***********************************************************/
780	780
781		static const tc0100scn_interface asuka_tc0100scn_intf =
782		{
783		1, 2,       /* gfxnum, txnum */
784		0, 0,       /* x_offset, y_offset */
785		0, 0,       /* flip_xoff, flip_yoff */
786		0, 0,       /* flip_text_xoff, flip_text_yoff */
787		0, 0
788		};
789
790		static const tc0100scn_interface cadash_tc0100scn_intf =
791		{
792		1, 2,       /* gfxnum, txnum */
793		1, 0,       /* x_offset, y_offset */
794		0, 0,       /* flip_xoff, flip_yoff */
795		0, 0,       /* flip_text_xoff, flip_text_yoff */
796		0, 0
797		};
798
799		static const pc090oj_interface asuka_pc090oj_intf =
800		{
801		0, 0, 8, 1
802		};
803
804		static const pc090oj_interface bonzeadv_pc090oj_intf =
805		{
806		0, 0, 8, 0
807		};
808
809
810
811	781	void asuka_state::machine_start()
812	782	{
813	783	/* configure the banks */
r29505	r29506
849	819	}
850	820	}
851	821
852		static const tc0140syt_interface asuka_tc0140syt_intf =
853		{
854		"maincpu", "audiocpu"
855		};
856
857	822	static MACHINE_CONFIG_START( bonzeadv, asuka_state )
858	823
859	824	/* basic machine hardware */
r29505	r29506
880	845	MCFG_GFXDECODE_ADD("gfxdecode", "palette", asuka)
881	846	MCFG_PALETTE_ADD("palette", 4096)
882	847
883		MCFG_PC090OJ_ADD("pc090oj", bonzeadv_pc090oj_intf)
	848	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
	849	MCFG_PC090OJ_OFFSETS(0, 8)
884	850	MCFG_PC090OJ_GFXDECODE("gfxdecode")
885	851	MCFG_PC090OJ_PALETTE("palette")
886		MCFG_TC0100SCN_ADD("tc0100scn", asuka_tc0100scn_intf)
	852
	853	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	854	MCFG_TC0100SCN_GFX_REGION(1)
	855	MCFG_TC0100SCN_TX_REGION(2)
887	856	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
888	857	MCFG_TC0100SCN_PALETTE("palette")
	858
889	859	MCFG_TC0110PCR_ADD("tc0110pcr")
890	860	MCFG_TC0110PCR_PALETTE("palette")
891	861
r29505	r29506
898	868	MCFG_SOUND_ROUTE(1, "mono", 1.0)
899	869	MCFG_SOUND_ROUTE(2, "mono", 1.0)
900	870
901		MCFG_TC0140SYT_ADD("tc0140syt", asuka_tc0140syt_intf)
	871	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	872	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	873	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
902	874	MACHINE_CONFIG_END
903	875
904	876	static MACHINE_CONFIG_START( asuka, asuka_state )
r29505	r29506
934	906	MCFG_GFXDECODE_ADD("gfxdecode", "palette", asuka)
935	907	MCFG_PALETTE_ADD("palette", 4096)
936	908
937		MCFG_PC090OJ_ADD("pc090oj", asuka_pc090oj_intf)
	909	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
	910	MCFG_PC090OJ_OFFSETS(0, 8)
	911	MCFG_PC090OJ_USEBUFFER(1)
938	912	MCFG_PC090OJ_GFXDECODE("gfxdecode")
939	913	MCFG_PC090OJ_PALETTE("palette")
940		MCFG_TC0100SCN_ADD("tc0100scn", asuka_tc0100scn_intf)
	914
	915	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	916	MCFG_TC0100SCN_GFX_REGION(1)
	917	MCFG_TC0100SCN_TX_REGION(2)
941	918	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
942	919	MCFG_TC0100SCN_PALETTE("palette")
	920
943	921	MCFG_TC0110PCR_ADD("tc0110pcr")
944	922	MCFG_TC0110PCR_PALETTE("palette")
945	923
r29505	r29506
957	935	MCFG_MSM5205_PRESCALER_SELECTOR(MSM5205_S48_4B)      /* 8 kHz */
958	936	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
959	937
960		MCFG_TC0140SYT_ADD("tc0140syt", asuka_tc0140syt_intf)
	938	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	939	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	940	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
961	941	MACHINE_CONFIG_END
962	942
963	943	static MACHINE_CONFIG_START( cadash, asuka_state )
r29505	r29506
997	977	MCFG_GFXDECODE_ADD("gfxdecode", "palette", asuka)
998	978	MCFG_PALETTE_ADD("palette", 4096)
999	979
1000		MCFG_PC090OJ_ADD("pc090oj", asuka_pc090oj_intf)
	980	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
	981	MCFG_PC090OJ_OFFSETS(0, 8)
	982	MCFG_PC090OJ_USEBUFFER(1)
1001	983	MCFG_PC090OJ_GFXDECODE("gfxdecode")
1002	984	MCFG_PC090OJ_PALETTE("palette")
1003		MCFG_TC0100SCN_ADD("tc0100scn", cadash_tc0100scn_intf)
	985
	986	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	987	MCFG_TC0100SCN_GFX_REGION(1)
	988	MCFG_TC0100SCN_TX_REGION(2)
	989	MCFG_TC0100SCN_OFFSETS(1, 0)
1004	990	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
1005	991	MCFG_TC0100SCN_PALETTE("palette")
	992
1006	993	MCFG_TC0110PCR_ADD("tc0110pcr")
1007	994	MCFG_TC0110PCR_PALETTE("palette")
1008	995
r29505	r29506
1015	1002	MCFG_SOUND_ROUTE(0, "mono", 0.50)
1016	1003	MCFG_SOUND_ROUTE(1, "mono", 0.50)
1017	1004
1018		MCFG_TC0140SYT_ADD("tc0140syt", asuka_tc0140syt_intf)
	1005	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	1006	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	1007	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
1019	1008	MACHINE_CONFIG_END
1020	1009
1021	1010	static MACHINE_CONFIG_START( mofflott, asuka_state )
r29505	r29506
1051	1040	MCFG_GFXDECODE_ADD("gfxdecode", "palette", asuka)
1052	1041	MCFG_PALETTE_ADD("palette", 4096)   /* only Mofflott uses full palette space */
1053	1042
1054		MCFG_PC090OJ_ADD("pc090oj", bonzeadv_pc090oj_intf)
	1043	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
	1044	MCFG_PC090OJ_OFFSETS(0, 8)
1055	1045	MCFG_PC090OJ_GFXDECODE("gfxdecode")
1056	1046	MCFG_PC090OJ_PALETTE("palette")
1057		MCFG_TC0100SCN_ADD("tc0100scn", cadash_tc0100scn_intf)
	1047
	1048	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	1049	MCFG_TC0100SCN_GFX_REGION(1)
	1050	MCFG_TC0100SCN_TX_REGION(2)
	1051	MCFG_TC0100SCN_OFFSETS(1, 0)
1058	1052	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
1059	1053	MCFG_TC0100SCN_PALETTE("palette")
	1054
1060	1055	MCFG_TC0110PCR_ADD("tc0110pcr")
1061	1056	MCFG_TC0110PCR_PALETTE("palette")
1062	1057
r29505	r29506
1074	1069	MCFG_MSM5205_PRESCALER_SELECTOR(MSM5205_S48_4B)      /* 8 kHz */
1075	1070	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1076	1071
1077		MCFG_TC0140SYT_ADD("tc0140syt", asuka_tc0140syt_intf)
	1072	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	1073	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	1074	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
1078	1075	MACHINE_CONFIG_END
1079	1076
1080	1077	static MACHINE_CONFIG_START( galmedes, asuka_state )
r29505	r29506
1110	1107	MCFG_GFXDECODE_ADD("gfxdecode", "palette", asuka)
1111	1108	MCFG_PALETTE_ADD("palette", 4096)   /* only Mofflott uses full palette space */
1112	1109
1113		MCFG_PC090OJ_ADD("pc090oj", bonzeadv_pc090oj_intf)
	1110	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
	1111	MCFG_PC090OJ_OFFSETS(0, 8)
1114	1112	MCFG_PC090OJ_GFXDECODE("gfxdecode")
1115	1113	MCFG_PC090OJ_PALETTE("palette")
1116		MCFG_TC0100SCN_ADD("tc0100scn", cadash_tc0100scn_intf)
	1114
	1115	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	1116	MCFG_TC0100SCN_GFX_REGION(1)
	1117	MCFG_TC0100SCN_TX_REGION(2)
	1118	MCFG_TC0100SCN_OFFSETS(1, 0)
1117	1119	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
1118	1120	MCFG_TC0100SCN_PALETTE("palette")
	1121
1119	1122	MCFG_TC0110PCR_ADD("tc0110pcr")
1120	1123	MCFG_TC0110PCR_PALETTE("palette")
1121	1124
r29505	r29506
1128	1131	MCFG_SOUND_ROUTE(0, "mono", 0.50)
1129	1132	MCFG_SOUND_ROUTE(1, "mono", 0.50)
1130	1133
1131		MCFG_TC0140SYT_ADD("tc0140syt", asuka_tc0140syt_intf)
	1134	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	1135	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	1136	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
1132	1137	MACHINE_CONFIG_END
1133	1138
1134	1139	static MACHINE_CONFIG_START( eto, asuka_state )
r29505	r29506
1164	1169	MCFG_GFXDECODE_ADD("gfxdecode", "palette", asuka)
1165	1170	MCFG_PALETTE_ADD("palette", 4096)
1166	1171
1167		MCFG_PC090OJ_ADD("pc090oj", bonzeadv_pc090oj_intf)
	1172	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
	1173	MCFG_PC090OJ_OFFSETS(0, 8)
1168	1174	MCFG_PC090OJ_GFXDECODE("gfxdecode")
1169	1175	MCFG_PC090OJ_PALETTE("palette")
1170		MCFG_TC0100SCN_ADD("tc0100scn", cadash_tc0100scn_intf)
	1176
	1177	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	1178	MCFG_TC0100SCN_GFX_REGION(1)
	1179	MCFG_TC0100SCN_TX_REGION(2)
	1180	MCFG_TC0100SCN_OFFSETS(1, 0)
1171	1181	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
1172	1182	MCFG_TC0100SCN_PALETTE("palette")
	1183
1173	1184	MCFG_TC0110PCR_ADD("tc0110pcr")
1174	1185	MCFG_TC0110PCR_PALETTE("palette")
1175	1186
r29505	r29506
1182	1193	MCFG_SOUND_ROUTE(0, "mono", 0.50)
1183	1194	MCFG_SOUND_ROUTE(1, "mono", 0.50)
1184	1195
1185		MCFG_TC0140SYT_ADD("tc0140syt", asuka_tc0140syt_intf)
	1196	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	1197	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	1198	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
1186	1199	MACHINE_CONFIG_END
1187	1200
1188	1201

branches/new_menus/src/mame/drivers/nmk16.c

r29505	r29506
3626	3626	m_maincpu->set_input_line(2, HOLD_LINE);
3627	3627	}
3628	3628
3629
3630		static const nmk112_interface nmk16_nmk112_intf =
3631		{
3632		"oki1", "oki2", 0
3633		};
3634
3635	3629	static MACHINE_CONFIG_START( tharrier, nmk16_state )
3636	3630
3637	3631	/* basic machine hardware */
r29505	r29506
4345	4339	MCFG_OKIM6295_ADD("oki2", 16000000/4, OKIM6295_PIN7_LOW)
4346	4340	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.20)
4347	4341
4348		MCFG_NMK112_ADD("nmk112", nmk16_nmk112_intf)
	4342	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	4343	MCFG_NMK112_ROM0("oki1")
	4344	MCFG_NMK112_ROM1("oki2")
4349	4345	MACHINE_CONFIG_END
4350	4346
4351	4347	static MACHINE_CONFIG_START( tdragon2, nmk16_state )
r29505	r29506
4390	4386	MCFG_OKIM6295_ADD("oki2", 16000000/4, OKIM6295_PIN7_LOW)
4391	4387	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.08)
4392	4388
4393		MCFG_NMK112_ADD("nmk112", nmk16_nmk112_intf)
	4389	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	4390	MCFG_NMK112_ROM0("oki1")
	4391	MCFG_NMK112_ROM1("oki2")
4394	4392	MACHINE_CONFIG_END
4395	4393
4396	4394	static MACHINE_CONFIG_START( raphero, nmk16_state )
r29505	r29506
4437	4435	MCFG_OKIM6295_ADD("oki2", 16000000/4, OKIM6295_PIN7_LOW)
4438	4436	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.08)
4439	4437
4440		MCFG_NMK112_ADD("nmk112", nmk16_nmk112_intf)
	4438	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	4439	MCFG_NMK112_ROM0("oki1")
	4440	MCFG_NMK112_ROM1("oki2")
4441	4441	MACHINE_CONFIG_END
4442	4442
4443	4443	static MACHINE_CONFIG_START( bjtwin, nmk16_state )
r29505	r29506
4473	4473	MCFG_OKIM6295_ADD("oki2", 16000000/4, OKIM6295_PIN7_LOW) /* verified on pcb */
4474	4474	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.20)
4475	4475
4476		MCFG_NMK112_ADD("nmk112", nmk16_nmk112_intf)
	4476	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	4477	MCFG_NMK112_ROM0("oki1")
	4478	MCFG_NMK112_ROM1("oki2")
4477	4479	MACHINE_CONFIG_END
4478	4480
4479	4481

branches/new_menus/src/mame/drivers/f1gp.c

r29505	r29506
367	367	m_audiocpu->set_input_line(0, state ? ASSERT_LINE : CLEAR_LINE);
368	368	}
369	369
370		static const k053936_interface f1gp_k053936_intf =
371		{
372		1, -58, -2  /* wrap, xoff, yoff */
373		};
374
375		static const k053936_interface f1gp2_k053936_intf =
376		{
377		1, -48, -21 /* wrap, xoff, yoff */
378		};
379
380
381	370	MACHINE_START_MEMBER(f1gp_state,f1gpb)
382	371	{
383	372	save_item(NAME(m_pending_command));
r29505	r29506
452	441
453	442	MCFG_VIDEO_START_OVERRIDE(f1gp_state,f1gp)
454	443
455		MCFG_K053936_ADD("k053936", f1gp_k053936_intf)
	444	MCFG_DEVICE_ADD("k053936", K053936, 0)
	445	MCFG_K053936_WRAP(1)
	446	MCFG_K053936_OFFSETS(-58, -2)
456	447
457	448	/* sound hardware */
458	449	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r29505	r29506
525	516	MCFG_VSYSTEM_SPR_GFXDECODE("gfxdecode")
526	517	MCFG_VSYSTEM_SPR_PALETTE("palette")
527	518
528		MCFG_DEVICE_REMOVE("k053936")
529		MCFG_K053936_ADD("k053936", f1gp2_k053936_intf)
	519	MCFG_DEVICE_MODIFY("k053936")
	520	MCFG_K053936_OFFSETS(-48, -21)
530	521
531	522	MCFG_VIDEO_START_OVERRIDE(f1gp_state,f1gp2)
532	523	MACHINE_CONFIG_END

branches/new_menus/src/mame/drivers/suprslam.c

r29505	r29506
283	283
284	284	/*** MACHINE DRIVER **********************************************************/
285	285
286		static const k053936_interface suprslam_k053936_intf =
287		{
288		1, -45, -21 /* wrap, xoff, yoff */
289		};
290
291	286	void suprslam_state::machine_start()
292	287	{
293	288	save_item(NAME(m_screen_bank));
r29505	r29506
333	328	MCFG_VSYSTEM_SPR_GFXDECODE("gfxdecode")
334	329	MCFG_VSYSTEM_SPR_PALETTE("palette")
335	330
336		MCFG_K053936_ADD("k053936", suprslam_k053936_intf)
	331	MCFG_DEVICE_ADD("k053936", K053936, 0)
	332	MCFG_K053936_WRAP(1)
	333	MCFG_K053936_OFFSETS(-45, -21)
337	334
338	335	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
339	336

branches/new_menus/src/mame/drivers/opwolf.c

r29505	r29506
366	366	AM_RANGE(0x380000, 0x380003) AM_WRITE(opwolf_spritectrl_w)  // usually 0x4, changes when you fire
367	367	AM_RANGE(0x3a0000, 0x3a0003) AM_READ(opwolf_lightgun_r)     /* lightgun, read at $11e0/6 */
368	368	AM_RANGE(0x3c0000, 0x3c0001) AM_WRITENOP                    /* watchdog ?? */
369		AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
370		AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	369	AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	370	AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
371	371	AM_RANGE(0xc00000, 0xc0ffff) AM_DEVREADWRITE("pc080sn", pc080sn_device, word_r, word_w)
372	372	AM_RANGE(0xc10000, 0xc1ffff) AM_WRITEONLY                   /* error in init code (?) */
373	373	AM_RANGE(0xc20000, 0xc20003) AM_DEVWRITE("pc080sn", pc080sn_device, yscroll_word_w)
r29505	r29506
387	387	AM_RANGE(0x380000, 0x380003) AM_WRITE(opwolf_spritectrl_w)  // usually 0x4, changes when you fire
388	388	AM_RANGE(0x3a0000, 0x3a0003) AM_READ(opwolf_lightgun_r)     /* lightgun, read at $11e0/6 */
389	389	AM_RANGE(0x3c0000, 0x3c0001) AM_WRITENOP                    /* watchdog ?? */
390		AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
391		AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	390	AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	391	AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
392	392	AM_RANGE(0xc00000, 0xc0ffff) AM_DEVREADWRITE("pc080sn", pc080sn_device, word_r, word_w)
393	393	AM_RANGE(0xc10000, 0xc1ffff) AM_WRITEONLY                   /* error in init code (?) */
394	394	AM_RANGE(0xc20000, 0xc20003) AM_DEVWRITE("pc080sn", pc080sn_device, yscroll_word_w)
r29505	r29506
536	536	AM_RANGE(0x8000, 0x8fff) AM_RAM
537	537	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_device,read,write)
538	538	AM_RANGE(0x9002, 0x9100) AM_READNOP
539		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
540		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	539	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	540	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
541	541	AM_RANGE(0xb000, 0xb006) AM_WRITE(opwolf_adpcm_b_w)
542	542	AM_RANGE(0xc000, 0xc006) AM_WRITE(opwolf_adpcm_c_w)
543	543	AM_RANGE(0xd000, 0xd000) AM_WRITE(opwolf_adpcm_d_w)
r29505	r29506
680	680	MACHINE DRIVERS
681	681	***********************************************************/
682	682
683		static const pc080sn_interface opwolf_pc080sn_intf =
684		{
685		1,   /* gfxnum */
686		0, 0, 0, 0  /* x_offset, y_offset, y_invert, dblwidth */
687		};
688
689		static const pc090oj_interface opwolf_pc090oj_intf =
690		{
691		0, 0, 0, 0
692		};
693
694		static const tc0140syt_interface opwolf_tc0140syt_intf =
695		{
696		"maincpu", "audiocpu"
697		};
698
699	683	static MACHINE_CONFIG_START( opwolf, opwolf_state )
700	684
701	685	/* basic machine hardware */
r29505	r29506
723	707	MCFG_PALETTE_ADD("palette", 8192)
724	708	MCFG_PALETTE_FORMAT(xxxxRRRRGGGGBBBB)
725	709
726		MCFG_PC080SN_ADD("pc080sn", opwolf_pc080sn_intf)
	710	MCFG_DEVICE_ADD("pc080sn", PC080SN, 0)
	711	MCFG_PC080SN_GFX_REGION(1)
727	712	MCFG_PC080SN_GFXDECODE("gfxdecode")
728	713	MCFG_PC080SN_PALETTE("palette")
729		MCFG_PC090OJ_ADD("pc090oj", opwolf_pc090oj_intf)
	714
	715	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
730	716	MCFG_PC090OJ_GFXDECODE("gfxdecode")
731	717	MCFG_PC090OJ_PALETTE("palette")
732	718
r29505	r29506
751	737	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.60)
752	738	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.60)
753	739
754		MCFG_TC0140SYT_ADD("tc0140syt", opwolf_tc0140syt_intf)
	740	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	741	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	742	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
755	743	MACHINE_CONFIG_END
756	744
757	745
r29505	r29506
785	773	MCFG_PALETTE_ADD("palette", 8192)
786	774	MCFG_PALETTE_FORMAT(xxxxRRRRGGGGBBBB)
787	775
788		MCFG_PC080SN_ADD("pc080sn", opwolf_pc080sn_intf)
	776	MCFG_DEVICE_ADD("pc080sn", PC080SN, 0)
	777	MCFG_PC080SN_GFX_REGION(1)
789	778	MCFG_PC080SN_GFXDECODE("gfxdecode")
790	779	MCFG_PC080SN_PALETTE("palette")
791		MCFG_PC090OJ_ADD("pc090oj", opwolf_pc090oj_intf)
	780
	781	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
792	782	MCFG_PC090OJ_GFXDECODE("gfxdecode")
793	783	MCFG_PC090OJ_PALETTE("palette")
794	784
r29505	r29506
813	803	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.60)
814	804	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.60)
815	805
816		MCFG_TC0140SYT_ADD("tc0140syt", opwolf_tc0140syt_intf)
	806	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	807	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	808	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
817	809	MACHINE_CONFIG_END
818	810
819	811

branches/new_menus/src/mame/drivers/jpmsys5.c

r29505	r29506
646	646
647	647	MCFG_NVRAM_ADD_0FILL("nvram")
648	648
649		MCFG_ROC10937_ADD("vfd",0,RIGHT_TO_LEFT)//for debug ports
	649	MCFG_S16LF01_ADD("vfd",0)//for debug ports
650	650
651	651	MCFG_MACHINE_START_OVERRIDE(jpmsys5_state,jpmsys5v)
652	652	MCFG_MACHINE_RESET_OVERRIDE(jpmsys5_state,jpmsys5v)
r29505	r29506
864	864	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(jpmsys5_state, write_acia_clock))
865	865
866	866	MCFG_NVRAM_ADD_0FILL("nvram")
867		MCFG_ROC10937_ADD("vfd",0,RIGHT_TO_LEFT)
	867	MCFG_S16LF01_ADD("vfd",0)
868	868
869	869	MCFG_MACHINE_START_OVERRIDE(jpmsys5_state,jpmsys5)
870	870	MCFG_MACHINE_RESET_OVERRIDE(jpmsys5_state,jpmsys5)
r29505	r29506
911	911	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(jpmsys5_state, write_acia_clock))
912	912
913	913	MCFG_NVRAM_ADD_0FILL("nvram")
914		MCFG_ROC10937_ADD("vfd",0,RIGHT_TO_LEFT)
	914	MCFG_S16LF01_ADD("vfd",0)
915	915
916	916	MCFG_MACHINE_START_OVERRIDE(jpmsys5_state,jpmsys5)
917	917	MCFG_MACHINE_RESET_OVERRIDE(jpmsys5_state,jpmsys5)

branches/new_menus/src/mame/drivers/lemmings.c

r29505	r29506
256	256
257	257
258	258	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
259		decospr_device::set_gfx_region(*device, 1);
	259	MCFG_DECO_SPRITE_GFX_REGION(1)
260	260	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
261	261	MCFG_DECO_SPRITE_PALETTE("palette")
262	262
263	263	MCFG_DEVICE_ADD("spritegen2", DECO_SPRITE, 0)
264		decospr_device::set_gfx_region(*device, 0);
	264	MCFG_DECO_SPRITE_GFX_REGION(0)
265	265	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
266	266	MCFG_DECO_SPRITE_PALETTE("palette")
267	267

branches/new_menus/src/mame/drivers/nmg5.c

r29505	r29506
1025	1025	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
1026	1026
1027	1027	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
1028		decospr_device::set_gfx_region(*device, 1);
1029		decospr_device::set_is_bootleg(*device, true);
1030		decospr_device::set_flipallx(*device, 1);
1031		decospr_device::set_offsets(*device, 0,8);
	1028	MCFG_DECO_SPRITE_GFX_REGION(1)
	1029	MCFG_DECO_SPRITE_ISBOOTLEG(true)
	1030	MCFG_DECO_SPRITE_FLIPALLX(1)
	1031	MCFG_DECO_SPRITE_OFFSETS(0, 8)
1032	1032	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
1033	1033	MCFG_DECO_SPRITE_PALETTE("palette")
1034	1034

branches/new_menus/src/mame/drivers/globalfr.c

r29505	r29506
7	7	Motherboard contains very few major components
8	8
9	9	Missing sound roms? (or is sound data in the program roms?)
10		NOTE: VFD is guessed as 16 segment, need to know more
	10	NOTE: VFD is guessed as Samsung 16 segment, need to know more
11	11	*******************************************************************************/
12	12
13	13
r29505	r29506
28	28	{ }
29	29
30	30	required_device<cpu_device> m_maincpu;
31		optional_device<roc10937_t> m_vfd;
	31	optional_device<s16lf01_t> m_vfd;
32	32
33	33	// serial vfd
34	34	int m_alpha_clock;
r29505	r29506
77	77	/* basic machine hardware */
78	78	MCFG_CPU_ADD("maincpu", M37710, 4000000)
79	79	MCFG_CPU_PROGRAM_MAP(globalfr_map)
80		MCFG_ROC10937_ADD("vfd",0,RIGHT_TO_LEFT)
	80	MCFG_S16LF01_ADD("vfd",0)
81	81	MCFG_DEFAULT_LAYOUT(layout_globalfr)
82	82	MACHINE_CONFIG_END
83	83

branches/new_menus/src/mame/drivers/funkyjet.c

r29505	r29506
347	347	MCFG_DECO16IC_PALETTE("palette")
348	348
349	349	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
350		decospr_device::set_gfx_region(*device, 2);
	350	MCFG_DECO_SPRITE_GFX_REGION(2)
351	351	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
352	352	MCFG_DECO_SPRITE_PALETTE("palette")
353	353

branches/new_menus/src/mame/drivers/hvyunit.c

r29505	r29506
625	625	m_mastercpu->set_input_line_and_vector(0, HOLD_LINE, 0xff);
626	626	}
627	627
628		static const kaneko_pandora_interface hvyunit_pandora_config =
629		{
630		0,          /* gfx_region */
631		0, 0        /* x_offs, y_offs */
632		};
633
634
635	628	/*************************************
636	629	*
637	630	*  Machine driver
r29505	r29506
660	653
661	654	MCFG_QUANTUM_TIME(attotime::from_hz(6000))
662	655
663
664	656	MCFG_SCREEN_ADD("screen", RASTER)
665	657	MCFG_SCREEN_REFRESH_RATE(58)
666	658	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
r29505	r29506
674	666	MCFG_PALETTE_ADD("palette", 0x800)
675	667	MCFG_PALETTE_FORMAT(xxxxRRRRGGGGBBBB)
676	668
677		MCFG_KANEKO_PANDORA_ADD("pandora", hvyunit_pandora_config)
	669	MCFG_DEVICE_ADD("pandora", KANEKO_PANDORA, 0)
678	670	MCFG_KANEKO_PANDORA_GFXDECODE("gfxdecode")
679	671	MCFG_KANEKO_PANDORA_PALETTE("palette")
680	672

branches/new_menus/src/mame/drivers/mlanding.c

r29505	r29506
742	742	AM_RANGE(0x2b0006, 0x2b0007) AM_READ(analog2_lsb_r)
743	743	AM_RANGE(0x2c0000, 0x2c0001) AM_READ(analog3_msb_r)
744	744	AM_RANGE(0x2c0002, 0x2c0003) AM_READ(analog3_lsb_r)
745		AM_RANGE(0x2d0000, 0x2d0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
746		AM_RANGE(0x2d0002, 0x2d0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	745	AM_RANGE(0x2d0000, 0x2d0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	746	AM_RANGE(0x2d0002, 0x2d0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
747	747	ADDRESS_MAP_END
748	748
749	749
r29505	r29506
797	797	AM_RANGE(0x0000, 0x7fff) AM_ROM
798	798	AM_RANGE(0x8000, 0x8fff) AM_RAM
799	799	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
800		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
801		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	800	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	801	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
802	802	AM_RANGE(0xb000, 0xb000) AM_WRITE(msm5205_2_start_w)
803	803	AM_RANGE(0xc000, 0xc000) AM_WRITE(msm5205_2_stop_w)
804	804	AM_RANGE(0xd000, 0xd000) AM_WRITE(msm5205_1_start_w)
r29505	r29506
925	925	*
926	926	*************************************/
927	927
928		static const tc0140syt_interface mlanding_tc0140syt_intf =
929		{
930		"maincpu", "audiocpu"
931		};
932
933
934	928	static Z80CTC_INTERFACE( ctc_intf )
935	929	{
936	930	DEVCB_NULL, // Interrupt handler
r29505	r29506
970	964	MCFG_CPU_IO_MAP(dsp_map_io)
971	965
972	966	MCFG_Z80CTC_ADD("ctc", 4000000, ctc_intf)
973		MCFG_TC0140SYT_ADD("tc0140syt", mlanding_tc0140syt_intf)
974	967
	968	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	969	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	970	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
	971
975	972	MCFG_QUANTUM_TIME(attotime::from_hz(600))
976	973
977	974	/* video hardware */

branches/new_menus/src/mame/drivers/dreambal.c

r29505	r29506
50	50	virtual void machine_start();
51	51	virtual void machine_reset();
52	52	UINT32 screen_update_dreambal(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
53		int bank_callback(int bank);
	53	DECO16IC_BANK_CB_MEMBER(bank_callback);
54	54
55	55	DECLARE_READ16_MEMBER( dreambal_protection_region_0_104_r );
56	56	DECLARE_WRITE16_MEMBER( dreambal_protection_region_0_104_w );
r29505	r29506
286	286	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
287	287	INPUT_PORTS_END
288	288
289		int dreambal_state::bank_callback( int bank )
	289	DECO16IC_BANK_CB_MEMBER(dreambal_state::bank_callback)
290	290	{
291	291	return ((bank >> 4) & 0x7) * 0x1000;
292	292	}

branches/new_menus/src/mame/drivers/galastrm.c

r29505	r29506
277	277
278	278	/***************************************************************************/
279	279
280		static const tc0100scn_interface galastrm_tc0100scn_intf =
281		{
282		0, 2,       /* gfxnum, txnum */
283		-48, -56,       /* x_offset, y_offset */
284		0, 0,       /* flip_xoff, flip_yoff */
285		0, 0,       /* flip_text_xoff, flip_text_yoff */
286		0, 0
287		};
288
289		static const tc0480scp_interface galastrm_tc0480scp_intf =
290		{
291		1, 3,       /* gfxnum, txnum */
292		0,      /* pixels */
293		-40, -3,        /* x_offset, y_offset */
294		0, 0,       /* text_xoff, text_yoff */
295		0, 0,       /* flip_xoff, flip_yoff */
296		0       /* col_base */
297		};
298
299	280	static MACHINE_CONFIG_START( galastrm, galastrm_state )
300	281	/* basic machine hardware */
301	282	MCFG_CPU_ADD("maincpu", M68EC020, 16000000) /* 16 MHz */
r29505	r29506
316	297	MCFG_GFXDECODE_ADD("gfxdecode", "palette", galastrm)
317	298	MCFG_PALETTE_ADD("palette", 4096)
318	299
319
320		MCFG_TC0100SCN_ADD("tc0100scn", galastrm_tc0100scn_intf)
	300	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	301	MCFG_TC0100SCN_GFX_REGION(0)
	302	MCFG_TC0100SCN_TX_REGION(2)
	303	MCFG_TC0100SCN_OFFSETS(-48, -56)
321	304	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
322	305	MCFG_TC0100SCN_PALETTE("palette")
323		MCFG_TC0480SCP_ADD("tc0480scp", galastrm_tc0480scp_intf)
	306
	307	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	308	MCFG_TC0480SCP_GFX_REGION(1)
	309	MCFG_TC0480SCP_TX_REGION(3)
	310	MCFG_TC0480SCP_OFFSETS(-40, -3)
324	311	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
325	312	MCFG_TC0480SCP_PALETTE("palette")
326	313

branches/new_menus/src/mame/drivers/mirage.c

r29505	r29506
80	80	virtual void machine_reset();
81	81	virtual void video_start();
82	82	UINT32 screen_update_mirage(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
83		int bank_callback(int bank);
	83	DECO16IC_BANK_CB_MEMBER(bank_callback);
84	84	};
85	85
86	86	void miragemi_state::video_start()
r29505	r29506
287	287	GFXDECODE_END
288	288
289	289
290		int miragemi_state::bank_callback( int bank )
	290	DECO16IC_BANK_CB_MEMBER(miragemi_state::bank_callback)
291	291	{
292	292	return ((bank >> 4) & 0x7) * 0x1000;
293	293	}
r29505	r29506
343	343	MCFG_DECO16IC_PALETTE("palette")
344	344
345	345	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
346		decospr_device::set_gfx_region(*device, 2);
	346	MCFG_DECO_SPRITE_GFX_REGION(2)
347	347	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
348	348	MCFG_DECO_SPRITE_PALETTE("palette")
349	349

branches/new_menus/src/mame/drivers/dietgo.c

r29505	r29506
189	189	GFXDECODE_ENTRY( "gfx2", 0, spritelayout,      512, 16 )    /* Sprites (16x16) */
190	190	GFXDECODE_END
191	191
192		int dietgo_state::bank_callback(int bank)
	192	DECO16IC_BANK_CB_MEMBER(dietgo_state::bank_callback)
193	193	{
194	194	return ((bank >> 4) & 0x7) * 0x1000;
195	195	}
r29505	r29506
241	241	MCFG_DECO16IC_PALETTE("palette")
242	242
243	243	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
244		decospr_device::set_gfx_region(*device, 2);
	244	MCFG_DECO_SPRITE_GFX_REGION(2)
245	245	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
246	246	MCFG_DECO_SPRITE_PALETTE("palette")
247	247

branches/new_menus/src/mame/drivers/wgp.c

r29505	r29506
610	610	WRITE16_MEMBER(wgp_state::wgp_sound_w)
611	611	{
612	612	if (offset == 0)
613		m_tc0140syt->tc0140syt_port_w(space, 0, data & 0xff);
	613	m_tc0140syt->master_port_w(space, 0, data & 0xff);
614	614	else if (offset == 1)
615		m_tc0140syt->tc0140syt_comm_w(space, 0, data & 0xff);
	615	m_tc0140syt->master_comm_w(space, 0, data & 0xff);
616	616	}
617	617
618	618	READ16_MEMBER(wgp_state::wgp_sound_r)
619	619	{
620	620	if (offset == 1)
621		return ((m_tc0140syt->tc0140syt_comm_r(space, 0) & 0xff));
	621	return ((m_tc0140syt->master_comm_r(space, 0) & 0xff));
622	622	else
623	623	return 0;
624	624	}
r29505	r29506
667	667	AM_RANGE(0x0000, 0x7fff) AM_ROM
668	668	AM_RANGE(0xc000, 0xdfff) AM_RAM
669	669	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
670		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
671		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	670	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	671	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
672	672	AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
673	673	AM_RANGE(0xea00, 0xea00) AM_READNOP
674	674	AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
r29505	r29506
933	933	machine().save().register_postload(save_prepost_delegate(FUNC(wgp_state::wgp_postload), this));
934	934	}
935	935
936		static const tc0100scn_interface wgp_tc0100scn_intf =
937		{
938		1, 3,       /* gfxnum, txnum */
939		0, 0,       /* x_offset, y_offset */
940		0, 0,       /* flip_xoff, flip_yoff */
941		0, 0,       /* flip_text_xoff, flip_text_yoff */
942		0, 0
943		};
944
945		static const tc0100scn_interface wgp2_tc0100scn_intf =
946		{
947		1, 3,       /* gfxnum, txnum */
948		4, 2,       /* x_offset, y_offset */
949		0, 0,       /* flip_xoff, flip_yoff */
950		0, 0,       /* flip_text_xoff, flip_text_yoff */
951		0, 0
952		};
953
954		static const tc0140syt_interface wgp_tc0140syt_intf =
955		{
956		"sub", "audiocpu"
957		};
958
959	936	static MACHINE_CONFIG_START( wgp, wgp_state )
960	937
961	938	/* basic machine hardware */
r29505	r29506
993	970	MCFG_PALETTE_ADD("palette", 4096)
994	971	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
995	972
996		MCFG_TC0100SCN_ADD("tc0100scn", wgp_tc0100scn_intf)
	973	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	974	MCFG_TC0100SCN_GFX_REGION(1)
	975	MCFG_TC0100SCN_TX_REGION(3)
997	976	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
998	977	MCFG_TC0100SCN_PALETTE("palette")
999	978
r29505	r29506
1007	986	MCFG_SOUND_ROUTE(1, "lspeaker",  1.0)
1008	987	MCFG_SOUND_ROUTE(2, "rspeaker", 1.0)
1009	988
1010		MCFG_TC0140SYT_ADD("tc0140syt", wgp_tc0140syt_intf)
	989	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	990	MCFG_TC0140SYT_MASTER_CPU("sub")
	991	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
1011	992	MACHINE_CONFIG_END
1012	993
1013	994
r29505	r29506
1017	998	/* video hardware */
1018	999	MCFG_VIDEO_START_OVERRIDE(wgp_state,wgp2)
1019	1000
1020		MCFG_DEVICE_REMOVE("tc0100scn")
1021		MCFG_TC0100SCN_ADD("tc0100scn", wgp2_tc0100scn_intf)
	1001	MCFG_DEVICE_MODIFY("tc0100scn")
	1002	MCFG_TC0100SCN_OFFSETS(4, 2)
1022	1003	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
1023	1004	MCFG_TC0100SCN_PALETTE("palette")
1024	1005	MACHINE_CONFIG_END

branches/new_menus/src/mame/drivers/taito_o.c

r29505	r29506
230	230	DEVCB_NULL, DEVCB_NULL,
231	231	};
232	232
233		static const tc0080vco_interface parentj_intf =
234		{
235		0, 1,   /* gfxnum, txnum */
236		1, 1, -2,
237		0
238		};
239
240	233	void taitoo_state::machine_start()
241	234	{
242	235	}
r29505	r29506
260	253	MCFG_PALETTE_ADD("palette", 33*16)
261	254	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
262	255
263		MCFG_TC0080VCO_ADD("tc0080vco", parentj_intf)
	256	MCFG_DEVICE_ADD("tc0080vco", TC0080VCO, 0)
	257	MCFG_TC0080VCO_GFX_REGION(0)
	258	MCFG_TC0080VCO_TX_REGION(1)
	259	MCFG_TC0080VCO_OFFSETS(1, 1)
	260	MCFG_TC0080VCO_BGFLIP_OFFS(-2)
264	261	MCFG_TC0080VCO_GFXDECODE("gfxdecode")
265	262	MCFG_TC0080VCO_PALETTE("palette")
266	263

branches/new_menus/src/mame/drivers/plygonet.c

r29505	r29506
643	643	m_sound_intck = state;
644	644	}
645	645
646
647		static const k053936_interface polygonet_k053936_intf =
648		{
649		0, 0, 0 /* wrap, xoff, yoff */
650		};
651
652	646	static MACHINE_CONFIG_START( plygonet, polygonet_state )
653	647
654	648	MCFG_CPU_ADD("maincpu", M68EC020, XTAL_32MHz/2)
r29505	r29506
679	673
680	674	MCFG_PALETTE_ADD("palette", 32768)
681	675
682		MCFG_K053936_ADD("k053936", polygonet_k053936_intf)
	676	MCFG_DEVICE_ADD("k053936", K053936, 0)
683	677
684	678	/* sound hardware */
685	679	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")

branches/new_menus/src/mame/drivers/warriorb.c

r29505	r29506
173	173	WRITE16_MEMBER(warriorb_state::warriorb_sound_w)
174	174	{
175	175	if (offset == 0)
176		m_tc0140syt->tc0140syt_port_w(space, 0, data & 0xff);
	176	m_tc0140syt->master_port_w(space, 0, data & 0xff);
177	177	else if (offset == 1)
178		m_tc0140syt->tc0140syt_comm_w(space, 0, data & 0xff);
	178	m_tc0140syt->master_comm_w(space, 0, data & 0xff);
179	179	}
180	180
181	181	READ16_MEMBER(warriorb_state::warriorb_sound_r)
182	182	{
183	183	if (offset == 1)
184		return ((m_tc0140syt->tc0140syt_comm_r(space, 0) & 0xff));
	184	return ((m_tc0140syt->master_comm_r(space, 0) & 0xff));
185	185	else
186	186	return 0;
187	187	}
r29505	r29506
254	254	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank10")
255	255	AM_RANGE(0xc000, 0xdfff) AM_RAM
256	256	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
257		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
258		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	257	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	258	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
259	259	AM_RANGE(0xe400, 0xe403) AM_WRITE(warriorb_pancontrol) /* pan */
260	260	AM_RANGE(0xea00, 0xea00) AM_READNOP
261	261	AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
r29505	r29506
423	423	MACHINE DRIVERS
424	424	***********************************************************/
425	425
426		static const tc0100scn_interface darius2d_tc0100scn_intf_l =
427		{
428		1, 3,       /* gfxnum, txnum */
429		4, 0,       /* x_offset, y_offset */
430		0, 0,       /* flip_xoff, flip_yoff */
431		0, 0,       /* flip_text_xoff, flip_text_yoff */
432		0, 0
433		};
434
435		static const tc0100scn_interface darius2d_tc0100scn_intf_r =
436		{
437		2, 3,       /* gfxnum, txnum */
438		4, 0,       /* x_offset, y_offset */
439		0, 0,       /* flip_xoff, flip_yoff */
440		0, 0,       /* flip_text_xoff, flip_text_yoff */
441		0, 1
442		};
443
444		static const tc0100scn_interface warriorb_tc0100scn_intf_l =
445		{
446		1, 3,       /* gfxnum, txnum */
447		4, 0,       /* x_offset, y_offset */
448		0, 0,       /* flip_xoff, flip_yoff */
449		0, 0,       /* flip_text_xoff, flip_text_yoff */
450		0, 0
451		};
452
453		static const tc0100scn_interface warriorb_tc0100scn_intf_r =
454		{
455		2, 3,       /* gfxnum, txnum */
456		4, 0,       /* x_offset, y_offset */
457		0, 0,       /* flip_xoff, flip_yoff */
458		0, 0,       /* flip_text_xoff, flip_text_yoff */
459		1, 1
460		};
461
462
463		static const tc0140syt_interface warriorb_tc0140syt_intf =
464		{
465		"maincpu", "audiocpu"
466		};
467
468
469	426	void warriorb_state::machine_start()
470	427	{
471	428	membank("bank10")->configure_entries(0, 8, memregion("audiocpu")->base() + 0xc000, 0x4000);
r29505	r29506
515	472	MCFG_SCREEN_UPDATE_DRIVER(warriorb_state, screen_update_warriorb_left)
516	473	MCFG_SCREEN_PALETTE("palette")
517	474
	475	MCFG_DEVICE_ADD("tc0100scn_1", TC0100SCN, 0)
	476	MCFG_TC0100SCN_GFX_REGION(1)
	477	MCFG_TC0100SCN_TX_REGION(3)
	478	MCFG_TC0100SCN_OFFSETS(4, 0)
	479	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
	480	MCFG_TC0100SCN_PALETTE("palette")
	481
	482	MCFG_TC0110PCR_ADD("tc0110pcr_1")
	483	MCFG_TC0110PCR_PALETTE("palette")
	484
518	485	MCFG_SCREEN_ADD("rscreen", RASTER)
519	486	MCFG_SCREEN_REFRESH_RATE(60)
520	487	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
r29505	r29506
523	490	MCFG_SCREEN_UPDATE_DRIVER(warriorb_state, screen_update_warriorb_right)
524	491	MCFG_SCREEN_PALETTE("palette2")
525	492
526		MCFG_TC0100SCN_ADD("tc0100scn_1", darius2d_tc0100scn_intf_l)
	493	MCFG_DEVICE_ADD("tc0100scn_2", TC0100SCN, 0)
	494	MCFG_TC0100SCN_GFX_REGION(2)
	495	MCFG_TC0100SCN_TX_REGION(3)
	496	MCFG_TC0100SCN_OFFSETS(4, 0)
	497	MCFG_TC0100SCN_MULTISCR_HACK(1)
527	498	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
528		MCFG_TC0100SCN_PALETTE("palette")
529
530		MCFG_TC0100SCN_ADD("tc0100scn_2", darius2d_tc0100scn_intf_r)
531		MCFG_TC0100SCN_GFXDECODE("gfxdecode")
532	499	MCFG_TC0100SCN_PALETTE("palette2")
533	500
534		MCFG_TC0110PCR_ADD("tc0110pcr_1")
535		MCFG_TC0110PCR_PALETTE("palette")
536	501	MCFG_TC0110PCR_ADD("tc0110pcr_2")
537	502	MCFG_TC0110PCR_PALETTE("palette2")
538	503
r29505	r29506
557	522	MCFG_FILTER_VOLUME_ADD("2610.2.r", 0)
558	523	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
559	524
560		MCFG_TC0140SYT_ADD("tc0140syt", warriorb_tc0140syt_intf)
	525	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	526	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	527	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
561	528	MACHINE_CONFIG_END
562	529
563	530
r29505	r29506
593	560	MCFG_SCREEN_UPDATE_DRIVER(warriorb_state, screen_update_warriorb_left)
594	561	MCFG_SCREEN_PALETTE("palette")
595	562
	563	MCFG_DEVICE_ADD("tc0100scn_1", TC0100SCN, 0)
	564	MCFG_TC0100SCN_GFX_REGION(1)
	565	MCFG_TC0100SCN_TX_REGION(3)
	566	MCFG_TC0100SCN_OFFSETS(4, 0)
	567	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
	568	MCFG_TC0100SCN_PALETTE("palette")
	569
	570	MCFG_TC0110PCR_ADD("tc0110pcr_1")
	571	MCFG_TC0110PCR_PALETTE("palette")
	572
596	573	MCFG_SCREEN_ADD("rscreen", RASTER)
597	574	MCFG_SCREEN_REFRESH_RATE(60)
598	575	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
r29505	r29506
601	578	MCFG_SCREEN_UPDATE_DRIVER(warriorb_state, screen_update_warriorb_right)
602	579	MCFG_SCREEN_PALETTE("palette2")
603	580
604		MCFG_TC0100SCN_ADD("tc0100scn_1", warriorb_tc0100scn_intf_l)
	581	MCFG_DEVICE_ADD("tc0100scn_2", TC0100SCN, 0)
	582	MCFG_TC0100SCN_GFX_REGION(2)
	583	MCFG_TC0100SCN_TX_REGION(3)
	584	MCFG_TC0100SCN_OFFSETS(4, 0)
	585	MCFG_TC0100SCN_MULTISCR_XOFFS(1)
	586	MCFG_TC0100SCN_MULTISCR_HACK(1)
605	587	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
606		MCFG_TC0100SCN_PALETTE("palette")
607
608		MCFG_TC0100SCN_ADD("tc0100scn_2", warriorb_tc0100scn_intf_r)
609		MCFG_TC0100SCN_GFXDECODE("gfxdecode")
610	588	MCFG_TC0100SCN_PALETTE("palette2")
611	589
612		MCFG_TC0110PCR_ADD("tc0110pcr_1")
613		MCFG_TC0110PCR_PALETTE("palette")
614	590	MCFG_TC0110PCR_ADD("tc0110pcr_2")
615	591	MCFG_TC0110PCR_PALETTE("palette2")
616	592
r29505	r29506
635	611	MCFG_FILTER_VOLUME_ADD("2610.2.r", 0)
636	612	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
637	613
638		MCFG_TC0140SYT_ADD("tc0140syt", warriorb_tc0140syt_intf)
	614	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	615	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	616	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
639	617	MACHINE_CONFIG_END
640	618
641	619

branches/new_menus/src/mame/drivers/zn.c

r29505	r29506
1113	1113	static ADDRESS_MAP_START(coh1000ta_map, AS_PROGRAM, 32, zn_state)
1114	1114	AM_RANGE(0x1f000000, 0x1f7fffff) AM_ROMBANK("bankedroms")
1115	1115	AM_RANGE(0x1fb40000, 0x1fb40003) AM_WRITE8(bank_coh1000t_w, 0x000000ff)
1116		AM_RANGE(0x1fb80000, 0x1fb80003) AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x000000ff)
1117		AM_RANGE(0x1fb80000, 0x1fb80003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff0000)
	1116	AM_RANGE(0x1fb80000, 0x1fb80003) AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x000000ff)
	1117	AM_RANGE(0x1fb80000, 0x1fb80003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff0000)
1118	1118
1119	1119	AM_IMPORT_FROM(zn_map)
1120	1120	ADDRESS_MAP_END
r29505	r29506
1129	1129	AM_RANGE(0x0000, 0x7fff) AM_ROM
1130	1130	AM_RANGE(0xc000, 0xdfff) AM_RAM
1131	1131	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
1132		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
1133		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	1132	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	1133	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
1134	1134	AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
1135	1135	AM_RANGE(0xee00, 0xee00) AM_NOP /* ? */
1136	1136	AM_RANGE(0xf000, 0xf000) AM_WRITENOP /* ? */
r29505	r29506
1143	1143	m_audiocpu->set_input_line(0, state ? ASSERT_LINE : CLEAR_LINE);
1144	1144	}
1145	1145
1146		static const tc0140syt_interface coh1000ta_tc0140syt_intf =
1147		{
1148		"maincpu", "audiocpu"
1149		};
1150
1151	1146	static MACHINE_CONFIG_DERIVED( coh1000ta, zn1_1mb_vram )
1152	1147	MCFG_CPU_MODIFY("maincpu")
1153	1148	MCFG_CPU_PROGRAM_MAP(coh1000ta_map)
r29505	r29506
1165	1160
1166	1161	MCFG_MB3773_ADD("mb3773")
1167	1162
1168		MCFG_TC0140SYT_ADD("tc0140syt", coh1000ta_tc0140syt_intf)
	1163	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	1164	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	1165	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
1169	1166	MACHINE_CONFIG_END
1170	1167
1171	1168	WRITE8_MEMBER(zn_state::fx1b_fram_w)

branches/new_menus/src/mame/drivers/cave.c

r29505	r29506
2067	2067	Donpachi
2068	2068	***************************************************************************/
2069	2069
2070		static const nmk112_interface donpachi_nmk112_intf =
2071		{
2072		"oki1", "oki2", 1 << 0  // chip #0 (music) is not paged
2073		};
2074
2075	2070	static MACHINE_CONFIG_START( donpachi, cave_state )
2076	2071
2077	2072	/* basic machine hardware */
r29505	r29506
2110	2105	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
2111	2106	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
2112	2107
2113		MCFG_NMK112_ADD("nmk112", donpachi_nmk112_intf)
	2108	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	2109	MCFG_NMK112_ROM0("oki1")
	2110	MCFG_NMK112_ROM1("oki2")
	2111	MCFG_NMK112_DISABLE_PAGEMASK(1 << 0)   // chip #0 (music) is not paged
2114	2112	MACHINE_CONFIG_END
2115	2113
2116	2114
r29505	r29506
2578	2576
2579	2577	/*  X1 = 12 MHz, X2 = 28 MHz, X3 = 16 MHz. OKI: / 165 mode A ; / 132 mode B */
2580	2578
2581		static const nmk112_interface pwrinst2_nmk112_intf =
2582		{
2583		"oki1", "oki2", 0
2584		};
2585
2586	2579	static MACHINE_CONFIG_START( pwrinst2, cave_state )
2587	2580
2588	2581	/* basic machine hardware */
r29505	r29506
2637	2630	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.00)
2638	2631	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.00)
2639	2632
2640		MCFG_NMK112_ADD("nmk112", pwrinst2_nmk112_intf)
	2633	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	2634	MCFG_NMK112_ROM0("oki1")
	2635	MCFG_NMK112_ROM1("oki2")
2641	2636	MACHINE_CONFIG_END
2642	2637
2643	2638

branches/new_menus/src/mame/drivers/rastan.c

r29505	r29506
212	212	AM_RANGE(0x390008, 0x390009) AM_READ_PORT("DSWA")
213	213	AM_RANGE(0x39000a, 0x39000b) AM_READ_PORT("DSWB")
214	214	AM_RANGE(0x3c0000, 0x3c0001) AM_WRITE(watchdog_reset16_w)
215		AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
216		AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
	215	AM_RANGE(0x3e0000, 0x3e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0x00ff)
	216	AM_RANGE(0x3e0002, 0x3e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0x00ff)
217	217	AM_RANGE(0xc00000, 0xc0ffff) AM_DEVREADWRITE("pc080sn", pc080sn_device, word_r, word_w)
218	218	AM_RANGE(0xc20000, 0xc20003) AM_DEVWRITE("pc080sn", pc080sn_device, yscroll_word_w)
219	219	AM_RANGE(0xc40000, 0xc40003) AM_DEVWRITE("pc080sn", pc080sn_device, xscroll_word_w)
r29505	r29506
227	227	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
228	228	AM_RANGE(0x8000, 0x8fff) AM_RAM
229	229	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
230		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
231		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	230	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	231	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
232	232	AM_RANGE(0xb000, 0xb000) AM_WRITE(rastan_msm5205_address_w)
233	233	AM_RANGE(0xc000, 0xc000) AM_WRITE(rastan_msm5205_start_w)
234	234	AM_RANGE(0xd000, 0xd000) AM_WRITE(rastan_msm5205_stop_w)
r29505	r29506
356	356	}
357	357
358	358
359		static const pc080sn_interface rastan_pc080sn_intf =
360		{
361		0,   /* gfxnum */
362		0, 0, 0, 0  /* x_offset, y_offset, y_invert, dblwidth */
363		};
364
365		static const pc090oj_interface rastan_pc090oj_intf =
366		{
367		1, 0, 0, 0
368		};
369
370		static const tc0140syt_interface rastan_tc0140syt_intf =
371		{
372		"maincpu", "audiocpu"
373		};
374
375	359	static MACHINE_CONFIG_START( rastan, rastan_state )
376	360
377	361	/* basic machine hardware */
r29505	r29506
398	382	MCFG_PALETTE_ADD("palette", 8192)
399	383	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
400	384
401		MCFG_PC080SN_ADD("pc080sn", rastan_pc080sn_intf)
	385	MCFG_DEVICE_ADD("pc080sn", PC080SN, 0)
402	386	MCFG_PC080SN_GFXDECODE("gfxdecode")
403	387	MCFG_PC080SN_PALETTE("palette")
404		MCFG_PC090OJ_ADD("pc090oj", rastan_pc090oj_intf)
	388
	389	MCFG_DEVICE_ADD("pc090oj", PC090OJ, 0)
	390	MCFG_PC090OJ_GFX_REGION(1)
405	391	MCFG_PC090OJ_GFXDECODE("gfxdecode")
406	392	MCFG_PC090OJ_PALETTE("palette")
407	393
r29505	r29506
419	405	MCFG_MSM5205_PRESCALER_SELECTOR(MSM5205_S48_4B)      /* 8 kHz */
420	406	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.60)
421	407
422		MCFG_TC0140SYT_ADD("tc0140syt", rastan_tc0140syt_intf)
	408	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	409	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	410	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
423	411	MACHINE_CONFIG_END
424	412
425	413

branches/new_menus/src/mame/drivers/othunder.c

r29505	r29506
391	391	WRITE16_MEMBER(othunder_state::othunder_sound_w)
392	392	{
393	393	if (offset == 0)
394		m_tc0140syt->tc0140syt_port_w(space, 0, data & 0xff);
	394	m_tc0140syt->master_port_w(space, 0, data & 0xff);
395	395	else if (offset == 1)
396		m_tc0140syt->tc0140syt_comm_w(space, 0, data & 0xff);
	396	m_tc0140syt->master_comm_w(space, 0, data & 0xff);
397	397	}
398	398
399	399	READ16_MEMBER(othunder_state::othunder_sound_r)
400	400	{
401	401	if (offset == 1)
402		return ((m_tc0140syt->tc0140syt_comm_r(space, 0) & 0xff));
	402	return ((m_tc0140syt->master_comm_r(space, 0) & 0xff));
403	403	else
404	404	return 0;
405	405	}
r29505	r29506
460	460	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank10")
461	461	AM_RANGE(0xc000, 0xdfff) AM_RAM
462	462	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
463		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
464		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	463	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	464	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
465	465	AM_RANGE(0xe400, 0xe403) AM_WRITE(othunder_TC0310FAM_w) /* pan */
466	466	AM_RANGE(0xe600, 0xe600) AM_WRITENOP /* ? */
467	467	AM_RANGE(0xea00, 0xea00) AM_READ_PORT(ROTARY_PORT_TAG)  /* rotary input */
r29505	r29506
623	623	MACHINE DRIVERS
624	624	***********************************************************/
625	625
626		static const tc0100scn_interface othunder_tc0100scn_intf =
627		{
628		1, 2,       /* gfxnum, txnum */
629		4, 0,       /* x_offset, y_offset */
630		0, 0,       /* flip_xoff, flip_yoff */
631		0, 0,       /* flip_text_xoff, flip_text_yoff */
632		0, 0
633		};
634
635		static const tc0140syt_interface othunder_tc0140syt_intf =
636		{
637		"maincpu", "audiocpu"
638		};
639
640	626	void othunder_state::machine_start()
641	627	{
642	628	membank("bank10")->configure_entries(0, 4, memregion("audiocpu")->base() + 0xc000, 0x4000);
r29505	r29506
688	674	MCFG_GFXDECODE_ADD("gfxdecode", "palette", othunder)
689	675	MCFG_PALETTE_ADD("palette", 4096)
690	676
691
692		MCFG_TC0100SCN_ADD("tc0100scn", othunder_tc0100scn_intf)
	677	MCFG_DEVICE_ADD("tc0100scn", TC0100SCN, 0)
	678	MCFG_TC0100SCN_GFX_REGION(1)
	679	MCFG_TC0100SCN_TX_REGION(2)
	680	MCFG_TC0100SCN_OFFSETS(4, 0)
693	681	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
694	682	MCFG_TC0100SCN_PALETTE("palette")
695	683
r29505	r29506
721	709	MCFG_FILTER_VOLUME_ADD("2610.2r", 0)
722	710	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
723	711
724		MCFG_TC0140SYT_ADD("tc0140syt", othunder_tc0140syt_intf)
	712	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	713	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	714	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
725	715	MACHINE_CONFIG_END
726	716
727	717

branches/new_menus/src/mame/drivers/bfmsys85.c

r29505	r29506
415	415	MCFG_CPU_ADD("maincpu", M6809, MASTER_CLOCK/4)          // 6809 CPU at 1 Mhz
416	416	MCFG_CPU_PROGRAM_MAP(memmap)                        // setup read and write memorymap
417	417	MCFG_CPU_PERIODIC_INT_DRIVER(bfmsys85_state, timer_irq,  1000)              // generate 1000 IRQ's per second
418		MCFG_MSC1937_ADD("vfd",0,RIGHT_TO_LEFT)
	418	MCFG_MSC1937_ADD("vfd",0)
419	419
420	420	MCFG_DEVICE_ADD("acia6850_0", ACIA6850, 0)
421	421	MCFG_ACIA6850_TXD_HANDLER(WRITELINE(bfmsys85_state,sys85_data_w))

branches/new_menus/src/mame/drivers/taito_b.c

r29505	r29506
474	474	AM_RANGE(0x200000, 0x201fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
475	475	AM_RANGE(0x600000, 0x607fff) AM_RAM /* Main RAM */ /*ashura up to 603fff only*/
476	476	TC0180VCU_MEMRW( 0x400000 )
477		AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
478		AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	477	AM_RANGE(0x800000, 0x800001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	478	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
479	479	AM_RANGE(0xa00000, 0xa0000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0xff00)
480	480	ADDRESS_MAP_END
481	481
r29505	r29506
484	484	AM_RANGE(0x000000, 0x07ffff) AM_ROM
485	485	AM_RANGE(0x200000, 0x20000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0xff00)
486	486	TC0180VCU_MEMRW( 0x400000 )
487		AM_RANGE(0x600000, 0x600001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
488		AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	487	AM_RANGE(0x600000, 0x600001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	488	AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
489	489	AM_RANGE(0x800000, 0x801fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
490	490	AM_RANGE(0xa00000, 0xa0ffff) AM_RAM /* Main RAM */
491	491	ADDRESS_MAP_END
r29505	r29506
493	493
494	494	static ADDRESS_MAP_START( tetrist_map, AS_PROGRAM, 16, taitob_state )
495	495	AM_RANGE(0x000000, 0x07ffff) AM_ROM
496		AM_RANGE(0x200000, 0x200001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
497		AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	496	AM_RANGE(0x200000, 0x200001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	497	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
498	498	TC0180VCU_MEMRW( 0x400000 )
499	499	AM_RANGE(0x600000, 0x60000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0xff00)
500	500	AM_RANGE(0x800000, 0x807fff) AM_RAM /* Main RAM */
r29505	r29506
508	508	AM_RANGE(0x600000, 0x600001) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, portreg_r, portreg_w, 0xff00)
509	509	AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, port_r, port_w, 0xff00)
510	510	AM_RANGE(0x800000, 0x803fff) AM_RAM /* Main RAM */
511		AM_RANGE(0xa00000, 0xa00001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
512		AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	511	AM_RANGE(0xa00000, 0xa00001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	512	AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
513	513	ADDRESS_MAP_END
514	514
515	515
r29505	r29506
518	518	TC0180VCU_MEMRW( 0x400000 )
519	519	AM_RANGE(0x600000, 0x60000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0xff00)
520	520	AM_RANGE(0x610000, 0x610001) AM_READ_PORT("P3_P4")
521		AM_RANGE(0x700000, 0x700001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
522		AM_RANGE(0x700002, 0x700003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	521	AM_RANGE(0x700000, 0x700001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	522	AM_RANGE(0x700002, 0x700003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
523	523	AM_RANGE(0x800000, 0x803fff) AM_RAM /* Main RAM */
524	524	AM_RANGE(0xa00000, 0xa01fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
525	525	AM_RANGE(0xb00000, 0xb7ffff) AM_RAM_WRITE(hitice_pixelram_w) AM_SHARE("pixelram")
r29505	r29506
531	531
532	532	static ADDRESS_MAP_START( rambo3_map, AS_PROGRAM, 16, taitob_state )
533	533	AM_RANGE(0x000000, 0x07ffff) AM_ROM
534		AM_RANGE(0x200000, 0x200001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
535		AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	534	AM_RANGE(0x200000, 0x200001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	535	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
536	536	TC0180VCU_MEMRW( 0x400000 )
537	537	AM_RANGE(0x600000, 0x60000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0xff00)
538	538	AM_RANGE(0x600010, 0x600011) AM_READ(tracky1_lo_r) /*player 1*/
r29505	r29506
557	557	AM_RANGE(0x500028, 0x500029) AM_WRITE(player_34_coin_ctrl_w)    /* simply locks coins 3&4 out */
558	558	AM_RANGE(0x50002e, 0x50002f) AM_READ_PORT("P3_P4_B")        /* shown in service mode, game omits to read it */
559	559	AM_RANGE(0x600000, 0x600003) AM_WRITE(gain_control_w)
560		AM_RANGE(0x700000, 0x700001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
561		AM_RANGE(0x700002, 0x700003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	560	AM_RANGE(0x700000, 0x700001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	561	AM_RANGE(0x700002, 0x700003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
562	562	AM_RANGE(0x800000, 0x801fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
563	563	AM_RANGE(0x900000, 0x90ffff) AM_RAM /* Main RAM */
564	564	ADDRESS_MAP_END
r29505	r29506
573	573	AM_RANGE(0x500028, 0x500029) AM_WRITE(player_34_coin_ctrl_w)    /* simply locks coins 3&4 out */
574	574	AM_RANGE(0x50002e, 0x50002f) AM_READ_PORT("P3_P4_B")
575	575	AM_RANGE(0x600000, 0x600003) AM_WRITE(gain_control_w)
576		AM_RANGE(0x700000, 0x700001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
577		AM_RANGE(0x700002, 0x700003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	576	AM_RANGE(0x700000, 0x700001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	577	AM_RANGE(0x700002, 0x700003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
578	578	AM_RANGE(0x800000, 0x801fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
579	579	AM_RANGE(0x900000, 0x90ffff) AM_RAM /* Main RAM */
580	580	ADDRESS_MAP_END
581	581
582	582	static ADDRESS_MAP_START( spacedxo_map, AS_PROGRAM, 16, taitob_state )
583	583	AM_RANGE(0x000000, 0x07ffff) AM_ROM
584		AM_RANGE(0x100000, 0x100001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
585		AM_RANGE(0x100002, 0x100003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	584	AM_RANGE(0x100000, 0x100001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	585	AM_RANGE(0x100002, 0x100003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
586	586	AM_RANGE(0x200000, 0x20000f) AM_DEVREAD8("tc0220ioc", tc0220ioc_device, read, 0x00ff) AM_WRITE(spacedxo_tc0220ioc_w)
587	587	AM_RANGE(0x210000, 0x210001) AM_READ_PORT("IN3")
588	588	AM_RANGE(0x220000, 0x220001) AM_READ_PORT("IN4")
r29505	r29506
602	602	AM_RANGE(0x200028, 0x200029) AM_READWRITE(player_34_coin_ctrl_r, player_34_coin_ctrl_w)
603	603	AM_RANGE(0x20002e, 0x20002f) AM_READ_PORT("P3_P4_B")    /* player 3,4 buttons */
604	604	TC0180VCU_MEMRW( 0x400000 )
605		AM_RANGE(0x600000, 0x600001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
606		AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	605	AM_RANGE(0x600000, 0x600001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	606	AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
607	607	AM_RANGE(0x700000, 0x700003) AM_WRITE(gain_control_w)
608	608	AM_RANGE(0x800000, 0x801fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
609	609	AM_RANGE(0x900000, 0x90ffff) AM_RAM /* Main RAM */
r29505	r29506
612	612
613	613	static ADDRESS_MAP_START( viofight_map, AS_PROGRAM, 16, taitob_state )
614	614	AM_RANGE(0x000000, 0x07ffff) AM_ROM
615		AM_RANGE(0x200000, 0x200001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
616		AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	615	AM_RANGE(0x200000, 0x200001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	616	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
617	617	TC0180VCU_MEMRW( 0x400000 )
618	618	AM_RANGE(0x600000, 0x601fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
619	619	AM_RANGE(0x800000, 0x80000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0xff00)
r29505	r29506
628	628	AM_RANGE(0x600000, 0x601fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
629	629	AM_RANGE(0x800000, 0x800001) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, portreg_r, portreg_w, 0xff00)
630	630	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, port_r, port_w, 0xff00)
631		AM_RANGE(0xa00000, 0xa00001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
632		AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	631	AM_RANGE(0xa00000, 0xa00001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	632	AM_RANGE(0xa00002, 0xa00003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
633	633	ADDRESS_MAP_END
634	634
635	635
636	636	static ADDRESS_MAP_START( silentd_map, AS_PROGRAM, 16, taitob_state )
637	637	AM_RANGE(0x000000, 0x07ffff) AM_ROM
638		AM_RANGE(0x100000, 0x100001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
639		AM_RANGE(0x100002, 0x100003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	638	AM_RANGE(0x100000, 0x100001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	639	AM_RANGE(0x100002, 0x100003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
640	640	//  AM_RANGE(0x10001a, 0x10001b) AM_READNOP // ??? read at $1e344
641	641	//  AM_RANGE(0x10001c, 0x10001d) AM_READNOP // ??? read at $1e356
642	642	AM_RANGE(0x200000, 0x20000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0x00ff)
r29505	r29506
658	658	AM_RANGE(0x300000, 0x301fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
659	659	AM_RANGE(0x400000, 0x40000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0xff00)
660	660	AM_RANGE(0x410000, 0x41000f) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_device, read, write, 0xff00) /* mirror address - seems to be only used for coin control */
661		AM_RANGE(0x500000, 0x500001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
662		AM_RANGE(0x500002, 0x500003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	661	AM_RANGE(0x500000, 0x500001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	662	AM_RANGE(0x500002, 0x500003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
663	663	ADDRESS_MAP_END
664	664
665	665
r29505	r29506
668	668	AM_RANGE(0x100000, 0x10ffff) AM_RAM /* Main RAM */
669	669	AM_RANGE(0x200000, 0x201fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
670	670	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_wordswap_r, halfword_wordswap_w)
671		AM_RANGE(0x320000, 0x320001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
672		AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0xff00)
	671	AM_RANGE(0x320000, 0x320001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	672	AM_RANGE(0x320002, 0x320003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w, 0xff00)
673	673	TC0180VCU_MEMRW( 0x900000 )
674	674	ADDRESS_MAP_END
675	675
r29505	r29506
680	680	AM_RANGE(0x130000, 0x13ffff) AM_RAM // Check me
681	681	AM_RANGE(0x180000, 0x18000f) AM_DEVREADWRITE("tc0510nio", tc0510nio_device, halfword_wordswap_r, halfword_wordswap_w)
682	682	AM_RANGE(0x184000, 0x184001) AM_WRITE(realpunc_video_ctrl_w)
683		AM_RANGE(0x188000, 0x188001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0xff00)
684		AM_RANGE(0x188002, 0x188003) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_w, 0xff00)
	683	AM_RANGE(0x188000, 0x188001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_port_w, 0xff00)
	684	AM_RANGE(0x188002, 0x188003) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_comm_w, 0xff00)
685	685	AM_RANGE(0x18c000, 0x18c001) AM_WRITE(realpunc_output_w)
686	686	TC0180VCU_MEMRW( 0x200000 )
687	687	AM_RANGE(0x280000, 0x281fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
688	688	AM_RANGE(0x300000, 0x300001) AM_DEVREADWRITE("hd63484", hd63484_device, status_r, address_w)
689	689	AM_RANGE(0x300002, 0x300003) AM_DEVREADWRITE("hd63484", hd63484_device, data_r, data_w)
690	690	//  AM_RANGE(0x320000, 0x320001) AM_NOP // ?
691		AM_RANGE(0x320002, 0x320003) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_w, 0xff00)
	691	AM_RANGE(0x320002, 0x320003) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, master_comm_w, 0xff00)
692	692	ADDRESS_MAP_END
693	693
694	694	static ADDRESS_MAP_START( masterw_sound_map, AS_PROGRAM, 8, taitob_state )
r29505	r29506
696	696	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
697	697	AM_RANGE(0x8000, 0x8fff) AM_RAM
698	698	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2203_device, read, write)
699		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
700		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	699	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	700	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
701	701	ADDRESS_MAP_END
702	702
703	703	static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, taitob_state )
r29505	r29506
705	705	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
706	706	AM_RANGE(0xc000, 0xdfff) AM_RAM
707	707	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
708		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
709		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	708	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	709	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
710	710	AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
711	711	AM_RANGE(0xe600, 0xe600) AM_WRITENOP /* ? */
712	712	AM_RANGE(0xea00, 0xea00) AM_READNOP
r29505	r29506
721	721	AM_RANGE(0x8000, 0x8fff) AM_RAM
722	722	AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2203_device, read, write)
723	723	AM_RANGE(0xb000, 0xb001) AM_DEVREADWRITE("oki", okim6295_device, read, write)       /* yes, both addresses for the same chip */
724		AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
725		AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
	724	AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	725	AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r, slave_comm_w)
726	726	ADDRESS_MAP_END
727	727
728	728
r29505	r29506
1906	1906	}
1907	1907	}
1908	1908
1909		/* this is the basic layout used in: Nastar, Ashura Blaster, Hit the Ice, Rambo3, Tetris */
1910		static const tc0180vcu_interface color0_tc0180vcu_intf =
1911		{
1912		0xc0,       /* background */
1913		0x80,       /* foreground */
1914		0x00        /* text       */
1915		};
1916	1909
1917		/* this is the reversed layout used in: Crime City, Puzzle Bobble */
1918		static const tc0180vcu_interface color1_tc0180vcu_intf =
1919		{
1920		0x00,       /* background */
1921		0x40,       /* foreground */
1922		0xc0        /* text       */
1923		};
1924
1925		/* this is used in: rambo3a, masterw, silentd, selfeena, ryujin */
1926		static const tc0180vcu_interface color2_tc0180vcu_intf =
1927		{
1928		0x30,       /* background */
1929		0x20,       /* foreground */
1930		0x00        /* text       */
1931		};
1932
1933
1934		static const tc0140syt_interface taitob_tc0140syt_intf =
1935		{
1936		"maincpu", "audiocpu"
1937		};
1938
1939	1910	void taitob_state::machine_start()
1940	1911	{
1941	1912	m_ym = machine().device("ymsnd");
r29505	r29506
1986	1957
1987	1958	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order0)
1988	1959
1989		MCFG_TC0180VCU_ADD("tc0180vcu", color0_tc0180vcu_intf)
	1960	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	1961	MCFG_TC0180VCU_BG_COLORBASE(0xc0)
	1962	MCFG_TC0180VCU_FG_COLORBASE(0x80)
	1963	MCFG_TC0180VCU_TX_COLORBASE(0x00)
1990	1964	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
1991	1965
1992	1966	/* sound hardware */
r29505	r29506
1998	1972	MCFG_SOUND_ROUTE(1, "mono", 1.0)
1999	1973	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2000	1974
2001		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	1975	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	1976	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	1977	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2002	1978	MACHINE_CONFIG_END
2003	1979
2004	1980
r29505	r29506
2037	2013
2038	2014	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order2)
2039	2015
2040		MCFG_TC0180VCU_ADD("tc0180vcu", color2_tc0180vcu_intf)
	2016	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2017	MCFG_TC0180VCU_BG_COLORBASE(0x30)
	2018	MCFG_TC0180VCU_FG_COLORBASE(0x20)
	2019	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2041	2020	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2042	2021
2043	2022	/* sound hardware */
r29505	r29506
2051	2030	MCFG_SOUND_ROUTE(2, "mono", 0.25)
2052	2031	MCFG_SOUND_ROUTE(3, "mono", 0.80)
2053	2032
2054		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2033	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2034	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2035	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2055	2036	MACHINE_CONFIG_END
2056	2037
2057	2038
r29505	r29506
2107	2088
2108	2089	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order0)
2109	2090
2110		MCFG_TC0180VCU_ADD("tc0180vcu", color0_tc0180vcu_intf)
	2091	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2092	MCFG_TC0180VCU_BG_COLORBASE(0xc0)
	2093	MCFG_TC0180VCU_FG_COLORBASE(0x80)
	2094	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2111	2095	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2112	2096
2113	2097	/* sound hardware */
r29505	r29506
2119	2103	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2120	2104	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2121	2105
2122		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2106	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2107	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2108	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2123	2109	MACHINE_CONFIG_END
2124	2110
2125	2111
r29505	r29506
2158	2144
2159	2145	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order1)
2160	2146
2161		MCFG_TC0180VCU_ADD("tc0180vcu", color1_tc0180vcu_intf)
	2147	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2148	MCFG_TC0180VCU_BG_COLORBASE(0x00)
	2149	MCFG_TC0180VCU_FG_COLORBASE(0x40)
	2150	MCFG_TC0180VCU_TX_COLORBASE(0xc0)
2162	2151	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2163	2152
2164	2153	/* sound hardware */
r29505	r29506
2170	2159	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2171	2160	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2172	2161
2173		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2162	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2163	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2164	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2174	2165	MACHINE_CONFIG_END
2175	2166
2176	2167
r29505	r29506
2210	2201	MCFG_VIDEO_START_OVERRIDE(taitob_state,hitice)
2211	2202	MCFG_VIDEO_RESET_OVERRIDE(taitob_state,hitice)
2212	2203
2213		MCFG_TC0180VCU_ADD("tc0180vcu", color0_tc0180vcu_intf)
	2204	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2205	MCFG_TC0180VCU_BG_COLORBASE(0xc0)
	2206	MCFG_TC0180VCU_FG_COLORBASE(0x80)
	2207	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2214	2208	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2215	2209
2216	2210	/* sound hardware */
r29505	r29506
2227	2221	MCFG_OKIM6295_ADD("oki", 1056000, OKIM6295_PIN7_HIGH) // clock frequency & pin 7 not verified
2228	2222	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
2229	2223
2230		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2224	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2225	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2226	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2231	2227	MACHINE_CONFIG_END
2232	2228
2233	2229
r29505	r29506
2266	2262
2267	2263	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order0)
2268	2264
2269		MCFG_TC0180VCU_ADD("tc0180vcu", color0_tc0180vcu_intf)
	2265	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2266	MCFG_TC0180VCU_BG_COLORBASE(0xc0)
	2267	MCFG_TC0180VCU_FG_COLORBASE(0x80)
	2268	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2270	2269	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2271	2270
2272	2271	/* sound hardware */
r29505	r29506
2278	2277	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2279	2278	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2280	2279
2281		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2280	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2281	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2282	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2282	2283	MACHINE_CONFIG_END
2283	2284
2284	2285
r29505	r29506
2317	2318
2318	2319	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order2)
2319	2320
2320		MCFG_TC0180VCU_ADD("tc0180vcu", color2_tc0180vcu_intf)
	2321	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2322	MCFG_TC0180VCU_BG_COLORBASE(0x30)
	2323	MCFG_TC0180VCU_FG_COLORBASE(0x20)
	2324	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2321	2325	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2322	2326
2323	2327	/* sound hardware */
r29505	r29506
2329	2333	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2330	2334	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2331	2335
2332		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2336	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2337	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2338	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2333	2339	MACHINE_CONFIG_END
2334	2340
2335	2341
r29505	r29506
2374	2380
2375	2381	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order1)
2376	2382
2377		MCFG_TC0180VCU_ADD("tc0180vcu", color1_tc0180vcu_intf)
	2383	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2384	MCFG_TC0180VCU_BG_COLORBASE(0x00)
	2385	MCFG_TC0180VCU_FG_COLORBASE(0x40)
	2386	MCFG_TC0180VCU_TX_COLORBASE(0xc0)
2378	2387	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2379	2388
2380	2389	/* sound hardware */
r29505	r29506
2386	2395	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2387	2396	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2388	2397
2389		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2398	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2399	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2400	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2390	2401	MACHINE_CONFIG_END
2391	2402
2392	2403
r29505	r29506
2431	2442
2432	2443	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order1)
2433	2444
2434		MCFG_TC0180VCU_ADD("tc0180vcu", color1_tc0180vcu_intf)
	2445	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2446	MCFG_TC0180VCU_BG_COLORBASE(0x00)
	2447	MCFG_TC0180VCU_FG_COLORBASE(0x40)
	2448	MCFG_TC0180VCU_TX_COLORBASE(0xc0)
2435	2449	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2436	2450
2437	2451	/* sound hardware */
r29505	r29506
2443	2457	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2444	2458	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2445	2459
2446		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2460	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2461	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2462	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2447	2463	MACHINE_CONFIG_END
2448	2464
2449	2465
r29505	r29506
2482	2498
2483	2499	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order2)
2484	2500
2485		MCFG_TC0180VCU_ADD("tc0180vcu", color2_tc0180vcu_intf)
	2501	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2502	MCFG_TC0180VCU_BG_COLORBASE(0x30)
	2503	MCFG_TC0180VCU_FG_COLORBASE(0x20)
	2504	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2486	2505	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2487	2506
2488	2507	/* sound hardware */
r29505	r29506
2494	2513	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2495	2514	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2496	2515
2497		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2516	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2517	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2518	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2498	2519	MACHINE_CONFIG_END
2499	2520
2500	2521
r29505	r29506
2539	2560
2540	2561	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order1)
2541	2562
2542		MCFG_TC0180VCU_ADD("tc0180vcu", color1_tc0180vcu_intf)
	2563	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2564	MCFG_TC0180VCU_BG_COLORBASE(0x00)
	2565	MCFG_TC0180VCU_FG_COLORBASE(0x40)
	2566	MCFG_TC0180VCU_TX_COLORBASE(0xc0)
2543	2567	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2544	2568
2545	2569	/* sound hardware */
r29505	r29506
2551	2575	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2552	2576	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2553	2577
2554		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2578	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2579	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2580	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2555	2581	MACHINE_CONFIG_END
2556	2582
2557	2583
r29505	r29506
2590	2616
2591	2617	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order2)
2592	2618
2593		MCFG_TC0180VCU_ADD("tc0180vcu", color2_tc0180vcu_intf)
	2619	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2620	MCFG_TC0180VCU_BG_COLORBASE(0x30)
	2621	MCFG_TC0180VCU_FG_COLORBASE(0x20)
	2622	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2594	2623	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2595	2624
2596	2625	/* sound hardware */
r29505	r29506
2607	2636	MCFG_OKIM6295_ADD("oki", XTAL_4_224MHz/4, OKIM6295_PIN7_HIGH) // 1.056MHz clock frequency, but pin 7 not verified
2608	2637	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
2609	2638
2610		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2639	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2640	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2641	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2611	2642	MACHINE_CONFIG_END
2612	2643
2613	2644
r29505	r29506
2646	2677
2647	2678	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order2)
2648	2679
2649		MCFG_TC0180VCU_ADD("tc0180vcu", color2_tc0180vcu_intf)
	2680	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2681	MCFG_TC0180VCU_BG_COLORBASE(0x30)
	2682	MCFG_TC0180VCU_FG_COLORBASE(0x20)
	2683	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2650	2684	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2651	2685
2652	2686	/* sound hardware */
r29505	r29506
2658	2692	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2659	2693	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2660	2694
2661		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2695	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2696	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2697	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2662	2698	MACHINE_CONFIG_END
2663	2699
2664	2700
r29505	r29506
2697	2733
2698	2734	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order2)
2699	2735
2700		MCFG_TC0180VCU_ADD("tc0180vcu", color2_tc0180vcu_intf)
	2736	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2737	MCFG_TC0180VCU_BG_COLORBASE(0x30)
	2738	MCFG_TC0180VCU_FG_COLORBASE(0x20)
	2739	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2701	2740	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2702	2741
2703	2742	/* sound hardware */
r29505	r29506
2709	2748	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2710	2749	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2711	2750
2712		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2751	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2752	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2753	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2713	2754	MACHINE_CONFIG_END
2714	2755
2715	2756	#if 0
r29505	r29506
2757	2798
2758	2799	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order2)
2759	2800
2760		MCFG_TC0180VCU_ADD("tc0180vcu", color2_tc0180vcu_intf)
	2801	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2802	MCFG_TC0180VCU_BG_COLORBASE(0x30)
	2803	MCFG_TC0180VCU_FG_COLORBASE(0x20)
	2804	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2761	2805	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2762	2806
2763	2807	/* sound hardware */
r29505	r29506
2769	2813	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2770	2814	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2771	2815
2772		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2816	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2817	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2818	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2773	2819	MACHINE_CONFIG_END
2774	2820
2775	2821	#if 0
r29505	r29506
2815	2861
2816	2862	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order0)
2817	2863
2818		MCFG_TC0180VCU_ADD("tc0180vcu", color0_tc0180vcu_intf)
	2864	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2865	MCFG_TC0180VCU_BG_COLORBASE(0xc0)
	2866	MCFG_TC0180VCU_FG_COLORBASE(0x80)
	2867	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2819	2868	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2820	2869
2821	2870	/* sound hardware */
r29505	r29506
2827	2876	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2828	2877	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2829	2878
2830		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2879	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2880	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2881	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2831	2882	MACHINE_CONFIG_END
2832	2883
2833	2884	/* TODO: Properly hook up the HD63484 */
r29505	r29506
2872	2923
2873	2924	MCFG_HD63484_ADD("hd63484", realpunc_hd63484_intf)
2874	2925
2875		MCFG_TC0180VCU_ADD("tc0180vcu", color0_tc0180vcu_intf)
	2926	MCFG_DEVICE_ADD("tc0180vcu", TC0180VCU, 0)
	2927	MCFG_TC0180VCU_BG_COLORBASE(0xc0)
	2928	MCFG_TC0180VCU_FG_COLORBASE(0x80)
	2929	MCFG_TC0180VCU_TX_COLORBASE(0x00)
2876	2930	MCFG_TC0180VCU_GFXDECODE("gfxdecode")
2877	2931
2878	2932	/* sound hardware */
r29505	r29506
2884	2938	MCFG_SOUND_ROUTE(1, "mono", 1.0)
2885	2939	MCFG_SOUND_ROUTE(2, "mono", 1.0)
2886	2940
2887		MCFG_TC0140SYT_ADD("tc0140syt", taitob_tc0140syt_intf)
	2941	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	2942	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	2943	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
2888	2944	MACHINE_CONFIG_END
2889	2945
2890	2946	/***************************************************************************

branches/new_menus/src/mame/drivers/metro.c

r29505	r29506
4501	4501	MACHINE_CONFIG_END
4502	4502
4503	4503
4504		static const k053936_interface blzntrnd_k053936_intf =
4505		{
4506		0, -69, -21
4507		};
4508
4509	4504	static MACHINE_CONFIG_START( blzntrnd, metro_state )
4510	4505
4511	4506	/* basic machine hardware */
r29505	r29506
4535	4530	MCFG_PALETTE_ADD("palette", 0x1000)
4536	4531	MCFG_PALETTE_FORMAT(GGGGGRRRRRBBBBBx)
4537	4532
4538		MCFG_K053936_ADD("k053936", blzntrnd_k053936_intf)
	4533	MCFG_DEVICE_ADD("k053936", K053936, 0)
	4534	MCFG_K053936_OFFSETS(-69, -21)
4539	4535
4540	4536	/* sound hardware */
4541	4537	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r29505	r29506
4550	4546
4551	4547	/* like blzntrnd but new vidstart / gfxdecode for the different bg tilemap */
4552	4548
4553		static const k053936_interface gstrik2_k053936_intf =
4554		{
4555		0, -69, -19
4556		};
4557
4558	4549	static MACHINE_CONFIG_START( gstrik2, metro_state )
4559	4550
4560	4551	/* basic machine hardware */
r29505	r29506
4584	4575	MCFG_PALETTE_ADD("palette", 0x1000)
4585	4576	MCFG_PALETTE_FORMAT(GGGGGRRRRRBBBBBx)
4586	4577
4587		MCFG_K053936_ADD("k053936", gstrik2_k053936_intf)
	4578	MCFG_DEVICE_ADD("k053936", K053936, 0)
	4579	MCFG_K053936_OFFSETS(-69, -19)
4588	4580
4589	4581	/* sound hardware */
4590	4582	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")

branches/new_menus/src/mame/drivers/ninjaw.c

r29505	r29506
362	362	WRITE16_MEMBER(ninjaw_state::ninjaw_sound_w)
363	363	{
364	364	if (offset == 0)
365		m_tc0140syt->tc0140syt_port_w(space, 0, data & 0xff);
	365	m_tc0140syt->master_port_w(space, 0, data & 0xff);
366	366	else if (offset == 1)
367		m_tc0140syt->tc0140syt_comm_w(space, 0, data & 0xff);
	367	m_tc0140syt->master_comm_w(space, 0, data & 0xff);
368	368
369	369	#ifdef MAME_DEBUG
370	370	if (data & 0xff00)
r29505	r29506
375	375	READ16_MEMBER(ninjaw_state::ninjaw_sound_r)
376	376	{
377	377	if (offset == 1)
378		return ((m_tc0140syt->tc0140syt_comm_r(space, 0) & 0xff));
	378	return ((m_tc0140syt->master_comm_r(space, 0) & 0xff));
379	379	else
380	380	return 0;
381	381	}
r29505	r29506
487	487	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank10")
488	488	AM_RANGE(0xc000, 0xdfff) AM_RAM
489	489	AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_device, read, write)
490		AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_port_w)
491		AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, tc0140syt_slave_comm_r,tc0140syt_slave_comm_w)
	490	AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, slave_port_w)
	491	AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, slave_comm_r,slave_comm_w)
492	492	AM_RANGE(0xe400, 0xe403) AM_WRITE(ninjaw_pancontrol) /* pan */
493	493	AM_RANGE(0xea00, 0xea00) AM_READNOP
494	494	AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
r29505	r29506
724	724	Darius2: arbitrary interleaving of 10 to keep cpus synced.
725	725	*************************************************************/
726	726
727		static const tc0100scn_interface darius2_tc0100scn_intf_l =
728		{
729		1, 3,       /* gfxnum, txnum */
730		22, 0,      /* x_offset, y_offset */
731		0, 0,       /* flip_xoff, flip_yoff */
732		0, 0,       /* flip_text_xoff, flip_text_yoff */
733		0, 0
734		};
735
736		static const tc0100scn_interface darius2_tc0100scn_intf_m =
737		{
738		2, 3,       /* gfxnum, txnum */
739		22, 0,      /* x_offset, y_offset */
740		0, 0,       /* flip_xoff, flip_yoff */
741		0, 0,       /* flip_text_xoff, flip_text_yoff */
742		2, 1
743		};
744
745		static const tc0100scn_interface darius2_tc0100scn_intf_r =
746		{
747		2, 3,       /* gfxnum, txnum */
748		22, 0,      /* x_offset, y_offset */
749		0, 0,       /* flip_xoff, flip_yoff */
750		0, 0,       /* flip_text_xoff, flip_text_yoff */
751		4, 1
752		};
753
754		static const tc0140syt_interface ninjaw_tc0140syt_intf =
755		{
756		"maincpu", "audiocpu"
757		};
758
759
760	727	void ninjaw_state::ninjaw_postload()
761	728	{
762	729	parse_control();
r29505	r29506
838	805	MCFG_SCREEN_UPDATE_DRIVER(ninjaw_state, screen_update_ninjaw_right)
839	806	MCFG_SCREEN_PALETTE("palette3")
840	807
841		MCFG_TC0100SCN_ADD("tc0100scn_1", darius2_tc0100scn_intf_l)
	808	MCFG_DEVICE_ADD("tc0100scn_1", TC0100SCN, 0)
	809	MCFG_TC0100SCN_GFX_REGION(1)
	810	MCFG_TC0100SCN_TX_REGION(3)
	811	MCFG_TC0100SCN_OFFSETS(22, 0)
	812	MCFG_TC0100SCN_MULTISCR_XOFFS(0)
	813	MCFG_TC0100SCN_MULTISCR_HACK(0)
842	814	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
843	815	MCFG_TC0100SCN_PALETTE("palette")
844		MCFG_TC0100SCN_ADD("tc0100scn_2", darius2_tc0100scn_intf_m)
	816
	817	MCFG_TC0110PCR_ADD("tc0110pcr_1")
	818	MCFG_TC0110PCR_PALETTE("palette")
	819
	820	MCFG_DEVICE_ADD("tc0100scn_2", TC0100SCN, 0)
	821	MCFG_TC0100SCN_GFX_REGION(2)
	822	MCFG_TC0100SCN_TX_REGION(3)
	823	MCFG_TC0100SCN_OFFSETS(22, 0)
	824	MCFG_TC0100SCN_MULTISCR_XOFFS(2)
	825	MCFG_TC0100SCN_MULTISCR_HACK(1)
845	826	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
846	827	MCFG_TC0100SCN_PALETTE("palette2")
847		MCFG_TC0100SCN_ADD("tc0100scn_3", darius2_tc0100scn_intf_r)
	828
	829	MCFG_TC0110PCR_ADD("tc0110pcr_2")
	830	MCFG_TC0110PCR_PALETTE("palette2")
	831
	832	MCFG_DEVICE_ADD("tc0100scn_3", TC0100SCN, 0)
	833	MCFG_TC0100SCN_GFX_REGION(2)
	834	MCFG_TC0100SCN_TX_REGION(3)
	835	MCFG_TC0100SCN_OFFSETS(22, 0)
	836	MCFG_TC0100SCN_MULTISCR_XOFFS(4)
	837	MCFG_TC0100SCN_MULTISCR_HACK(1)
848	838	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
849	839	MCFG_TC0100SCN_PALETTE("palette3")
850	840
851		MCFG_TC0110PCR_ADD("tc0110pcr_1")
852		MCFG_TC0110PCR_PALETTE("palette")
853		MCFG_TC0110PCR_ADD("tc0110pcr_2")
854		MCFG_TC0110PCR_PALETTE("palette2")
855	841	MCFG_TC0110PCR_ADD("tc0110pcr_3")
856	842	MCFG_TC0110PCR_PALETTE("palette3")
857	843
r29505	r29506
878	864
879	865	//  MCFG_SOUND_ADD("subwoofer", SUBWOOFER, 0)
880	866
881		MCFG_TC0140SYT_ADD("tc0140syt", ninjaw_tc0140syt_intf)
	867	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	868	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	869	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
882	870	MACHINE_CONFIG_END
883	871
884	872
r29505	r29506
937	925	MCFG_SCREEN_UPDATE_DRIVER(ninjaw_state, screen_update_ninjaw_right)
938	926	MCFG_SCREEN_PALETTE("palette3")
939	927
940		MCFG_TC0100SCN_ADD("tc0100scn_1", darius2_tc0100scn_intf_l)
	928	MCFG_DEVICE_ADD("tc0100scn_1", TC0100SCN, 0)
	929	MCFG_TC0100SCN_GFX_REGION(1)
	930	MCFG_TC0100SCN_TX_REGION(3)
	931	MCFG_TC0100SCN_OFFSETS(22, 0)
	932	MCFG_TC0100SCN_MULTISCR_XOFFS(0)
	933	MCFG_TC0100SCN_MULTISCR_HACK(0)
941	934	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
942	935	MCFG_TC0100SCN_PALETTE("palette")
943		MCFG_TC0100SCN_ADD("tc0100scn_2", darius2_tc0100scn_intf_m)
	936
	937	MCFG_TC0110PCR_ADD("tc0110pcr_1")
	938	MCFG_TC0110PCR_PALETTE("palette")
	939
	940	MCFG_DEVICE_ADD("tc0100scn_2", TC0100SCN, 0)
	941	MCFG_TC0100SCN_GFX_REGION(2)
	942	MCFG_TC0100SCN_TX_REGION(3)
	943	MCFG_TC0100SCN_OFFSETS(22, 0)
	944	MCFG_TC0100SCN_MULTISCR_XOFFS(2)
	945	MCFG_TC0100SCN_MULTISCR_HACK(1)
944	946	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
945	947	MCFG_TC0100SCN_PALETTE("palette2")
946		MCFG_TC0100SCN_ADD("tc0100scn_3", darius2_tc0100scn_intf_r)
	948
	949	MCFG_TC0110PCR_ADD("tc0110pcr_2")
	950	MCFG_TC0110PCR_PALETTE("palette2")
	951
	952	MCFG_DEVICE_ADD("tc0100scn_3", TC0100SCN, 0)
	953	MCFG_TC0100SCN_GFX_REGION(2)
	954	MCFG_TC0100SCN_TX_REGION(3)
	955	MCFG_TC0100SCN_OFFSETS(22, 0)
	956	MCFG_TC0100SCN_MULTISCR_XOFFS(4)
	957	MCFG_TC0100SCN_MULTISCR_HACK(1)
947	958	MCFG_TC0100SCN_GFXDECODE("gfxdecode")
948	959	MCFG_TC0100SCN_PALETTE("palette3")
949	960
950		MCFG_TC0110PCR_ADD("tc0110pcr_1")
951		MCFG_TC0110PCR_PALETTE("palette")
952		MCFG_TC0110PCR_ADD("tc0110pcr_2")
953		MCFG_TC0110PCR_PALETTE("palette2")
954	961	MCFG_TC0110PCR_ADD("tc0110pcr_3")
955	962	MCFG_TC0110PCR_PALETTE("palette3")
956	963
r29505	r29506
977	984
978	985	//  MCFG_SOUND_ADD("subwoofer", SUBWOOFER, 0)
979	986
980		MCFG_TC0140SYT_ADD("tc0140syt", ninjaw_tc0140syt_intf)
	987	MCFG_DEVICE_ADD("tc0140syt", TC0140SYT, 0)
	988	MCFG_TC0140SYT_MASTER_CPU("maincpu")
	989	MCFG_TC0140SYT_SLAVE_CPU("audiocpu")
981	990	MACHINE_CONFIG_END
982	991
983	992

branches/new_menus/src/mame/drivers/gunbustr.c

r29505	r29506
284	284	MACHINE DRIVERS
285	285	***********************************************************/
286	286
287		static const tc0480scp_interface gunbustr_tc0480scp_intf =
288		{
289		1, 2,           /* gfxnum, txnum */
290		0,              /* pixels */
291		0x20, 0x07,     /* x_offset, y_offset */
292		-1, -1,         /* text_xoff, text_yoff */
293		-1, 0,          /* flip_xoff, flip_yoff */
294		0               /* col_base */
295		};
296
297	287	static MACHINE_CONFIG_START( gunbustr, gunbustr_state )
298	288
299	289	/* basic machine hardware */
r29505	r29506
315	305	MCFG_GFXDECODE_ADD("gfxdecode", "palette", gunbustr)
316	306	MCFG_PALETTE_ADD("palette", 8192)
317	307
318
319		MCFG_TC0480SCP_ADD("tc0480scp", gunbustr_tc0480scp_intf)
	308	MCFG_DEVICE_ADD("tc0480scp", TC0480SCP, 0)
	309	MCFG_TC0480SCP_GFX_REGION(1)
	310	MCFG_TC0480SCP_TX_REGION(2)
	311	MCFG_TC0480SCP_OFFSETS(0x20, 0x07)
	312	MCFG_TC0480SCP_OFFSETS_TX(-1, -1)
	313	MCFG_TC0480SCP_OFFSETS_FLIP(-1, 0)
320	314	MCFG_TC0480SCP_GFXDECODE("gfxdecode")
321	315	MCFG_TC0480SCP_PALETTE("palette")
322	316

branches/new_menus/src/mame/drivers/playch10.c

r29505	r29506
665	665	"cart"
666	666	};
667	667
668
669	668	static MACHINE_CONFIG_START( playch10, playch10_state )
670	669	// basic machine hardware
671	670	MCFG_CPU_ADD("maincpu", Z80, 8000000/2) // 4 MHz
r29505	r29506
697	696	MCFG_SCREEN_UPDATE_DRIVER(playch10_state, screen_update_playch10_bottom)
698	697	MCFG_SCREEN_PALETTE("palette")
699	698
700
701		MCFG_PPU2C03B_ADD("ppu", playch10_ppu_interface)
	699	MCFG_PPU2C03B_ADD("ppu")
702	700	MCFG_PPU2C0X_SET_SCREEN("bottom")
	701	MCFG_PPU2C0X_CPU("cart")
	702	MCFG_PPU2C0X_COLORBASE(256)
703	703	MCFG_PPU2C0X_SET_NMI(playch10_state, ppu_irq)
704	704
705	705	// sound hardware

branches/new_menus/src/mame/drivers/bishi.c

r29505	r29506
372	372	bishi_tile_callback, "none"
373	373	};
374	374
375		static const k054338_interface bishi_k054338_intf =
376		{
377		0,
378		"none"
379		};
380
381	375	void bishi_state::machine_start()
382	376	{
383	377	save_item(NAME(m_cur_control));
r29505	r29506
416	410	MCFG_K056832_ADD("k056832", bishi_k056832_intf)
417	411	MCFG_K056832_GFXDECODE("gfxdecode")
418	412	MCFG_K056832_PALETTE("palette")
419		MCFG_K054338_ADD("k054338", bishi_k054338_intf)
	413
	414	MCFG_DEVICE_ADD("k054338", K054338, 0)
	415	// FP 201404: any reason why this is not connected to the k055555 below?
	416
420	417	MCFG_K055555_ADD("k055555")
421	418
422	419	/* sound hardware */

branches/new_menus/src/mame/drivers/quizpani.c

r29505	r29506
187	187	GFXDECODE_END
188	188
189	189
190		static const nmk112_interface quizpani_nmk112_intf =
191		{
192		"oki", "oki", 0
193		};
194
195
196	190	static MACHINE_CONFIG_START( quizpani, quizpani_state )
197	191	MCFG_CPU_ADD("maincpu", M68000, 10000000)
198	192	MCFG_CPU_PROGRAM_MAP(quizpani_map)
r29505	r29506
217	211	MCFG_OKIM6295_ADD("oki", 16000000/4, OKIM6295_PIN7_LOW)
218	212	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
219	213
220		MCFG_NMK112_ADD("nmk112", quizpani_nmk112_intf)
	214	MCFG_DEVICE_ADD("nmk112", NMK112, 0)
	215	MCFG_NMK112_ROM0("oki")
	216	MCFG_NMK112_ROM1("oki")
221	217	MACHINE_CONFIG_END
222	218
223	219	ROM_START( quizpani )

branches/new_menus/src/mame/audio/namco52.c

r29505	r29506
166	166	m_basenode(0),
167	167	m_extclock(0),
168	168	m_romread(*this),
169		m_si(*this)
	169	m_si(*this),
	170	m_latched_cmd(0),
	171	m_address(0)
170	172	{
171	173	}
172	174

branches/new_menus/src/mame/audio/taitosnd.c

r29505	r29506
44	44	m_submode(0),
45	45	m_status(0),
46	46	m_nmi_enabled(0),
47		m_mastercpu(NULL),
48		m_slavecpu(NULL)
	47	m_mastercpu(*this),
	48	m_slavecpu(*this)
49	49	{
50	50	memset(m_slavedata, 0, sizeof(UINT8)*4);
51	51	memset(m_masterdata, 0, sizeof(UINT8)*4);
r29505	r29506
58	58
59	59	void tc0140syt_device::device_start()
60	60	{
61		const tc0140syt_interface *intf = reinterpret_cast<const tc0140syt_interface*>(static_config());
62
63		m_mastercpu = machine().device(intf->master);
64		m_slavecpu = machine().device(intf->slave);
65
66	61	save_item(NAME(m_mainmode));
67	62	save_item(NAME(m_submode));
68	63	save_item(NAME(m_status));
r29505	r29506
100	95	UINT32 nmi_pending = m_status & (TC0140SYT_PORT23_FULL | TC0140SYT_PORT01_FULL);
101	96	UINT32 state = (nmi_pending && m_nmi_enabled) ? ASSERT_LINE : CLEAR_LINE;
102	97
103		m_slavecpu->execute().set_input_line(INPUT_LINE_NMI, state);
	98	m_slavecpu->set_input_line(INPUT_LINE_NMI, state);
104	99	}
105	100
106	101
r29505	r29506
108	103	//  MASTER SIDE
109	104	//-------------------------------------------------
110	105
111		WRITE8_MEMBER( tc0140syt_device::tc0140syt_port_w )
	106	WRITE8_MEMBER( tc0140syt_device::master_port_w )
112	107	{
113	108	data &= 0x0f;
114	109	m_mainmode = data;
r29505	r29506
119	114	}
120	115	}
121	116
122		WRITE8_MEMBER( tc0140syt_device::tc0140syt_comm_w )
	117	WRITE8_MEMBER( tc0140syt_device::master_comm_w )
123	118	{
124	119	machine().scheduler().synchronize(); // let slavecpu catch up before changing anything
125	120	data &= 0x0f; /* this is important, otherwise ballbros won't work */
r29505	r29506
148	143
149	144	case 0x04: // port status
150	145	/* this does a hi-lo transition to reset the sound cpu */
151		m_slavecpu->execute().set_input_line(INPUT_LINE_RESET, data ? ASSERT_LINE : CLEAR_LINE);
	146	m_slavecpu->set_input_line(INPUT_LINE_RESET, data ? ASSERT_LINE : CLEAR_LINE);
152	147	break;
153	148
154	149	default:
r29505	r29506
156	151	}
157	152	}
158	153
159		READ8_MEMBER( tc0140syt_device::tc0140syt_comm_r )
	154	READ8_MEMBER( tc0140syt_device::master_comm_r )
160	155	{
161	156	machine().scheduler().synchronize(); // let slavecpu catch up before changing anything
162	157	UINT8 res = 0;
r29505	r29506
197	192	//  SLAVE SIDE
198	193	//-------------------------------------------------
199	194
200		WRITE8_MEMBER( tc0140syt_device::tc0140syt_slave_port_w )
	195	WRITE8_MEMBER( tc0140syt_device::slave_port_w )
201	196	{
202	197	data &= 0x0f;
203	198	m_submode = data;
r29505	r29506
208	203	}
209	204	}
210	205
211		WRITE8_MEMBER( tc0140syt_device::tc0140syt_slave_comm_w )
	206	WRITE8_MEMBER( tc0140syt_device::slave_comm_w )
212	207	{
213	208	data &= 0x0f;
214	209
r29505	r29506
251	246	}
252	247	}
253	248
254		READ8_MEMBER( tc0140syt_device::tc0140syt_slave_comm_r )
	249	READ8_MEMBER( tc0140syt_device::slave_comm_r )
255	250	{
256	251	UINT8 res = 0;
257	252

branches/new_menus/src/mame/audio/taitosnd.h

r29505	r29506
6	6	//  INTERFACE CONFIGURATION MACROS
7	7	//**************************************************************************
8	8
9		#define MCFG_TC0140SYT_ADD(_tag, _interface) \
10		MCFG_DEVICE_ADD(_tag, TC0140SYT, 0) \
11		MCFG_DEVICE_CONFIG(_interface)
	9	#define MCFG_TC0140SYT_MASTER_CPU(_tag) \
	10	tc0140syt_device::set_master_tag(*device, "^"_tag);
12	11
	12	#define MCFG_TC0140SYT_SLAVE_CPU(_tag) \
	13	tc0140syt_device::set_slave_tag(*device, "^"_tag);
13	14
	15
14	16	//**************************************************************************
15	17	//  TYPE DEFINITIONS
16	18	//**************************************************************************
r29505	r29506
30	32	tc0140syt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
31	33	~tc0140syt_device() { }
32	34
	35	static void set_master_tag(device_t &device, const char *tag) { downcast<tc0140syt_device &>(device).m_mastercpu.set_tag(tag); }
	36	static void set_slave_tag(device_t &device, const char *tag)  { downcast<tc0140syt_device &>(device).m_slavecpu.set_tag(tag); }
	37
	38	// MASTER (4-bit bus) control functions
	39	DECLARE_WRITE8_MEMBER( master_port_w );
	40	DECLARE_WRITE8_MEMBER( master_comm_w );
	41	DECLARE_READ8_MEMBER( master_comm_r );
	42
	43	// SLAVE (4-bit bus) control functions ONLY
	44	DECLARE_WRITE8_MEMBER( slave_port_w );
	45	DECLARE_READ8_MEMBER( slave_comm_r );
	46	DECLARE_WRITE8_MEMBER( slave_comm_w );
	47
33	48	protected:
34	49	// device-level overrides
35	50	virtual void device_start();
36	51	virtual void device_reset();
37
38		public:
39		// MASTER (4-bit bus) control functions
40		DECLARE_WRITE8_MEMBER( tc0140syt_port_w );
41		DECLARE_WRITE8_MEMBER( tc0140syt_comm_w );
42		DECLARE_READ8_MEMBER( tc0140syt_comm_r );
43
44		// SLAVE (4-bit bus) control functions ONLY
45		DECLARE_WRITE8_MEMBER( tc0140syt_slave_port_w );
46		DECLARE_READ8_MEMBER( tc0140syt_slave_comm_r );
47		DECLARE_WRITE8_MEMBER( tc0140syt_slave_comm_w );
48
	52
49	53	private:
50	54	void update_nmi();
51	55
52		private:
53	56	UINT8     m_slavedata[4];  /* Data on master->slave port (4 nibbles) */
54	57	UINT8     m_masterdata[4]; /* Data on slave->master port (4 nibbles) */
55	58	UINT8     m_mainmode;      /* Access mode on master cpu side */
r29505	r29506
57	60	UINT8     m_status;        /* Status data */
58	61	UINT8     m_nmi_enabled;   /* 1 if slave cpu has nmi's enabled */
59	62
60		device_t *m_mastercpu;     /* this is the maincpu */
61		device_t *m_slavecpu;      /* this is the audiocpu */
	63	required_device<cpu_device> m_mastercpu;     /* this is the maincpu */
	64	required_device<cpu_device> m_slavecpu;      /* this is the audiocpu */
62	65	};
63	66
64	67	extern const device_type TC0140SYT;

branches/new_menus/src/mame/audio/namco54.c

r29505	r29506
134	134	: device_t(mconfig, NAMCO_54XX, "Namco 54xx", tag, owner, clock, "namco54", __FILE__),
135	135	m_cpu(*this, "mcu"),
136	136	m_discrete(*this),
137		m_basenode(0)
	137	m_basenode(0),
	138	m_latched_cmd(0)
138	139	{
139	140	}
140	141	//-------------------------------------------------

branches/new_menus/src/mame/machine/playch10.c

r29505	r29506
237	237	/* do the gun thing */
238	238	if (m_pc10_gun_controller)
239	239	{
240		ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
241	240	int trigger = ioport("P1")->read();
242	241	int x = ioport("GUNX")->read();
243	242	int y = ioport("GUNY")->read();
r29505	r29506
247	246	ret |= 0x08;
248	247
249	248	/* get the pixel at the gun position */
250		pix = ppu->get_pixel(x, y);
	249	pix = m_ppu->get_pixel(x, y);
251	250
252	251	/* get the color base from the ppu */
253		color_base = ppu->get_colorbase();
	252	color_base = m_ppu->get_colorbase();
254	253
255	254	/* look at the screen and see if the cursor is over a bright pixel */
256	255	if ((pix == color_base + 0x20) || (pix == color_base + 0x30) ||

branches/new_menus/src/mame/machine/vsnes.c

r29505	r29506
343	343
344	344	WRITE8_MEMBER(vsnes_state::gun_in0_w)
345	345	{
346		ppu2c0x_device *ppu1 = machine().device<ppu2c0x_device>("ppu1");
347
348	346	if (m_do_vrom_bank)
349	347	{
350	348	/* switch vrom */
r29505	r29506
363	361	UINT32 pix, color_base;
364	362
365	363	/* get the pixel at the gun position */
366		pix = ppu1->get_pixel(x, y);
	364	pix = m_ppu1->get_pixel(x, y);
367	365
368	366	/* get the color base from the ppu */
369		color_base = ppu1->get_colorbase();
	367	color_base = m_ppu1->get_colorbase();
370	368
371	369	/* look at the screen and see if the cursor is over a bright pixel */
372	370	if ((pix == color_base + 0x20 ) || (pix == color_base + 0x30) ||
r29505	r29506
669	667
670	668	WRITE8_MEMBER(vsnes_state::mapper4_w)
671	669	{
672		ppu2c0x_device *ppu1 = machine().device<ppu2c0x_device>("ppu1");
673	670	UINT8 MMC3_helper, cmd;
674	671
675	672	switch (offset & 0x6001)
r29505	r29506
718	715
719	716	case 0x2001: /* $a001 - extra RAM enable/disable */
720	717	/* ignored - we always enable it */
721
722	718	break;
	719
723	720	case 0x4000: /* $c000 - IRQ scanline counter */
724	721	m_IRQ_count = data;
725
726	722	break;
727	723
728	724	case 0x4001: /* $c001 - IRQ scanline latch */
729	725	m_IRQ_count_latch = data;
730
731	726	break;
732	727
733	728	case 0x6000: /* $e000 - Disable IRQs */
734	729	m_IRQ_enable = 0;
735	730	m_IRQ_count = m_IRQ_count_latch;
736
737		ppu1->set_scanline_callback(ppu2c0x_scanline_delegate());
738
	731	m_ppu1->set_scanline_callback(ppu2c0x_scanline_delegate());
739	732	break;
740	733
741	734	case 0x6001: /* $e001 - Enable IRQs */
742	735	m_IRQ_enable = 1;
743		ppu1->set_scanline_callback(ppu2c0x_scanline_delegate(FUNC(vsnes_state::mapper4_irq),this));
744
	736	m_ppu1->set_scanline_callback(ppu2c0x_scanline_delegate(FUNC(vsnes_state::mapper4_irq), this));
745	737	break;
746	738
747	739	default:

branches/new_menus/src/mame/machine/nmk112.c

r29505	r29506
18	18	const device_type NMK112 = &device_creator<nmk112_device>;
19	19
20	20	nmk112_device::nmk112_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
21		: device_t(mconfig, NMK112, "NMK 112", tag, owner, clock, "nmk112", __FILE__)
	21	: device_t(mconfig, NMK112, "NMK 112", tag, owner, clock, "nmk112", __FILE__),
	22	m_page_mask(0xff),
	23	m_rom0(NULL),
	24	m_rom1(NULL),
	25	m_size0(0),
	26	m_size1(0)
22	27	{
23	28	}
24	29
25	30	//-------------------------------------------------
26		//  device_config_complete - perform any
27		//  operations now that the configuration is
28		//  complete
29		//-------------------------------------------------
30
31		void nmk112_device::device_config_complete()
32		{
33		}
34
35		//-------------------------------------------------
36	31	//  device_start - device-specific startup
37	32	//-------------------------------------------------
38	33
39	34	void nmk112_device::device_start()
40	35	{
41		const nmk112_interface *intf = (const nmk112_interface *)static_config();
	36	save_item(NAME(m_current_bank));
	37	machine().save().register_postload(save_prepost_delegate(FUNC(nmk112_device::postload_bankswitch), this));
42	38
43		if (intf->rgn0 == NULL)
	39	if (m_tag0)
44	40	{
45		m_rom0 = NULL;
46		m_size0 = 0;
	41	m_rom0 = machine().root_device().memregion(m_tag0)->base();
	42	m_size0 = machine().root_device().memregion(m_tag0)->bytes() - 0x40000;
47	43	}
48		else
	44	if (m_tag1)
49	45	{
50		m_rom0 = machine().root_device().memregion(intf->rgn0)->base();
51		m_size0 = machine().root_device().memregion(intf->rgn0)->bytes() - 0x40000;
	46	m_rom1 = machine().root_device().memregion(m_tag1)->base();
	47	m_size1 = machine().root_device().memregion(m_tag1)->bytes() - 0x40000;
52	48	}
53
54		if (intf->rgn1 == NULL)
55		{
56		m_rom1 = NULL;
57		m_size1 = 0;
58		}
59		else
60		{
61		m_rom1 = machine().root_device().memregion(intf->rgn1)->base();
62		m_size1 = machine().root_device().memregion(intf->rgn1)->bytes() - 0x40000;
63		}
64
65		m_page_mask = ~intf->disable_page_mask;
66
67		save_item(NAME(m_current_bank));
68		machine().save().register_postload(save_prepost_delegate(FUNC(nmk112_device::postload_bankswitch), this));
69	49	}
70	50
71	51	//-------------------------------------------------
r29505	r29506
81	61	}
82	62	}
83	63
84
85	64	void nmk112_device::do_bankswitch( int offset, int data )
86	65	{
87	66	int chip = (offset & 4) >> 2;

branches/new_menus/src/mame/machine/nmk112.h

r29505	r29506
11	11	TYPE DEFINITIONS
12	12	***************************************************************************/
13	13
14		struct nmk112_interface
	14	class nmk112_device : public device_t
15	15	{
16		const char *rgn0, *rgn1;
17		UINT8 disable_page_mask;
18		};
19
20		class nmk112_device : public device_t,
21		public nmk112_interface
22		{
23	16	public:
24	17	nmk112_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
25	18	~nmk112_device() {}
26	19
	20	// static configuration
	21	static void set_rom0_tag(device_t &device, const char *tag) { downcast<nmk112_device &>(device).m_tag0 = tag; }
	22	static void set_rom1_tag(device_t &device, const char *tag) { downcast<nmk112_device &>(device).m_tag1 = tag; }
	23	static void set_page_mask(device_t &device, UINT8 mask) { downcast<nmk112_device &>(device).m_page_mask = ~mask; }
	24
27	25	DECLARE_WRITE8_MEMBER( okibank_w );
28	26	DECLARE_WRITE16_MEMBER( okibank_lsb_w );
29	27
30	28	protected:
31	29	// device-level overrides
32		virtual void device_config_complete();
33	30	virtual void device_start();
34	31	virtual void device_reset();
35	32
r29505	r29506
44	41
45	42	UINT8 m_current_bank[8];
46	43
	44	const char *m_tag0, *m_tag1;
47	45	UINT8 *m_rom0, *m_rom1;
48	46	int   m_size0, m_size1;
49	47	};
r29505	r29506
55	53	DEVICE CONFIGURATION MACROS
56	54	***************************************************************************/
57	55
58		#define MCFG_NMK112_ADD(_tag, _interface) \
59		MCFG_DEVICE_ADD(_tag, NMK112, 0) \
60		MCFG_DEVICE_CONFIG(_interface)
	56	#define MCFG_NMK112_ROM0(_tag) \
	57	nmk112_device::set_rom0_tag(*device, _tag);
61	58
	59	#define MCFG_NMK112_ROM1(_tag) \
	60	nmk112_device::set_rom1_tag(*device, _tag);
	61
	62	#define MCFG_NMK112_DISABLE_PAGEMASK(_mask) \
	63	nmk112_device::set_page_mask(*device, _mask);
	64
	65
62	66	#endif /* __NMK112_H__ */

branches/new_menus/src/mame/machine/archimds.c

r29505	r29506
75	75	void archimedes_state::archimedes_clear_irq_a(int mask)
76	76	{
77	77	m_ioc_regs[IRQ_STATUS_A] &= ~mask;
	78	archimedes_request_irq_a(0);
78	79	}
79	80
80	81	void archimedes_state::archimedes_clear_irq_b(int mask)
r29505	r29506
111	112
112	113	/* video DMA */
113	114	/* TODO: what type of DMA this is, burst or cycle steal? Docs doesn't explain it (4 usec is the DRAM refresh). */
	115	/* TODO: change m_region_vram into proper alloc array */
	116	/* TODO: Erotictac and Poizone sets up vidinit register AFTER vidend, for double buffering? (fixes Poizone "Eterna" logo display on attract) */
114	117	void archimedes_state::vidc_video_tick()
115	118	{
116	119	address_space &space = m_maincpu->space(AS_PROGRAM);
117	120	static UINT8 *vram = m_region_vram->base();
118	121	UINT32 size;
119	122	UINT32 m_vidc_ccur;
	123	UINT32 offset_ptr;
120	124
121	125	size = m_vidc_vidend-m_vidc_vidstart+0x10;
122	126
	127	offset_ptr = m_vidc_vidstart+m_vidc_vidinit;
	128	if(offset_ptr >= m_vidc_vidend+0x10) // TODO: correct?
	129	offset_ptr = m_vidc_vidstart;
	130
	131	//popmessage("%08x %08x %08x",m_vidc_vidstart,m_vidc_vidinit,m_vidc_vidend);
	132
123	133	for(m_vidc_vidcur = 0;m_vidc_vidcur < size;m_vidc_vidcur++)
124		vram[m_vidc_vidcur] = (space.read_byte(m_vidc_vidstart+m_vidc_vidcur));
	134	{
	135	vram[m_vidc_vidcur] = (space.read_byte(offset_ptr));
	136	offset_ptr++;
	137	if(offset_ptr >= m_vidc_vidend+0x10) // TODO: correct?
	138	offset_ptr = m_vidc_vidstart;
	139	}
125	140
126	141	size = m_vidc_vidend-m_vidc_vidstart+0x10;
127	142
r29505	r29506
129	144	m_cursor_vram[m_vidc_ccur] = (space.read_byte(m_vidc_cinit+m_vidc_ccur));
130	145
131	146	if(m_video_dma_on)
	147	{
132	148	m_vid_timer->adjust(m_screen->time_until_pos(m_vidc_regs[0xb4]));
	149	}
133	150	else
134	151	m_vid_timer->adjust(attotime::never);
135	152	}
r29505	r29506
174	191	372,   356,   340,   324,   308,   292,   276,   260,
175	192	244,   228,   212,   196,   180,   164,   148,   132,
176	193	120,   112,   104,    96,    88,    80,    72,    64,
177		56,    48,    40,    32,    24,    16,     8,     0
	194	56,    48,    40,    32,    24,    16,     8,     0
178	195	};
179	196
180	197	for(ch=0;ch<8;ch++)
r29505	r29506
214	231	{
215	232	case 0:
216	233	case 1:
217		m_timer[tmr]->adjust(attotime::from_usec(m_ioc_timercnt[tmr]/8), tmr); // TODO: ARM timings are quite off there, it should be latch and not latch/8
	234	m_timer[tmr]->adjust(attotime::from_usec(m_ioc_timercnt[tmr]/2), tmr); // TODO: ARM timings are quite off there, it should be latch and not latch/2
218	235	break;
219	236	case 2:
220	237	freq = 1000000.0 / (double)(m_ioc_timercnt[tmr]+1);
r29505	r29506
416	433	static const char *const ioc_regnames[] =
417	434	{
418	435	"(rw) Control",                 // 0
419		"(read) Keyboard receive (write) keyboard send",    // 1
	436	"(read) Keyboard receive (write) keyboard send",    // 4
420	437	"?",
421	438	"?",
422		"(read) IRQ status A",              // 4
423		"(read) IRQ request A (write) IRQ clear",   // 5
424		"(rw) IRQ mask A",              // 6
	439	"(read) IRQ status A",              // 10
	440	"(read) IRQ request A (write) IRQ clear",   // 14
	441	"(rw) IRQ mask A",              // 18
425	442	"?",
426		"(read) IRQ status B",      // 8
427		"(read) IRQ request B",     // 9
428		"(rw) IRQ mask B",      // 10
	443	"(read) IRQ status B",      // 20
	444	"(read) IRQ request B",     // 24
	445	"(rw) IRQ mask B",      // 28
429	446	"?",
430		"(read) FIQ status",        // 12
431		"(read) FIQ request",       // 13
432		"(rw) FIQ mask",        // 14
	447	"(read) FIQ status",        // 30
	448	"(read) FIQ request",       // 34
	449	"(rw) FIQ mask",        // 38
433	450	"?",
434		"(read) Timer 0 count low (write) Timer 0 latch low",       // 16
435		"(read) Timer 0 count high (write) Timer 0 latch high",     // 17
436		"(write) Timer 0 go command",                   // 18
437		"(write) Timer 0 latch command",                // 19
438		"(read) Timer 1 count low (write) Timer 1 latch low",       // 20
439		"(read) Timer 1 count high (write) Timer 1 latch high",     // 21
440		"(write) Timer 1 go command",                   // 22
441		"(write) Timer 1 latch command",                // 23
442		"(read) Timer 2 count low (write) Timer 2 latch low",       // 24
443		"(read) Timer 2 count high (write) Timer 2 latch high",     // 25
444		"(write) Timer 2 go command",                   // 26
445		"(write) Timer 2 latch command",                // 27
446		"(read) Timer 3 count low (write) Timer 3 latch low",       // 28
447		"(read) Timer 3 count high (write) Timer 3 latch high",     // 29
448		"(write) Timer 3 go command",                   // 30
449		"(write) Timer 3 latch command"                 // 31
	451	"(read) Timer 0 count low (write) Timer 0 latch low",       // 40
	452	"(read) Timer 0 count high (write) Timer 0 latch high",     // 44
	453	"(write) Timer 0 go command",                   // 48
	454	"(write) Timer 0 latch command",                // 4c
	455	"(read) Timer 1 count low (write) Timer 1 latch low",       // 50
	456	"(read) Timer 1 count high (write) Timer 1 latch high",     // 54
	457	"(write) Timer 1 go command",                   // 58
	458	"(write) Timer 1 latch command",                // 5c
	459	"(read) Timer 2 count low (write) Timer 2 latch low",       // 60
	460	"(read) Timer 2 count high (write) Timer 2 latch high",     // 64
	461	"(write) Timer 2 go command",                   // 68
	462	"(write) Timer 2 latch command",                // 6c
	463	"(read) Timer 3 count low (write) Timer 3 latch low",       // 70
	464	"(read) Timer 3 count high (write) Timer 3 latch high",     // 74
	465	"(write) Timer 3 go command",                   // 78
	466	"(write) Timer 3 latch command"                 // 7c
450	467	};
451	468
452	469	void archimedes_state::latch_timer_cnt(int tmr)
r29505	r29506
798	815	visarea.max_x = m_vidc_regs[VIDC_HBER] - m_vidc_regs[VIDC_HBSR] - 1;
799	816	visarea.max_y = (m_vidc_regs[VIDC_VBER] - m_vidc_regs[VIDC_VBSR]) * (m_vidc_interlace+1);
800	817
801		logerror("Configuring: htotal %d vtotal %d border %d x %d display %d x %d\n",
802		m_vidc_regs[VIDC_HCR], m_vidc_regs[VIDC_VCR],
803		visarea.max_x, visarea.max_y,
804		m_vidc_regs[VIDC_HDER]-m_vidc_regs[VIDC_HDSR],m_vidc_regs[VIDC_VDER]-m_vidc_regs[VIDC_VDSR]+1);
	818	//logerror("Configuring: htotal %d vtotal %d border %d x %d display %d x %d\n",
	819	//   m_vidc_regs[VIDC_HCR], m_vidc_regs[VIDC_VCR],
	820	//   visarea.max_x, visarea.max_y,
	821	//   m_vidc_regs[VIDC_HDER]-m_vidc_regs[VIDC_HDSR],m_vidc_regs[VIDC_VDER]-m_vidc_regs[VIDC_VDSR]+1);
805	822
806	823	/* FIXME: pixel clock */
807	824	refresh = HZ_TO_ATTOSECONDS(pixel_rate[m_vidc_pixel_clk]*2) * m_vidc_regs[VIDC_HCR] * m_vidc_regs[VIDC_VCR];

branches/new_menus/src/mame/machine/namco51.c

r29505	r29506
350	350	m_in_2(*this),
351	351	m_in_3(*this),
352	352	m_out_0(*this),
353		m_out_1(*this)
	353	m_out_1(*this),
	354	m_lastcoins(0),
	355	m_lastbuttons(0),
	356	m_mode(0),
	357	m_coincred_mode(0),
	358	m_remap_joy(0)
354	359	{
355	360	}
356	361

branches/new_menus/src/mame/machine/namco51.h

r29505	r29506
58	58	devcb2_read8 m_in_3;
59	59	devcb2_write8 m_out_0;
60	60	devcb2_write8 m_out_1;
	61
61	62	INT32 m_lastcoins;
62	63	INT32 m_lastbuttons;
63	64	INT32 m_credits;

branches/new_menus/src/osd/windows/d3dhlsl.c

r29505	r29506
1664	1664	float bloom_height = rt->target_height;
1665	1665	vec2f screendims = d3d->get_dims();
1666	1666	curr_effect->set_vector("ScreenSize", 2, &screendims.c.x);
	1667	float bloom_dims[11][2];
1667	1668	for(; bloom_size >= 2.0f && bloom_index < 11; bloom_size *= 0.5f)
1668	1669	{
1669		target_size[0] = bloom_width;
1670		target_size[1] = bloom_height;
1671		curr_effect->set_vector("TargetSize", 2, target_size);
	1670	bloom_dims[bloom_index][0] = bloom_width;
	1671	bloom_dims[bloom_index][1] = bloom_height;
	1672	curr_effect->set_vector("TargetSize", 2, bloom_dims[bloom_index]);
1672	1673
1673	1674	curr_effect->begin(&num_passes, 0);
1674	1675
r29505	r29506
1698	1699
1699	1700	curr_effect = bloom_effect;
1700	1701
	1702	float target_size[2] = { d3d->get_width(), d3d->get_height() };
	1703	curr_effect->set_vector("TargetSize", 2, target_size);
1701	1704	float weight0123[4] = { options->bloom_level0_weight, options->bloom_level1_weight, options->bloom_level2_weight, options->bloom_level3_weight };
1702	1705	float weight4567[4] = { options->bloom_level4_weight, options->bloom_level5_weight, options->bloom_level6_weight, options->bloom_level7_weight };
1703	1706	float weight89A[3]  = { options->bloom_level8_weight, options->bloom_level9_weight, options->bloom_level10_weight };
1704	1707	curr_effect->set_vector("Level0123Weight", 4, weight0123);
1705	1708	curr_effect->set_vector("Level4567Weight", 4, weight4567);
1706	1709	curr_effect->set_vector("Level89AWeight", 3, weight89A);
1707		curr_effect->set_vector("TargetSize", 2, &screendims.c.x);
	1710	curr_effect->set_vector("Level01Size", 4, bloom_dims[0]);
	1711	curr_effect->set_vector("Level23Size", 4, bloom_dims[2]);
	1712	curr_effect->set_vector("Level45Size", 4, bloom_dims[4]);
	1713	curr_effect->set_vector("Level67Size", 4, bloom_dims[6]);
	1714	curr_effect->set_vector("Level89Size", 4, bloom_dims[8]);
	1715	curr_effect->set_vector("LevelASize", 2, bloom_dims[10]);
1708	1716
1709	1717	curr_effect->set_texture("DiffuseA", rt->render_texture[2]);
1710	1718
r29505	r29506
1846	1854	float bloom_height = rt->target_height;
1847	1855	float screen_size[2] = { d3d->get_width(), d3d->get_height() };
1848	1856	curr_effect->set_vector("ScreenSize", 2, screen_size);
	1857	float bloom_dims[11][2];
1849	1858	for(; bloom_size >= 2.0f && bloom_index < 11; bloom_size *= 0.5f)
1850	1859	{
1851		target_size[0] = bloom_width;
1852		target_size[1] = bloom_height;
1853		curr_effect->set_vector("TargetSize", 2, target_size);
	1860	bloom_dims[bloom_index][0] = bloom_width;
	1861	bloom_dims[bloom_index][1] = bloom_height;
	1862	curr_effect->set_vector("TargetSize", 2, bloom_dims[bloom_index]);
1854	1863
1855	1864	curr_effect->begin(&num_passes, 0);
1856	1865
r29505	r29506
1891	1900	curr_effect->set_vector("Level0123Weight", 4, weight0123);
1892	1901	curr_effect->set_vector("Level4567Weight", 4, weight4567);
1893	1902	curr_effect->set_vector("Level89AWeight", 3, weight89A);
	1903	curr_effect->set_vector("Level01Size", 4, bloom_dims[0]);
	1904	curr_effect->set_vector("Level23Size", 4, bloom_dims[2]);
	1905	curr_effect->set_vector("Level45Size", 4, bloom_dims[4]);
	1906	curr_effect->set_vector("Level67Size", 4, bloom_dims[6]);
	1907	curr_effect->set_vector("Level89Size", 4, bloom_dims[8]);
	1908	curr_effect->set_vector("LevelASize", 2, bloom_dims[10]);
1894	1909
1895	1910	curr_effect->set_texture("DiffuseA", rt->render_texture[0]);
1896	1911
r29505	r29506
3140	3155	m_shader->set_vector("Floor", 3, options->floor);
3141	3156	break;
3142	3157
3143		case CU_BLOOM_TARGET_SIZE:
3144		m_shader->set_vector("TargetSize", 2, shadersys->target_size);
3145		break;
3146	3158	case CU_BLOOM_RESCALE:
3147	3159	m_shader->set_float("BloomRescale", options->raster_bloom_scale);
3148	3160	break;

branches/new_menus/src/osd/windows/d3dhlsl.h

r29505	r29506
88	88	CU_POST_POWER,
89	89	CU_POST_FLOOR,
90	90
91		CU_BLOOM_TARGET_SIZE,
92	91	CU_BLOOM_RESCALE,
93	92	CU_BLOOM_LVL0123_WEIGHTS,
94	93	CU_BLOOM_LVL4567_WEIGHTS,
r29505	r29506
402	401
403	402	texture_info *          curr_texture;
404	403	bool                    phosphor_passthrough;
405		float                   target_size[2];
406	404
407	405	public:
408	406	render_target *         targethead;

branches/new_menus/src/emu/sound.c

r29505	r29506
94	94	m_device.machine().save().save_item("stream", state_tag, outputnum, NAME(m_output[outputnum].m_gain));
95	95	}
96	96
	97	// Mark synchronous streams as such
	98	m_synchronous = m_sample_rate == STREAM_SYNC;
	99	if (m_synchronous)
	100	{
	101	m_sample_rate = 0;
	102	m_sync_timer = m_device.machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sound_stream::sync_update), this));
	103	}
	104	else
	105	m_sync_timer = NULL;
	106
97	107	// force an update to the sample rates; this will cause everything to be recomputed
98	108	// and will generate the initial resample buffers for our inputs
99	109	recompute_sample_rate_data();
r29505	r29506
284	294	}
285	295
286	296
	297	void sound_stream::sync_update(void *, INT32)
	298	{
	299	update();
	300	attotime time = m_device.machine().time();
	301	attoseconds_t next_edge = m_attoseconds_per_sample - (time.attoseconds % m_attoseconds_per_sample);
	302	m_sync_timer->adjust(attotime(0, next_edge));
	303	}
	304
	305
287	306	//-------------------------------------------------
288	307	//  output_since_last_update - return a pointer to
289	308	//  the output buffer and the number of samples
r29505	r29506
447	466
448	467	void sound_stream::recompute_sample_rate_data()
449	468	{
	469	if (m_synchronous)
	470	{
	471	m_sample_rate = 0;
	472	// When synchronous, pick the sample rate for the inputs, if any
	473	for (int inputnum = 0; inputnum < m_input.count(); inputnum++)
	474	{
	475	stream_input &input = m_input[inputnum];
	476	if (input.m_source != NULL)
	477	{
	478	if (!m_sample_rate)
	479	m_sample_rate = input.m_source->m_stream->m_sample_rate;
	480	else if (m_sample_rate != input.m_source->m_stream->m_sample_rate)
	481	throw emu_fatalerror("Incompatible sample rates as input of a synchronous stream: %d and %d\n", m_sample_rate, input.m_source->m_stream->m_sample_rate);
	482	}
	483	}
	484	if (!m_sample_rate)
	485	m_sample_rate = 1000;
	486	}
	487
	488
450	489	// recompute the timing parameters
451	490	attoseconds_t update_attoseconds = m_device.machine().sound().update_attoseconds();
452	491	m_attoseconds_per_sample = ATTOSECONDS_PER_SECOND / m_sample_rate;
r29505	r29506
483	522	assert(input.m_latency_attoseconds < update_attoseconds);
484	523	}
485	524	}
	525
	526	// If synchronous, prime the timer
	527	if (m_synchronous)
	528	{
	529	attotime time = m_device.machine().time();
	530	attoseconds_t next_edge = m_attoseconds_per_sample - (time.attoseconds % m_attoseconds_per_sample);
	531	m_sync_timer->adjust(attotime(0, next_edge));
	532	}
486	533	}
487	534
488	535

branches/new_menus/src/emu/sound.h

r29505	r29506
19	19
20	20
21	21	//**************************************************************************
	22	//  CONSTANTS
	23	//**************************************************************************
	24
	25	const int STREAM_SYNC       = -1;       // special rate value indicating a one-sample-at-a-time stream
	26	// with actual rate defined by its input
	27
	28	//**************************************************************************
22	29	//  MACROS
23	30	//**************************************************************************
24	31
r29505	r29506
133	140	void postload();
134	141	void generate_samples(int samples);
135	142	stream_sample_t *generate_resampled_data(stream_input &input, UINT32 numsamples);
	143	void sync_update(void *, INT32);
136	144
137	145	// linking information
138		device_t &          m_device;               // owning device
139		sound_stream *      m_next;                 // next stream in the chain
	146	device_t &          m_device;                     // owning device
	147	sound_stream *      m_next;                       // next stream in the chain
140	148
141	149	// general information
142		UINT32              m_sample_rate;          // sample rate of this stream
143		UINT32              m_new_sample_rate;      // newly-set sample rate for the stream
	150	UINT32              m_sample_rate;                // sample rate of this stream
	151	UINT32              m_new_sample_rate;            // newly-set sample rate for the stream
	152	bool                m_synchronous;                // synchronous stream that runs at the rate of its input
144	153
145	154	// timing information
146		attoseconds_t       m_attoseconds_per_sample;// number of attoseconds per sample
147		INT32               m_max_samples_per_update;// maximum samples per update
	155	attoseconds_t       m_attoseconds_per_sample;     // number of attoseconds per sample
	156	INT32               m_max_samples_per_update;     // maximum samples per update
	157	emu_timer *         m_sync_timer;                 // update timer for synchronous streams
148	158
149	159	// input information
150		dynamic_array<stream_input> m_input;        // list of streams we directly depend upon
151		dynamic_array<stream_sample_t *> m_input_array; // array of inputs for passing to the callback
	160	dynamic_array<stream_input> m_input;              // list of streams we directly depend upon
	161	dynamic_array<stream_sample_t *> m_input_array;   // array of inputs for passing to the callback
152	162
153	163	// resample buffer information
154		UINT32              m_resample_bufalloc;    // allocated size of each resample buffer
	164	UINT32              m_resample_bufalloc;          // allocated size of each resample buffer
155	165
156	166	// output information
157		dynamic_array<stream_output> m_output;      // list of streams which directly depend upon us
158		dynamic_array<stream_sample_t *> m_output_array; // array of outputs for passing to the callback
	167	dynamic_array<stream_output> m_output;            // list of streams which directly depend upon us
	168	dynamic_array<stream_sample_t *> m_output_array;  // array of outputs for passing to the callback
159	169
160	170	// output buffer information
161		UINT32              m_output_bufalloc;      // allocated size of each output buffer
162		INT32               m_output_sampindex;     // current position within each output buffer
163		INT32               m_output_update_sampindex;// position at time of last global update
164		INT32               m_output_base_sampindex;// sample at base of buffer, relative to the current emulated second
	171	UINT32              m_output_bufalloc;            // allocated size of each output buffer
	172	INT32               m_output_sampindex;           // current position within each output buffer
	173	INT32               m_output_update_sampindex;    // position at time of last global update
	174	INT32               m_output_base_sampindex;      // sample at base of buffer, relative to the current emulated second
165	175
166	176	// callback information
167		stream_update_func  m_callback;             // callback function
168		void *              m_param;                // callback function parameter
	177	stream_update_func  m_callback;                   // callback function
	178	void *              m_param;                      // callback function parameter
169	179	};
170	180
171	181

branches/new_menus/src/emu/cpu/tms7000/tms7000.h

r29505	r29506
92	92	static const opcode_func s_opfn_exl[0x100];
93	93	const opcode_func *m_opcode;
94	94
95		static UINT16 bcd_add( UINT16 a, UINT16 b );
96		static UINT16 bcd_tencomp( UINT16 a );
97		static UINT16 bcd_sub( UINT16 a, UINT16 b);
	95	inline UINT8 bcd_add( UINT8 a, UINT8 b, UINT8 c );
	96	inline UINT8 bcd_sub( UINT8 a, UINT8 b, UINT8 c );
98	97
99		PAIR        m_pc;         /* Program counter */
100		UINT8       m_sp;     /* Stack Pointer */
101		UINT8       m_sr;     /* Status Register */
102		UINT8       m_irq_state[3];   /* State of the three IRQs */
103		UINT8       m_rf[0x80];   /* Register file (SJE) */
104		UINT8       m_pf[0x100];  /* Perpherial file */
105		address_space *m_program;
106		direct_read_data *m_direct;
107		address_space *m_io;
	98	PAIR        m_pc;               /* Program counter */
	99	UINT8       m_sp;               /* Stack Pointer */
	100	UINT8       m_sr;               /* Status Register */
	101	UINT8       m_irq_state[3];     /* State of the three IRQs */
	102	UINT8       m_rf[0x80];         /* Register file (SJE) */
	103	UINT8       m_pf[0x100];        /* Perpherial file */
	104
108	105	int         m_icount;
109	106	int         m_div_by_16_trigger;
110	107	int         m_cycles_per_INT2;
111	108	UINT8       m_t1_capture_latch; /* Timer 1 capture latch */
112		INT8        m_t1_prescaler;   /* Timer 1 prescaler (5 bits) */
113		INT16       m_t1_decrementer; /* Timer 1 decrementer (8 bits) */
114		UINT8       m_idle_state; /* Set after the execution of an idle instruction */
	109	INT8        m_t1_prescaler;     /* Timer 1 prescaler (5 bits) */
	110	INT16       m_t1_decrementer;   /* Timer 1 decrementer (8 bits) */
	111	UINT8       m_idle_state;       /* Set after the execution of an idle instruction */
115	112
	113	address_space *m_program;
	114	direct_read_data *m_direct;
	115	address_space *m_io;
	116
116	117	inline UINT16 RM16( UINT32 mAddr );
117	118	inline UINT16 RRF16( UINT32 mAddr );
118	119	inline void WRF16( UINT32 mAddr, PAIR p );
	120
119	121	void tms7000_check_IRQ_lines();
120	122	void tms7000_do_interrupt( UINT16 address, UINT8 line );
121	123	void illegal();
r29505	r29506
348	350	void xorp_b2p();
349	351	void xorp_i2p();
350	352	void tms7000_service_timer1();
351
352	353	};
353	354
354	355

branches/new_menus/src/emu/cpu/tms7000/tms70op.inc

r29505	r29506
1292	1292
1293	1293	void tms7000_device::dac_b2a()
1294	1294	{
1295		UINT16  t;
	1295	WRA(bcd_add(RDA, RDB, pSR & SR_C));
1296	1296
1297		t = bcd_add( RDA, RDB );
1298
1299		if (pSR & SR_C)
1300		t = bcd_add( t, 1 );
1301
1302		WRA(t);
1303
1304		CLR_NZC;
1305		SET_C8(t);
1306		SET_N8(t);
1307		SET_Z8(t);
1308
1309	1297	m_icount -= 7;
1310	1298	}
1311	1299
1312	1300	void tms7000_device::dac_r2a()
1313	1301	{
1314		UINT8   r;
1315		UINT16  t;
1316
	1302	UINT8 r;
1317	1303	IMMBYTE(r);
1318	1304
1319		t = bcd_add( RDA, RM(r) );
	1305	WRA(bcd_add(RDA, RM(r), pSR & SR_C));
1320	1306
1321		if (pSR & SR_C)
1322		t = bcd_add( t, 1 );
1323
1324		WRA(t);
1325
1326		CLR_NZC;
1327		SET_C8(t);
1328		SET_N8(t);
1329		SET_Z8(t);
1330
1331	1307	m_icount -= 10;
1332	1308	}
1333	1309
1334	1310	void tms7000_device::dac_r2b()
1335	1311	{
1336		UINT8   r;
1337		UINT16  t;
1338
	1312	UINT8 r;
1339	1313	IMMBYTE(r);
1340	1314
1341		t = bcd_add( RDB, RM(r) );
	1315	WRB(bcd_add(RDB, RM(r), pSR & SR_C));
1342	1316
1343		if (pSR & SR_C)
1344		t = bcd_add( t, 1 );
1345
1346		WRB(t);
1347
1348		CLR_NZC;
1349		SET_C8(t);
1350		SET_N8(t);
1351		SET_Z8(t);
1352
1353	1317	m_icount -= 10;
1354	1318	}
1355	1319
1356	1320	void tms7000_device::dac_r2r()
1357	1321	{
1358		UINT8   r,s;
1359		UINT16  t;
1360
	1322	UINT8 s, r;
1361	1323	IMMBYTE(s);
1362	1324	IMMBYTE(r);
1363	1325
1364		t = bcd_add( RM(s), RM(r) );
	1326	WM(r, bcd_add(RM(s), RM(r), pSR & SR_C));
1365	1327
1366		if (pSR & SR_C)
1367		t = bcd_add( t, 1 );
1368
1369		WM(r,t);
1370
1371		CLR_NZC;
1372		SET_C8(t);
1373		SET_N8(t);
1374		SET_Z8(t);
1375
1376	1328	m_icount -= 12;
1377	1329	}
1378	1330
1379	1331	void tms7000_device::dac_i2a()
1380	1332	{
1381		UINT8   i;
1382		UINT16  t;
1383
	1333	UINT8 i;
1384	1334	IMMBYTE(i);
1385	1335
1386		t = bcd_add( i, RDA );
	1336	WRA(bcd_add(i, RDA, pSR & SR_C));
1387	1337
1388		if (pSR & SR_C)
1389		t = bcd_add( t, 1 );
1390
1391		WRA(t);
1392
1393		CLR_NZC;
1394		SET_C8(t);
1395		SET_N8(t);
1396		SET_Z8(t);
1397
1398	1338	m_icount -= 9;
1399	1339	}
1400	1340
1401	1341	void tms7000_device::dac_i2b()
1402	1342	{
1403		UINT8   i;
1404		UINT16  t;
1405
	1343	UINT8 i;
1406	1344	IMMBYTE(i);
1407	1345
1408		t = bcd_add( i, RDB );
	1346	WRB(bcd_add(i, RDB, pSR & SR_C));
1409	1347
1410		if (pSR & SR_C)
1411		t = bcd_add( t, 1 );
1412
1413		WRB(t);
1414
1415		CLR_NZC;
1416		SET_C8(t);
1417		SET_N8(t);
1418		SET_Z8(t);
1419
1420	1348	m_icount -= 9;
1421	1349	}
1422	1350
1423	1351	void tms7000_device::dac_i2r()
1424	1352	{
1425		UINT8   i,r;
1426		UINT16  t;
1427
	1353	UINT8 i, r;
1428	1354	IMMBYTE(i);
1429	1355	IMMBYTE(r);
1430	1356
1431		t = bcd_add( i, RM(r) );
	1357	WM(r, bcd_add(i, RM(r), pSR & SR_C));
1432	1358
1433		if (pSR & SR_C)
1434		t = bcd_add( t, 1 );
1435
1436		WM(r,t);
1437
1438		CLR_NZC;
1439		SET_C8(t);
1440		SET_N8(t);
1441		SET_Z8(t);
1442
1443	1359	m_icount -= 11;
1444	1360	}
1445	1361
r29505	r29506
1642	1558
1643	1559	void tms7000_device::dsb_b2a()
1644	1560	{
1645		UINT16  t;
	1561	WRA(bcd_sub(RDA, RDB, pSR & SR_C));
1646	1562
1647		t = bcd_sub( RDA, RDB );
1648
1649		if( !(pSR & SR_C) )
1650		t = bcd_sub( t, 1 );
1651
1652		WRA(t);
1653
1654		CLR_NZC;
1655		SET_C8(~t);
1656		SET_N8(t);
1657		SET_Z8(t);
1658
1659	1563	m_icount -= 7;
1660	1564	}
1661	1565
1662	1566	void tms7000_device::dsb_r2a()
1663	1567	{
1664		UINT8   r;
1665		UINT16  t;
1666
	1568	UINT8 r;
1667	1569	IMMBYTE(r);
1668	1570
1669		t = bcd_sub( RDA, RM(r) );
	1571	WRA(bcd_sub(RDA, RM(r), pSR & SR_C));
1670	1572
1671		if( !(pSR & SR_C) )
1672		t = bcd_sub( t, 1 );
1673
1674		WRA(t);
1675
1676		CLR_NZC;
1677		SET_C8(~t);
1678		SET_N8(t);
1679		SET_Z8(t);
1680
1681	1573	m_icount -= 10;
1682	1574	}
1683	1575
1684	1576	void tms7000_device::dsb_r2b()
1685	1577	{
1686		UINT8   r;
1687		UINT16  t;
1688
	1578	UINT8 r;
1689	1579	IMMBYTE(r);
1690	1580
1691		t = bcd_sub( RDB, RM(r) );
	1581	WRB(bcd_sub(RDB, RM(r), pSR & SR_C));
1692	1582
1693		if( !(pSR & SR_C) )
1694		t = bcd_sub( t, 1 );
1695
1696		WRB(t);
1697
1698		CLR_NZC;
1699		SET_C8(~t);
1700		SET_N8(t);
1701		SET_Z8(t);
1702
1703	1583	m_icount -= 10;
1704	1584	}
1705	1585
1706	1586	void tms7000_device::dsb_r2r()
1707	1587	{
1708		UINT8   r,s;
1709		UINT16  t;
1710
	1588	UINT8 s, r;
1711	1589	IMMBYTE(s);
1712	1590	IMMBYTE(r);
1713	1591
1714		t = bcd_sub( RM(s), RM(r) );
	1592	WM(r, bcd_sub(RM(s), RM(r), pSR & SR_C));
1715	1593
1716		if( !(pSR & SR_C) )
1717		t = bcd_sub( t, 1 );
1718
1719		WM(r,t);
1720
1721		CLR_NZC;
1722		SET_C8(~t);
1723		SET_N8(t);
1724		SET_Z8(t);
1725
1726	1594	m_icount -= 12;
1727	1595	}
1728	1596
1729	1597	void tms7000_device::dsb_i2a()
1730	1598	{
1731		UINT8   i;
1732		UINT16  t;
1733
	1599	UINT8 i;
1734	1600	IMMBYTE(i);
1735	1601
1736		t = bcd_sub( RDA, i );
	1602	WRA(bcd_sub(RDA, i, pSR & SR_C));
1737	1603
1738		if( !(pSR & SR_C) )
1739		t = bcd_sub( t, 1 );
1740
1741		WRA(t);
1742
1743		CLR_NZC;
1744		SET_C8(~t);
1745		SET_N8(t);
1746		SET_Z8(t);
1747
1748	1604	m_icount -= 9;
1749	1605	}
1750	1606
1751	1607	void tms7000_device::dsb_i2b()
1752	1608	{
1753		UINT8   i;
1754		UINT16  t;
1755
	1609	UINT8 i;
1756	1610	IMMBYTE(i);
1757	1611
1758		t = bcd_sub( RDB, i );
	1612	WRB(bcd_sub(RDB, i, pSR & SR_C));
1759	1613
1760		if( !(pSR & SR_C) )
1761		t = bcd_sub( t, 1 );
1762
1763		WRB(t);
1764
1765		CLR_NZC;
1766		SET_C8(~t);
1767		SET_N8(t);
1768		SET_Z8(t);
1769
1770	1614	m_icount -= 9;
1771	1615	}
1772	1616
1773	1617	void tms7000_device::dsb_i2r()
1774	1618	{
1775		UINT8   r,i;
1776		UINT16  t;
1777
	1619	UINT8 i, r;
1778	1620	IMMBYTE(i);
1779	1621	IMMBYTE(r);
1780	1622
1781		t = bcd_sub( RM(r), i );
	1623	WM(r, bcd_sub(RM(r), i, pSR & SR_C));
1782	1624
1783		if( !(pSR & SR_C) )
1784		t = bcd_sub( t, 1 );
1785
1786		WM(r,t);
1787
1788		CLR_NZC;
1789		SET_C8(~t);
1790		SET_N8(t);
1791		SET_Z8(t);
1792
1793	1625	m_icount -= 11;
1794	1626	}
1795	1627

branches/new_menus/src/emu/cpu/tms7000/tms7000.c

r29505	r29506
57	57
58	58
59	59	static ADDRESS_MAP_START(tms7000_mem, AS_PROGRAM, 8, tms7000_device )
60		AM_RANGE(0x0000, 0x007f)    AM_READWRITE(tms7000_internal_r, tms7000_internal_w) /* tms7000 internal RAM */
61		AM_RANGE(0x0080, 0x00ff)    AM_NOP                      /* reserved */
62		AM_RANGE(0x0100, 0x01ff)    AM_READWRITE(tms70x0_pf_r, tms70x0_pf_w)             /* tms7000 internal I/O ports */
	60	AM_RANGE(0x0000, 0x007f) AM_READWRITE(tms7000_internal_r, tms7000_internal_w) /* tms7000 internal RAM */
	61	AM_RANGE(0x0080, 0x00ff) AM_NOP                                               /* reserved */
	62	AM_RANGE(0x0100, 0x01ff) AM_READWRITE(tms70x0_pf_r, tms70x0_pf_w)             /* tms7000 internal I/O ports */
63	63	ADDRESS_MAP_END
64	64
65	65
r29505	r29506
133	133	return result | RM((mAddr+1)&0xffff);
134	134	}
135	135
136		UINT16 tms7000_device::RRF16( UINT32 mAddr )    /*Read register file (16 bit) */
	136	UINT16 tms7000_device::RRF16( UINT32 mAddr ) /* Read register file (16 bit) */
137	137	{
138	138	PAIR result;
139	139	result.b.h = RM((mAddr-1)&0xffff);
r29505	r29506
141	141	return result.w.l;
142	142	}
143	143
144		void tms7000_device::WRF16( UINT32 mAddr, PAIR p ) /*Write register file (16 bit) */
	144	void tms7000_device::WRF16( UINT32 mAddr, PAIR p ) /* Write register file (16 bit) */
145	145	{
146	146	WM( (mAddr-1)&0xffff, p.b.h );
147	147	WM( mAddr, p.b.l );
r29505	r29506
527	527	}
528	528
529	529	// BCD arthrimetic handling
530		UINT16 tms7000_device::bcd_add( UINT16 a, UINT16 b )
	530	static const UINT8 lut_bcd_out[6] = { 0x00, 0x06, 0x00, 0x66, 0x60, 0x66 };
	531
	532	inline UINT8 tms7000_device::bcd_add( UINT8 a, UINT8 b, UINT8 c )
531	533	{
532		UINT16  t1,t2,t3,t4,t5,t6;
	534	c = (c != 0) ? 1 : 0;
533	535
534		/* Sure it is a lot of code, but it works! */
535		t1 = a + 0x0666;
536		t2 = t1 + b;
537		t3 = t1 ^ b;
538		t4 = t2 ^ t3;
539		t5 = ~t4 & 0x1110;
540		t6 = (t5 >> 2) | (t5 >> 3);
541		return t2-t6;
	536	UINT8 h1 = a >> 4 & 0xf;
	537	UINT8 l1 = a >> 0 & 0xf;
	538	UINT8 h2 = b >> 4 & 0xf;
	539	UINT8 l2 = b >> 0 & 0xf;
	540
	541	// compute bcd constant
	542	UINT8 d = ((l1 + l2 + c) < 10) ? 0 : 1;
	543	if ((h1 + h2) == 9)
	544	d |= 2;
	545	else if ((h1 + h2) > 9)
	546	d |= 4;
	547
	548	UINT8 ret = a + b + c + lut_bcd_out[d];
	549
	550	CLR_NZC;
	551	SET_N8(ret);
	552	SET_Z8(ret);
	553
	554	if (d > 2)
	555	pSR |= SR_C;
	556
	557	return ret;
542	558	}
543	559
544		UINT16 tms7000_device::bcd_tencomp( UINT16 a )
	560	inline UINT8 tms7000_device::bcd_sub( UINT8 a, UINT8 b, UINT8 c )
545	561	{
546		UINT16  t1,t2,t3,t4,t5,t6;
	562	c = (c != 0) ? 0 : 1;
547	563
548		t1 = 0xffff - a;
549		t2 = -a;
550		t3 = t1 ^ 0x0001;
551		t4 = t2 ^ t3;
552		t5 = ~t4 & 0x1110;
553		t6 = (t5 >> 2)|(t5>>3);
554		return t2-t6;
555		}
	564	UINT8 h1 = a >> 4 & 0xf;
	565	UINT8 l1 = a >> 0 & 0xf;
	566	UINT8 h2 = b >> 4 & 0xf;
	567	UINT8 l2 = b >> 0 & 0xf;
556	568
557		/*
558		Compute difference a-b???
559		*/
560		UINT16 tms7000_device::bcd_sub( UINT16 a, UINT16 b)
561		{
562		//return bcd_tencomp(b) - bcd_tencomp(a);
563		return bcd_add(a, bcd_tencomp(b) & 0xff);
	569	// compute bcd constant
	570	UINT8 d = ((l1 - c) >= l2) ? 0 : 1;
	571	if (h1 == h2)
	572	d |= 2;
	573	else if (h1 < h2)
	574	d |= 4;
	575
	576	UINT8 ret = a - b - c - lut_bcd_out[d];
	577
	578	CLR_NZC;
	579	SET_N8(ret);
	580	SET_Z8(ret);
	581
	582	if (d > 2)
	583	pSR |= SR_C;
	584
	585	return ret;
564	586	}
565	587
566	588	WRITE8_MEMBER( tms7000_device::tms7000_internal_w )

branches/new_menus/src/emu/cpu/tms57002/tms57002.c

r29505	r29506
22	22
23	23	tms57002_device::tms57002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
24	24	: cpu_device(mconfig, TMS57002, "TMS57002", tag, owner, clock, "tms57002", __FILE__),
25		program_config("program", ENDIANNESS_LITTLE, 32, 8, -2, ADDRESS_MAP_NAME(internal_pgm)),
26		data_config("data", ENDIANNESS_LITTLE, 8, 20)
	25	device_sound_interface(mconfig, *this),
	26	program_config("program", ENDIANNESS_LITTLE, 32, 8, -2, ADDRESS_MAP_NAME(internal_pgm)),
	27	data_config("data", ENDIANNESS_LITTLE, 8, 20)
27	28	{
28	29	}
29	30
r29505	r29506
211	212	if(st0 & ST0_WORD) {
212	213	if(st0 & ST0_SEL) {
213	214	int off = 16 - ((adr & 3) << 3);
214		xrd = (xrd & ~(0xff << off)) | (v << off);
	215	txrd = (txrd & ~(0xff << off)) | (v << off);
215	216	done = off == 0;
216	217	} else {
217	218	int off = 20 - ((adr & 7) << 2);
218		xrd = (xrd & ~(0xf << off)) | ((v & 0xf) << off);
	219	txrd = (txrd & ~(0xf << off)) | ((v & 0xf) << off);
219	220	done = off == 0;
220	221	}
221	222	} else {
222	223	if(st0 & ST0_SEL) {
223	224	int off = 16 - ((adr & 1) << 3);
224		xrd = (xrd & ~(0xff << off)) | (v << off);
	225	txrd = (txrd & ~(0xff << off)) | (v << off);
225	226	done = off == 8;
226	227	if(done)
227		xrd &= 0xffff00;
	228	txrd &= 0xffff00;
228	229	} else {
229	230	int off = 20 - ((adr & 3) << 2);
230		xrd = (xrd & ~(0xf << off)) | ((v & 0xf) << off);
	231	txrd = (txrd & ~(0xf << off)) | ((v & 0xf) << off);
231	232	done = off == 8;
232	233	if(done)
233		xrd &= 0xffff00;
	234	txrd &= 0xffff00;
234	235	}
235	236	}
236	237	if(done) {
	238	xrd = txrd;
237	239	sti &= ~S_READ;
238	240	xm_adr = 0;
239	241	} else
r29505	r29506
782	784	icount = 0;
783	785	}
784	786
	787	void tms57002_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
	788	{
	789	assert(samples == 1);
	790
	791	if(st0 & ST0_SIM) {
	792	si[0] = (inputs[0][0] << 8) & 0xffffff;
	793	si[1] = (inputs[1][0] << 8) & 0xffffff;
	794	si[2] = (inputs[2][0] << 8) & 0xffffff;
	795	si[3] = (inputs[3][0] << 8) & 0xffffff;
	796	} else {
	797	si[0] = inputs[0][0] & 0xffffff;
	798	si[1] = inputs[1][0] & 0xffffff;
	799	si[2] = inputs[2][0] & 0xffffff;
	800	si[3] = inputs[3][0] & 0xffffff;
	801	}
	802	outputs[0][0] = INT16(so[0] >> 8);
	803	outputs[1][0] = INT16(so[1] >> 8);
	804	outputs[2][0] = INT16(so[2] >> 8);
	805	outputs[3][0] = INT16(so[3] >> 8);
	806
	807	sync_w(1);
	808	}
	809
785	810	void tms57002_device::device_start()
786	811	{
787	812	sti = S_IDLE;
r29505	r29506
812	837
813	838	m_icountptr = &icount;
814	839
	840	stream_alloc(4, 4, STREAM_SYNC);
	841
815	842	save_item(NAME(macc));
816	843
817	844	save_item(NAME(cmem));
r29505	r29506
829	856	save_item(NAME(xba));
830	857	save_item(NAME(xwr));
831	858	save_item(NAME(xrd));
	859	save_item(NAME(txrd));
832	860	save_item(NAME(creg));
833	861
834	862	save_item(NAME(pc));

branches/new_menus/src/emu/cpu/tms57002/tms57002.h

r29505	r29506
12	12	#ifndef __TMS57002_H__
13	13	#define __TMS57002_H__
14	14
15		class tms57002_device : public cpu_device {
	15	class tms57002_device : public cpu_device, public device_sound_interface {
16	16	public:
17	17	tms57002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
18	18
r29505	r29506
29	29	protected:
30	30	virtual void device_start();
31	31	virtual void device_reset();
	32	virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
32	33	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
33	34	virtual UINT32 execute_min_cycles() const;
34	35	virtual UINT32 execute_max_cycles() const;
r29505	r29506
126	127	UINT32 si[4], so[4];
127	128
128	129	UINT32 st0, st1, sti;
129		UINT32 aacc, xoa, xba, xwr, xrd, creg;
	130	UINT32 aacc, xoa, xba, xwr, xrd, txrd, creg;
130	131
131	132	UINT8 pc, hpc, ca, id, ba0, ba1, rptc, rptc_next, sa;
132	133

branches/new_menus/src/emu/dimemory.c

r29505	r29506
293	293	}
294	294
295	295	// if this entry references a memory region, validate it
296		if (entry->m_region != NULL && entry->m_share == 0)
	296	if (entry->m_region != NULL && entry->m_sharetag == 0)
297	297	{
298	298	// make sure we can resolve the full path to the region
299	299	bool found = false;
r29505	r29506
346	346	valid.validate_tag(entry->m_read.m_tag);
347	347	if (entry->m_write.m_type == AMH_BANK)
348	348	valid.validate_tag(entry->m_write.m_tag);
349		if (entry->m_share != NULL)
350		valid.validate_tag(entry->m_share);
	349	if (entry->m_sharetag != NULL)
	350	valid.validate_tag(entry->m_sharetag);
351	351	}
352	352
353	353	// release the address map

branches/new_menus/src/emu/addrmap.c

r29505	r29506
26	26	m_addrend((map.m_globalmask == 0) ? end : end & map.m_globalmask),
27	27	m_addrmirror(0),
28	28	m_addrmask(0),
29		m_share(NULL),
	29	m_sharebase(NULL),
	30	m_sharetag(NULL),
30	31	m_region(NULL),
31	32	m_rgnoffs(0),
32	33	m_rspace8(NULL),

branches/new_menus/src/emu/addrmap.h

r29505	r29506
83	83	void set_read_type(map_handler_type _type) { m_read.m_type = _type; }
84	84	void set_write_type(map_handler_type _type) { m_write.m_type = _type; }
85	85	void set_region(const char *tag, offs_t offset) { m_region = tag; m_rgnoffs = offset; }
86		void set_share(const char *tag) { assert(m_share == NULL); m_share = tag; }
	86	void set_share(device_t &device, const char *tag) { assert(m_sharetag == NULL); m_sharebase = &device; m_sharetag = tag; }
87	87
88	88	// mask setting
89	89	void set_mask(offs_t _mask);
r29505	r29506
117	117	map_handler_data        m_read;                 // data for read handler
118	118	map_handler_data        m_write;                // data for write handler
119	119	map_handler_data        m_setoffsethd;          // data for setoffset handler
120		const char *            m_share;                // tag of a shared memory block
	120	device_t *              m_sharebase;            // pointer to the base device for the share tag
	121	const char *            m_sharetag;             // tag of a shared memory block
121	122	const char *            m_region;               // tag of region containing the memory backing this entry
122	123	offs_t                  m_rgnoffs;              // offset within the region
123	124
r29505	r29506
566	567	#define AM_REGION(_tag, _offs) \
567	568	curentry->set_region(_tag, _offs);
568	569	#define AM_SHARE(_tag) \
569		curentry->set_share(_tag);
	570	curentry->set_share(device, _tag);
570	571
571	572	// common shortcuts
572	573	#define AM_ROMBANK(_bank)                   AM_READ_BANK(_bank)

branches/new_menus/src/emu/device.h

r29505	r29506
322	322	template<class _InterfaceClass> bool next(_InterfaceClass *&intf) const { return m_device.next(intf); }
323	323
324	324	// optional operation overrides
	325	//
	326	// WARNING: interface_pre_start must be callable multiple times in
	327	// case another interface throws a missing dependency.  In
	328	// particular, state saving registrations should be done in post.
325	329	virtual void interface_config_complete();
326	330	virtual void interface_validity_check(validity_checker &valid) const;
327	331	virtual void interface_pre_start();

branches/new_menus/src/emu/bus/pce/pce_slot.h

r29505	r29506
30	30	virtual DECLARE_READ8_MEMBER(read_cart) { return 0xff; }
31	31	virtual DECLARE_WRITE8_MEMBER(write_cart) {};
32	32
33		void rom_alloc(running_machine &machine, UINT32 size);
34		void ram_alloc(running_machine &machine, UINT32 size);
	33	void rom_alloc(UINT32 size);
	34	void ram_alloc(UINT32 size);
35	35	UINT8* get_rom_base() { return m_rom; }
36	36	UINT8* get_ram_base() { return m_ram; }
37		UINT32 get_rom_size() { return m_rom_size; }
38		UINT32 get_ram_size() { return m_ram_size; }
	37	UINT32 get_rom_size() { return m_rom.count(); }
	38	UINT32 get_ram_size() { return m_ram.count(); }
39	39
40	40	// internal state
41		UINT8 *m_rom;
42		UINT8 *m_ram;
43		UINT32 m_rom_size;
44		UINT32 m_ram_size;
	41	dynamic_buffer m_rom;
	42	dynamic_buffer m_ram;
45	43
46	44	void rom_map_setup(UINT32 size);
47	45

branches/new_menus/src/emu/bus/pce/pce_slot.c

r29505	r29506
25	25	//-------------------------------------------------
26	26
27	27	device_pce_cart_interface::device_pce_cart_interface(const machine_config &mconfig, device_t &device)
28		: device_slot_card_interface(mconfig, device),
29		m_rom(NULL),
30		m_ram(NULL),
31		m_rom_size(0),
32		m_ram_size(0)
	28	: device_slot_card_interface(mconfig, device)
33	29	{
34	30	}
35	31
r29505	r29506
46	42	//  rom_alloc - alloc the space for the cart
47	43	//-------------------------------------------------
48	44
49		void device_pce_cart_interface::rom_alloc(running_machine &machine, UINT32 size)
	45	void device_pce_cart_interface::rom_alloc(UINT32 size)
50	46	{
51	47	if (m_rom == NULL)
52		{
53		m_rom = auto_alloc_array_clear(machine, UINT8, size);
54		m_rom_size = size;
55		}
	48	m_rom.resize(size);
56	49	}
57	50
58	51
r29505	r29506
60	53	//  ram_alloc - alloc the space for the ram
61	54	//-------------------------------------------------
62	55
63		void device_pce_cart_interface::ram_alloc(running_machine &machine, UINT32 size)
	56	void device_pce_cart_interface::ram_alloc(UINT32 size)
64	57	{
65	58	if (m_ram == NULL)
66	59	{
67		m_ram = auto_alloc_array_clear(machine, UINT8, size);
68		m_ram_size = size;
69		state_save_register_item_pointer(machine, "PCE_CART", this->device().tag(), 0, m_ram, m_ram_size);
	60	m_ram.resize(size);
	61	device().save_item(NAME(m_ram));
70	62	}
71	63	}
72	64
r29505	r29506
228	220	fseek(offset, SEEK_SET);
229	221	}
230	222
231		m_cart->rom_alloc(machine(), len);
	223	m_cart->rom_alloc(len);
232	224	ROM = m_cart->get_rom_base();
233	225
234	226	if (software_entry() == NULL)
r29505	r29506
263	255	//printf("Type: %s\n", pce_get_slot(m_type));
264	256
265	257	if (m_type == PCE_POPULOUS)
266		m_cart->ram_alloc(machine(), 0x8000);
	258	m_cart->ram_alloc(0x8000);
267	259	if (m_type == PCE_CDSYS3J || m_type == PCE_CDSYS3U)
268		m_cart->ram_alloc(machine(), 0x30000);
	260	m_cart->ram_alloc(0x30000);
269	261
270	262	return IMAGE_INIT_PASS;
271	263	}

branches/new_menus/src/emu/bus/sega8/rom.c

r29505	r29506
329	329	int bank = offset / 0x4000;
330	330
331	331	if (bank == 2 && m_ram && m_ram_enabled)
332		return m_ram[(m_ram_base * 0x4000 + (offset & 0x3fff)) % m_ram_size];
	332	return m_ram[(m_ram_base * 0x4000 + (offset & 0x3fff)) % m_ram.count()];
333	333
334	334	if (offset < 0x400) // first 1k is hardcoded
335	335	return m_rom[offset];
r29505	r29506
342	342	int bank = offset / 0x4000;
343	343
344	344	if (bank == 2 && m_ram && m_ram_enabled)
345		m_ram[(m_ram_base * 0x4000 + (offset & 0x3fff)) % m_ram_size] = data;
	345	m_ram[(m_ram_base * 0x4000 + (offset & 0x3fff)) % m_ram.count()] = data;
346	346	}
347	347
348	348	WRITE8_MEMBER(sega8_rom_device::write_mapper)
r29505	r29506
422	422	if (offset >= 0x8000 && offset < 0xa000)
423	423	return m_ram[offset & 0x7ff];
424	424
425		return m_rom[offset % m_rom_size];
	425	return m_rom[offset % m_rom.count()];
426	426	}
427	427
428	428	WRITE8_MEMBER(sega8_othello_device::write_cart)
r29505	r29506
446	446	if (offset >= 0x8000 && offset < 0xa000)
447	447	return m_ram[offset & 0x1fff];
448	448
449		return m_rom[offset % m_rom_size];
	449	return m_rom[offset % m_rom.count()];
450	450	}
451	451
452	452	WRITE8_MEMBER(sega8_castle_device::write_cart)
r29505	r29506
470	470	if (offset >= 0x8000)
471	471	return m_ram[offset & 0x3fff];
472	472
473		return m_rom[offset % m_rom_size];
	473	return m_rom[offset % m_rom.count()];
474	474	}
475	475
476	476	WRITE8_MEMBER(sega8_basic_l3_device::write_cart)
r29505	r29506
504	504	if (offset >= 0x8000 && offset < 0xa000)
505	505	return m_ram[offset & 0x1fff];
506	506
507		return m_rom[offset % m_rom_size];
	507	return m_rom[offset % m_rom.count()];
508	508	}
509	509
510	510	WRITE8_MEMBER(sega8_music_editor_device::write_cart)
r29505	r29506
623	623	if (offset >= 0x2000 && offset < 0x4000)
624	624	return m_ram[offset & 0x1fff];
625	625
626		return m_rom[offset % m_rom_size];
	626	return m_rom[offset % m_rom.count()];
627	627	}
628	628
629	629	WRITE8_MEMBER(sega8_dahjee_typea_device::write_cart)
r29505	r29506
651	651	// TYPE B
652	652	READ8_MEMBER(sega8_dahjee_typeb_device::read_cart)
653	653	{
654		return m_rom[offset % m_rom_size];
	654	return m_rom[offset % m_rom.count()];
655	655	}
656	656
657	657	READ8_MEMBER(sega8_dahjee_typeb_device::read_ram)
r29505	r29506
750	750	int bank = offset / 0x2000;
751	751
752	752	if (bank == 5 && m_ram && m_ram_enabled)
753		return m_ram[(m_ram_base * 0x2000 + (offset & 0x1fff)) % m_ram_size];
	753	return m_ram[(m_ram_base * 0x2000 + (offset & 0x1fff)) % m_ram.count()];
754	754
755	755	return m_rom[m_rom_bank_base[bank/2] * 0x4000 + (offset & 0x3fff)];
756	756	}
r29505	r29506
782	782	}
783	783
784	784	if (bank == 5 && m_ram && m_ram_enabled)
785		m_ram[(m_ram_base * 0x2000 + (offset & 0x1fff)) % m_ram_size] = data;
	785	m_ram[(m_ram_base * 0x2000 + (offset & 0x1fff)) % m_ram.count()] = data;
786	786	}
787	787
788	788	/*-------------------------------------------------
r29505	r29506
824	824	int bank = offset / 0x2000;
825	825
826	826	if (bank >= 4 && m_ram && m_ram_enabled)
827		return m_ram[(m_ram_base * 0x2000 + (offset & 0x1fff)) % m_ram_size];
	827	return m_ram[(m_ram_base * 0x2000 + (offset & 0x1fff)) % m_ram.count()];
828	828
829	829	return m_rom[m_rom_bank_base[bank] * 0x2000 + (offset & 0x1fff)];
830	830	}
r29505	r29506
834	834	int bank = offset / 0x2000;
835	835
836	836	if (bank >= 4 && m_ram && m_ram_enabled)
837		m_ram[(m_ram_base * 0x2000 + (offset & 0x1fff)) % m_ram_size] = data;
	837	m_ram[(m_ram_base * 0x2000 + (offset & 0x1fff)) % m_ram.count()] = data;
838	838
839	839	if (offset < 4)
840	840	{

branches/new_menus/src/emu/bus/sega8/sega8_slot.h

r29505	r29506
49	49	virtual DECLARE_READ8_MEMBER(read_ram) { return 0xff; }
50	50	virtual DECLARE_WRITE8_MEMBER(write_ram) {}
51	51
52		void rom_alloc(running_machine &machine, UINT32 size);
53		void ram_alloc(running_machine &machine, UINT32 size);
	52	void rom_alloc(UINT32 size);
	53	void ram_alloc(UINT32 size);
54	54
55	55	virtual void late_bank_setup() {}
56	56
r29505	r29506
66	66	//protected:
67	67	UINT8* get_rom_base() { return m_rom; }
68	68	UINT8* get_ram_base() { return m_ram; }
69		UINT32 get_rom_size() { return m_rom_size; }
70		UINT32 get_ram_size() { return m_ram_size; }
	69	UINT32 get_rom_size() { return m_rom.count(); }
	70	UINT32 get_ram_size() { return m_ram.count(); }
71	71
72	72	void rom_map_setup(UINT32 size);
73	73	void ram_map_setup(UINT8 banks);
74	74
75	75	//private:
76	76	// internal state
77		UINT8  *m_rom;
78		UINT8  *m_ram;
79		UINT32 m_rom_size;
80		UINT32 m_ram_size;
	77	dynamic_buffer m_rom;
	78	dynamic_buffer m_ram;
81	79	int m_rom_page_count;
82	80
83	81	bool has_battery;

branches/new_menus/src/emu/bus/sega8/sega8_slot.c

r29505	r29506
49	49
50	50	device_sega8_cart_interface::device_sega8_cart_interface(const machine_config &mconfig, device_t &device)
51	51	: device_slot_card_interface(mconfig, device),
52		m_rom(NULL),
53		m_ram(NULL),
54		m_rom_size(0),
55		m_ram_size(0),
56	52	m_rom_page_count(0),
57	53	has_battery(FALSE),
58	54	m_late_battery_enable(FALSE),
r29505	r29506
74	70	//  rom_alloc - alloc the space for the cart
75	71	//-------------------------------------------------
76	72
77		void device_sega8_cart_interface::rom_alloc(running_machine &machine, UINT32 size)
	73	void device_sega8_cart_interface::rom_alloc(UINT32 size)
78	74	{
79	75	if (m_rom == NULL)
80	76	{
81		m_rom = auto_alloc_array_clear(machine, UINT8, size);
82		m_rom_size = size;
	77	m_rom.resize(size);
83	78	m_rom_page_count = size / 0x4000;
84	79	if (!m_rom_page_count)
85	80	m_rom_page_count = 1;   // we compute rom pages through (XXX % m_rom_page_count)!
r29505	r29506
92	87	//  ram_alloc - alloc the space for the ram
93	88	//-------------------------------------------------
94	89
95		void device_sega8_cart_interface::ram_alloc(running_machine &machine, UINT32 size)
	90	void device_sega8_cart_interface::ram_alloc(UINT32 size)
96	91	{
97	92	if (m_ram == NULL)
98	93	{
99		m_ram = auto_alloc_array_clear(machine, UINT8, size);
100		m_ram_size = size;
101		state_save_register_item_pointer(machine, "SEGA8_CART", this->device().tag(), 0, m_ram, m_ram_size);
	94	m_ram.resize(size);
	95	device().save_item(NAME(m_ram));
102	96	}
103	97	}
104	98
r29505	r29506
284	278	{
285	279	if (m_type == SEGA8_CASTLE)
286	280	{
287		m_cart->ram_alloc(machine(), 0x2000);
	281	m_cart->ram_alloc(0x2000);
288	282	m_cart->set_has_battery(FALSE);
289	283	}
290	284	else if (m_type == SEGA8_OTHELLO)
291	285	{
292		m_cart->ram_alloc(machine(), 0x800);
	286	m_cart->ram_alloc(0x800);
293	287	m_cart->set_has_battery(FALSE);
294	288	}
295	289	else if (m_type == SEGA8_BASIC_L3)
296	290	{
297		m_cart->ram_alloc(machine(), 0x8000);
	291	m_cart->ram_alloc(0x8000);
298	292	m_cart->set_has_battery(FALSE);
299	293	}
300	294	else if (m_type == SEGA8_MUSIC_EDITOR)
301	295	{
302		m_cart->ram_alloc(machine(), 0x2800);
	296	m_cart->ram_alloc(0x2800);
303	297	m_cart->set_has_battery(FALSE);
304	298	}
305	299	else if (m_type == SEGA8_DAHJEE_TYPEA)
306	300	{
307		m_cart->ram_alloc(machine(), 0x2400);
	301	m_cart->ram_alloc(0x2400);
308	302	m_cart->set_has_battery(FALSE);
309	303	}
310	304	else if (m_type == SEGA8_DAHJEE_TYPEB)
311	305	{
312		m_cart->ram_alloc(machine(), 0x2000);
	306	m_cart->ram_alloc(0x2000);
313	307	m_cart->set_has_battery(FALSE);
314	308	}
315	309	else if (m_type == SEGA8_CODEMASTERS)
316	310	{
317	311	// Codemasters cart can have 64KB of RAM (Ernie Els Golf? or 8KB?) and no battery
318		m_cart->ram_alloc(machine(), 0x10000);
	312	m_cart->ram_alloc(0x10000);
319	313	m_cart->set_has_battery(FALSE);
320	314	}
321	315	else
r29505	r29506
324	318	// how much RAM was in the cart and if there was a battery so we always alloc 32KB and
325	319	// we save its content only if the game enable the RAM
326	320	m_cart->set_late_battery(TRUE);
327		m_cart->ram_alloc(machine(), 0x08000);
	321	m_cart->ram_alloc(0x08000);
328	322	}
329	323	}
330	324	else
r29505	r29506
334	328	m_cart->set_late_battery(FALSE);
335	329
336	330	if (get_software_region_length("ram"))
337		m_cart->ram_alloc(machine(), get_software_region_length("ram"));
	331	m_cart->ram_alloc(get_software_region_length("ram"));
338	332
339	333	if (battery && !strcmp(battery, "yes"))
340	334	m_cart->set_has_battery(TRUE);
r29505	r29506
366	360	if (len & 0x3fff)
367	361	len = ((len >> 14) + 1) << 14;
368	362
369		m_cart->rom_alloc(machine(), len);
	363	m_cart->rom_alloc(len);
370	364	ROM = m_cart->get_rom_base();
371	365
372	366	if (software_entry() == NULL)

branches/new_menus/src/emu/bus/snes/snes_slot.c

r29505	r29506
67	67	//-------------------------------------------------
68	68
69	69	device_sns_cart_interface::device_sns_cart_interface(const machine_config &mconfig, device_t &device)
70		: device_slot_card_interface(mconfig, device),
71		m_rom(NULL),
72		m_nvram(NULL),
73		m_bios(NULL),
74		m_rtc_ram(NULL),
75		m_rom_size(0),
76		m_nvram_size(0),
77		m_bios_size(0),
78		m_rtc_ram_size(0)
	70	: device_slot_card_interface(mconfig, device)
79	71	{
80	72	}
81	73
r29505	r29506
92	84	//  rom_alloc - alloc the space for the cart
93	85	//-------------------------------------------------
94	86
95		void device_sns_cart_interface::rom_alloc(running_machine &machine, UINT32 size)
	87	void device_sns_cart_interface::rom_alloc(UINT32 size)
96	88	{
97	89	if (m_rom == NULL)
98		{
99		m_rom = auto_alloc_array_clear(machine, UINT8, size);
100		m_rom_size = size;
101		}
	90	m_rom.resize(size);
102	91	}
103	92
104	93
r29505	r29506
106	95	//  nvram_alloc - alloc the space for the nvram
107	96	//-------------------------------------------------
108	97
109		void device_sns_cart_interface::nvram_alloc(running_machine &machine, UINT32 size)
	98	void device_sns_cart_interface::nvram_alloc(UINT32 size)
110	99	{
111	100	if (m_nvram == NULL)
112	101	{
113		m_nvram = auto_alloc_array_clear(machine, UINT8, size);
114		m_nvram_size = size;
115		state_save_register_item_pointer(machine, "SNES_CART", this->device().tag(), 0, m_nvram, m_nvram_size);
	102	m_nvram.resize(size);
	103	device().save_item(NAME(m_nvram));
116	104	}
117	105	}
118	106
r29505	r29506
124	112	//  saved by the device itself)
125	113	//-------------------------------------------------
126	114
127		void device_sns_cart_interface::rtc_ram_alloc(running_machine &machine, UINT32 size)
	115	void device_sns_cart_interface::rtc_ram_alloc(UINT32 size)
128	116	{
129	117	if (m_rtc_ram == NULL)
130	118	{
131		m_rtc_ram = auto_alloc_array_clear(machine, UINT8, size);
132		m_rtc_ram_size = size;
133		state_save_register_item_pointer(machine, "SNES_CART", this->device().tag(), 0, m_rtc_ram, m_rtc_ram_size);
	119	m_rtc_ram.resize(size);
	120	device().save_item(NAME(m_rtc_ram));
134	121	}
135	122	}
136	123
r29505	r29506
140	127	//  (optional) add-on CPU bios
141	128	//-------------------------------------------------
142	129
143		void device_sns_cart_interface::addon_bios_alloc(running_machine &machine, UINT32 size)
	130	void device_sns_cart_interface::addon_bios_alloc(UINT32 size)
144	131	{
145	132	if (m_bios == NULL)
146		{
147		m_bios = auto_alloc_array_clear(machine, UINT8, size);
148		m_bios_size = size;
149		}
	133	m_bios.resize(size);
150	134	}
151	135
152	136
r29505	r29506
638	622
639	623	len = (software_entry() == NULL) ? (length() - offset) : get_software_region_length("rom");
640	624
641		m_cart->rom_alloc(machine(), len);
	625	m_cart->rom_alloc(len);
642	626	ROM = m_cart->get_rom_base();
643	627	if (software_entry() == NULL)
644	628	fread(ROM, len);
r29505	r29506
652	636	{
653	637	if (get_software_region("addon"))
654	638	{
655		m_cart->addon_bios_alloc(machine(), get_software_region_length("addon"));
	639	m_cart->addon_bios_alloc(get_software_region_length("addon"));
656	640	memcpy(m_cart->get_addon_bios_base(), get_software_region("addon"), get_software_region_length("addon"));
657	641	}
658	642	}
r29505	r29506
746	730	if ((m_cart->get_rom_size() & 0x7fff) == 0x2800)
747	731	{
748	732	logerror("Found NEC DSP dump at the bottom of the ROM.\n");
749		m_cart->addon_bios_alloc(machine(), 0x2800);
	733	m_cart->addon_bios_alloc(0x2800);
750	734	memcpy(m_cart->get_addon_bios_base(), m_cart->get_rom_base() + (m_cart->get_rom_size() - 0x2800), 0x2800);
751	735	m_cart->rom_map_setup(m_cart->get_rom_size() - 0x2800);
752	736	}
r29505	r29506
754	738	if ((m_cart->get_rom_size() & 0x7fff) == 0x2000)
755	739	{
756	740	logerror("Found NEC DSP dump (byuu's version) at the bottom of the ROM.\n");
757		m_cart->addon_bios_alloc(machine(), 0x2800);
	741	m_cart->addon_bios_alloc(0x2800);
758	742	for (int i = 0; i < 0x800; i++)
759	743	{
760	744	memcpy(m_cart->get_addon_bios_base() + i * 4 + 2, m_cart->get_rom_base() + (m_cart->get_rom_size() - 0x2000) + i * 3 + 0, 1);
r29505	r29506
772	756	if ((m_cart->get_rom_size() & 0x3ffff) == 0x11000)
773	757	{
774	758	logerror("Found Seta DSP dump at the bottom of the ROM.\n");
775		m_cart->addon_bios_alloc(machine(), 0x11000);
	759	m_cart->addon_bios_alloc(0x11000);
776	760	memcpy(m_cart->get_addon_bios_base(), m_cart->get_rom_base() + (m_cart->get_rom_size() - 0x11000), 0x11000);
777	761	m_cart->rom_map_setup(m_cart->get_rom_size() - 0x11000);
778	762	}
r29505	r29506
780	764	if ((m_cart->get_rom_size() & 0xffff) == 0xd000)
781	765	{
782	766	logerror("Found Seta DSP dump (byuu's version) at the bottom of the ROM.\n");
783		m_cart->addon_bios_alloc(machine(), 0x11000);
	767	m_cart->addon_bios_alloc(0x11000);
784	768	for (int i = 0; i < 0x4000; i++)
785	769	{
786	770	memcpy(m_cart->get_addon_bios_base() + i * 4 + 2, m_cart->get_rom_base() + (m_cart->get_rom_size() - 0xd000) + i * 3 + 0, 1);
r29505	r29506
796	780	if ((m_cart->get_rom_size() & 0x7fff) == 0x0c00)
797	781	{
798	782	logerror("Found CX4 dump at the bottom of the ROM.\n");
799		m_cart->addon_bios_alloc(machine(), 0x0c00);
	783	m_cart->addon_bios_alloc(0x0c00);
800	784	memcpy(m_cart->get_addon_bios_base(), m_cart->get_rom_base() + (m_cart->get_rom_size() - 0x0c00), 0x0c00);
801	785	m_cart->rom_map_setup(m_cart->get_rom_size() - 0x0c00);
802	786	}
r29505	r29506
805	789	if ((m_cart->get_rom_size() & 0x3ffff) == 0x28000)
806	790	{
807	791	logerror("Found ST018 dump at the bottom of the ROM.\n");
808		m_cart->addon_bios_alloc(machine(), 0x28000);
	792	m_cart->addon_bios_alloc(0x28000);
809	793	memcpy(m_cart->get_addon_bios_base(), m_cart->get_rom_base() + (m_cart->get_rom_size() - 0x28000), 0x28000);
810	794	m_cart->rom_map_setup(m_cart->get_rom_size() - 0x28000);
811	795	}
r29505	r29506
822	806	{
823	807	case ADDON_DSP1:
824	808	ROM = machine().root_device().memregion(region)->base();
825		m_cart->addon_bios_alloc(machine(), 0x2800);
	809	m_cart->addon_bios_alloc(0x2800);
826	810	memcpy(m_cart->get_addon_bios_base(), ROM, 0x2800);
827	811	break;
828	812	case ADDON_DSP1B:
829	813	ROM = machine().root_device().memregion(region)->base();
830		m_cart->addon_bios_alloc(machine(), 0x2800);
	814	m_cart->addon_bios_alloc(0x2800);
831	815	memcpy(m_cart->get_addon_bios_base(), ROM, 0x2800);
832	816	break;
833	817	case ADDON_DSP2:
834	818	ROM = machine().root_device().memregion(region)->base();
835		m_cart->addon_bios_alloc(machine(), 0x2800);
	819	m_cart->addon_bios_alloc(0x2800);
836	820	memcpy(m_cart->get_addon_bios_base(), ROM, 0x2800);
837	821	break;
838	822	case ADDON_DSP3:
839	823	ROM = machine().root_device().memregion(region)->base();
840		m_cart->addon_bios_alloc(machine(), 0x2800);
	824	m_cart->addon_bios_alloc(0x2800);
841	825	memcpy(m_cart->get_addon_bios_base(), ROM, 0x2800);
842	826	break;
843	827	case ADDON_DSP4:
844	828	ROM = machine().root_device().memregion(region)->base();
845		m_cart->addon_bios_alloc(machine(), 0x2800);
	829	m_cart->addon_bios_alloc(0x2800);
846	830	memcpy(m_cart->get_addon_bios_base(), ROM, 0x2800);
847	831	break;
848	832	case ADDON_ST010:
849	833	ROM = machine().root_device().memregion(region)->base();
850		m_cart->addon_bios_alloc(machine(), 0x11000);
	834	m_cart->addon_bios_alloc(0x11000);
851	835	memcpy(m_cart->get_addon_bios_base(), ROM, 0x11000);
852	836	break;
853	837	case ADDON_ST011:
854	838	ROM = machine().root_device().memregion(region)->base();
855		m_cart->addon_bios_alloc(machine(), 0x11000);
	839	m_cart->addon_bios_alloc(0x11000);
856	840	memcpy(m_cart->get_addon_bios_base(), ROM, 0x11000);
857	841	break;
858	842	}
r29505	r29506
883	867	}
884	868
885	869	if (size)
886		m_cart->nvram_alloc(machine(), size);
	870	m_cart->nvram_alloc(size);
887	871
888	872	if (m_type == SNES_STROM)
889		m_cart->nvram_alloc(machine(), 0x20000);
	873	m_cart->nvram_alloc(0x20000);
890	874	if (m_type == SNES_BSX)
891		m_cart->nvram_alloc(machine(), 0x8000);
	875	m_cart->nvram_alloc(0x8000);
892	876
893	877	// setup also RTC SRAM, when needed (to be removed when RTCs are converted to devices)
894	878	if (m_type == SNES_SRTC)
895		m_cart->rtc_ram_alloc(machine(), 13);
	879	m_cart->rtc_ram_alloc(13);
896	880	if (m_type == SNES_SPC7110_RTC)
897		m_cart->rtc_ram_alloc(machine(), 16);
	881	m_cart->rtc_ram_alloc(16);
898	882	}
899	883
900	884

branches/new_menus/src/emu/bus/snes/snes_slot.h

r29505	r29506
91	91	ADDON_Z80GB
92	92	};
93	93
94		// ======================> sns_cart_interface
95
96		struct sns_cart_interface
97		{
98		};
99
100
101	94	// ======================> device_sns_cart_interface
102	95
103	96	class device_sns_cart_interface : public device_slot_card_interface
r29505	r29506
110	103	// reading and writing
111	104	virtual DECLARE_READ8_MEMBER(read_l) { return 0xff; }   // ROM access in range [00-7f]
112	105	virtual DECLARE_READ8_MEMBER(read_h) { return 0xff; }   // ROM access in range [80-ff]
113		virtual DECLARE_READ8_MEMBER(read_ram) { if (m_nvram) { UINT32 mask = m_nvram_size - 1; return m_nvram[offset & mask]; } else return 0xff; }   // NVRAM access
	106	virtual DECLARE_READ8_MEMBER(read_ram) { if (m_nvram) { UINT32 mask = m_nvram.count() - 1; return m_nvram[offset & mask]; } else return 0xff; }   // NVRAM access
114	107	virtual DECLARE_WRITE8_MEMBER(write_l) {}   // used by carts with subslots
115	108	virtual DECLARE_WRITE8_MEMBER(write_h) {}   // used by carts with subslots
116		virtual DECLARE_WRITE8_MEMBER(write_ram) { if (m_nvram) { UINT32 mask = m_nvram_size - 1; m_nvram[offset & mask] = data; return; } } // NVRAM access
	109	virtual DECLARE_WRITE8_MEMBER(write_ram) { if (m_nvram) { UINT32 mask = m_nvram.count() - 1; m_nvram[offset & mask] = data; return; } } // NVRAM access
117	110	virtual DECLARE_READ8_MEMBER(chip_read) { return 0xff; }
118	111	virtual DECLARE_WRITE8_MEMBER(chip_write) {}
119	112	virtual void speedup_addon_bios_access() {};
120	113
121		void rom_alloc(running_machine &machine, UINT32 size);
122		void nvram_alloc(running_machine &machine, UINT32 size);
123		void rtc_ram_alloc(running_machine &machine, UINT32 size);
124		void addon_bios_alloc(running_machine &machine, UINT32 size);
	114	void rom_alloc(UINT32 size);
	115	void nvram_alloc(UINT32 size);
	116	void rtc_ram_alloc(UINT32 size);
	117	void addon_bios_alloc(UINT32 size);
125	118	UINT8* get_rom_base() { return m_rom; };
126	119	UINT8* get_nvram_base() { return m_nvram; };
127	120	UINT8* get_addon_bios_base() { return m_bios; };
128	121	UINT8* get_rtc_ram_base() { return m_rtc_ram; };
129		UINT32 get_rom_size() { return m_rom_size; };
130		UINT32 get_nvram_size() { return m_nvram_size; };
131		UINT32 get_addon_bios_size() { return m_bios_size; };
132		UINT32 get_rtc_ram_size() { return m_rtc_ram_size; };
	122	UINT32 get_rom_size() { return m_rom.count(); };
	123	UINT32 get_nvram_size() { return m_nvram.count(); };
	124	UINT32 get_addon_bios_size() { return m_bios.count(); };
	125	UINT32 get_rtc_ram_size() { return m_rtc_ram.count(); };
133	126
134	127	void rom_map_setup(UINT32 size);
135	128
136	129	// internal state
137		UINT8  *m_rom;
138		UINT8  *m_nvram;
139		UINT8  *m_bios;
140		UINT8  *m_rtc_ram;  // temp pointer to save RTC ram to nvram (will disappear when RTCs become devices)
141		UINT32 m_rom_size;
142		UINT32 m_nvram_size;
143		UINT32 m_bios_size;
144		UINT32 m_rtc_ram_size;  // temp
	130	dynamic_buffer m_rom;
	131	dynamic_buffer m_nvram;
	132	dynamic_buffer m_bios;
	133	dynamic_buffer m_rtc_ram;  // temp pointer to save RTC ram to nvram (will disappear when RTCs become devices)
145	134
146	135	UINT8 rom_bank_map[256];    // 32K chunks of rom
147	136	};
r29505	r29506
150	139	// ======================> base_sns_cart_slot_device
151	140
152	141	class base_sns_cart_slot_device : public device_t,
153		public sns_cart_interface,
154	142	public device_image_interface,
155	143	public device_slot_interface
156	144	{

branches/new_menus/src/emu/bus/snes/sa1.c

r29505	r29506
823	823	return 0xff;    // this should probably never happen, or are there SA-1 games with no BWRAM?
824	824
825	825	if (offset < 0x100000)
826		return m_nvram[offset & (m_nvram_size - 1)];
	826	return m_nvram[offset & (m_nvram.count() - 1)];
827	827
828	828	// Bitmap BWRAM
829	829	offset -= 0x100000;
r29505	r29506
844	844	}
845	845
846	846	// only return the correct bits
847		return (m_nvram[offset & (m_nvram_size - 1)] >> shift) & mask;
	847	return (m_nvram[offset & (m_nvram.count() - 1)] >> shift) & mask;
848	848	}
849	849
850	850	void sns_sa1_device::write_bwram(UINT32 offset, UINT8 data)
r29505	r29506
856	856
857	857	if (offset < 0x100000)
858	858	{
859		m_nvram[offset & (m_nvram_size - 1)] = data;
	859	m_nvram[offset & (m_nvram.count() - 1)] = data;
860	860	return;
861	861	}
862	862
r29505	r29506
879	879	}
880	880
881	881	// only change the correct bits, keeping the rest untouched
882		m_nvram[offset & (m_nvram_size - 1)] = (m_nvram[offset & (m_nvram_size - 1)] & ~mask) | data;
	882	m_nvram[offset & (m_nvram.count() - 1)] = (m_nvram[offset & (m_nvram.count() - 1)] & ~mask) | data;
883	883	}
884	884
885	885

branches/new_menus/src/emu/bus/isa/p1_hdc.c

r29505	r29506
37	37
38	38	const device_type P1_HDC = &device_creator<p1_hdc_device>;
39	39
40		static WD2010_INTERFACE( hdc_intf )
41		{
42		DEVCB_NULL,
43		DEVCB_NULL,
44		DEVCB_NULL,
45		DEVCB_NULL,
46		DEVCB_NULL,
47		DEVCB_NULL,
48		DEVCB_NULL,
49		DEVCB_NULL,
50		DEVCB_LINE_VCC,
51		DEVCB_LINE_VCC,
52		DEVCB_LINE_VCC,
53		DEVCB_LINE_VCC,
54		DEVCB_LINE_VCC
55		};
56
57	40	static MACHINE_CONFIG_FRAGMENT( hdc_b942 )
58		MCFG_WD2010_ADD(KM1809VG7_TAG, 5000000, hdc_intf) // XXX clock?
59
	41	MCFG_DEVICE_ADD(KM1809VG7_TAG, WD2010, 5000000) // XXX clock?
	42	MCFG_WD2010_IN_DRDY_CB(VCC)
	43	MCFG_WD2010_IN_INDEX_CB(VCC)
	44	MCFG_WD2010_IN_WF_CB(VCC)
	45	MCFG_WD2010_IN_TK000_CB(VCC)
	46	MCFG_WD2010_IN_SC_CB(VCC)
	47
60	48	MCFG_HARDDISK_ADD("hard0")
61	49	MCFG_HARDDISK_ADD("hard1")
62	50	MACHINE_CONFIG_END

branches/new_menus/src/emu/bus/isa/wdxt_gen.c

r29505	r29506
157	157
158	158
159	159	//-------------------------------------------------
160		//  WD2010_INTERFACE( hdc_intf )
161		//-------------------------------------------------
162
163		static WD2010_INTERFACE( hdc_intf )
164		{
165		DEVCB_NULL,
166		DEVCB_NULL,
167		DEVCB_DEVICE_LINE_MEMBER(WD11C00_17_TAG, wd11c00_17_device, clct_w),
168		DEVCB_DEVICE_MEMBER(WD11C00_17_TAG, wd11c00_17_device, read),
169		DEVCB_DEVICE_MEMBER(WD11C00_17_TAG, wd11c00_17_device, write),
170		DEVCB_NULL,
171		DEVCB_NULL,
172		DEVCB_NULL,
173		DEVCB_LINE_VCC,
174		DEVCB_LINE_VCC,
175		DEVCB_LINE_VCC,
176		DEVCB_LINE_VCC,
177		DEVCB_LINE_VCC
178		};
179
180
181		//-------------------------------------------------
182	160	//  MACHINE_DRIVER( wdxt_gen )
183	161	//-------------------------------------------------
184	162
r29505	r29506
187	165	MCFG_CPU_IO_MAP(wd1015_io)
188	166
189	167	MCFG_WD11C00_17_ADD(WD11C00_17_TAG, 5000000, host_intf)
190		MCFG_WD2010_ADD(WD2010A_TAG, 5000000, hdc_intf)
	168	MCFG_DEVICE_ADD(WD2010A_TAG, WD2010, 5000000)
	169	MCFG_WD2010_OUT_BCR_CB(DEVWRITELINE(WD11C00_17_TAG, wd11c00_17_device, clct_w))
	170	MCFG_WD2010_IN_BCS_CB(DEVREAD8(WD11C00_17_TAG, wd11c00_17_device, read))
	171	MCFG_WD2010_OUT_BCS_CB(DEVWRITE8(WD11C00_17_TAG, wd11c00_17_device, write))
	172	MCFG_WD2010_IN_DRDY_CB(VCC)
	173	MCFG_WD2010_IN_INDEX_CB(VCC)
	174	MCFG_WD2010_IN_WF_CB(VCC)
	175	MCFG_WD2010_IN_TK000_CB(VCC)
	176	MCFG_WD2010_IN_SC_CB(VCC)
191	177
192	178	MCFG_HARDDISK_ADD("hard0")
193	179	MCFG_HARDDISK_ADD("hard1")

branches/new_menus/src/emu/bus/nes/ggenie.c

r29505	r29506
254	254	//  MACHINE_CONFIG_FRAGMENT( sub_slot )
255	255	//-------------------------------------------------
256	256
257		static const nes_cart_interface gg_crt_interface =
258		{
259		};
260
261	257	static MACHINE_CONFIG_FRAGMENT( sub_slot )
262		MCFG_NES_CARTRIDGE_ADD("gg_slot", gg_crt_interface, nes_cart, NULL)
	258	MCFG_NES_CARTRIDGE_ADD("gg_slot", nes_cart, NULL)
263	259	MCFG_NES_CARTRIDGE_NOT_MANDATORY
264	260	MACHINE_CONFIG_END
265	261

branches/new_menus/src/emu/bus/nes/nes_slot.h

r29505	r29506
128	128	};
129	129
130	130
131		// ======================> nes_cart_interface
132
133		struct nes_cart_interface
134		{
135		};
136
137	131	#define CHRROM 0
138	132	#define CHRRAM 1
139	133
r29505	r29506
323	317	// ======================> nes_cart_slot_device
324	318
325	319	class nes_cart_slot_device : public device_t,
326		public nes_cart_interface,
327	320	public device_image_interface,
328	321	public device_slot_interface
329	322	{
r29505	r29506
400	393	DEVICE CONFIGURATION MACROS
401	394	***************************************************************************/
402	395
403		#define MCFG_NES_CARTRIDGE_ADD(_tag,_config,_slot_intf,_def_slot) \
	396	#define MCFG_NES_CARTRIDGE_ADD(_tag, _slot_intf, _def_slot) \
404	397	MCFG_DEVICE_ADD(_tag, NES_CART_SLOT, 0) \
405		MCFG_DEVICE_CONFIG(_config) \
406	398	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
407	399
408	400	#define MCFG_NES_CARTRIDGE_NOT_MANDATORY                                     \

branches/new_menus/src/emu/bus/x68k/x68k_scsiext.c

r29505	r29506
18	18
19	19	const device_type X68K_SCSIEXT = &device_creator<x68k_scsiext_device>;
20	20
21		static const mb89352_interface mb89352_intf =
22		{
23		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,x68k_scsiext_device,irq_w),
24		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,x68k_scsiext_device,drq_w)
25		};
26
27	21	//-------------------------------------------------
28	22	//  rom_region - device-specific ROM region
29	23	//-------------------------------------------------
r29505	r29506
48	42	MCFG_SCSIDEV_ADD("scsi:harddisk4", SCSIHD, SCSI_ID_4)
49	43	MCFG_SCSIDEV_ADD("scsi:harddisk5", SCSIHD, SCSI_ID_5)
50	44	MCFG_SCSIDEV_ADD("scsi:harddisk6", SCSIHD, SCSI_ID_6)
51		MCFG_MB89352A_ADD("scsi:mb89352",mb89352_intf)
	45	MCFG_DEVICE_ADD("scsi:mb89352", MB89352A, 0)
	46	MCFG_MB89352A_IRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, x68k_scsiext_device, irq_w))
	47	MCFG_MB89352A_DRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, x68k_scsiext_device, drq_w))
52	48	MACHINE_CONFIG_END
53	49
54	50	machine_config_constructor x68k_scsiext_device::device_mconfig_additions() const

branches/new_menus/src/emu/memory.c

r29505	r29506
1886	1886	adjust_addresses(entry->m_bytestart, entry->m_byteend, entry->m_bytemask, entry->m_bytemirror);
1887	1887
1888	1888	// if we have a share entry, add it to our map
1889		if (entry->m_share != NULL)
	1889	if (entry->m_sharetag != NULL)
1890	1890	{
1891	1891	// if we can't find it, add it to our map
1892	1892	astring fulltag;
1893		if (manager().m_sharelist.find(device().siblingtag(fulltag, entry->m_share).cstr()) == NULL)
	1893	if (manager().m_sharelist.find(entry->m_sharebase->subtag(fulltag, entry->m_sharetag).cstr()) == NULL)
1894	1894	{
1895	1895	VPRINTF(("Creating share '%s' of length 0x%X\n", fulltag.cstr(), entry->m_byteend + 1 - entry->m_bytestart));
1896	1896	memory_share *share = global_alloc(memory_share(m_map->m_databits, entry->m_byteend + 1 - entry->m_bytestart, endianness()));
r29505	r29506
1910	1910	}
1911	1911
1912	1912	// validate adjusted addresses against implicit regions
1913		if (entry->m_region != NULL && entry->m_share == NULL)
	1913	if (entry->m_region != NULL && entry->m_sharetag == NULL)
1914	1914	{
1915	1915	// determine full tag
1916	1916	astring fulltag;
r29505	r29506
2224	2224	for (address_map_entry *entry = m_map->m_entrylist.first(); entry != NULL; entry = entry->next())
2225	2225	{
2226	2226	// if we haven't assigned this block yet, see if we have a mapped shared pointer for it
2227		if (entry->m_memory == NULL && entry->m_share != NULL)
	2227	if (entry->m_memory == NULL && entry->m_sharetag != NULL)
2228	2228	{
2229	2229	astring fulltag;
2230		memory_share *share = manager().m_sharelist.find(device().siblingtag(fulltag, entry->m_share).cstr());
	2230	memory_share *share = manager().m_sharelist.find(entry->m_sharebase->subtag(fulltag, entry->m_sharetag).cstr());
2231	2231	if (share != NULL && share->ptr() != NULL)
2232	2232	{
2233	2233	entry->m_memory = share->ptr();
2234		VPRINTF(("memory range %08X-%08X -> shared_ptr '%s' [%p]\n", entry->m_addrstart, entry->m_addrend, entry->m_share, entry->m_memory));
	2234	VPRINTF(("memory range %08X-%08X -> shared_ptr '%s' [%p]\n", entry->m_addrstart, entry->m_addrend, entry->m_sharetag, entry->m_memory));
2235	2235	}
2236	2236	else
2237	2237	{
2238		VPRINTF(("memory range %08X-%08X -> shared_ptr '%s' but not found\n", entry->m_addrstart, entry->m_addrend, entry->m_share));
	2238	VPRINTF(("memory range %08X-%08X -> shared_ptr '%s' but not found\n", entry->m_addrstart, entry->m_addrend, entry->m_sharetag));
2239	2239	}
2240	2240	}
2241	2241
r29505	r29506
2247	2247	}
2248	2248
2249	2249	// if we're the first match on a shared pointer, assign it now
2250		if (entry->m_memory != NULL && entry->m_share != NULL)
	2250	if (entry->m_memory != NULL && entry->m_sharetag != NULL)
2251	2251	{
2252	2252	astring fulltag;
2253		memory_share *share = manager().m_sharelist.find(device().siblingtag(fulltag, entry->m_share).cstr());
	2253	memory_share *share = manager().m_sharelist.find(entry->m_sharebase->subtag(fulltag, entry->m_sharetag).cstr());
2254	2254	if (share != NULL && share->ptr() == NULL)
2255	2255	{
2256	2256	share->set_ptr(entry->m_memory);
2257		VPRINTF(("setting shared_ptr '%s' = %p\n", entry->m_share, entry->m_memory));
	2257	VPRINTF(("setting shared_ptr '%s' = %p\n", entry->m_sharetag, entry->m_memory));
2258	2258	}
2259	2259	}
2260	2260
r29505	r29506
2801	2801	bool address_space::needs_backing_store(const address_map_entry *entry)
2802	2802	{
2803	2803	// if we are sharing, and we don't have a pointer yet, create one
2804		if (entry->m_share != NULL)
	2804	if (entry->m_sharetag != NULL)
2805	2805	{
2806	2806	astring fulltag;
2807		memory_share *share = manager().m_sharelist.find(device().siblingtag(fulltag, entry->m_share).cstr());
	2807	memory_share *share = manager().m_sharelist.find(entry->m_sharebase->subtag(fulltag, entry->m_sharetag).cstr());
2808	2808	if (share != NULL && share->ptr() == NULL)
2809	2809	return true;
2810	2810	}

branches/new_menus/src/emu/diexec.c

r29505	r29506
492	492	m_profiler = profile_type(index + PROFILER_DEVICE_FIRST);
493	493	m_inttrigger = index + TRIGGER_INT;
494	494
495		// fill in the input states and IRQ callback information
496		for (int line = 0; line < ARRAY_LENGTH(m_input); line++)
497		m_input[line].start(this, line);
498
499	495	// allocate timers if we need them
500	496	if (m_timed_interrupt_period != attotime::zero)
501	497	m_timedint_timer = device().machine().scheduler().timer_alloc(FUNC(static_trigger_periodic_interrupt), (void *)this);
502
503		// register for save states
504		device().save_item(NAME(m_suspend));
505		device().save_item(NAME(m_nextsuspend));
506		device().save_item(NAME(m_eatcycles));
507		device().save_item(NAME(m_nexteatcycles));
508		device().save_item(NAME(m_trigger));
509		device().save_item(NAME(m_totalcycles));
510		device().save_item(NAME(m_localtime));
511	498	}
512	499
513	500
r29505	r29506
520	507	{
521	508	// make sure somebody set us up the icount
522	509	assert_always(m_icountptr != NULL, "m_icountptr never initialized!");
	510
	511	// register for save states
	512	device().save_item(NAME(m_suspend));
	513	device().save_item(NAME(m_nextsuspend));
	514	device().save_item(NAME(m_eatcycles));
	515	device().save_item(NAME(m_nexteatcycles));
	516	device().save_item(NAME(m_trigger));
	517	device().save_item(NAME(m_totalcycles));
	518	device().save_item(NAME(m_localtime));
	519
	520	// fill in the input states and IRQ callback information
	521	for (int line = 0; line < ARRAY_LENGTH(m_input); line++)
	522	m_input[line].start(this, line);
523	523	}
524	524
525	525

branches/new_menus/src/emu/debug/debugcmd.c

r29505	r29506
1993	1993	{
1994	1994	cheat_region[region_count].offset = space->address_to_byte(entry->m_addrstart) & space->bytemask();
1995	1995	cheat_region[region_count].endoffset = space->address_to_byte(entry->m_addrend) & space->bytemask();
1996		cheat_region[region_count].share = entry->m_share;
	1996	cheat_region[region_count].share = entry->m_sharetag;
1997	1997	cheat_region[region_count].disabled = (entry->m_write.m_type == AMH_RAM) ? FALSE : TRUE;
1998	1998
1999	1999	/* disable double share regions */
2000		if (entry->m_share != NULL)
	2000	if (entry->m_sharetag != NULL)
2001	2001	for (i = 0; i < region_count; i++)
2002	2002	if (cheat_region[i].share != NULL)
2003		if (strcmp(cheat_region[i].share, entry->m_share) == 0)
	2003	if (strcmp(cheat_region[i].share, entry->m_sharetag) == 0)
2004	2004	cheat_region[region_count].disabled = TRUE;
2005	2005
2006	2006	region_count++;

branches/new_menus/src/emu/video/crt9007.c

r29505	r29506
398	398
399	399	inline void crt9007_t::recompute_parameters()
400	400	{
401		#ifdef UNUSED_FOR_NOW
402	401	// check that necessary registers have been loaded
403	402	if (!HAS_VALID_PARAMETERS) return;
404	403
405	404	// screen dimensions
406		int horiz_pix_total = CHARACTERS_PER_HORIZONTAL_PERIOD * m_hpixels_per_column;
407		int vert_pix_total = SCAN_LINES_PER_FRAME;
	405	//int horiz_pix_total = CHARACTERS_PER_HORIZONTAL_PERIOD * m_hpixels_per_column;
	406	//int vert_pix_total = SCAN_LINES_PER_FRAME;
408	407
409	408	// refresh rate
410		attoseconds_t refresh = HZ_TO_ATTOSECONDS(clock()) * horiz_pix_total * vert_pix_total;
	409	//attoseconds_t refresh = HZ_TO_ATTOSECONDS(clock()) * horiz_pix_total * vert_pix_total;
411	410
412	411	// horizontal sync
413	412	m_hsync_start = 0;
r29505	r29506
426	425	m_vsync_end = VERTICAL_SYNC_WIDTH;
427	426
428	427	// visible area
429		rectangle visarea;
	428	//rectangle visarea;
430	429
431		visarea.set(m_hsync_end, horiz_pix_total - 1, m_vsync_end, vert_pix_total - 1);
	430	//visarea.set(m_hsync_end, horiz_pix_total - 1, m_vsync_end, vert_pix_total - 1);
432	431
433		if (LOG)
434		{
435		logerror("CRT9007 '%s' Screen: %u x %u @ %f Hz\n", tag(), horiz_pix_total, vert_pix_total, 1 / ATTOSECONDS_TO_DOUBLE(refresh));
436		logerror("CRT9007 '%s' Visible Area: (%u, %u) - (%u, %u)\n", tag(), visarea.min_x, visarea.min_y, visarea.max_x, visarea.max_y);
437		}
	432	//if (LOG)
	433	//{
	434	//   logerror("CRT9007 '%s' Screen: %u x %u @ %f Hz\n", tag(), horiz_pix_total, vert_pix_total, 1 / ATTOSECONDS_TO_DOUBLE(refresh));
	435	//   logerror("CRT9007 '%s' Visible Area: (%u, %u) - (%u, %u)\n", tag(), visarea.min_x, visarea.min_y, visarea.max_x, visarea.max_y);
	436	//}
438	437
439		m_screen->configure(horiz_pix_total, vert_pix_total, visarea, refresh);
	438	//m_screen->configure(horiz_pix_total, vert_pix_total, visarea, refresh);
440	439
441	440	m_hsync_timer->adjust(m_screen->time_until_pos(0, 0));
442	441	m_vsync_timer->adjust(m_screen->time_until_pos(0, 0));
443	442	m_vlt_timer->adjust(m_screen->time_until_pos(0, m_vlt_start), 1);
444	443	m_drb_timer->adjust(m_screen->time_until_pos(0, 0));
445		#endif
446	444	}
447	445
448	446

branches/new_menus/src/emu/tilemap.h

r29505	r29506
499	499	UINT32 width() const { return m_width; }
500	500	UINT32 height() const { return m_height; }
501	501	bool enabled() const { return m_enable; }
	502	int palette_offset() const { return m_palette_offset; }
502	503	int scrolldx() const { return (m_attributes & TILEMAP_FLIPX) ? m_dx_flipped : m_dx; }
503	504	int scrolldy() const { return (m_attributes & TILEMAP_FLIPY) ? m_dy_flipped : m_dy; }
504	505	int scrollx(int which = 0) const { return (which < m_scrollrows) ? m_rowscroll[which] : 0; }

branches/new_menus/src/emu/machine/hd63450.h

r29505	r29506
85	85
86	86	DECLARE_READ16_MEMBER( read );
87	87	DECLARE_WRITE16_MEMBER( write );
	88	DECLARE_WRITE_LINE_MEMBER(drq0_w);
	89	DECLARE_WRITE_LINE_MEMBER(drq1_w);
	90	DECLARE_WRITE_LINE_MEMBER(drq2_w);
	91	DECLARE_WRITE_LINE_MEMBER(drq3_w);
88	92
89	93	void single_transfer(int x);
90	94	void set_timer(int channel, attotime tm);
r29505	r29506
95	99	// device-level overrides
96	100	virtual void device_config_complete();
97	101	virtual void device_start();
	102	virtual void device_reset();
98	103
99	104	private:
100	105	devcb2_write8 m_dma_end;
r29505	r29506
115	120	int m_transfer_size[4];
116	121	int m_halted[4];  // non-zero if a channel has been halted, and can be continued later.
117	122	cpu_device *m_cpu;
	123	bool m_drq_state[4];
118	124
119	125	TIMER_CALLBACK_MEMBER(dma_transfer_timer);
120	126	void dma_transfer_abort(int channel);
121	127	void dma_transfer_halt(int channel);
122	128	void dma_transfer_continue(int channel);
123		void dma_transfer_start(int channel, int dir);
	129	void dma_transfer_start(int channel);
124	130	};
125	131
126	132	extern const device_type HD63450;

branches/new_menus/src/emu/machine/aakart.c

r29505	r29506
64	64	m_rxtimer = timer_alloc(RX_TIMER);
65	65	m_rxtimer->adjust(attotime::from_hz(clock()), 0, attotime::from_hz(clock()));
66	66	m_txtimer = timer_alloc(TX_TIMER);
67		m_txtimer->adjust(attotime::from_hz(clock()*3), 0, attotime::from_hz(clock()*3));
	67	m_txtimer->adjust(attotime::from_hz(clock()), 0, attotime::from_hz(clock()));
68	68	m_mousetimer = timer_alloc(MOUSE_TIMER);
69	69	m_mousetimer->adjust(attotime::from_hz(clock()), 0, attotime::from_hz(clock()));
70	70	m_keybtimer = timer_alloc(KEYB_TIMER);
r29505	r29506
98	98
99	99	void aakart_device::device_reset()
100	100	{
101		m_status = STATUS_NORMAL;
	101	m_status = STATUS_HRST;
102	102	m_new_command = 0;
103	103	m_rx = -1;
104	104	m_mouse_enable = 0;
r29505	r29506
108	108	//  device_timer - handler timer events
109	109	//-------------------------------------------------
110	110
111		#if 0
112
113	111	void aakart_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
114	112	{
115		#if 0
116		if(id == KEYB_TIMER && m_keyb_enable && m_status == STATUS_NORMAL)
117		{
118		m_new_command |= 2;
119		m_rx_latch = 0xd0 | 0; // keyb scancode (0xd0=up 0xc0=down, bits 3-0 row)
120		m_status = STATUS_KEYUP;
121		//m_ff ^= 1;
122		return;
123		}
124		#endif
	113	if(id == TX_TIMER && m_new_command & 1)
	114	{
	115	switch(m_tx_latch)
	116	{
	117	case 0x00:
	118	case 0x02:
	119	case 0x03:
	120	case 0x07:
	121	// ---- -x-- scroll lock
	122	// ---- --x- num lock
	123	// ---- ---x caps lock
	124	break;
	125	case 0x20:
	126	m_rx = 0x81;
	127	m_out_tx_func(ASSERT_LINE);
	128	break;
	129	case 0x30:
	130	case 0x31:
	131	case 0x32:
	132	case 0x33:
	133	m_keyb_enable = m_tx_latch & 1;
	134	m_mouse_enable = (m_tx_latch & 2) >> 1;
	135	if(m_keyb_enable & 1 && m_keyb_state & 1)
	136	{
	137	//printf("Got row\n");
	138	m_rx = m_keyb_row;
	139	m_out_tx_func(ASSERT_LINE);
	140	}
	141	break;
	142	case 0x3f:
	143	if(m_keyb_enable & 1 && m_keyb_state & 1)
	144	{
	145	//printf("Got col\n");
	146	m_rx = m_keyb_col;
	147	m_out_tx_func(ASSERT_LINE);
	148	m_keyb_state = 0;
	149	}
	150	break;
	151	case 0xfd:
	152	m_rx = 0xfd;
	153	m_out_tx_func(ASSERT_LINE);
	154	break;
	155	case 0xfe:
	156	m_rx = 0xfe;
	157	m_out_tx_func(ASSERT_LINE);
	158	break;
	159	case 0xff:
	160	m_rx = 0xff;
	161	m_out_tx_func(ASSERT_LINE);
	162	break;
	163	default:
	164	printf("%02x %02x %02x\n",m_tx_latch,m_rx_latch,m_keyb_enable);
	165	break;
	166	}
125	167
126		if(id == MOUSE_TIMER && m_mouse_enable && m_status == STATUS_NORMAL)
127		{
128		m_new_command |= 2;
129		m_rx_latch = 0; // mouse X position
130		m_status = STATUS_MOUSE;
131		//m_ff ^= 1;
132		return;
133		}
	168	//m_new_command &= ~1;
	169	m_out_rx_func(ASSERT_LINE);
	170	}
134	171
135		if(m_new_command == 0)
136		return;
137
138		if(id == RX_TIMER && m_new_command & 2)
139		{
140		m_out_rx_func(ASSERT_LINE);
141		m_new_command &= ~2;
142		m_rx = m_rx_latch;
143		return;
144		}
145
146		if(id == TX_TIMER && m_new_command & 1)
147		{
148		switch(m_status)
149		{
150		case STATUS_NORMAL:
151		{
152		switch(m_tx_latch)
153		{
154		case 0x00: // set leds
155		break;
156		case RQID:
157		m_rx_latch = 0x81; //keyboard ID
158		break;
159		case SMAK:
160		case MACK:
161		case SACK:
162		case NACK:
163		if(m_tx_latch & 2) { m_mouse_enable = 1; }
164		if(m_tx_latch & 1) { m_keyb_enable = 1; }
165		break;
166		case HRST:
167		m_rx_latch = HRST;
168		m_status = STATUS_HRST;
169		break;
170		default:
171		//printf("%02x\n",m_tx_latch);
172		break;
173		}
174		break;
175		}
176		case STATUS_KEYDOWN:
177		{
178		switch(m_tx_latch)
179		{
180		case BACK:
181		m_rx_latch = 0xc0 | 0; // keyb scancode (0xd0=up 0xc0=down, bits 3-0 col)
182		m_status = STATUS_NORMAL;
183		break;
184		case HRST:
185		m_rx_latch = HRST;
186		m_status = STATUS_HRST;
187		break;
188		}
189		break;
190		}
191		case STATUS_KEYUP:
192		{
193		switch(m_tx_latch)
194		{
195		case BACK:
196		m_rx_latch = 0xd0 | 0; // keyb scancode (0xd0=up 0xc0=down, bits 3-0 col)
197		m_status = STATUS_NORMAL;
198		break;
199		case HRST:
200		m_rx_latch = HRST;
201		m_status = STATUS_HRST;
202		break;
203		}
204		break;
205		}
206		case STATUS_MOUSE:
207		{
208		switch(m_tx_latch)
209		{
210		case BACK:
211		m_rx_latch = 0; // mouse Y
212		m_status = STATUS_NORMAL;
213		break;
214		default:
215		case HRST:
216		m_rx_latch = HRST;
217		m_status = STATUS_HRST;
218		break;
219		}
220		break;
221		}
222		case STATUS_HRST:
223		{
224		switch(m_tx_latch)
225		{
226		case HRST:  { m_rx_latch = HRST; m_keyb_enable = m_mouse_enable = 0; break; }
227		case RAK1:  { m_rx_latch = RAK1; m_keyb_enable = m_mouse_enable = 0; break; }
228		case RAK2:  { m_rx_latch = RAK2; m_status = STATUS_NORMAL; break; }
229		}
230		break;
231		}
232		}
233		m_out_tx_func(ASSERT_LINE);
234		m_new_command &= ~1;
235		m_new_command |= 2;
236		}
237	172	}
238		#else
239	173
240		void aakart_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
241		{
242		if(id == RX_TIMER && m_new_command & 2)
243		{
244		m_out_rx_func(ASSERT_LINE);
245		m_out_tx_func(CLEAR_LINE);
246		m_rx = m_rx_latch;
247		return;
248		}
249
250		if(id == TX_TIMER && m_new_command & 1)
251		{
252		m_out_tx_func(ASSERT_LINE);
253		m_new_command &= ~1;
254		m_new_command |= 2;
255		return;
256		}
257		}
258		#endif
259
260	174	//**************************************************************************
261	175	//  READ/WRITE HANDLERS
262	176	//**************************************************************************
263	177
	178	#include "debugger.h"
	179
264	180	READ8_MEMBER( aakart_device::read )
265	181	{
266		m_out_rx_func(CLEAR_LINE);
	182	m_out_tx_func(CLEAR_LINE);
	183	//debugger_break(machine());
267	184	return m_rx;
268	185	}
269	186
r29505	r29506
272	189	// if(m_new_command) printf("skip cmd %02x\n",data);
273	190
274	191	m_tx_latch = data;
275		switch(m_status)
276		{
277		case STATUS_NORMAL:
278		{
279		switch(m_tx_latch)
280		{
281		case 0x00: //set leds
282		break;
283		case RQID:
284		m_rx_latch = 0x81; //keyboard ID
285		break;
286		case HRST:
287		m_rx_latch = HRST;
288		m_status = STATUS_HRST;
289		break;
290		case SMAK:
291		case MACK:
292		case SACK:
293		case NACK:
294		if(m_tx_latch & 2) { m_mouse_enable = 1; }
295		if(m_tx_latch & 1) { m_keyb_enable = 1; }
296		m_rx_latch = 0;
297		break;
298		case BACK:
299		m_rx_latch = machine().rand(); // ???
300		break;
301		default:
302		//printf("%02x\n",data);
303		break;
304		}
305		break;
306		}
307		case STATUS_KEYDOWN:
308		{
309		m_rx_latch = machine().rand();
	192	m_out_rx_func(CLEAR_LINE);
	193	m_new_command |= 1;
	194	}
310	195
311		switch(m_tx_latch)
312		{
313		case HRST:
314		m_rx_latch = HRST;
315		m_status = STATUS_HRST;
316		break;
317		default:
318		//m_rx_latch = 0xc0 | 0x04;
319		printf("%02x\n",data);
320		break;
321		}
322		break;
323		}
324		case STATUS_HRST:
325		{
326		switch(m_tx_latch)
327		{
328		case HRST:  { m_rx_latch = HRST; m_keyb_enable = m_mouse_enable = 0; break; }
329		case RAK1:  { m_rx_latch = RAK1; m_keyb_enable = m_mouse_enable = 0; break; }
330		case RAK2:  { m_rx_latch = RAK2; m_status = STATUS_NORMAL; break; }
331		}
332		break;
333		}
334		}
335		m_new_command |= 1;
336
337		//m_tx_latch = data;
338		//m_new_command |= 1;
	196	void aakart_device::send_keycode_down(UINT8 row, UINT8 col)
	197	{
	198	//printf("keycode down\n");
	199	m_keyb_row = row | 0xc0;
	200	m_keyb_col = col | 0xc0;
	201	m_keyb_state = 1;
339	202	}
340	203
341		#if 0
342		void aakart_device::write_kbd_buf()
	204	void aakart_device::send_keycode_up(UINT8 row, UINT8 col)
343	205	{
344		//printf("%08x\n",data);
345		m_out_tx_func(ASSERT_LINE);
346		//debugger_break(machine());
347		m_status = STATUS_KEYDOWN;
	206	//printf("keycode up\n");
	207	m_keyb_row = row | 0xd0;
	208	m_keyb_col = col | 0xd0;
	209	m_keyb_state = 1;
348	210	}
349		#endif

branches/new_menus/src/emu/machine/aakart.h

r29505	r29506
52	52	// I/O operations
53	53	DECLARE_WRITE8_MEMBER( write );
54	54	DECLARE_READ8_MEMBER( read );
55
	55	void send_keycode_down(UINT8 row, UINT8 col);
	56	void send_keycode_up(UINT8 row, UINT8 col);
56	57	protected:
57	58	// device-level overrides
58	59	virtual void device_validity_check(validity_checker &valid) const;
r29505	r29506
73	74
74	75	devcb_resolved_write_line   m_out_tx_func;
75	76	devcb_resolved_write_line   m_out_rx_func;
76		int m_tx_latch, m_rx_latch;
77		int m_rx;
78		int m_new_command;
79		int m_status;
80		int m_mouse_enable;
81		int m_keyb_enable;
	77	UINT8 m_tx_latch, m_rx_latch;
	78	UINT8 m_rx;
	79	UINT8 m_new_command;
	80	UINT8 m_status;
	81	UINT8 m_mouse_enable;
	82	UINT8 m_keyb_enable;
	83	UINT8 m_keyb_row;
	84	UINT8 m_keyb_col;
	85	UINT8 m_keyb_state;
	86
82	87	};
83	88
84	89

branches/new_menus/src/emu/machine/roc10937.c

r29505	r29506
32	32	*/
33	33
34	34	static const UINT16 roc10937charset[]=
35		{            // FEDC BA98 7654 3210
	35	{           // FEDC BA98 7654 3210
36	36	0x507F, // 0101 0000 0111 1111 @.
37	37	0x44CF, // 0100 0100 1100 1111 A.
38	38	0x153F, // 0001 0101 0011 1111 B.
r29505	r29506
95	95	//                     -.
96	96	0x2001, // 0010 0000 0000 0001 -
97	97	//                     /.
98		0x2430, // 0010 0100 0011 0000 <.
	98	0x2430, // 0010 0010 0011 0000 <.
99	99	0x4430, // 0100 0100 0011 0000 =.
100	100	0x8830, // 1000 1000 0011 0000 >.
101	101	0x1407, // 0001 0100 0000 0111 ?.
102	102	};
103	103
	104
104	105	///////////////////////////////////////////////////////////////////////////
105	106	static const int roc10937poslut[]=
106	107	{
r29505	r29506
128	129	device_t(mconfig, type, name, tag, owner, clock, shortname, source)
129	130	{
130	131	m_port_val=0;
131		m_reversed=0;
132	132	}
133	133
134	134
r29505	r29506
138	138	roc.m_port_val = val;
139	139	}
140	140
141		void rocvfd_t::static_set_zero(device_t &device, bool reversed)
142		{
143		rocvfd_t &roc = downcast<rocvfd_t &>(device);
144		roc.m_reversed = reversed;
145		}
146
147	141	void rocvfd_t::device_start()
148	142	{
149	143	save_item(NAME(m_port_val));
150		save_item(NAME(m_reversed));
151	144	save_item(NAME(m_cursor_pos));
152	145	save_item(NAME(m_window_size));
153	146	save_item(NAME(m_shift_count));
r29505	r29506
196	189	}
197	190	}
198	191
	192	//Display on Rockwell chips is naturally backwards, due to the way it is wired. We emulate this by flipping the display at update time
199	193	void rocvfd_t::update_display()
200	194	{
201	195	for (int i =0; i<16; i++)
202	196	{
203		if (m_reversed)
204		{
205		m_outputs[i] = set_display(m_chars[15-i]);
206		}
207		else
208		{
209		m_outputs[i] = set_display(m_chars[i]);
210		}
	197	m_outputs[i] = set_display(m_chars[15-i]);
211	198	output_set_indexed_value("vfd", (m_port_val*16) + i, m_outputs[i]);
212	199	}
213	200	}
r29505	r29506
232	219	: rocvfd_t(mconfig, ROC10937, "Rockwell 10937 VFD controller and compatible", tag, owner, clock, "roc10937", __FILE__)
233	220	{
234	221	m_port_val=0;
235		m_reversed=0;
236	222	}
237	223
238	224	const device_type MSC1937 = &device_creator<msc1937_t>;
r29505	r29506
241	227	: rocvfd_t(mconfig, MSC1937, "OKI MSC1937 VFD controller", tag, owner, clock, "msc1937", __FILE__)
242	228	{
243	229	m_port_val=0;
244		m_reversed=0;
245	230	}
246	231
247	232	void rocvfd_t::write_char(int data)
r29505	r29506
301	286	: rocvfd_t(mconfig, ROC10957, "Rockwell 10957 VFD controller and compatible", tag, owner, clock, "roc10957", __FILE__)
302	287	{
303	288	m_port_val=0;
304		m_reversed=0;
305	289	}
306	290
307	291	void roc10957_t::write_char(int data)
r29505	r29506
363	347	}
364	348	}
365	349	}
	350
	351	const device_type S16LF01 = &device_creator<s16lf01_t>;
	352
	353	s16lf01_t::s16lf01_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	354	: rocvfd_t(mconfig, S16LF01, "Samsung 16LF01 Series VFD controller and compatible", tag, owner, clock, "s16lf01", __FILE__)
	355	{
	356	m_port_val=0;
	357	}
	358
	359	//Samsung chips fix the issue with the reversal of the drive.
	360	void s16lf01_t::update_display()
	361	{
	362	for (int i =0; i<16; i++)
	363	{
	364	m_outputs[i] = set_display(m_chars[i]);
	365	output_set_indexed_value("vfd", (m_port_val*16) + i, m_outputs[i]);
	366	}
	367	}

branches/new_menus/src/emu/machine/roc10937.h

r29505	r29506
1	1	/**********************************************************************
2	2
3		Rockwell 10937/10957 interface and emulation by J.Wallace
4		OKI MSC1937 is a clone of this chip
	3	Rockwell 10937/10957 interface and simlar chips
	4	Emulation by J.Wallace
	5	OKI MSC1937 is a clone of this chip, with many others.
5	6
6	7	**********************************************************************/
7	8	#pragma once
r29505	r29506
9	10	#ifndef ROC10937_H
10	11	#define ROC10937_H
11	12
12		#define LEFT_TO_RIGHT 1
13		#define RIGHT_TO_LEFT 0
	13	#define MCFG_ROC10937_ADD(_tag,_val) \
	14	MCFG_DEVICE_ADD(_tag, ROC10937,60)\
	15	MCFG_ROC10937_PORT(_val)
14	16
15		#define MCFG_ROC10937_ADD(_tag,_val,_reversed) \
16		MCFG_DEVICE_ADD(_tag, ROC10937,60)\
17		MCFG_ROC10937_PORT(_val) \
18		MCFG_ROC10937_REVERSE(_reversed)
19	17	#define MCFG_ROC10937_PORT(_val) \
20	18	roc10937_t::static_set_value(*device, _val);
21		#define MCFG_ROC10937_REVERSE(_reversed) \
22		roc10937_t::static_set_zero(*device, _reversed);
23	19	#define MCFG_ROC10937_REMOVE(_tag) \
24	20	MCFG_DEVICE_REMOVE(_tag)
25	21
26		#define MCFG_ROC10957_ADD(_tag,_val,_reversed) \
	22	#define MCFG_ROC10957_ADD(_tag,_val) \
27	23	MCFG_DEVICE_ADD(_tag, ROC10957,60)\
28		MCFG_ROC10957_PORT(_val) \
29		MCFG_ROC10957_REVERSE(_reversed)
	24	MCFG_ROC10957_PORT(_val)
	25
30	26	#define MCFG_ROC10957_PORT(_val) \
31	27	roc10957_t::static_set_value(*device, _val);
32		#define MCFG_ROC10957_REVERSE(_reversed) \
33		roc10957_t::static_set_zero(*device, _reversed);
34	28	#define MCFG_ROC10957_REMOVE(_tag) \
35	29	MCFG_DEVICE_REMOVE(_tag)
36	30
37		#define MCFG_MSC1937_ADD(_tag,_val,_reversed) \
	31	#define MCFG_MSC1937_ADD(_tag,_val) \
38	32	MCFG_DEVICE_ADD(_tag, ROC10937,60)\
39		MCFG_MSC1937_PORT(_val) \
40		MCFG_MSC1937_REVERSE(_reversed)
	33	MCFG_MSC1937_PORT(_val)
	34
41	35	#define MCFG_MSC1937_PORT(_val) \
42	36	MCFG_ROC10937_PORT(_val)
43	37
44		#define MCFG_MSC1937_REVERSE(_reversed) \
45		roc10937_t::static_set_zero(*device, _reversed);
46	38	#define MCFG_MSC1937_REMOVE(_tag) \
47	39	MCFG_DEVICE_REMOVE(_tag)
48	40
	41	#define MCFG_S16LF01_ADD(_tag,_val) \
	42	MCFG_DEVICE_ADD(_tag, S16LF01,60)\
	43	MCFG_S16LF01_PORT(_val)
49	44
	45	#define MCFG_S16LF01_PORT(_val) \
	46	MCFG_ROC10937_PORT(_val)
	47
50	48	class rocvfd_t : public device_t {
51	49	public:
52	50	rocvfd_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
53	51
54	52	// inline configuration helpers
55	53	static void static_set_value(device_t &device, int val);
56		static void static_set_zero(device_t &device, bool reversed);
57	54	virtual void update_display();
58	55	UINT8   m_port_val;
59		bool m_reversed;
60	56	void blank(int data);
61	57	void shift_data(int data);
62	58	void write_char(int data);
r29505	r29506
110	106
111	107	};
112	108
	109	class s16lf01_t : public rocvfd_t {
	110	public:
	111	s16lf01_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	112
	113	virtual void update_display();
	114	protected:
	115
	116	};
	117
113	118	extern const device_type ROC10937;
114	119	extern const device_type MSC1937;
115	120	extern const device_type ROC10957;
	121	extern const device_type S16LF01;
116	122
117	123	#endif

branches/new_menus/src/emu/machine/i8279.c

r29505	r29506
88	88	//-------------------------------------------------
89	89
90	90	i8279_device::i8279_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
91		: device_t(mconfig, I8279, "8279 KDC", tag, owner, clock, "i8279", __FILE__)
	91	: device_t(mconfig, I8279, "8279 KDC", tag, owner, clock, "i8279", __FILE__),
	92	m_out_irq_cb(*this),
	93	m_out_sl_cb(*this),
	94	m_out_disp_cb(*this),
	95	m_out_bd_cb(*this),
	96	m_in_rl_cb(*this),
	97	m_in_shift_cb(*this),
	98	m_in_ctrl_cb(*this)
92	99	{
93	100	}
94	101
95	102	//-------------------------------------------------
96		//  device_config_complete - perform any
97		//  operations now that the configuration is
98		//  complete
99		//-------------------------------------------------
100
101		void i8279_device::device_config_complete()
102		{
103		// inherit a copy of the static data
104		const i8279_interface *intf = reinterpret_cast<const i8279_interface *>(static_config());
105		if (intf != NULL)
106		{
107		*static_cast<i8279_interface *>(this) = *intf;
108		}
109
110		// or initialize to defaults if none provided
111		else
112		{
113		memset(&m_out_irq_cb, 0, sizeof(m_out_irq_cb));
114		memset(&m_out_sl_cb, 0, sizeof(m_out_sl_cb));
115		memset(&m_out_disp_cb, 0, sizeof(m_out_disp_cb));
116		memset(&m_out_bd_cb, 0, sizeof(m_out_bd_cb));
117		memset(&m_in_rl_cb, 0, sizeof(m_in_rl_cb));
118		memset(&m_in_shift_cb, 0, sizeof(m_in_shift_cb));
119		memset(&m_in_ctrl_cb, 0, sizeof(m_in_ctrl_cb));
120		}
121		}
122
123
124		//-------------------------------------------------
125	103	//  device_start - device-specific startup
126	104	//-------------------------------------------------
127	105
128	106	void i8279_device::device_start()
129	107	{
130	108	/* resolve callbacks */
131		m_out_irq_func.resolve(m_out_irq_cb, *this);
132		m_out_sl_func.resolve(m_out_sl_cb, *this);
133		m_out_disp_func.resolve(m_out_disp_cb, *this);
134		m_out_bd_func.resolve(m_out_bd_cb, *this);
135		m_in_rl_func.resolve(m_in_rl_cb, *this);
136		m_in_shift_func.resolve(m_in_shift_cb, *this);
137		m_in_ctrl_func.resolve(m_in_ctrl_cb, *this);
	109	m_out_irq_cb.resolve();
	110	m_out_sl_cb.resolve();
	111	m_out_disp_cb.resolve();
	112	m_out_bd_cb.resolve();
	113	m_in_rl_cb.resolve();
	114	m_in_shift_cb.resolve();
	115	m_in_ctrl_cb.resolve();
138	116	m_clock = clock();
139		m_timer = machine().scheduler().timer_alloc(FUNC(timerproc_callback), (void *)this);
	117	m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(i8279_device::timerproc_callback), this));
140	118	}
141	119
142	120
r29505	r29506
218	196
219	197	void i8279_device::set_irq(bool state)
220	198	{
221		if ( !m_out_irq_func.isnull() )
222		m_out_irq_func( state );
	199	if ( !m_out_irq_cb.isnull() )
	200	m_out_irq_cb( state );
223	201	}
224	202
225	203
r29505	r29506
267	245	}
268	246
269	247
270		TIMER_CALLBACK( i8279_device::timerproc_callback )
	248	TIMER_CALLBACK_MEMBER( i8279_device::timerproc_callback )
271	249	{
272		reinterpret_cast<i8279_device*>(ptr)->timer_mainloop();
	250	timer_mainloop();
273	251	}
274	252
275	253
r29505	r29506
295	273	// type 3 = strobed
296	274
297	275	// Get shift keys
298		if ( !m_in_shift_func.isnull() )
299		shift_key = m_in_shift_func();
	276	if ( !m_in_shift_cb.isnull() )
	277	shift_key = m_in_shift_cb();
300	278
301		if ( !m_in_ctrl_func.isnull() )
302		ctrl_key = m_in_ctrl_func();
	279	if ( !m_in_ctrl_cb.isnull() )
	280	ctrl_key = m_in_ctrl_cb();
303	281
304	282	if (ctrl_key && !m_ctrl_key)
305	283	strobe_pulse = 1; // low-to-high is a strobe
r29505	r29506
308	286
309	287	// Read a row of keys
310	288
311		if ( !m_in_rl_func.isnull() )
	289	if ( !m_in_rl_cb.isnull() )
312	290	{
313		UINT8 rl = m_in_rl_func(0);
	291	UINT8 rl = m_in_rl_cb(0);
314	292
315	293	// see if key still down from last time
316	294	UINT16 key_down = (m_scanner << 8) | rl;
r29505	r29506
367	345
368	346	m_scanner &= scanner_mask; // 4-bit port
369	347
370		if ( !m_out_sl_func.isnull() )
371		m_out_sl_func(0, m_scanner);
	348	if ( !m_out_sl_cb.isnull() )
	349	m_out_sl_cb((offs_t)0, m_scanner);
372	350
373	351	// output a digit
374	352
375		if ( !m_out_disp_func.isnull() )
376		m_out_disp_func(0, m_d_ram[m_scanner] );
	353	if ( !m_out_disp_cb.isnull() )
	354	m_out_disp_cb((offs_t)0, m_d_ram[m_scanner] );
377	355	}
378	356
379	357

branches/new_menus/src/emu/machine/i8279.h

r29505	r29506
44	44	DEVICE CONFIGURATION MACROS
45	45	***************************************************************************/
46	46
47		#define MCFG_I8279_ADD(_tag, _clock, _config) \
48		MCFG_DEVICE_ADD(_tag, I8279, _clock) \
49		MCFG_DEVICE_CONFIG(_config)
	47	#define MCFG_I8279_OUT_IRQ_CB(_devcb) \
	48	devcb = &i8279_device::set_out_irq_callback(*device, DEVCB2_##_devcb);
50	49
51		#define I8279_INTERFACE(_name) \
52		const i8279_interface (_name) =
	50	#define MCFG_I8279_OUT_SL_CB(_devcb) \
	51	devcb = &i8279_device::set_out_sl_callback(*device, DEVCB2_##_devcb);
53	52
	53	#define MCFG_I8279_OUT_DISP_CB(_devcb) \
	54	devcb = &i8279_device::set_out_disp_callback(*device, DEVCB2_##_devcb);
54	55
55		/***************************************************************************
56		TYPE DEFINITIONS
57		***************************************************************************/
	56	#define MCFG_I8279_OUT_BD_CB(_devcb) \
	57	devcb = &i8279_device::set_out_bd_callback(*device, DEVCB2_##_devcb);
58	58
	59	#define MCFG_I8279_IN_RL_CB(_devcb) \
	60	devcb = &i8279_device::set_in_rl_callback(*device, DEVCB2_##_devcb);
59	61
60		// ======================> i8279_interface
	62	#define MCFG_I8279_IN_SHIFT_CB(_devcb) \
	63	devcb = &i8279_device::set_in_shift_callback(*device, DEVCB2_##_devcb);
61	64
62		struct i8279_interface
63		{
64		devcb_write_line    m_out_irq_cb;       // IRQ
65		devcb_write8        m_out_sl_cb;        // Scanlines SL0-3
66		devcb_write8        m_out_disp_cb;      // B0-3,A0-3
67		devcb_write_line    m_out_bd_cb;        // BD
68		devcb_read8     m_in_rl_cb;     // kbd readlines RL0-7
69		devcb_read_line     m_in_shift_cb;      // Shift key
70		devcb_read_line     m_in_ctrl_cb;       // Ctrl-Strobe line
71		};
	65	#define MCFG_I8279_IN_CTRL_CB(_devcb) \
	66	devcb = &i8279_device::set_in_ctrl_callback(*device, DEVCB2_##_devcb);
72	67
	68	/***************************************************************************
	69	TYPE DEFINITIONS
	70	***************************************************************************/
73	71
74
75	72	// ======================> i8279_device
76	73
77		class i8279_device :  public device_t, public i8279_interface
	74	class i8279_device :  public device_t
78	75	{
79	76	public:
80	77	// construction/destruction
81	78	i8279_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
82	79
	80	template<class _Object> static devcb2_base &set_out_irq_callback(device_t &device, _Object object) { return downcast<i8279_device &>(device).m_out_irq_cb.set_callback(object); }
	81	template<class _Object> static devcb2_base &set_out_sl_callback(device_t &device, _Object object) { return downcast<i8279_device &>(device).m_out_sl_cb.set_callback(object); }
	82	template<class _Object> static devcb2_base &set_out_disp_callback(device_t &device, _Object object) { return downcast<i8279_device &>(device).m_out_disp_cb.set_callback(object); }
	83	template<class _Object> static devcb2_base &set_out_bd_callback(device_t &device, _Object object) { return downcast<i8279_device &>(device).m_out_bd_cb.set_callback(object); }
	84	template<class _Object> static devcb2_base &set_in_rl_callback(device_t &device, _Object object) { return downcast<i8279_device &>(device).m_in_rl_cb.set_callback(object); }
	85	template<class _Object> static devcb2_base &set_in_shift_callback(device_t &device, _Object object) { return downcast<i8279_device &>(device).m_in_shift_cb.set_callback(object); }
	86	template<class _Object> static devcb2_base &set_in_ctrl_callback(device_t &device, _Object object) { return downcast<i8279_device &>(device).m_in_ctrl_cb.set_callback(object); }
	87
83	88	// read & write handlers
84	89	DECLARE_READ8_MEMBER(status_r);
85	90	DECLARE_READ8_MEMBER(data_r);
r29505	r29506
89	94
90	95	protected:
91	96	// device-level overrides
92		virtual void device_config_complete();
93	97	virtual void device_start();
94	98	virtual void device_reset();
95	99	virtual void device_post_load() { }
96	100	virtual void device_clock_changed() { }
97	101
98		static TIMER_CALLBACK( timerproc_callback );
	102	TIMER_CALLBACK_MEMBER( timerproc_callback );
99	103
100	104	private:
101	105
r29505	r29506
107	111	void set_irq(bool state);
108	112	void set_display_mode(UINT8 data);
109	113
110		devcb_resolved_write_line   m_out_irq_func;
111		devcb_resolved_write8       m_out_sl_func;
112		devcb_resolved_write8       m_out_disp_func;
113		devcb_resolved_write_line   m_out_bd_func;
114		devcb_resolved_read8        m_in_rl_func;
115		devcb_resolved_read_line    m_in_shift_func;
116		devcb_resolved_read_line    m_in_ctrl_func;
	114	devcb2_write_line    m_out_irq_cb;       // IRQ
	115	devcb2_write8        m_out_sl_cb;        // Scanlines SL0-3
	116	devcb2_write8        m_out_disp_cb;      // B0-3,A0-3
	117	devcb2_write_line    m_out_bd_cb;        // BD
	118	devcb2_read8        m_in_rl_cb;        // kbd readlines RL0-7
	119	devcb2_read_line     m_in_shift_cb;      // Shift key
	120	devcb2_read_line     m_in_ctrl_cb;       // Ctrl-Strobe line
117	121
118	122	emu_timer *m_timer;
119	123

branches/new_menus/src/emu/machine/mb89352.c

r29505	r29506
109	109	const device_type MB89352A = &device_creator<mb89352_device>;
110	110
111	111
112		void mb89352_device::device_config_complete()
113		{
114		// copy static configuration if present
115		const mb89352_interface *intf = reinterpret_cast<const mb89352_interface *>(static_config());
116		if (intf != NULL)
117		*static_cast<mb89352_interface *>(this) = *intf;
118
119		// otherwise, initialize it to defaults
120		else
121		{
122		memset(&irq_callback,0,sizeof(irq_callback));
123		memset(&drq_callback,0,sizeof(drq_callback));
124		}
125		}
126
127	112	/*
128	113	* Device
129	114	*/
130	115
131	116	mb89352_device::mb89352_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
132		: device_t(mconfig, MB89352A, "MB89352A", tag, owner, clock, "mb89352", __FILE__)
	117	: device_t(mconfig, MB89352A, "MB89352A", tag, owner, clock, "mb89352", __FILE__),
	118	m_irq_cb(*this),
	119	m_drq_cb(*this)
133	120	{
134	121	}
135	122
r29505	r29506
146	133	m_spc_status |= SSTS_TC_ZERO;
147	134	m_ints = 0x00;
148	135
149		m_irq_func.resolve(irq_callback,*this);
150		m_drq_func.resolve(drq_callback,*this);
	136	m_irq_cb.resolve_safe();
	137	m_drq_cb.resolve_safe();
151	138
152	139	memset(m_SCSIdevices,0,sizeof(m_SCSIdevices));
153	140
r29505	r29506
204	191	case TIMER_TRANSFER:
205	192	// TODO: check interrupts are actually enabled
206	193	{
207		m_drq_func(1);
	194	m_drq_cb(1);
208	195	}
209	196	break;
210	197	}
r29505	r29506
325	312	m_spc_status |= SSTS_DREG_EMPTY;
326	313	m_ints |= INTS_COMMAND_COMPLETE;
327	314	if(m_int_enable != 0)
328		m_irq_func(1);
	315	m_irq_cb(1);
329	316	if(m_phase == SCSI_PHASE_MESSAGE_IN)
330	317	set_phase(SCSI_PHASE_BUS_FREE);
331	318	else if(m_phase == SCSI_PHASE_DATAIN)
r29505	r29506
427	414	if(m_busfree_int_enable)
428	415	{
429	416	if(m_int_enable != 0)
430		m_irq_func(1);
	417	m_irq_cb(1);
431	418	}
432	419	logerror("mb89352: SCMD: Bus free\n");
433	420	break;
r29505	r29506
458	445	m_spc_status |= SSTS_SPC_BSY;
459	446	m_ints |= INTS_COMMAND_COMPLETE;
460	447	if(m_int_enable != 0)
461		m_irq_func(1);
	448	m_irq_cb(1);
462	449	logerror("mb89352: SCMD: Selection (SCSI ID%i)\n",m_target);
463	450	break;
464	451	case 0x02:  // Reset ATN
r29505	r29506
558	545	break;
559	546	case 0x04:  // INTS - Interrupt Sense
560	547	m_ints &= ~data;  // resets relevant status bits to zero
561		m_irq_func(0);  // clear IRQ
	548	m_irq_cb(0);  // clear IRQ
562	549	logerror("mb89352: Reset INTS status bits %02x\n",data);
563	550	break;
564	551	case 0x08:  // PCTL - Phase control
r29505	r29506
613	600	m_spc_status |= SSTS_DREG_EMPTY;
614	601	m_ints |= INTS_COMMAND_COMPLETE;
615	602	if(m_int_enable != 0)
616		m_irq_func(1);
	603	m_irq_cb(1);
617	604	set_phase(SCSI_PHASE_STATUS);
618	605	}
619	606	}

branches/new_menus/src/emu/machine/mb89352.h

r29505	r29506
48	48	#define SERR_SCSI_PAR   0x80
49	49
50	50
51		struct mb89352_interface
52		{
53		devcb_write_line irq_callback;  /* irq callback */
54		devcb_write_line drq_callback;  /* drq callback */
55		};
	51	#define MCFG_MB89352A_IRQ_CB(_devcb) \
	52	devcb = &mb89352_device::set_irq_callback(*device, DEVCB2_##_devcb);
	53
	54	#define MCFG_MB89352A_DRQ_CB(_devcb) \
	55	devcb = &mb89352_device::set_drq_callback(*device, DEVCB2_##_devcb);
56	56
57		#define MCFG_MB89352A_ADD(_tag, _intrf) \
58		MCFG_DEVICE_ADD(_tag, MB89352A, 0) \
59		MCFG_DEVICE_CONFIG(_intrf)
60
61		class mb89352_device : public device_t,
62		public mb89352_interface
	57	class mb89352_device : public device_t
63	58	{
64	59	public:
65	60	// construction/destruction
66	61	mb89352_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
67	62
	63	template<class _Object> static devcb2_base &set_irq_callback(device_t &device, _Object object) { return downcast<mb89352_device &>(device).m_irq_cb.set_callback(object); }
	64	template<class _Object> static devcb2_base &set_drq_callback(device_t &device, _Object object) { return downcast<mb89352_device &>(device).m_drq_cb.set_callback(object); }
	65
68	66	// any publically accessible interfaces needed for runtime
69	67	DECLARE_READ8_MEMBER( mb89352_r );
70	68	DECLARE_WRITE8_MEMBER( mb89352_w );
r29505	r29506
77	75	virtual void device_start();
78	76	virtual void device_reset();
79	77	virtual void device_stop();
80		virtual void device_config_complete();
81	78	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
82	79
83	80	private:
r29505	r29506
87	84	int get_scsi_cmd_len(UINT8 cbyte);
88	85	//void set_ints(UINT8 flag);
89	86
90		devcb_resolved_write_line m_irq_func;
91		devcb_resolved_write_line m_drq_func;
	87	devcb2_write_line m_irq_cb;  /* irq callback */
	88	devcb2_write_line m_drq_cb;  /* drq callback */
92	89
93	90	scsihle_device* m_SCSIdevices[8];
94	91

branches/new_menus/src/emu/machine/ncr539x.c

r29505	r29506
104	104	return 6;
105	105	}
106	106
107		//-------------------------------------------------
108		//  device_config_complete - perform any
109		//  operations now that the configuration is
110		//  complete
111		//-------------------------------------------------
112
113		void ncr539x_device::device_config_complete()
114		{
115		// inherit a copy of the static data
116		const NCR539Xinterface *intf = reinterpret_cast<const NCR539Xinterface *>(static_config());
117		if (intf != NULL)
118		{
119		*static_cast<NCR539Xinterface *>(this) = *intf;
120		}
121
122		// or initialize to defaults if none provided
123		else
124		{
125		memset(&m_out_irq_cb, 0, sizeof(m_out_irq_cb));
126		memset(&m_out_drq_cb, 0, sizeof(m_out_drq_cb));
127		}
128		}
129
130	107	//**************************************************************************
131	108	//  LIVE DEVICE
132	109	//**************************************************************************
r29505	r29506
138	115	//-------------------------------------------------
139	116
140	117	ncr539x_device::ncr539x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
141		: device_t(mconfig, NCR539X, "539x SCSI", tag, owner, clock, "ncr539x", __FILE__)
	118	: device_t(mconfig, NCR539X, "539x SCSI", tag, owner, clock, "ncr539x", __FILE__),
	119	m_out_irq_cb(*this),
	120	m_out_drq_cb(*this)
142	121	{
143	122	}
144	123
r29505	r29506
151	130	memset(m_scsi_devices, 0, sizeof(m_scsi_devices));
152	131
153	132	// resolve line callbacks
154		m_out_irq_func.resolve(m_out_irq_cb, *this);
155		m_out_drq_func.resolve(m_out_drq_cb, *this);
	133	m_out_irq_cb.resolve_safe();
	134	m_out_drq_cb.resolve_safe();
156	135
157	136	// try to open the devices
158	137	for( device_t *device = owner()->first_subdevice(); device != NULL; device = device->next() )
r29505	r29506
189	168	m_chipid_available = false;
190	169	m_chipid_lock = false;
191	170
192		m_out_irq_func(CLEAR_LINE);
193		m_out_drq_func(CLEAR_LINE);
	171	m_out_irq_cb(CLEAR_LINE);
	172	m_out_drq_cb(CLEAR_LINE);
194	173	}
195	174
196	175	void ncr539x_device::dma_read_data(int bytes, UINT8 *pData)
r29505	r29506
233	212	// if this is a DMA command, raise DRQ now
234	213	if (m_command & 0x80)
235	214	{
236		m_out_drq_func(ASSERT_LINE);
	215	m_out_drq_cb(ASSERT_LINE);
237	216	}
238	217
239	218	switch (m_command & 0x7f)
r29505	r29506
267	246	m_status |= MAIN_STATUS_INTERRUPT;
268	247	m_irq_status |= IRQ_STATUS_DISCONNECTED;
269	248	}
270		m_out_irq_func(ASSERT_LINE);
	249	m_out_irq_cb(ASSERT_LINE);
271	250	break;
272	251
273	252	case 0x42:  // Select with ATN steps
r29505	r29506
298	277	m_status |= MAIN_STATUS_INTERRUPT;
299	278	m_irq_status |= IRQ_STATUS_DISCONNECTED;
300	279	}
301		m_out_irq_func(ASSERT_LINE);
	280	m_out_irq_cb(ASSERT_LINE);
302	281	break;
303	282
304	283	case 0x11:  // initiator command complete
r29505	r29506
308	287	m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
309	288	m_status &= ~7; // clear phase bits
310	289	m_status |= MAIN_STATUS_INTERRUPT | SCSI_PHASE_DATAIN;  // go to data in phase (?)
311		m_out_irq_func(ASSERT_LINE);
	290	m_out_irq_cb(ASSERT_LINE);
312	291
313	292	// this puts status and message bytes into the FIFO (todo: what are these?)
314	293	m_fifo_ptr = 0;
r29505	r29506
326	305	#endif
327	306	m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
328	307	m_status |= MAIN_STATUS_INTERRUPT;
329		m_out_irq_func(ASSERT_LINE);
	308	m_out_irq_cb(ASSERT_LINE);
330	309	break;
331	310
332	311	default:
r29505	r29506
407	386	m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
408	387	m_status &= 0x7;    // clear everything but the phase bits
409	388	m_status |= MAIN_STATUS_INTERRUPT | MAIN_STATUS_COUNT_TO_ZERO;
410		m_out_irq_func(ASSERT_LINE);
	389	m_out_irq_cb(ASSERT_LINE);
411	390
412	391	// if no data at all, drop the phase
413	392	if ((m_buffer_remaining + m_total_data) == 0)
r29505	r29506
436	415	rv = m_irq_status;
437	416	// clear the interrupt state
438	417	m_status &= ~MAIN_STATUS_INTERRUPT;
439		m_out_irq_func(CLEAR_LINE);
	418	m_out_irq_cb(CLEAR_LINE);
440	419	break;
441	420
442	421	case 6:
r29505	r29506
515	494	case 0x00:  // NOP
516	495	m_irq_status = IRQ_STATUS_SUCCESS;
517	496	m_status |= MAIN_STATUS_INTERRUPT;
518		m_out_irq_func(ASSERT_LINE);
	497	m_out_irq_cb(ASSERT_LINE);
519	498
520	499	// DMA NOP?  allow chip ID
521	500	if ((m_command == 0x80) && (!m_chipid_lock))
r29505	r29506
529	508	update_fifo_internal_state(0);
530	509	m_irq_status = IRQ_STATUS_SUCCESS;
531	510	m_status |= MAIN_STATUS_INTERRUPT;
532		m_out_irq_func(ASSERT_LINE);
	511	m_out_irq_cb(ASSERT_LINE);
533	512	break;
534	513
535	514	case 0x02:  // Reset device
r29505	r29506
537	516
538	517	m_irq_status = IRQ_STATUS_SUCCESS;
539	518	m_status |= MAIN_STATUS_INTERRUPT;
540		m_out_irq_func(ASSERT_LINE);
	519	m_out_irq_cb(ASSERT_LINE);
541	520	break;
542	521
543	522	case 0x03:  // Reset SCSI bus
544	523	m_status = 0;
545	524	m_irq_status = IRQ_STATUS_SUCCESS;
546	525	m_status |= MAIN_STATUS_INTERRUPT;
547		m_out_irq_func(ASSERT_LINE);
	526	m_out_irq_cb(ASSERT_LINE);
548	527	break;
549	528
550	529	case 0x10:  // information transfer (must happen immediately)
r29505	r29506
611	590	m_xfer_count = m_dma_size;
612	591	m_fifo_ptr = 0;
613	592	update_fifo_internal_state(fifo_fill_size);
614		m_out_drq_func(ASSERT_LINE);
	593	m_out_drq_cb(ASSERT_LINE);
615	594	}
616	595
617	596	m_status |= MAIN_STATUS_COUNT_TO_ZERO;
r29505	r29506
635	614	m_buffer_offset = 0;
636	615	m_buffer_remaining = 0;
637	616	}
638		m_out_irq_func(ASSERT_LINE);
	617	m_out_irq_cb(ASSERT_LINE);
639	618	break;
640	619
641	620	case 0x24:  // Terminate steps
r29505	r29506
644	623	#endif
645	624	m_irq_status = IRQ_STATUS_SUCCESS | IRQ_STATUS_DISCONNECTED;
646	625	m_status |= MAIN_STATUS_INTERRUPT;
647		m_out_irq_func(ASSERT_LINE);
	626	m_out_irq_cb(ASSERT_LINE);
648	627	m_fifo_ptr = 0;
649	628	update_fifo_internal_state(0);
650	629	break;
r29505	r29506
655	634	#endif
656	635	m_irq_status = IRQ_STATUS_SUCCESS;
657	636	m_status |= MAIN_STATUS_INTERRUPT;
658		m_out_irq_func(ASSERT_LINE);
	637	m_out_irq_cb(ASSERT_LINE);
659	638	break;
660	639
661	640	case 0x44:  // Enable selection/reselection
r29505	r29506
664	643	#endif
665	644	m_irq_status = IRQ_STATUS_SUCCESS;
666	645	m_status |= MAIN_STATUS_INTERRUPT;
667		m_out_irq_func(ASSERT_LINE);
	646	m_out_irq_cb(ASSERT_LINE);
668	647	break;
669	648
670	649	case 0x47:  // Reselect with ATN3 steps
r29505	r29506
695	674	m_status |= MAIN_STATUS_INTERRUPT;
696	675	m_irq_status |= IRQ_STATUS_DISCONNECTED;
697	676	}
698		m_out_irq_func(ASSERT_LINE);
	677	m_out_irq_cb(ASSERT_LINE);
699	678	break;
700	679
701	680	default:    // other commands are not instantaneous
r29505	r29506
846	825	m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
847	826	m_status &= 7;
848	827	m_status |= MAIN_STATUS_INTERRUPT;
849		m_out_irq_func(ASSERT_LINE);
	828	m_out_irq_cb(ASSERT_LINE);
850	829	}
851	830
852	831	if ((m_xfer_count == 0) && (m_total_data == 0))
r29505	r29506
858	837	m_buffer_offset = 0;
859	838	m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
860	839	m_status = MAIN_STATUS_INTERRUPT | SCSI_PHASE_STATUS;
861		m_out_irq_func(ASSERT_LINE);
	840	m_out_irq_cb(ASSERT_LINE);
862	841	}
863	842	}
864	843	}

branches/new_menus/src/emu/machine/ncr539x.h

r29505	r29506
8	8
9	9	#include "machine/scsihle.h"
10	10
11		struct NCR539Xinterface
12		{
13		devcb_write_line m_out_irq_cb;          /* IRQ line */
14		devcb_write_line m_out_drq_cb;          /* DRQ line */
15		};
16
17	11	//// 539x registers
18	12	//enum
19	13	//{
20	14	//};
21	15
22	16	// device stuff
23		#define MCFG_NCR539X_ADD(_tag, _clock, _intrf) \
24		MCFG_DEVICE_ADD(_tag, NCR539X, _clock) \
25		MCFG_DEVICE_CONFIG(_intrf)
26	17
27		class ncr539x_device : public device_t,
28		public NCR539Xinterface
	18	#define MCFG_NCR539X_OUT_IRQ_CB(_devcb) \
	19	devcb = &ncr539x_device::set_out_irq_callback(*device, DEVCB2_##_devcb);
	20
	21	#define MCFG_NCR539X_OUT_DRQ_CB(_devcb) \
	22	devcb = &ncr539x_device::set_out_drq_callback(*device, DEVCB2_##_devcb);
	23
	24
	25	class ncr539x_device : public device_t
29	26	{
30	27	public:
31	28	// construction/destruction
32	29	ncr539x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	30
	31	template<class _Object> static devcb2_base &set_out_irq_callback(device_t &device, _Object object) { return downcast<ncr539x_device &>(device).m_out_irq_cb.set_callback(object); }
	32	template<class _Object> static devcb2_base &set_out_drq_callback(device_t &device, _Object object) { return downcast<ncr539x_device &>(device).m_out_drq_cb.set_callback(object); }
33	33
34	34	// our API
35	35	DECLARE_READ8_MEMBER(read);
r29505	r29506
42	42	// device-level overrides
43	43	virtual void device_start();
44	44	virtual void device_reset();
45		virtual void device_config_complete();
46	45	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
47	46
48	47	private:
r29505	r29506
83	82
84	83	emu_timer *m_operation_timer;
85	84
86		devcb_resolved_write_line   m_out_irq_func;
87		devcb_resolved_write_line   m_out_drq_func;
	85	devcb2_write_line m_out_irq_cb;          /* IRQ line */
	86	devcb2_write_line m_out_drq_cb;          /* DRQ line */
88	87	};
89	88
90	89	// device type definition

branches/new_menus/src/emu/machine/wd2010.c

r29505	r29506
99	99	const device_type WD2010 = &device_creator<wd2010_device>;
100	100
101	101
102		//-------------------------------------------------
103		//  device_config_complete - perform any
104		//  operations now that the configuration is
105		//  complete
106		//-------------------------------------------------
107
108		void wd2010_device::device_config_complete()
109		{
110		// inherit a copy of the static data
111		const wd2010_interface *intf = reinterpret_cast<const wd2010_interface *>(static_config());
112		if (intf != NULL)
113		*static_cast<wd2010_interface *>(this) = *intf;
114
115		// or initialize to defaults if none provided
116		else
117		{
118		memset(&m_out_intrq_cb, 0, sizeof(m_out_intrq_cb));
119		memset(&m_out_bdrq_cb, 0, sizeof(m_out_bdrq_cb));
120		memset(&m_out_bcr_cb, 0, sizeof(m_out_bcr_cb));
121		memset(&m_in_bcs_cb, 0, sizeof(m_in_bcs_cb));
122		memset(&m_out_bcs_cb, 0, sizeof(m_out_bcs_cb));
123		memset(&m_out_dirin_cb, 0, sizeof(m_out_dirin_cb));
124		memset(&m_out_step_cb, 0, sizeof(m_out_step_cb));
125		memset(&m_out_rwc_cb, 0, sizeof(m_out_rwc_cb));
126		memset(&m_in_drdy_cb, 0, sizeof(m_in_drdy_cb));
127		memset(&m_in_index_cb, 0, sizeof(m_in_index_cb));
128		memset(&m_in_wf_cb, 0, sizeof(m_in_wf_cb));
129		memset(&m_in_tk000_cb, 0, sizeof(m_in_tk000_cb));
130		memset(&m_in_sc_cb, 0, sizeof(m_in_sc_cb));
131		}
132		}
133
134
135
136	102	//**************************************************************************
137	103	//  LIVE DEVICE
138	104	//**************************************************************************
r29505	r29506
143	109
144	110	wd2010_device::wd2010_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
145	111	: device_t(mconfig, WD2010, "Western Digital WD2010", tag, owner, clock, "wd2010", __FILE__),
	112	m_out_intrq_cb(*this),
	113	m_out_bdrq_cb(*this),
	114	m_out_bcr_cb(*this),
	115	m_in_bcs_cb(*this),
	116	m_out_bcs_cb(*this),
	117	m_out_dirin_cb(*this),
	118	m_out_step_cb(*this),
	119	m_out_rwc_cb(*this),
	120	m_in_drdy_cb(*this),
	121	m_in_index_cb(*this),
	122	m_in_wf_cb(*this),
	123	m_in_tk000_cb(*this),
	124	m_in_sc_cb(*this),
146	125	m_status(0),
147	126	m_error(0)
148	127	{
r29505	r29506
156	135	void wd2010_device::device_start()
157	136	{
158	137	// resolve callbacks
159		m_out_intrq_func.resolve(m_out_intrq_cb, *this);
160		m_out_bdrq_func.resolve(m_out_bdrq_cb, *this);
161		m_out_bcr_func.resolve(m_out_bcr_cb, *this);
162		m_in_bcs_func.resolve(m_in_bcs_cb, *this);
163		m_out_bcs_func.resolve(m_out_bcs_cb, *this);
164		m_out_dirin_func.resolve(m_out_dirin_cb, *this);
165		m_out_step_func.resolve(m_out_step_cb, *this);
166		m_out_rwc_func.resolve(m_out_rwc_cb, *this);
167		m_in_drdy_func.resolve(m_in_drdy_cb, *this);
168		m_in_index_func.resolve(m_in_index_cb, *this);
169		m_in_wf_func.resolve(m_in_wf_cb, *this);
170		m_in_tk000_func.resolve(m_in_tk000_cb, *this);
171		m_in_sc_func.resolve(m_in_sc_cb, *this);
	138	m_out_intrq_cb.resolve_safe();
	139	m_out_bdrq_cb.resolve_safe();
	140	m_out_bcr_cb.resolve_safe();
	141	m_in_bcs_cb.resolve_safe(0);
	142	m_out_bcs_cb.resolve_safe();
	143	m_out_dirin_cb.resolve_safe();
	144	m_out_step_cb.resolve_safe();
	145	m_out_rwc_cb.resolve_safe();
	146	m_in_drdy_cb.resolve_safe(0);
	147	m_in_index_cb.resolve_safe(0);
	148	m_in_wf_cb.resolve_safe(0);
	149	m_in_tk000_cb.resolve_safe(0);
	150	m_in_sc_cb.resolve_safe(0);
172	151	}
173	152
174	153
r29505	r29506
196	175	break;
197	176
198	177	case TASK_FILE_STATUS:
199		m_out_intrq_func(CLEAR_LINE);
	178	m_out_intrq_cb(CLEAR_LINE);
200	179	data = m_status | STATUS_RDY | STATUS_SC;
201	180	break;
202	181
r29505	r29506
324	303	void wd2010_device::restore(UINT8 data)
325	304	{
326	305	// reset INTRQ, errors, set BUSY, CIP
327		m_out_intrq_func(CLEAR_LINE);
	306	m_out_intrq_cb(CLEAR_LINE);
328	307	m_error = 0;
329	308	m_status = STATUS_BSY | STATUS_CIP;
330	309
331	310	// reset RWC, set direction=OUT, store step rate
332		m_out_rwc_func(0);
333		m_out_dirin_func(0);
	311	m_out_rwc_cb(0);
	312	m_out_dirin_cb(0);
334	313
335	314	int step_pulses = 0;
336	315
337	316	while (step_pulses < 2048)
338	317	{
339		while (!m_in_sc_func())
	318	while (!m_in_sc_cb())
340	319	{
341	320	// drive not ready or write fault?
342		if (!m_in_drdy_func() || m_in_wf_func())
	321	if (!m_in_drdy_cb() || m_in_wf_cb())
343	322	{
344	323	// pulse BCR, set AC, INTRQ, reset BSY, CIP
345		m_out_bcr_func(0);
346		m_out_bcr_func(1);
	324	m_out_bcr_cb(0);
	325	m_out_bcr_cb(1);
347	326	m_error = ERROR_AC;
348		m_status = (m_in_drdy_func() << 6) | (m_in_wf_func() << 5) | STATUS_ERR;
349		m_out_intrq_func(ASSERT_LINE);
	327	m_status = (m_in_drdy_cb() << 6) | (m_in_wf_cb() << 5) | STATUS_ERR;
	328	m_out_intrq_cb(ASSERT_LINE);
350	329	return;
351	330	}
352	331	}
353	332
354		if (m_in_tk000_func())
	333	if (m_in_tk000_cb())
355	334	{
356	335	// pulse BCR, set INTRQ, reset BSY, CIP
357		m_out_bcr_func(0);
358		m_out_bcr_func(1);
	336	m_out_bcr_cb(0);
	337	m_out_bcr_cb(1);
359	338	m_status &= ~(STATUS_BSY | STATUS_CIP);
360		m_out_intrq_func(ASSERT_LINE);
	339	m_out_intrq_cb(ASSERT_LINE);
361	340	return;
362	341	}
363	342
r29505	r29506
368	347	m_status |= STATUS_ERR;
369	348
370	349	// pulse BCR, set INTRQ, reset BSY, CIP
371		m_out_bcr_func(0);
372		m_out_bcr_func(1);
	350	m_out_bcr_cb(0);
	351	m_out_bcr_cb(1);
373	352	m_status &= ~(STATUS_BSY | STATUS_CIP);
374		m_out_intrq_func(ASSERT_LINE);
	353	m_out_intrq_cb(ASSERT_LINE);
375	354	return;
376	355	}
377	356
378	357	// issue a step pulse
379		m_out_step_func(1);
380		m_out_step_func(0);
	358	m_out_step_cb(1);
	359	m_out_step_cb(0);
381	360	step_pulses++;
382	361	}
383	362	}

branches/new_menus/src/emu/machine/wd2010.h

r29505	r29506
23	23	//  INTERFACE CONFIGURATION MACROS
24	24	//**************************************************************************
25	25
26		#define MCFG_WD2010_ADD(_tag, _clock, _config) \
27		MCFG_DEVICE_ADD(_tag, WD2010, _clock) \
28		MCFG_DEVICE_CONFIG(_config)
	26	#define MCFG_WD2010_OUT_INTRQ_CB(_devcb) \
	27	devcb = &wd2010_device::set_out_intrq_callback(*device, DEVCB2_##_devcb);
29	28
	29	#define MCFG_WD2010_OUT_BDRQ_CB(_devcb) \
	30	devcb = &wd2010_device::set_out_bdrq_callback(*device, DEVCB2_##_devcb);
30	31
31		#define WD2010_INTERFACE(_name) \
32		const wd2010_interface (_name) =
	32	#define MCFG_WD2010_OUT_BCR_CB(_devcb) \
	33	devcb = &wd2010_device::set_out_bcr_callback(*device, DEVCB2_##_devcb);
33	34
	35	#define MCFG_WD2010_IN_BCS_CB(_devcb) \
	36	devcb = &wd2010_device::set_in_bcs_callback(*device, DEVCB2_##_devcb);
34	37
	38	#define MCFG_WD2010_OUT_BCS_CB(_devcb) \
	39	devcb = &wd2010_device::set_out_bcs_callback(*device, DEVCB2_##_devcb);
35	40
	41	#define MCFG_WD2010_OUT_DIRIN_CB(_devcb) \
	42	devcb = &wd2010_device::set_out_dirin_callback(*device, DEVCB2_##_devcb);
	43
	44	#define MCFG_WD2010_OUT_STEP_CB(_devcb) \
	45	devcb = &wd2010_device::set_out_step_callback(*device, DEVCB2_##_devcb);
	46
	47	#define MCFG_WD2010_OUT_RWC_CB(_devcb) \
	48	devcb = &wd2010_device::set_out_rwc_callback(*device, DEVCB2_##_devcb);
	49
	50	#define MCFG_WD2010_IN_DRDY_CB(_devcb) \
	51	devcb = &wd2010_device::set_in_drdy_callback(*device, DEVCB2_##_devcb);
	52
	53	#define MCFG_WD2010_IN_INDEX_CB(_devcb) \
	54	devcb = &wd2010_device::set_in_index_callback(*device, DEVCB2_##_devcb);
	55
	56	#define MCFG_WD2010_IN_WF_CB(_devcb) \
	57	devcb = &wd2010_device::set_in_wf_callback(*device, DEVCB2_##_devcb);
	58
	59	#define MCFG_WD2010_IN_TK000_CB(_devcb) \
	60	devcb = &wd2010_device::set_in_tk000_callback(*device, DEVCB2_##_devcb);
	61
	62	#define MCFG_WD2010_IN_SC_CB(_devcb) \
	63	devcb = &wd2010_device::set_in_sc_callback(*device, DEVCB2_##_devcb);
	64
36	65	//**************************************************************************
37	66	//  TYPE DEFINITIONS
38	67	//**************************************************************************
39	68
40		// ======================> wd2010_interface
41
42		struct wd2010_interface
43		{
44		devcb_write_line    m_out_intrq_cb;
45		devcb_write_line    m_out_bdrq_cb;
46		devcb_write_line    m_out_bcr_cb;
47		devcb_read8         m_in_bcs_cb;
48		devcb_write8        m_out_bcs_cb;
49		devcb_write_line    m_out_dirin_cb;
50		devcb_write_line    m_out_step_cb;
51		devcb_write_line    m_out_rwc_cb;
52		devcb_read_line     m_in_drdy_cb;
53		devcb_read_line     m_in_index_cb;
54		devcb_read_line     m_in_wf_cb;
55		devcb_read_line     m_in_tk000_cb;
56		devcb_read_line     m_in_sc_cb;
57		};
58
59
60	69	// ======================> wd2010_device
61	70
62		class wd2010_device :   public device_t,
63		public wd2010_interface
	71	class wd2010_device :   public device_t
64	72	{
65	73	public:
66	74	// construction/destruction
67	75	wd2010_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
68	76
	77	template<class _Object> static devcb2_base &set_out_intrq_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_out_intrq_cb.set_callback(object); }
	78	template<class _Object> static devcb2_base &set_out_bdrq_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_out_bdrq_cb.set_callback(object); }
	79	template<class _Object> static devcb2_base &set_out_bcr_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_out_bcr_cb.set_callback(object); }
	80	template<class _Object> static devcb2_base &set_in_bcs_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_in_bcs_cb.set_callback(object); }
	81	template<class _Object> static devcb2_base &set_out_bcs_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_out_bcs_cb.set_callback(object); }
	82	template<class _Object> static devcb2_base &set_out_dirin_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_out_dirin_cb.set_callback(object); }
	83	template<class _Object> static devcb2_base &set_out_step_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_out_step_cb.set_callback(object); }
	84	template<class _Object> static devcb2_base &set_out_rwc_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_out_rwc_cb.set_callback(object); }
	85	template<class _Object> static devcb2_base &set_in_drdy_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_in_drdy_cb.set_callback(object); }
	86	template<class _Object> static devcb2_base &set_in_index_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_in_index_cb.set_callback(object); }
	87	template<class _Object> static devcb2_base &set_in_wf_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_in_wf_cb.set_callback(object); }
	88	template<class _Object> static devcb2_base &set_in_tk000_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_in_tk000_cb.set_callback(object); }
	89	template<class _Object> static devcb2_base &set_in_sc_callback(device_t &device, _Object object) { return downcast<wd2010_device &>(device).m_in_sc_cb.set_callback(object); }
	90
69	91	DECLARE_READ8_MEMBER( read );
70	92	DECLARE_WRITE8_MEMBER( write );
71	93
r29505	r29506
73	95	// device-level overrides
74	96	virtual void device_start();
75	97	virtual void device_reset();
76		virtual void device_config_complete();
77	98
78	99	private:
79	100	void compute_correction(UINT8 data);
r29505	r29506
85	106	void scan_id(UINT8 data);
86	107	void format(UINT8 data);
87	108
88		devcb_resolved_write_line   m_out_intrq_func;
89		devcb_resolved_write_line   m_out_bdrq_func;
90		devcb_resolved_write_line   m_out_bcr_func;
91		devcb_resolved_read8        m_in_bcs_func;
92		devcb_resolved_write8       m_out_bcs_func;
93		devcb_resolved_write_line   m_out_dirin_func;
94		devcb_resolved_write_line   m_out_step_func;
95		devcb_resolved_write_line   m_out_rwc_func;
96		devcb_resolved_read_line    m_in_drdy_func;
97		devcb_resolved_read_line    m_in_index_func;
98		devcb_resolved_read_line    m_in_wf_func;
99		devcb_resolved_read_line    m_in_tk000_func;
100		devcb_resolved_read_line    m_in_sc_func;
	109	devcb2_write_line    m_out_intrq_cb;
	110	devcb2_write_line    m_out_bdrq_cb;
	111	devcb2_write_line    m_out_bcr_cb;
	112	devcb2_read8         m_in_bcs_cb;
	113	devcb2_write8        m_out_bcs_cb;
	114	devcb2_write_line    m_out_dirin_cb;
	115	devcb2_write_line    m_out_step_cb;
	116	devcb2_write_line    m_out_rwc_cb;
	117	devcb2_read_line     m_in_drdy_cb;
	118	devcb2_read_line     m_in_index_cb;
	119	devcb2_read_line     m_in_wf_cb;
	120	devcb2_read_line     m_in_tk000_cb;
	121	devcb2_read_line     m_in_sc_cb;
101	122
102	123	UINT8 m_status;
103	124	UINT8 m_error;

branches/new_menus/src/emu/machine/hd63450.c

r29505	r29506
83	83	}
84	84	}
85	85
	86	void hd63450_device::device_reset()
	87	{
	88	m_drq_state[0] = m_drq_state[1] = m_drq_state[2] = m_drq_state[3] = 0;
	89	}
	90
86	91	READ16_MEMBER(hd63450_device::read)
87	92	{
88	93	int channel,reg;
r29505	r29506
143	148	case 0x00:  // CSR / CER
144	149	if(ACCESSING_BITS_8_15)
145	150	{
146		//          m_reg[channel].csr = (data & 0xff00) >> 8;
	151	m_reg[channel].csr &= ~((data & 0xff00) >> 8);
147	152	//          logerror("DMA#%i: Channel status write : %02x\n",channel,dmac.reg[channel].csr);
148	153	}
149	154	// CER is read-only, so no action needed there.
r29505	r29506
170	175	{
171	176	m_reg[channel].ccr = data & 0x00ff;
172	177	if((data & 0x0080))// && !m_dma_read[channel] && !m_dma_write[channel])
173		dma_transfer_start(channel,0);
	178	dma_transfer_start(channel);
174	179	if(data & 0x0010)  // software abort
175	180	dma_transfer_abort(channel);
176	181	if(data & 0x0020)  // halt operation
r29505	r29506
243	248	}
244	249	}
245	250
246		void hd63450_device::dma_transfer_start(int channel, int dir)
	251	void hd63450_device::dma_transfer_start(int channel)
247	252	{
248	253	address_space &space = m_cpu->space(AS_PROGRAM);
249	254	m_in_progress[channel] = 1;
r29505	r29506
293	298
294	299	void hd63450_device::dma_transfer_abort(int channel)
295	300	{
	301	if(!m_in_progress[channel])
	302	return;
	303
296	304	logerror("DMA#%i: Transfer aborted\n",channel);
297		m_timer[channel]->adjust(attotime::zero);
	305	m_timer[channel]->adjust(attotime::never);
298	306	m_in_progress[channel] = 0;
299		m_reg[channel].mtc = m_transfer_size[channel];
300		m_reg[channel].csr |= 0xe0;  // channel operation complete, block transfer complete
	307	m_reg[channel].csr |= 0x90;  // channel error
301	308	m_reg[channel].csr &= ~0x08;  // channel no longer active
	309	m_reg[channel].cer = 0x11;
	310	m_reg[channel].ccr &= ~0xc0;
	311	m_dma_error((offs_t)3, 1);
302	312	}
303	313
304	314	void hd63450_device::dma_transfer_halt(int channel)
305	315	{
306	316	m_halted[channel] = 1;
307		m_timer[channel]->adjust(attotime::zero);
	317	m_timer[channel]->adjust(attotime::never);
308	318	}
309	319
310	320	void hd63450_device::dma_transfer_continue(int channel)
r29505	r29506
478	488	m_in_progress[x] = 0;
479	489	m_reg[x].csr |= 0xe0;  // channel operation complete, block transfer complete
480	490	m_reg[x].csr &= ~0x08;  // channel no longer active
	491	m_reg[x].ccr &= ~0xc0;
481	492
482	493	// Burst transfer
483	494	if((m_reg[x].dcr & 0xc0) == 0x00)
r29505	r29506
491	502	}
492	503	}
493	504
	505	WRITE_LINE_MEMBER(hd63450_device::drq0_w)
	506	{
	507	bool ostate = m_drq_state[0];
	508	m_drq_state[0] = state;
	509
	510	if((m_reg[0].ocr & 2) && (state && !ostate))
	511	single_transfer(0);
	512	}
	513
	514	WRITE_LINE_MEMBER(hd63450_device::drq1_w)
	515	{
	516	bool ostate = m_drq_state[1];
	517	m_drq_state[1] = state;
	518
	519	if((m_reg[1].ocr & 2) && (state && !ostate))
	520	single_transfer(1);
	521	}
	522
	523	WRITE_LINE_MEMBER(hd63450_device::drq2_w)
	524	{
	525	bool ostate = m_drq_state[2];
	526	m_drq_state[2] = state;
	527
	528	if((m_reg[2].ocr & 2) && (state && !ostate))
	529	single_transfer(2);
	530	}
	531
	532	WRITE_LINE_MEMBER(hd63450_device::drq3_w)
	533	{
	534	bool ostate = m_drq_state[3];
	535	m_drq_state[3] = state;
	536
	537	if((m_reg[3].ocr & 2) && (state && !ostate))
	538	single_transfer(3);
	539	}
	540
494	541	int hd63450_device::get_vector(int channel)
495	542	{
496	543	return m_reg[channel].niv;

branches/new_menus/src/emu/digfx.h

r29505	r29506
105	105	#define GFXDECODE_START( name ) const gfx_decode_entry GFXDECODE_NAME(name)[] = {
106	106	#define GFXDECODE_END { 0 } };
107	107
	108	// use these to declare a gfx_decode_entry array as a member of a device class
	109	#define DECLARE_GFXDECODE_MEMBER( name ) static const gfx_decode_entry name[]
	110	#define GFXDECODE_MEMBER( name ) const gfx_decode_entry name[] = {
	111
	112
108	113	// common gfx_decode_entry macros
109	114	#define GFXDECODE_ENTRYX(region,offset,layout,start,colors,flags) { region, offset, &layout, start, colors, flags },
110	115	#define GFXDECODE_ENTRY(region,offset,layout,start,colors) { region, offset, &layout, start, colors, 0 },

branches/new_menus/src/mess/drivers/sms.c

r29505	r29506
11	11
12	12	- SIO interface for Game Gear (needs netplay, I guess)
13	13	- Gear to Gear Port SMS Controller Adaptor
14		- SMS Store Display Unit (kiosk console)
15	14	- Sega Demo Unit II (kiosk expansion device)
16	15	- SMS Disk System (floppy disk drive expansion device) - unreleased
17	16	- Sega Graphic Board (black version) - unreleased
r29505	r29506
203	202	8000      - System Control Register (R/W)
204	203	Reading:
205	204	bit7      - ready (0 = ready, 1 = not ready)
206		bit6-bit5 - unknown
207		bit4-bit3 - timer selection bit switches
208		bit2-bit0 - unknown
	205	bit6      - active timer bit switch (0 = selection 2, 1 = selection 1)
	206	bit5      - unknown
	207	bit4-bit3 - timer selection 2 bit switches (10s-25s)
	208	bit2-bit0 - timer selection 1 bit switches (30s-135s)
209	209	Writing:
210		bit7-bit4 - unknown, maybe led of selected game to set?
	210	bit7-bit4 - led of selected game to set
211	211	bit3      - unknown, 1 seems to be written all the time
212	212	bit2      - unknown, 1 seems to be written all the time
213	213	bit1      - reset signal for sms cpu, 0 = reset low, 1 = reset high
r29505	r29506
259	259	AM_RANGE(0x0000, 0x3fff) AM_ROM                     /* BIOS */
260	260	AM_RANGE(0x4000, 0x47ff) AM_RAM                     /* RAM */
261	261	AM_RANGE(0x6000, 0x7fff) AM_READ(store_cart_peek)
262		AM_RANGE(0x8000, 0x8000) AM_READWRITE(sms_store_control_r, sms_store_control_w) /* Control */
	262	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("DSW") AM_WRITE(sms_store_control_w) /* Control */
263	263	AM_RANGE(0xc000, 0xc000) AM_READWRITE(sms_store_cart_select_r, sms_store_cart_select_w) /* cartridge/card slot selector */
264		AM_RANGE(0xd800, 0xd800) AM_READ(sms_store_select1)         /* Game selector port #1 */
265		AM_RANGE(0xdc00, 0xdc00) AM_READ(sms_store_select2)         /* Game selector port #2 */
	264	AM_RANGE(0xd800, 0xd800) AM_READ_PORT("GAMESEL1")         /* Game selector port #1 */
	265	AM_RANGE(0xdc00, 0xdc00) AM_READ_PORT("GAMESEL2")         /* Game selector port #2 */
266	266	ADDRESS_MAP_END
267	267
268	268	// I/O ports $3E and $3F do not exist on Mark III
r29505	r29506
381	381	//PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Rapid Button") /* Not implemented */
382	382	INPUT_PORTS_END
383	383
	384	static INPUT_PORTS_START( smssdisp )
	385	PORT_INCLUDE( sms )
	386
	387	PORT_START("DSW")
	388	PORT_DIPNAME( 0x07, 0x07, "Timer 1 length" )
	389	PORT_DIPSETTING( 0x00, "135s" )
	390	PORT_DIPSETTING( 0x01, "120s" )
	391	PORT_DIPSETTING( 0x02, "105s" )
	392	PORT_DIPSETTING( 0x03, "90s" )
	393	PORT_DIPSETTING( 0x04, "75s" )
	394	PORT_DIPSETTING( 0x05, "60s" )
	395	PORT_DIPSETTING( 0x06, "45s" )
	396	PORT_DIPSETTING( 0x07, "30s" )
	397	PORT_DIPNAME( 0x18, 0x18, "Timer 2 length" )
	398	PORT_DIPSETTING( 0x00, "25s" )
	399	PORT_DIPSETTING( 0x08, "20s" )
	400	PORT_DIPSETTING( 0x10, "15s" )
	401	PORT_DIPSETTING( 0x18, "10s" )
	402	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	403	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	404	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	405	PORT_DIPNAME( 0x40, 0x40, "Select Timer" )
	406	PORT_DIPSETTING( 0x00, "Timer 2" )
	407	PORT_DIPSETTING( 0x40, "Timer 1" )
	408	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )   // READY, must be high
	409
	410	PORT_START("GAMESEL1")
	411	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 03") PORT_CODE(KEYCODE_B)
	412	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 02") PORT_CODE(KEYCODE_G)
	413	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 01") PORT_CODE(KEYCODE_T)
	414	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 00") PORT_CODE(KEYCODE_5)
	415	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 07") PORT_CODE(KEYCODE_N)
	416	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 06") PORT_CODE(KEYCODE_H)
	417	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 05") PORT_CODE(KEYCODE_Y)
	418	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 04") PORT_CODE(KEYCODE_6)
	419
	420	PORT_START("GAMESEL2")
	421	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 11") PORT_CODE(KEYCODE_M)
	422	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 10") PORT_CODE(KEYCODE_J)
	423	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 09") PORT_CODE(KEYCODE_U)
	424	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 08") PORT_CODE(KEYCODE_7)
	425	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 15") PORT_CODE(KEYCODE_COMMA)
	426	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 14") PORT_CODE(KEYCODE_K)
	427	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 13") PORT_CODE(KEYCODE_I)
	428	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Game 12") PORT_CODE(KEYCODE_8)
	429	INPUT_PORTS_END
	430
384	431	static INPUT_PORTS_START( gg )
385	432	PORT_START("GG_PORT_DC")
386	433	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1) PORT_8WAY
r29505	r29506
988	1035	CONS( 1985, sg1000m3,   sms,        0,      sg1000m3,    sg1000m3, sms_state,      sg1000m3, "Sega",     "SG-1000 Mark III",                 GAME_SUPPORTS_SAVE )
989	1036	CONS( 1986, sms1,       sms,        0,      sms1_ntsc,   sms1,     sms_state,      sms1,     "Sega",     "Master System I",                  GAME_SUPPORTS_SAVE )
990	1037	CONS( 1986, sms1pal,    sms,        0,      sms1_pal,    sms1,     sms_state,      sms1,     "Sega",     "Master System I (PAL)" ,           GAME_SUPPORTS_SAVE )
991		CONS( 1986, smssdisp,   sms,        0,      sms_sdisp,   sms,      smssdisp_state, smssdisp, "Sega",     "Master System Store Display Unit", GAME_NOT_WORKING | GAME_SUPPORTS_SAVE )
	1038	CONS( 1986, smssdisp,   sms,        0,      sms_sdisp,   smssdisp, smssdisp_state, smssdisp, "Sega",     "Master System Store Display Unit", GAME_SUPPORTS_SAVE )
992	1039	CONS( 1987, smsj,       sms,        0,      smsj,        smsj,     sms_state,      smsj,     "Sega",     "Master System (Japan)",            GAME_SUPPORTS_SAVE )
993	1040	CONS( 1990, sms,        0,          0,      sms2_ntsc,   sms,      sms_state,      sms1,     "Sega",     "Master System II",                 GAME_SUPPORTS_SAVE )
994	1041	CONS( 1990, smspal,     sms,        0,      sms2_pal,    sms,      sms_state,      sms1,     "Sega",     "Master System II (PAL)",           GAME_SUPPORTS_SAVE )

branches/new_menus/src/mess/drivers/vt100.c

r29505	r29506
374	374	m_vertical_int = 0;
375	375	}
376	376
377		static const vt_video_interface vt100_video_interface =
378		{
379		"chargen",
380		};
381
382	377	INTERRUPT_GEN_MEMBER(vt100_state::vt100_vertical_interrupt)
383	378	{
384	379	m_vertical_int = 1;
r29505	r29506
425	420
426	421	MCFG_DEFAULT_LAYOUT( layout_vt100 )
427	422
428		MCFG_VT100_VIDEO_ADD("vt100_video", "screen", vt100_video_interface)
	423	MCFG_DEVICE_ADD("vt100_video", VT100_VIDEO, 0)
	424	MCFG_VT_SET_SCREEN("screen")
	425	MCFG_VT_CHARGEN("chargen")
429	426	MCFG_VT_VIDEO_RAM_CALLBACK(READ8(vt100_state, vt100_read_video_ram_r))
430	427	MCFG_VT_VIDEO_CLEAR_VIDEO_INTERRUPT_CALLBACK(WRITELINE(vt100_state, vt100_clear_video_interrupt))
431	428

branches/new_menus/src/mess/drivers/mac.c

r29505	r29506
841	841	sony_read_status
842	842	};
843	843
844		static const struct NCR539Xinterface mac_539x_intf =
845		{
846		DEVCB_DRIVER_LINE_MEMBER(mac_state, irq_539x_1_w),
847		DEVCB_DRIVER_LINE_MEMBER(mac_state, drq_539x_1_w)
848		};
849
850	844	static const struct nbbus_interface nubus_intf =
851	845	{
852	846	// interrupt lines
r29505	r29506
1868	1862	MCFG_SCSIBUS_ADD("scsi")
1869	1863	MCFG_SCSIDEV_ADD("scsi:harddisk1", SCSIHD, SCSI_ID_6)
1870	1864	MCFG_SCSIDEV_ADD("scsi:harddisk2", SCSIHD, SCSI_ID_5)
1871		MCFG_NCR539X_ADD(MAC_539X_1_TAG, C7M, mac_539x_intf)
1872
	1865	MCFG_DEVICE_ADD(MAC_539X_1_TAG, NCR539X, C7M)
	1866	MCFG_NCR539X_OUT_IRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, mac_state, irq_539x_1_w))
	1867	MCFG_NCR539X_OUT_DRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, mac_state, drq_539x_1_w))
	1868
1873	1869	/* internal ram */
1874	1870	MCFG_RAM_ADD(RAM_TAG)
1875	1871	MCFG_RAM_DEFAULT_SIZE("4M")

branches/new_menus/src/mess/drivers/z88.c

r29505	r29506
56	56	WRITE8_MEMBER(z88_state::bank3_cart_w) { m_carts[m_bank[3].slot]->write(space, (m_bank[3].page<<14) + offset, data); }
57	57
58	58
59		void z88_state::bankswitch_update(int bank, UINT16 page, int rams)
	59	UPD65031_MEMORY_UPDATE(z88_state::bankswitch_update)
60	60	{
61	61	char bank_tag[6];
62	62	sprintf(bank_tag, "bank%d", bank + 2);
r29505	r29506
605	605	return data;
606	606	}
607	607
608		static UPD65031_MEMORY_UPDATE(z88_bankswitch_update)
609		{
610		z88_state *state = device.machine().driver_data<z88_state>();
611		state->bankswitch_update(bank, page, rams);
612		}
613
614		static UPD65031_SCREEN_UPDATE(z88_screen_update)
615		{
616		z88_state *state = device.machine().driver_data<z88_state>();
617		state->lcd_update(bitmap, sbf, hires0, hires1, lores0, lores1, flash);
618		}
619
620		static UPD65031_INTERFACE( z88_blink_intf )
621		{
622		z88_screen_update,                                      // callback for update the LCD
623		z88_bankswitch_update,                                  // callback for update the bankswitch
624		};
625
626	608	static const z88cart_interface z88_cart_interface =
627	609	{
628	610	DEVCB_DEVICE_LINE_MEMBER("blink", upd65031_device, flp_w)
r29505	r29506
659	641
660	642	MCFG_DEFAULT_LAYOUT(layout_lcd)
661	643
662		MCFG_UPD65031_ADD("blink", XTAL_9_8304MHz, z88_blink_intf)
	644	MCFG_DEVICE_ADD("blink", UPD65031, XTAL_9_8304MHz)
663	645	MCFG_UPD65031_KB_CALLBACK(READ8(z88_state, kb_r))
664	646	MCFG_UPD65031_INT_CALLBACK(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
665	647	MCFG_UPD65031_NMI_CALLBACK(INPUTLINE("maincpu", INPUT_LINE_NMI))
666	648	MCFG_UPD65031_SPKR_CALLBACK(DEVWRITELINE("speaker", speaker_sound_device, level_w))
	649	MCFG_UPD65031_SCR_UPDATE_CB(z88_state, lcd_update)
	650	MCFG_UPD65031_MEM_UPDATE_CB(z88_state, bankswitch_update)
667	651
668	652	/* sound hardware */
669	653	MCFG_SPEAKER_STANDARD_MONO("mono")

branches/new_menus/src/mess/drivers/rainbow.c

r29505	r29506
1143	1143	m_irq_high = (state == ASSERT_LINE) ? 0x80 : 0;
1144	1144	}
1145	1145
1146		static const vt_video_interface video_interface =
1147		{
1148		"chargen",
1149		};
1150
1151	1146	/* F4 Character Displayer */
1152	1147	static const gfx_layout rainbow_charlayout =
1153	1148	{
r29505	r29506
1211	1206	MCFG_SCREEN_PALETTE("vt100_video:palette")
1212	1207	MCFG_GFXDECODE_ADD("gfxdecode", "vt100_video:palette", rainbow)
1213	1208
1214		MCFG_RAINBOW_VIDEO_ADD("vt100_video", "screen", video_interface)
	1209	MCFG_DEVICE_ADD("vt100_video", RAINBOW_VIDEO, 0)
	1210	MCFG_VT_SET_SCREEN("screen")
	1211	MCFG_VT_CHARGEN("chargen")
1215	1212	MCFG_VT_VIDEO_RAM_CALLBACK(READ8(rainbow_state, read_video_ram_r))
1216	1213	MCFG_VT_VIDEO_CLEAR_VIDEO_INTERRUPT_CALLBACK(WRITELINE(rainbow_state, clear_video_interrupt))
1217	1214

branches/new_menus/src/mess/drivers/a310.c

r29505	r29506
86	86	DECLARE_DRIVER_INIT(a310);
87	87	virtual void machine_start();
88	88	virtual void machine_reset();
	89	DECLARE_INPUT_CHANGED_MEMBER(key_stroke);
89	90
	91
90	92	protected:
91	93	required_device<ram_device> m_ram;
92	94	};
r29505	r29506
151	153	ADDRESS_MAP_END
152	154
153	155
	156	INPUT_CHANGED_MEMBER(a310_state::key_stroke)
	157	{
	158	UINT8 row_val = (UINT8)(FPTR)(param) >> 4;
	159	UINT8 col_val = (UINT8)(FPTR)(param) & 0xf;
	160
	161	if(newval && !oldval)
	162	m_kart->send_keycode_down(row_val,col_val);
	163
	164	if(oldval && !newval)
	165	m_kart->send_keycode_up(row_val,col_val);
	166	}
	167
	168	// TODO:
	169	// PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x0c) PORT_IMPULSE(1) <- led enabled & 4
	170	// PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x1d) PORT_IMPULSE(1) <- English Pound symbol
	171	// PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x21) PORT_IMPULSE(1) <- unknown but used (changes cursor to full)
	172	// PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x22) PORT_IMPULSE(1) <- led enabled & 1
	173	// 0x37 - 0x39 another 7 - 9 (keypad?)
	174	// PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x3a) PORT_IMPULSE(1) <- another minus (keypad?)
	175	// 0x48 - 0x4a another 4 - 6 (keypad?)
	176	// PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x4b) PORT_IMPULSE(1) <- +
	177	// PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x4c) PORT_IMPULSE(1) <- another English Pound
	178	// PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x57) PORT_IMPULSE(1) <- another /
	179	// PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x5d) PORT_IMPULSE(1) <- led enabled & 2
	180
154	181	static INPUT_PORTS_START( a310 )
155	182	PORT_START("dip") /* DIP switches */
156	183	PORT_BIT(0xfd, 0xfd, IPT_UNUSED)
157	184
158	185	PORT_START("key0") /* KEY ROW 0 */
159		PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC)
160		PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("1  !") PORT_CODE(KEYCODE_1)
161		PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("2  \"") PORT_CODE(KEYCODE_2)
162		PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("3  #") PORT_CODE(KEYCODE_3)
163		PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("4  $") PORT_CODE(KEYCODE_4)
164		PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("5  %") PORT_CODE(KEYCODE_5)
165		PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("6  &") PORT_CODE(KEYCODE_6)
166		PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("7  '") PORT_CODE(KEYCODE_7)
	186	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x00) PORT_IMPULSE(1)
	187	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("1  !") PORT_CODE(KEYCODE_1) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x11) PORT_IMPULSE(1)
	188	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("2  \"") PORT_CODE(KEYCODE_2) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x12) PORT_IMPULSE(1)
	189	PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("3  #") PORT_CODE(KEYCODE_3) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x13) PORT_IMPULSE(1)
	190	PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("4  $") PORT_CODE(KEYCODE_4) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x14) PORT_IMPULSE(1)
	191	PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("5  %") PORT_CODE(KEYCODE_5) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x15) PORT_IMPULSE(1)
	192	PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("6  &") PORT_CODE(KEYCODE_6) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x16) PORT_IMPULSE(1)
	193	PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("7  '") PORT_CODE(KEYCODE_7) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x17) PORT_IMPULSE(1)
167	194
168	195	PORT_START("key1") /* KEY ROW 1 */
169		PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("8  *") PORT_CODE(KEYCODE_8)
170		PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("9  (") PORT_CODE(KEYCODE_9)
171		PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("0  )") PORT_CODE(KEYCODE_0)
172		PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("-  _") PORT_CODE(KEYCODE_MINUS)
173		PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("=  +") PORT_CODE(KEYCODE_EQUALS)
174		PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("`  ~") PORT_CODE(KEYCODE_TILDE)
175		PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("BACK SPACE") PORT_CODE(KEYCODE_BACKSPACE)
	196	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("8  *") PORT_CODE(KEYCODE_8) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x18) PORT_IMPULSE(1)
	197	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("9  (") PORT_CODE(KEYCODE_9) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x19) PORT_IMPULSE(1)
	198	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("0  )") PORT_CODE(KEYCODE_0) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x1a) PORT_IMPULSE(1)
	199	PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("-  _") PORT_CODE(KEYCODE_MINUS) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x1b) PORT_IMPULSE(1)
	200	PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("=  +") PORT_CODE(KEYCODE_EQUALS) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x1c) PORT_IMPULSE(1)
	201	PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("`  ~") PORT_CODE(KEYCODE_TILDE) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x10) PORT_IMPULSE(1)
	202	PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("BACK SPACE") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x1e) PORT_IMPULSE(1)
176	203	PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB)
177	204
178	205	PORT_START("key2") /* KEY ROW 2 */
179		PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("q  Q") PORT_CODE(KEYCODE_Q)
180		PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("w  W") PORT_CODE(KEYCODE_W)
181		PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("e  E") PORT_CODE(KEYCODE_E)
182		PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("r  R") PORT_CODE(KEYCODE_R)
183		PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("t  T") PORT_CODE(KEYCODE_T)
184		PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("y  Y") PORT_CODE(KEYCODE_Y)
185		PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("u  U") PORT_CODE(KEYCODE_U)
186		PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("i  I") PORT_CODE(KEYCODE_I)
	206	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("q  Q") PORT_CODE(KEYCODE_Q) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x27) PORT_IMPULSE(1)
	207	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("w  W") PORT_CODE(KEYCODE_W) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x28) PORT_IMPULSE(1)
	208	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("e  E") PORT_CODE(KEYCODE_E) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x29) PORT_IMPULSE(1)
	209	PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("r  R") PORT_CODE(KEYCODE_R) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x2a) PORT_IMPULSE(1)
	210	PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("t  T") PORT_CODE(KEYCODE_T) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x2b) PORT_IMPULSE(1)
	211	PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("y  Y") PORT_CODE(KEYCODE_Y) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x2c) PORT_IMPULSE(1)
	212	PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("u  U") PORT_CODE(KEYCODE_U) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x2d) PORT_IMPULSE(1)
	213	PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("i  I") PORT_CODE(KEYCODE_I) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x2e) PORT_IMPULSE(1)
187	214
188	215	PORT_START("key3") /* KEY ROW 3 */
189		PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("o  O") PORT_CODE(KEYCODE_O)
190		PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("p  P") PORT_CODE(KEYCODE_P)
191		PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("[  {") PORT_CODE(KEYCODE_OPENBRACE)
192		PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("]  }") PORT_CODE(KEYCODE_CLOSEBRACE)
193		PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("RETURN") PORT_CODE(KEYCODE_ENTER)
	216	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("o  O") PORT_CODE(KEYCODE_O) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x2f) PORT_IMPULSE(1)
	217	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("p  P") PORT_CODE(KEYCODE_P) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x30) PORT_IMPULSE(1)
	218	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("[  {") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x31) PORT_IMPULSE(1)
	219	PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("]  }") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x32) PORT_IMPULSE(1)
	220	PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("RETURN") PORT_CODE(KEYCODE_ENTER) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x47) PORT_IMPULSE(1)
194	221	PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("DEL") PORT_CODE(KEYCODE_DEL)
195	222	PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL)
196	223	PORT_BIT(0x80, 0x80, IPT_KEYBOARD) PORT_NAME("CAPS LOCK") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE
197	224
198	225	PORT_START("key4") /* KEY ROW 4 */
199		PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("a  A") PORT_CODE(KEYCODE_A)
200		PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("s  S") PORT_CODE(KEYCODE_S)
201		PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("d  D") PORT_CODE(KEYCODE_D)
202		PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("f  F") PORT_CODE(KEYCODE_F)
203		PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("g  G") PORT_CODE(KEYCODE_G)
204		PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("h  H") PORT_CODE(KEYCODE_H)
205		PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("j  J") PORT_CODE(KEYCODE_J)
206		PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("k  K") PORT_CODE(KEYCODE_K)
	226	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("a  A") PORT_CODE(KEYCODE_A) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x3c) PORT_IMPULSE(1)
	227	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("s  S") PORT_CODE(KEYCODE_S) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x3d) PORT_IMPULSE(1)
	228	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("d  D") PORT_CODE(KEYCODE_D) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x3e) PORT_IMPULSE(1)
	229	PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("f  F") PORT_CODE(KEYCODE_F) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x3f) PORT_IMPULSE(1)
	230	PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("g  G") PORT_CODE(KEYCODE_G) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x40) PORT_IMPULSE(1)
	231	PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("h  H") PORT_CODE(KEYCODE_H) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x41) PORT_IMPULSE(1)
	232	PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("j  J") PORT_CODE(KEYCODE_J) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x42) PORT_IMPULSE(1)
	233	PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("k  K") PORT_CODE(KEYCODE_K) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x43) PORT_IMPULSE(1)
207	234
208	235	PORT_START("key5") /* KEY ROW 5 */
209		PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("l  L") PORT_CODE(KEYCODE_L)
210		PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME(";  :") PORT_CODE(KEYCODE_COLON)
211		PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("'  \"") PORT_CODE(KEYCODE_QUOTE)
212		PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("\\  |") PORT_CODE(KEYCODE_ASTERISK)
	236	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("l  L") PORT_CODE(KEYCODE_L) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x44) PORT_IMPULSE(1)
	237	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME(";  :") PORT_CODE(KEYCODE_COLON) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x45) PORT_IMPULSE(1)
	238	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("'  \"") PORT_CODE(KEYCODE_QUOTE) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x46) PORT_IMPULSE(1)
	239	PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("\\  |") PORT_CODE(KEYCODE_ASTERISK) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x33) PORT_IMPULSE(1)
213	240	PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("SHIFT (L)") PORT_CODE(KEYCODE_LSHIFT)
214		PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("z  Z") PORT_CODE(KEYCODE_Z)
215		PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("x  X") PORT_CODE(KEYCODE_X)
216		PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("c  C") PORT_CODE(KEYCODE_C)
	241	PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("z  Z") PORT_CODE(KEYCODE_Z) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x4e) PORT_IMPULSE(1)
	242	PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("x  X") PORT_CODE(KEYCODE_X) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x4f) PORT_IMPULSE(1)
	243	PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("c  C") PORT_CODE(KEYCODE_C) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x50) PORT_IMPULSE(1)
217	244
218	245	PORT_START("key6") /* KEY ROW 6 */
219		PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("v  V") PORT_CODE(KEYCODE_V)
220		PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("b  B") PORT_CODE(KEYCODE_B)
221		PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("n  N") PORT_CODE(KEYCODE_N)
222		PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("m  M") PORT_CODE(KEYCODE_M)
223		PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME(",  <") PORT_CODE(KEYCODE_COMMA)
224		PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME(".  >") PORT_CODE(KEYCODE_STOP)
225		PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("/  ?") PORT_CODE(KEYCODE_SLASH)
	246	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("v  V") PORT_CODE(KEYCODE_V) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x51) PORT_IMPULSE(1)
	247	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("b  B") PORT_CODE(KEYCODE_B) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x52) PORT_IMPULSE(1)
	248	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("n  N") PORT_CODE(KEYCODE_N) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x53) PORT_IMPULSE(1)
	249	PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("m  M") PORT_CODE(KEYCODE_M) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x54) PORT_IMPULSE(1)
	250	PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME(",  <") PORT_CODE(KEYCODE_COMMA) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x55) PORT_IMPULSE(1)
	251	PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME(".  >") PORT_CODE(KEYCODE_STOP) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x56) PORT_IMPULSE(1)
	252	PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("/  ?") PORT_CODE(KEYCODE_SLASH) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x23) PORT_IMPULSE(1)
226	253	PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("SHIFT (R)") PORT_CODE(KEYCODE_RSHIFT)
227	254
228	255	PORT_START("key7") /* KEY ROW 7 */
229	256	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("LINE FEED")
230		PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("SPACE") PORT_CODE(KEYCODE_SPACE)
231		PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("- (KP)") PORT_CODE(KEYCODE_MINUS_PAD)
232		PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME(", (KP)") PORT_CODE(KEYCODE_PLUS_PAD)
	257	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("SPACE") PORT_CODE(KEYCODE_SPACE) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x26) PORT_IMPULSE(1)
	258	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("- (KP)") PORT_CODE(KEYCODE_MINUS_PAD)
	259	PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME(", (KP)") PORT_CODE(KEYCODE_PLUS_PAD)
233	260	PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("ENTER (KP)") PORT_CODE(KEYCODE_ENTER_PAD)
234	261	PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME(". (KP)") PORT_CODE(KEYCODE_DEL_PAD)
235	262	PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("0 (KP)") PORT_CODE(KEYCODE_0_PAD)
236	263	PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("1 (KP)") PORT_CODE(KEYCODE_1_PAD)
237	264
238	265	PORT_START("key8") /* KEY ROW 8 */
239		PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("2 (KP)") PORT_CODE(KEYCODE_2_PAD)
240		PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("3 (KP)") PORT_CODE(KEYCODE_3_PAD)
241		PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("4 (KP)") PORT_CODE(KEYCODE_4_PAD)
242		PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("5 (KP)") PORT_CODE(KEYCODE_5_PAD)
243		PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("6 (KP)") PORT_CODE(KEYCODE_6_PAD)
244		PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("7 (KP)") PORT_CODE(KEYCODE_7_PAD)
245		PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("8 (KP)") PORT_CODE(KEYCODE_8_PAD)
246		PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("9 (KP)") PORT_CODE(KEYCODE_9_PAD)
	266	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("2 (KP)") PORT_CODE(KEYCODE_2_PAD)
	267	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("3 (KP)") PORT_CODE(KEYCODE_3_PAD)
	268	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("4 (KP)") PORT_CODE(KEYCODE_4_PAD)
	269	PORT_BIT(0x08, 0x00, IPT_KEYBOARD) PORT_NAME("5 (KP)") PORT_CODE(KEYCODE_5_PAD)
	270	PORT_BIT(0x10, 0x00, IPT_KEYBOARD) PORT_NAME("6 (KP)") PORT_CODE(KEYCODE_6_PAD)
	271	PORT_BIT(0x20, 0x00, IPT_KEYBOARD) PORT_NAME("7 (KP)") PORT_CODE(KEYCODE_7_PAD)
	272	PORT_BIT(0x40, 0x00, IPT_KEYBOARD) PORT_NAME("8 (KP)") PORT_CODE(KEYCODE_8_PAD)
	273	PORT_BIT(0x80, 0x00, IPT_KEYBOARD) PORT_NAME("9 (KP)") PORT_CODE(KEYCODE_9_PAD)
247	274
	275	PORT_START("key9")
	276	PORT_BIT(0x01, 0x00, IPT_KEYBOARD) PORT_NAME("HOME") PORT_CODE(KEYCODE_HOME) PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x20) PORT_IMPULSE(1)
	277	PORT_BIT(0x02, 0x00, IPT_KEYBOARD) PORT_NAME("*") PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x24) PORT_IMPULSE(1) // (KP?)
	278	PORT_BIT(0x04, 0x00, IPT_KEYBOARD) PORT_NAME("#") PORT_CHANGED_MEMBER(DEVICE_SELF, a310_state, key_stroke, 0x25) PORT_IMPULSE(1) // (KP?)
	279
	280
248	281	PORT_START("via1a") /* VIA #1 PORT A */
249	282	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START) PORT_PLAYER(1)
250	283	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START) PORT_PLAYER(2)
251		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1                   )
252		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON2                   )
	284	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1)
	285	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON2)
253	286	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT) PORT_4WAY
254	287	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP) PORT_4WAY
255	288	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_4WAY
r29505	r29506
297	330	MCFG_CPU_ADD("maincpu", ARM, 8000000)        /* 8 MHz */
298	331	MCFG_CPU_PROGRAM_MAP(a310_mem)
299	332
300		MCFG_AAKART_ADD("kart", 8000000/128, kart_interface) // TODO: frequency
	333	MCFG_AAKART_ADD("kart", 8000000/256, kart_interface) // TODO: frequency
	334
301	335	MCFG_I2CMEM_ADD("i2cmem")
302	336	MCFG_I2CMEM_DATA_SIZE(0x100)
303	337

branches/new_menus/src/mess/drivers/megadriv.c

r29505	r29506
696	696	MCFG_SCREEN_VBLANK_DRIVER(md_cons_state, screen_eof_console)
697	697
698	698	MCFG_DEVICE_ADD("segacd", SEGA_SEGACD_US, 0)
	699	MCFG_GFX_PALETTE("gen_vdp:palette")
699	700
700	701	MCFG_CDROM_ADD( "cdrom",scd_cdrom )
701	702
r29505	r29506
712	713	MCFG_SCREEN_VBLANK_DRIVER(md_cons_state, screen_eof_console)
713	714
714	715	MCFG_DEVICE_ADD("segacd", SEGA_SEGACD_EUROPE, 0)
	716	MCFG_GFX_PALETTE("gen_vdp:palette")
715	717
716	718	MCFG_CDROM_ADD( "cdrom",scd_cdrom )
717	719
r29505	r29506
728	730	MCFG_SCREEN_VBLANK_DRIVER(md_cons_state, screen_eof_console)
729	731
730	732	MCFG_DEVICE_ADD("segacd", SEGA_SEGACD_JAPAN, 0)
	733	MCFG_GFX_PALETTE("gen_vdp:palette")
731	734
732	735	MCFG_CDROM_ADD( "cdrom",scd_cdrom )
733	736
r29505	r29506
738	741	static MACHINE_CONFIG_DERIVED( genesis_32x_scd, genesis_32x )
739	742
740	743	MCFG_DEVICE_ADD("segacd", SEGA_SEGACD_US, 0)
	744	MCFG_GFX_PALETTE("gen_vdp:palette")
	745
741	746	MCFG_CDROM_ADD( "cdrom",scd_cdrom )
742	747
743	748	MCFG_MACHINE_START_OVERRIDE(md_cons_state, ms_megacd)

branches/new_menus/src/mess/drivers/mmd1.c

r29505	r29506
410	410	return data;
411	411	}
412	412
413
414		static I8279_INTERFACE( mmd2_intf )
415		{
416		DEVCB_NULL,                     // irq
417		DEVCB_DRIVER_MEMBER(mmd1_state, mmd2_scanlines_w),  // scan SL lines
418		DEVCB_DRIVER_MEMBER(mmd1_state, mmd2_digit_w),      // display A&B
419		DEVCB_NULL,                     // BD
420		DEVCB_DRIVER_MEMBER(mmd1_state, mmd2_kbd_r),        // kbd RL lines
421		DEVCB_LINE_VCC,                     // Shift key
422		DEVCB_LINE_VCC
423		};
424
425	413	WRITE8_MEMBER( mmd1_state::mmd2_status_callback )
426	414	{
427	415	// operate the HALT LED
r29505	r29506
513	501	MCFG_DEFAULT_LAYOUT(layout_mmd2)
514	502
515	503	/* Devices */
516		MCFG_I8279_ADD("i8279", 400000, mmd2_intf) // based on divider
	504	MCFG_DEVICE_ADD("i8279", I8279, 400000) // based on divider
	505	MCFG_I8279_OUT_SL_CB(WRITE8(mmd1_state, mmd2_scanlines_w))         // scan SL lines
	506	MCFG_I8279_OUT_DISP_CB(WRITE8(mmd1_state, mmd2_digit_w))         // display A&B
	507	MCFG_I8279_IN_RL_CB(READ8(mmd1_state, mmd2_kbd_r))               // kbd RL lines
	508	MCFG_I8279_IN_SHIFT_CB(VCC)                              // Shift key
	509	MCFG_I8279_IN_CTRL_CB(VCC)
	510
517	511	MACHINE_CONFIG_END
518	512
519	513	/* ROM definition */

branches/new_menus/src/mess/drivers/sdk85.c

r29505	r29506
114	114	return data;
115	115	}
116	116
117		static I8279_INTERFACE( sdk85_intf )
118		{
119		DEVCB_CPU_INPUT_LINE("maincpu", I8085_RST55_LINE),  // irq
120		DEVCB_DRIVER_MEMBER(sdk85_state, scanlines_w),  // scan SL lines
121		DEVCB_DRIVER_MEMBER(sdk85_state, digit_w),      // display A&B
122		DEVCB_NULL,                     // BD
123		DEVCB_DRIVER_MEMBER(sdk85_state, kbd_r),        // kbd RL lines
124		DEVCB_LINE_VCC,                     // Shift key
125		DEVCB_LINE_VCC
126		};
127
128	117	static MACHINE_CONFIG_START( sdk85, sdk85_state )
129	118	/* basic machine hardware */
130	119	MCFG_CPU_ADD("maincpu", I8085A, XTAL_2MHz)
r29505	r29506
135	124	MCFG_DEFAULT_LAYOUT(layout_sdk85)
136	125
137	126	/* Devices */
138		MCFG_I8279_ADD("i8279", 3100000, sdk85_intf) // based on divider
	127	MCFG_DEVICE_ADD("i8279", I8279, 3100000) // based on divider
	128	MCFG_I8279_OUT_IRQ_CB(INPUTLINE("maincpu", I8085_RST55_LINE))   // irq
	129	MCFG_I8279_OUT_SL_CB(WRITE8(sdk85_state, scanlines_w))         // scan SL lines
	130	MCFG_I8279_OUT_DISP_CB(WRITE8(sdk85_state, digit_w))         // display A&B
	131	MCFG_I8279_IN_RL_CB(READ8(sdk85_state, kbd_r))               // kbd RL lines
	132	MCFG_I8279_IN_SHIFT_CB(VCC)                              // Shift key
	133	MCFG_I8279_IN_CTRL_CB(VCC)
139	134	MACHINE_CONFIG_END
140	135
141	136	/* ROM definition */

branches/new_menus/src/mess/drivers/tandy2k.c

r29505	r29506
13	13	- floppy
14	14	- HDL is also connected to WP/TS input where TS is used to detect motor status
15	15	- 3 second motor off delay timer
16		- DMA
17	16	- video (video RAM is at memory top - 0x1400, i.e. 0x1ec00)
18	17	- keyboard ROM
19	18	- hires graphics board
r29505	r29506
25	24
26	25	#include "includes/tandy2k.h"
27	26
	27	#define LOG 1
	28
28	29	// Read/Write Handlers
29	30
30	31	void tandy2k_state::update_drq()
r29505	r29506
50	51	void tandy2k_state::dma_request(int line, int state)
51	52	{
52	53	m_busdmarq[line] = state;
	54
53	55	update_drq();
54	56	}
55	57
r29505	r29506
119	121
120	122	0       KBEN        keyboard enable
121	123	1       EXTCLK      external baud rate clock
122		2       SPKRGATE    enable periodic m_speaker output
123		3       SPKRDATA    direct output to m_speaker
	124	2       SPKRGATE    enable periodic speaker output
	125	3       SPKRDATA    direct output to speaker
124	126	4       RFRQGATE    enable refresh and baud rate clocks
125	127	5       FDCRESET*   reset 8272
126	128	6       TMRIN0      enable 80186 timer 0
r29505	r29506
128	130
129	131	*/
130	132
	133	if (LOG) logerror("ENABLE %02x\n", data);
	134
131	135	// keyboard enable
132	136	m_kb->power_w(BIT(data, 0));
133	137
134	138	// external baud rate clock
135	139	m_extclk = BIT(data, 1);
136	140
137		// m_speaker gate
	141	// speaker gate
138	142	m_pit->write_gate0(BIT(data, 2));
139	143
140		// m_speaker data
	144	// speaker data
141	145	m_spkrdata = BIT(data, 3);
142	146	speaker_update();
143	147
r29505	r29506
146	150	m_pit->write_gate2(BIT(data, 4));
147	151
148	152	// FDC reset
149		if(!BIT(data, 5))
	153	if (!BIT(data, 5))
	154	{
150	155	m_fdc->reset();
	156	}
151	157
152	158	// timer 0 enable
153	159	m_maincpu->tmrin0_w(BIT(data, 6));
r29505	r29506
173	179
174	180	*/
175	181
	182	if (LOG) logerror("DMA MUX %02x\n", data);
	183
176	184	m_dma_mux = data;
177	185
178	186	// check for DMA error
r29505	r29506
228	236
229	237	READ8_MEMBER( tandy2k_state::fldtc_r )
230	238	{
	239	if (LOG) logerror("FLDTC\n");
	240
231	241	fldtc_w(space, 0, 0);
232	242
233	243	return 0;
r29505	r29506
256	266
257	267	*/
258	268
	269	if (LOG) logerror("Address Control %02x\n", data);
	270
259	271	// video access
260	272	m_vram_base = data & 0x1f;
261	273
r29505	r29506
281	293
282	294	// video source select
283	295	m_vidouts = BIT(data, 7);
284
285		logerror("Address Control %02x\n", data);
286	296	}
287	297
288	298	// Memory Maps
r29505	r29506
297	307
298	308	static ADDRESS_MAP_START( tandy2k_io, AS_IO, 16, tandy2k_state )
299	309	ADDRESS_MAP_UNMAP_HIGH
300		AM_RANGE(0x00000, 0x00001) AM_READWRITE8(enable_r, enable_w, 0x00ff)
301		AM_RANGE(0x00002, 0x00003) AM_WRITE8(dma_mux_w, 0x00ff)
302		AM_RANGE(0x00004, 0x00005) AM_READWRITE8(fldtc_r, fldtc_w, 0x00ff)
303		AM_RANGE(0x00010, 0x00013) AM_DEVREADWRITE8(I8251A_TAG, i8251_device, data_r, data_w, 0x00ff)
304		AM_RANGE(0x00030, 0x00033) AM_DEVICE8(I8272A_TAG, i8272a_device, map, 0x00ff)
305		AM_RANGE(0x00040, 0x00047) AM_DEVREADWRITE8(I8253_TAG, pit8253_device, read, write, 0x00ff)
306		AM_RANGE(0x00052, 0x00053) AM_READ8(kbint_clr_r, 0x00ff)
307		AM_RANGE(0x00050, 0x00057) AM_DEVREADWRITE8(I8255A_TAG, i8255_device, read, write, 0x00ff)
308		AM_RANGE(0x00060, 0x00063) AM_DEVREADWRITE8(I8259A_0_TAG, pic8259_device, read, write, 0x00ff)
309		AM_RANGE(0x00070, 0x00073) AM_DEVREADWRITE8(I8259A_1_TAG, pic8259_device, read, write, 0x00ff)
310		AM_RANGE(0x00080, 0x00081) AM_DEVREADWRITE8(I8272A_TAG, i8272a_device, mdma_r, mdma_w, 0x00ff)
	310	AM_RANGE(0x00000, 0x00001) AM_MIRROR(0x8) AM_READWRITE8(enable_r, enable_w, 0x00ff)
	311	AM_RANGE(0x00002, 0x00003) AM_MIRROR(0x8) AM_WRITE8(dma_mux_w, 0x00ff)
	312	AM_RANGE(0x00004, 0x00005) AM_MIRROR(0x8) AM_READWRITE8(fldtc_r, fldtc_w, 0x00ff)
	313	AM_RANGE(0x00010, 0x00013) AM_MIRROR(0xc) AM_DEVREADWRITE8(I8251A_TAG, i8251_device, data_r, data_w, 0x00ff)
	314	AM_RANGE(0x00030, 0x00033) AM_MIRROR(0xc) AM_DEVICE8(I8272A_TAG, i8272a_device, map, 0x00ff)
	315	AM_RANGE(0x00040, 0x00047) AM_MIRROR(0x8) AM_DEVREADWRITE8(I8253_TAG, pit8253_device, read, write, 0x00ff)
	316	AM_RANGE(0x00052, 0x00053) AM_MIRROR(0x8) AM_READ8(kbint_clr_r, 0x00ff)
	317	AM_RANGE(0x00050, 0x00057) AM_MIRROR(0x8) AM_DEVREADWRITE8(I8255A_TAG, i8255_device, read, write, 0x00ff)
	318	AM_RANGE(0x00060, 0x00063) AM_MIRROR(0xc) AM_DEVREADWRITE8(I8259A_0_TAG, pic8259_device, read, write, 0x00ff)
	319	AM_RANGE(0x00070, 0x00073) AM_MIRROR(0xc) AM_DEVREADWRITE8(I8259A_1_TAG, pic8259_device, read, write, 0x00ff)
	320	AM_RANGE(0x00080, 0x00081) AM_MIRROR(0xe) AM_DEVREADWRITE8(I8272A_TAG, i8272a_device, mdma_r, mdma_w, 0x00ff)
311	321	//  AM_RANGE(0x00100, 0x0017f) AM_DEVREADWRITE8(CRT9007_TAG, crt9007_t, read, write, 0x00ff) AM_WRITE8(addr_ctrl_w, 0xff00)
312	322	AM_RANGE(0x00100, 0x0017f) AM_READWRITE(vpac_r, vpac_w)
313	323	//  AM_RANGE(0x00180, 0x00180) AM_READ8(hires_status_r, 0x00ff)
r29505	r29506
516	526
517	527	WRITE_LINE_MEMBER( tandy2k_state::rfrqpulse_w )
518	528	{
	529	// memory refresh counter up
519	530	}
520	531
521	532	// Intel 8255A Interface
r29505	r29506
786	797	MCFG_DEVICE_ADD(CRT9021B_TAG, CRT9021, XTAL_16MHz*28/20)
787	798	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
788	799
789		MCFG_TIMER_DRIVER_ADD_PERIODIC("vidldsh", tandy2k_state, vidldsh_tick, attotime::from_hz(XTAL_16MHz*28/20/8))
	800	MCFG_TIMER_DRIVER_ADD("vidldsh", tandy2k_state, vidldsh_tick)
790	801
791	802	// sound hardware
792	803	MCFG_SPEAKER_STANDARD_MONO("mono")
r29505	r29506
806	817	MCFG_RS232_PORT_ADD(RS232_TAG, default_rs232_devices, NULL)
807	818	MCFG_RS232_RXD_HANDLER(DEVWRITELINE(I8251A_TAG, i8251_device, write_rxd))
808	819	MCFG_RS232_DSR_HANDLER(DEVWRITELINE(I8251A_TAG, i8251_device, write_dsr))
	820	// TODO pin 15 external transmit clock
	821	// TODO pin 17 external receiver clock
809	822
810	823	MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)
811	824	MCFG_PIT8253_CLK0(XTAL_16MHz/16)
812	825	MCFG_PIT8253_OUT0_HANDLER(WRITELINE(tandy2k_state, outspkr_w))
813	826	MCFG_PIT8253_CLK1(XTAL_16MHz/8)
814	827	MCFG_PIT8253_OUT1_HANDLER(WRITELINE(tandy2k_state, intbrclk_w))
815		MCFG_PIT8253_CLK2(XTAL_16MHz/8)
816		MCFG_PIT8253_OUT2_HANDLER(WRITELINE(tandy2k_state, rfrqpulse_w))
	828	//MCFG_PIT8253_CLK2(XTAL_16MHz/8)
	829	//MCFG_PIT8253_OUT2_HANDLER(WRITELINE(tandy2k_state, rfrqpulse_w))
817	830
818	831	MCFG_PIC8259_ADD(I8259A_0_TAG, DEVWRITELINE(I80186_TAG, i80186_cpu_device, int0_w), VCC, NULL)
819	832

branches/new_menus/src/mess/drivers/sdk86.c

r29505	r29506
137	137	m_usart->write_rxc(state);
138	138	}
139	139
140		static I8279_INTERFACE( sdk86_intf )
141		{
142		DEVCB_NULL, // irq
143		DEVCB_DRIVER_MEMBER(sdk86_state, scanlines_w),  // scan SL lines
144		DEVCB_DRIVER_MEMBER(sdk86_state, digit_w),      // display A&B
145		DEVCB_NULL,                     // BD
146		DEVCB_DRIVER_MEMBER(sdk86_state, kbd_r),        // kbd RL lines
147		DEVCB_LINE_GND,                     // Shift key
148		DEVCB_LINE_GND
149		};
150
151	140	static DEVICE_INPUT_DEFAULTS_START( terminal )
152	141	DEVICE_INPUT_DEFAULTS( "TERM_TXBAUD", 0xff, 0x05 ) // 4800
153	142	DEVICE_INPUT_DEFAULTS( "TERM_RXBAUD", 0xff, 0x05 ) // 4800
r29505	r29506
180	169	MCFG_DEVICE_ADD("usart_clock", CLOCK, 307200)
181	170	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(sdk86_state, write_usart_clock))
182	171
183		MCFG_I8279_ADD("i8279", 2500000, sdk86_intf) // based on divider
	172	MCFG_DEVICE_ADD("i8279", I8279, 2500000) // based on divider
	173	MCFG_I8279_OUT_SL_CB(WRITE8(sdk86_state, scanlines_w))         // scan SL lines
	174	MCFG_I8279_OUT_DISP_CB(WRITE8(sdk86_state, digit_w))         // display A&B
	175	MCFG_I8279_IN_RL_CB(READ8(sdk86_state, kbd_r))               // kbd RL lines
	176	MCFG_I8279_IN_SHIFT_CB(GND)                              // Shift key
	177	MCFG_I8279_IN_CTRL_CB(GND)
184	178
185	179	MACHINE_CONFIG_END
186	180

branches/new_menus/src/mess/drivers/nes.c

r29505	r29506
652	652	}
653	653
654	654
655		static const ppu2c0x_interface nes_ppu_interface =
656		{
657		"maincpu",
658		0,
659		0,
660		PPU_MIRROR_NONE
661		};
662
663	655	static const floppy_interface nes_floppy_interface =
664	656	{
665	657	DEVCB_NULL,
r29505	r29506
674	666	};
675	667
676	668
677		static const nes_cart_interface nes_crt_interface =
678		{
679		};
680
681
682	669	static const cassette_interface fc_cassette_interface =
683	670	{
684	671	cassette_default_formats,
r29505	r29506
710	697	MCFG_PALETTE_ADD("palette", 4*16*8)
711	698	MCFG_PALETTE_INIT_OWNER(nes_state, nes)
712	699
713		MCFG_PPU2C02_ADD("ppu", nes_ppu_interface)
	700	MCFG_PPU2C02_ADD("ppu")
	701	MCFG_PPU2C0X_CPU("maincpu")
714	702	MCFG_PPU2C0X_SET_NMI(nes_state, ppu_nmi)
715	703
716	704	/* sound hardware */
r29505	r29506
719	707	MCFG_SOUND_CONFIG(nes_apu_interface)
720	708	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
721	709
722		MCFG_NES_CARTRIDGE_ADD("nes_slot", nes_crt_interface, nes_cart, NULL)
	710	MCFG_NES_CARTRIDGE_ADD("nes_slot", nes_cart, NULL)
723	711	MCFG_SOFTWARE_LIST_ADD("cart_list", "nes")
724	712	MCFG_SOFTWARE_LIST_ADD("ade_list", "nes_ade")         // Camerica/Codemasters Aladdin Deck Enhancer mini-carts
725	713	MCFG_SOFTWARE_LIST_ADD("ntb_list", "nes_ntbrom")      // Sunsoft Nantettate! Baseball mini-carts
r29505	r29506
734	722	MCFG_CPU_CLOCK(PAL_CLOCK)
735	723
736	724	MCFG_DEVICE_REMOVE("ppu")
737		MCFG_PPU2C07_ADD("ppu", nes_ppu_interface)
	725	MCFG_PPU2C07_ADD("ppu")
	726	MCFG_PPU2C0X_CPU("maincpu")
738	727	MCFG_PPU2C0X_SET_NMI(nes_state, ppu_nmi)
739	728
740	729	/* video hardware */
r29505	r29506
757	746	MCFG_CPU_CLOCK( 26601712/15 ) /* 26.601712MHz / 15 == 1.77344746666... MHz */
758	747
759	748	MCFG_DEVICE_REMOVE("ppu")
760		MCFG_PPU2C07_ADD("ppu", nes_ppu_interface)
	749	MCFG_PPU2C07_ADD("ppu")
	750	MCFG_PPU2C0X_CPU("maincpu")
761	751	MCFG_PPU2C0X_SET_NMI(nes_state, ppu_nmi)
762	752
763	753	/* video hardware */
r29505	r29506
773	763
774	764	static MACHINE_CONFIG_DERIVED( famicom, nes )
775	765	MCFG_DEVICE_REMOVE("nes_slot")
776		MCFG_NES_CARTRIDGE_ADD("nes_slot", nes_crt_interface, nes_cart, NULL)
	766	MCFG_NES_CARTRIDGE_ADD("nes_slot", nes_cart, NULL)
777	767	MCFG_NES_CARTRIDGE_NOT_MANDATORY
778	768
779	769	MCFG_LEGACY_FLOPPY_DRIVE_ADD(FLOPPY_0, nes_floppy_interface)

branches/new_menus/src/mess/drivers/x68k.c

r29505	r29506
115	115	*/
116	116
117	117	#include "emu.h"
118		#include "cpu/m68000/m68000.h"
119		#include "machine/i8255.h"
120	118	#include "machine/mc68901.h"
121	119	#include "machine/upd765.h"
122		#include "sound/2151intf.h"
123	120	#include "sound/okim6258.h"
124		#include "machine/8530scc.h"
125	121	#include "machine/rp5c15.h"
126	122	#include "machine/mb89352.h"
127	123	#include "formats/xdf_dsk.h"
r29505	r29506
181	177	m_fdc.fdc->tc_w(ASSERT_LINE);
182	178	m_fdc.fdc->tc_w(CLEAR_LINE);
183	179	break;
	180	case TIMER_X68K_ADPCM:
	181	m_hd63450->drq3_w(1);
	182	m_hd63450->drq3_w(0);
	183	break;
184	184	default:
185	185	assert_always(FALSE, "Unknown id in x68k_state::device_timer");
186	186	}
r29505	r29506
213	213	// typically read from the SCC data port on receive buffer full interrupt per byte
214	214	int x68k_state::x68k_read_mouse()
215	215	{
216		scc8530_t *scc = machine().device<scc8530_t>("scc");
217	216	char val = 0;
218	217	char ipt = 0;
219	218
220		if(!(scc->get_reg_b(5) & 0x02))
	219	if(!(m_scc->get_reg_b(5) & 0x02))
221	220	return 0xff;
222	221
223	222	switch(m_mouse.inputtype)
224	223	{
225	224	case 0:
226		ipt = ioport("mouse1")->read();
	225	ipt = m_mouse1->read();
227	226	break;
228	227	case 1:
229		val = ioport("mouse2")->read();
	228	val = m_mouse2->read();
230	229	ipt = val - m_mouse.last_mouse_x;
231	230	m_mouse.last_mouse_x = val;
232	231	break;
233	232	case 2:
234		val = ioport("mouse3")->read();
	233	val = m_mouse3->read();
235	234	ipt = val - m_mouse.last_mouse_y;
236	235	m_mouse.last_mouse_y = val;
237	236	break;
r29505	r29506
239	238	m_mouse.inputtype++;
240	239	if(m_mouse.inputtype > 2)
241	240	{
242		int i_val = scc->get_reg_b(0);
	241	int i_val = m_scc->get_reg_b(0);
243	242	m_mouse.inputtype = 0;
244	243	m_mouse.bufferempty = 1;
245	244	i_val &= ~0x01;
246		scc->set_reg_b(0, i_val);
	245	m_scc->set_reg_b(0, i_val);
247	246	logerror("SCC: mouse buffer empty\n");
248	247	}
249	248
r29505	r29506
258	257	*/
259	258	READ16_MEMBER(x68k_state::x68k_scc_r )
260	259	{
261		scc8530_t *scc = machine().device<scc8530_t>("scc");
262	260	offset %= 4;
263	261	switch(offset)
264	262	{
265	263	case 0:
266		return scc->reg_r(space, 0);
	264	return m_scc->reg_r(space, 0);
267	265	case 1:
268	266	return x68k_read_mouse();
269	267	case 2:
270		return scc->reg_r(space, 1);
	268	return m_scc->reg_r(space, 1);
271	269	case 3:
272		return scc->reg_r(space, 3);
	270	return m_scc->reg_r(space, 3);
273	271	default:
274	272	return 0xff;
275	273	}
r29505	r29506
277	275
278	276	WRITE16_MEMBER(x68k_state::x68k_scc_w )
279	277	{
280		scc8530_t *scc = machine().device<scc8530_t>("scc");
281	278	offset %= 4;
282	279
283	280	switch(offset)
284	281	{
285	282	case 0:
286		scc->reg_w(space, 0,(UINT8)data);
287		if((scc->get_reg_b(5) & 0x02) != m_scc_prev)
	283	m_scc->reg_w(space, 0,(UINT8)data);
	284	if((m_scc->get_reg_b(5) & 0x02) != m_scc_prev)
288	285	{
289		if(scc->get_reg_b(5) & 0x02)  // Request to Send
	286	if(m_scc->get_reg_b(5) & 0x02)  // Request to Send
290	287	{
291		int val = scc->get_reg_b(0);
	288	int val = m_scc->get_reg_b(0);
292	289	m_mouse.bufferempty = 0;
293	290	val |= 0x01;
294		scc->set_reg_b(0,val);
	291	m_scc->set_reg_b(0,val);
295	292	}
296	293	}
297	294	break;
298	295	case 1:
299		scc->reg_w(space, 2,(UINT8)data);
	296	m_scc->reg_w(space, 2,(UINT8)data);
300	297	break;
301	298	case 2:
302		scc->reg_w(space, 1,(UINT8)data);
	299	m_scc->reg_w(space, 1,(UINT8)data);
303	300	break;
304	301	case 3:
305		scc->reg_w(space, 3,(UINT8)data);
	302	m_scc->reg_w(space, 3,(UINT8)data);
306	303	break;
307	304	}
308		m_scc_prev = scc->get_reg_b(5) & 0x02;
	305	m_scc_prev = m_scc->get_reg_b(5) & 0x02;
309	306	}
310	307
311	308	TIMER_CALLBACK_MEMBER(x68k_state::x68k_scc_ack)
312	309	{
313		scc8530_t *scc = machine().device<scc8530_t>("scc");
314	310	if(m_mouse.bufferempty != 0)  // nothing to do if the mouse data buffer is empty
315	311	return;
316	312
r29505	r29506
318	314	//      return;
319	315
320	316	// hard-code the IRQ vector for now, until the SCC code is more complete
321		if((scc->get_reg_a(9) & 0x08) || (scc->get_reg_b(9) & 0x08))  // SCC reg WR9 is the same for both channels
	317	if((m_scc->get_reg_a(9) & 0x08) || (m_scc->get_reg_b(9) & 0x08))  // SCC reg WR9 is the same for both channels
322	318	{
323		if((scc->get_reg_b(1) & 0x18) != 0)  // if bits 3 and 4 of WR1 are 0, then Rx IRQs are disabled on this channel
	319	if((m_scc->get_reg_b(1) & 0x18) != 0)  // if bits 3 and 4 of WR1 are 0, then Rx IRQs are disabled on this channel
324	320	{
325		if(scc->get_reg_b(5) & 0x02)  // RTS signal
	321	if(m_scc->get_reg_b(5) & 0x02)  // RTS signal
326	322	{
327	323	m_mouse.irqactive = 1;
328	324	m_current_vector[5] = 0x54;
r29505	r29506
354	350	}
355	351	if(m_adpcm.clock != 0)
356	352	rate = rate/2;
357		m_hd63450->set_timer(3,attotime::from_hz(rate));
	353	m_adpcm_timer->adjust(attotime::from_hz(rate), 0, attotime::from_hz(rate));
358	354	}
359	355
360	356	// Megadrive 3 button gamepad
r29505	r29506
367	363	{
368	364	if(port == 1)
369	365	{
370		UINT8 porta = ioport("md3b")->read() & 0xff;
371		UINT8 portb = (ioport("md3b")->read() >> 8) & 0xff;
	366	UINT8 porta = m_md3b->read() & 0xff;
	367	UINT8 portb = (m_md3b->read() >> 8) & 0xff;
372	368	if(m_mdctrl.mux1 & 0x10)
373	369	{
374	370	return porta | 0x90;
r29505	r29506
380	376	}
381	377	if(port == 2)
382	378	{
383		UINT8 porta = (ioport("md3b")->read() >> 16) & 0xff;
384		UINT8 portb = (ioport("md3b")->read() >> 24) & 0xff;
	379	UINT8 porta = (m_md3b->read() >> 16) & 0xff;
	380	UINT8 portb = (m_md3b->read() >> 24) & 0xff;
385	381	if(m_mdctrl.mux2 & 0x20)
386	382	{
387	383	return porta | 0x90;
r29505	r29506
415	411	{
416	412	if(port == 1)
417	413	{
418		UINT8 porta = ioport("md6b")->read() & 0xff;
419		UINT8 portb = (ioport("md6b")->read() >> 8) & 0xff;
420		UINT8 extra = ioport("md6b_extra")->read() & 0x0f;
	414	UINT8 porta = m_md6b->read() & 0xff;
	415	UINT8 portb = (m_md6b->read() >> 8) & 0xff;
	416	UINT8 extra = m_md6b_extra->read() & 0x0f;
421	417
422	418	switch(m_mdctrl.seq1)
423	419	{
r29505	r29506
453	449	}
454	450	if(port == 2)
455	451	{
456		UINT8 porta = (ioport("md6b")->read() >> 16) & 0xff;
457		UINT8 portb = (ioport("md6b")->read() >> 24) & 0xff;
458		UINT8 extra = (ioport("md6b_extra")->read() >> 4) & 0x0f;
	452	UINT8 porta = (m_md6b->read() >> 16) & 0xff;
	453	UINT8 portb = (m_md6b->read() >> 24) & 0xff;
	454	UINT8 extra = (m_md6b_extra->read() >> 4) & 0x0f;
459	455
460	456	switch(m_mdctrl.seq2)
461	457	{
r29505	r29506
503	499	{
504	500	if(port == 1)
505	501	{
506		UINT8 porta = ioport("xpd1lr")->read() & 0xff;
507		UINT8 portb = (ioport("xpd1lr")->read() >> 8) & 0xff;
	502	UINT8 porta = m_xpd1lr->read() & 0xff;
	503	UINT8 portb = (m_xpd1lr->read() >> 8) & 0xff;
508	504	if(m_mdctrl.mux1 & 0x10)
509	505	{
510	506	return porta;
r29505	r29506
516	512	}
517	513	if(port == 2)
518	514	{
519		UINT8 porta = (ioport("xpd1lr")->read() >> 16) & 0xff;
520		UINT8 portb = (ioport("xpd1lr")->read() >> 24) & 0xff;
	515	UINT8 porta = (m_xpd1lr->read() >> 16) & 0xff;
	516	UINT8 portb = (m_xpd1lr->read() >> 24) & 0xff;
521	517	if(m_mdctrl.mux2 & 0x20)
522	518	{
523	519	return porta;
r29505	r29506
533	529	// Judging from the XM6 source code, PPI ports A and B are joystick inputs
534	530	READ8_MEMBER(x68k_state::ppi_port_a_r)
535	531	{
536		int ctrl = ioport("ctrltype")->read() & 0x0f;
	532	int ctrl = m_ctrltype->read() & 0x0f;
537	533
538	534	switch(ctrl)
539	535	{
540	536	case 0x00:  // standard MSX/FM-Towns joystick
541	537	if(m_joy.joy1_enable == 0)
542		return ioport("joy1")->read();
	538	return m_joy1->read();
543	539	else
544	540	return 0xff;
545	541	case 0x01:  // 3-button Megadrive gamepad
r29505	r29506
555	551
556	552	READ8_MEMBER(x68k_state::ppi_port_b_r)
557	553	{
558		int ctrl = ioport("ctrltype")->read() & 0xf0;
	554	int ctrl = m_ctrltype->read() & 0xf0;
559	555
560	556	switch(ctrl)
561	557	{
562	558	case 0x00:  // standard MSX/FM-Towns joystick
563	559	if(m_joy.joy2_enable == 0)
564		return ioport("joy2")->read();
	560	return m_joy2->read();
565	561	else
566	562	return 0xff;
567	563	case 0x10:  // 3-button Megadrive gamepad
r29505	r29506
736	732	return m_fdc.fdc->dma_w(data);
737	733	}
738	734
739		WRITE_LINE_MEMBER( x68k_state::fdc_drq )
740		{
741		bool ostate = m_fdc.drq_state;
742		m_fdc.drq_state = state;
743		if(state && !ostate)
744		{
745		m_hd63450->single_transfer(0);
746		}
747		}
748
749	735	WRITE16_MEMBER(x68k_state::x68k_fm_w)
750	736	{
751	737	switch(offset)
752	738	{
753	739	case 0x00:
754	740	case 0x01:
755		machine().device<ym2151_device>("ym2151")->write(space, offset, data);
	741	m_ym2151->write(space, offset, data);
756	742	break;
757	743	}
758	744	}
r29505	r29506
760	746	READ16_MEMBER(x68k_state::x68k_fm_r)
761	747	{
762	748	if(offset == 0x01)
763		return machine().device<ym2151_device>("ym2151")->read(space, 1);
	749	return m_ym2151->read(space, 1);
764	750
765	751	return 0xffff;
766	752	}
r29505	r29506
901	887
902	888	WRITE16_MEMBER(x68k_state::x68k_ppi_w)
903	889	{
904		i8255_device *ppi = machine().device<i8255_device>("ppi8255");
905		ppi->write(space,offset & 0x03,data);
	890	m_ppi->write(space,offset & 0x03,data);
906	891	}
907	892
908	893	READ16_MEMBER(x68k_state::x68k_ppi_r)
909	894	{
910		i8255_device *ppi = machine().device<i8255_device>("ppi8255");
911		return ppi->read(space,offset & 0x03);
	895	return m_ppi->read(space,offset & 0x03);
912	896	}
913	897
914	898
r29505	r29506
1066	1050	then access causes a bus error */
1067	1051	m_current_vector[2] = 0x02;  // bus error
1068	1052	m_current_irq_line = 2;
1069		if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1053	if((m_options->read() & 0x02) && !space.debugger_access())
1070	1054	set_bus_error((offset << 1) + 0xbffffc, 0, mem_mask);
1071	1055	return 0xff;
1072	1056	}
r29505	r29506
1077	1061	then access causes a bus error */
1078	1062	m_current_vector[2] = 0x02;  // bus error
1079	1063	m_current_irq_line = 2;
1080		if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1064	if((m_options->read() & 0x02) && !space.debugger_access())
1081	1065	set_bus_error((offset << 1) + 0xbffffc, 1, mem_mask);
1082	1066	}
1083	1067
r29505	r29506
1087	1071	Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
1088	1072	m_current_vector[2] = 0x02;  // bus error
1089	1073	m_current_irq_line = 2;
1090		if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1074	if((m_options->read() & 0x02) && !space.debugger_access())
1091	1075	set_bus_error((offset << 1), 0, mem_mask);
1092	1076	return 0xff;
1093	1077	}
r29505	r29506
1098	1082	Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
1099	1083	m_current_vector[2] = 0x02;  // bus error
1100	1084	m_current_irq_line = 2;
1101		if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1085	if((m_options->read() & 0x02) && !space.debugger_access())
1102	1086	set_bus_error((offset << 1), 1, mem_mask);
1103	1087	}
1104	1088
r29505	r29506
1107	1091	/* These are expansion devices, if not present, they cause a bus error */
1108	1092	m_current_vector[2] = 0x02;  // bus error
1109	1093	m_current_irq_line = 2;
1110		if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1094	if((m_options->read() & 0x02) && !space.debugger_access())
1111	1095	set_bus_error((offset << 1) + 0xeafa00, 0, mem_mask);
1112	1096	return 0xff;
1113	1097	}
r29505	r29506
1117	1101	/* These are expansion devices, if not present, they cause a bus error */
1118	1102	m_current_vector[2] = 0x02;  // bus error
1119	1103	m_current_irq_line = 2;
1120		if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1104	if((m_options->read() & 0x02) && !space.debugger_access())
1121	1105	set_bus_error((offset << 1) + 0xeafa00, 1, mem_mask);
1122	1106	}
1123	1107
r29505	r29506
1147	1131	{
1148	1132	m_current_vector[3] = m_hd63450->get_error_vector(offset);
1149	1133	m_current_irq_line = 3;
	1134	logerror("DMA#%i: DMA Error (vector 0x%02x)\n",offset,m_current_vector[3]);
1150	1135	m_maincpu->set_input_line_and_vector(3,ASSERT_LINE,m_current_vector[3]);
1151	1136	}
1152	1137	}
r29505	r29506
1603	1588
1604	1589	}
1605	1590
1606		static const mb89352_interface x68k_scsi_intf =
1607		{
1608		DEVCB_DRIVER_LINE_MEMBER(x68k_state,x68k_scsi_irq),
1609		DEVCB_DRIVER_LINE_MEMBER(x68k_state,x68k_scsi_drq)
1610		};
1611
1612	1591	static X68K_EXPANSION_INTERFACE(x68k_exp_intf)
1613	1592	{
1614	1593	DEVCB_DRIVER_LINE_MEMBER(x68k_state,x68k_irq2_line),
r29505	r29506
1799	1778	m_led_timer = timer_alloc(TIMER_X68K_LED);
1800	1779	m_net_timer = timer_alloc(TIMER_X68K_NET_IRQ);
1801	1780	m_fdc_tc = timer_alloc(TIMER_X68K_FDC_TC);
	1781	m_adpcm_timer = timer_alloc(TIMER_X68K_ADPCM);
1802	1782
1803	1783	// Initialise timers for 6-button MD controllers
1804	1784	md_6button_init();
r29505	r29506
1897	1877
1898	1878	MCFG_UPD72065_ADD("upd72065", true, true)
1899	1879	MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(x68k_state, fdc_irq))
1900		MCFG_UPD765_DRQ_CALLBACK(WRITELINE(x68k_state, fdc_drq))
	1880	MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("hd63450", hd63450_device, drq0_w))
1901	1881	MCFG_FLOPPY_DRIVE_ADD("upd72065:0", x68k_floppies, "525hd", x68k_state::floppy_formats)
1902	1882	MCFG_FLOPPY_DRIVE_ADD("upd72065:1", x68k_floppies, "525hd", x68k_state::floppy_formats)
1903	1883	MCFG_FLOPPY_DRIVE_ADD("upd72065:2", x68k_floppies, "525hd", x68k_state::floppy_formats)
r29505	r29506
1938	1918	MCFG_SCSIDEV_ADD("scsi:harddisk4", SCSIHD, SCSI_ID_4)
1939	1919	MCFG_SCSIDEV_ADD("scsi:harddisk5", SCSIHD, SCSI_ID_5)
1940	1920	MCFG_SCSIDEV_ADD("scsi:harddisk6", SCSIHD, SCSI_ID_6)
1941		MCFG_MB89352A_ADD("scsi:mb89352",x68k_scsi_intf)
	1921	MCFG_DEVICE_ADD("scsi:mb89352", MB89352A, 0)
	1922	MCFG_MB89352A_IRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, x68k_state, x68k_scsi_irq))
	1923	MCFG_MB89352A_DRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, x68k_state, x68k_scsi_drq))
1942	1924	MACHINE_CONFIG_END
1943	1925
1944	1926	static MACHINE_CONFIG_START( x68kxvi, x68k_state )
r29505	r29506
1959	1941	MCFG_SCSIDEV_ADD("scsi:harddisk4", SCSIHD, SCSI_ID_4)
1960	1942	MCFG_SCSIDEV_ADD("scsi:harddisk5", SCSIHD, SCSI_ID_5)
1961	1943	MCFG_SCSIDEV_ADD("scsi:harddisk6", SCSIHD, SCSI_ID_6)
1962		MCFG_MB89352A_ADD("scsi:mb89352",x68k_scsi_intf)
	1944	MCFG_DEVICE_ADD("scsi:mb89352", MB89352A, 0)
	1945	MCFG_MB89352A_IRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, x68k_state, x68k_scsi_irq))
	1946	MCFG_MB89352A_DRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, x68k_state, x68k_scsi_drq))
1963	1947	MACHINE_CONFIG_END
1964	1948
1965	1949	static MACHINE_CONFIG_START( x68030, x68k_state )
r29505	r29506
1981	1965	MCFG_SCSIDEV_ADD("scsi:harddisk4", SCSIHD, SCSI_ID_4)
1982	1966	MCFG_SCSIDEV_ADD("scsi:harddisk5", SCSIHD, SCSI_ID_5)
1983	1967	MCFG_SCSIDEV_ADD("scsi:harddisk6", SCSIHD, SCSI_ID_6)
1984		MCFG_MB89352A_ADD("scsi:mb89352",x68k_scsi_intf)
	1968	MCFG_DEVICE_ADD("scsi:mb89352", MB89352A, 0)
	1969	MCFG_MB89352A_IRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, x68k_state, x68k_scsi_irq))
	1970	MCFG_MB89352A_DRQ_CB(DEVWRITELINE(DEVICE_SELF_OWNER, x68k_state, x68k_scsi_drq))
1985	1971	MACHINE_CONFIG_END
1986	1972
1987	1973	ROM_START( x68000 )

branches/new_menus/src/mess/drivers/pdp1.c

r29505	r29506
351	351	}
352	352
353	353
354		static const crt_interface pdp1_crt_interface =
355		{
356		pen_crt_num_levels,
357		crt_window_offset_x, crt_window_offset_y,
358		crt_window_width, crt_window_height
359		};
360
361
362	354	/*
363	355	pdp1 machine code
364	356
r29505	r29506
1945	1937	MCFG_CPU_PROGRAM_MAP(pdp1_map)
1946	1938	MCFG_CPU_VBLANK_INT_DRIVER("screen", pdp1_state,  pdp1_interrupt)   /* dummy interrupt: handles input */
1947	1939
1948
1949	1940	/* video hardware (includes the control panel and typewriter output) */
1950	1941	MCFG_SCREEN_ADD("screen", RASTER)
1951	1942	MCFG_SCREEN_REFRESH_RATE(refresh_rate)
r29505	r29506
1956	1947	MCFG_SCREEN_VBLANK_DRIVER(pdp1_state, screen_eof_pdp1)
1957	1948	MCFG_SCREEN_PALETTE("palette")
1958	1949
1959		MCFG_CRT_ADD( "crt", pdp1_crt_interface )
	1950	MCFG_DEVICE_ADD("crt", CRT, 0)
	1951	MCFG_CRT_NUM_LEVELS(pen_crt_num_levels)
	1952	MCFG_CRT_OFFSETS(crt_window_offset_x, crt_window_offset_y)
	1953	MCFG_CRT_SIZE(crt_window_width, crt_window_height)
	1954
1960	1955	MCFG_DEVICE_ADD("readt", PDP1_READTAPE, 0)
1961	1956	MCFG_DEVICE_ADD("punch", PDP1_PUNCHTAPE, 0)
1962	1957	MCFG_DEVICE_ADD("typewriter", PDP1_PRINTER, 0)

branches/new_menus/src/mess/drivers/selz80.c

r29505	r29506
153	153	return data;
154	154	}
155	155
156		static I8279_INTERFACE( selz80_intf )
157		{
158		DEVCB_NULL, // irq
159		DEVCB_DRIVER_MEMBER(selz80_state, scanlines_w), // scan SL lines
160		DEVCB_DRIVER_MEMBER(selz80_state, digit_w),     // display A&B
161		DEVCB_NULL,                     // BD
162		DEVCB_DRIVER_MEMBER(selz80_state, kbd_r),       // kbd RL lines
163		DEVCB_LINE_VCC,                     // Shift key
164		DEVCB_LINE_VCC
165		};
166
167	156	static MACHINE_CONFIG_START( selz80, selz80_state )
168	157	/* basic machine hardware */
169	158	MCFG_CPU_ADD("maincpu",Z80, XTAL_4MHz)
r29505	r29506
174	163	MCFG_DEFAULT_LAYOUT(layout_selz80)
175	164
176	165	/* Devices */
177		MCFG_I8279_ADD("i8279", 2500000, selz80_intf) // based on divider
	166	MCFG_DEVICE_ADD("i8279", I8279, 2500000) // based on divider
	167	MCFG_I8279_OUT_SL_CB(WRITE8(selz80_state, scanlines_w))         // scan SL lines
	168	MCFG_I8279_OUT_DISP_CB(WRITE8(selz80_state, digit_w))         // display A&B
	169	MCFG_I8279_IN_RL_CB(READ8(selz80_state, kbd_r))               // kbd RL lines
	170	MCFG_I8279_IN_SHIFT_CB(VCC)                              // Shift key
	171	MCFG_I8279_IN_CTRL_CB(VCC)
178	172	MACHINE_CONFIG_END
179	173
180	174	static MACHINE_CONFIG_DERIVED( dagz80, selz80 )

branches/new_menus/src/mess/drivers/digel804.c

r29505	r29506
585	585	MCFG_CPU_IO_MAP(z80_io_1_4)
586	586	MCFG_QUANTUM_TIME(attotime::from_hz(60))
587	587
588		MCFG_ROC10937_ADD("vfd",0,RIGHT_TO_LEFT)
	588	MCFG_ROC10937_ADD("vfd",0) // RIGHT_TO_LEFT
589	589
590	590	/* video hardware */
591	591	MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, digel804_terminal_intf)

branches/new_menus/src/mess/drivers/cat.c

r29505	r29506
282	282	data, though track 0 is just a disk "unique" identifier for the cat
283	283	meaning 404480 usable bytes
284	284	* (Once the floppy is working I'd declare the system working)
285		- WIP: Centronics port (not sure what is wrong right now, ip4 is never reading
286		as high meaning nothing works; does our centronics implementation correctly
287		assert BUSY at all?)
	285	- Centronics port finishing touches: verify where the paper out, slct/err, and IPP pins map in memory
288	286	- RS232C port and Modem "port" connected to the DUART's two ports
	287	These are currently optionally debug-logged but don't connect anywhere
289	288	- DTMF generator chip (connected to DUART 'user output' pins OP4,5,6,7)
290	289	- WIP: Watchdog timer/powerfail at 0x85xxxx (watchdog NMI needs to actually
291	290	fire if wdt goes above a certain number, possibly 3, 7 or F?)
r29505	r29506
308	307	happens inside an asic) for the SVROMS (or the svram or the code roms, for
309	308	that matter!)
310	309	- Hook Battery Low input to a dipswitch.
311		- Hook pfail to a dipswitch?
	310	- Hook pfail to a dipswitch.
312	311	- Hook the floppy control register readback up properly, things seem to get
313	312	confused.
314	313
r29505	r29506
341	340	#undef DEBUG_FLOPPY_DATA_R
342	341	#undef DEBUG_FLOPPY_STATUS_R
343	342
344		#define DEBUG_PRINTER_DATA_W 1
	343	#undef DEBUG_PRINTER_DATA_W
345	344	#undef DEBUG_PRINTER_CONTROL_W
346	345
347	346	#undef DEBUG_MODEM_R
r29505	r29506
353	352	// data sent to modem chip
354	353	#undef DEBUG_DUART_TXB
355	354	#undef DEBUG_DUART_IRQ_HANDLER
356		#define DEBUG_PRN_FF 1
	355	#undef DEBUG_PRN_FF
357	356
358	357	#undef DEBUG_TEST_W
359	358
r29505	r29506
820	819	* \--------- (unused?)
821	820	*/
822	821	#ifdef DEBUG_GA2OPR_W
823		fprintf(stderr, "GA2 OPR (video ena/inv, watchdog, and phone relay) reg write: offset %06X, data %04X\n", 0x840000+(offset<<1), data);
	822	if (data != 0x001C)
	823	fprintf(stderr, "GA2 OPR (video ena/inv, watchdog, and phone relay) reg write: offset %06X, data %04X\n", 0x840000+(offset<<1), data);
824	824	#endif
825	825	if (data&0x08) m_wdt_counter = 0;
826	826	m_video_enable = BIT( data, 2 );
r29505	r29506
834	834	* before each write to SVRAM, the forth code does NOT actually do that!
835	835	*
836	836	* 76543210
837		* ??????\\-- Watchdog count? (counts upward? if this reaches <some unknown number greater than 2> the watchdog fires? writing bit 3 set to opr above resets this)
	837	* ??????\\-- Watchdog count? (counts upward? if this reaches <some unknown number greater than 3> the watchdog fires? writing bit 3 set to opr above resets this)
838	838	*
839	839	* FEDCBA98
840	840	* |||||||\-- PFAIL state (MB3771 comparator: 1: vcc = 5v; 0: vcc != 5v, hence do not write to svram!)
r29505	r29506
1673	1673	ROMX_LOAD( "boulth1.ic5", 0x20000, 0x10000, CRC(bed1f761) SHA1(d177e1d3a39b005dd94a6bda186221d597129af4), ROM_SKIP(1) | ROM_BIOS(1))
1674	1674	/* This 2.40 code was compiled by Dwight Elvey based on the v2.40 source
1675	1675	* code disks recovered around 2004. It does NOT exactly match the above
1676		* set exactly but has a few small differences.
	1676	* set exactly but has a few small differences. One of the printer drivers
	1677	* may have been replaced by Dwight with an HP PCL4 driver.
1677	1678	* It is as of yet unknown whether it is earlier or later code than the
1678	1679	* set above.
1679	1680	*/

branches/new_menus/src/mess/drivers/tx0.c

r29505	r29506
300	300	}
301	301
302	302
303		static const crt_interface tx0_crt_interface =
304		{
305		pen_crt_num_levels,
306		crt_window_offset_x, crt_window_offset_y,
307		crt_window_width, crt_window_height
308		};
309	303
310
311	304	/*
312	305	TX-0
313	306	*
r29505	r29506
316	309
317	310
318	311
319
320
321
322
323
324
325
326
327
328
329
330	312	/* crt display timer */
331	313
332	314
r29505	r29506
1579	1561	/* dummy interrupt: handles input */
1580	1562	MCFG_CPU_VBLANK_INT_DRIVER("screen", tx0_state,  tx0_interrupt)
1581	1563
1582
1583	1564	/* video hardware (includes the control panel and typewriter output) */
1584	1565	MCFG_SCREEN_ADD("screen", RASTER)
1585	1566	MCFG_SCREEN_REFRESH_RATE(refresh_rate)
r29505	r29506
1590	1571	MCFG_SCREEN_VBLANK_DRIVER(tx0_state, screen_eof_tx0)
1591	1572	MCFG_SCREEN_PALETTE("palette")
1592	1573
1593		MCFG_CRT_ADD( "crt", tx0_crt_interface )
	1574	MCFG_DEVICE_ADD("crt", CRT, 0)
	1575	MCFG_CRT_NUM_LEVELS(pen_crt_num_levels)
	1576	MCFG_CRT_OFFSETS(crt_window_offset_x, crt_window_offset_y)
	1577	MCFG_CRT_SIZE(crt_window_width, crt_window_height)
	1578
1594	1579	MCFG_DEVICE_ADD("readt", TX0_READTAPE, 0)
1595	1580	MCFG_DEVICE_ADD("punch", TX0_PUNCHTAPE, 0)
1596	1581	MCFG_DEVICE_ADD("typewriter", TX0_PRINTER, 0)

branches/new_menus/src/mess/machine/sms.c

r29505	r29506
804	804	save_item(NAME(m_ctrl2_th_latch));
805	805	save_item(NAME(m_ctrl1_th_state));
806	806	save_item(NAME(m_ctrl2_th_state));
	807	save_item(NAME(m_lphaser_x_offs));
807	808	}
808	809
809	810	if (m_is_gamegear)
r29505	r29506
871	872
872	873	READ8_MEMBER(smssdisp_state::sms_store_cart_select_r)
873	874	{
874		return 0xff;
	875	return m_store_cart_selection_data;
875	876	}
876	877
877	878
r29505	r29506
897	898	UINT8 slot = data >> 4;
898	899	UINT8 slottype = data & 0x08;
899	900
900		// The SMS Store Display only uses the logical cartridge slot to map
901		// the active cartridge or card slot, of its multiple ones.
	901	// The SMS Store Display Unit only uses the logical cartridge slot to
	902	// map the active cartridge or card slot, of its multiple ones.
902	903	if (slottype == 0)
903	904	m_cartslot = m_slots[slot];
904	905	else
r29505	r29506
907	908	logerror("switching in part of %s slot #%d\n", slottype ? "card" : "cartridge", slot);
908	909	}
909	910
910
911		READ8_MEMBER(smssdisp_state::sms_store_select1)
912		{
913		return 0xff;
914		}
915
916
917		READ8_MEMBER(smssdisp_state::sms_store_select2)
918		{
919		return 0xff;
920		}
921
922
923		READ8_MEMBER(smssdisp_state::sms_store_control_r)
924		{
925		return m_store_control;
926		}
927
928
929	911	WRITE8_MEMBER(smssdisp_state::sms_store_control_w)
930	912	{
	913	int led_number = data >> 4;
	914	int led_column = led_number / 4;
	915	int led_line = 3 - (led_number % 4);
	916	int game_number = (4 * led_column) + led_line;
	917
931	918	logerror("0x%04X: sms_store_control write 0x%02X\n", space.device().safe_pc(), data);
	919	logerror("sms_store_control: LED #%d activated for game #%d\n", led_number, game_number);
	920
932	921	if (data & 0x02)
933	922	{
934	923	m_maincpu->resume(SUSPEND_REASON_HALT);

branches/new_menus/src/mess/machine/megacd.c

r29505	r29506
2	2	#include "machine/megacd.h"
3	3	#include "machine/nvram.h"
4	4	#include "megacd.lh"
5		#include "sound/rf5c68.h"
6	5
7	6
	7	const device_type SEGA_SEGACD_US = &device_creator<sega_segacd_us_device>;
	8	const device_type SEGA_SEGACD_JAPAN = &device_creator<sega_segacd_japan_device>;
	9	const device_type SEGA_SEGACD_EUROPE = &device_creator<sega_segacd_europe_device>;
	10
	11
8	12	/* Callback when the genesis enters interrupt code */
9	13	IRQ_CALLBACK_MEMBER(sega_segacd_device::segacd_sub_int_callback)
10	14	{
r29505	r29506
19	23	}
20	24
21	25
22		const device_type SEGA_SEGACD_US = &device_creator<sega_segacd_us_device>;
23		const device_type SEGA_SEGACD_JAPAN = &device_creator<sega_segacd_japan_device>;
24		const device_type SEGA_SEGACD_EUROPE = &device_creator<sega_segacd_europe_device>;
25
26		sega_segacd_device::sega_segacd_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
27		: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
28		m_scdcpu(*this, "segacd_68k"),
29		m_gfxdecode(*this, "gfxdecode")
	26	TIMER_DEVICE_CALLBACK_MEMBER( sega_segacd_device::irq3_timer_callback )
30	27	{
31		}
32
33		sega_segacd_us_device::sega_segacd_us_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
34		: sega_segacd_device(mconfig, SEGA_SEGACD_US, "sega_segacd_us", tag, owner, clock, "sega_segacd_us", __FILE__)
35		{
36		}
37
38		sega_segacd_japan_device::sega_segacd_japan_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
39		: sega_segacd_device(mconfig, SEGA_SEGACD_JAPAN, "sega_segacd_japan", tag, owner, clock, "sega_segacd_japan", __FILE__)
40		{
41		}
42
43		sega_segacd_europe_device::sega_segacd_europe_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
44		: sega_segacd_device(mconfig, SEGA_SEGACD_EUROPE, "sega_segacd_europe", tag, owner, clock, "sega_segacd_europe", __FILE__)
45		{
46		}
47
48
49		TIMER_DEVICE_CALLBACK_MEMBER( sega_segacd_device::segacd_irq3_timer_callback )
50		{
51	28	CHECK_SCD_LV3_INTERRUPT
52		segacd_irq3_timer->adjust(SEGACD_IRQ3_TIMER_SPEED);
	29	m_irq3_timer->adjust(SEGACD_IRQ3_TIMER_SPEED);
53	30	}
54	31
55	32
56		TIMER_DEVICE_CALLBACK_MEMBER( sega_segacd_device::segacd_gfx_conversion_timer_callback )
	33	TIMER_DEVICE_CALLBACK_MEMBER( sega_segacd_device::stamp_timer_callback )
57	34	{
58		//printf("segacd_gfx_conversion_timer_callback\n");
	35	//printf("stamp_timer_callback\n");
59	36
60	37	CHECK_SCD_LV1_INTERRUPT
61	38
r29505	r29506
66	43	}
67	44
68	45
69
70
71		ADDRESS_MAP_START( segacd_map, AS_PROGRAM, 16, sega_segacd_device )
72		AM_RANGE(0x000000, 0x07ffff) AM_RAM AM_SHARE("segacd_program")
73
	46	static ADDRESS_MAP_START( segacd_map, AS_PROGRAM, 16, sega_segacd_device )
	47	AM_RANGE(0x000000, 0x07ffff) AM_RAM AM_SHARE("prgram")
74	48	AM_RANGE(0x080000, 0x0bffff) AM_READWRITE(segacd_sub_dataram_part1_r, segacd_sub_dataram_part1_w) AM_SHARE("dataram")
75	49	AM_RANGE(0x0c0000, 0x0dffff) AM_READWRITE(segacd_sub_dataram_part2_r, segacd_sub_dataram_part2_w) //AM_SHARE("dataram2")
76	50
77		AM_RANGE(0xfe0000, 0xfe3fff) AM_READWRITE(segacd_backupram_r,segacd_backupram_w) AM_SHARE("backupram") // backup RAM, odd bytes only!
	51	AM_RANGE(0xfe0000, 0xfe3fff) AM_READWRITE8(backupram_r, backupram_w, 0x00ff) // backup RAM, odd bytes only!
78	52
79	53	AM_RANGE(0xff0000, 0xff001f) AM_DEVWRITE8("rfsnd", rf5c68_device, rf5c68_w, 0x00ff)  // PCM, RF5C164
80	54	AM_RANGE(0xff0020, 0xff003f) AM_DEVREAD8("rfsnd", rf5c68_device, rf5c68_r, 0x00ff)
81	55	AM_RANGE(0xff2000, 0xff3fff) AM_DEVREADWRITE8("rfsnd", rf5c68_device, rf5c68_mem_r, rf5c68_mem_w,0x00ff)  // PCM, RF5C164
82	56
83
84	57	AM_RANGE(0xff8000 ,0xff8001) AM_READWRITE(segacd_sub_led_ready_r, segacd_sub_led_ready_w)
85	58	AM_RANGE(0xff8002 ,0xff8003) AM_READWRITE(segacd_sub_memory_mode_r, segacd_sub_memory_mode_w)
86	59
r29505	r29506
98	71	AM_RANGE(0xff8036, 0xff8037) AM_DEVREADWRITE("tempcdc",lc89510_temp_device,segacd_cdd_ctrl_r,segacd_cdd_ctrl_w)
99	72	AM_RANGE(0xff8038, 0xff8041) AM_DEVREAD8("tempcdc",lc89510_temp_device,segacd_cdd_rx_r,0xffff)
100	73	AM_RANGE(0xff8042, 0xff804b) AM_DEVWRITE8("tempcdc",lc89510_temp_device,segacd_cdd_tx_w,0xffff)
101		AM_RANGE(0xff804c, 0xff804d) AM_READWRITE(segacd_font_color_r, segacd_font_color_w)
102		AM_RANGE(0xff804e, 0xff804f) AM_RAM AM_SHARE("segacd_font")
103		AM_RANGE(0xff8050, 0xff8057) AM_READ(segacd_font_converted_r)
	74	AM_RANGE(0xff804c, 0xff804d) AM_READWRITE8(font_color_r, font_color_w, 0x00ff)
	75	AM_RANGE(0xff804e, 0xff804f) AM_RAM AM_SHARE("font_bits")
	76	AM_RANGE(0xff8050, 0xff8057) AM_READ(font_converted_r)
104	77	AM_RANGE(0xff8058, 0xff8059) AM_READWRITE(segacd_stampsize_r, segacd_stampsize_w) // Stamp size
105	78	AM_RANGE(0xff805a, 0xff805b) AM_READWRITE(segacd_stampmap_base_address_r, segacd_stampmap_base_address_w) // Stamp map base address
106	79	AM_RANGE(0xff805c, 0xff805d) AM_READWRITE(segacd_imagebuffer_vcell_size_r, segacd_imagebuffer_vcell_size_w)// Image buffer V cell size
r29505	r29506
126	99	#define SEGACD_NUM_TILES16 (0x40000/SEGACD_BYTES_PER_TILE16)
127	100	#define SEGACD_NUM_TILES32 (0x40000/SEGACD_BYTES_PER_TILE32)
128	101
129		#define _16x16_SEQUENCE_1  { 8,12,0,4,24,28,16,20, 512+8, 512+12, 512+0, 512+4, 512+24, 512+28, 512+16, 512+20 },
130		#define _16x16_SEQUENCE_1_FLIP  { 512+20,512+16,512+28,512+24,512+4,512+0, 512+12,512+8, 20,16,28,24,4,0,12,8 },
	102	#define _16x16_SEQUENCE_1  { STEP8(0, 4), STEP8(512, 4) },
	103	#define _16x16_SEQUENCE_1_FLIP  { STEP8(512+28, -4), STEP8(28, -4) },
131	104
132		#define _16x16_SEQUENCE_2  { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32, 8*32, 9*32,10*32,11*32,12*32,13*32,14*32,15*32 },
133		#define _16x16_SEQUENCE_2_FLIP  { 15*32, 14*32, 13*32, 12*32, 11*32, 10*32, 9*32, 8*32, 7*32, 6*32, 5*32, 4*32, 3*32, 2*32, 1*32, 0*32 },
	105	#define _16x16_SEQUENCE_2  { STEP16(0, 32) },
	106	#define _16x16_SEQUENCE_2_FLIP  { STEP16(15*32, -32) },
134	107
135	108
136	109	#define _16x16_START \
r29505	r29506
153	126	8*512 \
154	127	};
155	128
	129	#define _32x32_SEQUENCE_1 { STEP8(0, 4), STEP8(1024, 4), STEP8(2048, 4), STEP8(3072, 4) },
	130	#define _32x32_SEQUENCE_1_FLIP { STEP8(3072+28, -4), STEP8(2048+28, -4), STEP8(1024+28, -4), STEP8(28, -4) },
156	131
157		#define _32x32_SEQUENCE_1 \
158		{ 8,12,0,4,24,28,16,20, \
159		1024+8, 1024+12, 1024+0, 1024+4, 1024+24, 1024+28, 1024+16, 1024+20, \
160		2048+8, 2048+12, 2048+0, 2048+4, 2048+24, 2048+28, 2048+16, 2048+20, \
161		3072+8, 3072+12, 3072+0, 3072+4, 3072+24, 3072+28, 3072+16, 3072+20  \
162		},
163		#define _32x32_SEQUENCE_1_FLIP \
164		{ 3072+20, 3072+16, 3072+28, 3072+24, 3072+4, 3072+0, 3072+12, 3072+8, \
165		2048+20, 2048+16, 2048+28, 2048+24, 2048+4, 2048+0, 2048+12, 2048+8, \
166		1024+20, 1024+16, 1024+28, 1024+24, 1024+4, 1024+0, 1024+12, 1024+8, \
167		20, 16, 28, 24, 4, 0, 12, 8},
	132	#define _32x32_SEQUENCE_2 { STEP32(0, 32) },
	133	#define _32x32_SEQUENCE_2_FLIP { STEP32(31*32, -32) },
168	134
169		#define _32x32_SEQUENCE_2 \
170		{ 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32, \
171		8*32, 9*32, 10*32, 11*32, 12*32, 13*32, 14*32, 15*32, \
172		16*32,17*32,18*32,19*32,20*32,21*32,22*32,23*32, \
173		24*32,25*32, 26*32, 27*32, 28*32, 29*32, 30*32, 31*32},
174		#define _32x32_SEQUENCE_2_FLIP \
175		{ 31*32, 30*32, 29*32, 28*32, 27*32, 26*32, 25*32, 24*32, \
176		23*32, 22*32, 21*32, 20*32, 19*32, 18*32, 17*32, 16*32, \
177		15*32, 14*32, 13*32, 12*32, 11*32, 10*32, 9*32 , 8*32 , \
178		7*32 , 6*32 , 5*32 , 4*32 , 3*32 , 2*32 , 1*32 , 0*32},
179	135
180	136	/* 16x16 decodes */
181	137	static const gfx_layout sega_16x16_r00_f0_layout =
r29505	r29506
275	231	_32x32_SEQUENCE_1_FLIP
276	232	_32x32_END
277	233
278		GFXDECODE_START( segacd )
279		GFXDECODE_ENTRY( NULL, 0, sega_16x16_r00_f0_layout, 0, 0 )
280		GFXDECODE_ENTRY( NULL, 0, sega_16x16_r01_f0_layout, 0, 0 )
281		GFXDECODE_ENTRY( NULL, 0, sega_16x16_r10_f0_layout, 0, 0 )
282		GFXDECODE_ENTRY( NULL, 0, sega_16x16_r11_f0_layout, 0, 0 )
283		GFXDECODE_ENTRY( NULL, 0, sega_16x16_r00_f1_layout, 0, 0 )
284		GFXDECODE_ENTRY( NULL, 0, sega_16x16_r11_f1_layout, 0, 0 )
285		GFXDECODE_ENTRY( NULL, 0, sega_16x16_r10_f1_layout, 0, 0 )
286		GFXDECODE_ENTRY( NULL, 0, sega_16x16_r01_f1_layout, 0, 0 )
287		GFXDECODE_ENTRY( NULL, 0, sega_32x32_r00_f0_layout, 0, 0 )
288		GFXDECODE_ENTRY( NULL, 0, sega_32x32_r01_f0_layout, 0, 0 )
289		GFXDECODE_ENTRY( NULL, 0, sega_32x32_r10_f0_layout, 0, 0 )
290		GFXDECODE_ENTRY( NULL, 0, sega_32x32_r11_f0_layout, 0, 0 )
291		GFXDECODE_ENTRY( NULL, 0, sega_32x32_r00_f1_layout, 0, 0 )
292		GFXDECODE_ENTRY( NULL, 0, sega_32x32_r11_f1_layout, 0, 0 )
293		GFXDECODE_ENTRY( NULL, 0, sega_32x32_r10_f1_layout, 0, 0 )
294		GFXDECODE_ENTRY( NULL, 0, sega_32x32_r01_f1_layout, 0, 0 )
	234	static GFXDECODE_START( segacd )
	235	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_16x16_r00_f0_layout, 0, 0 )
	236	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_16x16_r01_f0_layout, 0, 0 )
	237	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_16x16_r10_f0_layout, 0, 0 )
	238	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_16x16_r11_f0_layout, 0, 0 )
	239	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_16x16_r00_f1_layout, 0, 0 )
	240	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_16x16_r11_f1_layout, 0, 0 )
	241	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_16x16_r10_f1_layout, 0, 0 )
	242	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_16x16_r01_f1_layout, 0, 0 )
	243	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_32x32_r00_f0_layout, 0, 0 )
	244	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_32x32_r01_f0_layout, 0, 0 )
	245	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_32x32_r10_f0_layout, 0, 0 )
	246	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_32x32_r11_f0_layout, 0, 0 )
	247	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_32x32_r00_f1_layout, 0, 0 )
	248	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_32x32_r11_f1_layout, 0, 0 )
	249	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_32x32_r10_f1_layout, 0, 0 )
	250	GFXDECODE_DEVICE_RAM( "dataram", 0, sega_32x32_r01_f1_layout, 0, 0 )
295	251	GFXDECODE_END
296	252
297	253
298
299	254	static MACHINE_CONFIG_FRAGMENT( segacd_fragment )
300	255
301	256	MCFG_CPU_ADD("segacd_68k", M68000, SEGACD_CLOCK ) /* 12.5 MHz */
r29505	r29506
308	263	MCFG_SEGACD_HACK_SET_CDC_DO_DMA( sega_segacd_device, SegaCD_CDC_Do_DMA ) // hack
309	264
310	265	MCFG_TIMER_ADD_NONE("sw_timer") //stopwatch timer
311		MCFG_TIMER_DRIVER_ADD("irq3_timer", sega_segacd_device, segacd_irq3_timer_callback)
312		MCFG_TIMER_DRIVER_ADD("stamp_timer", sega_segacd_device, segacd_gfx_conversion_timer_callback)
313		MCFG_TIMER_DRIVER_ADD("scd_dma_timer", sega_segacd_device, scd_dma_timer_callback)
	266	MCFG_TIMER_DRIVER_ADD("stamp_timer", sega_segacd_device, stamp_timer_callback)
	267	MCFG_TIMER_DRIVER_ADD("irq3_timer", sega_segacd_device, irq3_timer_callback)
	268	MCFG_TIMER_DRIVER_ADD("dma_timer", sega_segacd_device, dma_timer_callback)
314	269
315		MCFG_GFXDECODE_ADD("gfxdecode", "^gen_vdp:palette", segacd) // FIXME
316
317	270	MCFG_DEFAULT_LAYOUT( layout_megacd )
318	271
319	272	MCFG_RF5C68_ADD("rfsnd", SEGACD_CLOCK) // RF5C164!
r29505	r29506
333	286	}
334	287
335	288
	289	sega_segacd_device::sega_segacd_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
	290	: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
	291	device_gfx_interface(mconfig, *this, GFXDECODE_NAME( segacd )),
	292	m_scdcpu(*this, "segacd_68k"),
	293	m_rfsnd(*this, "rfsnd"),
	294	m_lc89510_temp(*this, "tempcdc"),
	295	m_stopwatch_timer(*this, "sw_timer"),
	296	m_stamp_timer(*this, "stamp_timer"),
	297	m_irq3_timer(*this, "irq3_timer"),
	298	m_dma_timer(*this, "dma_timer"),
	299	m_prgram(*this, "prgram"),
	300	m_dataram(*this, "dataram"),
	301	m_font_bits(*this, "font_bits")
	302	{
	303	}
336	304
	305	sega_segacd_us_device::sega_segacd_us_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	306	: sega_segacd_device(mconfig, SEGA_SEGACD_US, "sega_segacd_us", tag, owner, clock, "sega_segacd_us", __FILE__)
	307	{
	308	}
337	309
	310	sega_segacd_japan_device::sega_segacd_japan_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	311	: sega_segacd_device(mconfig, SEGA_SEGACD_JAPAN, "sega_segacd_japan", tag, owner, clock, "sega_segacd_japan", __FILE__)
	312	{
	313	}
338	314
	315	sega_segacd_europe_device::sega_segacd_europe_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	316	: sega_segacd_device(mconfig, SEGA_SEGACD_EUROPE, "sega_segacd_europe", tag, owner, clock, "sega_segacd_europe", __FILE__)
	317	{
	318	}
339	319
340		inline void sega_segacd_device::write_pixel(running_machine& machine, UINT8 pix, int pixeloffset )
	320
	321	inline void sega_segacd_device::write_pixel(UINT8 pix, int pixeloffset)
341	322	{
342	323	int shift = 12-(4*(pixeloffset&0x3));
343	324	UINT16 datamask = (0x000f) << shift;
r29505	r29506
350	331	switch (segacd_memory_priority_mode)
351	332	{
352	333	case 0x00: // normal write, just write the data
353		segacd_dataram[offset] = segacd_dataram[offset] &~ datamask;
354		segacd_dataram[offset] |= pix << shift;
	334	m_dataram[offset] = m_dataram[offset] &~ datamask;
	335	m_dataram[offset] |= pix << shift;
355	336	break;
356	337
357	338	case 0x01: // underwrite, only write if the existing data is 0
358		if ((segacd_dataram[offset]&datamask) == 0x0000)
	339	if ((m_dataram[offset]&datamask) == 0x0000)
359	340	{
360		segacd_dataram[offset] = segacd_dataram[offset] &~ datamask;
361		segacd_dataram[offset] |= pix << shift;
	341	m_dataram[offset] = m_dataram[offset] &~ datamask;
	342	m_dataram[offset] |= pix << shift;
362	343	}
363	344	break;
364	345
365	346	case 0x02: // overwrite, only write non-zero data
366	347	if (pix)
367	348	{
368		segacd_dataram[offset] = segacd_dataram[offset] &~ datamask;
369		segacd_dataram[offset] |= pix << shift;
	349	m_dataram[offset] = m_dataram[offset] &~ datamask;
	350	m_dataram[offset] |= pix << shift;
370	351	}
371	352	break;
372	353
373	354	default:
374	355	case 0x03:
375		pix = machine.rand() & 0x000f;
376		segacd_dataram[offset] = segacd_dataram[offset] &~ datamask;
377		segacd_dataram[offset] |= pix << shift;
	356	pix = machine().rand() & 0x000f;
	357	m_dataram[offset] = m_dataram[offset] &~ datamask;
	358	m_dataram[offset] |= pix << shift;
378	359	break;
379	360
380	361	}
r29505	r29506
393	374
394	375	offset &=0x1ffff;
395	376
396		return segacd_dataram[offset];
	377	return m_dataram[offset];
397	378	}
398	379
399	380
r29505	r29506
413	394	switch (segacd_memory_priority_mode)
414	395	{
415	396	case 0x00: // normal write, just write the data
416		COMBINE_DATA(&segacd_dataram[offset]);
	397	COMBINE_DATA(&m_dataram[offset]);
417	398	break;
418	399
419	400	case 0x01: // underwrite, only write if the existing data is 0
420	401	if (ACCESSING_BITS_8_15)
421	402	{
422		if ((segacd_dataram[offset]&0xf000) == 0x0000) segacd_dataram[offset] |= (data)&0xf000;
423		if ((segacd_dataram[offset]&0x0f00) == 0x0000) segacd_dataram[offset] |= (data)&0x0f00;
	403	if ((m_dataram[offset]&0xf000) == 0x0000) m_dataram[offset] |= (data)&0xf000;
	404	if ((m_dataram[offset]&0x0f00) == 0x0000) m_dataram[offset] |= (data)&0x0f00;
424	405	}
425	406	if (ACCESSING_BITS_0_7)
426	407	{
427		if ((segacd_dataram[offset]&0x00f0) == 0x0000) segacd_dataram[offset] |= (data)&0x00f0;
428		if ((segacd_dataram[offset]&0x000f) == 0x0000) segacd_dataram[offset] |= (data)&0x000f;
	408	if ((m_dataram[offset]&0x00f0) == 0x0000) m_dataram[offset] |= (data)&0x00f0;
	409	if ((m_dataram[offset]&0x000f) == 0x0000) m_dataram[offset] |= (data)&0x000f;
429	410	}
430	411	break;
431	412
432	413	case 0x02: // overwrite, only write non-zero data
433	414	if (ACCESSING_BITS_8_15)
434	415	{
435		if ((data)&0xf000) segacd_dataram[offset] = (segacd_dataram[offset] & 0x0fff) | ((data)&0xf000);
436		if ((data)&0x0f00) segacd_dataram[offset] = (segacd_dataram[offset] & 0xf0ff) | ((data)&0x0f00);
	416	if ((data)&0xf000) m_dataram[offset] = (m_dataram[offset] & 0x0fff) | ((data)&0xf000);
	417	if ((data)&0x0f00) m_dataram[offset] = (m_dataram[offset] & 0xf0ff) | ((data)&0x0f00);
437	418	}
438	419	if (ACCESSING_BITS_0_7)
439	420	{
440		if ((data)&0x00f0) segacd_dataram[offset] = (segacd_dataram[offset] & 0xff0f) | ((data)&0x00f0);
441		if ((data)&0x000f) segacd_dataram[offset] = (segacd_dataram[offset] & 0xfff0) | ((data)&0x000f);
	421	if ((data)&0x00f0) m_dataram[offset] = (m_dataram[offset] & 0xff0f) | ((data)&0x00f0);
	422	if ((data)&0x000f) m_dataram[offset] = (m_dataram[offset] & 0xfff0) | ((data)&0x000f);
442	423	}
443	424	break;
444	425
445	426	default:
446	427	case 0x03: // invalid?
447		COMBINE_DATA(&segacd_dataram[offset]);
	428	COMBINE_DATA(&m_dataram[offset]);
448	429	break;
449	430
450	431	}
451	432	}
452	433	else
453	434	{
454		COMBINE_DATA(&segacd_dataram[offset]);
	435	COMBINE_DATA(&m_dataram[offset]);
455	436	}
456	437	}
457	438
r29505	r29506
731	712	READ16_MEMBER( sega_segacd_device::scd_4m_prgbank_ram_r )
732	713	{
733	714	UINT16 realoffset = ((segacd_4meg_prgbank * 0x20000)/2) + offset;
734		return segacd_4meg_prgram[realoffset];
	715	return m_prgram[realoffset];
735	716
736	717	}
737	718
r29505	r29506
742	723	// todo:
743	724	// check for write protection? (or does that only apply to writes on the SubCPU side?
744	725
745		COMBINE_DATA(&segacd_4meg_prgram[realoffset]);
	726	COMBINE_DATA(&m_prgram[realoffset]);
746	727
747	728	}
748	729
r29505	r29506
797	778	// is this correct?
798	779	if (!(scd_rammode&1))
799	780	{
800		//printf("segacd_main_dataram_part1_r in mode 0 %08x %04x\n", offset*2, segacd_dataram[offset]);
	781	//printf("segacd_main_dataram_part1_r in mode 0 %08x %04x\n", offset*2, m_dataram[offset]);
801	782
802		return segacd_dataram[offset];
	783	return m_dataram[offset];
803	784
804	785	}
805	786	else
r29505	r29506
864	845	// is this correct?
865	846	if (!(scd_rammode&1))
866	847	{
867		COMBINE_DATA(&segacd_dataram[offset]);
868		segacd_mark_tiles_dirty(space.machine(), offset);
	848	COMBINE_DATA(&m_dataram[offset]);
	849	segacd_mark_tiles_dirty(offset);
869	850	}
870	851	else
871	852	{
r29505	r29506
925	906	}
926	907
927	908
928
929
930
931
932		void sega_segacd_device::segacd_mark_tiles_dirty(running_machine& machine, int offset)
	909	void sega_segacd_device::segacd_mark_tiles_dirty(int offset)
933	910	{
934		m_gfxdecode->gfx(0)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
935		m_gfxdecode->gfx(1)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
936		m_gfxdecode->gfx(2)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
937		m_gfxdecode->gfx(3)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
938		m_gfxdecode->gfx(4)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
939		m_gfxdecode->gfx(5)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
940		m_gfxdecode->gfx(6)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
941		m_gfxdecode->gfx(7)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
	911	gfx(0)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
	912	gfx(1)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
	913	gfx(2)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
	914	gfx(3)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
	915	gfx(4)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
	916	gfx(5)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
	917	gfx(6)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
	918	gfx(7)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE16));
942	919
943		m_gfxdecode->gfx(8)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
944		m_gfxdecode->gfx(9)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
945		m_gfxdecode->gfx(10)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
946		m_gfxdecode->gfx(11)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
947		m_gfxdecode->gfx(12)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
948		m_gfxdecode->gfx(13)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
949		m_gfxdecode->gfx(14)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
950		m_gfxdecode->gfx(15)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
	920	gfx(8)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
	921	gfx(9)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
	922	gfx(10)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
	923	gfx(11)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
	924	gfx(12)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
	925	gfx(13)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
	926	gfx(14)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
	927	gfx(15)->mark_dirty((offset*2)/(SEGACD_BYTES_PER_TILE32));
951	928	}
952	929
953	930
r29505	r29506
964	941	tile_region = 0; // 16x16 tiles
965	942	int tile_base = (segacd_stampmap_base_address & 0xff80) * 4;
966	943
967		int tiledat = segacd_dataram[((tile_base>>1)+tile_index) & 0x1ffff];
	944	int tiledat = m_dataram[((tile_base>>1)+tile_index) & 0x1ffff];
968	945	tileno = tiledat & 0x07ff;
969	946	int xflip =  tiledat & 0x8000;
970	947	int roll  =  (tiledat & 0x6000)>>13;
r29505	r29506
978	955	tile_region = 8; // 32x32 tiles
979	956	int tile_base = (segacd_stampmap_base_address & 0xffe0) * 4;
980	957
981		int tiledat = segacd_dataram[((tile_base>>1)+tile_index) & 0x1ffff];
	958	int tiledat = m_dataram[((tile_base>>1)+tile_index) & 0x1ffff];
982	959	tileno = (tiledat & 0x07fc)>>2;
983	960	int xflip =  tiledat & 0x8000;
984	961	int roll  =  (tiledat & 0x6000)>>13;
r29505	r29506
993	970	tile_region = 0; // 16x16 tiles
994	971	int tile_base = (0x8000) * 4; // fixed address in this mode
995	972
996		int tiledat = segacd_dataram[((tile_base>>1)+tile_index) & 0x1ffff];
	973	int tiledat = m_dataram[((tile_base>>1)+tile_index) & 0x1ffff];
997	974	tileno = tiledat & 0x07ff;
998	975	int xflip =  tiledat & 0x8000;
999	976	int roll  =  (tiledat & 0x6000)>>13;
r29505	r29506
1008	985	tile_region = 8; // 32x32 tiles
1009	986	int tile_base = (segacd_stampmap_base_address & 0xe000) * 4;
1010	987
1011		int tiledat = segacd_dataram[((tile_base>>1)+tile_index) & 0x1ffff];
	988	int tiledat = m_dataram[((tile_base>>1)+tile_index) & 0x1ffff];
1012	989	tileno = (tiledat & 0x07fc)>>2;
1013	990	int xflip =  tiledat & 0x8000;
1014	991	int roll  =  (tiledat & 0x6000)>>13;
r29505	r29506
1052	1029
1053	1030	// non-tilemap functions to get a pixel from a 'tilemap' based on the above, but looking up each pixel, as to avoid the heavy cache bitmap
1054	1031
1055		inline UINT8 sega_segacd_device::get_stampmap_16x16_1x1_tile_info_pixel(running_machine& machine, int xpos, int ypos)
	1032	inline UINT8 sega_segacd_device::get_stampmap_16x16_1x1_tile_info_pixel(int xpos, int ypos)
1056	1033	{
1057	1034	const int tilesize = 4; // 0xf pixels
1058	1035	const int tilemapsize = 0x0f;
r29505	r29506
1082	1059	int tile_region, tileno;
1083	1060	SCD_GET_TILE_INFO_16x16_1x1(tile_region,tileno,(int)tile_index);
1084	1061
1085		gfx_element *gfx = m_gfxdecode->gfx(tile_region);
1086		tileno %= gfx->elements();
	1062	tileno %= gfx(tile_region)->elements();
1087	1063
1088	1064	if (tileno==0) return 0x00;
1089	1065
1090		const UINT8* srcdata = gfx->get_data(tileno);
	1066	const UINT8* srcdata = gfx(tile_region)->get_data(tileno);
1091	1067	return srcdata[((ypos&((1<<tilesize)-1))*(1<<tilesize))+(xpos&((1<<tilesize)-1))];
1092	1068	}
1093	1069
1094		inline UINT8 sega_segacd_device::get_stampmap_32x32_1x1_tile_info_pixel(running_machine& machine, int xpos, int ypos)
	1070	inline UINT8 sega_segacd_device::get_stampmap_32x32_1x1_tile_info_pixel(int xpos, int ypos)
1095	1071	{
1096	1072	const int tilesize = 5; // 0x1f pixels
1097	1073	const int tilemapsize = 0x07;
r29505	r29506
1121	1097	int tile_region, tileno;
1122	1098	SCD_GET_TILE_INFO_32x32_1x1(tile_region,tileno,(int)tile_index);
1123	1099
1124		gfx_element *gfx = m_gfxdecode->gfx(tile_region);
1125		tileno %= gfx->elements();
	1100	tileno %= gfx(tile_region)->elements();
1126	1101
1127	1102	if (tileno==0) return 0x00; // does this apply in this mode?
1128	1103
1129		const UINT8* srcdata = gfx->get_data(tileno);
	1104	const UINT8* srcdata = gfx(tile_region)->get_data(tileno);
1130	1105	return srcdata[((ypos&((1<<tilesize)-1))*(1<<tilesize))+(xpos&((1<<tilesize)-1))];
1131	1106	}
1132	1107
1133		inline UINT8 sega_segacd_device::get_stampmap_16x16_16x16_tile_info_pixel(running_machine& machine, int xpos, int ypos)
	1108	inline UINT8 sega_segacd_device::get_stampmap_16x16_16x16_tile_info_pixel(int xpos, int ypos)
1134	1109	{
1135	1110	const int tilesize = 4; // 0xf pixels
1136	1111	const int tilemapsize = 0xff;
r29505	r29506
1160	1135	int tile_region, tileno;
1161	1136	SCD_GET_TILE_INFO_16x16_16x16(tile_region,tileno,(int)tile_index);
1162	1137
1163		gfx_element *gfx = m_gfxdecode->gfx(tile_region);
1164		tileno %= gfx->elements();
	1138	tileno %= gfx(tile_region)->elements();
1165	1139
1166	1140	if (tileno==0) return 0x00; // does this apply in this mode
1167	1141
1168		const UINT8* srcdata = gfx->get_data(tileno);
	1142	const UINT8* srcdata = gfx(tile_region)->get_data(tileno);
1169	1143	return srcdata[((ypos&((1<<tilesize)-1))*(1<<tilesize))+(xpos&((1<<tilesize)-1))];
1170	1144	}
1171	1145
1172		inline UINT8 sega_segacd_device::get_stampmap_32x32_16x16_tile_info_pixel(running_machine& machine, int xpos, int ypos)
	1146	inline UINT8 sega_segacd_device::get_stampmap_32x32_16x16_tile_info_pixel(int xpos, int ypos)
1173	1147	{
1174	1148	const int tilesize = 5; // 0x1f pixels
1175	1149	const int tilemapsize = 0x7f;
r29505	r29506
1199	1173	int tile_region, tileno;
1200	1174	SCD_GET_TILE_INFO_32x32_16x16(tile_region,tileno,(int)tile_index);
1201	1175
1202		gfx_element *gfx = m_gfxdecode->gfx(tile_region);
1203		tileno %= gfx->elements();
	1176	tileno %= gfx(tile_region)->elements();
1204	1177
1205	1178	if (tileno==0) return 0x00;
1206	1179
1207		const UINT8* srcdata = gfx->get_data(tileno);
	1180	const UINT8* srcdata = gfx(tile_region)->get_data(tileno);
1208	1181	return srcdata[((ypos&((1<<tilesize)-1))*(1<<tilesize))+(xpos&((1<<tilesize)-1))];
1209	1182	}
1210	1183
r29505	r29506
1213	1186	WRITE16_MEMBER( sega_segacd_device::segacd_stopwatch_timer_w )
1214	1187	{
1215	1188	if(data == 0)
1216		stopwatch_timer->reset();
	1189	m_stopwatch_timer->reset();
1217	1190	else
1218	1191	printf("Stopwatch timer %04x\n",data);
1219	1192	}
1220	1193
1221	1194	READ16_MEMBER( sega_segacd_device::segacd_stopwatch_timer_r )
1222	1195	{
1223		INT32 result = (stopwatch_timer->time_elapsed() * ATTOSECONDS_TO_HZ(ATTOSECONDS_IN_USEC(30.72))).as_double();
	1196	INT32 result = (m_stopwatch_timer->time_elapsed() * ATTOSECONDS_TO_HZ(ATTOSECONDS_IN_USEC(30.72))).as_double();
1224	1197
1225	1198	return result & 0xfff;
1226	1199	}
r29505	r29506
1279	1252	{
1280	1253	// is this correct?
1281	1254	if (scd_rammode&1)
1282		return segacd_dataram[offset];
	1255	return m_dataram[offset];
1283	1256	else
1284	1257	{
1285	1258	//printf("Illegal: segacd_sub_dataram_part1_r in mode 0 without permission\n");
r29505	r29506
1322	1295	// is this correct?
1323	1296	if (scd_rammode&1)
1324	1297	{
1325		COMBINE_DATA(&segacd_dataram[offset]);
1326		segacd_mark_tiles_dirty(space.machine(), offset);
	1298	COMBINE_DATA(&m_dataram[offset]);
	1299	segacd_mark_tiles_dirty(offset);
1327	1300	}
1328	1301	else
1329	1302	{
r29505	r29506
1452	1425	// the lower 3 bits of segacd_imagebuffer_hdot_size are set
1453	1426
1454	1427	// this really needs to be doing it's own lookups rather than depending on the inefficient MAME cache..
1455		inline UINT8 sega_segacd_device::read_pixel_from_stampmap( running_machine& machine, bitmap_ind16* srcbitmap, int x, int y)
	1428	inline UINT8 sega_segacd_device::read_pixel_from_stampmap(bitmap_ind16* srcbitmap, int x, int y)
1456	1429	{
1457	1430	/*
1458	1431	if (!srcbitmap)
r29505	r29506
1470	1443
1471	1444	switch (segacd_get_active_stampmap_tilemap()&3)
1472	1445	{
1473		case 0x00: return get_stampmap_16x16_1x1_tile_info_pixel( machine, x, y );
1474		case 0x01: return get_stampmap_32x32_1x1_tile_info_pixel( machine, x, y );
1475		case 0x02: return get_stampmap_16x16_16x16_tile_info_pixel( machine, x, y );
1476		case 0x03: return get_stampmap_32x32_16x16_tile_info_pixel( machine, x, y );
	1446	case 0x00: return get_stampmap_16x16_1x1_tile_info_pixel( x, y );
	1447	case 0x01: return get_stampmap_32x32_1x1_tile_info_pixel( x, y );
	1448	case 0x02: return get_stampmap_16x16_16x16_tile_info_pixel( x, y );
	1449	case 0x03: return get_stampmap_32x32_16x16_tile_info_pixel( x, y );
1477	1450	}
1478	1451
1479	1452	return 0;
r29505	r29506
1504	1477	segacd_conversion_active = 1;
1505	1478
1506	1479	// todo: proper time calculation
1507		segacd_gfx_conversion_timer->adjust(attotime::from_nsec(30000));
	1480	m_stamp_timer->adjust(attotime::from_nsec(30000));
1508	1481
1509	1482
1510	1483
r29505	r29506
1521	1494	INT16 tilemapxoffs,tilemapyoffs;
1522	1495	INT16 deltax,deltay;
1523	1496
1524		tilemapxoffs = segacd_dataram[(currbase+0x0)>>1];
1525		tilemapyoffs = segacd_dataram[(currbase+0x2)>>1];
1526		deltax = segacd_dataram[(currbase+0x4)>>1]; // x-zoom
1527		deltay = segacd_dataram[(currbase+0x6)>>1]; // rotation
	1497	tilemapxoffs = m_dataram[(currbase+0x0)>>1];
	1498	tilemapyoffs = m_dataram[(currbase+0x2)>>1];
	1499	deltax = m_dataram[(currbase+0x4)>>1]; // x-zoom
	1500	deltay = m_dataram[(currbase+0x6)>>1]; // rotation
1528	1501
1529	1502	//printf("%06x:  %04x (%d) %04x (%d) %04x %04x\n", currbase, tilemapxoffs, tilemapxoffs>>3, tilemapyoffs, tilemapyoffs>>3, deltax, deltay);
1530	1503
r29505	r29506
1537	1510	//int i;
1538	1511	UINT8 pix = 0x0;
1539	1512
1540		pix = read_pixel_from_stampmap(space.machine(), srcbitmap, xbase>>(3+8), ybase>>(3+8));
	1513	pix = read_pixel_from_stampmap(srcbitmap, xbase>>(3+8), ybase>>(3+8));
1541	1514
1542	1515	xbase += deltax;
1543	1516	ybase += deltay;
r29505	r29506
1557	1530
1558	1531	offset+=countx & 0x7;
1559	1532
1560		write_pixel( space.machine(), pix, offset );
	1533	write_pixel( pix, offset );
1561	1534
1562		segacd_mark_tiles_dirty(space.machine(), (offset>>3));
1563		segacd_mark_tiles_dirty(space.machine(), (offset>>3)+1);
	1535	segacd_mark_tiles_dirty(offset>>3);
	1536	segacd_mark_tiles_dirty((offset>>3)+1);
1564	1537
1565	1538	}
1566	1539
r29505	r29506
1648	1621
1649	1622	READ16_MEMBER( sega_segacd_device::segacd_irq3timer_r )
1650	1623	{
1651		return segacd_irq3_timer_reg; // always returns value written, not current counter!
	1624	return m_irq3_timer_reg; // always returns value written, not current counter!
1652	1625	}
1653	1626
1654	1627
r29505	r29506
1656	1629	{
1657	1630	if (ACCESSING_BITS_0_7)
1658	1631	{
1659		segacd_irq3_timer_reg = data & 0xff;
	1632	m_irq3_timer_reg = data & 0xff;
1660	1633
1661	1634	// time = reg * 30.72 us
1662	1635
1663		if (segacd_irq3_timer_reg)
1664		segacd_irq3_timer->adjust(SEGACD_IRQ3_TIMER_SPEED);
	1636	if (m_irq3_timer_reg)
	1637	m_irq3_timer->adjust(SEGACD_IRQ3_TIMER_SPEED);
1665	1638	else
1666		segacd_irq3_timer->adjust(attotime::never);
	1639	m_irq3_timer->adjust(attotime::never);
1667	1640
1668		//printf("segacd_irq3timer_w %02x\n", segacd_irq3_timer_reg);
	1641	//printf("segacd_irq3timer_w %02x\n", segacd_m_irq3_timer_reg);
1669	1642	}
1670	1643	}
1671	1644
1672	1645
1673
1674
1675
1676
1677
1678		READ16_MEMBER( sega_segacd_device::segacd_backupram_r )
	1646	READ8_MEMBER( sega_segacd_device::backupram_r )
1679	1647	{
1680		if(ACCESSING_BITS_8_15 && !(space.debugger_access()))
1681		printf("Warning: read to backupram even bytes! [%04x]\n",offset);
1682
1683		return segacd_backupram[offset] & 0xff;
	1648	return m_backupram[offset];
1684	1649	}
1685	1650
1686		WRITE16_MEMBER( sega_segacd_device::segacd_backupram_w )
	1651	WRITE8_MEMBER( sega_segacd_device::backupram_w )
1687	1652	{
1688		if(ACCESSING_BITS_0_7)
1689		segacd_backupram[offset] = data;
1690
1691		if(ACCESSING_BITS_8_15 && !(space.debugger_access()))
1692		printf("Warning: write to backupram even bytes! [%04x] %02x\n",offset,data);
	1653	m_backupram[offset] = data;
1693	1654	}
1694	1655
1695		READ16_MEMBER( sega_segacd_device::segacd_font_color_r )
	1656	READ8_MEMBER( sega_segacd_device::font_color_r )
1696	1657	{
1697		return segacd_font_color;
	1658	return m_font_color;
1698	1659	}
1699	1660
1700		WRITE16_MEMBER( sega_segacd_device::segacd_font_color_w )
	1661	WRITE8_MEMBER( sega_segacd_device::font_color_w )
1701	1662	{
1702		if (ACCESSING_BITS_0_7)
1703		{
1704		segacd_font_color = data & 0xff;
1705		}
	1663	m_font_color = data;
1706	1664	}
1707	1665
1708		READ16_MEMBER( sega_segacd_device::segacd_font_converted_r )
	1666	READ16_MEMBER( sega_segacd_device::font_converted_r )
1709	1667	{
1710		int scbg = (segacd_font_color & 0x0f);
1711		int scfg = (segacd_font_color & 0xf0)>>4;
	1668	int scbg = (m_font_color & 0x0f);
	1669	int scfg = (m_font_color & 0xf0)>>4;
1712	1670	UINT16 retdata = 0;
1713	1671	int bit;
1714	1672
1715	1673	for (bit=0;bit<4;bit++)
1716	1674	{
1717		if (*segacd_font_bits&((0x1000>>offset*4)<<bit))
	1675	if (*m_font_bits&((0x1000>>offset*4)<<bit))
1718	1676	retdata |= scfg << (bit*4);
1719	1677	else
1720	1678	retdata |= scbg << (bit*4);
r29505	r29506
1729	1687
1730	1688	void sega_segacd_device::device_start()
1731	1689	{
1732		if (!m_gfxdecode->started())
1733		throw device_missing_dependencies();
1734
1735		segacd_gfx_conversion_timer = machine().device<timer_device>(":segacd:stamp_timer");
1736		segacd_irq3_timer = machine().device<timer_device>(":segacd:irq3_timer");
1737		scd_dma_timer = machine().device<timer_device>(":segacd:scd_dma_timer");
1738
1739	1690	address_space& space = machine().device("maincpu")->memory().space(AS_PROGRAM);
1740	1691
1741		segacd_font_bits = reinterpret_cast<UINT16 *>(memshare(":segacd:segacd_font")->ptr());
1742		segacd_backupram = reinterpret_cast<UINT16 *>(memshare(":segacd:backupram")->ptr());
1743		segacd_dataram = reinterpret_cast<UINT16 *>(memshare(":segacd:dataram")->ptr());
1744		//  segacd_dataram2 = reinterpret_cast<UINT16 *>(memshare(":segacd:dataram2")->ptr());
1745		segacd_4meg_prgram = reinterpret_cast<UINT16 *>(memshare(":segacd:segacd_program")->ptr());
	1692	m_backupram.resize(0x2000);
	1693	subdevice<nvram_device>("backupram")->set_base(m_backupram, 0x2000);
1746	1694
1747	1695	segacd_4meg_prgbank = 0;
1748	1696
1749
1750	1697	space.unmap_readwrite        (0x020000,0x3fffff);
1751	1698
1752
1753	1699	space.install_read_handler (0x0020000, 0x003ffff, read16_delegate(FUNC(sega_segacd_device::scd_4m_prgbank_ram_r),this) );
1754	1700	space.install_write_handler (0x0020000, 0x003ffff, write16_delegate(FUNC(sega_segacd_device::scd_4m_prgbank_ram_w),this) );
1755	1701
r29505	r29506
1775	1721
1776	1722	space.install_read_handler (0x0000070, 0x0000073, read16_delegate(FUNC(sega_segacd_device::scd_hint_vector_r),this) );
1777	1723
1778		/* create the char set (gfx will then be updated dynamically from RAM) */
1779		for (int i = 0; i < 16; i++)
1780		m_gfxdecode->gfx(i)->set_source((UINT8 *)segacd_dataram);
	1724	segacd_stampmap[0] = &machine().tilemap().create(*this, tilemap_get_info_delegate(FUNC(sega_segacd_device::get_stampmap_16x16_1x1_tile_info),this), TILEMAP_SCAN_ROWS, 16, 16, 16, 16);
	1725	segacd_stampmap[1] = &machine().tilemap().create(*this, tilemap_get_info_delegate(FUNC(sega_segacd_device::get_stampmap_32x32_1x1_tile_info),this), TILEMAP_SCAN_ROWS, 32, 32, 8, 8);
	1726	segacd_stampmap[2] = &machine().tilemap().create(*this, tilemap_get_info_delegate(FUNC(sega_segacd_device::get_stampmap_16x16_16x16_tile_info),this), TILEMAP_SCAN_ROWS, 16, 16, 256, 256); // 128kb!
	1727	segacd_stampmap[3] = &machine().tilemap().create(*this, tilemap_get_info_delegate(FUNC(sega_segacd_device::get_stampmap_32x32_16x16_tile_info),this), TILEMAP_SCAN_ROWS, 32, 32, 128, 128); // 32kb!
1781	1728
1782		segacd_stampmap[0] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(sega_segacd_device::get_stampmap_16x16_1x1_tile_info),this), TILEMAP_SCAN_ROWS, 16, 16, 16, 16);
1783		segacd_stampmap[1] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(sega_segacd_device::get_stampmap_32x32_1x1_tile_info),this), TILEMAP_SCAN_ROWS, 32, 32, 8, 8);
1784		segacd_stampmap[2] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(sega_segacd_device::get_stampmap_16x16_16x16_tile_info),this), TILEMAP_SCAN_ROWS, 16, 16, 256, 256); // 128kb!
1785		segacd_stampmap[3] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(sega_segacd_device::get_stampmap_32x32_16x16_tile_info),this), TILEMAP_SCAN_ROWS, 32, 32, 128, 128); // 32kb!
1786
1787	1729	// todo register save state stuff
1788	1730	}
1789	1731
r29505	r29506
1809	1751	scd_rammode = 0;
1810	1752	scd_mode_dmna_ret_flags = 0x5421;
1811	1753
1812		lc89510_temp = machine().device<lc89510_temp_device>(":segacd:tempcdc");
1813		lc89510_temp->reset_cd();
	1754	m_lc89510_temp->reset_cd();
1814	1755	m_dmaaddr = 0;
1815		scd_dma_timer->adjust(attotime::zero);
	1756	m_dma_timer->adjust(attotime::zero);
1816	1757
1817		stopwatch_timer = machine().device<timer_device>(":segacd:sw_timer");
1818
1819	1758	m_total_scanlines = 262;
1820	1759
1821	1760	// HACK!!!! timegal, anettfut, roadaven end up with the SubCPU waiting in a loop for *something*
r29505	r29506
1848	1787	segacd_redled = 0;
1849	1788	segacd_greenled = 0;
1850	1789	segacd_ready = 1; // actually set 100ms after startup?
1851		segacd_irq3_timer_reg = 0;
	1790	m_irq3_timer_reg = 0;
1852	1791
1853		segacd_gfx_conversion_timer->adjust(attotime::never);
1854		segacd_irq3_timer->adjust(attotime::never);
	1792	m_stamp_timer->adjust(attotime::never);
	1793	m_irq3_timer->adjust(attotime::never);
1855	1794
1856	1795	}
1857	1796
1858	1797
1859	1798	// todo: tidy up
1860		TIMER_DEVICE_CALLBACK_MEMBER( sega_segacd_device::scd_dma_timer_callback )
	1799	TIMER_DEVICE_CALLBACK_MEMBER( sega_segacd_device::dma_timer_callback )
1861	1800	{
1862	1801	// todo: accurate timing of this!
1863	1802
1864	1803	#define RATE 256
1865		lc89510_temp->CDC_Do_DMA(machine(), RATE);
	1804	m_lc89510_temp->CDC_Do_DMA(machine(), RATE);
1866	1805
1867	1806	// timed reset of flags
1868	1807	scd_mode_dmna_ret_flags |= 0x0021;
1869	1808
1870		scd_dma_timer->adjust(attotime::from_hz(m_framerate) / m_total_scanlines);
	1809	m_dma_timer->adjust(attotime::from_hz(m_framerate) / m_total_scanlines);
1871	1810
1872	1811	}
1873	1812
r29505	r29506
1875	1814	void sega_segacd_device::SegaCD_CDC_Do_DMA(int &dmacount, UINT8 *CDC_BUFFER, UINT16 &dma_addrc, UINT16 &destination )
1876	1815	{
1877	1816	int length = dmacount;
1878		UINT8 *dest;
	1817	UINT16 *dest;
1879	1818	int srcoffset = 0;
1880	1819	int dstoffset = 0;
1881	1820	address_space& space = m_scdcpu->space(AS_PROGRAM);
r29505	r29506
1899	1838
1900	1839	if (destination==DMA_PRG)
1901	1840	{
1902		dest = (UINT8 *) segacd_4meg_prgram;
	1841	dest = m_prgram;
1903	1842	}
1904	1843	else if (destination==DMA_WRAM)
1905	1844	{
1906		dest = (UINT8*)segacd_dataram;
	1845	dest = m_dataram;
1907	1846	}
1908	1847	else if (destination==DMA_PCM)
1909	1848	{
r29505	r29506
1916	1855
1917	1856	if (PCM_DMA)
1918	1857	{
1919		space.write_byte(0xff2000+(((dstoffset*2)+1)&0x1fff),data >> 8);
1920		space.write_byte(0xff2000+(((dstoffset*2)+3)&0x1fff),data & 0xff);
	1858	m_rfsnd->rf5c68_mem_w(space, dstoffset & 0xfff, data >> 8);
	1859	m_rfsnd->rf5c68_mem_w(space, (dstoffset+1) & 0xfff, data);
1921	1860	//  printf("PCM_DMA writing %04x %04x\n",0xff2000+(dstoffset*2), data);
1922	1861	}
1923	1862	else
r29505	r29506
1930	1869	{
1931	1870	dstoffset &= 0x3ffff;
1932	1871
1933		dest[dstoffset+1] = data >>8;
1934		dest[dstoffset+0] = data&0xff;
	1872	dest[dstoffset/2] = data;
1935	1873
1936		segacd_mark_tiles_dirty(space.machine(), dstoffset/2);
	1874	segacd_mark_tiles_dirty(dstoffset/2);
1937	1875	}
1938	1876	else
1939	1877	{
r29505	r29506
1953	1891	else
1954	1892	{
1955	1893	// main ram
1956		dest[dstoffset+1] = data >>8;
1957		dest[dstoffset+0] = data&0xff;
	1894	dest[dstoffset/2] = data;
1958	1895	}
1959	1896
1960	1897	}

branches/new_menus/src/mess/machine/megacd.h

r29505	r29506
3	3	#include "cpu/m68000/m68000.h"
4	4	#include "machine/lc89510.h"
5	5	#include "machine/megacdcd.h"
	6	#include "sound/rf5c68.h"
6	7
7	8	#define SEGACD_CLOCK      12500000
8	9
r29505	r29506
15	16
16	17	// irq3 timer
17	18	#define CHECK_SCD_LV3_INTERRUPT \
18		if (lc89510_temp->get_segacd_irq_mask() & 0x08) \
	19	if (m_lc89510_temp->get_segacd_irq_mask() & 0x08) \
19	20	{ \
20	21	m_scdcpu->set_input_line(3, HOLD_LINE); \
21	22	}
22	23	// from master
23	24	#define CHECK_SCD_LV2_INTERRUPT \
24		if (lc89510_temp->get_segacd_irq_mask() & 0x04) \
	25	if (m_lc89510_temp->get_segacd_irq_mask() & 0x04) \
25	26	{ \
26	27	m_scdcpu->set_input_line(2, HOLD_LINE); \
27	28	}
28	29
29	30	// gfx convert
30	31	#define CHECK_SCD_LV1_INTERRUPT \
31		if (lc89510_temp->get_segacd_irq_mask() & 0x02) \
	32	if (m_lc89510_temp->get_segacd_irq_mask() & 0x02) \
32	33	{ \
33	34	m_scdcpu->set_input_line(1, HOLD_LINE); \
34	35	}
35	36
36		#define SEGACD_IRQ3_TIMER_SPEED (attotime::from_nsec(segacd_irq3_timer_reg*30720))
	37	#define SEGACD_IRQ3_TIMER_SPEED (attotime::from_nsec(m_irq3_timer_reg*30720))
37	38
38	39
39		class sega_segacd_device : public device_t
	40	class sega_segacd_device : public device_t, public device_gfx_interface
40	41	{
41	42	public:
42	43	sega_segacd_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
43	44
44	45	required_device<cpu_device> m_scdcpu;
45		lc89510_temp_device *lc89510_temp;
	46	required_device<rf5c68_device> m_rfsnd;
	47	required_device<lc89510_temp_device> m_lc89510_temp;
	48	required_device<timer_device> m_stopwatch_timer;
	49	required_device<timer_device> m_stamp_timer;
	50	required_device<timer_device> m_irq3_timer;
	51	required_device<timer_device> m_dma_timer;
	52	//required_device<timer_device> m_hock_timer;
46	53
47		UINT16 *segacd_backupram;
48		timer_device *stopwatch_timer;
49		UINT8 segacd_font_color;
50		UINT16* segacd_font_bits;
	54	required_shared_ptr<UINT16> m_prgram;
	55	required_shared_ptr<UINT16> m_dataram;
	56	required_shared_ptr<UINT16> m_font_bits;
	57
	58	// can't use a memshare because it's 8-bit RAM in a 16-bit address space
	59	dynamic_array<UINT8> m_backupram;
	60
	61	UINT8 m_font_color;
	62
51	63	UINT16 scd_rammode;
52	64	UINT32 scd_mode_dmna_ret_flags ;
53	65
54		timer_device *segacd_gfx_conversion_timer;
55		timer_device *segacd_irq3_timer;
56		//timer_device *segacd_hock_timer;
57
58		UINT16* segacd_4meg_prgram;  // pointer to SubCPU PrgRAM
59		UINT16* segacd_dataram;
60		UINT16* segacd_dataram2;
61	66	tilemap_t    *segacd_stampmap[4];
62	67
63	68
r29505	r29506
84	89	int segacd_redled;// = 0;
85	90	int segacd_greenled;// = 0;
86	91	int segacd_ready;// = 1; // actually set 100ms after startup?
87		UINT16 segacd_irq3_timer_reg;
	92	UINT8 m_irq3_timer_reg;
88	93
89	94
90		TIMER_DEVICE_CALLBACK_MEMBER( segacd_irq3_timer_callback );
91		TIMER_DEVICE_CALLBACK_MEMBER( segacd_gfx_conversion_timer_callback );
	95	TIMER_DEVICE_CALLBACK_MEMBER( irq3_timer_callback );
	96	TIMER_DEVICE_CALLBACK_MEMBER( stamp_timer_callback );
92	97
93	98	UINT16 handle_segacd_sub_int_callback(int irqline);
94	99
95		inline void write_pixel(running_machine& machine, UINT8 pix, int pixeloffset );
	100	inline void write_pixel(UINT8 pix, int pixeloffset);
96	101	UINT16 segacd_1meg_mode_word_read(int offset, UINT16 mem_mask);
97	102	void segacd_1meg_mode_word_write(int offset, UINT16 data, UINT16 mem_mask, int use_pm);
98	103
r29505	r29506
106	111	int m_base_total_scanlines;
107	112	int m_total_scanlines;
108	113
109		void segacd_mark_tiles_dirty(running_machine& machine, int offset);
	114	void segacd_mark_tiles_dirty(int offset);
110	115	int segacd_get_active_stampmap_tilemap(void);
111	116
112	117	// set some variables at start, depending on region (shall be moved to a device interface?)
r29505	r29506
124	129	TILE_GET_INFO_MEMBER( get_stampmap_16x16_16x16_tile_info );
125	130	TILE_GET_INFO_MEMBER( get_stampmap_32x32_16x16_tile_info );
126	131
127		UINT8 get_stampmap_16x16_1x1_tile_info_pixel(running_machine& machine, int xpos, int ypos);
128		UINT8 get_stampmap_32x32_1x1_tile_info_pixel(running_machine& machine, int xpos, int ypos);
129		UINT8 get_stampmap_16x16_16x16_tile_info_pixel(running_machine& machine, int xpos, int ypos);
130		UINT8 get_stampmap_32x32_16x16_tile_info_pixel(running_machine& machine, int xpos, int ypos);
	132	UINT8 get_stampmap_16x16_1x1_tile_info_pixel(int xpos, int ypos);
	133	UINT8 get_stampmap_32x32_1x1_tile_info_pixel(int xpos, int ypos);
	134	UINT8 get_stampmap_16x16_16x16_tile_info_pixel(int xpos, int ypos);
	135	UINT8 get_stampmap_32x32_16x16_tile_info_pixel(int xpos, int ypos);
131	136
132	137	WRITE16_MEMBER( scd_a12000_halt_reset_w );
133	138	READ16_MEMBER( scd_a12000_halt_reset_r );
r29505	r29506
177	182	READ16_MEMBER( segacd_stampsize_r );
178	183	WRITE16_MEMBER( segacd_stampsize_w );
179	184
180		UINT8 read_pixel_from_stampmap( running_machine& machine, bitmap_ind16* srcbitmap, int x, int y);
	185	UINT8 read_pixel_from_stampmap(bitmap_ind16* srcbitmap, int x, int y);
181	186
182	187	WRITE16_MEMBER( segacd_trace_vector_base_address_w );
183	188	READ16_MEMBER( segacd_imagebuffer_vdot_size_r );
r29505	r29506
194	199	WRITE16_MEMBER( segacd_imagebuffer_hdot_size_w );
195	200	READ16_MEMBER( segacd_irq3timer_r );
196	201	WRITE16_MEMBER( segacd_irq3timer_w );
197		READ16_MEMBER( segacd_backupram_r );
198		WRITE16_MEMBER( segacd_backupram_w );
199		READ16_MEMBER( segacd_font_color_r );
200		WRITE16_MEMBER( segacd_font_color_w );
201		READ16_MEMBER( segacd_font_converted_r );
202		TIMER_DEVICE_CALLBACK_MEMBER( scd_dma_timer_callback );
	202	READ8_MEMBER( backupram_r );
	203	WRITE8_MEMBER( backupram_w );
	204	READ8_MEMBER( font_color_r );
	205	WRITE8_MEMBER( font_color_w );
	206	READ16_MEMBER( font_converted_r );
	207	TIMER_DEVICE_CALLBACK_MEMBER( dma_timer_callback );
203	208	IRQ_CALLBACK_MEMBER(segacd_sub_int_callback);
204	209
205	210	void SegaCD_CDC_Do_DMA( int &dmacount, UINT8 *CDC_BUFFER, UINT16 &dma_addrc, UINT16 &destination );
206		timer_device* scd_dma_timer;
207		required_device<gfxdecode_device> m_gfxdecode;
208	211
209	212	protected:
210	213	virtual void device_start();

branches/new_menus/src/mess/machine/upd65031.c

r29505	r29506
204	204
205	205
206	206	//-------------------------------------------------
207		//  device_config_complete - perform any
208		//  operations now that the configuration is
209		//  complete
210		//-------------------------------------------------
211
212		void upd65031_device::device_config_complete()
213		{
214		// inherit a copy of the static data
215		const upd65031_interface *intf = reinterpret_cast<const upd65031_interface *>(static_config());
216		if (intf != NULL)
217		{
218		*static_cast<upd65031_interface *>(this) = *intf;
219		}
220		// or initialize to defaults if none provided
221		else
222		{
223		m_screen_update_cb = NULL;
224		m_out_mem_cb = NULL;
225		}
226		}
227
228
229		//-------------------------------------------------
230	207	//  device_start - device-specific startup
231	208	//-------------------------------------------------
232	209
r29505	r29506
238	215	m_write_nmi.resolve_safe();
239	216	m_write_spkr.resolve_safe();
240	217
	218	// bind delegates
	219	m_screen_update_cb.bind_relative_to(*owner());
	220	m_out_mem_cb.bind_relative_to(*owner());
	221
241	222	// allocate timers
242	223	m_rtc_timer = timer_alloc(TIMER_RTC);
243	224	m_flash_timer = timer_alloc(TIMER_FLASH);
r29505	r29506
282	263	m_mode = 0;
283	264	set_mode(STATE_AWAKE);
284	265
285		if (m_out_mem_cb)
	266	if (!m_out_mem_cb.isnull())
286	267	{
287	268	// reset bankswitch
288		(m_out_mem_cb)(*this, 0, 0, 0);
289		(m_out_mem_cb)(*this, 1, 0, 0);
290		(m_out_mem_cb)(*this, 2, 0, 0);
291		(m_out_mem_cb)(*this, 3, 0, 0);
	269	m_out_mem_cb(0, 0, 0);
	270	m_out_mem_cb(1, 0, 0);
	271	m_out_mem_cb(2, 0, 0);
	272	m_out_mem_cb(3, 0, 0);
292	273	}
293	274	}
294	275
r29505	r29506
405	386
406	387	UINT32 upd65031_device::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
407	388	{
408		if (m_screen_update_cb && (m_com & COM_LCDON))
409		(m_screen_update_cb)(*this, bitmap, m_lcd_regs[4], m_lcd_regs[2], m_lcd_regs[3], m_lcd_regs[0], m_lcd_regs[1], m_flash);
	389	if (!m_screen_update_cb.isnull() && (m_com & COM_LCDON))
	390	m_screen_update_cb(bitmap, m_lcd_regs[4], m_lcd_regs[2], m_lcd_regs[3], m_lcd_regs[0], m_lcd_regs[1], m_flash);
410	391	else
411	392	bitmap.fill(0, cliprect);
412	393
r29505	r29506
528	509	}
529	510
530	511	// bit 2 controls the lower 8kb of memory
531		if (BIT(m_com^data, 2) && m_out_mem_cb)
532		(m_out_mem_cb)(*this, 0, m_sr[0], BIT(data, 2));
	512	if (BIT(m_com^data, 2) && !m_out_mem_cb.isnull())
	513	m_out_mem_cb(0, m_sr[0], BIT(data, 2));
533	514
534	515	m_com = data;
535	516	break;
r29505	r29506
582	563	case REG_SR1:
583	564	case REG_SR2:
584	565	case REG_SR3:
585		if (m_out_mem_cb && m_sr[port & 3] != data)
586		(m_out_mem_cb)(*this, port & 3, data, BIT(m_com, 2));
	566	if (!m_out_mem_cb.isnull() && m_sr[port & 3] != data)
	567	m_out_mem_cb(port & 3, data, BIT(m_com, 2));
587	568
588	569	m_sr[port & 3] = data;
589	570	break;

branches/new_menus/src/mess/machine/upd65031.h

r29505	r29506
17	17	//  INTERFACE CONFIGURATION MACROS
18	18	//**************************************************************************
19	19
20		#define MCFG_UPD65031_ADD(_tag, _clock, _config) \
21		MCFG_DEVICE_ADD((_tag), UPD65031, _clock)   \
22		MCFG_DEVICE_CONFIG(_config)
23
24		#define UPD65031_INTERFACE(name) \
25		const upd65031_interface (name) =
26
27	20	#define MCFG_UPD65031_KB_CALLBACK(_read) \
28	21	devcb = &upd65031_device::set_kb_rd_callback(*device, DEVCB2_##_read);
29	22
r29505	r29506
36	29	#define MCFG_UPD65031_SPKR_CALLBACK(_write) \
37	30	devcb = &upd65031_device::set_spkr_wr_callback(*device, DEVCB2_##_write);
38	31
	32	#define MCFG_UPD65031_SCR_UPDATE_CB(_class, _method) \
	33	upd65031_device::set_screen_update_callback(*device, upd65031_screen_update_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
39	34
	35	#define MCFG_UPD65031_MEM_UPDATE_CB(_class, _method) \
	36	upd65031_device::set_memory_update_callback(*device, upd65031_memory_update_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
	37
	38
40	39	//**************************************************************************
41	40	//  TYPE DEFINITIONS
42	41	//**************************************************************************
43	42
44		typedef void (*upd65031_screen_update_func)(device_t &device, bitmap_ind16 &bitmap, UINT16 sbf, UINT16 hires0, UINT16 hires1, UINT16 lores0, UINT16 lores1, int flash);
45		#define UPD65031_SCREEN_UPDATE(name) void name(device_t &device, bitmap_ind16 &bitmap, UINT16 sbf, UINT16 hires0, UINT16 hires1, UINT16 lores0, UINT16 lores1, int flash)
	43	typedef device_delegate<void (bitmap_ind16 &bitmap, UINT16 sbf, UINT16 hires0, UINT16 hires1, UINT16 lores0, UINT16 lores1, int flash)> upd65031_screen_update_delegate;
	44	typedef device_delegate<void (int bank, UINT16 page, int rams)> upd65031_memory_update_delegate;
46	45
47		typedef void (*upd65031_memory_update_func)(device_t &device, int bank, UINT16 page, int rams);
48		#define UPD65031_MEMORY_UPDATE(name) void name(device_t &device, int bank, UINT16 page, int rams)
	46	#define UPD65031_SCREEN_UPDATE(_name) void _name(bitmap_ind16 &bitmap, UINT16 sbf, UINT16 hires0, UINT16 hires1, UINT16 lores0, UINT16 lores1, int flash)
	47	#define UPD65031_MEMORY_UPDATE(_name) void _name(int bank, UINT16 page, int rams)
49	48
50	49
51		// ======================> upd65031_interface
52
53		struct upd65031_interface
54		{
55		upd65031_screen_update_func m_screen_update_cb;  // callback for update the LCD
56		upd65031_memory_update_func m_out_mem_cb;        // callback for update bankswitch
57		};
58
59
60	50	// ======================> upd65031_device
61	51
62		class upd65031_device : public device_t,
63		public upd65031_interface
	52	class upd65031_device : public device_t
64	53	{
65	54	public:
66	55	// construction/destruction
r29505	r29506
71	60	template<class _Object> static devcb2_base &set_nmi_wr_callback(device_t &device, _Object object) { return downcast<upd65031_device &>(device).m_write_nmi.set_callback(object); }
72	61	template<class _Object> static devcb2_base &set_spkr_wr_callback(device_t &device, _Object object) { return downcast<upd65031_device &>(device).m_write_spkr.set_callback(object); }
73	62
	63	static void set_screen_update_callback(device_t &device, upd65031_screen_update_delegate callback) { downcast<upd65031_device &>(device).m_screen_update_cb = callback; }
	64	static void set_memory_update_callback(device_t &device, upd65031_memory_update_delegate callback) { downcast<upd65031_device &>(device).m_out_mem_cb = callback; }
	65
74	66	DECLARE_READ8_MEMBER( read );
75	67	DECLARE_WRITE8_MEMBER( write );
76	68	DECLARE_WRITE_LINE_MEMBER( flp_w );
r29505	r29506
79	71
80	72	protected:
81	73	// device-level overrides
82		virtual void device_config_complete();
83	74	virtual void device_start();
84	75	virtual void device_reset();
85	76	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
r29505	r29506
97	88	devcb2_write_line   m_write_nmi;
98	89	devcb2_write_line   m_write_spkr;
99	90
	91	upd65031_screen_update_delegate m_screen_update_cb;  // callback for update the LCD
	92	upd65031_memory_update_delegate m_out_mem_cb;        // callback for update bankswitch
	93
100	94	int     m_mode;
101	95	UINT16  m_lcd_regs[5];      // LCD registers
102	96	UINT8   m_tim[5];           // RTC registers

branches/new_menus/src/mess/includes/z88.h

r29505	r29506
58	58
59	59	virtual void machine_start();
60	60	virtual void machine_reset();
61		void bankswitch_update(int bank, UINT16 page, int rams);
62	61	DECLARE_READ8_MEMBER(kb_r);
	62	UPD65031_MEMORY_UPDATE(bankswitch_update);
	63	UPD65031_SCREEN_UPDATE(lcd_update);
63	64
64	65	// cartridges read/write
65	66	DECLARE_READ8_MEMBER(bank0_cart_r);
r29505	r29506
77	78	void vh_render_8x8(bitmap_ind16 &bitmap, int x, int y, UINT16 pen0, UINT16 pen1, UINT8 *gfx);
78	79	void vh_render_6x8(bitmap_ind16 &bitmap, int x, int y, UINT16 pen0, UINT16 pen1, UINT8 *gfx);
79	80	void vh_render_line(bitmap_ind16 &bitmap, int x, int y, UINT16 pen);
80		void lcd_update(bitmap_ind16 &bitmap, UINT16 sbf, UINT16 hires0, UINT16 hires1, UINT16 lores0, UINT16 lores1, int flash);
81	81
82	82	struct
83	83	{

branches/new_menus/src/mess/includes/tandy2k.h

r29505	r29506
76	76	m_pb_sel(0),
77	77	m_vram_base(0),
78	78	m_vidouts(0),
79		m_clkspd(0),
80		m_clkcnt(0),
	79	m_clkspd(-1),
	80	m_clkcnt(-1),
81	81	m_blc(0),
82	82	m_bkc(0),
83	83	m_cblank(0),

branches/new_menus/src/mess/includes/x68k.h

r29505	r29506
15	15	#include "machine/upd765.h"
16	16	#include "sound/okim6258.h"
17	17	#include "machine/ram.h"
	18	#include "machine/8530scc.h"
	19	#include "sound/2151intf.h"
	20	#include "machine/i8255.h"
18	21
19	22	#define MC68901_TAG     "mc68901"
20	23	#define RP5C15_TAG      "rp5c15"
r29505	r29506
40	43	TIMER_X68K_CRTC_RASTER_IRQ,
41	44	TIMER_X68K_CRTC_VBLANK_IRQ,
42	45	TIMER_X68K_FDC_TC,
	46	TIMER_X68K_ADPCM
43	47	};
44	48
45	49	x68k_state(const machine_config &mconfig, device_type type, const char *tag)
r29505	r29506
52	56	m_palette(*this, "palette"),
53	57	m_mfpdev(*this, MC68901_TAG),
54	58	m_rtc(*this, RP5C15_TAG),
	59	m_scc(*this, "scc"),
	60	m_ym2151(*this, "ym2151"),
	61	m_ppi(*this, "ppi8255"),
55	62	m_nvram16(*this, "nvram16"),
56	63	m_nvram32(*this, "nvram32"),
57	64	m_gvram16(*this, "gvram16"),
58	65	m_tvram16(*this, "tvram16"),
59	66	m_gvram32(*this, "gvram32"),
60		m_tvram32(*this, "tvram32") { }
	67	m_tvram32(*this, "tvram32"),
	68	m_options(*this, "options"),
	69	m_mouse1(*this, "mouse1"),
	70	m_mouse2(*this, "mouse2"),
	71	m_mouse3(*this, "mouse3"),
	72	m_xpd1lr(*this, "xpd1lr"),
	73	m_ctrltype(*this, "ctrltype"),
	74	m_joy1(*this, "joy1"),
	75	m_joy2(*this, "joy2"),
	76	m_md3b(*this, "md3b"),
	77	m_md6b(*this, "md6b"),
	78	m_md6b_extra(*this, "md6b_extra")
	79	{ }
61	80
62	81	required_device<m68000_base_device> m_maincpu;
63	82	required_device<okim6258_device> m_okim6258;
r29505	r29506
67	86	required_device<palette_device> m_palette;
68	87	required_device<mc68901_device> m_mfpdev;
69	88	required_device<rp5c15_device> m_rtc;
	89	required_device<scc8530_t> m_scc;
	90	required_device<ym2151_device> m_ym2151;
	91	required_device<i8255_device> m_ppi;
70	92
71	93	optional_shared_ptr<UINT16> m_nvram16;
72	94	optional_shared_ptr<UINT32> m_nvram32;
r29505	r29506
75	97	optional_shared_ptr<UINT16> m_tvram16;
76	98	optional_shared_ptr<UINT32> m_gvram32;
77	99	optional_shared_ptr<UINT32> m_tvram32;
	100
	101	required_ioport m_options;
	102	required_ioport m_mouse1;
	103	required_ioport m_mouse2;
	104	required_ioport m_mouse3;
	105	required_ioport m_xpd1lr;
	106	required_ioport m_ctrltype;
	107	required_ioport m_joy1;
	108	required_ioport m_joy2;
	109	required_ioport m_md3b;
	110	required_ioport m_md6b;
	111	required_ioport m_md6b_extra;
78	112
79	113	DECLARE_WRITE_LINE_MEMBER( mfp_tbo_w );
80	114
r29505	r29506
100	134	int eject[4];
101	135	int motor[4];
102	136	int selected_drive;
103		int drq_state;
104	137	} m_fdc;
105	138	struct
106	139	{
r29505	r29506
203	236	emu_timer* m_raster_irq;
204	237	emu_timer* m_vblank_irq;
205	238	emu_timer* m_fdc_tc;
	239	emu_timer* m_adpcm_timer;
206	240	UINT16* m_spriteram;
207	241	UINT16* m_spritereg;
208	242	tilemap_t* m_bg0_8;
r29505	r29506
241	275	DECLARE_READ8_MEMBER(ppi_port_c_r);
242	276	DECLARE_WRITE8_MEMBER(ppi_port_c_w);
243	277	DECLARE_WRITE_LINE_MEMBER(fdc_irq);
244		DECLARE_WRITE_LINE_MEMBER(fdc_drq);
245	278	DECLARE_WRITE8_MEMBER(x68k_ct_w);
246	279	DECLARE_WRITE_LINE_MEMBER(x68k_rtc_alarm_irq);
247	280	DECLARE_WRITE8_MEMBER(x68030_adpcm_w);

branches/new_menus/src/mess/includes/sms.h

r29505	r29506
200	200
201	201	DECLARE_READ8_MEMBER(sms_store_cart_select_r);
202	202	DECLARE_WRITE8_MEMBER(sms_store_cart_select_w);
203		DECLARE_READ8_MEMBER(sms_store_select1);
204		DECLARE_READ8_MEMBER(sms_store_select2);
205		DECLARE_READ8_MEMBER(sms_store_control_r);
206	203	DECLARE_WRITE8_MEMBER(sms_store_control_w);
207	204	DECLARE_DRIVER_INIT(smssdisp);
208	205

branches/new_menus/src/mess/video/crt.c

r29505	r29506
25	25	Based on earlier work by Chris Salomon
26	26	*/
27	27
28		#include <math.h>
29	28	#include "emu.h"
30	29	#include "video/crt.h"
31	30
r29505	r29506
68	67
69	68	void crt_device::device_start()
70	69	{
71		const crt_interface *intf = (const crt_interface *)static_config();
72		int width = intf->width;
73		int height = intf->height;
74		int i;
75
76		m_num_intensity_levels = intf->num_levels;
77		m_window_offset_x = intf->offset_x;
78		m_window_offset_y = intf->offset_y;
79		m_window_width = width;
80		m_window_height = height;
81
82	70	/* alloc the arrays */
83		m_list = auto_alloc_array(machine(), crt_point, width * height);
	71	m_list = auto_alloc_array(machine(), crt_point, m_window_width * m_window_height);
	72	m_list_head = auto_alloc_array(machine(), int, m_window_height);
84	73
85		m_list_head = auto_alloc_array(machine(), int, height);
86
87	74	/* fill with black and set up list as empty */
88		for (i=0; i<(width * height); i++)
89		{
	75	for (int i = 0; i < (m_window_width * m_window_height); i++)
90	76	m_list[i].intensity = intensity_pixel_not_in_list;
91		}
92	77
93		for (i=0; i<height; i++)
	78	for (int i = 0; i < m_window_height; i++)
94	79	m_list_head[i] = -1;
95	80
96	81	m_decay_counter = 0;

branches/new_menus/src/mess/video/crt.h

r29505	r29506
6	6
7	7	*************************************************************************/
8	8
9		#ifndef CRT_H_
10		#define CRT_H_
	9	#ifndef __CRT_H__
	10	#define __CRT_H__
11	11
12	12
13	13	//**************************************************************************
14	14	//  INTERFACE CONFIGURATION MACROS
15	15	//**************************************************************************
16	16
17		#define MCFG_CRT_ADD(_tag, _interface) \
18		MCFG_DEVICE_ADD(_tag, CRT, 0) \
19		MCFG_DEVICE_CONFIG(_interface)
	17	#define MCFG_CRT_NUM_LEVELS(_lev) \
	18	crt_device::set_num_levels(*device, _lev);
20	19
	20	#define MCFG_CRT_OFFSETS(_xoffs, _yoffs) \
	21	crt_device::set_offsets(*device, _xoffs, _yoffs);
21	22
	23	#define MCFG_CRT_SIZE(_width, _height) \
	24	crt_device::set_size(*device, _width, _height);
	25
	26
22	27	//**************************************************************************
23	28	//  TYPE DEFINITIONS
24	29	//**************************************************************************
25	30
26		struct crt_interface
27		{
28		int num_levels;
29		int offset_x, offset_y;
30		int width, height;
31		};
32
33
34	31	struct crt_point
35	32	{
36	33	crt_point() :
r29505	r29506
50	47	crt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
51	48	~crt_device() { }
52	49
	50	static void set_num_levels(device_t &device, int levels) { downcast<crt_device &>(device).m_num_intensity_levels = levels; }
	51	static void set_offsets(device_t &device, int x_offset, int y_offset)
	52	{
	53	crt_device &dev = downcast<crt_device &>(device);
	54	dev.m_window_offset_x = x_offset;
	55	dev.m_window_offset_y = y_offset;
	56	}
	57	static void set_size(device_t &device, int width, int height)
	58	{
	59	crt_device &dev = downcast<crt_device &>(device);
	60	dev.m_window_width = width;
	61	dev.m_window_height = height;
	62	}
	63
	64	void plot(int x, int y);
	65	void eof();
	66	void update(bitmap_ind16 &bitmap);
	67
53	68	protected:
54	69	// device-level overrides
55	70	virtual void device_start();
56	71
57		public:
58		void plot(int x, int y);
59		void eof();
60		void update(bitmap_ind16 &bitmap);
61
62	72	private:
63	73	crt_point *m_list; /* array of (crt_window_width*crt_window_height) point */
64	74	int *m_list_head;  /* head of the list of lit pixels (index in the array) */

branches/new_menus/src/mess/video/vtvideo.c

r29505	r29506
49	49	device_video_interface(mconfig, *this),
50	50	m_read_ram(*this),
51	51	m_write_clear_video_interrupt(*this),
	52	m_char_rom_tag(""),
52	53	m_palette(*this, "palette")
53	54	{
54	55	}
r29505	r29506
59	60	device_video_interface(mconfig, *this),
60	61	m_read_ram(*this),
61	62	m_write_clear_video_interrupt(*this),
	63	m_char_rom_tag(""),
62	64	m_palette(*this, "palette")
63	65	{
64	66	}
r29505	r29506
71	73
72	74
73	75	//-------------------------------------------------
74		//  device_config_complete - perform any
75		//  operations now that the configuration is
76		//  complete
77		//-------------------------------------------------
78
79		void vt100_video_device::device_config_complete()
80		{
81		// inherit a copy of the static data
82		const vt_video_interface *intf = reinterpret_cast<const vt_video_interface *>(static_config());
83		if (intf != NULL)
84		*static_cast<vt_video_interface *>(this) = *intf;
85
86		// or initialize to defaults if none provided
87		else
88		{
89		m_char_rom_tag = "";
90		}
91		}
92
93		//-------------------------------------------------
94	76	//  device_start - device-specific startup
95	77	//-------------------------------------------------
96	78

branches/new_menus/src/mess/video/vtvideo.h

r29505	r29506
15	15
16	16	#include "emu.h"
17	17
18		#define MCFG_VT_VIDEO_RAM_CALLBACK(_read) \
19		devcb = &vt100_video_device::set_ram_rd_callback(*device, DEVCB2_##_read);
20
21		#define MCFG_VT_VIDEO_CLEAR_VIDEO_INTERRUPT_CALLBACK(_write) \
22		devcb = &vt100_video_device::set_clear_video_irq_wr_callback(*device, DEVCB2_##_write);
23
24		struct vt_video_interface
25		{
26		const char *m_char_rom_tag; /* character rom region */
27		};
28
29
30	18	class vt100_video_device : public device_t,
31		public device_video_interface,
32		public vt_video_interface
	19	public device_video_interface
33	20	{
34	21	public:
35	22	vt100_video_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
r29505	r29506
39	26	template<class _Object> static devcb2_base &set_ram_rd_callback(device_t &device, _Object object) { return downcast<vt100_video_device &>(device).m_read_ram.set_callback(object); }
40	27	template<class _Object> static devcb2_base &set_clear_video_irq_wr_callback(device_t &device, _Object object) { return downcast<vt100_video_device &>(device).m_write_clear_video_interrupt.set_callback(object); }
41	28
	29	static void set_chargen_tag(device_t &device, const char *tag) { downcast<vt100_video_device &>(device).m_char_rom_tag = tag; }
	30
42	31	DECLARE_READ8_MEMBER(lba7_r);
43	32	DECLARE_WRITE8_MEMBER(dc012_w);
44	33	DECLARE_WRITE8_MEMBER(dc011_w);
r29505	r29506
47	36	virtual void video_update(bitmap_ind16 &bitmap, const rectangle &cliprect);
48	37	protected:
49	38	// device-level overrides
50		virtual void device_config_complete();
51	39	virtual void device_start();
52	40	virtual void device_reset();
53	41	virtual machine_config_constructor device_mconfig_additions() const;
r29505	r29506
67	55	bool MHFU_FLAG;
68	56	int MHFU_counter;
69	57
70
71	58	// dc012 attributes
72	59	UINT8 m_scroll_latch;
73	60	UINT8 m_scroll_latch_valid;
r29505	r29506
82	69	UINT8 m_frequency;
83	70	UINT8 m_interlaced;
84	71
	72	const char *m_char_rom_tag; /* character rom region */
85	73	required_device<palette_device> m_palette;
86	74	};
87	75
r29505	r29506
106	94	extern const device_type RAINBOW_VIDEO;
107	95
108	96
109		#define MCFG_VT100_VIDEO_ADD(_tag, _screen_tag, _intrf) \
110		MCFG_DEVICE_ADD(_tag, VT100_VIDEO, 0) \
111		MCFG_DEVICE_CONFIG(_intrf) \
112		MCFG_VIDEO_SET_SCREEN(_screen_tag)
	97	#define MCFG_VT_SET_SCREEN MCFG_VIDEO_SET_SCREEN
113	98
114		#define MCFG_RAINBOW_VIDEO_ADD(_tag, _screen_tag, _intrf) \
115		MCFG_DEVICE_ADD(_tag, RAINBOW_VIDEO, 0) \
116		MCFG_DEVICE_CONFIG(_intrf) \
117		MCFG_VIDEO_SET_SCREEN(_screen_tag)
	99	#define MCFG_VT_CHARGEN(_tag) \
	100	vt100_video_device::set_chargen_tag(*device, _tag);
118	101
	102	#define MCFG_VT_VIDEO_RAM_CALLBACK(_read) \
	103	devcb = &vt100_video_device::set_ram_rd_callback(*device, DEVCB2_##_read);
119	104
	105	#define MCFG_VT_VIDEO_CLEAR_VIDEO_INTERRUPT_CALLBACK(_write) \
	106	devcb = &vt100_video_device::set_clear_video_irq_wr_callback(*device, DEVCB2_##_write);
120	107
121	108	#endif

branches/new_menus/src/mess/video/z88.c

r29505	r29506
72	72	plot_pixel(bitmap, x + i, y + 7, pen);
73	73	}
74	74
75		void z88_state::lcd_update(bitmap_ind16 &bitmap, UINT16 sbf, UINT16 hires0, UINT16 hires1, UINT16 lores0, UINT16 lores1, int flash)
	75	UPD65031_SCREEN_UPDATE(z88_state::lcd_update)
76	76	{
77	77	if (sbf == 0)
78	78	{

Property changes on: branches/new_menus

Modified: svn:mergeinfo    Merged /trunk:r29425-29482

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team