MAME SVN History

199869 Revisions

r29503 Wednesday 9th April, 2014 at 18:31:16 UTC by hap
assume portb high bit is read-only

[src/mame/drivers]

namcos12.c namcos23.c

trunk/src/mame/drivers/namcos12.c
r29502	r29503
1077	1077
1078	1078	int m_ttt_cnt;
1079	1079	UINT32 m_ttt_val[2];
1080		int m_s12_porta;
1081		int m_s12_lastpB;
	1080	UINT8 m_sub_porta;
	1081	UINT8 m_sub_portb;
1082	1082
1083	1083	DECLARE_WRITE16_MEMBER(sharedram_w);
1084	1084	DECLARE_READ16_MEMBER(sharedram_r);
r29502	r29503
1235	1235	{
1236	1236	m_sub->set_input_line(1, vblank_state ? ASSERT_LINE : CLEAR_LINE);
1237	1237	m_adc->adtrg_w(vblank_state);
1238		m_s12_~~last~~pB = (m_s12_~~last~~pB & 0x7f) \| (vblank_state << 7);
	1238	m_sub_portb = (m_sub_portb & 0x7f) \| (vblank_state << 7);
1239	1239	}
1240	1240
1241	1241	static ADDRESS_MAP_START( namcos12_map, AS_PROGRAM, 32, namcos12_state )
r29502	r29503
1473	1473
1474	1474	READ16_MEMBER(namcos12_state::s12_mcu_pa_r)
1475	1475	{
1476		return m_s12_porta;
	1476	return m_sub_porta;
1477	1477	}
1478	1478
1479	1479	WRITE16_MEMBER(namcos12_state::s12_mcu_pa_w)
1480	1480	{
1481	1481	logerror("pa_w %02x\n", data);
1482		m_s12_porta = data;
1483		m_rtc->ce_w((m_s12_lastpB & 0x20) && (m_s12_porta & 1));
1484		m_settings->ce_w((m_s12_lastpB & 0x20) && !(m_s12_porta & 1));
	1482	m_sub_porta = data;
	1483	m_rtc->ce_w((m_sub_portb & 0x20) && (m_sub_porta & 1));
	1484	m_settings->ce_w((m_sub_portb & 0x20) && !(m_sub_porta & 1));
1485	1485	}
1486	1486
1487	1487	READ16_MEMBER(namcos12_state::s12_mcu_portB_r)
1488	1488	{
1489		return m_s12_~~last~~pB;
	1489	return m_sub_portb;
1490	1490	}
1491	1491
1492	1492	WRITE16_MEMBER(namcos12_state::s12_mcu_portB_w)
1493	1493	{
1494		m_s12_lastpB = data;
1495		m_rtc->ce_w((m_s12_lastpB & 0x20) && (m_s12_porta & 1));
1496		m_settings->ce_w((m_s12_lastpB & 0x20) && !(m_s12_porta & 1));
	1494	m_sub_portb = (m_sub_portb & 0x80) \| (data & 0x7f);
	1495	m_rtc->ce_w((m_sub_portb & 0x20) && (m_sub_porta & 1));
	1496	m_settings->ce_w((m_sub_portb & 0x20) && !(m_sub_porta & 1));
1497	1497	}
1498	1498
1499	1499	static ADDRESS_MAP_START( s12h8iomap, AS_IO, 16, namcos12_state )
r29502	r29503
1537	1537	{
1538	1538	membank("bank1")->configure_entries(0, memregion( "user2" )->bytes() / 0x200000, memregion( "user2" )->base(), 0x200000 );
1539	1539
1540		m_s12_porta = 0;
1541		m_s12_lastpB = 0x50;
	1540	m_sub_porta = 0;
	1541	m_sub_portb = 0x50;
1542	1542
1543	1543	m_n_tektagdmaoffset = 0;
1544	1544	m_n_dmaoffset = 0;

trunk/src/mame/drivers/namcos23.c
r29502	r29503
1447	1447	UINT16 m_c435_buffer[256];
1448	1448	int m_c435_buffer_pos;
1449	1449
1450		int m_porta;
1451		int m_lastpb;
	1450	UINT8 m_sub_porta;
	1451	UINT8 m_sub_portb;
1452	1452	UINT8 m_tssio_port_4;
1453	1453
1454	1454	void update_main_interrupts(UINT32 cause);
r29502	r29503
1508	1508	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
1509	1509	INTERRUPT_GEN_MEMBER(interrupt);
1510	1510	TIMER_CALLBACK_MEMBER(c361_timer_cb);
1511		void sub_irq(screen_device &screen, bool state);
	1511	void sub_irq(screen_device &screen, bool vblank_state);
1512	1512	UINT8 nthbyte(const UINT32 *pSource, int offs);
1513	1513	UINT16 nthword(const UINT32 *pSource, int offs);
1514	1514	inline INT32 u32_to_s24(UINT32 v);
r29502	r29503
2255	2255	m_render.count[m_render.cur] = 0;
2256	2256	}
2257	2257
2258		void namcos23_state::sub_irq(screen_device &screen, bool state)
	2258	void namcos23_state::sub_irq(screen_device &screen, bool vblank_state)
2259	2259	{
2260		m_subcpu->set_input_line(1, state ? ASSERT_LINE : CLEAR_LINE);
2261		m_adc->adtrg_w(state);
2262		m_lastpb = (m_lastpb & 0x7f) \| (state << 7);
	2260	m_subcpu->set_input_line(1, vblank_state ? ASSERT_LINE : CLEAR_LINE);
	2261	m_adc->adtrg_w(vblank_state);
	2262	m_sub_portb = (m_sub_portb & 0x7f) \| (vblank_state << 7);
2263	2263	}
2264	2264
2265	2265
r29502	r29503
2861	2861
2862	2862	READ16_MEMBER(namcos23_state::mcu_pa_r)
2863	2863	{
2864		return m_porta;
	2864	return m_sub_porta;
2865	2865	}
2866	2866
2867	2867	WRITE16_MEMBER(namcos23_state::mcu_pa_w)
2868	2868	{
2869	2869	m_rtc->ce_w(data & 1);
2870		m_porta = data;
2871		m_rtc->ce_w((m_lastpb & 0x20) && (m_porta & 1));
2872		m_settings->ce_w((m_lastpb & 0x20) && !(m_porta & 1));
	2870	m_sub_porta = data;
	2871	m_rtc->ce_w((m_sub_portb & 0x20) && (m_sub_porta & 1));
	2872	m_settings->ce_w((m_sub_portb & 0x20) && !(m_sub_porta & 1));
2873	2873	}
2874	2874
2875	2875
r29502	r29503
2878	2878
2879	2879	READ16_MEMBER(namcos23_state::mcu_pb_r)
2880	2880	{
2881		return m_lastpb;
	2881	return m_sub_portb;
2882	2882	}
2883	2883
2884	2884	WRITE16_MEMBER(namcos23_state::mcu_pb_w)
2885	2885	{
2886		m_lastpb = data;
2887		m_rtc->ce_w((m_lastpb & 0x20) && (m_porta & 1));
2888		m_settings->ce_w((m_lastpb & 0x20) && !(m_porta & 1));
	2886	m_sub_portb = (m_sub_portb & 0x80) \| (data & 0x7f);
	2887	m_rtc->ce_w((m_sub_portb & 0x20) && (m_sub_porta & 1));
	2888	m_settings->ce_w((m_sub_portb & 0x20) && !(m_sub_porta & 1));
2889	2889	}
2890	2890
2891	2891
r29502	r29503
3256	3256	m_jvssense = 1;
3257	3257	m_main_irqcause = 0;
3258	3258	m_ctl_vbl_active = false;
3259		m_lastpb = 0x50;
	3259	m_sub_portb = 0x50;
3260	3260	m_tssio_port_4 = 0;
3261		m_porta = 0;
	3261	m_sub_porta = 0;
3262	3262	m_subcpu_running = false;
3263	3263	m_render.count[0] = m_render.count[1] = 0;
3264	3264	m_render.cur = 0;

199869 Revisions