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r29482 Wednesday 9th April, 2014 at 12:12:09 UTC by Alex Jackson
namcona1.c: use set_palette_offset for tilemaps; use GFXDECODE_RAM; more cleanups [Alex Jackson]

[src/emu]	tilemap.h
[src/mame/drivers]	namcona1.c
[src/mame/includes]	namcona1.h
[src/mame/video]	namcona1.c

trunk/src/emu/tilemap.h

r29481	r29482
499	499	UINT32 width() const { return m_width; }
500	500	UINT32 height() const { return m_height; }
501	501	bool enabled() const { return m_enable; }
	502	int palette_offset() const { return m_palette_offset; }
502	503	int scrolldx() const { return (m_attributes & TILEMAP_FLIPX) ? m_dx_flipped : m_dx; }
503	504	int scrolldy() const { return (m_attributes & TILEMAP_FLIPY) ? m_dy_flipped : m_dy; }
504	505	int scrollx(int which = 0) const { return (which < m_scrollrows) ? m_rowscroll[which] : 0; }

trunk/src/mame/drivers/namcona1.c

r29481	r29482
293	293
294	294	/***************************************************************/
295	295
296		READ16_MEMBER(namcona1_state::namcona1_vreg_r)
297		{
298		return m_vreg[offset];
299		} /* namcona1_vreg_r */
300
301	296	int namcona1_state::transfer_dword( UINT32 dest, UINT32 source )
302	297	{
303	298	UINT16 data;
r29481	r29482
549	544	AM_RANGE(0xc00000, 0xdfffff) AM_ROM AM_REGION("maincpu", 0x080000)  /* code */
550	545	AM_RANGE(0xe00000, 0xe00fff) AM_DEVREADWRITE8("eeprom", eeprom_parallel_28xx_device, read, write, 0x00ff)
551	546	AM_RANGE(0xe40000, 0xe4000f) AM_READWRITE(custom_key_r, custom_key_w)
552		AM_RANGE(0xefff00, 0xefffff) AM_READWRITE(namcona1_vreg_r, namcona1_vreg_w) AM_SHARE("vreg")
553		AM_RANGE(0xf00000, 0xf01fff) AM_READWRITE(namcona1_paletteram_r, namcona1_paletteram_w) AM_SHARE("paletteram")
554		AM_RANGE(0xf40000, 0xf7ffff) AM_READWRITE(namcona1_gfxram_r, namcona1_gfxram_w)
555		AM_RANGE(0xff0000, 0xffbfff) AM_READWRITE(namcona1_videoram_r, namcona1_videoram_w) AM_SHARE("videoram")
	547	AM_RANGE(0xefff00, 0xefffff) AM_RAM_WRITE(namcona1_vreg_w) AM_SHARE("vreg")
	548	AM_RANGE(0xf00000, 0xf01fff) AM_RAM_WRITE(namcona1_paletteram_w) AM_SHARE("paletteram")
	549	AM_RANGE(0xf40000, 0xf7ffff) AM_READWRITE(namcona1_gfxram_r, namcona1_gfxram_w) AM_SHARE("cgram")
	550	AM_RANGE(0xff0000, 0xffbfff) AM_RAM_WRITE(namcona1_videoram_w) AM_SHARE("videoram")
556	551	AM_RANGE(0xffd000, 0xffdfff) AM_RAM /* unknown */
557	552	AM_RANGE(0xffe000, 0xffefff) AM_RAM AM_SHARE("scroll")      /* scroll registers */
558	553	AM_RANGE(0xfff000, 0xffffff) AM_RAM AM_SHARE("spriteram")           /* spriteram */
r29481	r29482
571	566	AM_RANGE(0xe00000, 0xe00fff) AM_DEVREADWRITE8("eeprom", eeprom_parallel_28xx_device, read, write, 0x00ff)
572	567	/* xday: additional battery-backed ram at 00E024FA? */
573	568	AM_RANGE(0xe40000, 0xe4000f) AM_READWRITE(custom_key_r, custom_key_w)
574		AM_RANGE(0xefff00, 0xefffff) AM_READWRITE(namcona1_vreg_r, namcona1_vreg_w) AM_SHARE("vreg")
575		AM_RANGE(0xf00000, 0xf01fff) AM_READWRITE(namcona1_paletteram_r, namcona1_paletteram_w) AM_SHARE("paletteram")
576		AM_RANGE(0xf40000, 0xf7ffff) AM_READWRITE(namcona1_gfxram_r, namcona1_gfxram_w)
577		AM_RANGE(0xff0000, 0xffbfff) AM_READWRITE(namcona1_videoram_r, namcona1_videoram_w) AM_SHARE("videoram")
	569	AM_RANGE(0xefff00, 0xefffff) AM_RAM_WRITE(namcona1_vreg_w) AM_SHARE("vreg")
	570	AM_RANGE(0xf00000, 0xf01fff) AM_RAM_WRITE(namcona1_paletteram_w) AM_SHARE("paletteram")
	571	AM_RANGE(0xf40000, 0xf7ffff) AM_READWRITE(namcona1_gfxram_r, namcona1_gfxram_w) AM_SHARE("cgram")
	572	AM_RANGE(0xff0000, 0xffbfff) AM_RAM_WRITE(namcona1_videoram_w) AM_SHARE("videoram")
578	573	AM_RANGE(0xffd000, 0xffdfff) AM_RAM /* unknown */
579	574	AM_RANGE(0xffe000, 0xffefff) AM_RAM AM_SHARE("scroll")      /* scroll registers */
580	575	AM_RANGE(0xfff000, 0xffffff) AM_RAM AM_SHARE("spriteram")           /* spriteram */
r29481	r29482
875	870
876	871	/***************************************************************************/
877	872
	873	static const gfx_layout cg_layout_8bpp =
	874	{
	875	8,8,
	876	RGN_FRAC(1,1),
	877	8, /* 8BPP */
	878	{ 0,1,2,3,4,5,6,7 },
	879	{ STEP8(0, 8) },
	880	{ STEP8(0, 8*8) },
	881	8*8*8
	882	};
	883
	884	static const gfx_layout cg_layout_4bpp =
	885	{
	886	8,8,
	887	RGN_FRAC(1,1),
	888	4, /* 4BPP */
	889	{ 4,5,6,7 },
	890	{ STEP8(0, 8) },
	891	{ STEP8(0, 8*8) },
	892	8*8*8
	893	};
	894
	895	static const gfx_layout shape_layout =
	896	{
	897	8,8,
	898	0x1000,
	899	1,
	900	{ 0 },
	901	{ STEP8(0, 1) },
	902	{ STEP8(0, 8) },
	903	8*8
	904	};
	905
	906	static GFXDECODE_START( namcona1 )
	907	GFXDECODE_RAM( "cgram", 0, cg_layout_8bpp, 0, 0x2000/256 )
	908	GFXDECODE_RAM( "cgram", 0, cg_layout_4bpp, 0, 0x2000/16  )
	909	GFXDECODE_RAM(  NULL,   0, shape_layout,   0, 0x2000/2   )
	910	GFXDECODE_END
	911
	912	/***************************************************************************/
	913
878	914	TIMER_DEVICE_CALLBACK_MEMBER(namcona1_state::namcona1_interrupt)
879	915	{
880	916	int scanline = param;
r29481	r29482
948	984
949	985	MCFG_PALETTE_ADD("palette", 0x2000)
950	986	MCFG_PALETTE_ENABLE_SHADOWS()
951		MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
	987	MCFG_GFXDECODE_ADD("gfxdecode", "palette", namcona1)
952	988
953	989	/* sound hardware */
954	990	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")

trunk/src/mame/includes/namcona1.h

r29481	r29482
22	22	NAMCO_XDAY2
23	23	};
24	24
25		#define NAMCONA1_NUM_TILEMAPS 4
26	25
27
28	26	class namcona1_state : public driver_device
29	27	{
30	28	public:
r29481	r29482
37	35	m_screen(*this, "screen"),
38	36	m_palette(*this, "palette"),
39	37	m_c140(*this, "c140"),
40		m_videoram(*this,"videoram"),
41		m_spriteram(*this,"spriteram"),
42	38	m_workram(*this,"workram"),
43	39	m_vreg(*this,"vreg"),
44		m_scroll(*this,"scroll")
	40	m_paletteram(*this, "paletteram"),
	41	m_cgram(*this, "cgram"),
	42	m_videoram(*this,"videoram"),
	43	m_scroll(*this,"scroll"),
	44	m_spriteram(*this,"spriteram")
45	45	{ }
46	46
47	47	required_device<cpu_device> m_maincpu;
r29481	r29482
51	51	required_device<screen_device> m_screen;
52	52	required_device<palette_device> m_palette;
53	53	required_device<c140_device> m_c140;
54		required_shared_ptr<UINT16> m_videoram;
55		required_shared_ptr<UINT16> m_spriteram;
56	54	required_shared_ptr<UINT16> m_workram;
57	55	required_shared_ptr<UINT16> m_vreg;
	56	required_shared_ptr<UINT16> m_paletteram;
	57	required_shared_ptr<UINT16> m_cgram;
	58	required_shared_ptr<UINT16> m_videoram;
58	59	required_shared_ptr<UINT16> m_scroll;
	60	required_shared_ptr<UINT16> m_spriteram;
59	61
	62	// this has to be UINT8 to be in the right byte order for the tilemap system
	63	dynamic_array<UINT8> m_shaperam;
	64
60	65	UINT16 *m_mpBank0;
61	66	UINT16 *m_mpBank1;
62	67	int m_mEnableInterrupts;
r29481	r29482
68	73	UINT8 m_mcu_port5;
69	74	UINT8 m_mcu_port6;
70	75	UINT8 m_mcu_port8;
71		UINT16 *m_shaperam;
72		UINT16 *m_cgram;
73		tilemap_t *m_roz_tilemap;
74		int m_roz_palette;
75		tilemap_t *m_bg_tilemap[NAMCONA1_NUM_TILEMAPS];
76		int m_tilemap_palette_bank[NAMCONA1_NUM_TILEMAPS];
	76	tilemap_t *m_bg_tilemap[4+1];
77	77	int m_palette_is_dirty;
78		UINT8 m_mask_data[8];
79		UINT8 m_conv_data[9];
80	78
81	79
82	80	DECLARE_READ16_MEMBER(custom_key_r);
83	81	DECLARE_WRITE16_MEMBER(custom_key_w);
84		DECLARE_READ16_MEMBER(namcona1_vreg_r);
85	82	DECLARE_WRITE16_MEMBER(namcona1_vreg_w);
86	83	DECLARE_READ16_MEMBER(mcu_mailbox_r);
87	84	DECLARE_WRITE16_MEMBER(mcu_mailbox_w_68k);
r29481	r29482
106	103	void init_namcona1(int gametype);
107	104	void UpdatePalette(int offset);
108	105	DECLARE_WRITE16_MEMBER(namcona1_videoram_w);
109		DECLARE_READ16_MEMBER(namcona1_videoram_r);
110		DECLARE_READ16_MEMBER(namcona1_paletteram_r);
111	106	DECLARE_WRITE16_MEMBER(namcona1_paletteram_w);
112	107	DECLARE_READ16_MEMBER(namcona1_gfxram_r);
113	108	DECLARE_WRITE16_MEMBER(namcona1_gfxram_w);
r29481	r29482
142	137	TIMER_DEVICE_CALLBACK_MEMBER(mcu_interrupt);
143	138
144	139	private:
145		void tilemap_get_info(tile_data &tileinfo, int tile_index, const UINT16 *tilemap_videoram, int tilemap_color, bool use_4bpp_gfx);
	140	void tilemap_get_info(tile_data &tileinfo, int tile_index, const UINT16 *tilemap_videoram, bool use_4bpp_gfx);
146	141	};

trunk/src/mame/video/namcona1.c

r29481	r29482
14	14	tile_data &tileinfo,
15	15	int tile_index,
16	16	const UINT16 *tilemap_videoram,
17		int tilemap_color,
18	17	bool use_4bpp_gfx )
19	18	{
20	19	UINT16 *source;
21	20
22	21	int data = tilemap_videoram[tile_index];
23	22	int tile = data&0xfff;
24		int gfx;
	23	int gfx = use_4bpp_gfx ? 1 : 0;
	24	int color = use_4bpp_gfx ? (data & 0x7000)>>12 : 0;
25	25
26		if( use_4bpp_gfx )
27		{
28		gfx = 1;
29		tilemap_color *= 0x10;
30		tilemap_color += (data & 0x7000)>>12;
31		}
32		else
33		{
34		gfx = 0;
35		}
36
37	26	if( data & 0x8000 )
38	27	{
39		SET_TILE_INFO_MEMBER(gfx,tile,tilemap_color,TILE_FORCE_LAYER0 );
	28	SET_TILE_INFO_MEMBER(gfx,tile,color,TILE_FORCE_LAYER0 );
40	29	}
41	30	else
42	31	{
43		SET_TILE_INFO_MEMBER(gfx,tile,tilemap_color,0 );
44		if (ENDIANNESS_NATIVE == ENDIANNESS_BIG)
45		tileinfo.mask_data = (UINT8 *)(m_shaperam+4*tile);
46		else
47		{
48		UINT8 *mask_data = m_mask_data;
49		source = m_shaperam+4*tile;
50		mask_data[0] = source[0]>>8;
51		mask_data[1] = source[0]&0xff;
52		mask_data[2] = source[1]>>8;
53		mask_data[3] = source[1]&0xff;
54		mask_data[4] = source[2]>>8;
55		mask_data[5] = source[2]&0xff;
56		mask_data[6] = source[3]>>8;
57		mask_data[7] = source[3]&0xff;
58		tileinfo.mask_data = mask_data;
59		}
	32	SET_TILE_INFO_MEMBER(gfx,tile,color,0 );
	33	tileinfo.mask_data = &m_shaperam[tile*8];
60	34	}
61	35	} /* tilemap_get_info */
62	36
63	37	TILE_GET_INFO_MEMBER(namcona1_state::tilemap_get_info0)
64	38	{
65	39	UINT16 *videoram = m_videoram;
66		tilemap_get_info(tileinfo,tile_index,0*0x1000+videoram,m_tilemap_palette_bank[0],m_vreg[0xbc/2]&1);
	40	tilemap_get_info(tileinfo,tile_index,0*0x1000+videoram,m_vreg[0xbc/2]&1);
67	41	}
68	42
69	43	TILE_GET_INFO_MEMBER(namcona1_state::tilemap_get_info1)
70	44	{
71	45	UINT16 *videoram = m_videoram;
72		tilemap_get_info(tileinfo,tile_index,1*0x1000+videoram,m_tilemap_palette_bank[1],m_vreg[0xbc/2]&2);
	46	tilemap_get_info(tileinfo,tile_index,1*0x1000+videoram,m_vreg[0xbc/2]&2);
73	47	}
74	48
75	49	TILE_GET_INFO_MEMBER(namcona1_state::tilemap_get_info2)
76	50	{
77	51	UINT16 *videoram = m_videoram;
78		tilemap_get_info(tileinfo,tile_index,2*0x1000+videoram,m_tilemap_palette_bank[2],m_vreg[0xbc/2]&4);
	52	tilemap_get_info(tileinfo,tile_index,2*0x1000+videoram,m_vreg[0xbc/2]&4);
79	53	}
80	54
81	55	TILE_GET_INFO_MEMBER(namcona1_state::tilemap_get_info3)
82	56	{
83	57	UINT16 *videoram = m_videoram;
84		tilemap_get_info(tileinfo,tile_index,3*0x1000+videoram,m_tilemap_palette_bank[3],m_vreg[0xbc/2]&8);
	58	tilemap_get_info(tileinfo,tile_index,3*0x1000+videoram,m_vreg[0xbc/2]&8);
85	59	}
86	60
87	61	TILE_GET_INFO_MEMBER(namcona1_state::roz_get_info)
88	62	{
89		UINT16 *videoram = m_videoram;
90	63	/* each logical tile is constructed from 4*4 normal tiles */
91		int tilemap_color = m_roz_palette;
92	64	int use_4bpp_gfx = m_vreg[0xbc/2]&16; /* ? */
93	65	int c = tile_index%0x40;
94	66	int r = tile_index/0x40;
95		int data = videoram[0x8000/2+(r/4)*0x40+c/4]&0xfbf; /* mask out bit 0x40 - patch for Emeraldia Japan */
	67	int data = m_videoram[0x8000/2+(r/4)*0x40+c/4]&0xfbf; /* mask out bit 0x40 - patch for Emeraldia Japan */
96	68	int tile = (data+(c%4)+(r%4)*0x40)&0xfff;
97		int gfx = use_4bpp_gfx;
98		if( use_4bpp_gfx )
99		{
100		tilemap_color *= 0x10;
101		tilemap_color += (data & 0x7000)>>12;
102		}
	69	int gfx = use_4bpp_gfx ? 1 : 0;
	70	int color = use_4bpp_gfx ? (data & 0x7000)>>12 : 0;
	71
103	72	if( data & 0x8000 )
104	73	{
105		SET_TILE_INFO_MEMBER(gfx,tile,tilemap_color,TILE_FORCE_LAYER0 );
	74	SET_TILE_INFO_MEMBER(gfx,tile,color,TILE_FORCE_LAYER0 );
106	75	}
107	76	else
108	77	{
109		UINT8 *mask_data = (UINT8 *)(m_shaperam+4*tile);
110
111		if (ENDIANNESS_NATIVE == ENDIANNESS_LITTLE)
112		{
113		UINT16 *source = (UINT16 *)mask_data;
114		UINT8 *conv_data = m_conv_data;
115		conv_data[0] = source[0]>>8;
116		conv_data[1] = source[0]&0xff;
117		conv_data[2] = source[1]>>8;
118		conv_data[3] = source[1]&0xff;
119		conv_data[4] = source[2]>>8;
120		conv_data[5] = source[2]&0xff;
121		conv_data[6] = source[3]>>8;
122		conv_data[7] = source[3]&0xff;
123		mask_data = conv_data;
124		}
125		SET_TILE_INFO_MEMBER(gfx,tile,tilemap_color,0 );
126		tileinfo.mask_data = mask_data;
	78	SET_TILE_INFO_MEMBER(gfx,tile,color,0 );
	79	tileinfo.mask_data = &m_shaperam[tile*8];
127	80	}
128	81	} /* roz_get_info */
129	82
r29481	r29482
135	88	COMBINE_DATA( &videoram[offset] );
136	89	if( offset<0x8000/2 )
137	90	{
138		m_bg_tilemap[offset/0x1000]->mark_tile_dirty(offset&0xfff );
	91	m_bg_tilemap[offset/0x1000]->mark_tile_dirty(offset&0xfff);
139	92	}
140	93	else if( offset<0xa000/2 )
141	94	{
142		m_roz_tilemap ->mark_all_dirty();
	95	m_bg_tilemap[4]->mark_all_dirty();
143	96	}
144	97	} /* namcona1_videoram_w */
145	98
146		READ16_MEMBER(namcona1_state::namcona1_videoram_r)
147		{
148		UINT16 *videoram = m_videoram;
149		return videoram[offset];
150		} /* namcona1_videoram_r */
151
152	99	/*************************************************************************/
153	100
154	101	void namcona1_state::UpdatePalette( int offset )
155	102	{
156		UINT16 data = m_generic_paletteram_16[offset]; /* -RRRRRGG GGGBBBBB */
	103	UINT16 data = m_paletteram[offset]; /* -RRRRRGG GGGBBBBB */
157	104	/**
158	105	* sprites can be configured to use an alternate interpretation of palette ram
159	106	* (used in-game in Emeraldia)
r29481	r29482
168	115	m_palette->set_pen_color(offset, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
169	116	} /* namcona1_paletteram_w */
170	117
171		READ16_MEMBER(namcona1_state::namcona1_paletteram_r)
172		{
173		return m_generic_paletteram_16[offset];
174		} /* namcona1_paletteram_r */
175
176	118	WRITE16_MEMBER(namcona1_state::namcona1_paletteram_w)
177	119	{
178		COMBINE_DATA( &m_generic_paletteram_16[offset] );
	120	COMBINE_DATA( &m_paletteram[offset] );
179	121	if( m_vreg[0x8e/2] )
180	122	{ /* graphics enabled; update palette immediately */
181	123	UpdatePalette( offset );
r29481	r29482
186	128	}
187	129	}
188	130
189		/*************************************************************************/
190	131
191		static const gfx_layout shape_layout =
192		{
193		8,8,
194		0x1000,
195		1,
196		{ 0 },
197		{ STEP8(0, 1) },
198		{ STEP8(0, 8) },
199		8*8
200		}; /* shape_layout */
201
202		static const gfx_layout cg_layout_8bpp =
203		{
204		8,8,
205		0x1000,
206		8, /* 8BPP */
207		{ 0,1,2,3,4,5,6,7 },
208		{ STEP8(0, 8) },
209		{ STEP8(0, 8*8) },
210		8*8*8
211		}; /* cg_layout_8bpp */
212
213		static const gfx_layout cg_layout_4bpp =
214		{
215		8,8,
216		0x1000,
217		4, /* 4BPP */
218		{ 4,5,6,7 },
219		{ STEP8(0, 8) },
220		{ STEP8(0, 8*8) },
221		8*8*8
222		}; /* cg_layout_4bpp */
223
224	132	READ16_MEMBER(namcona1_state::namcona1_gfxram_r)
225	133	{
226	134	UINT16 type = m_vreg[0x0c/2];
r29481	r29482
228	136	{
229	137	if( offset<0x4000 )
230	138	{
231		return m_shaperam[offset];
	139	offset *= 2;
	140	return (m_shaperam[offset] << 8) | m_shaperam[offset+1];
232	141	}
233	142	}
234	143	else if( type == 0x02 )
r29481	r29482
247	156	{
248	157	if( offset<0x4000 )
249	158	{
250		old_word = m_shaperam[offset];
251		COMBINE_DATA( &m_shaperam[offset] );
252		if( m_shaperam[offset]!=old_word )
253		m_gfxdecode->gfx(2)->mark_dirty(offset/4);
	159	offset *= 2;
	160	if (ACCESSING_BITS_8_15)
	161	m_shaperam[offset] = data >> 8;
	162	if (ACCESSING_BITS_0_7)
	163	m_shaperam[offset+1] = data;
	164	m_gfxdecode->gfx(2)->mark_dirty(offset/8);
254	165	}
255	166	}
256	167	else if( type == 0x02 )
r29481	r29482
267	178
268	179	void namcona1_state::video_start()
269	180	{
270		m_roz_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::roz_get_info),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
271		m_roz_palette = -1;
272
273		for( int i=0; i<NAMCONA1_NUM_TILEMAPS; i++ )
274		{
275		m_tilemap_palette_bank[i] = -1;
276		}
277
	181	// normal tilemaps
278	182	m_bg_tilemap[0] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info0),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
279	183	m_bg_tilemap[1] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info1),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
280	184	m_bg_tilemap[2] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info2),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
281	185	m_bg_tilemap[3] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info3),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
282	186
283		m_shaperam           = auto_alloc_array_clear(machine(), UINT16, 0x2000*4/2 );
284		m_cgram              = auto_alloc_array_clear(machine(), UINT16, 0x1000*0x40/2 );
	187	// roz tilemap
	188	m_bg_tilemap[4] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::roz_get_info),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
285	189
286		m_gfxdecode->set_gfx(0, global_alloc( gfx_element(m_palette, cg_layout_8bpp, (UINT8 *)m_cgram, NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries()/256, 0 )));
287		m_gfxdecode->set_gfx(1, global_alloc( gfx_element(m_palette, cg_layout_4bpp, (UINT8 *)m_cgram, NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries()/16, 0 )));
288		m_gfxdecode->set_gfx(2, global_alloc( gfx_element(m_palette, shape_layout, (UINT8 *)m_shaperam, NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries()/2, 0 )));
	190	m_shaperam.resize(0x8000);
289	191
	192	m_gfxdecode->gfx(2)->set_source(m_shaperam);
290	193	} /* namcona1_vh_start */
291	194
292	195	/*************************************************************************/
r29481	r29482
533	436
534	437	void namcona1_state::draw_background(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int which, int primask )
535	438	{
536		if(which == NAMCONA1_NUM_TILEMAPS )
	439	if(which == 4)
537	440	{
538		/* draw roz all at once */
	441	/* draw the roz tilemap all at once */
539	442	int incxx = ((INT16)m_vreg[0xc0/2])<<8;
540	443	int incxy = ((INT16)m_vreg[0xc2/2])<<8;
541	444	int incyx = ((INT16)m_vreg[0xc4/2])<<8;
r29481	r29482
546	449	int dy = -8; /* vertical adjust */
547	450	UINT32 startx = (xoffset<<12)+incxx*dx+incyx*dy;
548	451	UINT32 starty = (yoffset<<12)+incxy*dx+incyy*dy;
549		m_roz_tilemap->draw_roz(screen, bitmap, cliprect,
	452	m_bg_tilemap[4]->draw_roz(screen, bitmap, cliprect,
550	453	startx, starty, incxx, incxy, incyx, incyy, 0, 0, primask, 0);
551	454	}
552	455	else
r29481	r29482
559	462	*  tmap3   ffec00  ffee00
560	463	*/
561	464	const UINT16 *scroll = &m_scroll[which * 0x400/2];
562		const pen_t *paldata = &m_palette->pen(m_tilemap_palette_bank[which] * 256);
	465	const pen_t *paldata = &m_palette->pen(m_bg_tilemap[which]->palette_offset());
563	466	rectangle clip = cliprect;
564	467	int xadjust = 0x3a - which*2;
565	468	int scrollx = 0;
r29481	r29482
626	529	m_palette_is_dirty = 0;
627	530	}
628	531
629		for( which=0; which<NAMCONA1_NUM_TILEMAPS; which++ )
630		{
631		int tilemap_color = m_vreg[0xb0/2+(which&3)]&0xf;
632		if( tilemap_color!=m_tilemap_palette_bank[which] )
633		{
634		m_bg_tilemap[which] ->mark_all_dirty();
635		m_tilemap_palette_bank[which] = tilemap_color;
636		}
637		} /* next tilemap */
	532	for( which=0; which < 4; which++ )
	533	m_bg_tilemap[which]->set_palette_offset((m_vreg[0xb0/2 + which] & 0xf) * 256);
638	534
639		{ /* ROZ tilemap */
640		int color = m_vreg[0xba/2]&0xf;
641		if( color != m_roz_palette )
642		{
643		m_roz_tilemap ->mark_all_dirty();
644		m_roz_palette = color;
645		}
646		}
	535	m_bg_tilemap[4]->set_palette_offset((m_vreg[0xba/2] & 0xf) * 256);
647	536
648	537	screen.priority().fill(0, cliprect );
649	538

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