trunk/src/mame/machine/archimds.c
| r29456 | r29457 | |
|---|
| 75 | 75 | void archimedes_state::archimedes_clear_irq_a(int mask) |
| 76 | 76 | { |
| 77 | 77 | m_ioc_regs[IRQ_STATUS_A] &= ~mask; |
| 78 | archimedes_request_irq_a(0); |
| 78 | 79 | } |
| 79 | 80 | |
| 80 | 81 | void archimedes_state::archimedes_clear_irq_b(int mask) |
| r29456 | r29457 | |
|---|
| 111 | 112 | |
| 112 | 113 | /* video DMA */ |
| 113 | 114 | /* TODO: what type of DMA this is, burst or cycle steal? Docs doesn't explain it (4 usec is the DRAM refresh). */ |
| 115 | /* TODO: change m_region_vram into proper alloc array */ |
| 114 | 116 | void archimedes_state::vidc_video_tick() |
| 115 | 117 | { |
| 116 | 118 | address_space &space = m_maincpu->space(AS_PROGRAM); |
| 117 | 119 | static UINT8 *vram = m_region_vram->base(); |
| 118 | 120 | UINT32 size; |
| 119 | 121 | UINT32 m_vidc_ccur; |
| 122 | UINT32 offset_ptr; |
| 120 | 123 | |
| 121 | 124 | size = m_vidc_vidend-m_vidc_vidstart+0x10; |
| 122 | 125 | |
| 126 | offset_ptr = m_vidc_vidstart+m_vidc_vidinit; |
| 127 | |
| 123 | 128 | for(m_vidc_vidcur = 0;m_vidc_vidcur < size;m_vidc_vidcur++) |
| 124 | | vram[m_vidc_vidcur] = (space.read_byte(m_vidc_vidstart+m_vidc_vidcur)); |
| 129 | { |
| 130 | vram[m_vidc_vidcur] = (space.read_byte(offset_ptr)); |
| 131 | offset_ptr++; |
| 132 | if(offset_ptr >= m_vidc_vidend+0x10) // TODO: correct? |
| 133 | offset_ptr = m_vidc_vidstart; |
| 134 | } |
| 125 | 135 | |
| 126 | 136 | size = m_vidc_vidend-m_vidc_vidstart+0x10; |
| 127 | 137 | |
| r29456 | r29457 | |
|---|
| 129 | 139 | m_cursor_vram[m_vidc_ccur] = (space.read_byte(m_vidc_cinit+m_vidc_ccur)); |
| 130 | 140 | |
| 131 | 141 | if(m_video_dma_on) |
| 142 | { |
| 132 | 143 | m_vid_timer->adjust(m_screen->time_until_pos(m_vidc_regs[0xb4])); |
| 144 | } |
| 133 | 145 | else |
| 134 | 146 | m_vid_timer->adjust(attotime::never); |
| 135 | 147 | } |
| r29456 | r29457 | |
|---|
| 798 | 810 | visarea.max_x = m_vidc_regs[VIDC_HBER] - m_vidc_regs[VIDC_HBSR] - 1; |
| 799 | 811 | visarea.max_y = (m_vidc_regs[VIDC_VBER] - m_vidc_regs[VIDC_VBSR]) * (m_vidc_interlace+1); |
| 800 | 812 | |
| 801 | | logerror("Configuring: htotal %d vtotal %d border %d x %d display %d x %d\n", |
| 802 | | m_vidc_regs[VIDC_HCR], m_vidc_regs[VIDC_VCR], |
| 803 | | visarea.max_x, visarea.max_y, |
| 804 | | m_vidc_regs[VIDC_HDER]-m_vidc_regs[VIDC_HDSR],m_vidc_regs[VIDC_VDER]-m_vidc_regs[VIDC_VDSR]+1); |
| 813 | //logerror("Configuring: htotal %d vtotal %d border %d x %d display %d x %d\n", |
| 814 | // m_vidc_regs[VIDC_HCR], m_vidc_regs[VIDC_VCR], |
| 815 | // visarea.max_x, visarea.max_y, |
| 816 | // m_vidc_regs[VIDC_HDER]-m_vidc_regs[VIDC_HDSR],m_vidc_regs[VIDC_VDER]-m_vidc_regs[VIDC_VDSR]+1); |
| 805 | 817 | |
| 806 | 818 | /* FIXME: pixel clock */ |
| 807 | 819 | refresh = HZ_TO_ATTOSECONDS(pixel_rate[m_vidc_pixel_clk]*2) * m_vidc_regs[VIDC_HCR] * m_vidc_regs[VIDC_VCR]; |