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r29436 Tuesday 8th April, 2014 at 07:56:04 UTC by Curt Coder
(MESS) tandy2k: WIP. (nw)
[src/emu/video]crt9007.c
[src/mess/drivers]tandy2k.c
[src/mess/includes]tandy2k.h

trunk/src/emu/video/crt9007.c
r29435r29436
398398
399399inline void crt9007_t::recompute_parameters()
400400{
401#ifdef UNUSED_FOR_NOW
402401   // check that necessary registers have been loaded
403402   if (!HAS_VALID_PARAMETERS) return;
404403
405404   // screen dimensions
406   int horiz_pix_total = CHARACTERS_PER_HORIZONTAL_PERIOD * m_hpixels_per_column;
407   int vert_pix_total = SCAN_LINES_PER_FRAME;
405   //int horiz_pix_total = CHARACTERS_PER_HORIZONTAL_PERIOD * m_hpixels_per_column;
406   //int vert_pix_total = SCAN_LINES_PER_FRAME;
408407
409408   // refresh rate
410   attoseconds_t refresh = HZ_TO_ATTOSECONDS(clock()) * horiz_pix_total * vert_pix_total;
409   //attoseconds_t refresh = HZ_TO_ATTOSECONDS(clock()) * horiz_pix_total * vert_pix_total;
411410
412411   // horizontal sync
413412   m_hsync_start = 0;
r29435r29436
426425   m_vsync_end = VERTICAL_SYNC_WIDTH;
427426
428427   // visible area
429   rectangle visarea;
428   //rectangle visarea;
430429
431   visarea.set(m_hsync_end, horiz_pix_total - 1, m_vsync_end, vert_pix_total - 1);
430   //visarea.set(m_hsync_end, horiz_pix_total - 1, m_vsync_end, vert_pix_total - 1);
432431
433   if (LOG)
434   {
435      logerror("CRT9007 '%s' Screen: %u x %u @ %f Hz\n", tag(), horiz_pix_total, vert_pix_total, 1 / ATTOSECONDS_TO_DOUBLE(refresh));
436      logerror("CRT9007 '%s' Visible Area: (%u, %u) - (%u, %u)\n", tag(), visarea.min_x, visarea.min_y, visarea.max_x, visarea.max_y);
437   }
432   //if (LOG)
433   //{
434   //   logerror("CRT9007 '%s' Screen: %u x %u @ %f Hz\n", tag(), horiz_pix_total, vert_pix_total, 1 / ATTOSECONDS_TO_DOUBLE(refresh));
435   //   logerror("CRT9007 '%s' Visible Area: (%u, %u) - (%u, %u)\n", tag(), visarea.min_x, visarea.min_y, visarea.max_x, visarea.max_y);
436   //}
438437
439   m_screen->configure(horiz_pix_total, vert_pix_total, visarea, refresh);
438   //m_screen->configure(horiz_pix_total, vert_pix_total, visarea, refresh);
440439
441440   m_hsync_timer->adjust(m_screen->time_until_pos(0, 0));
442441   m_vsync_timer->adjust(m_screen->time_until_pos(0, 0));
443442   m_vlt_timer->adjust(m_screen->time_until_pos(0, m_vlt_start), 1);
444443   m_drb_timer->adjust(m_screen->time_until_pos(0, 0));
445#endif
446444}
447445
448446
trunk/src/mess/includes/tandy2k.h
r29435r29436
7676      m_pb_sel(0),
7777      m_vram_base(0),
7878      m_vidouts(0),
79      m_clkspd(0),
80      m_clkcnt(0),
79      m_clkspd(-1),
80      m_clkcnt(-1),
8181      m_blc(0),
8282      m_bkc(0),
8383      m_cblank(0),
trunk/src/mess/drivers/tandy2k.c
r29435r29436
1313    - floppy
1414        - HDL is also connected to WP/TS input where TS is used to detect motor status
1515        - 3 second motor off delay timer
16    - DMA
1716    - video (video RAM is at memory top - 0x1400, i.e. 0x1ec00)
1817    - keyboard ROM
1918    - hires graphics board
r29435r29436
2524
2625#include "includes/tandy2k.h"
2726
27#define LOG 1
28
2829// Read/Write Handlers
2930
3031void tandy2k_state::update_drq()
r29435r29436
5051void tandy2k_state::dma_request(int line, int state)
5152{
5253   m_busdmarq[line] = state;
54
5355   update_drq();
5456}
5557
r29435r29436
119121
120122       0       KBEN        keyboard enable
121123       1       EXTCLK      external baud rate clock
122       2       SPKRGATE    enable periodic m_speaker output
123       3       SPKRDATA    direct output to m_speaker
124       2       SPKRGATE    enable periodic speaker output
125       3       SPKRDATA    direct output to speaker
124126       4       RFRQGATE    enable refresh and baud rate clocks
125127       5       FDCRESET*   reset 8272
126128       6       TMRIN0      enable 80186 timer 0
r29435r29436
128130
129131   */
130132
133   if (LOG) logerror("ENABLE %02x\n", data);
134
131135   // keyboard enable
132136   m_kb->power_w(BIT(data, 0));
133137
134138   // external baud rate clock
135139   m_extclk = BIT(data, 1);
136140
137   // m_speaker gate
141   // speaker gate
138142   m_pit->write_gate0(BIT(data, 2));
139143
140   // m_speaker data
144   // speaker data
141145   m_spkrdata = BIT(data, 3);
142146   speaker_update();
143147
r29435r29436
146150   m_pit->write_gate2(BIT(data, 4));
147151
148152   // FDC reset
149   if(!BIT(data, 5))
153   if (!BIT(data, 5))
154   {
150155      m_fdc->reset();
156   }
151157
152158   // timer 0 enable
153159   m_maincpu->tmrin0_w(BIT(data, 6));
r29435r29436
173179
174180   */
175181
182   if (LOG) logerror("DMA MUX %02x\n", data);
183
176184   m_dma_mux = data;
177185
178186   // check for DMA error
r29435r29436
228236
229237READ8_MEMBER( tandy2k_state::fldtc_r )
230238{
239   if (LOG) logerror("FLDTC\n");
240
231241   fldtc_w(space, 0, 0);
232242
233243   return 0;
r29435r29436
256266
257267   */
258268
269   if (LOG) logerror("Address Control %02x\n", data);
270
259271   // video access
260272   m_vram_base = data & 0x1f;
261273
r29435r29436
281293
282294   // video source select
283295   m_vidouts = BIT(data, 7);
284
285   logerror("Address Control %02x\n", data);
286296}
287297
288298// Memory Maps
r29435r29436
297307
298308static ADDRESS_MAP_START( tandy2k_io, AS_IO, 16, tandy2k_state )
299309   ADDRESS_MAP_UNMAP_HIGH
300   AM_RANGE(0x00000, 0x00001) AM_READWRITE8(enable_r, enable_w, 0x00ff)
301   AM_RANGE(0x00002, 0x00003) AM_WRITE8(dma_mux_w, 0x00ff)
302   AM_RANGE(0x00004, 0x00005) AM_READWRITE8(fldtc_r, fldtc_w, 0x00ff)
303   AM_RANGE(0x00010, 0x00013) AM_DEVREADWRITE8(I8251A_TAG, i8251_device, data_r, data_w, 0x00ff)
304   AM_RANGE(0x00030, 0x00033) AM_DEVICE8(I8272A_TAG, i8272a_device, map, 0x00ff)
305   AM_RANGE(0x00040, 0x00047) AM_DEVREADWRITE8(I8253_TAG, pit8253_device, read, write, 0x00ff)
306   AM_RANGE(0x00052, 0x00053) AM_READ8(kbint_clr_r, 0x00ff)
307   AM_RANGE(0x00050, 0x00057) AM_DEVREADWRITE8(I8255A_TAG, i8255_device, read, write, 0x00ff)
308   AM_RANGE(0x00060, 0x00063) AM_DEVREADWRITE8(I8259A_0_TAG, pic8259_device, read, write, 0x00ff)
309   AM_RANGE(0x00070, 0x00073) AM_DEVREADWRITE8(I8259A_1_TAG, pic8259_device, read, write, 0x00ff)
310   AM_RANGE(0x00080, 0x00081) AM_DEVREADWRITE8(I8272A_TAG, i8272a_device, mdma_r, mdma_w, 0x00ff)
310   AM_RANGE(0x00000, 0x00001) AM_MIRROR(0x8) AM_READWRITE8(enable_r, enable_w, 0x00ff)
311   AM_RANGE(0x00002, 0x00003) AM_MIRROR(0x8) AM_WRITE8(dma_mux_w, 0x00ff)
312   AM_RANGE(0x00004, 0x00005) AM_MIRROR(0x8) AM_READWRITE8(fldtc_r, fldtc_w, 0x00ff)
313   AM_RANGE(0x00010, 0x00013) AM_MIRROR(0xc) AM_DEVREADWRITE8(I8251A_TAG, i8251_device, data_r, data_w, 0x00ff)
314   AM_RANGE(0x00030, 0x00033) AM_MIRROR(0xc) AM_DEVICE8(I8272A_TAG, i8272a_device, map, 0x00ff)
315   AM_RANGE(0x00040, 0x00047) AM_MIRROR(0x8) AM_DEVREADWRITE8(I8253_TAG, pit8253_device, read, write, 0x00ff)
316   AM_RANGE(0x00052, 0x00053) AM_MIRROR(0x8) AM_READ8(kbint_clr_r, 0x00ff)
317   AM_RANGE(0x00050, 0x00057) AM_MIRROR(0x8) AM_DEVREADWRITE8(I8255A_TAG, i8255_device, read, write, 0x00ff)
318   AM_RANGE(0x00060, 0x00063) AM_MIRROR(0xc) AM_DEVREADWRITE8(I8259A_0_TAG, pic8259_device, read, write, 0x00ff)
319   AM_RANGE(0x00070, 0x00073) AM_MIRROR(0xc) AM_DEVREADWRITE8(I8259A_1_TAG, pic8259_device, read, write, 0x00ff)
320   AM_RANGE(0x00080, 0x00081) AM_MIRROR(0xe) AM_DEVREADWRITE8(I8272A_TAG, i8272a_device, mdma_r, mdma_w, 0x00ff)
311321//  AM_RANGE(0x00100, 0x0017f) AM_DEVREADWRITE8(CRT9007_TAG, crt9007_t, read, write, 0x00ff) AM_WRITE8(addr_ctrl_w, 0xff00)
312322   AM_RANGE(0x00100, 0x0017f) AM_READWRITE(vpac_r, vpac_w)
313323//  AM_RANGE(0x00180, 0x00180) AM_READ8(hires_status_r, 0x00ff)
r29435r29436
516526
517527WRITE_LINE_MEMBER( tandy2k_state::rfrqpulse_w )
518528{
529   // memory refresh counter up
519530}
520531
521532// Intel 8255A Interface
r29435r29436
786797   MCFG_DEVICE_ADD(CRT9021B_TAG, CRT9021, XTAL_16MHz*28/20)
787798   MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
788799
789   MCFG_TIMER_DRIVER_ADD_PERIODIC("vidldsh", tandy2k_state, vidldsh_tick, attotime::from_hz(XTAL_16MHz*28/20/8))
800   MCFG_TIMER_DRIVER_ADD("vidldsh", tandy2k_state, vidldsh_tick)
790801
791802   // sound hardware
792803   MCFG_SPEAKER_STANDARD_MONO("mono")
r29435r29436
806817   MCFG_RS232_PORT_ADD(RS232_TAG, default_rs232_devices, NULL)
807818   MCFG_RS232_RXD_HANDLER(DEVWRITELINE(I8251A_TAG, i8251_device, write_rxd))
808819   MCFG_RS232_DSR_HANDLER(DEVWRITELINE(I8251A_TAG, i8251_device, write_dsr))
820   // TODO pin 15 external transmit clock
821   // TODO pin 17 external receiver clock
809822
810823   MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)
811824   MCFG_PIT8253_CLK0(XTAL_16MHz/16)
812825   MCFG_PIT8253_OUT0_HANDLER(WRITELINE(tandy2k_state, outspkr_w))
813826   MCFG_PIT8253_CLK1(XTAL_16MHz/8)
814827   MCFG_PIT8253_OUT1_HANDLER(WRITELINE(tandy2k_state, intbrclk_w))
815   MCFG_PIT8253_CLK2(XTAL_16MHz/8)
816   MCFG_PIT8253_OUT2_HANDLER(WRITELINE(tandy2k_state, rfrqpulse_w))
828   //MCFG_PIT8253_CLK2(XTAL_16MHz/8)
829   //MCFG_PIT8253_OUT2_HANDLER(WRITELINE(tandy2k_state, rfrqpulse_w))
817830
818831   MCFG_PIC8259_ADD(I8259A_0_TAG, DEVWRITELINE(I80186_TAG, i80186_cpu_device, int0_w), VCC, NULL)
819832

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