MAME SVN History

199869 Revisions

r29425 Tuesday 8th April, 2014 at 00:06:17 UTC by Nathan Woods
Merge branch 'master' of ssh://mess.org/mame into new_menus

[/branches/new_menus/hash]	pico.xml
[/branches/new_menus/src/emu]	digfx.c
[/branches/new_menus/src/emu/bus]	bus.mak
[/branches/new_menus/src/emu/bus/iq151]	video32.c video64.c
[/branches/new_menus/src/emu/bus/rs232]	loopback.c* loopback.h* rs232.c
[/branches/new_menus/src/emu/cpu/h8]	h8_sci.c
[/branches/new_menus/src/emu/imagedev]	bitbngr.h
[/branches/new_menus/src/emu/machine]	hd63450.c netlist.c upd765.c upd765.h
[/branches/new_menus/src/emu/netlist]	nl_base.c nl_base.h nl_dice_compat.h nl_lists.h nl_setup.c pstate.c
[/branches/new_menus/src/emu/netlist/devices]	net_lib.c nld_74107.c nld_system.h
[/branches/new_menus/src/emu/sound]	es5506.c
[/branches/new_menus/src/emu/ui]	imgcntrl.h
[/branches/new_menus/src/emu/video]	crt9007.c
[/branches/new_menus/src/lib]	lib.mak
[/branches/new_menus/src/lib/formats]	tandy2k_dsk.c* tandy2k_dsk.h*
[/branches/new_menus/src/mame]	mame.lst
[/branches/new_menus/src/mame/drivers]	4enlinea.c halleys.c metro.c mystwarr.c pong.c toaplan2.c tourvis.c
[/branches/new_menus/src/mame/video]	c45.c mystwarr.c
[/branches/new_menus/src/mess/drivers]	a7800.c esqkt.c esqmr.c fanucspmg.c pecom.c tandy2k.c x68k.c
[/branches/new_menus/src/mess/includes]	tandy2k.h x68k.h
[/branches/new_menus/src/mess/machine]	a7800.c megacd.c
[/branches/new_menus/src/mess/video]	a7800.c

branches/new_menus/hash/pico.xml
r29424	r29425
2244	2244	</part>
2245	2245	</software>
2246	2246
2247		<software name="oz">
	2247	<software name="oz"> <!-- this only runs in the picou driver, but it's a Japan set, there is an explicit check in the code, are our regions mixed up? -->
2248	2248	<description>Minna de Odorou - Oz no Mahoutsukai (Jpn)</description>
2249	2249	<year>1996</year>
2250	2250	<publisher>Sega</publisher>

branches/new_menus/src/emu/cpu/h8/h8_sci.c
r29424	r29425
125	125
126	126	if(tx_state == ST_IDLE && !(ssr & SSR_TDRE))
127	127	tx_start();
	128
	129	if((scr & SCR_RE) && rx_state == ST_IDLE && !(ssr & (SSR_ORER\|SSR_PER\|SSR_FER)))
	130	rx_start();
128	131	}
129	132
130	133	READ8_MEMBER(h8_sci_device::ssr_r)
r29424	r29425
261	264	ext_clock_counter = 0;
262	265	rx_value = true;
263	266	clk_cb(clock_value);
	267	tx_cb(1);
264	268	cur_sync_time = attotime::never;
265	269	}
266	270
r29424	r29425
558	562	tx_state = ST_IDLE;
559	563	tx_bit = 0;
560	564	clock_stop(CLK_TX);
	565	tx_cb(1);
561	566	ssr \|= SSR_TEND;
562	567	if(scr & SCR_TEIE)
563	568	intc->internal_interrupt(tei_int);

branches/new_menus/src/emu/video/crt9007.c
r29424	r29425
398	398
399	399	inline void crt9007_t::recompute_parameters()
400	400	{
	401	#ifdef UNUSED_FOR_NOW
401	402	// check that necessary registers have been loaded
402	403	if (!HAS_VALID_PARAMETERS) return;
403	404
r29424	r29425
441	442	m_vsync_timer->adjust(m_screen->time_until_pos(0, 0));
442	443	m_vlt_timer->adjust(m_screen->time_until_pos(0, m_vlt_start), 1);
443	444	m_drb_timer->adjust(m_screen->time_until_pos(0, 0));
	445	#endif
444	446	}
445	447
446	448

branches/new_menus/src/emu/sound/es5506.c
r29424	r29425
230	230	m_irqv = 0x80;
231	231	m_channels = channels;
232	232
	233	/* KT-76 assumes all voices are active on an ES5506 without setting them! */
	234	m_active_voices = 31;
	235	m_sample_rate = m_master_clock / (16 * (m_active_voices + 1));
	236	m_stream->set_sample_rate(m_sample_rate);
	237
233	238	/* compute the tables */
234	239	compute_tables();
235	240

branches/new_menus/src/emu/bus/iq151/video32.c
r29424	r29425
40	40	GFXDECODE_END
41	41
42	42	static MACHINE_CONFIG_FRAGMENT( video32 )
43		MCFG_GFXDECODE_ADD("gfxdecode", ":palette", video32)
	43	MCFG_GFXDECODE_ADD("gfxdecode", "^^palette", video32)
44	44	MACHINE_CONFIG_END
45	45
46	46	//**************************************************************************

branches/new_menus/src/emu/bus/iq151/video64.c
r29424	r29425
40	40	GFXDECODE_END
41	41
42	42	static MACHINE_CONFIG_FRAGMENT( video64 )
43		MCFG_GFXDECODE_ADD("gfxdecode", ":palette", video64)
	43	MCFG_GFXDECODE_ADD("gfxdecode", "^^palette", video64)
44	44	MACHINE_CONFIG_END
45	45
46	46	//**************************************************************************

branches/new_menus/src/emu/bus/bus.mak
r29424	r29425
703	703	ifneq ($(filter RS232,$(BUSES)),)
704	704	OBJDIRS += $(BUSOBJ)/rs232
705	705	BUSOBJS += $(BUSOBJ)/rs232/keyboard.o
	706	BUSOBJS += $(BUSOBJ)/rs232/loopback.o
706	707	BUSOBJS += $(BUSOBJ)/rs232/null_modem.o
707	708	BUSOBJS += $(BUSOBJ)/rs232/rs232.o
708	709	BUSOBJS += $(BUSOBJ)/rs232/ser_mouse.o

branches/new_menus/src/emu/bus/rs232/loopback.h
r0	r29425
	1	// license:MAME
	2	// copyright-holders:smf
	3
	4	#ifndef RS232_LOOPBACK_H_
	5	#define RS232_LOOPBACK_H_
	6
	7	#include "bus/rs232/rs232.h"
	8
	9	class rs232_loopback_device : public device_t,
	10	public device_rs232_port_interface
	11	{
	12	public:
	13	rs232_loopback_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	14
	15	virtual WRITE_LINE_MEMBER( input_txd );
	16	virtual WRITE_LINE_MEMBER( input_rts );
	17	virtual WRITE_LINE_MEMBER( input_dtr );
	18
	19	protected:
	20	virtual void device_start();
	21	};
	22
	23	extern const device_type RS232_LOOPBACK;
	24
	25	#endif

Property changes on: branches/new_menus/src/emu/bus/rs232/loopback.h
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branches/new_menus/src/emu/bus/rs232/loopback.c
r0	r29425
	1	// license:MAME
	2	// copyright-holders:smf
	3
	4	#include "loopback.h"
	5
	6	const device_type RS232_LOOPBACK = &device_creator<rs232_loopback_device>;
	7
	8	rs232_loopback_device::rs232_loopback_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	9	: device_t(mconfig, RS232_LOOPBACK, "RS232 Loopback", tag, owner, clock, "rs232_loopback", __FILE__),
	10	device_rs232_port_interface(mconfig, *this)
	11	{
	12	}
	13
	14	void rs232_loopback_device::device_start()
	15	{
	16	}
	17
	18	WRITE_LINE_MEMBER( rs232_loopback_device::input_txd )
	19	{
	20	if (started())
	21	{
	22	output_rxd(state);
	23	}
	24	}
	25
	26	WRITE_LINE_MEMBER( rs232_loopback_device::input_rts )
	27	{
	28	if (started())
	29	{
	30	output_ri(state);
	31	output_cts(state);
	32	}
	33	}
	34
	35	WRITE_LINE_MEMBER( rs232_loopback_device::input_dtr )
	36	{
	37	if (started())
	38	{
	39	output_dsr(state);
	40	output_dcd(state);
	41	}
	42	}

Property changes on: branches/new_menus/src/emu/bus/rs232/loopback.c
Added: svn:mime-type + text/plain Added: svn:eol-style + native

branches/new_menus/src/emu/bus/rs232/rs232.c
r29424	r29425
96	96	{
97	97	}
98	98
	99	#include "loopback.h"
99	100	#include "null_modem.h"
100	101	#include "terminal.h"
101	102
102	103	SLOT_INTERFACE_START( default_rs232_devices )
	104	SLOT_INTERFACE("loopback", RS232_LOOPBACK)
	105	SLOT_INTERFACE("null_modem", NULL_MODEM)
103	106	SLOT_INTERFACE("serial_terminal", SERIAL_TERMINAL)
104		SLOT_INTERFACE("null_modem", NULL_MODEM)
105	107	SLOT_INTERFACE_END

branches/new_menus/src/emu/ui/imgcntrl.h
r29424	r29425
42	42	private:
43	43	// instance variables
44	44	bool create_confirmed;
45		bool softlist_done;
	45	//bool softlist_done;
46	46	const software_info *swi;
47	47	const software_part *swp;
48	48	class software_list_device *sld;

branches/new_menus/src/emu/imagedev/bitbngr.h
r29424	r29425
24	24	BITBANGER_4800,
25	25	BITBANGER_9600,
26	26	BITBANGER_14400,
	27	BITBANGER_19200,
27	28	BITBANGER_28800,
28	29	BITBANGER_38400,
29	30	BITBANGER_57600,

branches/new_menus/src/emu/machine/netlist.c
r29424	r29425
403	403	LOG_DEV_CALLS(("device_post_load\n"));
404	404
405	405	netlist().post_load();
	406	netlist().rebuild_lists();
406	407	}
407	408
408	409	ATTR_COLD void netlist_mame_device_t::device_pre_save()

branches/new_menus/src/emu/machine/upd765.c
r29424	r29425
101	101	upd765_family_device::upd765_family_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source) :
102	102	pc_fdc_interface(mconfig, type, name, tag, owner, clock, shortname, source),
103	103	intrq_cb(*this),
104		drq_cb(*this)
	104	drq_cb(*this),
	105	hdl_cb(*this)
105	106	{
106	107	ready_polled = true;
107	108	ready_connected = true;
108	109	select_connected = true;
109	110	external_ready = false;
	111	no_poll_irq = false;
110	112	dor_reset = 0x00;
111	113	mode = MODE_AT;
112	114	}
r29424	r29425
128	130
129	131	void upd765_family_device::device_start()
130	132	{
131		intrq_cb.resolve();
132		drq_cb.resolve();
	133	intrq_cb.resolve_safe();
	134	drq_cb.resolve_safe();
	135	hdl_cb.resolve_safe();
133	136
134	137	for(int i=0; i != 4; i++) {
135	138	char name[2];
r29424	r29425
441	444	{
442	445	if(state != drq) {
443	446	drq = state;
444		if(!drq_cb.isnull())
445		drq_cb(drq);
	447	drq_cb(drq);
446	448	}
447	449	}
448	450
r29424	r29425
1441	1443
1442	1444	if(fi.dev)
1443	1445	fi.dev->ss_w(command[1] & 4 ? 1 : 0);
	1446	hdl_cb(1);
1444	1447	read_data_continue(fi);
1445	1448	}
1446	1449
r29424	r29425
1618	1621	st1 = ST1_MA;
1619	1622	st2 = 0x00;
1620	1623
	1624	hdl_cb(1);
1621	1625	write_data_continue(fi);
1622	1626	}
1623	1627
r29424	r29425
1726	1730
1727	1731	if(fi.dev)
1728	1732	fi.dev->ss_w(command[1] & 4 ? 1 : 0);
	1733	hdl_cb(1);
1729	1734	read_track_continue(fi);
1730	1735	}
1731	1736
r29424	r29425
1840	1845	fi.dev->ss_w(command[1] & 4 ? 1 : 0);
1841	1846	sector_size = calc_sector_size(command[2]);
1842	1847
	1848	hdl_cb(1);
1843	1849	format_track_continue(fi);
1844	1850	}
1845	1851
r29424	r29425
1902	1908	for(int i=0; i<4; i++)
1903	1909	cur_live.idbuf[i] = 0x00;
1904	1910
	1911	hdl_cb(1);
1905	1912	read_id_continue(fi);
1906	1913	}
1907	1914
r29424	r29425
1954	1961	bool old_irq = cur_irq;
1955	1962	cur_irq = data_irq \|\| other_irq \|\| internal_drq;
1956	1963	cur_irq = cur_irq && (dor & 4) && (mode != MODE_AT \|\| (dor & 8));
1957		if(cur_irq != old_irq ~~&& !intrq_cb.isnull()~~) {
	1964	if(cur_irq != old_irq) {
1958	1965	logerror("%s: irq = %d\n", tag(), cur_irq);
1959	1966	intrq_cb(cur_irq);
1960	1967	}
r29424	r29425
2018	2025	if(!flopi[fid].st0_filled) {
2019	2026	flopi[fid].st0 = ST0_ABRT \| fid;
2020	2027	flopi[fid].st0_filled = true;
2021		other_irq = true;
	2028	if(!no_poll_irq)
	2029	other_irq = true;
2022	2030	}
2023	2031	}
2024	2032	}
r29424	r29425
2225	2233	upd72065_device::upd72065_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) : upd765_family_device(mconfig, UPD72065, "UPD72065", tag, owner, clock, "upd72065", __FILE__)
2226	2234	{
2227	2235	dor_reset = 0x0c;
	2236	no_poll_irq = true;
2228	2237	}
2229	2238
2230	2239	smc37c78_device::smc37c78_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) : upd765_family_device(mconfig, SMC37C78, "SMC37C78", tag, owner, clock, "smc37c78", __FILE__)

branches/new_menus/src/emu/machine/upd765.h
r29424	r29425
61	61	#define MCFG_UPD765_DRQ_CALLBACK(_write) \
62	62	devcb = &upd765_family_device::set_drq_wr_callback(*device, DEVCB2_##_write);
63	63
	64	#define MCFG_UPD765_HDL_CALLBACK(_write) \
	65	devcb = &upd765_family_device::set_hdl_wr_callback(*device, DEVCB2_##_write);
	66
64	67	/* Interface required for PC ISA wrapping */
65	68	class pc_fdc_interface : public device_t {
66	69	public:
r29424	r29425
91	94
92	95	template<class _Object> static devcb2_base &set_intrq_wr_callback(device_t &device, _Object object) { return downcast<upd765_family_device &>(device).intrq_cb.set_callback(object); }
93	96	template<class _Object> static devcb2_base &set_drq_wr_callback(device_t &device, _Object object) { return downcast<upd765_family_device &>(device).drq_cb.set_callback(object); }
	97	template<class _Object> static devcb2_base &set_hdl_wr_callback(device_t &device, _Object object) { return downcast<upd765_family_device &>(device).hdl_cb.set_callback(object); }
94	98
95	99	virtual DECLARE_ADDRESS_MAP(map, 8) = 0;
96	100
r29424	r29425
298	302
299	303	bool ready_connected, ready_polled, select_connected;
300	304
301		bool external_ready;
	305	bool external_ready, no_poll_irq;
302	306
303	307	int mode;
304	308	int main_phase;
305	309
306	310	live_info cur_live, checkpoint_live;
307		devcb2_write_line intrq_cb, drq_cb;
	311	devcb2_write_line intrq_cb, drq_cb, hdl_cb;
308	312	bool cur_irq, other_irq, data_irq, drq, internal_drq, tc, tc_done, locked, mfm;
309	313	floppy_info flopi[4];
310	314

branches/new_menus/src/emu/machine/hd63450.c
r29424	r29425
269	269	m_timer[channel]->adjust(attotime::from_usec(500), channel, m_our_clock[channel]);
270	270	else if((m_reg[channel].ocr & 3) == 3)
271	271	m_timer[channel]->adjust(attotime::from_usec(500), channel, attotime::never);
	272	else if((m_reg[channel].ocr & 3) == 2)
	273	m_timer[channel]->adjust(attotime::never, channel, attotime::never);
272	274
273	275	m_transfer_size[channel] = m_reg[channel].mtc;
274	276
r29424	r29425
284	286
285	287	TIMER_CALLBACK_MEMBER(hd63450_device::dma_transfer_timer)
286	288	{
	289	if((m_reg[param].ocr & 3) == 2)
	290	return;
287	291	single_transfer(param);
288	292	}
289	293

branches/new_menus/src/emu/netlist/nl_base.h
r29424	r29425
625	625
626	626	ATTR_HOT void solve();
627	627
	628	netlist_list_t<netlist_core_terminal_t *> m_registered; // save post-start m_list ...
628	629	plinked_list<netlist_core_terminal_t> m_list;
629	630
	631	ATTR_COLD void rebuild_list(); /* rebuild m_list after a load */
	632
630	633	protected: //FIXME: needed by current solver code
631	634
632	635	UINT16 m_num_cons;
r29424	r29425
1029	1032	ATTR_HOT void process_queue(const netlist_time delta);
1030	1033	ATTR_HOT inline void abort_current_queue_slice() { m_stop = netlist_time::zero; }
1031	1034
	1035	ATTR_COLD void rebuild_lists(); /* must be called after post_load ! */
	1036
1032	1037	ATTR_COLD void set_setup(netlist_setup_t *asetup) { m_setup = asetup; }
1033	1038	ATTR_COLD netlist_setup_t &setup() { return *m_setup; }
1034	1039

branches/new_menus/src/emu/netlist/nl_setup.c
r29424	r29425
17	17	static NETLIST_START(base)
18	18	TTL_INPUT(ttlhigh, 1)
19	19	TTL_INPUT(ttllow, 0)
20		GND()
	20	NET_REGISTER_DEV(gnd, GND)
21	21
22	22	INCLUDE(diode_models);
23	23	INCLUDE(bjt_models);
r29424	r29425
45	45
46	46	netlist_setup_t::~netlist_setup_t()
47	47	{
48		m_links.re~~set~~();
	48	m_links.clear();
49	49	m_alias.reset();
50	50	m_params.reset();
51	51	m_terminals.reset();
r29424	r29425
614	614
615	615	netlist().log("deleting empty nets ...");
616	616
617		// delete empty nets ...
	617	// delete empty nets ... and save m_list ...
618	618
619	619	netlist_net_t::list_t todelete;
620	620
r29424	r29425
624	624	{
625	625	todelete.add(*pn);
626	626	}
	627	else
	628	{
	629	for (netlist_core_terminal_t p = (pn)->m_list.first(); p != NULL; p = (*pn)->m_list.next(p))
	630	(*pn)->m_registered.add(p);
	631	}
627	632	}
628	633
629	634	for (int i=0; i < todelete.count(); i++)

branches/new_menus/src/emu/netlist/nl_lists.h
r29424	r29425
130	130	ATTR_HOT inline const _ListClass *last() const { return &m_list[m_count -1]; }
131	131	ATTR_HOT inline int count() const { return m_count; }
132	132	ATTR_HOT inline bool empty() const { return (m_count == 0); }
133		ATTR_HOT inline void re~~set~~() { m_count = 0; }
	133	ATTR_HOT inline void clear() { m_count = 0; }
134	134	ATTR_HOT inline int capacity() const { return m_num_elements; }
135	135
136		ATTR_COLD void re~~set~~_and_free()
	136	ATTR_COLD void clear_and_free()
137	137	{
138	138	for (_ListClass *i = m_list; i < m_list + m_count; i++)
139	139	{
140	140	delete *i;
141	141	}
142		re~~set~~();
	142	clear();
143	143	}
144	144
145	145	ATTR_HOT inline _ListClass& operator[](const int & index) { return m_list[index]; }

branches/new_menus/src/emu/netlist/pstate.c
r29424	r29425
7	7
8	8	ATTR_COLD pstate_manager_t::~pstate_manager_t()
9	9	{
10		m_save.re~~set~~_and_free();
	10	m_save.clear_and_free();
11	11	}
12	12
13	13
r29424	r29425
44	44	{
45	45	m_save.remove(todelete[i]);
46	46	}
47		todelete.re~~set~~_and_free();
	47	todelete.clear_and_free();
48	48	}
49	49
50	50	ATTR_COLD void pstate_manager_t::pre_save()

branches/new_menus/src/emu/netlist/devices/net_lib.c
r29424	r29425
78	78	net_device_t_base_factory p = e;
79	79	delete p;
80	80	}
81		m_list.re~~set~~();
	81	m_list.clear();
82	82	}
83	83
84	84	void netlist_factory_t::initialize()

branches/new_menus/src/emu/netlist/devices/nld_74107.c
r29424	r29425
57	57	{
58	58	const netlist_sig_t t = m_Q.net().Q();
59	59	newstate((!t & m_Q1) \| (t & m_Q2) \| m_F);
60		if (!m_Q1)
	60	if (UNEXPECTED(m_Q1 ^ 1))
61	61	m_clk.inactivate();
62	62	}
63	63

branches/new_menus/src/emu/netlist/devices/nld_system.h
r29424	r29425
33	33	NET_REGISTER_DEV(clock, _name) \
34	34	PARAM(_name.FREQ, _freq)
35	35
36		#define GND() \
	36	#define GNDA() \
37	37	NET_REGISTER_DEV(gnd, GND)
38	38
39	39	// ----------------------------------------------------------------------------------------

branches/new_menus/src/emu/netlist/nl_base.c
r29424	r29425
148	148	}
149	149	}
150	150
151		m_nets.re~~set~~();
	151	m_nets.clear();
152	152
153	153	tagmap_free_entries<tagmap_devices_t>(m_devices);
154	154
r29424	r29425
200	200	return NULL;
201	201	}
202	202
	203	ATTR_COLD void netlist_base_t::rebuild_lists()
	204	{
	205	for (int i = 0; i < m_nets.count(); i++)
	206	m_nets[i]->rebuild_list();
	207	}
	208
	209
203	210	ATTR_COLD void netlist_base_t::reset()
204	211	{
205	212	m_time = netlist_time::zero;
r29424	r29425
537	544	}
538	545	}
539	546
	547	ATTR_COLD void netlist_net_t::rebuild_list()
	548	{
	549	/* rebuild m_list */
540	550
	551	m_list.clear();
	552	for (int i=0; i < m_registered.count(); i++)
	553	if (m_registered[i]->state() != netlist_input_t::STATE_INP_PASSIVE)
	554	m_list.add(*m_registered[i]);
	555	}
	556
541	557	ATTR_COLD void netlist_net_t::reset()
542	558	{
543	559	m_last_Analog = 0.0;
r29424	r29425
550	566	m_active = 0;
551	567	m_in_queue = 2;
552	568
	569	/* rebuild m_list */
	570
	571	m_list.clear();
	572	for (int i=0; i < m_registered.count(); i++)
	573	m_list.add(*m_registered[i]);
	574
553	575	for (netlist_core_terminal_t *t = m_list.first(); t != NULL; t = m_list.next(t))
554	576	{
555	577	t->do_reset();

branches/new_menus/src/emu/netlist/nl_dice_compat.h
r29424	r29425
13	13	* -------------------------------------------------------------------- */
14	14
15	15	//#define CHIP(_n, _t) netlist.register_dev(NET_NEW(_t ## _dip), _n);
16		#define CHIP(_n, _t) net~~list~~.register_dev( new nld_ ## _t ## _dip(), _n);
	16	#define CHIP(_n, _t) setup.register_dev( new nld_ ## _t ## _dip(), _n);
17	17
18	18	#define CONNECTION( a... ) CONNECTIONX( a )
19		#define CONNECTIONX(_a, _b, _c, _d) netlist.register_link(_a "." # _b, _c "." # _d);
20		#define NET_CSTR(_a, _b) netlist.register_link( _a, _b);
	19	#define CONNECTIONX(_a, _b, _c, _d) setup.register_link(_a "." # _b, _c "." # _d);
	20	#define NET_CSTR(_a, _b) setup.register_link( _a, _b);
21	21
22	22	#define CIRCUIT_LAYOUT(x) NETLIST_START(x)
23	23	#define CIRCUIT_LAYOUT_END NETLIST_END()

branches/new_menus/src/emu/digfx.c
r29424	r29425
80	80
81	81	// find our palette device, either as a sibling device or subdevice
82	82	if (m_palette_is_sibling)
83		m_palette = device().sib~~ling~~device<palette_device>(m_palette_tag);
	83	m_palette = device().owner()->subdevice<palette_device>(m_palette_tag);
84	84	else
85	85	m_palette = device().subdevice<palette_device>(m_palette_tag);
86	86
r29424	r29425
301	301	{
302	302	palette_device *palette;
303	303	if (m_palette_is_sibling)
304		palette = device().sib~~ling~~device<palette_device>(m_palette_tag);
	304	palette = device().owner()->subdevice<palette_device>(m_palette_tag);
305	305	else
306	306	palette = device().subdevice<palette_device>(m_palette_tag);
307	307

branches/new_menus/src/lib/formats/tandy2k_dsk.c
r0	r29425
	1	// license:BSD-3-Clause
	2	// copyright-holders:Curt Coder
	3	/*********************************************************************
	4
	5	formats/tandy2k_dsk.c
	6
	7	Tandy 2000 disk format
	8
	9	*********************************************************************/
	10
	11	#include "emu.h"
	12	#include "formats/tandy2k_dsk.h"
	13
	14	tandy2k_format::tandy2k_format() : upd765_format(formats)
	15	{
	16	}
	17
	18	const char *tandy2k_format::name() const
	19	{
	20	return "tandy2k";
	21	}
	22
	23	const char *tandy2k_format::description() const
	24	{
	25	return "Tandy 2000 disk image";
	26	}
	27
	28	const char *tandy2k_format::extensions() const
	29	{
	30	return "dsk";
	31	}
	32
	33	const tandy2k_format::format tandy2k_format::formats[] = {
	34	{ // 720K 5.25 inch quad density - gaps unverified
	35	floppy_image::FF_525, floppy_image::DSQD, floppy_image::MFM,
	36	2000, 9, 80, 2, 512, {}, 1, {}, 80, 50, 22, 80
	37	},
	38	{}
	39	};
	40
	41	const floppy_format_type FLOPPY_TANDY_2000_FORMAT = &floppy_image_format_creator<tandy2k_format>;

Property changes on: branches/new_menus/src/lib/formats/tandy2k_dsk.c
Added: svn:mime-type + text/plain Added: svn:eol-style + native

branches/new_menus/src/lib/formats/tandy2k_dsk.h
r0	r29425
	1	// license:BSD-3-Clause
	2	// copyright-holders:Curt Coder
	3	/*********************************************************************
	4
	5	formats/tandy2k_dsk.h
	6
	7	Tandy 2000 disk format
	8
	9	*********************************************************************/
	10
	11	#ifndef BW2_DSK_H_
	12	#define BW2_DSK_H_
	13
	14	#include "upd765_dsk.h"
	15
	16	class tandy2k_format : public upd765_format {
	17	public:
	18	tandy2k_format();
	19
	20	virtual const char *name() const;
	21	virtual const char *description() const;
	22	virtual const char *extensions() const;
	23
	24	private:
	25	static const format formats[];
	26	};
	27
	28	extern const floppy_format_type FLOPPY_TANDY_2000_FORMAT;
	29
	30	#endif

Property changes on: branches/new_menus/src/lib/formats/tandy2k_dsk.h
Added: svn:mime-type + text/plain Added: svn:eol-style + native

branches/new_menus/src/lib/lib.mak
r29424	r29425
192	192	$(LIBOBJ)/formats/st_dsk.o \
193	193	$(LIBOBJ)/formats/svi_cas.o \
194	194	$(LIBOBJ)/formats/svi_dsk.o \
	195	$(LIBOBJ)/formats/tandy2k_dsk.o \
195	196	$(LIBOBJ)/formats/td0_dsk.o \
196	197	$(LIBOBJ)/formats/thom_cas.o \
197	198	$(LIBOBJ)/formats/thom_dsk.o \

branches/new_menus/src/mess/includes/x68k.h
r29424	r29425
9	9	#ifndef X68K_H_
10	10	#define X68K_H_
11	11
	12	#include "cpu/m68000/m68000.h"
12	13	#include "machine/hd63450.h"
13	14	#include "machine/rp5c15.h"
14	15	#include "machine/upd765.h"
r29424	r29425
58	59	m_gvram32(*this, "gvram32"),
59	60	m_tvram32(*this, "tvram32") { }
60	61
61		required_device<~~cpu~~_device> m_maincpu;
	62	required_device<m68000_base_device> m_maincpu;
62	63	required_device<okim6258_device> m_okim6258;
63	64	required_device<hd63450_device> m_hd63450;
64	65	required_device<ram_device> m_ram;
r29424	r29425
327	328
328	329	protected:
329	330	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	331	void set_bus_error(UINT32 address, bool write, UINT16 mem_mask);
	332	bool m_bus_error;
330	333	};
331	334
332	335

branches/new_menus/src/mess/includes/tandy2k.h
r29424	r29425
8	8	#include "bus/rs232/rs232.h"
9	9	#include "cpu/i86/i186.h"
10	10	#include "cpu/mcs48/mcs48.h"
	11	#include "formats/tandy2k_dsk.h"
11	12	#include "imagedev/harddriv.h"
12	13	#include "machine/i8255.h"
13	14	#include "machine/i8251.h"
r29424	r29425
125	126	optional_shared_ptr<UINT8> m_char_ram;
126	127
127	128	virtual void machine_start();
	129	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
128	130
129	131	void update_drq();
130	132	void dma_request(int line, int state);
r29424	r29425
160	162	DECLARE_WRITE_LINE_MEMBER( kbdclk_w );
161	163	DECLARE_WRITE_LINE_MEMBER( kbddat_w );
162	164	DECLARE_READ8_MEMBER( irq_callback );
163		DECLARE_WRITE_LINE_MEMBER( fdc_drq );
	165	DECLARE_WRITE_LINE_MEMBER( fdc_drq_w );
	166	DECLARE_WRITE_LINE_MEMBER( fdc_hdl_w );
164	167	DECLARE_WRITE_LINE_MEMBER(write_centronics_ack);
165	168	DECLARE_WRITE_LINE_MEMBER(write_centronics_busy);
166	169	DECLARE_WRITE_LINE_MEMBER(write_centronics_perror);
r29424	r29425
168	171	DECLARE_WRITE_LINE_MEMBER(write_centronics_fault);
169	172	CRT9021_DRAW_CHARACTER_MEMBER( vac_draw_character );
170	173	TIMER_DEVICE_CALLBACK_MEMBER( vidldsh_tick );
	174	DECLARE_FLOPPY_FORMATS( floppy_formats );
171	175
172	176	enum
173	177	{

branches/new_menus/src/mess/video/a7800.c
r29424	r29425
127	127	int maria_cycles;
128	128
129	129	if ( m_maria_offset == 0 )
130		maria_cycles = 5+19; // DMA startup + last line shutdown
	130	maria_cycles = 5+21; // DMA startup + last line shutdown
131	131	else
132		maria_cycles = 5+13; // DMA startup + other line shutdown
	132	maria_cycles = 5+16; // DMA startup + other line shutdown
133	133
134	134	cells = 0;
135	135
r29424	r29425
286	286	m_maria_holey = (READ_MEM(m_maria_dll) & 0x60) >> 5;
287	287	m_maria_nmi = READ_MEM(m_maria_dll) & 0x80;
288	288	/* logerror("DLL=%x\n",m_maria_dll); */
	289	maria_draw_scanline();
289	290	}
290	291
291	292
292		if( ( frame_scanline > 15 ) && (frame_scanline < (m_lines - 5)) && m_maria_dmaon )
	293	if( ( frame_scanline > 16 ) && (frame_scanline < (m_lines - 5)) && m_maria_dmaon )
293	294	{
294	295	maria_draw_scanline();
295	296

branches/new_menus/src/mess/drivers/esqkt.c
r29424	r29425
18	18	0x280000-0x2801FF ES5510
19	19	0x300000-0x30000F 68681 DUART
20	20	0xFF0000-0xFFFFFF OS RAM
	21
	22	Ensoniq KT-76
	23	Ensoniq 1994
21	24
	25	This is a wavetable-based synth keyboard made by Ensoniq in 1994
	26
	27	PCB Layout
	28	----------
	29
	30	KT-76
	31	\|---------------------------------------------\|
	32	\|J12 J3 J11 J10 \|
	33	\| LM393 LM358\|
	34	\| 74HC4051\|
	35	\|ADM691 \|
	36	\| 62256 \|
	37	\| \|
	38	\|3V_BATTERY KT76_0590_LO.U5 ROM0 \|
	39	\| \|
	40	\| 68EC020 62256 OTTOR2 ROM1 \|
	41	\| \|
	42	\| KT76_690B_HI.U6 ROM2 \|
	43	\| PAL1 \|
	44	\| HP_6N138 \|
	45	\| PAL2 OTTOR2 J6\|
	46	\| 7407 \|
	47	\| \|
	48	\| D41464 D41464 \|
	49	\| \|
	50	\| SCN2681 D41464 D41464 \|
	51	\| 137000402 \|
	52	\| \|
	53	\| 18.432MHz \|
	54	\| ESPR6 16MHz \|
	55	\| POT \|
	56	\| R1136-11 \|
	57	\| \|
	58	\| LM339 LM339 \|
	59	\| J13 J5 J1 J2 J4 \|
	60	\|---------------------------------------------\|
	61	Notes:
	62	J1 - connector for digital jacks
	63	J2 - connector for keyboard
	64	J3 - connector for LCD display
	65	J4 - connector for keyboard
	66	J5 - connector for power input
	67	J6 - connector for wave expansion
	68	J10 - connector for wheels/pressure
	69	J11 - connector for memory card
	70	J12 - connector for headphones
	71	J13 - connector for analog jacks
	72	68EC020 - Motorola MC68EC020FG16 CPU. Clock input 16MHz
	73	1370000402 - Unknown PLCC44 IC stamped with the Ensoniq logo. Likely CPLD or gate array.
	74	ESPR6 - Ensoniq ESPR6 (ES5510) sound chip
	75	OTTOR2 - Ensoniq OTTOR2 (ES5506) sound chip
	76	POT - ESP adjustment pot
	77	KT76* - 27C2048/27C210 EPROM
	78	ROM* - 2M x8-bit SOP44 mask ROM
	79	R1136-11 - DIP40 IC manufactured by Rockwell - believed to be some type of MCU.
	80	D41464 - NEC D41464 64k x4-bit DRAM
	81	62256 - 32k x8-bit SRAM
	82	SCN2681 - Philips SCN2681 Dual Universal Asynchronous Receiver/Transmitter (DUART)
	83	HP_6N138 - HP/Agilent HP 6N138 Low Input Current High Gain Optocoupler
	84	PAL1 - MMI PAL20L8ACN stamped 'KT-76 MMU 6A0A'. Printing is faint so 0 could be a B or a D.
	85	PAL2 - MMI PAL20L8ACN stamped 'KT-76 BCU 73D6'
	86
22	87	***************************************************************************/
23	88
24	89	#include "bus/midi/midi.h"
r29424	r29425
48	113
49	114	virtual void machine_reset();
50	115
51		DECLARE_READ32_MEMBER(lower_r);
52		DECLARE_WRITE32_MEMBER(lower_w);
53
54	116	DECLARE_WRITE_LINE_MEMBER(duart_irq_handler);
55	117	DECLARE_WRITE_LINE_MEMBER(duart_tx_a);
56	118	DECLARE_WRITE_LINE_MEMBER(duart_tx_b);
r29424	r29425
74	136	m_bCalibSecondByte = false;
75	137	}
76	138
77		READ32_MEMBER(esqkt_state::lower_r)
78		{
79		offset &= 0x3fff;
80
81		// get pointers when 68k resets
82		if (!m_rom)
83		{
84		m_rom = (UINT32 *)memregion("osrom")->base();
85		m_ram = (UINT32 *)memshare("osram")->ptr();
86		}
87
88		if (offset < 0x2000)
89		{
90		if (m68k_get_fc(m_maincpu) == 0x6) // supervisor mode = ROM
91		{
92		return m_rom[offset];
93		}
94		else
95		{
96		return m_ram[offset];
97		}
98		}
99		else
100		{
101		return m_ram[offset];
102		}
103		}
104
105		WRITE32_MEMBER(esqkt_state::lower_w)
106		{
107		offset &= 0x3fff;
108
109		if (offset < 0x2000)
110		{
111		if (m68k_get_fc(m_maincpu) != 0x6) // if not supervisor mode, RAM
112		{
113		COMBINE_DATA(&m_ram[offset]);
114		}
115		else
116		{
117		logerror("Write to ROM: %x @ %x (fc=%x)\n", data, offset, m68k_get_fc(m_maincpu));
118		}
119		}
120		else
121		{
122		COMBINE_DATA(&m_ram[offset]);
123		}
124		}
125
126	139	static ADDRESS_MAP_START( kt_map, AS_PROGRAM, 32, esqkt_state )
127	140	AM_RANGE(0x000000, 0x07ffff) AM_ROM AM_REGION("osrom", 0)
128	141	AM_RANGE(0x200000, 0x20003f) AM_DEVREADWRITE8("ensoniq", es5506_device, read, write, 0xffffffff)
r29424	r29425
233	246	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
234	247	MCFG_SOUND_ADD("ensoniq", ES5506, XTAL_16MHz)
235	248	MCFG_SOUND_CONFIG(es5506_config)
236		MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
237		MCFG_SOUND_ROUTE(1, "rspeaker", 2.0)
	249	MCFG_SOUND_ROUTE(0, "lspeaker", 0.5)
	250	MCFG_SOUND_ROUTE(1, "rspeaker", 0.5)
238	251	MCFG_SOUND_ADD("ensoniq2", ES5506, XTAL_16MHz)
239	252	MCFG_SOUND_CONFIG(es5506_2_config)
240		MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
241		MCFG_SOUND_ROUTE(1, "rspeaker", 2.0)
	253	MCFG_SOUND_ROUTE(0, "lspeaker", 0.5)
	254	MCFG_SOUND_ROUTE(1, "rspeaker", 0.5)
242	255	MACHINE_CONFIG_END
243	256
244	257	static INPUT_PORTS_START( kt )
r29424	r29425
249	262	ROM_LOAD32_WORD( "kt76_162_lo.bin", 0x000000, 0x020000, CRC(1a1ab910) SHA1(dcc80db2297fd25993e090c2e5bb7f947319a8bf) )
250	263	ROM_LOAD32_WORD( "kt76_162_hi.bin", 0x000002, 0x040000, CRC(de16d236) SHA1(c55fca86453e90e8c34a048bed45817063237370) )
251	264
252		ROM_REGION(0x200000, "waverom", ROMREGION_ERASE00)
253		ROM_REGION(0x200000, "waverom2", ROMREGION_ERASE00)
254		ROM_REGION(0x200000, "waverom3", ROMREGION_ERASE00)
	265	ROM_REGION(0x400000, "waverom", ROMREGION_ERASE00)
	266	ROM_LOAD16_BYTE( "1351000401_rom0.u103", 0x000001, 0x200000, CRC(425047af) SHA1(9680d1fc222b29ba24f0fbf6136982bee87a60ef) )
	267
	268	ROM_REGION(0x400000, "waverom2", ROMREGION_ERASE00)
	269	ROM_LOAD16_BYTE( "1351000402_rom1.u102", 0x000001, 0x200000, CRC(64459185) SHA1(0fa20b16847fc02a384057fc3d385226eb3e7527) )
	270
	271	ROM_REGION(0x400000, "waverom3", ROMREGION_ERASE00)
	272	ROM_LOAD16_BYTE( "1351000403_rom2.u104", 0x000001, 0x200000, CRC(c2aacc5d) SHA1(7fab518ba92ddb23cdc4dcb04751b26d25c298c0) )
	273
255	274	ROM_REGION(0x200000, "waverom4", ROMREGION_ERASE00)
256	275	ROM_END
257	276
r29424	r29425
260	279	m_duart_io = 0;
261	280	}
262	281
263		CONS( 1996, kt76, 0, 0, kt, kt, esqkt_state, kt, "Ensoniq", "KT-76", GAME_NOT_WO~~RKI~~NG )
	282	CONS( 1996, kt76, 0, 0, kt, kt, esqkt_state, kt, "Ensoniq", "KT-76", GAME_IMPERFECT_SOUND )

branches/new_menus/src/mess/drivers/pecom.c
r29424	r29425
206	206	ROM_LOAD( "090786.bin", 0x8000, 0x4000, CRC(b3b1ea23) SHA1(de69f22568161ced801973345fa39d6d207b9e8c) )
207	207	ROM_END
208	208
209
210	209	ROM_START( pecom64 )
211	210	ROM_REGION( 0x10000, CDP1802_TAG, ROMREGION_ERASEFF )
212	211	ROM_SYSTEM_BIOS(0, "ver4", "version 4")
r29424	r29425
220	219	/* Driver */
221	220
222	221	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
223		COMP( 1987, pecom32, 0, 0, pecom64, pecom, driver_device, 0, "Ei Nis", "Pecom 32", 0)
	222	COMP( 1986, pecom32, 0, 0, pecom64, pecom, driver_device, 0, "Ei Nis", "Pecom 32", 0)
224	223	COMP( 1987, pecom64, pecom32, 0, pecom64, pecom, driver_device, 0, "Ei Nis", "Pecom 64", 0)

branches/new_menus/src/mess/drivers/esqmr.c
r29424	r29425
12	12	Memory map:
13	13
14	14	0x000000-0x0FFFFF OS ROM
	15
	16	MR Rack
	17	Ensoniq, 1995
15	18
	19	This is a 64-voice expandable synth module made by Ensoniq in 1995.
	20
	21	PCB Layout
	22	----------
	23
	24	\|--------------------------------------------------------\|
	25	\| J6 J7 J12 J13 J21 J23 J22\|
	26	\| J5\|
	27	\| 4565 4565 HP_6N138 \|
	28	\| \|
	29	\| BATTERY 7407 \|
	30	\| 4565 \|
	31	\| \|
	32	\| OTTOR2 OTTOR2 \|
	33	\|AD1861 \|
	34	\|AD1861 \|
	35	\|AD1861 \|
	36	\|AD1861 \|--J3-----\| \|
	37	\| HC04 \|EXPANSION\| \|
	38	\| \|BOARD #3 \| \|
	39	\| \| \| \|
	40	\| 1370001501 \| \| \|
	41	\| \| \| \|
	42	\| \|--J8-----\| \|
	43	\| ESP2 ROM2 \|
	44	\| \|--J2-----\| \|
	45	\| \|EXPANSION\| \|
	46	\| ROM0 \|BOARD #2 \| \|
	47	\| \| \| \|
	48	\| D43256 IDT7130 \| \| \|
	49	\| D43256 35MHz 16MHz ROM1 \| \| \|
	50	\| D43256 J14 \|--J9-----\| \|
	51	\| D43256 22.5792MHz ADM691\|
	52	\| D43256 MC68340 \|--J1-----\| \|
	53	\| D43256 \|EXPANSION\| \|
	54	\| 6MHz \|BOARD #1 \| \|
	55	\| EPROM_UP \| \| \|
	56	\| MC68HC705C4A KM681000 \| \|
	57	\|J4 EPROM_LO KM681000 \|J11\|
	58	\| J19 J18 \|--J10----\| \|
	59	\|--------------------------------------------------------\|
	60	Notes:
	61	J4/J18/J19 - Connectors to front panel buttons, LCD etc
	62	J1/J10 - Connectors for expansion board #1
	63	J2/J9 - Connectors for expansion board #2
	64	J3/J8 - Connectors for expansion board #3
	65	J11 - Memory card connector
	66	J14 - JTAG connector
	67	J6 - Main left/mono jack
	68	J7 - Main right jack
	69	J12 - Aux left/mono jack
	70	J13 - Aux right jack
	71	J21 - MIDI in connector
	72	J23 - MIDI out connector
	73	J22 - MIDI thru connector
	74	J5 - Power input connector
	75	1370001501 - Unknown TQFP144 IC stamped with the Ensoniq logo. CPLD or gate array.
	76	ESP2 - Ensoniq ESP2 (ES5511) sound chip
	77	OTTOR2 - Ensoniq OTTOR2 (ES5506) sound chip
	78	ROM* - 4M x8-bit SOP44 mask ROM
	79	D43256 - NEC D43256 32k x8-bit SRAM
	80	HP_6N138 - HP/Agilent HP 6N138 Low Input Current High Gain Optocoupler
	81	4565 - JRC4565 Dual Operational Amplifier
	82	AD1861 - Analog Devices AD1861 16-bit/18-bit PCM Audio DAC
	83	MC68HC705C4A - Motorola MC68HC705C4A Microcontroller. Clock input is tied to the TQFP CPLD
	84	MC68340 - Motorola MC68340PV16E 68000-compatible 32-bit processor with on-board peripherals. Clock input 6.000MHz
	85	EPROM* - 27C4001 EPROM
	86	FDT7130 - IDT7130 High Speed 1k x8-bit Dual Port Static RAM
	87	KM681000 - Samsung KM681000 128k x8-bit Static RAM
	88
16	89	***************************************************************************/
17	90
18	91	#include "emu.h"
r29424	r29425
92	165	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
93	166	MCFG_SOUND_ADD("ensoniq", ES5506, XTAL_16MHz)
94	167	MCFG_SOUND_CONFIG(es5506_config)
95		MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
96		MCFG_SOUND_ROUTE(1, "rspeaker", 2.0)
	168	MCFG_SOUND_ROUTE(0, "lspeaker", 0.5)
	169	MCFG_SOUND_ROUTE(1, "rspeaker", 0.5)
97	170	MCFG_SOUND_ADD("ensoniq2", ES5506, XTAL_16MHz)
98	171	MCFG_SOUND_CONFIG(es5506_2_config)
99		MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
100		MCFG_SOUND_ROUTE(1, "rspeaker", 2.0)
	172	MCFG_SOUND_ROUTE(0, "lspeaker", 0.5)
	173	MCFG_SOUND_ROUTE(1, "rspeaker", 0.5)
101	174	MACHINE_CONFIG_END
102	175
103	176	static INPUT_PORTS_START( mr )
r29424	r29425
108	181	ROM_LOAD16_WORD_SWAP( "mrw-osf-11af-2.10.bin", 0x000000, 0x080000, CRC(5854314e) SHA1(8fb2e2ee2f5fb12eae8ea33cb18f757efaec6780) )
109	182	ROM_LOAD16_WORD_SWAP( "mrw-romc-32ef-1.20.bin", 0x080000, 0x080000, CRC(68321347) SHA1(56cb96943ba42c35ba2787a49b5f4adf7c8dffb8) )
110	183
111		ROM_REGION(0x200000, "waverom", ROMREGION_ERASE00)
112		ROM_REGION(0x200000, "waverom2", ROMREGION_ERASE00)
113		ROM_REGION(0x200000, "waverom3", ROMREGION_ERASE00)
	184	ROM_REGION(0x400000, "waverom", ROMREGION_ERASE00)
	185
	186	ROM_REGION(0x400000, "waverom2", ROMREGION_ERASE00)
	187
	188	ROM_REGION(0x400000, "waverom3", ROMREGION_ERASE00)
	189
114	190	ROM_REGION(0x200000, "waverom4", ROMREGION_ERASE00)
115	191	ROM_END
116	192
117	193	ROM_START( mrrack )
	194	// 68340 main MCU
118	195	ROM_REGION(0x100000, "maincpu", 0)
119		ROM_LOAD16_BYTE( "mr-rack-150-lo.bin", 0x000001, 0x080000, CRC(b29988a1) SHA1(986c2def11de27fa2b9be55ac32f7fec0c414bca) )
120		ROM_LOAD16_BYTE( "mr-rack-150-up.bin", 0x000000, 0x080000, CRC(71511692) SHA1(54744f16f1db1ac5abb2f70b6e04aebf1e0e029d) )
	196	ROM_LOAD16_BYTE( "mr_r_ec51_lo_1.50.u36", 0x000001, 0x080000, CRC(b29988a1) SHA1(986c2def11de27fa2b9be55ac32f7fec0c414bca) )
	197	ROM_LOAD16_BYTE( "mr_r_9dac_up_1.50.u35", 0x000000, 0x080000, CRC(71511692) SHA1(54744f16f1db1ac5abb2f70b6e04aebf1e0e029d) )
121	198
122		ROM_REGION(0x200000, "waverom", ROMREGION_ERASE00)
123		ROM_REGION(0x200000, "waverom2", ROMREGION_ERASE00)
124		ROM_REGION(0x200000, "waverom3", ROMREGION_ERASE00)
	199	// 68705 display/front panel MCU
	200	ROM_REGION(0x2000, "mcu", 0)
	201	ROM_LOAD( "68hc705.u40", 0x000000, 0x002000, CRC(7b0291a7) SHA1(c92c19ce9289b7b21dbc915475cdff8930e3c677) )
	202
	203	ROM_REGION(0x400000, "waverom", ROMREGION_ERASE00)
	204	ROM_LOAD( "1351000901_h-rom0.u5", 0x000000, 0x400000, CRC(89654b42) SHA1(4bdffd8060eb20cdb01f6178222aeb32fdbfd703) )
	205
	206	ROM_REGION(0x400000, "waverom2", ROMREGION_ERASE00)
	207	ROM_LOAD( "1351000902_h-rom1.u23", 0x000000, 0x400000, CRC(4a19e517) SHA1(e819f1e0b50c4911c4855ad95ed505998a2bbe86) )
	208
	209	ROM_REGION(0x400000, "waverom3", ROMREGION_ERASE00)
	210	ROM_LOAD( "1351000903_h-rom2.u24", 0x000000, 0x400000, CRC(c9ab1214) SHA1(92f48b068bbe49eacbffd03e428599e3ab21b8ec) )
	211
125	212	ROM_REGION(0x200000, "waverom4", ROMREGION_ERASE00)
126	213	ROM_END
127	214

branches/new_menus/src/mess/drivers/tandy2k.c
r29424	r29425
4	4
5	5	Tandy 2000
6	6
7		Skeleton driver.
8
9	7	****************************************************************************/
10	8
11	9	/*
12	10
13	11	TODO:
14	12
	13	- floppy
	14	- HDL is also connected to WP/TS input where TS is used to detect motor status
	15	- 3 second motor off delay timer
	16	- DMA
15	17	- video (video RAM is at memory top - 0x1400, i.e. 0x1ec00)
16		- DMA
17		- floppy
18	18	- keyboard ROM
19	19	- hires graphics board
20	20	- WD1010
r29424	r29425
146	146	m_pit->write_gate2(BIT(data, 4));
147	147
148	148	// FDC reset
149		if(BIT(data, 5))
	149	if(!BIT(data, 5))
150	150	m_fdc->reset();
151	151
152	152	// timer 0 enable
r29424	r29425
335	335
336	336	// Video
337	337
	338	UINT32 tandy2k_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	339	{
	340	const pen_t *pen = m_palette->pens();
	341	address_space &program = m_maincpu->space(AS_PROGRAM);
	342
	343	for (int y = 0; y < 400; y++)
	344	{
	345	UINT8 cgra = y % 16;
	346
	347	for (int sx = 0; sx < 80; sx++)
	348	{
	349	offs_t addr = m_ram->size() - 0x1400 + (((y / 16) * 80) + sx) * 2;
	350	UINT8 vidla = program.read_word(addr);
	351	UINT8 data = m_char_ram[(vidla << 4) \| cgra];
	352
	353	for (int x = 0; x < 8; x++)
	354	{
	355	int color = BIT(data, 7);
	356	bitmap.pix32(y, (sx * 8) + x) = pen[color];
	357	data <<= 1;
	358	}
	359	}
	360	}
	361
	362	return 0;
	363	}
	364
338	365	WRITE_LINE_MEMBER( tandy2k_state::vpac_vlt_w )
339	366	{
340	367	m_drb0->ren_w(state);
r29424	r29425
638	665
639	666	// Intel 8272 Interface
640	667
641		WRITE_LINE_MEMBER( tandy2k_state::fdc_drq )
	668	WRITE_LINE_MEMBER( tandy2k_state::fdc_drq_w )
642	669	{
643	670	dma_request(0, state);
644	671	}
645	672
	673	WRITE_LINE_MEMBER( tandy2k_state::fdc_hdl_w )
	674	{
	675	m_floppy0->mon_w(!state);
	676	m_floppy1->mon_w(!state);
	677	}
	678
	679	FLOPPY_FORMATS_MEMBER( tandy2k_state::floppy_formats )
	680	FLOPPY_TANDY_2000_FORMAT
	681	FLOPPY_FORMATS_END
	682
646	683	static SLOT_INTERFACE_START( tandy2k_floppies )
647	684	SLOT_INTERFACE( "525qd", FLOPPY_525_QD )
648	685	SLOT_INTERFACE_END
r29424	r29425
688	725
689	726	m_char_ram.allocate(0x1000);
690	727
691		// HACK these should be connected to FDC HLD output
692		m_floppy0->mon_w(0);
693		m_floppy1->mon_w(0);
694
695	728	// register for state saving
696	729	save_item(NAME(m_dma_mux));
697	730	save_item(NAME(m_kbdclk));
r29424	r29425
721	754	MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
722	755	MCFG_SCREEN_REFRESH_RATE(50)
723	756	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // not accurate
724		MCFG_SCREEN_SIZE(640, 480)
725		MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
726		MCFG_SCREEN_UPDATE_DEVICE(CRT9021B_TAG, crt9021_t, screen_update)
	757	MCFG_SCREEN_SIZE(640, 400)
	758	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 400-1)
	759	//MCFG_SCREEN_UPDATE_DEVICE(CRT9021B_TAG, crt9021_t, screen_update)
	760	MCFG_SCREEN_UPDATE_DRIVER(tandy2k_state, screen_update)
727	761
728		MCFG_PALETTE_ADD_~~BLACK_A~~N~~D_W~~HITE("palette")
	762	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
729	763
730		MCFG_DEVICE_ADD(CRT9007_TAG, CRT9007, XTAL_16MHz*28/~~16/1~~0)
	764	MCFG_DEVICE_ADD(CRT9007_TAG, CRT9007, XTAL_16MHz*28/20/8)
731	765	MCFG_DEVICE_ADDRESS_MAP(AS_0, vpac_mem)
732		MCFG_CRT9007_CHARACTER_WIDTH(10)
	766	MCFG_CRT9007_CHARACTER_WIDTH(8)
733	767	MCFG_CRT9007_INT_CALLBACK(DEVWRITELINE(I8259A_1_TAG, pic8259_device, ir1_w))
734	768	MCFG_CRT9007_VS_CALLBACK(DEVWRITELINE(CRT9021B_TAG, crt9021_t, vsync_w))
735	769	MCFG_CRT9007_VLT_CALLBACK(WRITELINE(tandy2k_state, vpac_vlt_w))
r29424	r29425
749	783	MCFG_CRT9212_WEN2_VCC()
750	784	MCFG_CRT9212_DOUT_CALLBACK(WRITE8(tandy2k_state, drb_attr_w))
751	785
752		MCFG_DEVICE_ADD(CRT9021B_TAG, CRT9021, XTAL_16MHz*28/16)
	786	MCFG_DEVICE_ADD(CRT9021B_TAG, CRT9021, XTAL_16MHz*28/20)
753	787	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
754	788
755		MCFG_TIMER_DRIVER_ADD_PERIODIC("vidldsh", tandy2k_state, vidldsh_tick, attotime::from_hz(XTAL_16MHz*28/16))
	789	MCFG_TIMER_DRIVER_ADD_PERIODIC("vidldsh", tandy2k_state, vidldsh_tick, attotime::from_hz(XTAL_16MHz*28/20/8))
756	790
757	791	// sound hardware
758	792	MCFG_SPEAKER_STANDARD_MONO("mono")
r29424	r29425
782	816	MCFG_PIT8253_OUT2_HANDLER(WRITELINE(tandy2k_state, rfrqpulse_w))
783	817
784	818	MCFG_PIC8259_ADD(I8259A_0_TAG, DEVWRITELINE(I80186_TAG, i80186_cpu_device, int0_w), VCC, NULL)
	819
785	820	MCFG_PIC8259_ADD(I8259A_1_TAG, DEVWRITELINE(I80186_TAG, i80186_cpu_device, int1_w), VCC, NULL)
	821
786	822	MCFG_I8272A_ADD(I8272A_TAG, true)
787	823	downcast<i8272a_device *>(device)->set_select_lines_connected(true);
788	824	MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE(I8259A_0_TAG, pic8259_device, ir4_w))
789		MCFG_UPD765_DRQ_CALLBACK(WRITELINE(tandy2k_state, fdc_drq))
790		MCFG_FLOPPY_DRIVE_ADD(I8272A_TAG ":0", tandy2k_floppies, "525qd", floppy_image_device::default_floppy_formats)
791		MCFG_FLOPPY_DRIVE_ADD(I8272A_TAG ":1", tandy2k_floppies, "525qd", floppy_image_device::default_floppy_formats)
	825	MCFG_UPD765_DRQ_CALLBACK(WRITELINE(tandy2k_state, fdc_drq_w))
	826	MCFG_UPD765_HDL_CALLBACK(WRITELINE(tandy2k_state, fdc_hdl_w))
	827	MCFG_FLOPPY_DRIVE_ADD(I8272A_TAG ":0", tandy2k_floppies, "525qd", tandy2k_state::floppy_formats)
	828	MCFG_FLOPPY_DRIVE_ADD(I8272A_TAG ":1", tandy2k_floppies, "525qd", tandy2k_state::floppy_formats)
792	829
793	830	MCFG_CENTRONICS_ADD(CENTRONICS_TAG, centronics_printers, "image")
794	831	MCFG_CENTRONICS_ACK_HANDLER(WRITELINE(tandy2k_state, write_centronics_ack))

branches/new_menus/src/mess/drivers/fanucspmg.c
r29424	r29425
2	2	// copyright-holders:R. Belmont
3	3	/***************************************************************************
4	4
5		Fanuc System P Model G
	5	Fanuc System P Model G
	6	Fanuc 1983
6	7
7		2014-03-22 Skeleton driver.
	8	2014-03-22 Skeleton driver.
	9	This is a machine from 1983 in a single case
	10	with a lot of ports and a unique keyboard.
8	11
9		This is a machine from 1983 in a single case with a
10		lot of ports and a unique keyboard.
11
12		Also known as Fanuc P-G System, this is a dedicated 8085+8086+8087-based computer
13		system running software for CNC Programming.
14		The system boots up from ROM and then application software is loaded from floppies.
15		The softwares are not point and click auto-generation type conversational CAD/CAM
16		applications.
17		The earlier 'non-Symbolic' software requires knowledge of programming in APT and other
18		languages of the era. The 'Symbolic' software has menus and asks questions and the blanks
19		must be filled in correctly. The graphics are mostly made of lines but are
20		sufficient to complete the task easily. Efficient and effective use of this system
21		requires deep knowledge of CNC Machining techniques (Turning/Milling etc) and a
22		good understanding of machining processes and procedures. With correct usage this system
23		can be used to create CNC G-Code programs for any part that can be manufactured on a
24		CNC Machine. Because the system is made in Japan in the early 80's and the manuals are
25		very technical it also requires some skill in deciphering Japanese-English translated
26		technical texts to understand how to use it properly.
	12	Also known as Fanuc P-G System, this is a dedicated 8085+8086+8087-based computer
	13	system running software for CNC Programming.
	14	The system boots up from on-board EPROM and shows a big ASCII-art boot screen
	15	FANUC SYSTEM P MODEL G and the ROM software version in the lower right corner.
	16	To initiate booting from the floppy drive hold down the LOAD key for 3-5 seconds.
	17	The system checks for a long LOAD key press so that it doesn't load software
	18	if the LOAD key is accidentally pressed quickly while using the system, which would
	19	erase everything in memory and all data up to that point and re-load the software from
	20	scratch. When loading is activated application software is read from floppies.
27	21
28		The box housing everything is 20" wide by 20" deep by 12" high and weighs
29		approximately 40 pounds. Power input is 85VAC to 110VAC. For the non-US and
30		non-Japanese markets a separate dedicated power supply is provided and is 12"
31		wide by 8" deep by 10" high and weighs approximately 20 pounds.
	22	The softwares are not point and click auto-generation type conversational CAD/CAM
	23	applications. The earlier 'non-Symbolic' software requires knowledge of programming in APT
	24	and other languages of the era. The 'Symbolic' software has menus and asks questions and
	25	the blanks must be filled in correctly. The graphics are mostly made of lines but are
	26	sufficient to complete the task easily. Efficient and effective use of this system
	27	requires deep knowledge of CNC Machining techniques (Turning/Milling etc) and a
	28	good understanding of machining processes and procedures. With correct usage this system
	29	can be used to create CNC G-Code programs for any part that can be manufactured on a
	30	CNC Machine. Because the system is made in Japan in the early 80's and the manuals are
	31	very technical it also requires some skill in deciphering Japanese-English translated
	32	technical texts to understand how to use it properly.
32	33
33		A number of optional peripherals can connect to it including a Fanuc Printer,
34		Fanuc PPR Unit (Paper tape Puncher/Reader with built-in printer), Fanuc Program
35		File (containing a 20MB HDD, two 8" floppy drives and two RS232 ports), Fanuc Cassette
36		Adapter, XY Plotter (A3 or A1), Fanuc Digitizing Tablet (A3 or A0) and Fanuc I/O Selector Box.
	34	The box housing everything is 20" wide by 20" deep by 12" high and weighs
	35	approximately 40 pounds. Power input is 85VAC to 110VAC. For the non-US and
	36	non-Japanese markets a separate dedicated power supply is provided and is 12"
	37	wide by 8" deep by 10" high and weighs approximately 20 pounds.
37	38
38		The P-G System has an internal 12" color monitor and dual 5 1/4" floppy drives.
39		A later model was released in 1986 called the Mark II using dual 3 1/2" floppy
40		drives. The previous version was SYSTEM P MODEL D. It had a 12" green monochrome
41		monitor and booted from, and stored to, a cassette tape or floppy disk.
	39	A number of optional peripherals can connect to it including a Fanuc Printer,
	40	Fanuc PPR Unit (Paper tape Puncher/Reader with built-in printer), Fanuc Program
	41	File (containing a 20MB HDD, two 8" floppy drives and two RS232 ports), Fanuc Cassette
	42	Adapter, XY Plotter (A3 or A1), Fanuc Digitizing Tablet (A3 or A0) and Fanuc I/O Selector Box.
42	43
43		The screen resolution is 512 x 384 pixels.
44		It can display 64 characters x 24 lines.
	44	The P-G System has an internal 12" color monitor and dual 5 1/4" floppy drives.
	45	A later model was released in 1986 called the Mark II using dual 3 1/2" floppy
	46	drives. The previous version was SYSTEM P MODEL D. It had a 12" green monochrome
	47	monitor and booted from, and stored to, a cassette tape or floppy disk.
45	48
46		The floppy format is custom. Floppies are double sided double density and
47		regular PC DSDD 360k floppies can be used after they are formatted using the
48		P-G System.
49		The floppy geometry is 40 tracks, 16 sectors per track, 256 bytes per sector
50		and 2 sides for a total storage capacity of 327680 bytes.
51		The floppy drives are typical PC-type 5 1/4" 360k drives and were manufactured
52		by Y-E DATA, model YD-580.
	49	The screen resolution is 512 x 384 pixels.
	50	It can display 64 characters x 24 lines.
53	51
54		The floppy disks can be backed-up and imaged using a DOS program called ImageDisk
55		which is available here.....
56		http://www.classiccmp.org/dunfield/img/index.htm
57		With a 5 1/4" HD floppy drive, in the GUI in settings change the number of
58		cylinders to 40, translate speed 300 -> 250 (to read a DD disk on a HD drive).
59		On the main menu press R to Read, type a file-name and press enter, press enter
60		again to skip the comment. Press enter again and it will read the disk and save
61		it to the HDD.
	52	The floppy format is custom. Floppies are double sided double density and
	53	regular PC DSDD 360k floppies can be used after they are formatted using the
	54	P-G System.
	55	The floppy geometry is 40 tracks, 16 sectors per track, 256 bytes per sector
	56	and 2 sides for a total storage capacity of 327680 bytes.
	57	The floppy drives are typical PC-type 5 1/4" 360k drives and were manufactured
	58	by Y-E DATA, model YD-580.
62	59
63		The following is a complete list of software titles available.
64		The info is taken from a glossy sales brochure printed in July 1985.
65		Other versions did exist so this list is not final.
66		* denotes it is dumped. All other titles are not dumped and are needed.
	60	The floppy disks can be backed-up and imaged using a DOS program called ImageDisk
	61	which is available here.....
	62	http://www.classiccmp.org/dunfield/img/index.htm
	63	With a 5 1/4" HD floppy drive, in the GUI in settings change the number of
	64	cylinders to 40, translate speed 300 -> 250 (to read a DD disk on a HD drive).
	65	On the main menu press R to Read, type a file-name and press enter, press enter
	66	again to skip the comment. Press enter again and it will read the disk and save
	67	it to the HDD.
67	68
68		Language Input -
	69	The following is a complete list of software titles available.
	70	The info is taken from a glossy sales brochure printed in July 1985.
	71	Other versions did exist so this list is not final.
	72	* denotes it is dumped. All other titles are not dumped and are needed.
69	73
70		Title Part Number
71		--------------------------------
72		FAPT TURN A08B-0033-J600#E
73		FAPT CUT A08B-0033-J620#E
74		FAPT MILL A08B-0033-J640#E
75		FAPT DIE-II A08B-0033-J660#E
76		FAPT PUNCH-I A08B-0033-J520#E
77		FAPT PUNCH-II A08B-0033-J700#E
78		FAPT HELICAL A08B-0033-J642#E
79		FAPT POST A08B-0033-H642#E
80		*FAPT POST A08B-0031-H630 Edition C 85/1/31
	74	Language Input -
81	75
	76	Title Part Number
	77	--------------------------------
	78	FAPT TURN A08B-0033-J600#E
	79	FAPT CUT A08B-0033-J620#E
	80	FAPT MILL A08B-0033-J640#E
	81	FAPT DIE-II A08B-0033-J660#E
	82	FAPT PUNCH-I A08B-0033-J520#E
	83	FAPT PUNCH-II A08B-0033-J700#E
	84	FAPT HELICAL A08B-0033-J642#E
	85	FAPT POST A08B-0033-H642#E
	86	*FAPT POST A08B-0031-H630 Edition C 85/1/31
82	87
83		Graphic Input -
84	88
85		Title Part Number
86		--------------------------------------
87		*Symbolic FAPT TURN A08B-0033-J800#E +English
88		Symbolic FAPT MILL A08B-0033-J840#E
89		Symbolic FAPT DRILL A08B-0033-J860#E
90		Symbolic FAPT CUT A08B-0033-J820#E
91		FAPT DIGITIZER A08B-0033-J510#E
	89	Graphic Input -
92	90
93		+ Symbolic FAPT TURN was available in English, German, French, Dutch, Finnish,
94		and Swedish versions.
	91	Title Part Number
	92	--------------------------------------
	93	*Symbolic FAPT TURN A08B-0033-J800#E +English
	94	Symbolic FAPT MILL A08B-0033-J840#E
	95	Symbolic FAPT DRILL A08B-0033-J860#E
	96	Symbolic FAPT CUT A08B-0033-J820#E
	97	FAPT DIGITIZER A08B-0033-J510#E
95	98
	99	+ Symbolic FAPT TURN was available in English, German, French, Dutch, Finnish,
	100	and Swedish versions.
96	101
97		Support System -
98	102
99		Title Part Number
100		-------------------------------
101		*FAPT TRACER A08B-0033-H620#E Edition B 85/1/16
102		*FAPT TEACHER A08B-0033-J610#E Edition B 85/1/12
103		*FAPT DOCTOR A08B-0033-J600#E Edition B 84/12/21
	103	Support System -
104	104
	105	Title Part Number
	106	-------------------------------
	107	*FAPT TRACER A08B-0033-H620#E Edition B 85/1/16
	108	*FAPT TEACHER A08B-0033-J610#E Edition B 85/1/12
	109	*FAPT DOCTOR A08B-0033-J600#E Edition B 84/12/21
105	110
106		The software for the Fanuc System P Model G is extremely rare now and very
107		difficult to find. If you do have any of these wanted software titles or any manuals
108		listed below and want to help please contact me (Guru) via http://mamedev.org/contact.html
109	111
110		The following is a complete list of manuals available for the first edition of the
111		Fanuc System P Model G released in 1983. The info is taken from a glossy sales brochure
112		printed in July 1985. There were other manuals released later for the Mark II and
113		updated manuals (each with a different part number).
114		The manuals were available in Japanese and English. The part numbers listed here
115		are English versions, denoted by the E at the end of the part number.
116		* denotes these manuals are secured and available in PDF format.
	112	Note: To initiate booting from the floppy drive hold down the LOAD key for 3-5 seconds.
117	113
118		Description -
	114	The software for the Fanuc System P Model G is extremely rare now and very
	115	difficult to find. If you do have any of these wanted software titles or any manuals
	116	listed below and want to help please contact me (Guru) via http://mamedev.org/contact.html
119	117
120		Title Part Number
121		---------------------------------------
122		FAPT TURN/MILL Description B-54102E
123		FAPT CUT Description B-54103E
124		FAPT PUNCH-I Description B-54104E
125		FAPT TRACER Description B-54106E
126		FAPT DIGITIZER Description B-54107E
127		Symbolic FAPT Description B-54131E
128		FAPT DIE-II Description B-54121E
	118	The following is a complete list of manuals available for the first edition of the
	119	Fanuc System P Model G released in 1983. The info is taken from a glossy sales brochure
	120	printed in July 1985. There were other manuals released later for the Mark II and
	121	updated manuals (each with a different part number).
	122	The manuals were available in Japanese and English. The part numbers listed here
	123	are English versions, denoted by the E at the end of the part number.
	124	* denotes these manuals are secured and available in PDF format.
129	125
	126	Description -
130	127
131		Operator's Manual -
	128	Title Part Number
	129	---------------------------------------
	130	FAPT TURN/MILL Description B-54102E
	131	FAPT CUT Description B-54103E
	132	FAPT PUNCH-I Description B-54104E
	133	FAPT TRACER Description B-54106E
	134	FAPT DIGITIZER Description B-54107E
	135	FAPT DIE-II Description B-54121E
	136	Symbolic FAPT Description B-54131E
132	137
133		Title Part Number
134		----------------------------------------------------------
135		System P-Model G Operator's Manual B-54111E
136		System P-Model G Mark II Operator's Manual B-66014E
137		*System P-Model G Operator's Manual Supplement B-54112E/03-1
138		FAPT TURN/MILL Operator's Manual B-54112E
139		FAPT CUT Operator's Manual B-54113E
140		FAPT PUNCH-I Operator's Manual B-54114E
141		FAPT PUNCH-II Operator's Manual B-54115E
142		*Symbolic FAPT TURN Operator's Manual B-54132E
143		*Symbolic FAPT TURN Operator's Manual B-66025E (for System P Mark II)
144		Symbolic FAPT MILL Operator's Manual B-54134E
145		Symbolic FAPT DRILL Operator's Manual B-54138E
146		Symbolic FAPT CUT Operator's Manual B-54136E
147		FAPT DIE-II Operator's Manual B-54122E (Two Volumes)
148		FAPT TRACER Operator's Manual B-54116E
149		FAPT DIGITIZER Operator's Manual B-54117E
150		FAPT TEACHER Operator's Manual B-54126E
151	138
	139	Operator's Manual -
152	140
153		Others -
	141	Title Part Number
	142	----------------------------------------------------------
	143	*System P-Model G Operator's Manual B-54111E/03
	144	System P-Model G Mark II Operator's Manual B-66014E
	145	*System P-Model G Operator's Manual Supplement B-54112E/03-1
	146	FAPT TURN/MILL Operator's Manual B-54112E
	147	FAPT CUT Operator's Manual B-54113E
	148	FAPT PUNCH-I Operator's Manual B-54114E
	149	FAPT PUNCH-II Operator's Manual B-54115E
	150	*FAPT TRACER Operator's Manual B-54116E/03
	151	FAPT DIGITIZER Operator's Manual B-54117E
	152	*FAPT Universal POST Operator's Manual B-54118E/02
	153	FAPT DIE-II Operator's Manual (Volume 1) B-54122E
	154	FAPT DIE-II Operator's Manual (Volume 2) B-54122E-1
	155	*FAPT TEACHER Operator's Manual B-54126E/01
	156	220S FAPT MILL Operator's Manual B-54127E
	157	*Symbolic FAPT TURN Operator's Manual B-54132E/01
	158	Symbolic FAPT MILL Operator's Manual B-54134E
	159	Symbolic FAPT CUT Operator's Manual B-54136E
	160	Symbolic FAPT DRILL Operator's Manual B-54138E
	161	*Symbolic FAPT TURN Operator's Manual B-66025E/01 (for System P Mark II)
154	162
155		Title Part Number
156		-----------------------------------------------------
157		System P-Model G Operator's Handbook B-54158E
158		*System P-Model G Maintenance Manual B-54159E
159		FAPT TURN/MILL/CUT Part program examples B-54128E
160		FANUC CASSETTE Operator's Manual B-53484E
161		*Symbolic FAPT TURN Operator's Handbook B-53034E (for System P Model D)
162		Symbolic FAPT TURN Operator's Handbook B-54133E
163		FAPT DIE-II Part program examples B-54123E
164		FANUC PPR Operator's Manual B-54584E
165	163
166		Not~~e t~~he ~~handbooks we~~r~~e pocket-~~s~~ized~~ ~~8" long by 3 1/2" wide and approximately 50 pages.~~
	164	Others -
167	165
	166	Title Part Number
	167	-----------------------------------------------------
	168	*Symbolic FAPT TURN Operator's Handbook B-53034E (for System P Model D)
	169	FANUC CASSETTE Operator's Manual B-53484E
	170	FAPT DIE-II Part program examples B-54123E
	171	FAPT TURN/MILL/CUT Part program examples B-54128E
	172	Symbolic FAPT TURN Operator's Handbook B-54133E
	173	System P-Model G Operator's Handbook B-54158E
	174	*System P-Model G Maintenance Manual B-54159E/01
	175	*FANUC PPR Operator's Manual B-54584E/01
168	176
169		The unit has it's own dedicated keyboard with many special keys.
170		The keyboard layout is shown below.
	177	Note the handbooks are pocket-sized 8" long by 3 1/2" wide and approximately 50 pages.
171	178
172		\|------------------------------------------------------------------------------\|
173		\| \|
174		\| LOAD F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 R0 R1 R2 R3 \|
175		\| \|
176		\| \|
177		\| ! " # $ % & ' ( ) = \|
178		\| K0 1 2 3 4 5 6 7 8 9 0 - ^ Y DEL 7 8 9 + \| (Y is Japanese Yen sign)
179		\| \|
180		\| \|
181		\| K1 CAN Q W E R T Y U I O P @ [ NL BS 4 5 6 - \| (NL means NEXT LINE, BS is backspace)
182		\| \| (NL is equivalent to return or enter and)
183		\| + * \| (forces the cursor to move to the next data entry point)
184		\| K2 UC A S D F G H J K L ; : ] UC 1 2 3 x \| (UC is uppercase)
185		\| \|
186		\| < > ? \|
187		\| K3 LC Z X C V B N M , . / - LC 0 , . / \| (LC is lowercase)
188		\| \|
189		\| \|
190		\| _S__P__A__C__E__B__A__R_ _N__L_ \|
191		\| \|
192		\|------------------------------------------------------------------------------\|
193	179
194		On the numeric keypad there are directional arrows on numbers 1 2 3 4 6 7 8 9
195		1 3 7 9 have arrows pointing South West, South East, North West, North East.
196		2 4 6 8 have arrows pointing down, left, right and up.
197		5 is the center and has no additional markings on it.
198		Number 0 has an anti-clockwise 180 degrees arc with an arrow at the end and . has
199		a clockwise 180 degrees arc with an arrow at the end.
200		These keys are the 'Symbolic' keys.
	180	The unit has it's own dedicated keyboard with many special keys.
	181	The keyboard layout is shown below.
201	182
202		The F-keys and R-keys are programmed by the software that is running on the system.
203		The F-keys are SPDT type keys so they can be either up or locked in the down position.
204		For Symbolic FAPT TURN these keys are pre-programmed as follows.....
	183	\|------------------------------------------------------------------------------\|
	184	\| \|
	185	\| LOAD F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 R0 R1 R2 R3 \|
	186	\| \|
	187	\| \|
	188	\| ! " # $ % & ' ( ) = \|
	189	\| K0 1 2 3 4 5 6 7 8 9 0 - ^ Y DEL 7 8 9 + \| (Y is Japanese Yen sign)
	190	\| \|
	191	\| \|
	192	\| K1 CAN Q W E R T Y U I O P @ [ NL BS 4 5 6 - \| (NL means NEXT LINE, BS is backspace)
	193	\| \| (NL is equivalent to return or enter and)
	194	\| + * \| (forces the cursor to move to the next data entry point)
	195	\| K2 UC A S D F G H J K L ; : ] UC 1 2 3 x \| (UC is uppercase)
	196	\| \|
	197	\| < > ? \|
	198	\| K3 LC Z X C V B N M , . / - LC 0 , . / \| (LC is lowercase)
	199	\| \|
	200	\| \|
	201	\| _S__P__A__C__E__B__A__R_ _N__L_ \|
	202	\| \|
	203	\|------------------------------------------------------------------------------\|
205	204
206		F0 - ON: Sets the backwards direction when using the R1 key.
207		OFF: Sets the forwards direction when using the R1 key. Default is OFF.
208		F1 - ON: Makes the whole screen the graphic area.
209		OFF: Auto-calc the graphic area so the graphic does not overlap the text. Default is OFF.
210		F2 - ON: Shows the parts figure (graphics). Default is ON.
211		OFF: Does not show the parts figure.
212		F3 - ON: Display the NC G-Code data on screen. Default is ON.
213		OFF: Does not display the NC G-Code data on screen.
214		F4 - ON: Printer ON.
215		OFF: Printer OFF. Default is OFF. The printer can be switched on or off any time. When enabled
216		everything displayed on the screen will also print on the printer.
217		F5 - ON: Stops execution of the NC G-Code data before each process begins. Keyboard input additions
218		can also be done at this time.
219		OFF: Program execution continues to the end. Default is OFF.
220		F6 - ON: Outputs the NC G-Code data to a separately selected medium (floppy/cassette or paper tape)
221		OFF: No output to additional medium. Default is OFF.
222		F7 - ON: Stops each time a line of NC G-Code data is output. This is equivalent to Single Block on a CNC Machine.
223		OFF: Program execution continues to the end. Default is OFF.
224		F8 -
225		F9 -
226		F10- ON: Sends the part figure graphic and NC G-Code data to the XY plotter
227		OFF: No output to XY plotter
228		F11-
229		F12-
230		F13-
231		F14-
232		F15-
	205	On the numeric keypad there are directional arrows on numbers 1 2 3 4 6 7 8 9
	206	1 3 7 9 have arrows pointing South West, South East, North West, North East.
	207	2 4 6 8 have arrows pointing down, left, right and up.
	208	5 is the center and has no additional markings on it.
	209	Number 0 has an anti-clockwise 180 degrees arc with an arrow at the end and . has
	210	a clockwise 180 degrees arc with an arrow at the end.
	211	These keys are the 'Symbolic' keys.
233	212
234		The function of the R-keys changes depending on the application and the menu shown on the screen.
235		The initial Symbolic FAPT TURN settings for the R-keys are....
236		R0 - FAPT Execution
237		R1 - Family Program
238		R2 - Setting
239		R3 - Auxiliary Work
	213	The F-keys and R-keys are programmed by the software that is running on the system.
	214	The F-keys act like SPDT switches and can be toggled either off or on.
	215	When they are on, a LED in the center of the key lights.
	216	For Symbolic FAPT TURN these keys are pre-programmed as follows.....
240	217
	218	F0 - ON: Sets the backwards direction when using the R1 key.
	219	OFF: Sets the forwards direction when using the R1 key. Default is OFF.
	220	F1 - ON: Makes the whole screen the graphic area.
	221	OFF: Auto-calc the graphic area so the graphic does not overlap the text. Default is OFF.
	222	F2 - ON: Shows the parts figure (graphics). Default is ON.
	223	OFF: Does not show the parts figure.
	224	F3 - ON: Display the NC G-Code data on screen. Default is ON.
	225	OFF: Does not display the NC G-Code data on screen.
	226	F4 - ON: Printer ON.
	227	OFF: Printer OFF. The printer can be switched on or off any time. When enabled
	228	everything displayed on the screen will also print on the printer. Default is OFF.
	229	F5 - ON: Stops execution of the NC G-Code data before each process begins. Keyboard input additions
	230	can also be done at this time. To continue press NL.
	231	OFF: Program execution continues to the end. Default is OFF.
	232	F6 - ON: Outputs the NC G-Code data to a separately selected medium (floppy/cassette or paper tape)
	233	OFF: No output to additional medium. Default is OFF.
	234	F7 - ON: Stops each time a line of NC G-Code data is output. This is equivalent to Single Block on a CNC Machine.
	235	To continue press NL.
	236	OFF: Program execution continues to the end. Default is OFF.
	237	F8 -
	238	F9 -
	239	F10- ON: Sends the part figure graphic and NC G-Code data to the XY plotter
	240	OFF: No output to XY plotter
	241	F11-
	242	F12-
	243	F13-
	244	F14-
	245	F15-
241	246
	247	The function of the R-keys changes depending on the application and the menu shown on the screen.
	248	The R-keys are used for tasks within the current screen so the function of the R-keys is always
	249	displayed on screen at all times.
	250	The initial Symbolic FAPT TURN settings for the R-keys are....
	251	R0 - FAPT Execution
	252	R1 - Family Program
	253	R2 - Setting
	254	R3 - Auxiliary Work
242	255
243		Box Layout (top view)
244		----------
245	256
246		A08B-0033-B001
247		\|--------------------------------------------\|
248		\| ------------MAIN PCB---------------------- \|
249		\| -----------SUB-PCB----------- \| \|
250		\| \| \|
251		\| \|-----------------------\| \| \|
252		\| \| \| \| \|
253		\| \| \| P \|
254		\| \| CRT UNIT \| O \|
255		\| \| \| W \|
256		\| \| \| E \|
257		\| \| 12" COLOR \| \|---------\| R \|
258		\| \| \| \|FDD UNIT \| \| \|
259		\| \| SCREEN \| \|A87L-0001\| P \|
260		\| \| \| \|-0026 \| C \|
261		\| \| \| \| \| B \|
262		\| \| \| \| \| \| \|
263		\| \| \| \|5 1/4" \| \| \|
264		\| \| \| \|FLOPPY \| \|
265		\| \| \| \|DRIVES \| \|
266		\| \| \| \|x2 \| \|
267		\| \|-----------------------\| \|---------\| \|
268		\|--------------------------------------------\|
	257	Box Layout (top view)
	258	----------
269	259
	260	A08B-0033-B001
	261	\|--------------------------------------------\|
	262	\| ------------MAIN PCB---------------------- \|
	263	\| -----------SUB-PCB----------- \| \|
	264	\| \| \|
	265	\| \|-----------------------\| \| \|
	266	\| \| \| \| \|
	267	\| \| \| P \|
	268	\| \| CRT UNIT \| O \|
	269	\| \| \| W \|
	270	\| \| \| E \|
	271	\| \| 12" COLOR \| \|---------\| R \|
	272	\| \| \| \|FDD UNIT \| \| \|
	273	\| \| SCREEN \| \|A87L-0001\| P \|
	274	\| \| \| \|-0026 \| C \|
	275	\| \| \| \| \| B \|
	276	\| \| \| \| \| \| \|
	277	\| \| \| \|5 1/4" \| \| \|
	278	\| \| \| \|FLOPPY \| \|
	279	\| \| \| \|DRIVES \| \|
	280	\| \| \| \|x2 \| \|
	281	\| \|-----------------------\| \|---------\| \|
	282	\|--------------------------------------------\|
270	283
271		Main PCB Layout
272		---------------
273	284
274		A20B-1000-0710/03B
275		\|-------------------------------------------\|
276		\| CNF CNE CND CNC CNB CNA \|
277		\| VR1 ^ \|
278		\| JUMPERS XXXXXXXXX\|
279		\| % MB15541 XXXXXXXXXXXXXXXXXX\|
280		\| XXXXXXXXXXXXXXXXXX\|
281		\| 8087-3 D8253 XXXXXXXXXXXXXXXXXX\|
282		\| 8086-2 D765 D8253 XXXXXXXXX\|
283		\| D8257 \|
284		\|15MHz D8259 D8259 D8251 D8251 \|
285		\|D8284 040_001A.13A D8251 D8251 \|
286		\| 040_002A.15A VR2 CN2 CN1 \|
287		\| CN7 CN6 CN5 CN4 CN3 \|
288		\|-------------------------------------------\|
289		Notes:
290		D8086 - Intel 8086 CPU
291		D8087 - Intel 8087 x87 Floating-Point Co-Processor
292		XXXXXXX - Fujitsu MB8265-15 65536 x1-bit DRAM (72 chips total)
293		MB15541 - Fujitsu MB15541 Custom Chip
294		D765 - NEC D765 Single/Double Density Floppy-Disk Controller
295		D8251 - Intel D8251 Programmable Communications Interface (USART)
296		D8253 - NEC D8253 Programmable Interval Timer
297		D8257 - NEC D8257 Programmable DMA Controller
298		D8259 - NEC D8259 Programmable Interrupt Controller
299		D8284 - Intel D8284 Clock Generator and Driver for 8086/8088 Processors
300		A40_00* - Fujitsu MBM2764 8k x8-bit EPROM
301		VR1/VR2 - Potentiometer
302		^ - 3 chips marked Y-E Data Fujitsu
303		MB4393
304		MB14324
305		MB14323
306		% - Unknown 20-pin DIP chip with heat-sink
307		CNA - 50-pin flat cable joining to Sub PCB
308		CNB - 50-pin flat cable joining to Sub PCB
309		CNC - 6-pin power cable joining to Sub PCB
310		CND - 34-pin flat cable joining to FDD Unit
311		CNE - Fanuc Honda MR-50 50-pin female connector for expansion (not used)
312		CNF - Power input connector
313		CN1 - 25-pin Female D-type connector. Generally this is connected to the CNC Machine serial port)
314		CN2 - 25-pin Female D-type connector (for RS232 external peripherals)
315		CN3 - 25-pin Female D-type connector (for RS232 external peripherals)
316		CN4 - 25-pin Female D-type connector (for RS232 external peripherals)
317		CN5 - Fanuc Honda MR-50 50-pin female connector (probably for external connection of the Fanuc Program File Unit)
318		CN6 - Fanuc Honda MR-20 20-pin female connector for connection of the keyboard
319		CN7 - Fanuc Honda MR-20 20-pin male Facit 4070 Parallel Reader/Puncher connector (PPR Unit)
320		Pinout: (pin 1 is top left, location key is on the opposite side)
321		\|---------------------------------------------------\|
322		\| \|
323		\| 1_PR 2_TE 3_ERR 4_TTY3 5_+6V 6_TTY2 7_TTY1 \|
324		\| \|
325		\| 8_SG 9_SD 10_0V 11_CH1 12_CH2 13_CH3 O
326		\| \|
327		\| 14_CH4 15_CH5 16_CH6 17_CH7 18_CH8 19_CH9 20_PI \|
328		\| \|
329		\|---------------------------------------------------\|
330		JUMPERS - 15 2-pin jumpers labelled S1 to S15. S2, S3 & S4 are not shorted. All others are shorted.
	285	Main PCB Layout
	286	---------------
331	287
	288	A20B-1000-0710/03B
	289	\|-------------------------------------------\|
	290	\| CNF CNE CND CNC CNB CNA \|
	291	\| VR1 ^ \|
	292	\| JUMPERS XXXXXXXXX\|
	293	\| % MB15541 XXXXXXXXXXXXXXXXXX\|
	294	\| XXXXXXXXXXXXXXXXXX\|
	295	\| 8087-3 D8253 XXXXXXXXXXXXXXXXXX\|
	296	\| 8086-2 D765 D8253 XXXXXXXXX\|
	297	\| D8257 \|
	298	\|15MHz D8259 D8259 D8251 D8251 \|
	299	\|D8284 040_001A.13A D8251 D8251 \|
	300	\| 040_002A.15A VR2 CN2 CN1 \|
	301	\| CN7 CN6 CN5 CN4 CN3 \|
	302	\|-------------------------------------------\|
	303	Notes:
	304	D8086 - Intel 8086 CPU. Clock input 5.000MHz [15/3]
	305	D8087 - Intel 8087 x87 Floating-Point Co-Processor. Clock input 5.000MHz [15/3]
	306	XXXXXXX - Fujitsu MB8265-15 65536 x1-bit DRAM (72 chips total)
	307	MB15541 - Fujitsu MB15541 Custom Chip
	308	D765 - NEC D765 Single/Double Density Floppy-Disk Controller. Clock input 4.000MHz [16/4]
	309	D8251 - Intel D8251 Programmable Communications Interface (USART)
	310	D8253 - NEC D8253 Programmable Interval Timer. Clock input 1.25MHz [15/12]
	311	D8257 - NEC D8257 Programmable DMA Controller. Clock input 3.000MHz [15/5]
	312	D8259 - NEC D8259 Programmable Interrupt Controller
	313	D8284 - Intel D8284 Clock Generator and Driver for 8086/8088 Processors
	314	A40_00* - Fujitsu MBM2764 8k x8-bit EPROM
	315	VR1/VR2 - Potentiometer
	316	^ - 3 chips marked Y-E Data Fujitsu
	317	MB4393
	318	MB14324
	319	MB14323
	320	% - Unknown 20-pin Ceramic DIP chip with heat-sink
	321	CNA - 50-pin flat cable joining to Sub PCB
	322	CNB - 50-pin flat cable joining to Sub PCB
	323	CNC - 6-pin power cable joining to Sub PCB
	324	CND - 34-pin flat cable joining to FDD Unit
	325	CNE - Fanuc Honda MR-50 50-pin female connector for expansion (not used)
	326	CNF - Power input connector
	327	CN1 - 25-pin Female D-type connector. (for RS232 external peripherals \ CNC Machine,
	328	CN2 - 25-pin Female D-type connector. (for RS232 external peripherals \| PPR Unit, X-Y Plotter,
	329	CN3 - 25-pin Female D-type connector. (for RS232 external peripherals \| Tablet,
	330	CN4 - 25-pin Female D-type connector. (for RS232 external peripherals / Cassette Adapter etc (connections in any order)
	331	CN5 - Fanuc Honda MR-50 50-pin female connector (probably for external connection of the Fanuc Program File Unit)
	332	CN6 - Fanuc Honda MR-20 20-pin female connector for the keyboard
	333	CN7 - Fanuc Honda MR-20 20-pin male. Specification says 'not used' but this appears to be a
	334	Facit 4070 Parallel Reader/Puncher connector
	335	Pinout: (pin 1 is top left, location key is on the opposite side)
	336	\|---------------------------------------------------\|
	337	\| \|
	338	\| 1_PR 2_TE 3_ERR 4_TTY3 5_+6V 6_TTY2 7_TTY1 \|
	339	\| \|
	340	\| 8_SG 9_SD 10_0V 11_CH1 12_CH2 13_CH3 O
	341	\| \|
	342	\| 14_CH4 15_CH5 16_CH6 17_CH7 18_CH8 19_CH9 20_PI \|
	343	\| \|
	344	\|---------------------------------------------------\|
	345	JUMPERS - 15 2-pin jumpers labelled S1 to S15. S2, S3 & S4 are not shorted. All others are shorted.
332	346
333		Sub PCB Layout
334		--------------
335	347
336		A20B-1000-0720/02B
337		\|--------------------------------\|
338		\| CNA CNB CNC CND \|
339		\| \|
340		\| MB15542 CNE\|
341		\| \|
342		\| HD6845S D8085\|
343		\| 16MHz \|
344		\| \|
345		\| X \|
346		\| XXXXXXXX \|
347		\| XXXXXXXX \|
348		\| XXXXXXXX 6264 A41_010B.28B\|
349		\| 6264 A41_020A.30B\|
350		\|--------------------------------\|
351		Notes:
352		D8085 - NEC D8085A-2 CPU
353		HD6845S - Hitachi HD6845S / HD46505S CRT Controller
354		6264 - Hitachi HM6264P-15 8k x 8-bit SRAM
355		XXXXXXX - Fujitsu MB8265-15 65536 x1-bit DRAM (25 chips total)
356		MB15542 - Fujitsu MB15542 Custom Chip
357		A41_010B- Intel D27128 16k x8-bit EPROM
358		A42_020A- Hitachi 27256G 32k x8-bit EPROM
359		CNA - 50-pin flat cable joining to Main PCB
360		CNB - 50-pin flat cable joining to Main PCB
361		CNC - 6-pin power cable joining to Main PCB
362		CND - 20-pin flat cable joining to CRT Unit (video output)
363		CNE - Fanuc Honda MR-50 50-pin male connector for expansion (not used)
	348	Sub PCB Layout
	349	--------------
	350
	351	A20B-1000-0720/02B
	352	\|--------------------------------\|
	353	\| CNA CNB CNC CND \|
	354	\| \|
	355	\| MB15542 CNE\|
	356	\| \|
	357	\| HD6845S D8085\|
	358	\| 16MHz \|
	359	\| \|
	360	\| X \|
	361	\| XXXXXXXX \|
	362	\| XXXXXXXX \|
	363	\| XXXXXXXX 6264 A41_010B.28B\|
	364	\| 6264 A41_020A.30B\|
	365	\|--------------------------------\|
	366	Notes:
	367	D8085 - NEC D8085A-2 CPU. Clock input 8.000MHz [16/2].
	368	Note 8085 has internal /2 divider so actual clock speed is 4.000MHz
	369	HD6845S - Hitachi HD6845S / HD46505S CRT Controller. Clock input 2.000MHz [8/2]
	370	6264 - Hitachi HM6264P-15 8k x 8-bit SRAM
	371	XXXXXXX - Fujitsu MB8265-15 65536 x1-bit DRAM (25 chips total)
	372	MB15542 - Fujitsu MB15542 Custom Chip
	373	A41_010B- Intel D27128 16k x8-bit EPROM
	374	A42_020A- Hitachi 27256G 32k x8-bit EPROM
	375	CNA - 50-pin flat cable joining to Main PCB
	376	CNB - 50-pin flat cable joining to Main PCB
	377	CNC - 6-pin power cable joining to Main PCB
	378	CND - 20-pin flat cable joining to CRT Unit (video output)
	379	CNE - Fanuc Honda MR-50 50-pin male connector for expansion (not used)
	380	HSync - 22.7273kHz
	381	VSync - 54.6330Hz
	382
	383
	384	Block Diagram
	385	-------------
	386	Below is the block diagram shown in the Maintenance Manual.
	387	The arrows denote direction of data flow.
	388
	389	\|-------\| \|--------\| \|----------------\|
	390	\|Sub CPU\| \|Main CPU\|<---->\|Math Coprocessor\|
	391	\|-------\| \|--------\| \|----------------\|
	392	/\ /\ /\
	393	\| \| \|
	394	\| \/ \/
	395	\|-----\| \| \|------------------\|
	396	\|EPROM\|<--->\| /\
	397	\|-----\| \| \|---------------\| \| \|----------------\|
	398	\| \| Common memory \|<---------------------------------->\|<--->\|RS232C interface\|---CN1
	399	\|<-------->\|===============\| \| \|----------------\|
	400	\| /-->\| Graphic memory\|------\| \|
	401	\| \| \|---------------\| \| \| \|----------------\|
	402	\| \| \| \|--------\| \|<--->\|RS232C interface\|---CN2
	403	\| \| \| \| BOOT \|<-------->\| \|----------------\|
	404	\| \| \| \| EPROM \| \|
	405	\| \| \|----------------\| \| \|--------\| \| \|----------------\|
	406	\|<-----\|-->\|Character memory\|--\| \| \|<--->\|RS232C interface\|---CN3
	407	\| \|-->\|----------------\| \| \| \|--------\| \| \|----------------\|
	408	\| \| \| \| \|Main RAM\|<-------->\|
	409	\| \| \| \| \|--------\| \| \|----------------\|
	410	\| \| \| \| \|<--->\|RS232C interface\|---CN4
	411	\| \| \| \| \| \|----------------\|
	412	\|---------\| \| \| \/ \/ \|
	413	\|Keyboard \| \/ \---\|---------------------------\| \| \|-----------------\| CN9 \|--------\|
	414	\|interface\|<->\|<-------->\| CRT control circuit \| \|<--->\|Floppy controller\|---O---\|FDD UNIT\|
	415	\|----\|----\| \|-------------\|-------------\| \| \|-----------------\| \|--------\|
	416	\| \| \|
	417	\| \| \/
	418	O CN6 O CN8 O CN5
	419	\| \|
	420	\| \|
	421	\|---\|----\| \|----\|----\|
	422	\|Keyboard\| \| Screen \|
	423	\|--------\| \|---------\|
364	424
365	425
366		Tech notes:
367		- Once the big ASCII-art boot screen appears, you must press the "LOAD" key
368		a few times to initiate booting from the floppy drive.
369
370
371		The block diagram in the Maintenance Manual looks like this:
372
373		\|sub CPU\| \|main CPU\|---\|math coprocessor\|
374		\| \| \|
375		\|EPROM\|----\| \|---------------/
376		\|-------------\| Common memory / graphic memory \| ------------------\|
377		\| \| \|--------\|RS232C interface\|---CN1
378		\| \| \|EPROM\|-----\|--------\|RS232C interface\|---CN2
379		\|----\|character memory\| \| \|--------\|RS232C interface\|---CN3
380		\| \| \| \|main RAM\|--\|--------\|RS232C interface\|---CN4
381		\| \| \| \|
382		\|----\| CRTC and video circuits \|---CN8 \| floppy controller \|----CN9
383		\|
384		\|keyboard interface\|---CN6
385
386
387	426	TODO:
388		- Find char gen data. Is it inside the MB15542 custom? :-(
389		- What's the a42_020a.30b ROM do? Both CPUs are currently happy without it,
390		and it doesn't appear to contain valid 8086 or 8085 code.
391	427	- Is the VRAM hookup anything like correct?
392	428	- Hookup enough keyboard to get it to boot a floppy, the FAPT DOCTOR
393	429	program will be invaluable to answering many questions.
394	430	- Shared RAM is 8k, but there are 2 6264s on the sub board. Is shared RAM
395	431	banked?
	432	- I/O is at F00xx:
	433	':maincpu' (FC15A): unmapped program memory write to F0012 = 00CE & 00FF
	434	':maincpu' (FC15D): unmapped program memory write to F0016 = 00CE & 00FF
	435	':maincpu' (FC160): unmapped program memory write to F001A = 00CE & 00FF
	436	':maincpu' (FC163): unmapped program memory write to F001E = 00CE & 00FF
	437	':maincpu' (FC16D): unmapped program memory write to F000E = 0034 & 00FF
	438	':maincpu' (FC172): unmapped program memory write to F0008 = 00D4 & 00FF
	439	':maincpu' (FC177): unmapped program memory write to F0008 = 0030 & 00FF
	440	':maincpu' (FC17C): unmapped program memory write to F000E = 0056 & 00FF
	441	':maincpu' (FC181): unmapped program memory write to F000A = 0010 & 00FF
	442	':maincpu' (FC186): unmapped program memory write to F000E = 0096 & 00FF
	443	':maincpu' (FC18B): unmapped program memory write to F000C = 0010 & 00FF
	444	':maincpu' (FC190): unmapped program memory write to F004E = 0034 & 00FF
	445	':maincpu' (FC195): unmapped program memory write to F0048 = 0020 & 00FF
	446	':maincpu' (FC19A): unmapped program memory write to F0048 = 004E & 00FF
	447	':maincpu' (FC19F): unmapped program memory write to F004E = 0056 & 00FF
	448	':maincpu' (FC1A4): unmapped program memory write to F004A = 0010 & 00FF
	449	':maincpu' (FC1A9): unmapped program memory write to F004E = 0096 & 00FF
	450	':maincpu' (FC1AE): unmapped program memory write to F004C = 0010 & 00FF
396	451
397	452	****************************************************************************/
398	453
r29424	r29425
481	536	DECLARE_READ8_MEMBER(keyboard_r);
482	537	DECLARE_WRITE8_MEMBER(video_ctrl_w);
483	538
	539	DECLARE_READ8_MEMBER(test_r);
	540	DECLARE_READ8_MEMBER(vbl_r);
	541
484	542	DECLARE_WRITE_LINE_MEMBER(vsync_w);
485	543
486	544	DECLARE_DRIVER_INIT(fanucspmg);
r29424	r29425
493	551	INT32 m_vram_bank;
494	552	UINT8 m_vbl_ctrl;
495	553	UINT8 m_keyboard_row;
	554	UINT8 m_vbl_stat;
496	555	};
497	556
498	557	DRIVER_INIT_MEMBER(fanucspmg_state, fanucspmg)
r29424	r29425
516	575	m_shared[offset] = data;
517	576	}
518	577
	578	READ8_MEMBER(fanucspmg_state::test_r)
	579	{
	580	return 0x00; // 0x80 to start weird not-sure-what process which may be FDC related
	581	}
	582
	583	READ8_MEMBER(fanucspmg_state::vbl_r)
	584	{
	585	return m_vbl_stat;
	586	}
	587
519	588	static ADDRESS_MAP_START(maincpu_mem, AS_PROGRAM, 16, fanucspmg_state)
520	589	AM_RANGE(0x00000, 0x7ffff) AM_RAM // main RAM
521	590
522		AM_RANGE(0xf0000, 0xf00ff) AM_RA~~M // not su~~re if ~~this is RAM or I/O~~
	591	AM_RANGE(0x88000, 0x88001) AM_READ8(vbl_r, 0xffff)
523	592
	593	AM_RANGE(0xf0004, 0xf0005) AM_READ8(test_r, 0xffff)
	594
524	595	AM_RANGE(0xf8000, 0xf9fff) AM_READWRITE8(shared_r, shared_w, 0xffff)
525
526	596	AM_RANGE(0xfc000, 0xfffff) AM_ROM AM_REGION(MAINCPU_TAG, 0)
527	597	ADDRESS_MAP_END
528	598
r29424	r29425
538	608	m_subcpu->set_input_line(I8085_RST75_LINE, ASSERT_LINE);
539	609	}
540	610	}
	611
	612	m_vbl_stat = (state == ASSERT_LINE) ? 1 : 0;
541	613	}
542	614
543	615	READ8_MEMBER(fanucspmg_state::vram1_r)
r29424	r29425
572	644	return 0xff;
573	645	}
574	646
	647	// bit 1 seems to route to bit 7 of f0004 on the 8086 (signals the "LOAD" key pressed?)
575	648	// bit 3 appears to enable vblank IRQs
576	649	WRITE8_MEMBER(fanucspmg_state::vbl_ctrl_w)
577	650	{
r29424	r29425
725	798
726	799	static MACHINE_CONFIG_START( fanucspmg, fanucspmg_state )
727	800	/* basic machine hardware */
728		MCFG_CPU_ADD(MAINCPU_TAG, I8086, XTAL_15MHz/~~4) // guess -~~ 3~~.75 MHz~~
	801	MCFG_CPU_ADD(MAINCPU_TAG, I8086, XTAL_15MHz/3)
729	802	MCFG_CPU_PROGRAM_MAP(maincpu_mem)
730	803	MCFG_CPU_IO_MAP(maincpu_io)
731	804
732		MCFG_CPU_ADD(SUBCPU_TAG, I8085A, XTAL_16MHz/8) /~~/ part is -~~2 ~~rated~~
	805	MCFG_CPU_ADD(SUBCPU_TAG, I8085A, XTAL_16MHz/2/2)
733	806	MCFG_CPU_PROGRAM_MAP(subcpu_mem)
734	807
735	808	MCFG_DEVICE_ADD(USART0_TAG, I8251, 0)
r29424	r29425
738	811	MCFG_DEVICE_ADD(USART3_TAG, I8251, 0)
739	812
740	813	MCFG_DEVICE_ADD(PIT0_TAG, PIT8253, 0)
741		MCFG_PIT8253_CLK0(XTAL_15MHz/4)
742		MCFG_PIT8253_CLK1(XTAL_15MHz/4)
743		MCFG_PIT8253_CLK2(XTAL_15MHz/4)
	814	MCFG_PIT8253_CLK0(XTAL_15MHz/12)
	815	MCFG_PIT8253_CLK1(XTAL_15MHz/12)
	816	MCFG_PIT8253_CLK2(XTAL_15MHz/12)
744	817	MCFG_DEVICE_ADD(PIT1_TAG, PIT8253, 0)
745		MCFG_PIT8253_CLK0(XTAL_15MHz/4)
746		MCFG_PIT8253_CLK1(XTAL_15MHz/4)
747		MCFG_PIT8253_CLK2(XTAL_15MHz/4)
	818	MCFG_PIT8253_CLK0(XTAL_15MHz/12)
	819	MCFG_PIT8253_CLK1(XTAL_15MHz/12)
	820	MCFG_PIT8253_CLK2(XTAL_15MHz/12)
748	821
749		MCFG_I8257_ADD(DMAC_TAG, XTAL_15MHz / 4, fanucspmg_dma)
	822	MCFG_I8257_ADD(DMAC_TAG, XTAL_15MHz / 5, fanucspmg_dma)
750	823
751	824	MCFG_PIC8259_ADD(PIC0_TAG, INPUTLINE("maincpu", 0), VCC, NULL)
752	825	MCFG_PIC8259_ADD(PIC1_TAG, INPUTLINE("maincpu", 0), VCC, NULL)
r29424	r29425
759	832	MCFG_SCREEN_RAW_PARAMS(XTAL_15MHz, 640, 0, 512, 390, 0, 384 )
760	833	MCFG_SCREEN_UPDATE_DEVICE( CRTC_TAG, mc6845_device, screen_update )
761	834
762		MCFG_MC6845_ADD( CRTC_TAG, HD6845, SCREEN_TAG, XTAL_15MHz/3, mc6845_fanuc_intf)
	835	MCFG_MC6845_ADD( CRTC_TAG, HD6845, SCREEN_TAG, XTAL_8MHz/2, mc6845_fanuc_intf)
763	836	MACHINE_CONFIG_END
764	837
765	838	/* ROM definition */

branches/new_menus/src/mess/drivers/a7800.c
r29424	r29425
75	75	2014/01/02 Robert Tuccitto Corrected joystick buttons assignment & minor
76	76	palette notes cleanup.
77	77
78		2014/01/09 Robert Tuccitto Positional description for difficulty
79		switches added.
	78	2014/01/09 Robert Tuccitto Positional description for difficulty
	79	switches added.
80	80
81		2014/02/15 Robert Tuccitto Added more details and clarification
82		regarding the potentiometer.
	81	2014/02/15 Robert Tuccitto Added more details and clarification
	82	regarding the potentiometer.
83	83
84		2014/03/25 Mike Saarna Fixed Riot Timer
	84	2014/03/25 Mike Saarna Fixed Riot Timer
85	85	***************************************************************************/
86	86
87	87	#include "emu.h"
r29424	r29425
259	259	structure order and have similar appearance differences that are dependent
260	260	upon display type.
261	261	***************************************************************************/
	262
262	263	/***************************************************************************
263		PALETTE - 26.2 PHASE SHIFT
	264	PALETTE - 25.7 PHASE SHIFT
264	265	***************************************************************************/
265	266
266	267	#define NTSC_GREY \
267		rgb_t(0x00,0x00,0x00), rgb_t(0x11,0x11,0x11), rgb_t(0x22,0x22,0x22), rgb_t(0x33,0x33,0x33), \
268		rgb_t(0x44,0x44,0x44), rgb_t(0x55,0x55,0x55), rgb_t(0x66,0x66,0x66), rgb_t(0x77,0x77,0x77), \
269		rgb_t(0x88,0x88,0x88), rgb_t(0x99,0x99,0x99), rgb_t(0xAA,0xAA,0xAA), rgb_t(0xBB,0xBB,0xBB), \
270		rgb_t(0xCC,0xCC,0xCC), rgb_t(0xDD,0xDD,0xDD), rgb_t(0xEE,0xEE,0xEE), rgb_t(0xFF,0xFF,0xFF )
	268	rgb_t(0x00,0x00,0x00), rgb_t(0x11,0x11,0x11), rgb_t(0x22,0x22,0x22), rgb_t(0x33,0x33,0x33), \
	269	rgb_t(0x44,0x44,0x44), rgb_t(0x55,0x55,0x55), rgb_t(0x66,0x66,0x66), rgb_t(0x77,0x77,0x77), \
	270	rgb_t(0x88,0x88,0x88), rgb_t(0x99,0x99,0x99), rgb_t(0xAA,0xAA,0xAA), rgb_t(0xBB,0xBB,0xBB), \
	271	rgb_t(0xCC,0xCC,0xCC), rgb_t(0xDD,0xDD,0xDD), rgb_t(0xEE,0xEE,0xEE), rgb_t(0xFF,0xFF,0xFF )
271	272
272	273	#define NTSC_GOLD \
273		rgb_t(0x1A,0x07,0x00), rgb_t(0x2B,0x18,0x00), rgb_t(0x3C,0x29,0x00), rgb_t(0x4D,0x3A,0x00), \
274		rgb_t(0x5E,0x4B,0x00), rgb_t(0x6F,0x5C,0x00), rgb_t(0x80,0x6D,0x00), rgb_t(0x91,0x7E,0x09), \
275		rgb_t(0xA2,0x8F,0x1A), rgb_t(0xB3,0xA0,0x2B), rgb_t(0xC4,0xB1,0x3C), rgb_t(0xD5,0xC2,0x4D), \
276		rgb_t(0xE6,0xD3,0x5E), rgb_t(0xF7,0xE4,0x6F), rgb_t(0xFF,0xF5,0x83), rgb_t(0xFF,0xF7,0x97 )
	274	rgb_t(0x1A,0x07,0x00), rgb_t(0x2B,0x18,0x00), rgb_t(0x3C,0x29,0x00), rgb_t(0x4D,0x3A,0x00), \
	275	rgb_t(0x5E,0x4B,0x00), rgb_t(0x6F,0x5C,0x00), rgb_t(0x80,0x6D,0x00), rgb_t(0x91,0x7E,0x09), \
	276	rgb_t(0xA2,0x8F,0x1A), rgb_t(0xB3,0xA0,0x2B), rgb_t(0xC4,0xB1,0x3C), rgb_t(0xD5,0xC2,0x4D), \
	277	rgb_t(0xE6,0xD3,0x5E), rgb_t(0xF7,0xE4,0x6F), rgb_t(0xFF,0xF5,0x83), rgb_t(0xFF,0xF7,0x97 )
277	278
278	279	#define NTSC_ORANGE \
279		rgb_t(0x31,0x00,0x00), rgb_t(0x42,0x06,0x00), rgb_t(0x53,0x17,0x00), rgb_t(0x64,0x28,0x00), \
280		rgb_t(0x75,0x39,0x00), rgb_t(0x86,0X4A,0x00), rgb_t(0x97,0x5B,0x0B), rgb_t(0xA8,0x6C,0x1C), \
281		rgb_t(0xB9,0x7D,0x2D), rgb_t(0xCA,0x8E,0x3E), rgb_t(0xDB,0x9F,0x4F), rgb_t(0xEC,0xB0,0x60), \
282		rgb_t(0xFD,0xC1,0x71), rgb_t(0xFF,0xD2,0x86), rgb_t(0xFF,0xE3,0x9D), rgb_t(0xFF,0xF4,0xB3 )
	280	rgb_t(0x31,0x00,0x00), rgb_t(0x42,0x06,0x00), rgb_t(0x53,0x17,0x00), rgb_t(0x64,0x28,0x00), \
	281	rgb_t(0x75,0x39,0x00), rgb_t(0x86,0X4A,0x00), rgb_t(0x97,0x5B,0x0A), rgb_t(0xA8,0x6C,0x1B), \
	282	rgb_t(0xB9,0x7D,0x2C), rgb_t(0xCA,0x8E,0x3D), rgb_t(0xDB,0x9F,0x4E), rgb_t(0xEC,0xB0,0x5F), \
	283	rgb_t(0xFD,0xC1,0x70), rgb_t(0xFF,0xD2,0x85), rgb_t(0xFF,0xE3,0x9C), rgb_t(0xFF,0xF4,0xB2 )
283	284
284	285	#define NTSC_RED_ORANGE \
285		rgb_t(0x3E,0x00,0x00), rgb_t(0x4F,0x00,0x00), rgb_t(0x60,0x08,0x00), rgb_t(0x71,0x19,0x00), \
286		rgb_t(0x82,0x2A,0x0F), rgb_t(0x93,0x3B,0x20), rgb_t(0xA4,0x4C,0x31), rgb_t(0xB5,0x5D,0x42), \
287		rgb_t(0xC6,0x6E,0x53), rgb_t(0xD7,0x7F,0x64), rgb_t(0xE8,0x90,0x75), rgb_t(0xF9,0xA1,0x86), \
288		rgb_t(0xFF,0xB2,0x9A), rgb_t(0xFF,0xC3,0xB0), rgb_t(0xFF,0xD4,0xC6), rgb_t(0xFF,0xE5,0xDC )
	286	rgb_t(0x3E,0x00,0x00), rgb_t(0x4F,0x00,0x00), rgb_t(0x60,0x08,0x00), rgb_t(0x71,0x19,0x00), \
	287	rgb_t(0x82,0x2A,0x0D), rgb_t(0x93,0x3B,0x1E), rgb_t(0xA4,0x4C,0x2F), rgb_t(0xB5,0x5D,0x40), \
	288	rgb_t(0xC6,0x6E,0x51), rgb_t(0xD7,0x7F,0x62), rgb_t(0xE8,0x90,0x73), rgb_t(0xF9,0xA1,0x83), \
	289	rgb_t(0xFF,0xB2,0x98), rgb_t(0xFF,0xC3,0xAE), rgb_t(0xFF,0xD4,0xC4), rgb_t(0xFF,0xE5,0xDA )
289	290
290	291	#define NTSC_PINK \
291		rgb_t(0x3E,0x00,0x06), rgb_t(0x4F,0x00,0x12), rgb_t(0x60,0x00,0x1E), rgb_t(0x71,0x0E,0x2E), \
292		rgb_t(0x82,0x1F,0x3F), rgb_t(0x93,0x30,0x50), rgb_t(0xA4,0x41,0x61), rgb_t(0xB5,0x52,0x72), \
293		rgb_t(0xC6,0x63,0x83), rgb_t(0xD7,0x74,0x94), rgb_t(0xE8,0x85,0xA5), rgb_t(0xF9,0x96,0xB6), \
294		rgb_t(0xFF,0xA7,0xCB), rgb_t(0xFF,0xB8,0xE1), rgb_t(0xFF,0xC9,0xEF), rgb_t(0xFF,0xDA,0xF4 )
	292	rgb_t(0x3F,0x00,0x03), rgb_t(0x50,0x00,0x0F), rgb_t(0x61,0x00,0x1B), rgb_t(0x72,0x0F,0x2B), \
	293	rgb_t(0x83,0x20,0x3C), rgb_t(0x94,0x31,0x4D), rgb_t(0xA5,0x42,0x5E), rgb_t(0xB6,0x53,0x6F), \
	294	rgb_t(0xC7,0x64,0x80), rgb_t(0xD8,0x75,0x91), rgb_t(0xE9,0x86,0xA2), rgb_t(0xFA,0x97,0xB3), \
	295	rgb_t(0xFF,0xA8,0xC8), rgb_t(0xFF,0xB9,0xDE), rgb_t(0xFF,0xCA,0xEF), rgb_t(0xFF,0xDB,0xF4 )
295	296
296	297	#define NTSC_PURPLE \
297		rgb_t(0x32,0x00,0x38), rgb_t(0x43,0x00,0x44), rgb_t(0x54,0x00,0x50), rgb_t(0x65,0x0C,0x5F), \
298		rgb_t(0x76,0x1D,0x70), rgb_t(0x87,0x2E,0x81), rgb_t(0x98,0x3F,0x92), rgb_t(0xA9,0x50,0xA3), \
299		rgb_t(0xBA,0x61,0xB4), rgb_t(0xCB,0x72,0xC5), rgb_t(0xDC,0x83,0xD6), rgb_t(0xED,0x94,0xE4), \
300		rgb_t(0xFE,0xA5,0xE4), rgb_t(0xFF,0xB6,0xE9), rgb_t(0xFF,0xC7,0xEE), rgb_t(0xFF,0xD8,0xF3 )
	298	rgb_t(0x33,0x00,0x35), rgb_t(0x44,0x00,0x41), rgb_t(0x55,0x00,0x4C), rgb_t(0x66,0x0C,0x5C), \
	299	rgb_t(0x77,0x1D,0x6D), rgb_t(0x88,0x2E,0x7E), rgb_t(0x99,0x3F,0x8F), rgb_t(0xAA,0x50,0xA0), \
	300	rgb_t(0xBB,0x61,0xB1), rgb_t(0xCC,0x72,0xC2), rgb_t(0xDD,0x83,0xD3), rgb_t(0xEE,0x94,0xE4), \
	301	rgb_t(0xFF,0xA5,0xE4), rgb_t(0xFF,0xB6,0xE9), rgb_t(0xFF,0xC7,0xEE), rgb_t(0xFF,0xD8,0xF3 )
301	302
302	303	#define NTSC_PURPLE_BLUE \
303		rgb_t(0x1B,0x00,0x5F), rgb_t(0x2C,0x00,0x6B), rgb_t(0x3D,0x00,0x77), rgb_t(0x4E,0x11,0x88), \
304		rgb_t(0x5F,0x22,0x99), rgb_t(0x70,0x33,0xAA), rgb_t(0x81,0x44,0xBB), rgb_t(0x92,0x55,0xCC), \
305		rgb_t(0xA3,0x66,0xDD), rgb_t(0xB4,0x77,0xED), rgb_t(0xC5,0x88,0xED), rgb_t(0xD6,0x99,0xED), \
306		rgb_t(0xE7,0xAA,0xED), rgb_t(0xF8,0xBB,0xED), rgb_t(0xFF,0xCC,0xF0), rgb_t(0xFF,0xDD,0xF5 )
	304	rgb_t(0x1D,0x00,0x5C), rgb_t(0x2E,0x00,0x68), rgb_t(0x40,0x00,0x74), rgb_t(0x51,0x10,0x84), \
	305	rgb_t(0x62,0x21,0x95), rgb_t(0x73,0x32,0xA6), rgb_t(0x84,0x43,0xB7), rgb_t(0x95,0x54,0xC8), \
	306	rgb_t(0xA6,0x65,0xD9), rgb_t(0xB7,0x76,0xEA), rgb_t(0xC8,0x87,0xEB), rgb_t(0xD9,0x98,0xEB), \
	307	rgb_t(0xE9,0xA9,0xEC), rgb_t(0xFB,0xBA,0xEB), rgb_t(0xFF,0xCB,0xEF), rgb_t(0xFF,0xDC,0xF4 )
307	308
308	309	#define NTSC_BLUE1 \
309		rgb_t(0x00,0x00,0x72), rgb_t(0x10,0x00,0x7E), rgb_t(0x21,0x0D,0x8E), rgb_t(0x32,0x1E,0x9F), \
310		rgb_t(0x43,0x2F,0xB0), rgb_t(0x54,0x40,0xC1), rgb_t(0x65,0x51,0xD2), rgb_t(0x76,0x62,0xE3), \
311		rgb_t(0x87,0x73,0xF4), rgb_t(0x98,0x84,0xF9), rgb_t(0xA9,0x95,0xF9), rgb_t(0xBA,0xA6,0xF9), \
312		rgb_t(0xCB,0xB7,0xF9), rgb_t(0xDC,0xC8,0xF9), rgb_t(0xED,0xD9,0xF9), rgb_t(0xFE,0xEA,0xF9 )
	310	rgb_t(0x02,0x00,0x71), rgb_t(0x13,0x00,0x7D), rgb_t(0x24,0x0B,0x8C), rgb_t(0x35,0x1C,0x9D), \
	311	rgb_t(0x46,0x2D,0xAE), rgb_t(0x57,0x3E,0xBF), rgb_t(0x68,0x4F,0xD0), rgb_t(0x79,0x60,0xE1), \
	312	rgb_t(0x8A,0x71,0xF2), rgb_t(0x9B,0x82,0xF7), rgb_t(0xAC,0x93,0xF7), rgb_t(0xBD,0xA4,0xF7), \
	313	rgb_t(0xCE,0xB5,0xF7), rgb_t(0xDF,0xC6,0xF7), rgb_t(0xF0,0xD7,0xF7), rgb_t(0xFF,0xE8,0xF8 )
313	314
314	315	#define NTSC_BLUE2 \
315		rgb_t(0x00,0x00,0x65), rgb_t(0x00,0x0C,0x7A), rgb_t(0x05,0x1D,0x8E), rgb_t(0x16,0x2E,0x9F), \
316		rgb_t(0x27,0x3F,0xB0), rgb_t(0x38,0x50,0xC1), rgb_t(0x49,0x61,0xD2), rgb_t(0x5A,0x72,0xE3), \
317		rgb_t(0x6B,0x83,0xF4), rgb_t(0x7C,0x94,0xFF), rgb_t(0x8D,0xA5,0xFF), rgb_t(0x9E,0xB6,0xFF), \
318		rgb_t(0xAF,0xC7,0xFF), rgb_t(0xC0,0xD8,0xFF), rgb_t(0xD1,0xE9,0xFF), rgb_t(0xE2,0xFA,0xFF )
	316	rgb_t(0x00,0x00,0x68), rgb_t(0x00,0x0A,0x7C), rgb_t(0x08,0x1B,0x90), rgb_t(0x19,0x2C,0xA1), \
	317	rgb_t(0x2A,0x3D,0xB2), rgb_t(0x3B,0x4E,0xC3), rgb_t(0x4C,0x5F,0xD4), rgb_t(0x5D,0x70,0xE5), \
	318	rgb_t(0x6E,0x81,0xF6), rgb_t(0x7F,0x92,0xFF), rgb_t(0x90,0xA3,0xFF), rgb_t(0xA1,0xB4,0xFF), \
	319	rgb_t(0xB2,0xC5,0xFF), rgb_t(0xC3,0xD6,0xFF), rgb_t(0xD4,0xE7,0xFF), rgb_t(0xE5,0xF8,0xFF )
319	320
320	321	#define NTSC_LIGHT_BLUE \
321		rgb_t(0x00,0x0D,0x48), rgb_t(0x00,0x1E,0x5E), rgb_t(0x00,0x2F,0x74), rgb_t(0x00,0x40,0x8A), \
322		rgb_t(0x11,0x51,0x9B), rgb_t(0x22,0x62,0xAC), rgb_t(0x33,0x73,0xBD), rgb_t(0x44,0x84,0xCE), \
323		rgb_t(0x55,0x95,0xDF), rgb_t(0x66,0xA6,0xF0), rgb_t(0x77,0xB7,0xFF), rgb_t(0x88,0xC8,0xFF), \
324		rgb_t(0x99,0xD9,0xFF), rgb_t(0xAA,0xEA,0xFF), rgb_t(0xBB,0xFB,0xFF), rgb_t(0xCC,0xFF,0xFF )
	322	rgb_t(0x00,0x0A,0x4D), rgb_t(0x00,0x1B,0x63), rgb_t(0x00,0x2C,0x79), rgb_t(0x02,0x3D,0x8F), \
	323	rgb_t(0x13,0x4E,0xA0), rgb_t(0x24,0x5F,0xB1), rgb_t(0x35,0x70,0xC2), rgb_t(0x46,0x81,0xD3), \
	324	rgb_t(0x57,0x92,0xE4), rgb_t(0x68,0xA3,0xF5), rgb_t(0x79,0xB4,0xFF), rgb_t(0x8A,0xC5,0xFF), \
	325	rgb_t(0x9B,0xD6,0xFF), rgb_t(0xAC,0xE7,0xFF), rgb_t(0xBD,0xF8,0xFF), rgb_t(0xCE,0xFF,0xFF )
325	326
326	327	#define NTSC_TURQUOISE \
327		rgb_t(0x00,0x1C,0x1C), rgb_t(0x00,0x2D,0x32), rgb_t(0x00,0x3E,0x49), rgb_t(0x00,0x4F,0x5F), \
328		rgb_t(0x05,0x60,0x73), rgb_t(0x16,0x71,0x84), rgb_t(0x27,0x82,0x95), rgb_t(0x38,0x93,0xA6), \
329		rgb_t(0x49,0xA4,0xB7), rgb_t(0x5A,0xB5,0xC8), rgb_t(0x6B,0xC6,0xD9), rgb_t(0x7C,0xD7,0xEA), \
330		rgb_t(0x8D,0xE8,0xFB), rgb_t(0x9E,0xF9,0xFF), rgb_t(0xAF,0xFF,0xFF), rgb_t(0xC0,0xFF,0xFF )
	328	rgb_t(0x00,0x1A,0x26), rgb_t(0x00,0x2B,0x3C), rgb_t(0x00,0x3C,0x52), rgb_t(0x00,0x4D,0x68), \
	329	rgb_t(0x06,0x5E,0x7C), rgb_t(0x17,0x6F,0x8D), rgb_t(0x28,0x80,0x9E), rgb_t(0x39,0x91,0xAF), \
	330	rgb_t(0x4A,0xA2,0xC0), rgb_t(0x5B,0xB3,0xD1), rgb_t(0x6C,0xC4,0xE2), rgb_t(0x7D,0xD5,0xF3), \
	331	rgb_t(0x8E,0xE6,0xFF), rgb_t(0x9F,0xF7,0xFF), rgb_t(0xB0,0xFF,0xFF), rgb_t(0xC1,0xFF,0xFF )
331	332
332	333	#define NTSC_GREEN_BLUE \
333		rgb_t(0x00,0x25,0x0B), rgb_t(0x00,0x36,0x10), rgb_t(0x00,0x47,0x18), rgb_t(0x00,0x58,0x2E), \
334		rgb_t(0x07,0x69,0x42), rgb_t(0x18,0x7A,0x53), rgb_t(0x29,0x8B,0x64), rgb_t(0x3A,0x9C,0x75), \
335		rgb_t(0x4B,0xAD,0x86), rgb_t(0x5C,0xBE,0x97), rgb_t(0x6D,0xCF,0xA8), rgb_t(0x7E,0xE0,0xB9), \
336		rgb_t(0x8F,0xF1,0xCA), rgb_t(0xA0,0xFF,0xDA), rgb_t(0xB1,0xFF,0xE6), rgb_t(0xC2,0xFF,0xF2 )
	334	rgb_t(0x00,0x24,0x0B), rgb_t(0x00,0x35,0x10), rgb_t(0x00,0x46,0x22), rgb_t(0x00,0x57,0x38), \
	335	rgb_t(0x05,0x68,0x4D), rgb_t(0x16,0x79,0x5E), rgb_t(0x27,0x8A,0x6F), rgb_t(0x38,0x9B,0x80), \
	336	rgb_t(0x49,0xAC,0x91), rgb_t(0x5A,0xBD,0xA2), rgb_t(0x6B,0xCE,0xB3), rgb_t(0x7C,0xDF,0xC4), \
	337	rgb_t(0x8D,0xF0,0xD5), rgb_t(0x9E,0xFF,0xE5), rgb_t(0xAF,0xFF,0xF1), rgb_t(0xC0,0xFF,0xFD )
337	338
338	339	#define NTSC_GREEN \
339		rgb_t(0x00,0x27,0x0C), rgb_t(0x00,0x38,0x11), rgb_t(0x00,0x49,0x16), rgb_t(0x04,0x5A,0x1A), \
340		rgb_t(0x15,0x6B,0x1A), rgb_t(0x26,0x7C,0x22), rgb_t(0x37,0x8D,0x33), rgb_t(0x48,0x9E,0x44), \
341		rgb_t(0x59,0xAF,0x55), rgb_t(0x6A,0xC0,0x66), rgb_t(0x7B,0xD1,0x77), rgb_t(0x8C,0xE2,0x88), \
342		rgb_t(0x9D,0xF3,0x99), rgb_t(0xAE,0xFF,0xA8), rgb_t(0xBF,0xFF,0xB4), rgb_t(0xD0,0xFF,0xC0 )
	340	rgb_t(0x00,0x27,0x0C), rgb_t(0x00,0x38,0x11), rgb_t(0x00,0x49,0x16), rgb_t(0x00,0x5A,0x1B), \
	341	rgb_t(0x10,0x6B,0x1B), rgb_t(0x21,0x7C,0x2C), rgb_t(0x32,0x8D,0x3D), rgb_t(0x43,0x9E,0x4E), \
	342	rgb_t(0x54,0xAF,0x5F), rgb_t(0x65,0xC0,0x70), rgb_t(0x76,0xD1,0x81), rgb_t(0x87,0xE2,0x92), \
	343	rgb_t(0x98,0xF3,0xA3), rgb_t(0xA9,0xFF,0xB3), rgb_t(0xBA,0xFF,0xBF), rgb_t(0xCB,0xFF,0xCB )
343	344
344	345	#define NTSC_YELLOW_GREEN \
345		rgb_t(0x00,0x21,0x0A), rgb_t(0x00,0x32,0x0F), rgb_t(0x0A,0x43,0x11), rgb_t(0x1B,0x54,0x11), \
346		rgb_t(0x2C,0x65,0x11), rgb_t(0x3D,0x76,0x11), rgb_t(0x4E,0x87,0x11), rgb_t(0x5F,0x98,0x1E), \
347		rgb_t(0x70,0xA9,0x2F), rgb_t(0x81,0xBA,0x40), rgb_t(0x92,0xCB,0x51), rgb_t(0xA3,0xDC,0x62), \
348		rgb_t(0xB4,0xED,0x73), rgb_t(0xC5,0xFE,0x84), rgb_t(0xD6,0xFF,0x90), rgb_t(0xE7,0xFF,0x9C )
	346	rgb_t(0x00,0x23,0x0A), rgb_t(0x00,0x34,0x10), rgb_t(0x04,0x45,0x13), rgb_t(0x15,0x56,0x13), \
	347	rgb_t(0x26,0x67,0x13), rgb_t(0x37,0x78,0x13), rgb_t(0x48,0x89,0x14), rgb_t(0x59,0x9A,0x25), \
	348	rgb_t(0x6A,0xAB,0x36), rgb_t(0x7B,0xBC,0x47), rgb_t(0x8C,0xCD,0x58), rgb_t(0x9D,0xDE,0x69), \
	349	rgb_t(0xAE,0xEF,0x7A), rgb_t(0xBF,0xFF,0x8B), rgb_t(0xD0,0xFF,0x97), rgb_t(0xE1,0xFF,0xA3 )
349	350
350	351	#define NTSC_ORANGE_GREEN \
351		rgb_t(0x05,0x13,0x04), rgb_t(0x16,0x24,0x04), rgb_t(0x27,0x35,0x04), rgb_t(0x38,0x46,0x04), \
352		rgb_t(0x49,0x57,0x04), rgb_t(0x5A,0x68,0x04), rgb_t(0x6B,0x79,0x04), rgb_t(0x7C,0x8A,0x09), \
353		rgb_t(0x8D,0x9B,0x1A), rgb_t(0x9E,0xAC,0x2B), rgb_t(0xAF,0xBD,0x3C), rgb_t(0xC0,0xCE,0x4D), \
354		rgb_t(0xD1,0xDF,0x5E), rgb_t(0xE2,0xF0,0x6F), rgb_t(0xF3,0xFF,0x80), rgb_t(0xFF,0xFF,0x8D )
	352	rgb_t(0x00,0x17,0x07), rgb_t(0x0E,0x28,0x08), rgb_t(0x1F,0x39,0x08), rgb_t(0x30,0x4A,0x08), \
	353	rgb_t(0x41,0x5B,0x08), rgb_t(0x52,0x6C,0x08), rgb_t(0x63,0x7D,0x08), rgb_t(0x74,0x8E,0x0D), \
	354	rgb_t(0x85,0x9F,0x1E), rgb_t(0x96,0xB0,0x2F), rgb_t(0xA7,0xC1,0x40), rgb_t(0xB8,0xD2,0x51), \
	355	rgb_t(0xC9,0xE3,0x62), rgb_t(0xDA,0xF4,0x73), rgb_t(0xEB,0xFF,0x82), rgb_t(0xFC,0xFF,0x8E )
355	356
356	357	#define NTSC_LIGHT_ORANGE \
357		rgb_t(0x21,0x02,0x00), rgb_t(0x32,0x13,0x00), rgb_t(0x43,0x24,0x00), rgb_t(0x54,0x35,0x00), \
358		rgb_t(0x65,0x46,0x00), rgb_t(0x76,0x57,0x00), rgb_t(0x87,0x68,0x00), rgb_t(0x98,0x79,0x0C), \
359		rgb_t(0xA9,0x8A,0x1D), rgb_t(0xBA,0x9B,0x2E), rgb_t(0xCB,0xAC,0x3F), rgb_t(0xDC,0xBD,0x50), \
360		rgb_t(0xED,0xCE,0x61), rgb_t(0xFE,0xDF,0x72), rgb_t(0xFF,0xF0,0x87), rgb_t(0xFF,0xFF,0x9D )
	358	rgb_t(0x19,0x07,0x00), rgb_t(0x2A,0x18,0x00), rgb_t(0x3B,0x29,0x00), rgb_t(0x4C,0x3A,0x00), \
	359	rgb_t(0x5D,0x4B,0x00), rgb_t(0x6E,0x5C,0x00), rgb_t(0x7F,0x6D,0x00), rgb_t(0x90,0x7E,0x09), \
	360	rgb_t(0xA1,0x8F,0x1A), rgb_t(0xB2,0xA0,0x2B), rgb_t(0xC3,0xB1,0x3C), rgb_t(0xD4,0xC2,0x4D), \
	361	rgb_t(0xE5,0xD3,0x5E), rgb_t(0xF6,0xE4,0x6F), rgb_t(0xFF,0xF5,0x82), rgb_t(0xFF,0xFF,0x96 )
361	362
362	363	static const rgb_t a7800_palette[256*3] =
363	364	{
r29424	r29425
400	401	};
401	402
402	403	/***************************************************************************
403		PALETTE - PHASE ~~24.7~~ SHIFT
	404	PALETTE - 24.7 PHASE SHIFT
404	405
405	406
406	407	define NTSC_GREY
r29424	r29425
500	501	rgb_t(0xD6,0xDD,0x5E), rgb_t(0xE7,0xEE,0x6F), rgb_t(0xF8,0xFF,0x80), rgb_t(0xFF,0xFF,0x8F )
501	502	***************************************************************************/
502	503
	504
503	505	/***************************************************************************
504		PALETTE - PHASE ~~25.2~~ SHIFT
	506	PALETTE - 25.2 PHASE SHIFT
505	507
506	508
507	509	define NTSC_GREY
r29424	r29425
601	603	rgb_t(0xDE,0xD8,0x5D), rgb_t(0xEF,0xE9,0x6E), rgb_t(0xFF,0xFA,0x80), rgb_t(0xFF,0xFF,0x92 )
602	604	***************************************************************************/
603	605
	606
604	607	/***************************************************************************
605		PALETTE - PHASE ~~25.7~~ SHIFT
	608	PALETTE - 25.7 PHASE SHIFT
606	609
607	610
608	611	define NTSC_GREY
r29424	r29425
702	705	rgb_t(0xE5,0xD3,0x5E), rgb_t(0xF6,0xE4,0x6F), rgb_t(0xFF,0xF5,0x82), rgb_t(0xFF,0xFF,0x96 )
703	706	***************************************************************************/
704	707
	708
705	709	/***************************************************************************
706		PALETTE - PHASE ~~26.7~~ SHIFT
	710	PALETTE - 26.2 PHASE SHIFT
707	711
708	712
	713	#define NTSC_GREY \
	714	rgb_t(0x00,0x00,0x00), rgb_t(0x11,0x11,0x11), rgb_t(0x22,0x22,0x22), rgb_t(0x33,0x33,0x33), \
	715	rgb_t(0x44,0x44,0x44), rgb_t(0x55,0x55,0x55), rgb_t(0x66,0x66,0x66), rgb_t(0x77,0x77,0x77), \
	716	rgb_t(0x88,0x88,0x88), rgb_t(0x99,0x99,0x99), rgb_t(0xAA,0xAA,0xAA), rgb_t(0xBB,0xBB,0xBB), \
	717	rgb_t(0xCC,0xCC,0xCC), rgb_t(0xDD,0xDD,0xDD), rgb_t(0xEE,0xEE,0xEE), rgb_t(0xFF,0xFF,0xFF )
	718
	719	#define NTSC_GOLD \
	720	rgb_t(0x1A,0x07,0x00), rgb_t(0x2B,0x18,0x00), rgb_t(0x3C,0x29,0x00), rgb_t(0x4D,0x3A,0x00), \
	721	rgb_t(0x5E,0x4B,0x00), rgb_t(0x6F,0x5C,0x00), rgb_t(0x80,0x6D,0x00), rgb_t(0x91,0x7E,0x09), \
	722	rgb_t(0xA2,0x8F,0x1A), rgb_t(0xB3,0xA0,0x2B), rgb_t(0xC4,0xB1,0x3C), rgb_t(0xD5,0xC2,0x4D), \
	723	rgb_t(0xE6,0xD3,0x5E), rgb_t(0xF7,0xE4,0x6F), rgb_t(0xFF,0xF5,0x83), rgb_t(0xFF,0xF7,0x97 )
	724
	725	#define NTSC_ORANGE \
	726	rgb_t(0x31,0x00,0x00), rgb_t(0x42,0x06,0x00), rgb_t(0x53,0x17,0x00), rgb_t(0x64,0x28,0x00), \
	727	rgb_t(0x75,0x39,0x00), rgb_t(0x86,0X4A,0x00), rgb_t(0x97,0x5B,0x0B), rgb_t(0xA8,0x6C,0x1C), \
	728	rgb_t(0xB9,0x7D,0x2D), rgb_t(0xCA,0x8E,0x3E), rgb_t(0xDB,0x9F,0x4F), rgb_t(0xEC,0xB0,0x60), \
	729	rgb_t(0xFD,0xC1,0x71), rgb_t(0xFF,0xD2,0x86), rgb_t(0xFF,0xE3,0x9D), rgb_t(0xFF,0xF4,0xB3 )
	730
	731	#define NTSC_RED_ORANGE \
	732	rgb_t(0x3E,0x00,0x00), rgb_t(0x4F,0x00,0x00), rgb_t(0x60,0x08,0x00), rgb_t(0x71,0x19,0x00), \
	733	rgb_t(0x82,0x2A,0x0F), rgb_t(0x93,0x3B,0x20), rgb_t(0xA4,0x4C,0x31), rgb_t(0xB5,0x5D,0x42), \
	734	rgb_t(0xC6,0x6E,0x53), rgb_t(0xD7,0x7F,0x64), rgb_t(0xE8,0x90,0x75), rgb_t(0xF9,0xA1,0x86), \
	735	rgb_t(0xFF,0xB2,0x9A), rgb_t(0xFF,0xC3,0xB0), rgb_t(0xFF,0xD4,0xC6), rgb_t(0xFF,0xE5,0xDC )
	736
	737	#define NTSC_PINK \
	738	rgb_t(0x3E,0x00,0x06), rgb_t(0x4F,0x00,0x12), rgb_t(0x60,0x00,0x1E), rgb_t(0x71,0x0E,0x2E), \
	739	rgb_t(0x82,0x1F,0x3F), rgb_t(0x93,0x30,0x50), rgb_t(0xA4,0x41,0x61), rgb_t(0xB5,0x52,0x72), \
	740	rgb_t(0xC6,0x63,0x83), rgb_t(0xD7,0x74,0x94), rgb_t(0xE8,0x85,0xA5), rgb_t(0xF9,0x96,0xB6), \
	741	rgb_t(0xFF,0xA7,0xCB), rgb_t(0xFF,0xB8,0xE1), rgb_t(0xFF,0xC9,0xEF), rgb_t(0xFF,0xDA,0xF4 )
	742
	743	#define NTSC_PURPLE \
	744	rgb_t(0x32,0x00,0x38), rgb_t(0x43,0x00,0x44), rgb_t(0x54,0x00,0x50), rgb_t(0x65,0x0C,0x5F), \
	745	rgb_t(0x76,0x1D,0x70), rgb_t(0x87,0x2E,0x81), rgb_t(0x98,0x3F,0x92), rgb_t(0xA9,0x50,0xA3), \
	746	rgb_t(0xBA,0x61,0xB4), rgb_t(0xCB,0x72,0xC5), rgb_t(0xDC,0x83,0xD6), rgb_t(0xED,0x94,0xE4), \
	747	rgb_t(0xFE,0xA5,0xE4), rgb_t(0xFF,0xB6,0xE9), rgb_t(0xFF,0xC7,0xEE), rgb_t(0xFF,0xD8,0xF3 )
	748
	749	#define NTSC_PURPLE_BLUE \
	750	rgb_t(0x1B,0x00,0x5F), rgb_t(0x2C,0x00,0x6B), rgb_t(0x3D,0x00,0x77), rgb_t(0x4E,0x11,0x88), \
	751	rgb_t(0x5F,0x22,0x99), rgb_t(0x70,0x33,0xAA), rgb_t(0x81,0x44,0xBB), rgb_t(0x92,0x55,0xCC), \
	752	rgb_t(0xA3,0x66,0xDD), rgb_t(0xB4,0x77,0xED), rgb_t(0xC5,0x88,0xED), rgb_t(0xD6,0x99,0xED), \
	753	rgb_t(0xE7,0xAA,0xED), rgb_t(0xF8,0xBB,0xED), rgb_t(0xFF,0xCC,0xF0), rgb_t(0xFF,0xDD,0xF5 )
	754
	755	#define NTSC_BLUE1 \
	756	rgb_t(0x00,0x00,0x72), rgb_t(0x10,0x00,0x7E), rgb_t(0x21,0x0D,0x8E), rgb_t(0x32,0x1E,0x9F), \
	757	rgb_t(0x43,0x2F,0xB0), rgb_t(0x54,0x40,0xC1), rgb_t(0x65,0x51,0xD2), rgb_t(0x76,0x62,0xE3), \
	758	rgb_t(0x87,0x73,0xF4), rgb_t(0x98,0x84,0xF9), rgb_t(0xA9,0x95,0xF9), rgb_t(0xBA,0xA6,0xF9), \
	759	rgb_t(0xCB,0xB7,0xF9), rgb_t(0xDC,0xC8,0xF9), rgb_t(0xED,0xD9,0xF9), rgb_t(0xFE,0xEA,0xF9 )
	760
	761	#define NTSC_BLUE2 \
	762	rgb_t(0x00,0x00,0x65), rgb_t(0x00,0x0C,0x7A), rgb_t(0x05,0x1D,0x8E), rgb_t(0x16,0x2E,0x9F), \
	763	rgb_t(0x27,0x3F,0xB0), rgb_t(0x38,0x50,0xC1), rgb_t(0x49,0x61,0xD2), rgb_t(0x5A,0x72,0xE3), \
	764	rgb_t(0x6B,0x83,0xF4), rgb_t(0x7C,0x94,0xFF), rgb_t(0x8D,0xA5,0xFF), rgb_t(0x9E,0xB6,0xFF), \
	765	rgb_t(0xAF,0xC7,0xFF), rgb_t(0xC0,0xD8,0xFF), rgb_t(0xD1,0xE9,0xFF), rgb_t(0xE2,0xFA,0xFF )
	766
	767	#define NTSC_LIGHT_BLUE \
	768	rgb_t(0x00,0x0D,0x48), rgb_t(0x00,0x1E,0x5E), rgb_t(0x00,0x2F,0x74), rgb_t(0x00,0x40,0x8A), \
	769	rgb_t(0x11,0x51,0x9B), rgb_t(0x22,0x62,0xAC), rgb_t(0x33,0x73,0xBD), rgb_t(0x44,0x84,0xCE), \
	770	rgb_t(0x55,0x95,0xDF), rgb_t(0x66,0xA6,0xF0), rgb_t(0x77,0xB7,0xFF), rgb_t(0x88,0xC8,0xFF), \
	771	rgb_t(0x99,0xD9,0xFF), rgb_t(0xAA,0xEA,0xFF), rgb_t(0xBB,0xFB,0xFF), rgb_t(0xCC,0xFF,0xFF )
	772
	773	#define NTSC_TURQUOISE \
	774	rgb_t(0x00,0x1C,0x1C), rgb_t(0x00,0x2D,0x32), rgb_t(0x00,0x3E,0x49), rgb_t(0x00,0x4F,0x5F), \
	775	rgb_t(0x05,0x60,0x73), rgb_t(0x16,0x71,0x84), rgb_t(0x27,0x82,0x95), rgb_t(0x38,0x93,0xA6), \
	776	rgb_t(0x49,0xA4,0xB7), rgb_t(0x5A,0xB5,0xC8), rgb_t(0x6B,0xC6,0xD9), rgb_t(0x7C,0xD7,0xEA), \
	777	rgb_t(0x8D,0xE8,0xFB), rgb_t(0x9E,0xF9,0xFF), rgb_t(0xAF,0xFF,0xFF), rgb_t(0xC0,0xFF,0xFF )
	778
	779	#define NTSC_GREEN_BLUE \
	780	rgb_t(0x00,0x25,0x0B), rgb_t(0x00,0x36,0x10), rgb_t(0x00,0x47,0x18), rgb_t(0x00,0x58,0x2E), \
	781	rgb_t(0x07,0x69,0x42), rgb_t(0x18,0x7A,0x53), rgb_t(0x29,0x8B,0x64), rgb_t(0x3A,0x9C,0x75), \
	782	rgb_t(0x4B,0xAD,0x86), rgb_t(0x5C,0xBE,0x97), rgb_t(0x6D,0xCF,0xA8), rgb_t(0x7E,0xE0,0xB9), \
	783	rgb_t(0x8F,0xF1,0xCA), rgb_t(0xA0,0xFF,0xDA), rgb_t(0xB1,0xFF,0xE6), rgb_t(0xC2,0xFF,0xF2 )
	784
	785	#define NTSC_GREEN \
	786	rgb_t(0x00,0x27,0x0C), rgb_t(0x00,0x38,0x11), rgb_t(0x00,0x49,0x16), rgb_t(0x04,0x5A,0x1A), \
	787	rgb_t(0x15,0x6B,0x1A), rgb_t(0x26,0x7C,0x22), rgb_t(0x37,0x8D,0x33), rgb_t(0x48,0x9E,0x44), \
	788	rgb_t(0x59,0xAF,0x55), rgb_t(0x6A,0xC0,0x66), rgb_t(0x7B,0xD1,0x77), rgb_t(0x8C,0xE2,0x88), \
	789	rgb_t(0x9D,0xF3,0x99), rgb_t(0xAE,0xFF,0xA8), rgb_t(0xBF,0xFF,0xB4), rgb_t(0xD0,0xFF,0xC0 )
	790
	791	#define NTSC_YELLOW_GREEN \
	792	rgb_t(0x00,0x21,0x0A), rgb_t(0x00,0x32,0x0F), rgb_t(0x0A,0x43,0x11), rgb_t(0x1B,0x54,0x11), \
	793	rgb_t(0x2C,0x65,0x11), rgb_t(0x3D,0x76,0x11), rgb_t(0x4E,0x87,0x11), rgb_t(0x5F,0x98,0x1E), \
	794	rgb_t(0x70,0xA9,0x2F), rgb_t(0x81,0xBA,0x40), rgb_t(0x92,0xCB,0x51), rgb_t(0xA3,0xDC,0x62), \
	795	rgb_t(0xB4,0xED,0x73), rgb_t(0xC5,0xFE,0x84), rgb_t(0xD6,0xFF,0x90), rgb_t(0xE7,0xFF,0x9C )
	796
	797	#define NTSC_ORANGE_GREEN \
	798	rgb_t(0x05,0x13,0x04), rgb_t(0x16,0x24,0x04), rgb_t(0x27,0x35,0x04), rgb_t(0x38,0x46,0x04), \
	799	rgb_t(0x49,0x57,0x04), rgb_t(0x5A,0x68,0x04), rgb_t(0x6B,0x79,0x04), rgb_t(0x7C,0x8A,0x09), \
	800	rgb_t(0x8D,0x9B,0x1A), rgb_t(0x9E,0xAC,0x2B), rgb_t(0xAF,0xBD,0x3C), rgb_t(0xC0,0xCE,0x4D), \
	801	rgb_t(0xD1,0xDF,0x5E), rgb_t(0xE2,0xF0,0x6F), rgb_t(0xF3,0xFF,0x80), rgb_t(0xFF,0xFF,0x8D )
	802
	803	#define NTSC_LIGHT_ORANGE \
	804	rgb_t(0x21,0x02,0x00), rgb_t(0x32,0x13,0x00), rgb_t(0x43,0x24,0x00), rgb_t(0x54,0x35,0x00), \
	805	rgb_t(0x65,0x46,0x00), rgb_t(0x76,0x57,0x00), rgb_t(0x87,0x68,0x00), rgb_t(0x98,0x79,0x0C), \
	806	rgb_t(0xA9,0x8A,0x1D), rgb_t(0xBA,0x9B,0x2E), rgb_t(0xCB,0xAC,0x3F), rgb_t(0xDC,0xBD,0x50), \
	807	rgb_t(0xED,0xCE,0x61), rgb_t(0xFE,0xDF,0x72), rgb_t(0xFF,0xF0,0x87), rgb_t(0xFF,0xFF,0x9D )
	808	***************************************************************************/
	809
	810
	811	/***************************************************************************
	812	PALETTE - 26.7 PHASE SHIFT
	813
	814
709	815	define NTSC_GREY
710	816	rgb_t(0x00,0x00,0x00), rgb_t(0x11,0x11,0x11), rgb_t(0x22,0x22,0x22), rgb_t(0x33,0x33,0x33), \
711	817	rgb_t(0x44,0x44,0x44), rgb_t(0x55,0x55,0x55), rgb_t(0x66,0x66,0x66), rgb_t(0x77,0x77,0x77), \
r29424	r29425
805	911
806	912
807	913	/***************************************************************************
808		PALETTE - PHASE ~~27.2~~ SHIFT
	914	PALETTE - 27.2 PHASE SHIFT
809	915
810	916
811	917	define NTSC_GREY
r29424	r29425
1033	1139
1034	1140	/* video hardware */
1035	1141	MCFG_SCREEN_ADD("screen", RASTER)
1036		MCFG_SCREEN_RAW_PARAMS( 7159090, 456, 0, 320, 263, 26, 26 + 192 + 30 )
	1142	MCFG_SCREEN_RAW_PARAMS( 7159090, 456, 0, 320, 263, 27, 27 + 192 + 32 )
1037	1143	MCFG_SCREEN_UPDATE_DRIVER(a7800_state, screen_update_a7800)
1038	1144	MCFG_SCREEN_PALETTE("palette")
1039	1145
r29424	r29425
1072	1178	// MCFG_TIMER_ADD_SCANLINE("scantimer", a7800_interrupt, "screen", 0, 1)
1073	1179
1074	1180	MCFG_SCREEN_MODIFY( "screen" )
1075		MCFG_SCREEN_RAW_PARAMS( 7093788, 456, 0, 320, 313, 34, 34 + 228 + 30 )
	1181	MCFG_SCREEN_RAW_PARAMS( 7093788, 456, 0, 320, 313, 35, 35 + 228 + 32 )
1076	1182
1077	1183	MCFG_PALETTE_MODIFY("palette")
1078	1184	MCFG_PALETTE_INIT_OWNER(a7800_state, a7800p )
r29424	r29425
1084	1190
1085	1191	/* devices */
1086	1192	MCFG_DEVICE_REMOVE("riot")
1087		MCFG_RIOT6532_ADD("riot", ~~3546894/3~~, a7800_r6532_interface)
	1193	MCFG_RIOT6532_ADD("riot", CLK_PAL, a7800_r6532_interface)
1088	1194
1089	1195	/* software lists */
1090	1196	MCFG_DEVICE_REMOVE("cart_list")

branches/new_menus/src/mess/drivers/x68k.c
r29424	r29425
1042	1042
1043	1043	TIMER_CALLBACK_MEMBER(x68k_state::x68k_bus_error)
1044	1044	{
1045		int val = param;
1046		int v;
1047		UINT8 *ram = m_ram->pointer();
	1045	m_bus_error = false;
	1046	}
1048	1047
1049		if(strcmp(machine().system().name,"x68030") == 0)
1050		v = 0x0b;
1051		else
1052		v = 0x09;
1053		if(ram[v] != 0x02) // normal vector for bus errors points to 02FF0540
1054		{
1055		m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
1056		m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
1057		popmessage("Bus error: Unused RAM access [%08x]", val);
1058		}
	1048	void x68k_state::set_bus_error(UINT32 address, bool write, UINT16 mem_mask)
	1049	{
	1050	if(m_bus_error)
	1051	return;
	1052	if(!ACCESSING_BITS_8_15)
	1053	address++;
	1054	m_bus_error = true;
	1055	m68k_set_buserror_details(m_maincpu, address, write, m68k_get_fc(m_maincpu));
	1056	m_maincpu->mmu_tmp_buserror_address = address; // Hack for x68030
	1057	m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
	1058	m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
	1059	timer_set(m_maincpu->cycles_to_attotime(16), TIMER_X68K_BUS_ERROR); // let rmw cycles complete
	1060	logerror("%s: Bus error: Unused RAM access [%08x]\n", machine().describe_context(), address);
1059	1061	}
1060	1062
1061	1063	READ16_MEMBER(x68k_state::x68k_rom0_r)
r29424	r29425
1064	1066	then access causes a bus error */
1065	1067	m_current_vector[2] = 0x02; // bus error
1066	1068	m_current_irq_line = 2;
1067		// m_maincpu->set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
1068		if(ioport("options")->read() & 0x02)
1069		{
1070		offset *= 2;
1071		if(ACCESSING_BITS_0_7)
1072		offset++;
1073		timer_set(m_maincpu->cycles_to_attotime(4), TIMER_X68K_BUS_ERROR, 0xbffffc+offset);
1074		}
	1069	if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1070	set_bus_error((offset << 1) + 0xbffffc, 0, mem_mask);
1075	1071	return 0xff;
1076	1072	}
1077	1073
r29424	r29425
1081	1077	then access causes a bus error */
1082	1078	m_current_vector[2] = 0x02; // bus error
1083	1079	m_current_irq_line = 2;
1084		// m_maincpu->set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
1085		if(ioport("options")->read() & 0x02)
1086		{
1087		offset *= 2;
1088		if(ACCESSING_BITS_0_7)
1089		offset++;
1090		timer_set(m_maincpu->cycles_to_attotime(4), TIMER_X68K_BUS_ERROR, 0xbffffc+offset);
1091		}
	1080	if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1081	set_bus_error((offset << 1) + 0xbffffc, 1, mem_mask);
1092	1082	}
1093	1083
1094	1084	READ16_MEMBER(x68k_state::x68k_emptyram_r)
r29424	r29425
1097	1087	Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
1098	1088	m_current_vector[2] = 0x02; // bus error
1099	1089	m_current_irq_line = 2;
1100		// m_maincpu->set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
1101		if(ioport("options")->read() & 0x02)
1102		{
1103		offset *= 2;
1104		if(ACCESSING_BITS_0_7)
1105		offset++;
1106		timer_set(m_maincpu->cycles_to_attotime(4), TIMER_X68K_BUS_ERROR, offset);
1107		}
	1090	if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1091	set_bus_error((offset << 1), 0, mem_mask);
1108	1092	return 0xff;
1109	1093	}
1110	1094
r29424	r29425
1114	1098	Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
1115	1099	m_current_vector[2] = 0x02; // bus error
1116	1100	m_current_irq_line = 2;
1117		// m_maincpu->set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
1118		if(ioport("options")->read() & 0x02)
1119		{
1120		offset *= 2;
1121		if(ACCESSING_BITS_0_7)
1122		offset++;
1123		timer_set(m_maincpu->cycles_to_attotime(4), TIMER_X68K_BUS_ERROR, offset);
1124		}
	1101	if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1102	set_bus_error((offset << 1), 1, mem_mask);
1125	1103	}
1126	1104
1127	1105	READ16_MEMBER(x68k_state::x68k_exp_r)
1128	1106	{
1129	1107	/* These are expansion devices, if not present, they cause a bus error */
1130		if(ioport("options")->read() & 0x02)
1131		{
1132		m_current_vector[2] = 0x02; // bus error
1133		m_current_irq_line = 2;
1134		offset *= 2;
1135		if(ACCESSING_BITS_0_7)
1136		offset++;
1137		timer_set(m_maincpu->cycles_to_attotime(16), TIMER_X68K_BUS_ERROR, 0xeafa00+offset);
1138		// m_maincpu->set_input_line_and_vector(2,ASSERT_LINE,state->m_current_vector[2]);
1139		}
1140		return 0xffff;
	1108	m_current_vector[2] = 0x02; // bus error
	1109	m_current_irq_line = 2;
	1110	if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1111	set_bus_error((offset << 1) + 0xeafa00, 0, mem_mask);
	1112	return 0xff;
1141	1113	}
1142	1114
1143	1115	WRITE16_MEMBER(x68k_state::x68k_exp_w)
1144	1116	{
1145	1117	/* These are expansion devices, if not present, they cause a bus error */
1146		if(ioport("options")->read() & 0x02)
1147		{
1148		m_current_vector[2] = 0x02; // bus error
1149		m_current_irq_line = 2;
1150		offset *= 2;
1151		if(ACCESSING_BITS_0_7)
1152		offset++;
1153		timer_set(m_maincpu->cycles_to_attotime(16), TIMER_X68K_BUS_ERROR, 0xeafa00+offset);
1154		// m_maincpu->set_input_line_and_vector(2,ASSERT_LINE,state->m_current_vector[2]);
1155		}
	1118	m_current_vector[2] = 0x02; // bus error
	1119	m_current_irq_line = 2;
	1120	if((ioport("options")->read() & 0x02) && !space.debugger_access())
	1121	set_bus_error((offset << 1) + 0xeafa00, 1, mem_mask);
1156	1122	}
1157	1123
1158	1124	void x68k_state::dma_irq(int channel)
r29424	r29425
1766	1732	address_space &space = m_maincpu->space(AS_PROGRAM);
1767	1733	/* Install RAM handlers */
1768	1734	m_spriteram = (UINT16)(memregion("user1"));
1769		space.install_read_handler(0x000000,0xbffffb,0xffffffff,0,read16_delegate(FUNC(x68k_state::x68k_rom0_r),this),0xffffffff);
1770		space.install_write_handler(0x000000,0xbffffb,0xffffffff,0,write16_delegate(FUNC(x68k_state::x68k_rom0_w),this),0xffffffff);
	1735	space.install_read_handler(0x000000,0xbffffb,0xffffffff,0,read16_delegate(FUNC(x68k_state::x68k_emptyram_r),this),0xffffffff);
	1736	space.install_write_handler(0x000000,0xbffffb,0xffffffff,0,write16_delegate(FUNC(x68k_state::x68k_emptyram_w),this),0xffffffff);
1771	1737	space.install_readwrite_bank(0x000000,m_ram->size()-1,0xffffffff,0,"bank1");
1772	1738	membank("bank1")->set_base(m_ram->pointer());
1773	1739	space.install_read_handler(0xc00000,0xdfffff,0xffffffff,0,read32_delegate(FUNC(x68k_state::x68k_gvram32_r),this));

branches/new_menus/src/mess/machine/a7800.c
r29424	r29425
18	18	added F18 Hornet bank select type
19	19	added Activision bank select type
20	20	19-Feb-2010 DanB Added return values for TIA collision registers
	21
	22	04-Apr-2014 Mike Saarna Fix to controller button RIOT behavior and
	23	expanded cart handling (bit 05).
21	24	***************************************************************************/
22	25
23	26	#include "emu.h"
r29424	r29425
46	49
47	50	WRITE8_MEMBER(a7800_state::riot_button_pullup_w)
48	51	{
49		m_p1_one_button = data & 0x04; // pin 6 of the controller port is held high by the riot chip when reading two-button controllers (from schematic)
50		m_p2_one_button = data & 0x10;
	52	if(m_maincpu->space(AS_PROGRAM).read_byte(0x283) & 0x04)
	53	m_p1_one_button = data & 0x04; // pin 6 of the controller port is held high by the riot chip when reading two-button controllers (from schematic)
	54	if(m_maincpu->space(AS_PROGRAM).read_byte(0x283) & 0x10)
	55	m_p2_one_button = data & 0x10;
51	56	}
52	57
53	58	const riot6532_interface a7800_r6532_interface =

branches/new_menus/src/mess/machine/megacd.c
r29424	r29425
312	312	MCFG_TIMER_DRIVER_ADD("stamp_timer", sega_segacd_device, segacd_gfx_conversion_timer_callback)
313	313	MCFG_TIMER_DRIVER_ADD("scd_dma_timer", sega_segacd_device, scd_dma_timer_callback)
314	314
315		MCFG_GFXDECODE_ADD("gfxdecode", ":gen_vdp:palette", segacd) // FIXME
	315	MCFG_GFXDECODE_ADD("gfxdecode", "^gen_vdp:palette", segacd) // FIXME
316	316
317	317	MCFG_DEFAULT_LAYOUT( layout_megacd )
318	318

branches/new_menus/src/mame/drivers/halleys.c
r29424	r29425
253	253	DECLARE_READ8_MEMBER(blitter_r);
254	254	DECLARE_WRITE8_MEMBER(blitter_w);
255	255	DECLARE_READ8_MEMBER(collision_id_r);
256		DECLARE_WRITE8_MEMBER(halleys_paletteram_IIRRGGBB_w);
	256	DECLARE_READ8_MEMBER(paletteram_r);
	257	DECLARE_WRITE8_MEMBER(paletteram_w);
257	258	DECLARE_READ8_MEMBER(zero_r);
258	259	DECLARE_READ8_MEMBER(debug_r);
259	260	DECLARE_READ8_MEMBER(vector_r);
r29424	r29425
1221	1222	*b = prom_6330[0x40 + (bit0\|bit1\|bit2\|bit3\|bit4)];
1222	1223	}
1223	1224
1224		WRITE8_MEMBER(halleys_state::~~halleys_~~paletteram_~~IIRRGGBB_w~~)
	1225	READ8_MEMBER(halleys_state::paletteram_r)
1225	1226	{
	1227	return m_paletteram[offset];
	1228	}
	1229
	1230	WRITE8_MEMBER(halleys_state::paletteram_w)
	1231	{
1226	1232	UINT32 d, r, g, b, i, j;
1227	1233	UINT32 *pal_ptr = m_internal_palette;
1228	1234
r29424	r29425
1691	1697	AM_RANGE(0xff9c, 0xff9c) AM_WRITE(firq_ack_w)
1692	1698	AM_RANGE(0xff00, 0xffbf) AM_RAM AM_SHARE("io_ram") // I/O write fall-through
1693	1699
1694		AM_RANGE(0xffc0, 0xffdf) AM_RAM_WRITE(halleys_paletteram~~_IIRRGGBB~~_w)
	1700	AM_RANGE(0xffc0, 0xffdf) AM_READWRITE(paletteram_r, paletteram_w)
1695	1701	AM_RANGE(0xffe0, 0xffff) AM_READ(vector_r)
1696	1702	ADDRESS_MAP_END
1697	1703

branches/new_menus/src/mame/drivers/tourvis.c
r29424	r29425
14	14
15	15	Known games:
16	16
17		Aero Blaster (label shows "Vol. 33")
	17	Aero Blaster (label shows "Vol. 33") [dumped]
18	18	After Burner
19	19	Bonk
20		Columns
	20	Columns [dumped]
21	21	Cyber Core
22	22	Dead Moon
23	23	Doraemon Meikyuu Daisakusen
24	24	Down Load
25		Dungeon Explorer
26		Final Lap
	25	Dungeon Explorer [dumped]
	26	Final Lap Twin [dumped]
27	27	Final Match Tennis
28		Formation Soccer
29		Legendary Axe
	28	Formation Soccer [dumped]
	29	Gomola Speed [dumped]
	30	Jackie Chan [dumped]
	31	Legendary Axe [dumped]
30	32	Mr. Heli
31	33	Out Run
32		Power Eleven
33		Power League IV
	34	PC Genjin 2 [dumped]
	35	Power Eleven [dumped]
	36	Power League IV [dumped]
34	37	Power Sports
35	38	Puzzle Boy
36		Rastan Saga II
	39	Rastan Saga II [dumped]
37	40	Saigo no Nindou
38	41	Son Son II
39		Special Criminal Investigation
40		Super Star Soldier (label shows "Vol. 30")
41		Super Volley ball
42		Thunder Blade
43		USA Pro Basketball
	42	Special Criminal Investigation [dumped]
	43	Super Star Soldier (label shows "Vol. 30") [dumped]
	44	Super Volley ball [dumped]
	45	Thunder Blade [dumped]
	46	USA Pro Basketball [dumped]
44	47	Vigilante
45		Volfied
	48	Volfied [dumped]
46	49
47	50	_______________________________________________________________________________________________________________________________________________
48	51	\| \|
r29424	r29425
536	539	TOURVISION_BIOS
537	540	ROM_END
538	541
	542
	543	ROM_START(tvablast)
	544	ROM_REGION( 0x100000, "maincpu", 0 )
	545	ROM_LOAD( "tourv_ablast.bin", 0x00000, 0x100000, CRC(9302f6d0) SHA1(76ef27a6d639514ed261b9d65f37217f2989d1c0) )
	546
	547	TOURVISION_BIOS
	548	ROM_END
	549
	550
	551	ROM_START(tvcolumn)
	552	ROM_REGION( 0x100000, "maincpu", 0 )
	553	ROM_LOAD( "tourv_column.bin", 0x00000, 0x100000, CRC(bb01dea8) SHA1(24e00aee5117e996becb56b59851e54e3f2fa11f) )
	554
	555	TOURVISION_BIOS
	556	ROM_END
	557
	558
	559	ROM_START(tvflaptw)
	560	ROM_REGION( 0x100000, "maincpu", 0 )
	561	ROM_LOAD( "tourv_flaptw.bin", 0x00000, 0x100000, CRC(3ca56272) SHA1(9b5417ae9a9400fead170e882d3dae19edfd7157) )
	562
	563	TOURVISION_BIOS
	564	ROM_END
	565
	566
	567	ROM_START(tvfsoc90)
	568	ROM_REGION( 0x100000, "maincpu", 0 )
	569	ROM_LOAD( "tourv_fsoc90.bin", 0x00000, 0x100000, CRC(428ffeb1) SHA1(5d12f3ed7f42b2b6da4d8eba95a16e2d34616846) )
	570
	571	TOURVISION_BIOS
	572	ROM_END
	573
	574
	575	ROM_START(tvgomola)
	576	ROM_REGION( 0x100000, "maincpu", 0 )
	577	ROM_LOAD( "tourv_gomola.bin", 0x00000, 0x100000, CRC(41e8e18f) SHA1(210e511b85056bf216fc0d2540ed379a9dc7c18f) )
	578
	579	TOURVISION_BIOS
	580	ROM_END
	581
	582
	583	ROM_START(tvjchan)
	584	ROM_REGION( 0x100000, "maincpu", 0 )
	585	ROM_LOAD( "tourv_jchan.bin", 0x00000, 0x100000, CRC(7fe2b77c) SHA1(f27251451301dfb800e454c09fbb82d43b518592) )
	586
	587	TOURVISION_BIOS
	588	ROM_END
	589
	590
	591	ROM_START(tvpcgen2)
	592	ROM_REGION( 0x100000, "maincpu", 0 )
	593	ROM_LOAD( "tourv_pckid2.bin", 0x00000, 0x100000, CRC(57fab9ee) SHA1(07c8b18905fceac73c3e18b747e8cf92d8a5f515) )
	594
	595	TOURVISION_BIOS
	596	ROM_END
	597
	598
	599	ROM_START(tvpow11)
	600	ROM_REGION( 0x100000, "maincpu", 0 )
	601	ROM_LOAD( "tourv_pow11.bin", 0x00000, 0x100000, CRC(375114a3) SHA1(845633345886b335e6c82b3f56ef012d9820e64d) )
	602
	603	TOURVISION_BIOS
	604	ROM_END
	605
	606
	607	ROM_START(tvsssold)
	608	ROM_REGION( 0x100000, "maincpu", 0 )
	609	ROM_LOAD( "tourv_sssold.bin", 0x00000, 0x100000, CRC(bb2a0b14) SHA1(5380d25b4d5bb3e0048ed857fd36a8206e81a234) )
	610
	611	TOURVISION_BIOS
	612	ROM_END
	613
	614
	615	ROM_START(tvvolfd)
	616	ROM_REGION( 0x100000, "maincpu", 0 )
	617	ROM_LOAD( "tourv_volfd.bin", 0x00000, 0x100000, BAD_DUMP CRC(c33efba5) SHA1(41ad4f85e551321487be61e2adbeae67e65c47de) )
	618
	619	TOURVISION_BIOS
	620	ROM_END
	621
	622
539	623	GAME( 19??, tourvis, 0, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision)", "Tourvision PCE bootleg", GAME_IS_BIOS_ROOT \| GAME_NOT_WORKING )
540	624	GAME( 1988, tvlegaxe, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Victor Musical Industries, Inc.", "Makyo Densetsu - The Legenary Axe (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	625	GAME( 1989, tvflaptw, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Namco", "Final Lap Twin (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
541	626	GAME( 1989, tvusapb, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Aicom", "USA Pro Basketball (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	627	GAME( 1989, tvvolfd, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Taito", "Volfied (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
542	628	GAME( 1989, tvdunexp, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Hudson / Atlus", "Dungeon Explorer (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	629	GAME( 1990, tvablast, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Hudson / Kaneko", "Aero Blasters (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	630	GAME( 1990, tvfsoc90, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Human", "Formation Soccer - Human Cup '90 (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	631	GAME( 1990, tvgomola, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Human", "Gomola Speed (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	632	GAME( 1990, tvsssold, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Hudson / Kaneko", "Super Star Soldier (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
543	633	GAME( 1990, tvthbld, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Sega / NEC Avenue", "Thunder Blade (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
544	634	GAME( 1990, tvrs2, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Taito", "Rastan Saga II (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
545	635	GAME( 1990, tvsvball, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Video System", "Super Volley ball (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	636	GAME( 1991, tvcolumn, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Telenet Japan", "Columns (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	637	GAME( 1991, tvjchan, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Hudson", "Jackie Chan (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	638	GAME( 1991, tvpcgen2, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Hudson", "PC Genjin 2 - Pithecanthropus Computerurus (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
	639	GAME( 1991, tvpow11, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Hudson", "Power Eleven (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
546	640	GAME( 1991, tvpwlg4, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Hudson", "Power League IV (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )
547	641	GAME( 1991, tvsci, tourvis, tourvision, tourvision, pce_common_state, pce_common, ROT0, "bootleg (Tourvision) / Taito", "Special Criminal Investigation (Tourvision PCE bootleg)", GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING )

branches/new_menus/src/mame/drivers/pong.c
r29424	r29425
58	58
59	59	#define HRES_MULT (1)
60	60
61		fixedfreq_interface fixedfreq_mode_pong = {
	61	fixedfreq_interface fixedfreq_mode_pongd = {
62	62	MASTER_CLOCK,
63		H_TOTAL-67,H_TOTAL-40,H_TOTAL-8,H_TOTAL,
	63	H_TOTAL-67,H_TOTAL-52,H_TOTAL-8,H_TOTAL,
64	64	V_TOTAL-22,V_TOTAL-19,V_TOTAL-12,V_TOTAL,
65	65	1, /* non-interlaced */
66	66	0.31
67	67	};
68	68
	69	fixedfreq_interface fixedfreq_mode_pong = {
	70	MASTER_CLOCK,
	71	H_TOTAL-67,H_TOTAL-40,H_TOTAL-8,H_TOTAL,
	72	V_TOTAL-22,V_TOTAL-19,V_TOTAL-12,V_TOTAL,
	73	1, /* non-interlaced */
	74	0.31
	75	};
	76
69	77	fixedfreq_interface fixedfreq_mode_pongX2 = {
70	78	MASTER_CLOCK * 2,
71	79	(H_TOTAL-67) * 2, (H_TOTAL-40) * 2, (H_TOTAL-8) * 2, (H_TOTAL) * 2,
r29424	r29425
105	113	#if 1
106	114	#if 0
107	115	/* this is the clock circuit in schematics. */
108		MAINCLOCK(xclk)
109		//CLOCK(clk)
110		PARAM(xclk.FREQ, 7159000.0*2)
	116	MAINCLOCK(xclk, 7159000.0*2)
111	117	TTL_74107(ic_f6a, xclk, high, high, high)
112	118	ALIAS(clk, ic_f6a.Q)
113	119	#else
114		/* abstracting this, performance increases by 40%
	120	/* abstracting this, performance increases by 60%
115	121	* No surprise, the clock is extremely expensive */
116	122	MAINCLOCK(clk, 7159000.0)
117		//CLOCK(clk, 7159000.0)
118	123	#endif
119	124	#else
120	125	// benchmarking ...
r29424	r29425
728	733
729	734	static NETLIST_START(pongd)
730	735
731		~~NETLIST_~~INCLUDE(pongdoubles)
	736	INCLUDE(pongdoubles)
732	737
733	738	//NETDEV_ANALOG_CALLBACK(sound_cb, AUDIO, pong_state, sound_cb, "")
734	739	//NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
r29424	r29425
946	951
947	952	//MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_ntsc720)
948	953	//MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_pongX2)
949		MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_pong)
	954	MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_pongd)
950	955
951	956	/* sound hardware */
952	957	MCFG_SPEAKER_STANDARD_MONO("mono")

branches/new_menus/src/mame/drivers/metro.c
r29424	r29425
1699	1699	Puzzlet
1700	1700	***************************************************************************/
1701	1701
	1702	#define MCFG_PUZZLET_IO_ADD(_tag) \
	1703	MCFG_DEVICE_ADD(_tag, PUZZLET_IO, 0)
	1704
	1705	#define MCFG_PUZZLET_IO_DATA_CALLBACK(_devcb) \
	1706	devcb = &puzzlet_io_device::set_data_cb(*device, DEVCB2_##_devcb);
	1707
	1708	class puzzlet_io_device : public device_t {
	1709	public:
	1710	puzzlet_io_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	1711
	1712	DECLARE_WRITE_LINE_MEMBER( ce_w );
	1713	DECLARE_WRITE_LINE_MEMBER( clk_w );
	1714
	1715	template<class _Object> static devcb2_base &set_data_cb(device_t &device, _Object object) { return downcast<puzzlet_io_device &>(device).data_cb.set_callback(object); }
	1716
	1717	protected:
	1718	virtual void device_start();
	1719	virtual void device_reset();
	1720
	1721	private:
	1722	devcb2_write_line data_cb;
	1723	required_ioport port;
	1724	int ce, clk;
	1725	int cur_bit;
	1726	UINT8 value;
	1727	};
	1728
	1729	const device_type PUZZLET_IO = &device_creator<puzzlet_io_device>;
	1730
	1731
	1732	puzzlet_io_device::puzzlet_io_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	1733	: device_t(mconfig, PUZZLET_IO, "Puzzlet Coin/Start I/O", tag, owner, clock, "puzzlet_io", __FILE__),
	1734	data_cb(*this),
	1735	port(*this, ":IN0")
	1736	{
	1737	}
	1738
	1739	void puzzlet_io_device::device_start()
	1740	{
	1741	data_cb.resolve_safe();
	1742	save_item(NAME(ce));
	1743	save_item(NAME(clk));
	1744	save_item(NAME(cur_bit));
	1745	save_item(NAME(value));
	1746	ce = 1;
	1747	clk = 1;
	1748	}
	1749
	1750	void puzzlet_io_device::device_reset()
	1751	{
	1752	cur_bit = 0;
	1753	value = 0xff;
	1754	}
	1755
	1756	WRITE_LINE_MEMBER(puzzlet_io_device::ce_w)
	1757	{
	1758	if(ce && !state) {
	1759	value = port->read();
	1760	cur_bit = 0;
	1761	} else if(!ce && state)
	1762	data_cb(1);
	1763
	1764	ce = state;
	1765	}
	1766
	1767	WRITE_LINE_MEMBER(puzzlet_io_device::clk_w)
	1768	{
	1769	if(clk && !state) {
	1770	if(cur_bit == 8)
	1771	data_cb(1);
	1772	else {
	1773	data_cb((value >> cur_bit) & 1);
	1774	cur_bit++;
	1775	}
	1776	}
	1777	clk = state;
	1778	}
	1779
	1780
1702	1781	WRITE16_MEMBER(metro_state::puzzlet_irq_enable_w)
1703	1782	{
1704	1783	if (ACCESSING_BITS_0_7)
r29424	r29425
4530	4609	MCFG_MACHINE_START_OVERRIDE(metro_state,metro)
4531	4610	MCFG_MACHINE_RESET_OVERRIDE(metro_state,metro)
4532	4611
	4612	/* Coins/service */
	4613	MCFG_PUZZLET_IO_ADD("coins")
	4614	MCFG_PUZZLET_IO_DATA_CALLBACK(DEVWRITELINE("maincpu:sci1", h8_sci_device, rx_w))
	4615	MCFG_DEVICE_MODIFY("maincpu:sci1")
	4616	MCFG_H8_SCI_TX_CALLBACK(DEVWRITELINE(":coins", puzzlet_io_device, ce_w))
	4617	MCFG_H8_SCI_CLK_CALLBACK(DEVWRITELINE(":coins", puzzlet_io_device, clk_w))
	4618
4533	4619	/* video hardware */
4534	4620	MCFG_SCREEN_ADD("screen", RASTER)
4535	4621	MCFG_SCREEN_REFRESH_RATE(58)

branches/new_menus/src/mame/drivers/mystwarr.c
r29424	r29425
1069	1069	MCFG_TIMER_DRIVER_CALLBACK(mystwarr_state, metamrph_interrupt)
1070	1070
1071	1071	MCFG_DEVICE_MODIFY("k053252")
1072		MCFG_K053252_OFFSETS(24, 24)
	1072	MCFG_K053252_OFFSETS(24, 15)
1073	1073
1074	1074	MCFG_K053250_ADD("k053250_1", "palette", "screen", -7, 0)
1075	1075
r29424	r29425
1081	1081	MCFG_SCREEN_MODIFY("screen")
1082	1082	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(900))
1083	1083	MCFG_SCREEN_SIZE(648, 328)
1084		MCFG_SCREEN_VISIBLE_AREA(24, 24+288-1, 17, 17+224-1)
	1084	MCFG_SCREEN_VISIBLE_AREA(24, 24+288-1, 15, 15+224-1)
1085	1085	MACHINE_CONFIG_END
1086	1086
1087	1087	static MACHINE_CONFIG_DERIVED( dadandrn, mystwarr )

branches/new_menus/src/mame/drivers/4enlinea.c
r29424	r29425
137	137	8952 (PIN 04) --\|02 19\|-- GAL (PIN 17) 8952 (PIN 08) --\|02 19\|-- GAL (PIN 16)
138	138	MAIN Z80 (D7) --\|03 18\|-- MAIN Z80 (D0) MAIN Z80 (D7) --\|03 18\|-- MAIN Z80 (D0)
139	139	8952 (PIN 03) --\|04 17\|-- 8952 (PIN 40) 8952 (PIN 07) --\|04 17\|-- 8952 (PIN 36)
140		MAIN Z80 (D6) --\|05 16\|-- MAIN Z80 (D1) MAIN Z80 (D6) --\|05 16\|-- MAIN Z80 (D1)
	140	MAIN Z80 (D6) --\|05 16\|-- MAIN Z80 (D1) MAIN Z80 (D6) --\|05 16\|-- MAIN Z80 (D1)
141	141	8952 (PIN 02) --\|06 15\|-- 8952 (PIN 39) 8952 (PIN 06) --\|06 15\|-- 8952 (PIN 35)
142	142	MAIN Z80 (D5) --\|07 14\|-- MAIN Z80 (D2) MAIN Z80 (D5) --\|07 14\|-- MAIN Z80 (D2)
143	143	8952 (PIN 01) --\|08 13\|-- 8952 (PIN 38) 8952 (PIN 05) --\|08 13\|-- 8952 (PIN 34)
144		MAIN Z80 (D4) --\|09 12\|-- MAIN Z80 (D3) MAIN Z80 (D4) --\|09 12\|-- MAIN Z80 (D3)
	144	MAIN Z80 (D4) --\|09 12\|-- MAIN Z80 (D3) MAIN Z80 (D4) --\|09 12\|-- MAIN Z80 (D3)
145	145	GND --\|10 11\|-- 8952 (PIN 37) GND --\|10 11\|-- 8952 (PIN 33)
146	146	'-------' '-------'
147	147
r29424	r29425
198	198	#include "cpu/z80/z80.h"
199	199	#include "video/mc6845.h"
200	200	#include "sound/ay8910.h"
	201	#include "bus/isa/isa.h"
	202	#include "bus/isa/cga.h"
	203	#include "video/cgapal.h"
201	204
202	205	class _4enlinea_state : public driver_device
203	206	{
r29424	r29425
205	208	_4enlinea_state(const machine_config &mconfig, device_type type, const char *tag)
206	209	: driver_device(mconfig, type, tag),
207	210	m_ay(*this, "aysnd"),
208		m_videoram(*this, "videoram"),
209		m_videoram2(*this, "videoram2"),
210		m_maincpu(*this, "maincpu"),
211		m_gfxdecode(*this, "gfxdecode"),
212		m_screen(*this, "screen"),
213		m_palette(*this, "palette") { }
	211	m_maincpu(*this, "maincpu")
	212	{ }
214	213
215	214
216	215	required_device<ay8910_device> m_ay;
217		required_shared_ptr<UINT8> m_videoram;
218		required_shared_ptr<UINT8> m_videoram2;
219	216
220		DECLARE_WRITE8_MEMBER(crtc_config_w);
221		DECLARE_WRITE8_MEMBER(crtc_mode_ctrl_w);
222		DECLARE_WRITE8_MEMBER(crtc_colormode_w);
223		DECLARE_READ8_MEMBER(crtc_status_r);
224	217	DECLARE_READ8_MEMBER(unk_e000_r);
225	218	DECLARE_READ8_MEMBER(unk_e001_r);
	219	INTERRUPT_GEN_MEMBER(_4enlinea_irq);
	220	UINT8 m_irq_count;
226	221
227	222	virtual void machine_start();
228	223	virtual void machine_reset();
229		virtual void video_start();
230		DECLARE_PALETTE_INIT(_4enlinea);
231		UINT32 screen_update_4enlinea(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
232	224	required_device<cpu_device> m_maincpu;
233		required_device<gfxdecode_device> m_gfxdecode;
234		required_device<screen_device> m_screen;
235		required_device<palette_device> m_palette;
236
237		DECLARE_WRITE8_MEMBER(vram_w);
238		DECLARE_WRITE8_MEMBER(vram2_w);
239
240	225	};
241	226
242	227
r29424	r29425
244	229	* Video Hardware *
245	230	***********************************/
246	231
247		~~void~~ _4enlinea_~~stat~~e::video_sta~~rt()~~
	232	class isa8_cga_4enlinea_device : public isa8_cga_device
248	233	{
249		m_gfxdecode->gfx(0)->set_source(m_videoram);
250		}
	234	public:
	235	// construction/destruction
	236	isa8_cga_4enlinea_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
251	237
252		UINT32 _4enlinea_state::screen_update_4enlinea(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	238	virtual void device_start();
	239	virtual const rom_entry *device_rom_region() const;
	240	};
	241
	242	const rom_entry *isa8_cga_4enlinea_device::device_rom_region() const
253	243	{
254		/* note: chars are 1612 pixels /
	244	return NULL;
	245	}
255	246
256		int offset = 0;
257		int offset2 = 0;
	247	const device_type ISA8_CGA_4ENLINEA = &device_creator<isa8_cga_4enlinea_device>;
258	248
259		for (int y = 0; y < 200; y++)
260		{
261		UINT16* dstptr_bitmap = &bitmap.pix16(y);
	249	isa8_cga_4enlinea_device::isa8_cga_4enlinea_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	250	isa8_cga_device( mconfig, ISA8_CGA_4ENLINEA, "ISA8_CGA_4ENLINEA", tag, owner, clock, "4enlinea_cga", __FILE__)
	251	{
	252	}
262	253
263		for (int x = 0; x < 320; x += 4)
264		{
265		UINT8 pix;
266	254
267		if (y & 1) pix = m_videoram2[offset2++];
268		else pix = m_videoram[offset++];
269	255
270		dstptr_bitmap[x + 3] = (pix >> 0) & 0x3;
271		dstptr_bitmap[x + 2] = (pix >> 2) & 0x3;
272		dstptr_bitmap[x + 1] = (pix >> 4) & 0x3;
273		dstptr_bitmap[x + 0] = (pix >> 6) & 0x3;
274		}
275		}
	256	void isa8_cga_4enlinea_device::device_start()
	257	{
	258	if (m_palette != NULL && !m_palette->started())
	259	throw device_missing_dependencies();
276	260
277		return 0;
278		}
	261	set_isa_device();
	262	m_vram_size = 0x4000;
	263	m_vram.resize(m_vram_size);
279	264
	265	m_update_row = NULL;
	266	m_isa->install_device(0x3d0, 0x3df, 0, 0, read8_delegate( FUNC(isa8_cga_device::io_read), this ), write8_delegate( FUNC(isa8_cga_device::io_write), this ) );
	267	m_isa->install_bank(0x8000, 0xbfff, 0, 0, "bank1", m_vram);
280	268
281		WRITE8_MEMBER(_4enlinea_state::vram_w)
282		{
283		m_videoram[offset] = data;
284		// m_gfxdecode->gfx(0)->mark_dirty(offset/16);
285		}
	269	/* Initialise the cga palette */
	270	int i;
286	271
287		WRITE8_MEMBER(_4enlinea_state::vram2_w)
288		{
289		m_videoram2[offset] = data;
290		// m_gfxdecode->gfx(0)->mark_dirty(offset/16);
291		}
292
293		WRITE8_MEMBER(_4enlinea_state::crtc_config_w)
294		{
295		/* Bit 6 enables the CGA mode, otherwise is MGA */
296		if(data & 0x40)
	272	for ( i = 0; i < CGA_PALETTE_SETS * 16; i++ )
297	273	{
298		logerror(~~"CRTC~~ c~~onf~~ig ~~mod~~e ~~(3BFh): CGA\n"~~);
	274	m_palette->set_pen_color( i, cga_palette[i][0], cga_palette[i][1], cga_palette[i][2] );
299	275	}
300		else
	276
	277	i = 0x8000;
	278	for ( int r = 0; r < 32; r++ )
301	279	{
302		logerror("CRTC config mode (3BFh): MGA\n");
	280	for ( int g = 0; g < 32; g++ )
	281	{
	282	for ( int b = 0; b < 32; b++ )
	283	{
	284	m_palette->set_pen_color( i, r << 3, g << 3, b << 3 );
	285	i++;
	286	}
	287	}
303	288	}
304		}
305	289
306		WRITE8_MEMBER(_4enlinea_state::crtc_mode_ctrl_w)
307		{
308		/* Bit 3 enables/disables the video (see the notes above) */
309		logerror("CRTC mode control (3D8h): %02x\n", data);
	290	// astring tempstring;
	291	// m_chr_gen_base = memregion(subtag(tempstring, "gfx1"))->base();
	292	// m_chr_gen = m_chr_gen_base + m_chr_gen_offset[1];
310	293	}
311	294
312		WRITE8_MEMBER(_4enlinea_state::crtc_colormode_w)
313		{
314		logerror("CRTC color mode (3D9h): %02x\n", data);
315		}
316	295
317		READ8_MEMBER(_4enlinea_state::crtc_status_r)
318		{
319		/*----- bits -----
320		7 6 5 4 3 2 1 0 For CGA Mode.
321		x x x x - - - - (bits 4-5-6-7 are unused)
322		\| \| \| \|
323		\| \| \| '-- 0: Display active period.
324		\| \| \| 1: Non-display period.
325		\| \| \|
326		\| \| '---- 0: Light pen reset.
327		\| \| 1: Light pen set.
328		\| \|
329		\| '------ 0: Light pen switch off.
330		\| 1: Light pen switch on.
331		\|
332		'-------- 0: Non-vertical sync period.
333		1: Vertical sync period.
334
335		*/
336		return (m_screen->vpos() >= 200) ? 0x80 : 0x00; // bit 7 is suppossed to be unused in CGA mode
337		}
338
339	296	READ8_MEMBER(_4enlinea_state::unk_e000_r)
340	297	{
341	298	logerror("read e000\n");
r29424	r29425
350	307	// return (machine().rand() & 0x0f); // after 30 seconds, random gfx appear on the screen.
351	308	}
352	309
353
354	310	/***********************************
355	311	* Memory Map Information *
356	312	***********************************/
357	313
358	314	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, _4enlinea_state )
359	315	AM_RANGE(0x0000, 0x7fff) AM_ROM
360		AM_RANGE(0x8000, 0x9fff) AM_RAM_WRITE(vram_w) AM_SHARE("videoram") // even lines
361		AM_RANGE(0xa000, 0xbfff) AM_RAM_WRITE(vram2_w) AM_SHARE("videoram2") // odd lines
	316	// AM_RANGE(0x8000, 0xbfff) AM_RAM // CGA VRAM
362	317	AM_RANGE(0xc000, 0xdfff) AM_RAM
363	318
364	319	AM_RANGE(0xe000, 0xe000) AM_READ(unk_e000_r)
r29424	r29425
372	327	static ADDRESS_MAP_START( main_portmap, AS_IO, 8, _4enlinea_state )
373	328	ADDRESS_MAP_GLOBAL_MASK(0x3ff)
374	329
375		AM_RANGE(0x3d4, 0x3d4) AM_DEVWRITE("crtc", mc6845_device, address_w)
376		AM_RANGE(0x3d5, 0x3d5) AM_DEVWRITE("crtc", mc6845_device, register_w)
377		AM_RANGE(0x3d8, 0x3d8) AM_WRITE(crtc_mode_ctrl_w)
378		AM_RANGE(0x3d9, 0x3d9) AM_WRITE(crtc_colormode_w)
379		AM_RANGE(0x3da, 0x3da) AM_READ(crtc_status_r)
380		AM_RANGE(0x3bf, 0x3bf) AM_WRITE(crtc_config_w)
381
	330	// AM_RANGE(0x3d4, 0x3df) CGA regs
382	331	ADDRESS_MAP_END
383	332
384	333
r29424	r29425
423	372	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
424	373	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
425	374	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	375
	376
	377	PORT_START( "pcvideo_cga_config" )
	378	PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED )
426	379	INPUT_PORTS_END
427	380
428	381
r29424	r29425
430	383	* Graphics Layouts *
431	384	***********************************/
432	385
433		static const gfx_layout charlayout =
434		{
435		8,8,
436		0x4000/16,
437		2,
438		{ 0, 1 },
439		{ 0, 2, 4, 6, 8, 10, 12, 14 },
440		{ 016, 116, 216, 316, 416, 516, 616, 716 },
441		8*16
442		};
443	386
	387
444	388	/****************************************
445	389	* Graphics Decode Information *
446	390	****************************************/
447	391
448		static GFXDECODE_START( 4enlinea )
449		GFXDECODE_ENTRY( NULL, 0, charlayout, 0, 1 )
450		GFXDECODE_END
	392	//static GFXDECODE_START( 4enlinea )
	393	//GFXDECODE_END
451	394
452	395
453	396	/****************************************
r29424	r29425
469	412	* CRTC Interface *
470	413	**********************************/
471	414
472		static MC6845_ON_UPDATE_ADDR_CHANGED(crtc_addr)
473		{
474	415
475		}
476	416
477		static MC6845_INTERFACE( mc6845_intf )
478		{
479		false, /* show border area */
480		0,0,0,0, /* visarea adjustment */
481		8, /* number of pixels per video memory address */
482		NULL, /* before pixel update callback */
483		NULL, /* row update callback */
484		NULL, /* after pixel update callback */
485		DEVCB_NULL, /* callback for display state changes */
486		DEVCB_NULL, /* callback for cursor state changes */
487		DEVCB_NULL, /* HSYNC callback */
488		DEVCB_NULL, /* VSYNC callback */
489		crtc_addr /* update address callback */
490		};
491
492
493	417	/***********************************
494	418	* Sound Interface *
495	419	***********************************/
r29424	r29425
509	433	* Machine Drivers *
510	434	***********************************/
511	435
	436	SLOT_INTERFACE_START( 4enlinea_isa8_cards )
	437	SLOT_INTERFACE_INTERNAL("4enlinea", ISA8_CGA_4ENLINEA)
	438	SLOT_INTERFACE_END
	439
	440	static const isa8bus_interface _4enlinea_isabus_intf =
	441	{
	442	// interrupts
	443	DEVCB_NULL,
	444	DEVCB_NULL,
	445	DEVCB_NULL,
	446	DEVCB_NULL,
	447	DEVCB_NULL,
	448	DEVCB_NULL,
	449
	450	// dma request
	451	DEVCB_NULL,
	452	DEVCB_NULL,
	453	DEVCB_NULL
	454	};
	455
	456	/* TODO: irq sources are unknown */
	457	INTERRUPT_GEN_MEMBER(_4enlinea_state::_4enlinea_irq)
	458	{
	459	if(m_irq_count == 0)
	460	device.execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
	461	else
	462	device.execute().set_input_line(0, HOLD_LINE);
	463
	464	m_irq_count++;
	465	m_irq_count&=3;
	466	}
	467
512	468	static MACHINE_CONFIG_START( 4enlinea, _4enlinea_state )
513	469
514	470	/* basic machine hardware */
515	471	MCFG_CPU_ADD("maincpu", Z80, PRG_CPU_CLOCK)
516	472	MCFG_CPU_PROGRAM_MAP(main_map)
517	473	MCFG_CPU_IO_MAP(main_portmap)
518		MCFG_CPU_VBLANK_INT_DRIVER("screen", _4enlinea_state, nmi_line_pulse)
519		MCFG_CPU_PERIODIC_INT_DRIVER(_4enlinea_state, irq0_line_hold, 4*60)
	474	MCFG_CPU_PERIODIC_INT_DRIVER(_4enlinea_state, _4enlinea_irq, 60) //TODO
	475	// MCFG_CPU_PERIODIC_INT_DRIVER(_4enlinea_state, irq0_line_hold, 4*35)
520	476
521	477	MCFG_CPU_ADD("audiocpu", Z80, SND_CPU_CLOCK)
522	478	MCFG_CPU_PROGRAM_MAP(audio_map)
523	479	MCFG_CPU_IO_MAP(audio_portmap)
524	480
525		/* video hardware */
526		MCFG_SCREEN_ADD("screen", RASTER)
527		MCFG_SCREEN_REFRESH_RATE(60)
528		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
529		MCFG_SCREEN_SIZE(320, 200)
530		MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 200-1)
531		MCFG_SCREEN_UPDATE_DRIVER(_4enlinea_state, screen_update_4enlinea)
532		MCFG_SCREEN_PALETTE("palette")
	481	MCFG_ISA8_BUS_ADD("isa", ":maincpu", _4enlinea_isabus_intf)
	482	MCFG_ISA8_SLOT_ADD("isa", "isa1", 4enlinea_isa8_cards, "4enlinea", true)
533	483
534		MCFG_GFXDECODE_ADD("gfxdecode", "palette", 4enlinea)
535		MCFG_PALETTE_ADD("palette", 256)
536	484
537	485	/* 6845 clock is a guess, since it's a UM6845R embedded in the UM487F.
538	486	CRTC_CLOCK is 8MHz, entering for pin 1 of UM487F. This clock is used
r29424	r29425
542	490	CRTC_CLOCK / 4.5 = 59.521093 Hz.
543	491	CRTC_CLOCK / 5.0 = 53.569037 Hz.
544	492	*/
545		// MCFG_MC6845_ADD("crtc", MC6845, "screen", CRTC_CLOCK / 2, mc6845_intf) // seems that MC6845 doesn't support the game mode
546		MCFG_MC6845_ADD("crtc", R6545_1, "screen", CRTC_CLOCK / 4.5, mc6845_intf)
547	493
548	494	/* sound hardware */
549	495	MCFG_SPEAKER_STANDARD_MONO("mono")

branches/new_menus/src/mame/drivers/toaplan2.c
r29424	r29425
36	36	batsugun TP-030 Toaplan Batsugun
37	37	batsuguna TP-030 Toaplan Batsugun (older)
38	38	batsugunsp TP-030 Toaplan Batsugun (Special Version)
39		pwrkick ~~??????~~ Sunwise Power Kick
	39	pwrkick SW931201 Sunwise Power Kick
40	40	othldrby ?????? Sunwise Othello Derby
41		snowbro2 ~~??????~~ Hanafram Snow Bros. 2 - With New Elves
	41	snowbro2 TP-033 Hanafram Snow Bros. 2 - With New Elves
42	42
43	43	* This version of Whoopee!! is on a board labeled TP-020
44	44	(same board number, and same hardware, as Teki Paki)
r29424	r29425
4595	4595
4596	4596	ROM_REGION( 0x40000, "oki", 0 ) /* ADPCM Samples */
4597	4597	ROM_LOAD( "tp030_2.bin", 0x00000, 0x40000, CRC(276146f5) SHA1(bf11d1f6782cefcad77d52af4f7e6054a8f93440) )
	4598
	4599	ROM_REGION( 0x1000, "plds", 0 ) /* Logic for mixing output of both GP9001 GFX controllers */
	4600	ROM_LOAD( "tp030_u19_gal16v8b-15.bin", 0x0000, 0x117, CRC(f71669e8) SHA1(ec1fbe04605fee864af4b01f001af227938c9f21) )
	4601	// ROM_LOAD( "tp030_u19_gal16v8b-15.jed", 0x0000, 0x991, CRC(31be54a2) SHA1(06278942a9a2ea858c0352b2ef5a65bf329b7b82) )
4598	4602	ROM_END
4599	4603
4600	4604
r29424	r29425
4617	4621
4618	4622	ROM_REGION( 0x40000, "oki", 0 ) /* ADPCM Samples */
4619	4623	ROM_LOAD( "tp030_2.bin", 0x00000, 0x40000, CRC(276146f5) SHA1(bf11d1f6782cefcad77d52af4f7e6054a8f93440) )
	4624
	4625	ROM_REGION( 0x1000, "plds", 0 ) /* Logic for mixing output of both GP9001 GFX controllers */
	4626	ROM_LOAD( "tp030_u19_gal16v8b-15.bin", 0x0000, 0x117, CRC(f71669e8) SHA1(ec1fbe04605fee864af4b01f001af227938c9f21) )
4620	4627	ROM_END
4621	4628
4622	4629
r29424	r29425
4639	4646
4640	4647	ROM_REGION( 0x40000, "oki", 0 ) /* ADPCM Samples */
4641	4648	ROM_LOAD( "tp030_2.bin", 0x00000, 0x40000, CRC(276146f5) SHA1(bf11d1f6782cefcad77d52af4f7e6054a8f93440) )
	4649
	4650	ROM_REGION( 0x1000, "plds", 0 ) /* Logic for mixing output of both GP9001 GFX controllers */
	4651	ROM_LOAD( "tp030_u19_gal16v8b-15.bin", 0x0000, 0x117, CRC(f71669e8) SHA1(ec1fbe04605fee864af4b01f001af227938c9f21) )
4642	4652	ROM_END
4643	4653
4644	4654
r29424	r29425
4681	4691	ROM_END
4682	4692
4683	4693	ROM_START( snowbro2b ) // seems to be the same data as the main set, but with the extra user1 rom and different rom layout
4684		ROM_REGION( 0x080000, "maincpu", 0 ) /* Main 68K code */
	4694	ROM_REGION( 0x080000, "maincpu", 0 ) /* Main 68K code - difference with main set is year changed from 1994 to 1998 and upper FFFF fill changed to 00FF fill */
4685	4695	ROM_LOAD16_BYTE( "sb2-prg1.u39", 0x000000, 0x040000, CRC(e1fec8a2) SHA1(30c1a351070d784da9ba0dca68be8a262dba2045) )
4686	4696	ROM_LOAD16_BYTE( "sb2-prg0.u23", 0x000001, 0x040000, CRC(b473cd57) SHA1(331130faa9de01b3ca93845174e8c3684bd269c7) )
4687	4697
4688		ROM_REGION( 0x400000, "gfx1", 0 ) // one of these seems badly read, check
4689		ROM_LOAD( "sb2-gfx.u177", 0x000000, 0x200000, BAD_DUMP CRC(ebeec910) SHA1(e179f393b98135caa8419b68cd979038ab47a413) )
4690		ROM_LOAD( "sb2-gfx.u175", 0x200000, 0x200000, BAD_DUMP CRC(72622795) SHA1(03f041e30b78da2c554b70ed0e5dae7f0214103d) )
	4698	ROM_REGION( 0x400000, "gfx1", 0 )
	4699	ROM_LOAD( "sb2-gfx.u177", 0x000000, 0x200000, CRC(ebeec910) SHA1(e179f393b98135caa8419b68cd979038ab47a413) )
	4700	ROM_LOAD( "sb2-gfx.u175", 0x200000, 0x200000, CRC(e349c75b) SHA1(7d40d00fc0e15a68c427fe94db410bb7cbe00117) )
4691	4701
4692	4702	ROM_REGION( 0x80000, "oki", 0 ) /* ADPCM Samples */
4693		ROM_LOAD( "sb2-snd.4", 0x00000, 0x80000, CRC(638f341e) SHA1(aa3fca25f099339ece1878ea730c5e9f18ec4823) )
	4703	ROM_LOAD( "sb2-snd-4.u17", 0x00000, 0x80000, CRC(638f341e) SHA1(aa3fca25f099339ece1878ea730c5e9f18ec4823) )
4694	4704
4695		ROM_REGION( 0x8000, "user1", 0 ) /* ??? Some sort of table - same as other bootleg boards */
	4705	ROM_REGION( 0x8000, "user1", 0 ) /* ??? Some sort of table - same as other bootleg boards */
4696	4706	ROM_LOAD( "sb2-unk.u100", 0x0000, 0x8000, CRC(456dd16e) SHA1(84779ee64d3ea33ba1ba4dee39b504a81c6811a1) )
4697	4707	ROM_END
4698	4708
r29424	r29425
5392	5402	GAME( 1995, othldrby, 0, othldrby, othldrby,driver_device, 0, ROT0, "Sunwise", "Othello Derby (Japan)", 0 )
5393	5403
5394	5404	GAME( 1994, snowbro2, 0, snowbro2, snowbro2, driver_device, 0, ROT0, "Hanafram", "Snow Bros. 2 - With New Elves / Otenki Paradise", GAME_SUPPORTS_SAVE )
5395		GAME( 1994, snowbro2b, snowbro2, snowbro2, snowbro2, driver_device, 0, ROT0, "bootleg", "Snow Bros. 2 - With New Elves / Otenki Paradise (bootleg)", GAME_SUPPORTS_SAVE )
	5405	GAME( 1998, snowbro2b, snowbro2, snowbro2, snowbro2, driver_device, 0, ROT0, "bootleg", "Snow Bros. 2 - With New Elves / Otenki Paradise (bootleg)", GAME_SUPPORTS_SAVE )
5396	5406
5397	5407	GAME( 1993, sstriker, 0, mahoudai, sstriker, driver_device, 0, ROT270, "Raizing", "Sorcer Striker (set 1)" , GAME_SUPPORTS_SAVE ) // verified on two different PCBs
5398	5408	GAME( 1993, sstrikera, sstriker, mahoudai, sstrikera, driver_device, 0, ROT270, "Raizing", "Sorcer Striker (set 2)" , GAME_SUPPORTS_SAVE ) // from Korean board

branches/new_menus/src/mame/mame.lst
r29424	r29425
2672	2672	vfive // TP-027 (c) 1993 Toaplan (Japan)
2673	2673	batsugun // TP-030 (c) 1993 Toaplan
2674	2674	batsuguna // TP-030 (c) 1993 Toaplan
2675		batsugunsp // TP-??? (c) 1993 Toaplan
2676		snowbro2 // TP-??? (c) 1994 Hanafram
	2675	batsugunsp // TP-030 (c) 1993 Toaplan
	2676	snowbro2 // TP-033 (c) 1994 Hanafram
2677	2677	snowbro2b //
2678	2678	pwrkick // (c) 1994 Sunwise
2679	2679	othldrby // (c) 1995 Sunwise
r29424	r29425
11128	11128	paranoia // (c) 1990 Naxat Soft
11129	11129	tourvis // (c) ???? Tourvision
11130	11130	tvlegaxe // (c) 1988 Victor Musical Industries, Inc. (Tourvision bootleg)
	11131	tvflaptw // (c) 1989 Namco (Tourvision bootleg)
11131	11132	tvusapb // (c) 1989 Aicom (Tourvision bootleg)
	11133	tvvolfd // (c) 1989 Taito (Tourvision bootleg)
11132	11134	tvdunexp // (c) 1989 Hudson / Atlus (Tourvision bootleg)
	11135	tvablast // (c) 1990 Hudson / Kaneko (Tourvision bootleg)
	11136	tvfsoc90 // (c) 1990 Human (Tourvision bootleg)
	11137	tvgomola // (c) 1990 Human (Tourvision bootleg)
	11138	tvsssold // (c) 1990 Hudson / Kaneko (Tourvision bootleg)
11133	11139	tvthbld // (c) 1990 Sega / NEC Avenue (Tourvision bootleg)
11134	11140	tvrs2 // (c) 1990 Taito (Tourvision bootleg)
	11141	tvcolumn // (c) 1991 Telenet Japan (Tourvision bootleg)
	11142	tvjchan // (c) 1991 Hudson (Tourvision bootleg)
	11143	tvpcgen2 // (c) 1991 Hudson (Tourvision bootleg)
	11144	tvpow11 // (c) 1991 Hudson (Tourvision bootleg)
11135	11145	tvpwlg4 // (c) 1991 Hudson (Tourvision bootleg)
11136	11146	tvsci // (c) 1991 Taito (Tourvision bootleg)
11137	11147	tvsvball // (c) 1990 Video System (Tourvision bootleg)

branches/new_menus/src/mame/video/c45.c
r29424	r29425
214	214	}
215	215
216	216	MACHINE_CONFIG_FRAGMENT( namco_c45_road )
217		MCFG_GFXDECODE_ADD("gfxdecode", ":palette", empty) // FIXME
	217	MCFG_GFXDECODE_ADD("gfxdecode", "^palette", empty) // FIXME
218	218	MACHINE_CONFIG_END
219	219	//-------------------------------------------------
220	220	// device_mconfig_additions - return a pointer to

branches/new_menus/src/mame/video/mystwarr.c
r29424	r29425
259	259
260	260	mystwarr_decode_tiles(machine());
261	261
262		m_k055673->alt_k055673_vh_start(machine(), "gfx2", 1, -51, -22, metamrph_sprite_callback);
	262	m_k055673->alt_k055673_vh_start(machine(), "gfx2", 1, -51, -24, metamrph_sprite_callback);
263	263
264	264	konamigx_mixer_init(*m_screen, 0);
265	265

Property changes on: branches/new_menus
Modified: svn:mergeinfo Merged /trunk:r29350-29387

199869 Revisions