MAME SVN History

199869 Revisions

r29405 Monday 7th April, 2014 at 06:04:18 UTC by Miodrag Milanović
Cleanups and version bump

[hash]	a7800.xml coco_flop.xml msx1_cart.xml msx1_flop.xml pico.xml psx.xml
[src]	version.c
[src/build]	flags_gcc.mak png2bdc.c
[src/emu]	clifront.h crsshair.c delegate.h devfind.c digfx.c digfx.h diimage.c diimage.h dioutput.c diserial.h drawgfx.h drivenum.c emualloc.h emuopts.c emupal.c emupal.h ioport.c ioport.h machine.h mame.c memarray.h output.c render.c rendfont.c rendfont.h rendlay.c rendlay.h screen.c screen.h softlist.c softlist.h tilemap.h validity.c validity.h video.c
[src/emu/bus/a2bus]	a2cffa.c a2corvus.c a2pic.c a2ssc.c a2ultraterm.c a2videoterm.c a2videoterm.h a2vulcan.c
[src/emu/bus/adam]	exp.h
[src/emu/bus/adamnet]	fdc.h spi.c spi.h
[src/emu/bus/bml3]	bml3mp1805.h
[src/emu/bus/c64]	magic_formel.c
[src/emu/bus/cbm2]	hrg.c hrg.h user.h
[src/emu/bus/cbmiec]	c1541.c c1541.h c1571.c c1571.h
[src/emu/bus/coco]	coco_fdc.c coco_fdc.h
[src/emu/bus/coleco]	exp.h hand.h sac.h std.h
[src/emu/bus/compucolor]	floppy.c
[src/emu/bus/comx35]	exp.h printer.c
[src/emu/bus/ecbbus]	ecbbus.h grip.c
[src/emu/bus/econet]	e01.c econet.c econet.h
[src/emu/bus/ep64]	exp.h
[src/emu/bus/gameboy]	gb_slot.c
[src/emu/bus/ieee488]	c2031.c c2031.h c2040.c c2040.h c2040fdc.c c8050.c hardbox.c softbox.c
[src/emu/bus/imi7000]	imi5000h.h
[src/emu/bus/isa]	3c505.c adlib.h aga.c aga.h cga.c cga.h dectalk.c ega.h gblaster.h isa.c isa.h mda.c mda.h mufdc.c mufdc.h omti8621.c omti8621.h pds.c sblaster.c sblaster.h sc499.c side116.h
[src/emu/bus/megadrive]	md_carts.c md_slot.c
[src/emu/bus/nes]	act53.c aladdin.c aladdin.h bandai.c bandai.h camerica.c datach.c datach.h jy.c jy.h karastudio.c karastudio.h mmc5.c mmc5.h nes_carts.c nes_ines.inc nes_slot.h nxrom.c sunsoft_dcs.c sunsoft_dcs.h
[src/emu/bus/nubus]	nubus_specpdq.c nubus_specpdq.h
[src/emu/bus/plus4]	c1551.c c1551.h
[src/emu/bus/sms_exp]	smsexp.h
[src/emu/bus/vidbrain]	exp.h
[src/emu/bus/wangpc]	tig.c tig.h wangpc.h
[src/emu/cpu]	cpu.mak
[src/emu/cpu/avr8]	avr8.c avr8.h avr8dasm.c
[src/emu/cpu/cosmac]	cosmac.h
[src/emu/cpu/cubeqcpu]	cubeqcpu.h
[src/emu/cpu/dsp32]	dsp32.c
[src/emu/cpu/esrip]	esrip.h
[src/emu/cpu/g65816]	g65816.h
[src/emu/cpu/h8]	h8.c h8.h h8.lst h83002.h h83006.h h83008.h h83048.h h83337.c h83337.h h8_adc.c h8_adc.h h8_intc.c h8_intc.h h8_port.c h8_port.h h8_sci.c h8_sci.h h8_timer16.c h8_timer16.h h8_timer8.c h8_timer8.h h8s2245.c h8s2245.h h8s2320.c h8s2320.h h8s2357.c h8s2357.h h8s2655.c h8s2655.h
[src/emu/cpu/i386]	i386.c
[src/emu/cpu/i86]	i186.c
[src/emu/cpu/mn10200]	mn10200.c mn10200.h
[src/emu/cpu/pdp1]	pdp1.c pdp1.h tx0.c tx0.h
[src/emu/cpu/powerpc]	ppccom.c
[src/emu/cpu/rsp]	rsp.h rspdrc.c
[src/emu/cpu/sc61860]	sc61860.c
[src/emu/cpu/scmp]	scmp.c
[src/emu/cpu/se3208]	se3208.c se3208.h
[src/emu/cpu/sh2]	sh2comn.c
[src/emu/cpu/sharc]	sharc.c sharc.h
[src/emu/cpu/ssp1601]	ssp1601.c
[src/emu/cpu/superfx]	superfx.c
[src/emu/cpu/tlcs90]	tlcs90.c
[src/emu/cpu/tms32010]	tms32010.c
[src/emu/cpu/tms32025]	tms32025.c tms32025.h
[src/emu/cpu/tms32051]	tms32051.c tms32051.h
[src/emu/cpu/tms34010]	34010gfx.c tms34010.c tms34010.h
[src/emu/cpu/tms7000]	tms7000.c
[src/emu/cpu/unsp]	unsp.c
[src/emu/cpu/upd7810]	upd7810.c upd7810.h
[src/emu/cpu/v60]	v60.c v60.h
[src/emu/cpu/v810]	v810.c
[src/emu/cpu/z180]	z180.c z180tbl.h
[src/emu/cpu/z80]	tlcs_z80.c z80.c
[src/emu/cpu/z8000]	z8000.c z8000.h z8000ops.inc
[src/emu/drivers]	xtal.h
[src/emu/imagedev]	flopdrv.c harddriv.h
[src/emu/machine]	64h156.c 6522via.c 6526cia.h 6850acia.c 68561mpcc.c 74145.h 8042kbdc.h 8530scc.c bcreader.c bcreader.h com8116.h ds75161a.h generic.c hd63450.c hd63450.h hd64610.h i8251.c i8271.c i8271.h i8355.h im6402.h ins8154.h k053252.h kb3600.c kb3600.h kr2376.c kr2376.h laserdsc.c latch8.c latch8.h lh5810.h mb87078.c mb87078.h mc2661.h mc68328.h mc6843.c mc6843.h mc6846.h mc68681.c mc68681.h mc68901.c mc68901.h mm58167.c mm58167.h mm74c922.h mos6530.h mos6551.c msm6242.h ncr5380.h netlist.c netlist.h nsc810.c pc_lpt.c pci.c pckeybrd.c pckeybrd.h rp5c01.h rp5c15.h rtc4543.c rtc65271.h s3c2400.c s3c2400.h s3c2410.c s3c2410.h s3c2440.c s3c2440.h s3c24xx.inc saturn.c seibu_cop.h smc91c9x.h smc92x4.c smc92x4.h tc009xlvc.h terminal.c tmp68301.h tms5501.c upd1990a.c upd1990a.h upd7002.c upd7002.h upd765.c wd17xx.c wd17xx.h wd33c93.h z80dma.c z8536.h
[src/emu/netlist]	nl_base.c nl_base.h nl_dice_compat.h nl_lists.h nl_parser.c nl_parser.h nl_setup.c nl_setup.h pstate.c pstate.h pstring.h
[src/emu/netlist/analog]	nld_bjt.c nld_bjt.h nld_fourterm.c nld_fourterm.h nld_solver.c nld_solver.h nld_switches.c nld_switches.h nld_twoterm.c nld_twoterm.h
[src/emu/netlist/devices]	net_lib.c nld_4066.c nld_4066.h nld_7400.c nld_7400.h nld_7402.c nld_7402.h nld_7404.c nld_7404.h nld_7410.c nld_7410.h nld_74107.c nld_74107.h nld_74153.c nld_74153.h nld_7420.c nld_7420.h nld_7425.c nld_7425.h nld_7427.c nld_7427.h nld_7430.c nld_7430.h nld_7448.c nld_7448.h nld_7450.c nld_7450.h nld_7474.c nld_7474.h nld_7483.c nld_7483.h nld_7486.c nld_7486.h nld_7490.c nld_7490.h nld_7493.c nld_7493.h nld_74ls629.c nld_74ls629.h nld_9316.c nld_9316.h nld_legacy.c nld_ne555.c nld_ne555.h nld_signal.h nld_system.c nld_system.h
[src/emu/sound]	aica.c aica.h ay8910.c cdp1869.c cdp1869.h dmadac.c dmadac.h es5503.c es5503.h ics2115.c k007232.h mos6560.h msm5205.h msm5232.c msm5232.h qs1000.c qs1000.h qsound.c scsp.c scsp.h sp0256.h spu.c tc8830f.c upd7759.c upd7759.h votrax.h ymf278b.c ymz280b.c zsg2.c zsg2.h
[src/emu/ui]	barcode.c barcode.h devctrl.h filemngr.c filesel.c filesel.h imgcntrl.c imginfo.c mainmenu.c menu.c menu.h selgame.c selgame.h swlist.c swlist.h ui.c ui.h viewgfx.c
[src/emu/video]	315_5124.h 315_5313.c 315_5313.h crt9007.h crt9021.h crt9212.h dl1416.h ef9345.h epic12.c epic12.h epic12_blit2.c epic12_blit3.c epic12_blit4.c epic12_blit6.c epic12_blit7.c epic12_blit8.c epic12in.inc epic12pixel.inc fixfreq.c hd44352.h hd44780.h hd61830.h huc6260.h huc6270.h mb_vcu.h mc6845.c mc6847.c mc6847.h pc_vga.c ramdac.h tms34061.c tms34061.h upd3301.c upd7220.h v9938.h vic4567.h
[src/lib/formats]	cassimg.c ccvf_dsk.c d64_dsk.c fmtowns_dsk.c g64_dsk.c mbee_cas.h phc25_cas.c phc25_cas.h sol_cas.c sol_cas.h sorc_cas.h spc1000_cas.h z80ne_dsk.c
[src/lib/libflac/include/FLAC]	export.h format.h metadata.h stream_decoder.h stream_encoder.h
[src/lib/libflac/include/private]	fixed.h float.h lpc.h window.h
[src/lib/libflac/libFLAC]	bitreader.c float.c lpc.c md5.c metadata_iterators.c metadata_object.c stream_decoder.c stream_encoder.c
[src/lib/util]	chd.h corealloc.c cstrpool.c cstrpool.h options.h palette.c palette.h tagmap.c tagmap.h
[src/mame]	mame.lst
[src/mame/audio]	cclimber.c cclimber.h cps3.c namco52.c namco52.h namco54.c namco54.h taito_en.h taito_zm.c taito_zm.h
[src/mame/drivers]	1942.c 1945kiii.c 20pacgal.c 3x3puzzl.c 4enlinea.c 5clown.c 88games.c a1supply.c acefruit.c aerofgt.c albazc.c aleisttl.c amusco.c arcadia.c aristmk4.c asteroid.c astinvad.c astrof.c asuka.c atarigx2.c atarittl.c atetris.c backfire.c bailey.c battlnts.c beathead.c big10.c blackt96.c bladestl.c blmbycar.c blockhl.c bloodbro.c blstroid.c bmcbowl.c bmcpokr.c bnstars.c boogwing.c bowltry.c boxer.c btime.c bzone.c cabal.c calomega.c carrera.c cavepc.c cball.c cbuster.c cd32.c centiped.c chanbara.c chicago.c chqflag.c cliffhgr.c cmmb.c cninja.c cntsteer.c cobra.c coinmstr.c coolridr.c cps1.c cps3.c crystal.c cswat.c cubeqst.c cv1k.c d9final.c dacholer.c dai3wksi.c dassault.c dblcrown.c dblewing.c ddealer.c ddenlovr.c ddragon3.c dec0.c deco32.c deco_ld.c deshoros.c destroyr.c dfruit.c discoboy.c dkong.c docastle.c dominob.c dooyong.c dorachan.c dotrikun.c dreamwld.c dunhuang.c dwarfd.c ecoinf2.c electra.c enigma2.c exedexes.c exerion.c exidyttl.c exprraid.c f1gp.c fantland.c fcrash.c feversoc.c firefox.c firetrk.c flipjack.c flkatck.c flyball.c fungames.c funkyjet.c funworld.c gaelco3d.c gaiden.c galaga.c galaxi.c galaxian.c galaxold.c galivan.c galpani2.c gaplus.c gatron.c gbusters.c gei.c ggconnie.c ghosteo.c gladiatr.c go2000.c goldnpkr.c goldstar.c gstream.c gsword.c gticlub.c gunpey.c gunsmoke.c halleys.c highvdeo.c hng64.c hornet.c hshavoc.c hvyunit.c hyperspt.c igs017.c igs_m027.c igspoker.c ikki.c intrscti.c itgambl3.c itgamble.c jackie.c jclub2.c kaneko16.c kingobox.c koftball.c konamigx.c konendev.c kopunch.c lastbank.c lethal.c littlerb.c ltcasino.c m14.c m62.c m63.c mappy.c mazerbla.c mcr3.c mcr68.c meadwttl.c megaphx.c megaplay.c megatech.c metalmx.c metro.c mgolf.c mhavoc.c micro3d.c mil4000.c mirage.c mitchell.c mlanding.c model1.c model2.c model3.c monacogp.c mpoker.c mpu4.c mpu4hw.c mpu4misc.c mugsmash.c multfish.c multfish_boot.c multfish_ref.c murogmbl.c mystwarr.c namcos12.c namcos22.c naomi.c nbmj8891.c nbmj8900.c neogeo.c neptunp2.c nightgal.c ninjaw.c nmg5.c nss.c nwk-tr.c nycaptor.c nyny.c offtwall.c ohmygod.c olibochu.c onetwo.c othello.c overdriv.c pacman.c panicr.c pcxt.c pengadvb.c peplus.c pgm.c pgm2.c photon.c pinkiri8.c pkscram.c pktgaldx.c polepos.c pong.c popeye.c popobear.c puckpkmn.c pzletime.c qdrmfgp.c quantum.c r2dx_v33.c raiden2.c ramtek.c rcorsair.c realbrk.c rltennis.c rockrage.c rohga.c rollerg.c rungun.c s7.c safarir.c scobra.c scramble.c seabattl.c segac2.c segaorun.c segas16a.c segas18.c segaybd.c seicross.c seta.c seta2.c sf.c sidearms.c sigmab98.c simpl156.c skylncr.c slapfght.c slapshot.c smsmcorp.c spy.c statriv2.c stuntair.c subs.c subsino.c subsino2.c supbtime.c supercrd.c superwng.c system16.c taito_b.c taito_f2.c taitoair.c taitogn.c taitojc.c taitottl.c taotaido.c tceptor.c tecmo16.c thunderx.c toaplan1.c toaplan2.c tourtabl.c toypop.c triforce.c truco.c tugboat.c tumbleb.c tumblep.c turrett.c uapce.c ultraman.c vamphalf.c vaportra.c vball.c vega.c vendetta.c vlc.c volfied.c vp101.c wardner.c warpwarp.c wecleman.c welltris.c witch.c wiz.c wolfpack.c xmen.c xybots.c xyonix.c zaxxon.c zr107.c
[src/mame/etc]	template_driver.c
[src/mame/includes]	1943.h airbustr.h amiga.h atari.h atarisy1.h aztarac.h balsente.h battlane.h battlera.h bfm_sc45.h bigevglf.h bladestl.h btime.h bublbobl.h bwing.h calomega.h carpolo.h cave.h ccastles.h cchasm.h centiped.h cidelsa.h citycon.h cninja.h combatsc.h contra.h cop01.h copsnrob.h cps1.h crbaloon.h crimfght.h crshrace.h cvs.h darius.h dbz.h dcheese.h deadang.h dec8.h deco32.h djboy.h dkong.h docastle.h equites.h espial.h esripsys.h exerion.h exidy.h exidy440.h exprraid.h f1gp.h fastfred.h fcombat.h fgoal.h firetrap.h firetrk.h fuukifg2.h fuukifg3.h gaelco3d.h galaga.h galpanic.h gaplus.h gcpinbal.h gladiatr.h gottlieb.h gradius3.h grchamp.h gridlee.h gsword.h gyruss.h harddriv.h homedata.h homerun.h hyprduel.h ikki.h irobot.h ironhors.h itech32.h jackal.h kaneko16.h karnov.h konamigx.h labyrunr.h ladybug.h laserbat.h lasso.h lastduel.h lazercmd.h liberate.h lkage.h lockon.h lsasquad.h m10.h m107.h m52.h m72.h m92.h macrossp.h matmania.h mcatadv.h mcr68.h meadows.h metlclsh.h micro3d.h model3.h mouser.h mrflea.h ms32.h mugsmash.h multfish.h munchmo.h n8080.h namcona1.h namcos1.h namcos2.h naughtyb.h nemesis.h ninjaw.h nitedrvr.h nycaptor.h ojankohs.h orbit.h othunder.h pandoras.h paradise.h pcktgal.h pktgaldx.h playch10.h pooyan.h popeye.h portrait.h powerins.h psikyo4.h pushman.h rainbow.h rockrage.h rohga.h rungun.h sbasketb.h scramble.h segas16b.h segas18.h seicross.h seta.h skyfox.h slapfght.h slapshot.h snes.h snowbros.h spacefb.h sprcros2.h ssv.h stadhero.h stv.h system16.h tail2nos.h taito_f2.h taito_h.h taito_o.h taitojc.h taitosj.h tceptor.h thedeep.h thunderx.h timeplt.h toki.h topspeed.h tp84.h tubep.h tumbleb.h tunhunt.h turbo.h twin16.h undrfire.h vaportra.h volfied.h warriorb.h wecleman.h wgp.h wiz.h zac2650.h zodiack.h
[src/mame/layout]	cherryb3.lay dblcrown.lay gamball.lay goldstar.lay
[src/mame/machine]	asteroid.c atari.c atarigen.h cdi070.h gaelco3d.h igs036crypt.c igs036crypt.h inder_sb.c inder_sb.h inder_vid.c inder_vid.h megadriv.c namco06.c namco06.h namco50.c namco50.h namco51.h namco53.c namco53.h namco62.h namcoio.h namcos1.c naomim4.c pcecommn.c pcecommn.h slapfght.c tait8741.c tait8741.h taitoio.h
[src/mame/video]	alpha68k.c amspdwy.c angelkds.c appoooh.c argus.c atarimo.c avgdvg.c avgdvg.h baraduke.c battlane.c battlex.c bfm_adr2.c bfm_adr2.h bfm_dm01.c bfm_dm01.h bogeyman.c bwing.c c45.c c45.h canyon.c carpolo.c cclimber.c chaknpop.c champbas.c cheekyms.c combatsc.c cps1.c crimfght.c darkmist.c ddribble.c dec8.c decbac06.h deckarn.h decmxc06.c decmxc06.h deco16ic.h decocomn.h decospr.h djmain.c drgnmst.c exerion.c fcombat.c firetrk.c fitfight.c gaelco2.c galaxian.c goindol.c gottlieb.c gotya.c gp9001.h grchamp.c gticlub.c gyruss.c hyperspt.c jalblend.c k001005.h k001604.h k007121.h k007342.c k007342.h k007420.c k007420.h k051316.h k053244_k053245.h k053246_k053247_k055673.h k053250.h k054338.c kaneko16.c kaneko_spr.c kaneko_spr.h kopunch.c ladyfrog.c lastduel.c m10.c m52.c mermaid.c mikie.c mrflea.c ms32.c mugsmash.c munchmo.c mystston.c namcona1.c namcos22.c ninjakd2.c nova2001.c oneshot.c pooyan.c popeye.c ppu2c0x.c ppu2c0x.h psikyo4.c raiden.c sbasketb.c segaic16.h segaic24.h seibu_crtc.h shangkid.c sidearms.c slapfght.c solomon.c sonson.c ssozumo.c sspeedr.c stadhero.c starcrus.c stlforce.c strnskil.c tagteam.c taito_h.c taito_o.c taitoair.c taitosj.c tc0080vco.h tc0110pcr.c tc0110pcr.h tc0480scp.h tceptor.c tecmo_spr.c thepit.c tia.h tigeroad.c trackfld.c tunhunt.c twincobr.c wecleman.c wiz.c wolfpack.c ygv608.c ygv608.h yiear.c zaxxon.c
[src/mess]	mess.lst mess.mak
[src/mess/audio]	upd1771.h
[src/mess/drivers]	a2600.c a7000.c a7800.c abc1600.c ace.c adam.c alphasma.c alphatro.c amiga.c amstr_pc.c amstrad.c amust.c apc.c apf.c apollo.c apple2.c apple2gs.c apple3.c applix.c apricot.c apricotf.c apricotp.c argo.c asst128.c at.c atari400.c atarist.c atm.c avigo.c bcs3.c beehive.c bigbord2.c binbug.c bmjr.c bml3.c c128.c casloopy.c cat.c coco12.c compis.c compucolor.c d6800.c dct11em.c dm7000.c dms5000.c esq1.c esq5505.c esqasr.c esqkt.c esqmr.c europc.c fanucs15.c fanucspmg.c fk1.c fmtowns.c fp6000.c gb.c geniusiq.c grfd2301.c hec2hrp.c homelab.c homez80.c hp48.c hp9k.c hprot1.c hunter2.c hx20.c ibm6580.c ibmpcjr.c ie15.c indiana.c intv.c ip20.c ip22.c iq151.c irisha.c itt3030.c jonos.c jupiter.c k8915.c kaypro.c konin.c kyocera.c lcmate2.c llc.c lola8a.c m20.c mac.c mbc200.c mbee.c mc80.c megadriv.c mes.c micronic.c mirage.c mk85.c mk90.c modellot.c molecular.c msx.c multi16.c multi8.c mx2178.c myb3k.c mycom.c mz2500.c mz3500.c mz700.c mz80.c nakajies.c nanos.c nc.c ng_aes.c ngp.c octopus.c odyssey2.c p2000t.c palm.c paso1600.c pasopia7.c pb1000.c pc.c pc100.c pc1500.c pc4.c pc6001.c pc8001.c pc8801.c pc9801.c pcm.c pcw16.c pda600.c pentagon.c phc25.c phunsy.c pipbug.c plan80.c plus4.c pocketc.c portfoli.c pp01.c psion.c psx.c pt68k4.c ptcsol.c pv1000.c pve500.c px4.c ql.c qx10.c rainbow.c rd110.c replicator.c rex6000.c rm380z.c rmt32.c rsc55.c rx78.c sapi1.c saturn.c sbrain.c sgi_ip2.c sitcom.c sm1800.c smc777.c socrates.c softbox.c sorcerer.c special.c spectrum.c ssem.c stratos.c super80.c supracan.c sv8000.c svmu.c swtpc09.c sym1.c tandy1t.c tandy2k.c tavernie.c thomson.c ti85.c ti89.c tim011.c tim100.c tk80bs.c trs80.c uknc.c unior.c unistar.c univac.c ut88.c v6809.c vboy.c vector06.c victor9k.c vip.c vt100.c vt220.c vt320.c vt520.c vta2000.c vtech1.c wangpc.c wswan.c x07.c x68k.c xerox820.c ymmu100.c z100.c z1013.c z80ne.c z9001.c zorba.c zrt80.c
[src/mess/includes]	a7800.h advision.h amstrad.h apollo.h apple2gs.h apple3.h apricotf.h aquarius.h atarist.h avigo.h b2m.h bbc.h dm7000.h einstein.h fm7.h genpc.h intv.h kaypro.h lisa.h mc1502.h mikromik.h nascom1.h p2000t.h partner.h pcw.h pocketc.h ql.h rmnimbus.h softbox.h special.h studio2.h super80.h svi318.h swtpc09.h thomson.h tiki100.h tvc.h vc4000.h vector06.h x68k.h z88.h zx.h
[src/mess/layout]	pve500.lay rainbow.lay
[src/mess/machine]	6883sam.h a7800.c amstrad.c apollo.c apollo_kbd.c apple2.c apple2gs.c apple3.c apricotkb.c apricotkb.h atarifdc.c atarifdc.h bbc.c beta.h dec_lk201.c dgn_beta.c hp48.c mac.c mackbd.h mega32x.c mega32x.h megacd.h micropolis.h nes.c oric.c partner.c pecom.c sgi.c sgi.h smartmed.c sms.c svi318.c swtpc09.c thomson.c x68k_kbd.c zx8302.h
[src/mess/machine/ti99]	990_hd.h grom.c grom.h gromport.c speech8.h
[src/mess/video]	a7800.c abc80.c abc800.c apollo.c apple3.c gb_lcd.c gime.h intv.c mikromik.c nascom1.c osi.c pc1251.c pc1350.c pc1401.c tmc600.c v1050.c vtvideo.c vtvideo.h zx8301.h
[src/osd]	osdcomm.h osdcore.h
[src/osd/sdl]	blit13.h drawogl.c gl_shader_mgr.c window.c
[src/tools]	nltool.c srcclean.c unidasm.c

trunk/hash/psx.xml
r29404	r29405
2	2	<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
3	3	<softwarelist name="psx" description="Sony Playstation CD-ROMs">
4	4
5		<!-- todo, reconvert original dumps using current CHDMAN verison - Feb 2014 -->
6
	5	<!-- todo, reconvert original dumps using current CHDMAN verison - Feb 2014 -->
	6
7	7	<!--
8	8	***********************
9	9	NON-REDUMP Rips
r29404	r29405
49	49
50	50	<!-- Prototype disks -->
51	51
52
	52
53	53	<software name="bublbob2" >
54	54	<!-- Original images
55		bb2.bin 62,620,864 1c2c9f63
56		bb2.cue 69 096e5077
	55	bb2.bin 62,620,864 1c2c9f63
	56	bb2.cue 69 096e5077
57	57	-->
58	58	<description>Bubble Bobble II (prototype)</description>
59	59	<year>1995</year>
r29404	r29405
65	65	</part>
66	66	</software>
67	67
68
69
	68
	69
70	70	<software name="baldgate" supported="no">
71	71	<!-- Original images (from drx)
72	72	<rom name="baldur's gate - disc 1.bin" size="657475728" crc="96e9befa"/>

trunk/hash/msx1_flop.xml
r29404	r29405
6	6	Things listed here should have a requirement of BASIC 1.0 + Disk Basic 1.0 (ie a Standard MSX1 type system with FDD)
7	7	I've noticed some 'MSX1' floppy images in TOSEC seem to require a higher BASIC version?
8	8	Some also require more RAM? the driver currently isn't very flexible.
9
	9
10	10	This for now is just a skeleton list for quick testing.
11
	11
12	12	To use the floppy drive the disk basic ROM must be mounted, example use case.
13	13	msx -cart1 diskbas -flop1 ohshit
14
	14
15	15	-->
16	16
17	17	<software name="jsw2">
r29404	r29405
25	25	</part>
26	26	</software>
27	27
28		<software name="ohmummy">
29		<description>Oh Mummy!!</description>
30		<year>1984</year>
31		<publisher>Longman Software</publisher>
32		<part name="flop1" interface="floppy_5_25">
33		<dataarea name="flop" size="737280">
34		<rom name="oh mummy!! (1984)(longman software)(gb).dsk" size="737280" crc="9cf775cc" sha1="cd7db0faf25ae33699b1708a19a874e3662e158a" offset="0" />
35		</dataarea>
36		</part>
37		</software>
	28	<software name="ohmummy">
	29	<description>Oh Mummy!!</description>
	30	<year>1984</year>
	31	<publisher>Longman Software</publisher>
	32	<part name="flop1" interface="floppy_5_25">
	33	<dataarea name="flop" size="737280">
	34	<rom name="oh mummy!! (1984)(longman software)(gb).dsk" size="737280" crc="9cf775cc" sha1="cd7db0faf25ae33699b1708a19a874e3662e158a" offset="0" />
	35	</dataarea>
	36	</part>
	37	</software>
38	38
39		<software name="ohshit">
40		<description>Oh Shit!</description>
41		<year>1986</year>
42		<publisher>Aackosoft</publisher>
43		<part name="flop1" interface="floppy_5_25">
44		<dataarea name="flop" size="737280">
45		<rom name="oh shit! (1986)(aackosoft)(nl).dsk" size="737280" crc="735ebc21" sha1="7de3f69a8a5136e0dd25214d36b1194a6506b377" offset="0" />
46		</dataarea>
47		</part>
48		</software>
	39	<software name="ohshit">
	40	<description>Oh Shit!</description>
	41	<year>1986</year>
	42	<publisher>Aackosoft</publisher>
	43	<part name="flop1" interface="floppy_5_25">
	44	<dataarea name="flop" size="737280">
	45	<rom name="oh shit! (1986)(aackosoft)(nl).dsk" size="737280" crc="735ebc21" sha1="7de3f69a8a5136e0dd25214d36b1194a6506b377" offset="0" />
	46	</dataarea>
	47	</part>
	48	</software>
49	49
50		<software name="ohno" cloneof="ohshit">
51		<description>Oh No!</description>
52		<year>1986</year>
53		<publisher>Eaglesoft</publisher>
54		<part name="flop1" interface="floppy_5_25">
55		<dataarea name="flop" size="737280">
56		<rom name="oh no! (1986)(eaglesoft)(nl)[aka oh shit!].dsk" size="737280" crc="aee65f34" sha1="5c2cd6dd8192a8c29fc0e272181272cb26cc2af6" offset="0" />
57		</dataarea>
58		</part>
59		</software>
	50	<software name="ohno" cloneof="ohshit">
	51	<description>Oh No!</description>
	52	<year>1986</year>
	53	<publisher>Eaglesoft</publisher>
	54	<part name="flop1" interface="floppy_5_25">
	55	<dataarea name="flop" size="737280">
	56	<rom name="oh no! (1986)(eaglesoft)(nl)[aka oh shit!].dsk" size="737280" crc="aee65f34" sha1="5c2cd6dd8192a8c29fc0e272181272cb26cc2af6" offset="0" />
	57	</dataarea>
	58	</part>
	59	</software>
60	60
61	61
62	62	</softwarelist>

trunk/hash/pico.xml
r29404	r29405
2354	2354	</dataarea>
2355	2355	</part>
2356	2356	</software>
2357
	2357
2358	2358	<software name="okaissod">
2359	2359	<description>NHK Okaasan to Issho Do Re Mi Fa Do~nuts! Oekaki Daisuki! Omoshiro Oekaki Daishuugou! (Jpn)</description>
2360	2360	<year>1998</year>

trunk/hash/a7800.xml
r29404	r29405
2264	2264	</part>
2265	2265	</software>
2266	2266
2267		<!-- XM board enhanced -->
	2267	<!-- XM board enhanced -->
2268	2268
2269		<!-- these should require an XM board? but the emulation seems to be built into the base driver?-->
2270		<!-- these have had the header stripped vs the .a78 files offered
2271		there was also a 'binary' with size 0x24000, CRC fd503bd4 -->
2272		<software name="dkongxm">
2273		<description>Donkey Kong (homebrew, XM enhanced, HSC support) (Demo)</description>
2274		<year>2012</year>
2275		<publisher><homebrew></publisher> <!-- TEP392 -->
2276		<sharedfeat name="compatibility" value="PAL"/>
2277		<part name="cart" interface="a7800_cart">
2278		<feature name="pcb_type" value="TYPE-XM" />
2279		<dataarea name="rom" size="0x24000">
2280		<rom name="dkxm_final_demo_pal_hsc.a78" size="0x24000" crc="6510b674" sha1="65b723b470d287af51e9888813149c43fb11ac26" offset="0" />
2281		</dataarea>
2282		</part>
2283		</software>
	2269	<!-- these should require an XM board? but the emulation seems to be built into the base driver?-->
	2270	<!-- these have had the header stripped vs the .a78 files offered
	2271	there was also a 'binary' with size 0x24000, CRC fd503bd4 -->
	2272	<software name="dkongxm">
	2273	<description>Donkey Kong (homebrew, XM enhanced, HSC support) (Demo)</description>
	2274	<year>2012</year>
	2275	<publisher><homebrew></publisher> <!-- TEP392 -->
	2276	<sharedfeat name="compatibility" value="PAL"/>
	2277	<part name="cart" interface="a7800_cart">
	2278	<feature name="pcb_type" value="TYPE-XM" />
	2279	<dataarea name="rom" size="0x24000">
	2280	<rom name="dkxm_final_demo_pal_hsc.a78" size="0x24000" crc="6510b674" sha1="65b723b470d287af51e9888813149c43fb11ac26" offset="0" />
	2281	</dataarea>
	2282	</part>
	2283	</software>
2284	2284
2285		<software name="dkongxmu" cloneof="dkongxm" >
2286		<description>Donkey Kong (homebrew, XM enhanced, HSC support) (Demo) (NTSC)</description>
2287		<year>2012</year>
2288		<publisher><homebrew></publisher> <!-- TEP392 -->
2289		<sharedfeat name="compatibility" value="NTSC"/>
2290		<part name="cart" interface="a7800_cart">
2291		<feature name="pcb_type" value="TYPE-XM" />
2292		<dataarea name="rom" size="0x24000">
2293		<rom name="dkxm_final_demo_ntsc_hsc.a78" size="0x24000" crc="2c67fea7" sha1="7825c1946e3c7492fa9bbfae33029cd68c0d1135" offset="0" />
2294		</dataarea>
2295		</part>
2296		</software>
	2285	<software name="dkongxmu" cloneof="dkongxm" >
	2286	<description>Donkey Kong (homebrew, XM enhanced, HSC support) (Demo) (NTSC)</description>
	2287	<year>2012</year>
	2288	<publisher><homebrew></publisher> <!-- TEP392 -->
	2289	<sharedfeat name="compatibility" value="NTSC"/>
	2290	<part name="cart" interface="a7800_cart">
	2291	<feature name="pcb_type" value="TYPE-XM" />
	2292	<dataarea name="rom" size="0x24000">
	2293	<rom name="dkxm_final_demo_ntsc_hsc.a78" size="0x24000" crc="2c67fea7" sha1="7825c1946e3c7492fa9bbfae33029cd68c0d1135" offset="0" />
	2294	</dataarea>
	2295	</part>
	2296	</software>
2297	2297
2298		<software name="dkongxmn" cloneof="dkongxm">
2299		<description>Donkey Kong (homebrew, XM enhanced) (Demo)</description>
2300		<year>2012</year>
2301		<publisher><homebrew></publisher> <!-- TEP392 -->
2302		<sharedfeat name="compatibility" value="PAL"/>
2303		<part name="cart" interface="a7800_cart">
2304		<feature name="pcb_type" value="TYPE-XM" />
2305		<dataarea name="rom" size="0x24000">
2306		<rom name="dkxm_final_demo_pal.a78" size="0x24000" crc="d362712e" sha1="118c462d6698bd23c378785f80062fdd7d65ca00" offset="0" />
2307		</dataarea>
2308		</part>
2309		</software>
	2298	<software name="dkongxmn" cloneof="dkongxm">
	2299	<description>Donkey Kong (homebrew, XM enhanced) (Demo)</description>
	2300	<year>2012</year>
	2301	<publisher><homebrew></publisher> <!-- TEP392 -->
	2302	<sharedfeat name="compatibility" value="PAL"/>
	2303	<part name="cart" interface="a7800_cart">
	2304	<feature name="pcb_type" value="TYPE-XM" />
	2305	<dataarea name="rom" size="0x24000">
	2306	<rom name="dkxm_final_demo_pal.a78" size="0x24000" crc="d362712e" sha1="118c462d6698bd23c378785f80062fdd7d65ca00" offset="0" />
	2307	</dataarea>
	2308	</part>
	2309	</software>
2310	2310
2311		<software name="dkongxmnu" cloneof="dkongxm" >
2312		<description>Donkey Kong (homebrew, XM enhanced) (Demo) (NTSC)</description>
2313		<year>2012</year>
2314		<publisher><homebrew></publisher> <!-- TEP392 -->
2315		<sharedfeat name="compatibility" value="NTSC"/>
2316		<part name="cart" interface="a7800_cart">
2317		<feature name="pcb_type" value="TYPE-XM" />
2318		<dataarea name="rom" size="0x24000">
2319		<rom name="dkxm_final_demo_ntsc.a78" size="0x24000" crc="6e170055" sha1="f4da231312da06ff9e8af5681b5013b14886b455" offset="0" />
2320		</dataarea>
2321		</part>
2322		</software>
	2311	<software name="dkongxmnu" cloneof="dkongxm" >
	2312	<description>Donkey Kong (homebrew, XM enhanced) (Demo) (NTSC)</description>
	2313	<year>2012</year>
	2314	<publisher><homebrew></publisher> <!-- TEP392 -->
	2315	<sharedfeat name="compatibility" value="NTSC"/>
	2316	<part name="cart" interface="a7800_cart">
	2317	<feature name="pcb_type" value="TYPE-XM" />
	2318	<dataarea name="rom" size="0x24000">
	2319	<rom name="dkxm_final_demo_ntsc.a78" size="0x24000" crc="6e170055" sha1="f4da231312da06ff9e8af5681b5013b14886b455" offset="0" />
	2320	</dataarea>
	2321	</part>
	2322	</software>
2323	2323	</softwarelist>

trunk/hash/msx1_cart.xml
r29404	r29405
16845	16845
16846	16846
16847	16847
16848		<!-- Devices -->
	16848	<!-- Devices -->
16849	16849
16850		<!-- mounting this should add the floppy drive, rather than it always being there? -->
16851		<software name="diskbas">
16852		<description>Disk BASIC v1.0 for FS-FD1 (Japan)</description>
16853		<year>1987</year>
16854		<publisher>Matsushita</publisher>
16855		<part name="cart" interface="msx_cart">
16856		<feature name="mapper" value="DISK_ROM" />
16857		<dataarea name="rom" size="0x4000">
16858		<rom name="disk basic v1.0 for fs-fd1 (1987)(matsushita electric industrial)(jp).rom" size="0x4000" crc="4c9b8214" sha1="8e3f6f08309f082a82be8298a66c9b90f2d34ad4" offset="0" />
16859		</dataarea>
16860		</part>
16861		</software>
	16850	<!-- mounting this should add the floppy drive, rather than it always being there? -->
	16851	<software name="diskbas">
	16852	<description>Disk BASIC v1.0 for FS-FD1 (Japan)</description>
	16853	<year>1987</year>
	16854	<publisher>Matsushita</publisher>
	16855	<part name="cart" interface="msx_cart">
	16856	<feature name="mapper" value="DISK_ROM" />
	16857	<dataarea name="rom" size="0x4000">
	16858	<rom name="disk basic v1.0 for fs-fd1 (1987)(matsushita electric industrial)(jp).rom" size="0x4000" crc="4c9b8214" sha1="8e3f6f08309f082a82be8298a66c9b90f2d34ad4" offset="0" />
	16859	</dataarea>
	16860	</part>
	16861	</software>
16862	16862
16863		<!-- SORT -->
	16863	<!-- SORT -->
16864	16864
16865	16865
16866	16866

trunk/hash/coco_flop.xml
r29404	r29405
3	3
4	4	<softwarelist name="coco_flop" description="Tandy Radio Shack Color Computer disk images">
5	5
6		<!-- coco3 only requires 512Kb, audio is a farty, run best with a a 6309? - coco3h driver) -->
7		<!-- RUN"DONKEY" -->
8		<software name="dkong" supported ="partial">
	6	<!-- coco3 only requires 512Kb, audio is a farty, run best with a a 6309? - coco3h driver) -->
	7	<!-- RUN"DONKEY" -->
	8	<software name="dkong" supported ="partial">
9	9	<description>Donkey Kong (Sock Master's Donkey Kong Emulator for CoCo 3) (512Kb)</description>
10	10	<year>2007</year>
11	11	<publisher>Sock Master</publisher>

trunk/src/build/flags_gcc.mak
r29404	r29405
8	8	ifeq ($(findstring 4.8.,$(TEST_GCC)),4.8.)
9	9	CCOMFLAGS += -Wno-narrowing -Wno-attributes -Wno-unused-local-typedefs
10	10	# array bounds checking seems to be buggy in 4.8.1 (try it on video/stvvdp1.c and video/model1.c without -Wno-array-bounds)
11		CCOMFLAGS += -Wno-unused-variable -Wno-array-bounds -Wno-strict-overflow
	11	CCOMFLAGS += -Wno-unused-variable -Wno-array-bounds -Wno-strict-overflow
12	12	endif
13	13
14	14	ifeq ($(findstring arm,$(UNAME)),arm)

trunk/src/build/png2bdc.c
r29404	r29405
74	74	INT32 width; // width from this character to the next
75	75	INT32 xoffs, yoffs; // X and Y offset from baseline to top,left of bitmap
76	76	INT32 bmwidth, bmheight; // width and height of bitmap
77		bitmap_argb32 * bitmap; // pointer to the bitmap containing the raw data
	77	bitmap_argb32 * bitmap; // pointer to the bitmap containing the raw data
78	78	};
79	79
80	80
r29404	r29405
107	107
108	108	//-------------------------------------------------
109	109	// write_data - write data to the given file and
110		// throw an exception if an error occurs
	110	// throw an exception if an error occurs
111	111	//-------------------------------------------------
112	112
113	113	static void write_data(core_file &file, UINT8 base, UINT8 end)
r29404	r29405
123	123
124	124	//-------------------------------------------------
125	125	// render_font_save_cached - write the cached
126		// data out to the file
	126	// data out to the file
127	127	//-------------------------------------------------
128	128
129	129	static bool render_font_save_cached(render_font &font, const char *filename, UINT32 hash)
r29404	r29405
248	248
249	249	//-------------------------------------------------
250	250	// bitmap_to_chars - convert a bitmap to
251		// characters in the given font
	251	// characters in the given font
252	252	//-------------------------------------------------
253	253
254	254	static bool bitmap_to_chars(bitmap_argb32 &bitmap, render_font &font)

trunk/src/mame/etc/template_driver.c
r29404	r29405
146	146
147	147	/* video hardware */
148	148	MCFG_SCREEN_ADD("screen", RASTER)
149		// MCFG_SCREEN_REFRESH_RATE(60)
150		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
	149	// MCFG_SCREEN_REFRESH_RATE(60)
	150	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
151	151	MCFG_SCREEN_UPDATE_DRIVER(xxx_state, screen_update)
152		// MCFG_SCREEN_SIZE(328, 328)
153		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
	152	// MCFG_SCREEN_SIZE(328, 328)
	153	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
154	154	MCFG_SCREEN_RAW_PARAMS(MAIN_CLOCK/2, 442, 0, 320, 264, 0, 240) /* generic video timing, change accordingly */
155	155	MCFG_SCREEN_PALETTE("palette")
156	156

trunk/src/mame/layout/gamball.lay
r29404	r29405
10	10	<bounds x="0" y="0" width="1" height="1" />
11	11	<color red="0" green="0" blue="0" />
12	12	</rect>
13		</element>
	13	</element>
14	14	<element name="reellamp">
15	15	<rect state ="0">
16	16	<bounds x="0" y="0" width="7" height="3" />
r29404	r29405
309	309	<backdrop name="sreel1" element="SteppersReel1" state="0">
310	310	<bounds x="85" y="463" width="49" height="87.9999"/>
311	311	</backdrop>
312
	312
313	313	<backdrop name="blk" element="bezelblock" state="0">
314	314	<bounds x="85" y="463" width="49" height="29.3333"/>
315	315	</backdrop>

trunk/src/mame/layout/cherryb3.lay
r29404	r29405
1	1	<?xml version="1.0"?>
2	2	<mamelayout version="2">
3	3	<!--
4		Cherry Bonus III control panel
5		Written by Roberto Fresca.
	4	Cherry Bonus III control panel
	5	Written by Roberto Fresca.
6	6	-->
7	7
8	8	<!-- define button-lamps -->

trunk/src/mame/layout/dblcrown.lay
r29404	r29405
1	1	<?xml version="1.0"?>
2	2	<mamelayout version="2">
3	3	<!--
4		Double Crown control panel
5		Written by Roberto Fresca.
	4	Double Crown control panel
	5	Written by Roberto Fresca.
6	6	-->
7	7
8	8	<!-- define button-lamps -->

trunk/src/mame/layout/goldstar.lay
r29404	r29405
1	1	<?xml version="1.0"?>
2	2	<mamelayout version="2">
3	3	<!--
4		Golden Star control panel.
5		Written by Roberto Fresca.
	4	Golden Star control panel.
	5	Written by Roberto Fresca.
6	6	-->
7	7
8	8	<!-- define button-lamps -->

trunk/src/mame/drivers/mhavoc.c
r29404	r29405
516	516	MCFG_SCREEN_SIZE(400, 300)
517	517	MCFG_SCREEN_VISIBLE_AREA(0, 300, 0, 260)
518	518	MCFG_SCREEN_UPDATE_DEVICE("vector", vector_device, screen_update)
519
	519
520	520	MCFG_DEVICE_ADD("avg", AVG_MHAVOC, 0)
521	521	MCFG_AVGDVG_VECTOR("vector")
522	522

trunk/src/mame/drivers/simpl156.c
r29404	r29405
441	441	MCFG_DECO16IC_ADD("tilegen1", simpl156_deco16ic_tilegen1_intf)
442	442	MCFG_DECO16IC_GFXDECODE("gfxdecode")
443	443	MCFG_DECO16IC_PALETTE("palette")
444
	444
445	445	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
446	446	decospr_device::set_gfx_region(*device, 2);
447	447	decospr_device::set_pri_callback(*device, simpl156_pri_callback);

trunk/src/mame/drivers/cliffhgr.c
r29404	r29405
120	120	TIMER_CALLBACK_MEMBER(cliff_irq_callback);
121	121	required_device<cpu_device> m_maincpu;
122	122	required_device<discrete_device> m_discrete;
123		required_device<screen_device> m_screen;
	123	required_device<screen_device> m_screen;
124	124	};
125	125
126	126

trunk/src/mame/drivers/multfish.c
r29404	r29405
3	3	to make it clearer why all the sets with hacked bank
4	4	setup existed in the wild
5	5
6		note:
7		this file contains the originals only
8		for bootlegs see multfish_boot.c
9		for reference information about undumped sets see multfish_Ref.c - if adding a new set ALWAYS check that, anything not listed in there is
10		almost certainly a bootleg.
	6	note:
	7	this file contains the originals only
	8	for bootlegs see multfish_boot.c
	9	for reference information about undumped sets see multfish_Ref.c - if adding a new set ALWAYS check that, anything not listed in there is
	10	almost certainly a bootleg.
11	11
12	12	*/
13	13
r29404	r29405
1058	1058	MCFG_SCREEN_VISIBLE_AREA(1716, 1024-167-1, 116, 3216-1*16-1)
1059	1059	MCFG_SCREEN_UPDATE_DRIVER(igrosoft_gamble_state, screen_update_igrosoft_gamble)
1060	1060	MCFG_SCREEN_PALETTE("palette")
1061
	1061
1062	1062	MCFG_GFXDECODE_ADD("gfxdecode", "palette", igrosoft_gamble)
1063	1063	MCFG_PALETTE_ADD("palette", 0x1000)
1064	1064
r29404	r29405
2807	2807	GAME( 2010, crzmon2, 0, igrosoft_gamble, igrosoft_gamble, igrosoft_gamble_state,crzmon2, ROT0, "Igrosoft", "Crazy Monkey 2 (100310)", GAME_NOT_WORKING\|GAME_SUPPORTS_SAVE ) /* World */ // xored and bitswapped palette and gfx roms
2808	2808	GAME( 2010, crzmon2_2, crzmon2_parent, igrosoft_gamble, igrosoft_gamble, igrosoft_gamble_state,crzmon2lot,ROT0, "Igrosoft", "Crazy Monkey 2 (100311 Lottery)", GAME_NOT_WORKING\|GAME_SUPPORTS_SAVE ) /* Lottery */
2809	2809	GAME( 2010, crzmon2_3, crzmon2_parent, igrosoft_gamble, igrosoft_gamble, igrosoft_gamble_state,crzmon2ent,ROT0, "Igrosoft", "Crazy Monkey 2 (100315 Entertainment)", GAME_NOT_WORKING\|GAME_SUPPORTS_SAVE ) /* Entertainment */
2810
2811

trunk/src/mame/drivers/battlnts.c
r29404	r29405
253	253	MCFG_K007342_GFXNUM(0)
254	254	MCFG_K007342_CALLBACK_OWNER(battlnts_state, battlnts_tile_callback)
255	255	MCFG_K007342_GFXDECODE("gfxdecode")
256
	256
257	257	MCFG_K007420_ADD("k007420")
258	258	MCFG_K007420_BANK_LIMIT(0x3ff)
259	259	MCFG_K007420_CALLBACK_OWNER(battlnts_state, battlnts_sprite_callback)

trunk/src/mame/drivers/galpani2.c
r29404	r29405
966	966
967	967	ROM_START( galpani2e2 )
968	968	ROM_REGION( 0x100000, "maincpu", 0 ) /* CPU#1 Code */
969		ROM_LOAD16_BYTE( "g000i1-u133-0.u133", 0x000000, 0x080000, CRC(7df7b759) SHA1(2479a6389649ee6042b175b71d7ed54bc116add5) ) //english version specific
970		ROM_LOAD16_BYTE( "g001i1-u134-0.u134", 0x000001, 0x080000, CRC(c92937c3) SHA1(0c9e894c0e23e319bd2d01ec573f02ed510e3ed6) ) //same as german version
	969	ROM_LOAD16_BYTE( "g000i1-u133-0.u133", 0x000000, 0x080000, CRC(7df7b759) SHA1(2479a6389649ee6042b175b71d7ed54bc116add5) ) //english version specific
	970	ROM_LOAD16_BYTE( "g001i1-u134-0.u134", 0x000001, 0x080000, CRC(c92937c3) SHA1(0c9e894c0e23e319bd2d01ec573f02ed510e3ed6) ) //same as german version
971	971
972	972	ROM_REGION( 0x40000, "sub", 0 ) /* CPU#2 Code */
973	973	ROM_LOAD16_BYTE( "g002i1.125", 0x000000, 0x020000, CRC(a3034e1c) SHA1(493e4be36f2aea0083d5d37e16486ed66dab952e) )

trunk/src/mame/drivers/bowltry.c
r29404	r29405
1	1	/************************************************************************************************************
2	2
3		Bowling Try
	3	Bowling Try
4	4
5		(c)200? Atlus
	5	(c)200? Atlus
6	6
7		TODO:
8		- Tight loops at 0x60e090-0x60e093, control status from video chip?
9		- YGV631-B ... what's that?
	7	TODO:
	8	- Tight loops at 0x60e090-0x60e093, control status from video chip?
	9	- YGV631-B ... what's that?
10	10
11		ATLUS PCB BT-208001
12		------------------------
	11	ATLUS PCB BT-208001
	12	------------------------
13	13
14		At U12 the chip is Toshiba TA8428FG
	14	At U12 the chip is Toshiba TA8428FG
15	15
16		At U1 the chip is H8/3008
	16	At U1 the chip is H8/3008
17	17
18		At X1 on the crystal it is printed S753
	18	At X1 on the crystal it is printed S753
19	19
20		big gfx chip marked
	20	big gfx chip marked
21	21
22		YAMAHA JAPAN
23		YGV631-B
24		0806LU004
	22	YAMAHA JAPAN
	23	YGV631-B
	24	0806LU004
25	25
26	26	************************************************************************************************************/
27	27
r29404	r29405
94	94	static MACHINE_CONFIG_START( bowltry, bowltry_state )
95	95	MCFG_CPU_ADD("maincpu", H83008, 16000000 )
96	96	MCFG_CPU_PROGRAM_MAP( bowltry_map )
97		// MCFG_CPU_VBLANK_INT_DRIVER("screen", bowltry_state, irq0_line_hold) // uses vector $64, IMIAB according to the manual (timer/compare B, internal to the CPU)
	97	// MCFG_CPU_VBLANK_INT_DRIVER("screen", bowltry_state, irq0_line_hold) // uses vector $64, IMIAB according to the manual (timer/compare B, internal to the CPU)
98	98
99	99	MCFG_SCREEN_ADD("screen", RASTER)
100	100	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mame/drivers/monacogp.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	Sega Monaco GP
4	4
5	5	1980
6	6
7
	7
8	8	Board 96598-P is an oscillator board that generates the game sounds. It is activated by outputs from Board Assy A (96577X).
9
	9
10	10	Board Assy's A (96577X) and B (96578X) are the main guts of the gameplay and contain the roms (all sprites).
11		Board Assy A accepts all of the game inputs (Coin, wheel, shift, accelerator pedal), sends the signals for the sounds to the Oscillator board, outputs to the L.E.D. score display board, and directly interacts with Board Assy B
	11	Board Assy A accepts all of the game inputs (Coin, wheel, shift, accelerator pedal), sends the signals for the sounds to the Oscillator board, outputs to the L.E.D. score display board, and directly interacts with Board Assy B
12	12	Board Assy B outputs the video, outputs to the L.E.D. score display board. and directly interacts with Board Assy A.
13
14		On the second set, boards A and B have different part numbers (97091X and 97092X) and two less roms. These boards were made later then the first set.
	13
	14	On the second set, boards A and B have different part numbers (97091X and 97092X) and two less roms. These boards were made later then the first set.
15	15	These boards seem to be interchangable, the only difference seems to be the rom size, which only 2 of the roms utilize the full 1024 bytes (second set).
16
17		ROM SET A <type 7461, 24 pin> ROM SET B <type MB7132E, 24 pin>
18		Board 96577X Board 97091X
19		ROM ID IC# ROM ID
20		PRa125 (Light data) IC59 PRb-01 (identical to PRa125)
21		PRa126 (Explosion) IC65 PRb-02 (identical to PRa126)
22		PRa131 (????) IC71 PRb-04 (identical to PRa131)
23		PRa127 (car(2)) IC77 PRb-13 (identical to PRa127)
24		PRa128 (car(2)rotated) IC84 PRb-03 (identical to PRa128)
25		PRa129 (car) IC91 -----
26		PRa130 (car(2) spinout) IC98 PRb-14 (contains PRa130 and half of PRa129)
27		PRa132 (car(2)(main)) IC111 PRb-15 (identical to PRa132)
28
29		PRm-39 IC105 PRm-39 <both type 6331-1, 16 pin>
30		PRm-38 IC115 PRm-38 <both type 6331-1, 16 pin>
31
32		Board 96578X Board 97092X
33		ROM ID IC# ROM ID
34		PRa140 (brdge-water) IC12 -----
35		PRa141 (brdge-pillar) IC17 PRb-16 (contains both PRa140 and PRa141)
36		PRa138 (firetruck) IC30 PRb-10 (identical to PRa138)
37		PRa139 (car+bridge symb)IC51 PRb-11 (identical to PRa139)
38		PRa133 (text(4) IC64 PRb-05 (identical to PRa133)
39		PRa136 (house) IC99 PRb-08 (identical to PRa136)
40		PRa135 (shrub) IC106 PRb-07 (identical to PRa135)
41		PRa134 (tree, grass) IC113 PRb-06 (identical to PRa134)
42		PRa137 (tunnel,oil slip)IC120 PRb-09 (identical to PRa137)
43
	16
	17	ROM SET A <type 7461, 24 pin> ROM SET B <type MB7132E, 24 pin>
	18	Board 96577X Board 97091X
	19	ROM ID IC# ROM ID
	20	PRa125 (Light data) IC59 PRb-01 (identical to PRa125)
	21	PRa126 (Explosion) IC65 PRb-02 (identical to PRa126)
	22	PRa131 (????) IC71 PRb-04 (identical to PRa131)
	23	PRa127 (car(2)) IC77 PRb-13 (identical to PRa127)
	24	PRa128 (car(2)rotated) IC84 PRb-03 (identical to PRa128)
	25	PRa129 (car) IC91 -----
	26	PRa130 (car(2) spinout) IC98 PRb-14 (contains PRa130 and half of PRa129)
	27	PRa132 (car(2)(main)) IC111 PRb-15 (identical to PRa132)
	28
	29	PRm-39 IC105 PRm-39 <both type 6331-1, 16 pin>
	30	PRm-38 IC115 PRm-38 <both type 6331-1, 16 pin>
	31
	32	Board 96578X Board 97092X
	33	ROM ID IC# ROM ID
	34	PRa140 (brdge-water) IC12 -----
	35	PRa141 (brdge-pillar) IC17 PRb-16 (contains both PRa140 and PRa141)
	36	PRa138 (firetruck) IC30 PRb-10 (identical to PRa138)
	37	PRa139 (car+bridge symb)IC51 PRb-11 (identical to PRa139)
	38	PRa133 (text(4) IC64 PRb-05 (identical to PRa133)
	39	PRa136 (house) IC99 PRb-08 (identical to PRa136)
	40	PRa135 (shrub) IC106 PRb-07 (identical to PRa135)
	41	PRa134 (tree, grass) IC113 PRb-06 (identical to PRa134)
	42	PRa137 (tunnel,oil slip)IC120 PRb-09 (identical to PRa137)
	43
44	44	Oscillator Board 96598
45		ROM ID IC#
46		PRm-40 IC21 PRm-40 <both type 6331-1, 16 pin>
47
	45	ROM ID IC#
	46	PRm-40 IC21 PRm-40 <both type 6331-1, 16 pin>
	47
48	48	--------------------------------------------------------
49
	49
50	50	7641
51
	51
52	52	512*8
53	53	+------+
54	54	A7 \|1 24\| Vcc
r29404	r29405
63	63	D1 \|10 15\| D5
64	64	D2 \|11 14\| D4
65	65	GND\|12 13\| D3
66		+------+
	66	+------+
67	67	-----------------------------------------------
68
	68
69	69	6331-1 PROM
70
71		32*8
72		+------+
	70
	71	32*8
	72	+------+
73	73	O1 \|1 16\| Vcc
74	74	O2 \|2 15\| CE/
75	75	O3 \|3 14\| A4
r29404	r29405
78	78	O6 \|6 11\| A1
79	79	O7 \|7 10\| A0
80	80	GND \|8 9\| O8
81		+------+
82
	81	+------+
	82
83	83	-----------------------------------------------
84
	84
85	85	7132:
86
87		1024*8
88		+------+
	86
	87	1024*8
	88	+------+
89	89	A7 \|1 24\| Vcc
90	90	A6 \|2 23\| A8
91	91	A5 \|3 22\| A9
r29404	r29405
98	98	D1 \|10 15\| D5
99	99	D2 \|11 14\| D4
100	100	GND\|12 13\| D3
101		+------+
102
103
	101	+------+
	102
	103
104	104	***************************************************************************/
105	105
106	106
r29404	r29405
140	140	public:
141	141	monacogp_state(const machine_config &mconfig, device_type type, const char *tag)
142	142	: driver_device(mconfig, type, tag),
143		m_maincpu(*this, "maincpu"),
144		m_video(*this, "fixfreq")
	143	m_maincpu(*this, "maincpu"),
	144	m_video(*this, "fixfreq")
145	145	{
146	146	}
147
	147
148	148	// devices
149	149	required_device<netlist_mame_device_t> m_maincpu;
150	150	required_device<fixedfreq_device> m_video;
151
	151
152	152	protected:
153
	153
154	154	// driver_device overrides
155	155	virtual void machine_start();
156	156	virtual void machine_reset();
157
	157
158	158	virtual void video_start();
159
	159
160	160	private:
161
	161
162	162	};
163	163
164	164
165	165	static NETLIST_START(monacogp)
166	166	SOLVER(Solver, 48000)
167		// PARAM(Solver.FREQ, 48000)
	167	// PARAM(Solver.FREQ, 48000)
168	168	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
169	169
170	170	// schematics
171	171	//...
172	172
173		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
174		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	173	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	174	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
175	175	NETLIST_END()
176	176
177	177
r29404	r29405
201	201
202	202
203	203	/***************************************************************************
204
	204
205	205	Game driver(s)
206
	206
207	207	***************************************************************************/
208	208
209	209

trunk/src/mame/drivers/seta2.c
r29404	r29405
518	518	devcb = &funcube_touchscreen_device::set_tx_cb(*device, DEVCB2_##_devcb);
519	519
520	520	class funcube_touchscreen_device : public device_t,
521		public device_serial_interface
	521	public device_serial_interface
522	522	{
523	523	public:
524	524	funcube_touchscreen_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
r29404	r29405
539	539	required_ioport m_x;
540	540	required_ioport m_y;
541	541	required_ioport m_btn;
542
	542
543	543	UINT8 m_button_state;
544	544	int m_serial_pos;
545	545	UINT8 m_serial[4];

trunk/src/mame/drivers/flkatck.c
r29404	r29405
289	289	ROM_LOAD( "669_m02.16b", 0x000000, 0x008000, CRC(7e11e6b9) SHA1(7a7d65a458b15842a6345388007c8f682aec20a7) )
290	290
291	291	ROM_REGION( 0x080000, "gfx1", 0 ) /* tiles + sprites */ // same data as above set, on PWB 450593 sub-board instead.
292		ROM_LOAD16_BYTE( "669_f03a.4b", 0x000001, 0x010000, CRC(f0ed4c1e) SHA1(58efe3cd81054d22de54a7d195aa3b865bde4a01) )
293		ROM_LOAD16_BYTE( "669_f03e.4d", 0x000000, 0x010000, CRC(95a57a26) SHA1(c8aa30c2c734c0740630b1b04ae43c69931cc7c1) )
294		ROM_LOAD16_BYTE( "669_f03b.5b", 0x020001, 0x010000, CRC(e2593f3c) SHA1(aa0f6d04015650eaef17c4a39f228eaccf9a2948) )
295		ROM_LOAD16_BYTE( "669_f03f.5d", 0x020000, 0x010000, CRC(c6c9903e) SHA1(432ad6d03992499cc533273226944a666b40fa58) )
296		ROM_LOAD16_BYTE( "669_f03c.6b", 0x040001, 0x010000, CRC(47be92dd) SHA1(9ccc62d7d42fccbd5ad60e35e3a0478a04405cf1) )
297		ROM_LOAD16_BYTE( "669_f03g.6d", 0x040000, 0x010000, CRC(70d35fbd) SHA1(21384f738684c5da4a7a84a1c9aa173fffddf47a) )
298		ROM_LOAD16_BYTE( "669_f03d.7b", 0x060001, 0x010000, CRC(18d48f9e) SHA1(b95e38aa813e0f3a0dc6bd45fdb4bf71f7e2066c) )
299		ROM_LOAD16_BYTE( "669_f03h.7d", 0x060000, 0x010000, CRC(abfe76e7) SHA1(f8661f189308e83056ec442fa6c936efff67ba0a) )
	292	ROM_LOAD16_BYTE( "669_f03a.4b", 0x000001, 0x010000, CRC(f0ed4c1e) SHA1(58efe3cd81054d22de54a7d195aa3b865bde4a01) )
	293	ROM_LOAD16_BYTE( "669_f03e.4d", 0x000000, 0x010000, CRC(95a57a26) SHA1(c8aa30c2c734c0740630b1b04ae43c69931cc7c1) )
	294	ROM_LOAD16_BYTE( "669_f03b.5b", 0x020001, 0x010000, CRC(e2593f3c) SHA1(aa0f6d04015650eaef17c4a39f228eaccf9a2948) )
	295	ROM_LOAD16_BYTE( "669_f03f.5d", 0x020000, 0x010000, CRC(c6c9903e) SHA1(432ad6d03992499cc533273226944a666b40fa58) )
	296	ROM_LOAD16_BYTE( "669_f03c.6b", 0x040001, 0x010000, CRC(47be92dd) SHA1(9ccc62d7d42fccbd5ad60e35e3a0478a04405cf1) )
	297	ROM_LOAD16_BYTE( "669_f03g.6d", 0x040000, 0x010000, CRC(70d35fbd) SHA1(21384f738684c5da4a7a84a1c9aa173fffddf47a) )
	298	ROM_LOAD16_BYTE( "669_f03d.7b", 0x060001, 0x010000, CRC(18d48f9e) SHA1(b95e38aa813e0f3a0dc6bd45fdb4bf71f7e2066c) )
	299	ROM_LOAD16_BYTE( "669_f03h.7d", 0x060000, 0x010000, CRC(abfe76e7) SHA1(f8661f189308e83056ec442fa6c936efff67ba0a) )
300	300
301	301	ROM_REGION( 0x040000, "k007232", 0 ) /* 007232 data (chip 1) */
302	302	ROM_LOAD( "mask2m.11a", 0x000000, 0x040000, CRC(6d1ea61c) SHA1(9e6eb9ac61838df6e1f74e74bb72f3edf1274aed) )

trunk/src/mame/drivers/sigmab98.c
r29404	r29405
116	116	required_device<gfxdecode_device> m_gfxdecode;
117	117	dynamic_array<UINT8> m_paletteram;
118	118	required_device<screen_device> m_screen;
119		required_device<palette_device> m_palette;
	119	required_device<palette_device> m_palette;
120	120
121	121	UINT8 m_reg;
122	122	UINT8 m_rombank;
r29404	r29405
2150	2150
2151	2151	// RAM banks
2152	2152	m_paletteram.resize_and_clear(0x3000);
2153		m_palette->basemem().set(m_paletteram, ENDIANNESS_BIG, 2);
	2153	m_palette->basemem().set(m_paletteram, ENDIANNESS_BIG, 2);
2154	2154	membank("palbank")->set_base(m_paletteram);
2155	2155	m_rambank = 0x64;
2156	2156

trunk/src/mame/drivers/pong.c
r29404	r29405
67	67	};
68	68
69	69	fixedfreq_interface fixedfreq_mode_pong = {
70		MASTER_CLOCK,
71		H_TOTAL-67,H_TOTAL-40,H_TOTAL-8,H_TOTAL,
72		V_TOTAL-22,V_TOTAL-19,V_TOTAL-12,V_TOTAL,
73		1, /* non-interlaced */
74		0.31
	70	MASTER_CLOCK,
	71	H_TOTAL-67,H_TOTAL-40,H_TOTAL-8,H_TOTAL,
	72	V_TOTAL-22,V_TOTAL-19,V_TOTAL-12,V_TOTAL,
	73	1, /* non-interlaced */
	74	0.31
75	75	};
76	76
77	77	fixedfreq_interface fixedfreq_mode_pongX2 = {
r29404	r29405
102	102
103	103
104	104	static NETLIST_START(pong_schematics)
105		SOLVER(Solver, 48000)
106		PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
	105	SOLVER(Solver, 48000)
	106	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
107	107
108		ANALOG_INPUT(V5, 5)
	108	ANALOG_INPUT(V5, 5)
109	109
110	110	TTL_INPUT(high, 1)
111	111	TTL_INPUT(low, 0)
r29404	r29405
128	128	PARAM(xclk.FREQ, 7159000.0*2)
129	129	#endif
130	130
131		/* 3V Logic - Just a resistor - the value is not given in schematics */
	131	/* 3V Logic - Just a resistor - the value is not given in schematics */
132	132
133		RES(R3V, 50) // Works ...
134		NET_C(R3V.1, V5)
135		ALIAS(V3, R3V.2)
	133	RES(R3V, 50) // Works ...
	134	NET_C(R3V.1, V5)
	135	ALIAS(V3, R3V.2)
136	136
137		/* Coin, antenna and startup circuit */
	137	/* Coin, antenna and startup circuit */
138	138
139		ANALOG_INPUT(STOPG, 0)
140
141		ALIAS(SRSTQ, c9f.Q)
142		ALIAS(SRST, c9c.Q)
	139	ANALOG_INPUT(STOPG, 0)
143	140
144		/* SRSTQ has a diode to +3V to protect against overvoltage - omitted */
	141	ALIAS(SRSTQ, c9f.Q)
	142	ALIAS(SRST, c9c.Q)
145	143
146		~~TTL_INPUT(~~antenna, 0)
	144	/* SRSTQ has a diode to +3V to protect against overvoltage - omitted */
147	145
148		ALIAS(runQ, ~~Q1.C~~)
	146	TTL_INPUT(antenna, 0)
149	147
150		TTL~~_7404_~~I~~NVERT~~(~~e4d~~, ~~STOPG~~)
	148	ALIAS(runQ, Q1.C)
151	149
152		TTL_7404_INVERT(c9f, c9c.Q)
153		TTL_7404_INVERT(c9c, c9f.Q)
	150	TTL_7404_INVERT(e4d, STOPG)
154	151
155		SWITCH2(coinsw)
156		NET_C(c9c.Q, coinsw.1)
157		NET_C(c9f.Q, coinsw.2)
	152	TTL_7404_INVERT(c9f, c9c.Q)
	153	TTL_7404_INVERT(c9c, c9f.Q)
158	154
159		NET_C(coinsw.Q, GND)
	155	SWITCH2(coinsw)
	156	NET_C(c9c.Q, coinsw.1)
	157	NET_C(c9f.Q, coinsw.2)
160	158
161		/* Antenna circuit */
162		/* Has a diode to clamp negative voltages - omitted here */
	159	NET_C(coinsw.Q, GND)
163	160
164		QBJT_SW(Q3, "BC237B")
165		NET_C(antenna, Q3.B)
166		NET_C(GND, Q3.E)
167		RES(RX5, 100)
168		CAP(CX1, CAP_U(0.1))
	161	/* Antenna circuit */
	162	/* Has a diode to clamp negative voltages - omitted here */
169	163
170		NET_C(RX5.1, CX1.1)
171		NET_C(RX5.1, Q3.C)
172		NET_C(RX5.2, GND)
173		NET_C(CX1.2, GND)
174		QBJT_SW(Q1, "BC237B")
175		NET_C(Q1.B, RX5.1)
176		NET_C(Q1.E, GND)
	164	QBJT_SW(Q3, "BC237B")
	165	NET_C(antenna, Q3.B)
	166	NET_C(GND, Q3.E)
	167	RES(RX5, 100)
	168	CAP(CX1, CAP_U(0.1))
177	169
178		DIODE(D3, "1N914")
179		NET_C(D3.A, Q1.C)
180		NET_C(D3.K, SRSTQ)
	170	NET_C(RX5.1, CX1.1)
	171	NET_C(RX5.1, Q3.C)
	172	NET_C(RX5.2, GND)
	173	NET_C(CX1.2, GND)
	174	QBJT_SW(Q1, "BC237B")
	175	NET_C(Q1.B, RX5.1)
	176	NET_C(Q1.E, GND)
181	177
182		DIODE(D2, "1N914")
183		RES(RX4, 220)
184		NET_C(D2.K, e4d.Q)
185		NET_C(D2.A, RX4.1)
186		NET_C(RX4.2, Q3.C)
	178	DIODE(D3, "1N914")
	179	NET_C(D3.A, Q1.C)
	180	NET_C(D3.K, SRSTQ)
187	181
188		RES(RX1, 100)
189		RES(RX2, 100)
190		RES(RX3, 330)
191		CAP(CX2, CAP_U(0.1))
	182	DIODE(D2, "1N914")
	183	RES(RX4, 220)
	184	NET_C(D2.K, e4d.Q)
	185	NET_C(D2.A, RX4.1)
	186	NET_C(RX4.2, Q3.C)
192	187
193		NET_C(RX3.2, D3.A)
194		NET_C(RX3.1, RX1.2)
195		NET_C(RX1.1, V3)
	188	RES(RX1, 100)
	189	RES(RX2, 100)
	190	RES(RX3, 330)
	191	CAP(CX2, CAP_U(0.1))
196	192
197		NET_C(RX1.1, CX2.1)
198		NET_C(RX1.2, CX2.2)
	193	NET_C(RX3.2, D3.A)
	194	NET_C(RX3.1, RX1.2)
	195	NET_C(RX1.1, V3)
199	196
200		QBJT_SW(Q2, "BC556B")
201		NET_C(Q2.E, V3)
202		NET_C(Q2.B, RX1.2)
203		NET_C(Q2.C, RX2.2)
	197	NET_C(RX1.1, CX2.1)
	198	NET_C(RX1.2, CX2.2)
204	199
205		NET_C(RX2.1, D2.A)
	200	QBJT_SW(Q2, "BC556B")
	201	NET_C(Q2.E, V3)
	202	NET_C(Q2.B, RX1.2)
	203	NET_C(Q2.C, RX2.2)
206	204
207		~~/* hit logic */~~
	205	NET_C(RX2.1, D2.A)
208	206
209		TTL_7404_INVERT(hitQ, hit)
210		TTL_7400_NAND(hit, hit1Q, hit2Q)
	207	/* hit logic */
211	208
212		TTL_7402_NOR(attractQ, StopG, runQ)
213		TTL_7404_INVERT(attract, attractQ)
	209	TTL_7404_INVERT(hitQ, hit)
	210	TTL_7400_NAND(hit, hit1Q, hit2Q)
214	211
215		TTL_7420_NAND(ic_h6a, hvidQ, hvidQ, hvidQ, hvidQ)
216		ALIAS(hvid, ic_h6a.Q)
	212	TTL_7402_NOR(attractQ, StopG, runQ)
	213	TTL_7404_INVERT(attract, attractQ)
217	214
218		TTL_7400_NAND(ic_e6c, hvid, hblank)
219		ALIAS(MissQ, ic_e6c.Q)
	215	TTL_7420_NAND(ic_h6a, hvidQ, hvidQ, hvidQ, hvidQ)
	216	ALIAS(hvid, ic_h6a.Q)
220	217
221		TTL_7404_INVERT(ic_d1e, MissQ)
222		TTL_7400_NAND(ic_e1a, ic_d1e.Q, attractQ)
223		ALIAS(Missed, ic_e1a.Q)
	218	TTL_7400_NAND(ic_e6c, hvid, hblank)
	219	ALIAS(MissQ, ic_e6c.Q)
224	220
225		TTL_7400_NAND(rstspeed, SRSTQ, MissQ)
226		TTL_7400_NAND(StopG, StopG1Q, StopG2Q)
227		ALIAS(L, ic_h3b.Q)
228		ALIAS(R, ic_h3b.QQ)
	221	TTL_7404_INVERT(ic_d1e, MissQ)
	222	TTL_7400_NAND(ic_e1a, ic_d1e.Q, attractQ)
	223	ALIAS(Missed, ic_e1a.Q)
229	224
230		TTL_7400_NAND(hit1Q, pad1, ic_g1b.Q)
231		TTL_7400_NAND(hit2Q, pad2, ic_g1b.Q)
	225	TTL_7400_NAND(rstspeed, SRSTQ, MissQ)
	226	TTL_7400_NAND(StopG, StopG1Q, StopG2Q)
	227	ALIAS(L, ic_h3b.Q)
	228	ALIAS(R, ic_h3b.QQ)
232	229
233		TTL_7400_NAND(ic_g3c, 128H, ic_h3a.QQ)
234		TTL_7427_NOR(ic_g2c, ic_g3c.Q, 256H, vpad1Q)
235		ALIAS(pad1, ic_g2c.Q)
236		TTL_7427_NOR(ic_g2a, ic_g3c.Q, 256HQ, vpad2Q)
237		ALIAS(pad2, ic_g2a.Q)
	230	TTL_7400_NAND(hit1Q, pad1, ic_g1b.Q)
	231	TTL_7400_NAND(hit2Q, pad2, ic_g1b.Q)
238	232
239		// ----------------------------------------------------------------------------------------
240		// horizontal counter
241		// ----------------------------------------------------------------------------------------
242		TTL_7493(ic_f8, clk, ic_f8.QA, ic_e7b.QQ, ic_e7b.QQ) // f8, f9, f6b
243		TTL_7493(ic_f9, ic_f8.QD, ic_f9.QA, ic_e7b.QQ, ic_e7b.QQ) // f8, f9, f6b
244		TTL_74107(ic_f6b, ic_f9.QD, high, high, ic_e7b.Q)
245		TTL_7430_NAND(ic_f7, ic_f8.QB, ic_f8.QC, ic_f9.QC, ic_f9.QD, ic_f6b.Q, high, high, high)
246		TTL_7474(ic_e7b, clk, ic_f7, high, high)
	233	TTL_7400_NAND(ic_g3c, 128H, ic_h3a.QQ)
	234	TTL_7427_NOR(ic_g2c, ic_g3c.Q, 256H, vpad1Q)
	235	ALIAS(pad1, ic_g2c.Q)
	236	TTL_7427_NOR(ic_g2a, ic_g3c.Q, 256HQ, vpad2Q)
	237	ALIAS(pad2, ic_g2a.Q)
247	238
248		ALIAS(hreset, ic_e7b.QQ)
249		ALIAS(hresetQ, ic_e7b.Q)
250		ALIAS( 4H, ic_f8.QC)
251		ALIAS( 8H, ic_f8.QD)
252		ALIAS( 16H, ic_f9.QA)
253		ALIAS( 32H, ic_f9.QB)
254		ALIAS( 64H, ic_f9.QC)
255		ALIAS(128H, ic_f9.QD)
256		ALIAS(256H, ic_f6b.Q)
257		ALIAS(256HQ, ic_f6b.QQ)
	239	// ----------------------------------------------------------------------------------------
	240	// horizontal counter
	241	// ----------------------------------------------------------------------------------------
	242	TTL_7493(ic_f8, clk, ic_f8.QA, ic_e7b.QQ, ic_e7b.QQ) // f8, f9, f6b
	243	TTL_7493(ic_f9, ic_f8.QD, ic_f9.QA, ic_e7b.QQ, ic_e7b.QQ) // f8, f9, f6b
	244	TTL_74107(ic_f6b, ic_f9.QD, high, high, ic_e7b.Q)
	245	TTL_7430_NAND(ic_f7, ic_f8.QB, ic_f8.QC, ic_f9.QC, ic_f9.QD, ic_f6b.Q, high, high, high)
	246	TTL_7474(ic_e7b, clk, ic_f7, high, high)
258	247
259		// ----------------------------------------------------------------------------------------
260		// vertical counter
261		// ----------------------------------------------------------------------------------------
262		TTL_7493(ic_e8, hreset, ic_e8.QA, ic_e7a.QQ, ic_e7a.QQ) // e8, e9, d9b
263		TTL_7493(ic_e9, ic_e8.QD,ic_e9.QA, ic_e7a.QQ, ic_e7a.QQ) // e8, e9, d9b
264		TTL_74107(ic_d9b, ic_e9.QD, high, high, ic_e7a.Q)
265		TTL_7474(ic_e7a, hreset, e7a_data, high, high)
266		TTL_7410_NAND(e7a_data, ic_e8.QA, ic_e8.QC, ic_d9b.Q)
	248	ALIAS(hreset, ic_e7b.QQ)
	249	ALIAS(hresetQ, ic_e7b.Q)
	250	ALIAS( 4H, ic_f8.QC)
	251	ALIAS( 8H, ic_f8.QD)
	252	ALIAS( 16H, ic_f9.QA)
	253	ALIAS( 32H, ic_f9.QB)
	254	ALIAS( 64H, ic_f9.QC)
	255	ALIAS(128H, ic_f9.QD)
	256	ALIAS(256H, ic_f6b.Q)
	257	ALIAS(256HQ, ic_f6b.QQ)
267	258
268		ALIAS(vreset, ic_e7a.QQ)
269		ALIAS( 4V, ic_e8.QC)
270		ALIAS( 8V, ic_e8.QD)
271		ALIAS( 16V, ic_e9.QA)
272		ALIAS( 32V, ic_e9.QB)
273		ALIAS( 64V, ic_e9.QC)
274		ALIAS(128V, ic_e9.QD)
275		ALIAS(256V, ic_d9b.Q)
276		ALIAS(256VQ, ic_d9b.QQ)
	259	// ----------------------------------------------------------------------------------------
	260	// vertical counter
	261	// ----------------------------------------------------------------------------------------
	262	TTL_7493(ic_e8, hreset, ic_e8.QA, ic_e7a.QQ, ic_e7a.QQ) // e8, e9, d9b
	263	TTL_7493(ic_e9, ic_e8.QD,ic_e9.QA, ic_e7a.QQ, ic_e7a.QQ) // e8, e9, d9b
	264	TTL_74107(ic_d9b, ic_e9.QD, high, high, ic_e7a.Q)
	265	TTL_7474(ic_e7a, hreset, e7a_data, high, high)
	266	TTL_7410_NAND(e7a_data, ic_e8.QA, ic_e8.QC, ic_d9b.Q)
277	267
	268	ALIAS(vreset, ic_e7a.QQ)
	269	ALIAS( 4V, ic_e8.QC)
	270	ALIAS( 8V, ic_e8.QD)
	271	ALIAS( 16V, ic_e9.QA)
	272	ALIAS( 32V, ic_e9.QB)
	273	ALIAS( 64V, ic_e9.QC)
	274	ALIAS(128V, ic_e9.QD)
	275	ALIAS(256V, ic_d9b.Q)
	276	ALIAS(256VQ, ic_d9b.QQ)
278	277
279		// ----------------------------------------------------------------------------------------
280		// hblank flip flop
281		// ----------------------------------------------------------------------------------------
282	278
283		TTL_7400_NAND(ic_g5b, 16H, 64H)
	279	// ----------------------------------------------------------------------------------------
	280	// hblank flip flop
	281	// ----------------------------------------------------------------------------------------
284	282
285		// the time critical one
286		TTL_7400_NAND(ic_h5c, ic_h5b.Q, hresetQ)
287		TTL_7400_NAND(ic_h5b, ic_h5c.Q, ic_g5b.Q)
	283	TTL_7400_NAND(ic_g5b, 16H, 64H)
288	284
289		ALIAS(hblank, ic_h5c.Q)
290		ALIAS(hblankQ, ic_h5b.Q)
291		TTL_7400_NAND(hsyncQ, hblank, 32H)
	285	// the time critical one
	286	TTL_7400_NAND(ic_h5c, ic_h5b.Q, hresetQ)
	287	TTL_7400_NAND(ic_h5b, ic_h5c.Q, ic_g5b.Q)
292	288
293		// ----------------------------------------------------------------------------------------
294		// vblank flip flop
295		// ----------------------------------------------------------------------------------------
296		TTL_7402_NOR(ic_f5c, ic_f5d.Q, vreset)
297		TTL_7402_NOR(ic_f5d, ic_f5c.Q, 16V)
	289	ALIAS(hblank, ic_h5c.Q)
	290	ALIAS(hblankQ, ic_h5b.Q)
	291	TTL_7400_NAND(hsyncQ, hblank, 32H)
298	292
299		ALIAS(vblank, ic_f5d.Q)
300		ALIAS(vblankQ, ic_f5c.Q)
	293	// ----------------------------------------------------------------------------------------
	294	// vblank flip flop
	295	// ----------------------------------------------------------------------------------------
	296	TTL_7402_NOR(ic_f5c, ic_f5d.Q, vreset)
	297	TTL_7402_NOR(ic_f5d, ic_f5c.Q, 16V)
301	298
302		TTL_7400_NAND(ic_h5a, 8V, 8V)
303		TTL_7410_NAND(ic_g5a, vblank, 4V, ic_h5a.Q)
304		ALIAS(vsyncQ, ic_g5a.Q)
	299	ALIAS(vblank, ic_f5d.Q)
	300	ALIAS(vblankQ, ic_f5c.Q)
305	301
306		// ----------------------------------------------------------------------------------------
307		// move logic
308		// ----------------------------------------------------------------------------------------
	302	TTL_7400_NAND(ic_h5a, 8V, 8V)
	303	TTL_7410_NAND(ic_g5a, vblank, 4V, ic_h5a.Q)
	304	ALIAS(vsyncQ, ic_g5a.Q)
309	305
310		TTL_7400_NAND(ic_e1d, hit_sound, ic_e1c.Q)
311		TTL_7400_NAND(ic_e1c, ic_f1.QC, ic_f1.QD)
312		TTL_7493(ic_f1, ic_e1d.Q, ic_f1.QA, rstspeed, rstspeed)
	306	// ----------------------------------------------------------------------------------------
	307	// move logic
	308	// ----------------------------------------------------------------------------------------
313	309
314		TTL_7402_NOR(ic_g1d, ic_f1.QC, ic_f1.QD)
315		TTL_7400_NAND(ic_h1a, ic_g1d.Q, ic_g1d.Q)
316		TTL_7400_NAND(ic_h1d, ic_e1c.Q, ic_h1a.Q)
	310	TTL_7400_NAND(ic_e1d, hit_sound, ic_e1c.Q)
	311	TTL_7400_NAND(ic_e1c, ic_f1.QC, ic_f1.QD)
	312	TTL_7493(ic_f1, ic_e1d.Q, ic_f1.QA, rstspeed, rstspeed)
317	313
318		TTL_7400_NAND(ic_h1c, ic_h1d.Q, vreset)
319		TTL_7400_NAND(ic_h1b, ic_h1a.Q, vreset)
320		TTL_7402_NOR(ic_g1c, 256HQ, vreset)
	314	TTL_7402_NOR(ic_g1d, ic_f1.QC, ic_f1.QD)
	315	TTL_7400_NAND(ic_h1a, ic_g1d.Q, ic_g1d.Q)
	316	TTL_7400_NAND(ic_h1d, ic_e1c.Q, ic_h1a.Q)
321	317
322		TTL_74107(ic_h2a, ic_g1c.Q, ic_h2b.Q, low, ic_h1b.Q)
323		TTL_74107(ic_h2b, ic_g1c.Q, high, move, ic_h1c.Q)
	318	TTL_7400_NAND(ic_h1c, ic_h1d.Q, vreset)
	319	TTL_7400_NAND(ic_h1b, ic_h1a.Q, vreset)
	320	TTL_7402_NOR(ic_g1c, 256HQ, vreset)
324	321
325		TTL_7400_NAND(ic_h4a, ic_h2b.Q, ic_h2a.Q)
326		ALIAS(move, ic_h4a.Q)
	322	TTL_74107(ic_h2a, ic_g1c.Q, ic_h2b.Q, low, ic_h1b.Q)
	323	TTL_74107(ic_h2b, ic_g1c.Q, high, move, ic_h1c.Q)
327	324
328		TTL_7400_NAND(ic_c1d, SC, attract)
329		TTL_7404_INVERT(ic_d1a, ic_c1d.Q)
330		TTL_7474(ic_h3b, ic_d1a.Q, ic_h3b.QQ, hit1Q, hit2Q)
	325	TTL_7400_NAND(ic_h4a, ic_h2b.Q, ic_h2a.Q)
	326	ALIAS(move, ic_h4a.Q)
331	327
332		TTL_7400_NAND(ic_h4d, ic_h3b.Q, move)
333		TTL_7400_NAND(ic_h4b, ic_h3b.QQ, move)
334		TTL_7400_NAND(ic_h4c, ic_h4d.Q, ic_h4b.Q)
335		ALIAS(Aa, ic_h4c.Q)
336		ALIAS(Ba, ic_h4b.Q)
	328	TTL_7400_NAND(ic_c1d, SC, attract)
	329	TTL_7404_INVERT(ic_d1a, ic_c1d.Q)
	330	TTL_7474(ic_h3b, ic_d1a.Q, ic_h3b.QQ, hit1Q, hit2Q)
337	331
338		// ----------------------------------------------------------------------------------------
339		// hvid circuit
340		// ----------------------------------------------------------------------------------------
	332	TTL_7400_NAND(ic_h4d, ic_h3b.Q, move)
	333	TTL_7400_NAND(ic_h4b, ic_h3b.QQ, move)
	334	TTL_7400_NAND(ic_h4c, ic_h4d.Q, ic_h4b.Q)
	335	ALIAS(Aa, ic_h4c.Q)
	336	ALIAS(Ba, ic_h4b.Q)
341	337
342		TTL_7400_NAND(hball_resetQ, Serve, attractQ)
	338	// ----------------------------------------------------------------------------------------
	339	// hvid circuit
	340	// ----------------------------------------------------------------------------------------
343	341
344		TTL_9316(ic_g7, clk, high, hblankQ, hball_resetQ, ic_g5c.Q, Aa, Ba, low, high)
345		TTL_9316(ic_h7, clk, ic_g7.RC, high, hball_resetQ, ic_g5c.Q, low, low, low, high)
346		TTL_74107(ic_g6b, ic_h7.RC, high, high, hball_resetQ)
347		TTL_7410_NAND(ic_g5c, ic_g6b.Q, ic_h7.RC, ic_g7.RC)
348		TTL_7420_NAND(ic_h6b, ic_g6b.Q, ic_h7.RC, ic_g7.QC, ic_g7.QD)
349		ALIAS(hvidQ, ic_h6b.Q)
	342	TTL_7400_NAND(hball_resetQ, Serve, attractQ)
350	343
351		// ----------------------------------------------------------------------------------------
352		// vvid circuit
353		// ----------------------------------------------------------------------------------------
	344	TTL_9316(ic_g7, clk, high, hblankQ, hball_resetQ, ic_g5c.Q, Aa, Ba, low, high)
	345	TTL_9316(ic_h7, clk, ic_g7.RC, high, hball_resetQ, ic_g5c.Q, low, low, low, high)
	346	TTL_74107(ic_g6b, ic_h7.RC, high, high, hball_resetQ)
	347	TTL_7410_NAND(ic_g5c, ic_g6b.Q, ic_h7.RC, ic_g7.RC)
	348	TTL_7420_NAND(ic_h6b, ic_g6b.Q, ic_h7.RC, ic_g7.QC, ic_g7.QD)
	349	ALIAS(hvidQ, ic_h6b.Q)
354	350
355		TTL_9316(ic_b3, hsyncQ, high, vblankQ, high, ic_b2b.Q, a6, b6, c6, d6)
356		TTL_9316(ic_a3, hsyncQ, ic_b3.RC, high, high, ic_b2b.Q, low, low, low, low)
357		TTL_7400_NAND(ic_b2b, ic_a3.RC, ic_b3.RC)
358		TTL_7410_NAND(ic_e2b, ic_a3.RC, ic_b3.QC, ic_b3.QD)
359		ALIAS(vvidQ, ic_e2b.Q)
360		TTL_7404_INVERT(vvid, vvidQ) // D2D
361		ALIAS(vpos256, ic_a3.RC)
362		ALIAS(vpos32, ic_a3.QB)
363		ALIAS(vpos16, ic_a3.QA)
	351	// ----------------------------------------------------------------------------------------
	352	// vvid circuit
	353	// ----------------------------------------------------------------------------------------
364	354
365		// ----------------------------------------------------------------------------------------
366		// vball ctrl circuit
367		// ----------------------------------------------------------------------------------------
	355	TTL_9316(ic_b3, hsyncQ, high, vblankQ, high, ic_b2b.Q, a6, b6, c6, d6)
	356	TTL_9316(ic_a3, hsyncQ, ic_b3.RC, high, high, ic_b2b.Q, low, low, low, low)
	357	TTL_7400_NAND(ic_b2b, ic_a3.RC, ic_b3.RC)
	358	TTL_7410_NAND(ic_e2b, ic_a3.RC, ic_b3.QC, ic_b3.QD)
	359	ALIAS(vvidQ, ic_e2b.Q)
	360	TTL_7404_INVERT(vvid, vvidQ) // D2D
	361	ALIAS(vpos256, ic_a3.RC)
	362	ALIAS(vpos32, ic_a3.QB)
	363	ALIAS(vpos16, ic_a3.QA)
368	364
369		TTL_7450_ANDORINVERT(ic_a6a, b1, 256HQ, b2, 256H)
370		TTL_7450_ANDORINVERT(ic_a6b, c1, 256HQ, c2, 256H)
371		TTL_7450_ANDORINVERT(ic_b6b, d1, 256HQ, d2, 256H)
	365	// ----------------------------------------------------------------------------------------
	366	// vball ctrl circuit
	367	// ----------------------------------------------------------------------------------------
372	368
373		TTL_7474(ic_a5b, hit, ic_a6a, attractQ, high)
374		TTL_7474(ic_a5a, hit, ic_a6b, attractQ, high)
375		TTL_7474(ic_b5a, hit, ic_b6b, attractQ, high)
376		TTL_74107(ic_h2x, vblank, vvid, vvid, hitQ) // two marked at position h2a ==> this h2x
	369	TTL_7450_ANDORINVERT(ic_a6a, b1, 256HQ, b2, 256H)
	370	TTL_7450_ANDORINVERT(ic_a6b, c1, 256HQ, c2, 256H)
	371	TTL_7450_ANDORINVERT(ic_b6b, d1, 256HQ, d2, 256H)
377	372
378		TTL_7486_XOR(ic_a4c, ic_a5b.Q, ic_h2x.Q)
379		TTL_7486_XOR(ic_a4b, ic_a5a.Q, ic_h2x.Q)
	373	TTL_7474(ic_a5b, hit, ic_a6a, attractQ, high)
	374	TTL_7474(ic_a5a, hit, ic_a6b, attractQ, high)
	375	TTL_7474(ic_b5a, hit, ic_b6b, attractQ, high)
	376	TTL_74107(ic_h2x, vblank, vvid, vvid, hitQ) // two marked at position h2a ==> this h2x
380	377
381		TTL_7450_ANDORINVERT(ic_b6a, ic_b5a.Q, ic_h2x.Q, ic_b5a.QQ, ic_h2x.QQ)
	378	TTL_7486_XOR(ic_a4c, ic_a5b.Q, ic_h2x.Q)
	379	TTL_7486_XOR(ic_a4b, ic_a5a.Q, ic_h2x.Q)
382	380
383		TTL_7404_INVERT(ic_c4a, ic_b6a)
	381	TTL_7450_ANDORINVERT(ic_b6a, ic_b5a.Q, ic_h2x.Q, ic_b5a.QQ, ic_h2x.QQ)
384	382
385		TTL_7483(ic_b4, ic_a4c, ic_a4b, ic_b6a, low, ic_c4a, high, high, low, low)
386		ALIAS(a6, ic_b4.S1)
387		ALIAS(b6, ic_b4.S2)
388		ALIAS(c6, ic_b4.S3)
389		ALIAS(d6, ic_b4.S4)
	383	TTL_7404_INVERT(ic_c4a, ic_b6a)
390	384
391		// ----------------------------------------------------------------------------------------
392		// serve monoflop
393		// ----------------------------------------------------------------------------------------
	385	TTL_7483(ic_b4, ic_a4c, ic_a4b, ic_b6a, low, ic_c4a, high, high, low, low)
	386	ALIAS(a6, ic_b4.S1)
	387	ALIAS(b6, ic_b4.S2)
	388	ALIAS(c6, ic_b4.S3)
	389	ALIAS(d6, ic_b4.S4)
394	390
395		TTL_7404_INVERT(f4_trig, rstspeed)
	391	// ----------------------------------------------------------------------------------------
	392	// serve monoflop
	393	// ----------------------------------------------------------------------------------------
396	394
397		RES(ic_f4_serve_R, RES_K(330))
398		CAP(ic_f4_serve_C, CAP_U(4.7))
399		NE555(ic_f4_serve)
	395	TTL_7404_INVERT(f4_trig, rstspeed)
400	396
401		NET_C(ic_f4_serve.VCC, V5)
402		NET_C(ic_f4_serve.GND, GND)
403		NET_C(ic_f4_serve.RESET, V5)
404		NET_C(ic_f4_serve_R.1, V5)
405		NET_C(ic_f4_serve_R.2, ic_f4_serve.THRESH)
406		NET_C(ic_f4_serve_R.2, ic_f4_serve.DISCH)
407		NET_C(f4_trig, ic_f4_serve.TRIG)
408		NET_C(ic_f4_serve_R.2, ic_f4_serve_C.1)
409		NET_C(GND, ic_f4_serve_C.2)
	397	RES(ic_f4_serve_R, RES_K(330))
	398	CAP(ic_f4_serve_C, CAP_U(4.7))
	399	NE555(ic_f4_serve)
410	400
411		TTL_7427_NOR(ic_e5a, ic_f4_serve.OUT, StopG, runQ)
412		TTL_7474(ic_b5b_serve, pad1, ic_e5a, ic_e5a, high)
	401	NET_C(ic_f4_serve.VCC, V5)
	402	NET_C(ic_f4_serve.GND, GND)
	403	NET_C(ic_f4_serve.RESET, V5)
	404	NET_C(ic_f4_serve_R.1, V5)
	405	NET_C(ic_f4_serve_R.2, ic_f4_serve.THRESH)
	406	NET_C(ic_f4_serve_R.2, ic_f4_serve.DISCH)
	407	NET_C(f4_trig, ic_f4_serve.TRIG)
	408	NET_C(ic_f4_serve_R.2, ic_f4_serve_C.1)
	409	NET_C(GND, ic_f4_serve_C.2)
413	410
414		ALIAS(Serve, ic_b5b_serve.QQ)
415		ALIAS(ServeQ, ic_b5b_serve.Q)
	411	TTL_7427_NOR(ic_e5a, ic_f4_serve.OUT, StopG, runQ)
	412	TTL_7474(ic_b5b_serve, pad1, ic_e5a, ic_e5a, high)
416	413
417		// ----------------------------------------------------------------------------------------
418		// score logic
419		// ----------------------------------------------------------------------------------------
	414	ALIAS(Serve, ic_b5b_serve.QQ)
	415	ALIAS(ServeQ, ic_b5b_serve.Q)
420	416
421		TTL_7474(ic_h3a, 4H, 128H, high, attractQ)
	417	// ----------------------------------------------------------------------------------------
	418	// score logic
	419	// ----------------------------------------------------------------------------------------
422	420
423		// ----------------------------------------------------------------------------------------
424		// sound logic
425		// ----------------------------------------------------------------------------------------
426		TTL_7474(ic_c2a, vpos256, high, hitQ, high)
427		TTL_74107(ic_f3_topbot, vblank, vvid, vvidQ, ServeQ)
	421	TTL_7474(ic_h3a, 4H, 128H, high, attractQ)
428	422
429		// ----------------------------------------------------------------------------------------
430		// monoflop with NE555 determines duration of score sound
431		// ----------------------------------------------------------------------------------------
	423	// ----------------------------------------------------------------------------------------
	424	// sound logic
	425	// ----------------------------------------------------------------------------------------
	426	TTL_7474(ic_c2a, vpos256, high, hitQ, high)
	427	TTL_74107(ic_f3_topbot, vblank, vvid, vvidQ, ServeQ)
432	428
433		RES(ic_g4_R, RES_K(220))
434		CAP(ic_g4_C, CAP_U(1))
435		NE555(ic_g4_sc)
436		ALIAS(SC, ic_g4_sc.OUT)
	429	// ----------------------------------------------------------------------------------------
	430	// monoflop with NE555 determines duration of score sound
	431	// ----------------------------------------------------------------------------------------
437	432
438		NET_C(ic_g4_sc.VCC, V5)
439		NET_C(ic_g4_sc.GND, GND)
440		NET_C(ic_g4_sc.RESET, V5)
441		NET_C(ic_g4_R.1, V5)
442		NET_C(ic_g4_R.2, ic_g4_sc.THRESH)
443		NET_C(ic_g4_R.2, ic_g4_sc.DISCH)
444		NET_C(MissQ, ic_g4_sc.TRIG)
445		NET_C(ic_g4_R.2, ic_g4_C.1)
446		NET_C(GND, ic_g4_C.2)
	433	RES(ic_g4_R, RES_K(220))
	434	CAP(ic_g4_C, CAP_U(1))
	435	NE555(ic_g4_sc)
	436	ALIAS(SC, ic_g4_sc.OUT)
447	437
448		ALIAS(hit_sound_en, ic_c2a.QQ)
449		TTL_7400_NAND(hit_sound, hit_sound_en, vpos16)
450		TTL_7400_NAND(score_sound, SC, vpos32)
451		TTL_7400_NAND(topbothitsound, ic_f3_topbot.Q, vpos32)
	438	NET_C(ic_g4_sc.VCC, V5)
	439	NET_C(ic_g4_sc.GND, GND)
	440	NET_C(ic_g4_sc.RESET, V5)
	441	NET_C(ic_g4_R.1, V5)
	442	NET_C(ic_g4_R.2, ic_g4_sc.THRESH)
	443	NET_C(ic_g4_R.2, ic_g4_sc.DISCH)
	444	NET_C(MissQ, ic_g4_sc.TRIG)
	445	NET_C(ic_g4_R.2, ic_g4_C.1)
	446	NET_C(GND, ic_g4_C.2)
452	447
453		TTL_7410_NAND(ic_c4b, topbothitsound, hit_sound, score_sound)
454		TTL_7400_NAND(ic_c1b, ic_c4b.Q, attractQ)
455		ALIAS(sound, ic_c1b.Q)
	448	ALIAS(hit_sound_en, ic_c2a.QQ)
	449	TTL_7400_NAND(hit_sound, hit_sound_en, vpos16)
	450	TTL_7400_NAND(score_sound, SC, vpos32)
	451	TTL_7400_NAND(topbothitsound, ic_f3_topbot.Q, vpos32)
456	452
	453	TTL_7410_NAND(ic_c4b, topbothitsound, hit_sound, score_sound)
	454	TTL_7400_NAND(ic_c1b, ic_c4b.Q, attractQ)
	455	ALIAS(sound, ic_c1b.Q)
457	456
458		// ----------------------------------------------------------------------------------------
459		// paddle1 logic 1
460		// ----------------------------------------------------------------------------------------
461	457
462		POT(ic_b9_POT, RES_K(1)) // This is a guess!!
463		PARAM(ic_b9_POT.DIALLOG, 1) // Log Dial ...
464		RES(ic_b9_RPRE, 470)
	458	// ----------------------------------------------------------------------------------------
	459	// paddle1 logic 1
	460	// ----------------------------------------------------------------------------------------
465	461
466		NET_C(ic_b9_POT.1, V5)
467		NET_C(ic_b9_POT.3, GND)
468		NET_C(ic_b9_POT.2, ic_b9_RPRE.1)
469		NET_C(ic_b9_RPRE.2, ic_b9.CONT)
	462	POT(ic_b9_POT, RES_K(1)) // This is a guess!!
	463	PARAM(ic_b9_POT.DIALLOG, 1) // Log Dial ...
	464	RES(ic_b9_RPRE, 470)
470	465
471		RES(ic_b9_R, RES_K(81)) // Adjustment pot
472		CAP(ic_b9_C, CAP_U(.1))
473		DIODE(ic_b9_D, "1N914")
474		NE555(ic_b9)
	466	NET_C(ic_b9_POT.1, V5)
	467	NET_C(ic_b9_POT.3, GND)
	468	NET_C(ic_b9_POT.2, ic_b9_RPRE.1)
	469	NET_C(ic_b9_RPRE.2, ic_b9.CONT)
475	470
476		NET_C(ic_b9.VCC, V5)
477		NET_C(ic_b9.GND, GND)
478		NET_C(ic_b9.RESET, V5)
479		NET_C(ic_b9_R.1, V5)
480		NET_C(ic_b9_R.2, ic_b9.THRESH)
481		NET_C(ic_b9_R.2, ic_b9_D.A)
482		NET_C(ic_b9_D.K, ic_b9.DISCH)
483		NET_C(256VQ, ic_b9.TRIG)
484		NET_C(ic_b9_R.2, ic_b9_C.1)
485		NET_C(GND, ic_b9_C.2)
	471	RES(ic_b9_R, RES_K(81)) // Adjustment pot
	472	CAP(ic_b9_C, CAP_U(.1))
	473	DIODE(ic_b9_D, "1N914")
	474	NE555(ic_b9)
486	475
487		TTL_7404_INVERT(ic_c9b, ic_b9.OUT)
488		TTL_7400_NAND(ic_b7b, ic_a7b.Q, hsyncQ)
489		TTL_7493(ic_b8, ic_b7b.Q, ic_b8.QA, ic_b9.OUT, ic_b9.OUT)
490		TTL_7400_NAND(ic_b7a, ic_c9b.Q, ic_a7b.Q)
491		TTL_7420_NAND(ic_a7b, ic_b8.QA, ic_b8.QB, ic_b8.QC, ic_b8.QD)
492		ALIAS(vpad1Q, ic_b7a.Q)
	476	NET_C(ic_b9.VCC, V5)
	477	NET_C(ic_b9.GND, GND)
	478	NET_C(ic_b9.RESET, V5)
	479	NET_C(ic_b9_R.1, V5)
	480	NET_C(ic_b9_R.2, ic_b9.THRESH)
	481	NET_C(ic_b9_R.2, ic_b9_D.A)
	482	NET_C(ic_b9_D.K, ic_b9.DISCH)
	483	NET_C(256VQ, ic_b9.TRIG)
	484	NET_C(ic_b9_R.2, ic_b9_C.1)
	485	NET_C(GND, ic_b9_C.2)
493	486
494		ALIAS(b1, ic_b8.QB)
495		ALIAS(c1, ic_b8.QC)
496		ALIAS(d1, ic_b8.QD)
	487	TTL_7404_INVERT(ic_c9b, ic_b9.OUT)
	488	TTL_7400_NAND(ic_b7b, ic_a7b.Q, hsyncQ)
	489	TTL_7493(ic_b8, ic_b7b.Q, ic_b8.QA, ic_b9.OUT, ic_b9.OUT)
	490	TTL_7400_NAND(ic_b7a, ic_c9b.Q, ic_a7b.Q)
	491	TTL_7420_NAND(ic_a7b, ic_b8.QA, ic_b8.QB, ic_b8.QC, ic_b8.QD)
	492	ALIAS(vpad1Q, ic_b7a.Q)
497	493
498		// ----------------------------------------------------------------------------------------
499		// paddle1 logic 2
500		// ----------------------------------------------------------------------------------------
	494	ALIAS(b1, ic_b8.QB)
	495	ALIAS(c1, ic_b8.QC)
	496	ALIAS(d1, ic_b8.QD)
501	497
502		POT(ic_a9_POT, RES_K(1)) // This is a guess!!
503		PARAM(ic_a9_POT.DIALLOG, 1) // Log Dial ...
504		RES(ic_a9_RPRE, 470)
	498	// ----------------------------------------------------------------------------------------
	499	// paddle1 logic 2
	500	// ----------------------------------------------------------------------------------------
505	501
506		NET_C(ic_a9_POT.1, V5)
507		NET_C(ic_a9_POT.3, GND)
508		NET_C(ic_a9_POT.2, ic_a9_RPRE.1)
509		NET_C(ic_a9_RPRE.2, ic_a9.CONT)
	502	POT(ic_a9_POT, RES_K(1)) // This is a guess!!
	503	PARAM(ic_a9_POT.DIALLOG, 1) // Log Dial ...
	504	RES(ic_a9_RPRE, 470)
510	505
511		RES(ic_a9_R, RES_K(81)) // Adjustment pot
512		CAP(ic_a9_C, CAP_U(.1))
513		DIODE(ic_a9_D, "1N914")
514		NE555(ic_a9)
	506	NET_C(ic_a9_POT.1, V5)
	507	NET_C(ic_a9_POT.3, GND)
	508	NET_C(ic_a9_POT.2, ic_a9_RPRE.1)
	509	NET_C(ic_a9_RPRE.2, ic_a9.CONT)
515	510
516		NET_C(ic_a9.VCC, V5)
517		NET_C(ic_a9.GND, GND)
518		NET_C(ic_a9.RESET, V5)
519		NET_C(ic_a9_R.1, V5)
520		NET_C(ic_a9_R.2, ic_a9.THRESH)
521		NET_C(ic_a9_R.2, ic_a9_D.A)
522		NET_C(ic_a9_D.K, ic_a9.DISCH)
523		NET_C(256VQ, ic_a9.TRIG)
524		NET_C(ic_a9_R.2, ic_a9_C.1)
525		NET_C(GND, ic_a9_C.2)
	511	RES(ic_a9_R, RES_K(81)) // Adjustment pot
	512	CAP(ic_a9_C, CAP_U(.1))
	513	DIODE(ic_a9_D, "1N914")
	514	NE555(ic_a9)
526	515
527		TTL_7404_INVERT(ic_c9a, ic_a9.OUT)
528		TTL_7400_NAND(ic_b7c, ic_a7a.Q, hsyncQ)
529		TTL_7493(ic_a8, ic_b7c.Q, ic_a8.QA, ic_a9.OUT, ic_a9.OUT)
530		TTL_7400_NAND(ic_b7d, ic_c9a.Q, ic_a7a.Q)
531		TTL_7420_NAND(ic_a7a, ic_a8.QA, ic_a8.QB, ic_a8.QC, ic_a8.QD)
532		ALIAS(vpad2Q, ic_b7d.Q)
	516	NET_C(ic_a9.VCC, V5)
	517	NET_C(ic_a9.GND, GND)
	518	NET_C(ic_a9.RESET, V5)
	519	NET_C(ic_a9_R.1, V5)
	520	NET_C(ic_a9_R.2, ic_a9.THRESH)
	521	NET_C(ic_a9_R.2, ic_a9_D.A)
	522	NET_C(ic_a9_D.K, ic_a9.DISCH)
	523	NET_C(256VQ, ic_a9.TRIG)
	524	NET_C(ic_a9_R.2, ic_a9_C.1)
	525	NET_C(GND, ic_a9_C.2)
533	526
534		ALIAS(b2, ic_a8.QB)
535		ALIAS(c2, ic_a8.QC)
536		ALIAS(d2, ic_a8.QD)
	527	TTL_7404_INVERT(ic_c9a, ic_a9.OUT)
	528	TTL_7400_NAND(ic_b7c, ic_a7a.Q, hsyncQ)
	529	TTL_7493(ic_a8, ic_b7c.Q, ic_a8.QA, ic_a9.OUT, ic_a9.OUT)
	530	TTL_7400_NAND(ic_b7d, ic_c9a.Q, ic_a7a.Q)
	531	TTL_7420_NAND(ic_a7a, ic_a8.QA, ic_a8.QB, ic_a8.QC, ic_a8.QD)
	532	ALIAS(vpad2Q, ic_b7d.Q)
537	533
538		// ----------------------------------------------------------------------------------------
539		// C5-EN Logic
540		// ----------------------------------------------------------------------------------------
	534	ALIAS(b2, ic_a8.QB)
	535	ALIAS(c2, ic_a8.QC)
	536	ALIAS(d2, ic_a8.QD)
541	537
542		TTL_7404_INVERT(ic_e3a, 128H)
543		TTL_7427_NOR( ic_e3b, 256H, 64H, ic_e3a.Q)
544		TTL_7410_NAND(ic_e2c, 256H, 64H, ic_e3a.Q)
545		TTL_7404_INVERT(ic_e3c, ic_e2c.Q)
546		TTL_7402_NOR(ic_d2c, ic_e3c.Q, ic_e3b.Q)
547		TTL_7404_INVERT(ic_g1a, 32V)
548		TTL_7425_NOR(ic_f2a, ic_g1a.Q, 64V, 128V, ic_d2c.Q)
549		ALIAS(c5_en, ic_f2a.Q)
	538	// ----------------------------------------------------------------------------------------
	539	// C5-EN Logic
	540	// ----------------------------------------------------------------------------------------
550	541
551		// ----------------------------------------------------------------------------------------
552		// Score logic ...
553		// ----------------------------------------------------------------------------------------
	542	TTL_7404_INVERT(ic_e3a, 128H)
	543	TTL_7427_NOR( ic_e3b, 256H, 64H, ic_e3a.Q)
	544	TTL_7410_NAND(ic_e2c, 256H, 64H, ic_e3a.Q)
	545	TTL_7404_INVERT(ic_e3c, ic_e2c.Q)
	546	TTL_7402_NOR(ic_d2c, ic_e3c.Q, ic_e3b.Q)
	547	TTL_7404_INVERT(ic_g1a, 32V)
	548	TTL_7425_NOR(ic_f2a, ic_g1a.Q, 64V, 128V, ic_d2c.Q)
	549	ALIAS(c5_en, ic_f2a.Q)
554	550
555		TTL_7402_NOR(ic_f5b, L, Missed)
556		TTL_7490(ic_c7, ic_f5b, ic_c7.QA, SRST, SRST, low, low)
557		TTL_74107(ic_c8a, ic_c7.QD, high, high, SRSTQ)
558		SWITCH2(sw1a)
559		PARAM(sw1a.POS, 0)
	551	// ----------------------------------------------------------------------------------------
	552	// Score logic ...
	553	// ----------------------------------------------------------------------------------------
560	554
561		NET_C(sw1a.1, high)
562		//NET_C(sw1a.1, V5)
563		NET_C(sw1a.2, ic_c7.QC)
	555	TTL_7402_NOR(ic_f5b, L, Missed)
	556	TTL_7490(ic_c7, ic_f5b, ic_c7.QA, SRST, SRST, low, low)
	557	TTL_74107(ic_c8a, ic_c7.QD, high, high, SRSTQ)
	558	SWITCH2(sw1a)
	559	PARAM(sw1a.POS, 0)
564	560
565		TTL_7410_NAND(ic_d8a, ic_c7.QA, sw1a.Q, ic_c8a.Q) // would be nand2 for 11 instead of 15 points, need a switch dev!
	561	NET_C(sw1a.1, high)
	562	//NET_C(sw1a.1, V5)
	563	NET_C(sw1a.2, ic_c7.QC)
566	564
567		ALIAS(StopG1Q, ic_d8a.Q)
568		ALIAS(score1_1, ic_c7.QA)
569		ALIAS(score1_2, ic_c7.QB)
570		ALIAS(score1_4, ic_c7.QC)
571		ALIAS(score1_8, ic_c7.QD)
572		ALIAS(score1_10, ic_c8a.Q)
573		ALIAS(score1_10Q, ic_c8a.QQ)
	565	TTL_7410_NAND(ic_d8a, ic_c7.QA, sw1a.Q, ic_c8a.Q) // would be nand2 for 11 instead of 15 points, need a switch dev!
574	566
575		TTL_7402_NOR(ic_f5a, R, Missed)
576		TTL_7490(ic_d7, ic_f5a, ic_d7.QA, SRST, SRST, low, low)
577		TTL_74107(ic_c8b, ic_d7.QD, high, high, SRSTQ)
578		SWITCH2(sw1b)
579		PARAM(sw1b.POS, 0)
	567	ALIAS(StopG1Q, ic_d8a.Q)
	568	ALIAS(score1_1, ic_c7.QA)
	569	ALIAS(score1_2, ic_c7.QB)
	570	ALIAS(score1_4, ic_c7.QC)
	571	ALIAS(score1_8, ic_c7.QD)
	572	ALIAS(score1_10, ic_c8a.Q)
	573	ALIAS(score1_10Q, ic_c8a.QQ)
580	574
581		NET_C(sw1b.1, high)
582		//NET_C(sw1b.1, V5)
583		NET_C(sw1b.2, ic_d7.QC)
	575	TTL_7402_NOR(ic_f5a, R, Missed)
	576	TTL_7490(ic_d7, ic_f5a, ic_d7.QA, SRST, SRST, low, low)
	577	TTL_74107(ic_c8b, ic_d7.QD, high, high, SRSTQ)
	578	SWITCH2(sw1b)
	579	PARAM(sw1b.POS, 0)
584	580
	581	NET_C(sw1b.1, high)
	582	//NET_C(sw1b.1, V5)
	583	NET_C(sw1b.2, ic_d7.QC)
585	584
586		TTL_7410_NAND(ic_d8b, ic_d7.QA, sw1b.Q, ic_c8b.Q) // would be nand2 for 11 instead of 15 points, need a switch dev!
587	585
588		ALIAS(StopG2Q, ic_d8b.Q)
589		ALIAS(score2_1, ic_d7.QA)
590		ALIAS(score2_2, ic_d7.QB)
591		ALIAS(score2_4, ic_d7.QC)
592		ALIAS(score2_8, ic_d7.QD)
593		ALIAS(score2_10, ic_c8b.Q)
594		ALIAS(score2_10Q, ic_c8b.QQ)
	586	TTL_7410_NAND(ic_d8b, ic_d7.QA, sw1b.Q, ic_c8b.Q) // would be nand2 for 11 instead of 15 points, need a switch dev!
595	587
596		// ----------------------------------------------------------------------------------------
597		// Score display
598		// ----------------------------------------------------------------------------------------
	588	ALIAS(StopG2Q, ic_d8b.Q)
	589	ALIAS(score2_1, ic_d7.QA)
	590	ALIAS(score2_2, ic_d7.QB)
	591	ALIAS(score2_4, ic_d7.QC)
	592	ALIAS(score2_8, ic_d7.QD)
	593	ALIAS(score2_10, ic_c8b.Q)
	594	ALIAS(score2_10Q, ic_c8b.QQ)
599	595
600		TTL_74153(ic_d6a, score1_10Q, score1_4, score2_10Q, score2_4, 32H, 64H, low)
601		TTL_74153(ic_d6b, score1_10Q, score1_8, score2_10Q, score2_8, 32H, 64H, low)
	596	// ----------------------------------------------------------------------------------------
	597	// Score display
	598	// ----------------------------------------------------------------------------------------
602	599
603		TTL_74153(ic_c6a, high, score1_1, high, score2_1, 32H, 64H, low)
604		TTL_74153(ic_c6b, score1_10Q, score1_2, score2_10Q, score2_2, 32H, 64H, low)
	600	TTL_74153(ic_d6a, score1_10Q, score1_4, score2_10Q, score2_4, 32H, 64H, low)
	601	TTL_74153(ic_d6b, score1_10Q, score1_8, score2_10Q, score2_8, 32H, 64H, low)
605	602
606		TTL_7448(ic_c5, ic_c6a.AY, ic_c6b.AY, ic_d6a.AY, ic_d6b.AY, high, c5_en, high)
	603	TTL_74153(ic_c6a, high, score1_1, high, score2_1, 32H, 64H, low)
	604	TTL_74153(ic_c6b, score1_10Q, score1_2, score2_10Q, score2_2, 32H, 64H, low)
607	605
608		TTL_7404_INVERT(ic_e4b, 16H)
609		TTL_7427_NOR(ic_e5c, ic_e4b.Q, 8H, 4H)
610		ALIAS(scoreFE, ic_e5c.Q)
	606	TTL_7448(ic_c5, ic_c6a.AY, ic_c6b.AY, ic_d6a.AY, ic_d6b.AY, high, c5_en, high)
611	607
612		TTL_7400_NAND(ic_c3d, 8H, 4H)
613		//TTL_7400_NAND(ic_c3d, 4H, 8H)
614		TTL_7402_NOR(ic_d2b, ic_e4b.Q, ic_c3d.Q)
615		ALIAS(scoreBC, ic_d2b.Q)
	608	TTL_7404_INVERT(ic_e4b, 16H)
	609	TTL_7427_NOR(ic_e5c, ic_e4b.Q, 8H, 4H)
	610	ALIAS(scoreFE, ic_e5c.Q)
616	611
617		TTL_7427_NOR(ic_e5b, ic_e4b.Q, 8V, 4V)
618		ALIAS(scoreA, ic_e5b.Q)
	612	TTL_7400_NAND(ic_c3d, 8H, 4H)
	613	//TTL_7400_NAND(ic_c3d, 4H, 8H)
	614	TTL_7402_NOR(ic_d2b, ic_e4b.Q, ic_c3d.Q)
	615	ALIAS(scoreBC, ic_d2b.Q)
619	616
620		TTL_7410_NAND(ic_e2a, 16H, 8V, 4V)
621		TTL_7404_INVERT(ic_e4a, ic_e2a.Q)
622		ALIAS(scoreGD, ic_e4a.Q)
	617	TTL_7427_NOR(ic_e5b, ic_e4b.Q, 8V, 4V)
	618	ALIAS(scoreA, ic_e5b.Q)
623	619
624		TTL_7404_INVERT(ic_e4c, 16V)
	620	TTL_7410_NAND(ic_e2a, 16H, 8V, 4V)
	621	TTL_7404_INVERT(ic_e4a, ic_e2a.Q)
	622	ALIAS(scoreGD, ic_e4a.Q)
625	623
626		TTL_7410_NAND(ic_d4a, ic_e4c.Q, ic_c5.f, scoreFE)
627		TTL_7410_NAND(ic_d5c, 16V, ic_c5.e, scoreFE)
628		TTL_7410_NAND(ic_c4c, ic_e4c.Q, ic_c5.b, scoreBC)
629		TTL_7410_NAND(ic_d5a, 16V, ic_c5.c, scoreBC)
630		TTL_7410_NAND(ic_d4c, ic_e4c.Q, ic_c5.a, scoreA)
631		TTL_7410_NAND(ic_d4b, ic_e4c.Q, ic_c5.g, scoreGD)
632		TTL_7410_NAND(ic_d5b, 16V, ic_c5.d, scoreGD)
	624	TTL_7404_INVERT(ic_e4c, 16V)
633	625
634		TTL_7430_NAND(ic_d3, ic_d4a, ic_d5c, ic_c4c, ic_d5a, ic_d4c, ic_d4b, ic_d5b, high)
635		ALIAS(score, ic_d3.Q) //FIXME
	626	TTL_7410_NAND(ic_d4a, ic_e4c.Q, ic_c5.f, scoreFE)
	627	TTL_7410_NAND(ic_d5c, 16V, ic_c5.e, scoreFE)
	628	TTL_7410_NAND(ic_c4c, ic_e4c.Q, ic_c5.b, scoreBC)
	629	TTL_7410_NAND(ic_d5a, 16V, ic_c5.c, scoreBC)
	630	TTL_7410_NAND(ic_d4c, ic_e4c.Q, ic_c5.a, scoreA)
	631	TTL_7410_NAND(ic_d4b, ic_e4c.Q, ic_c5.g, scoreGD)
	632	TTL_7410_NAND(ic_d5b, 16V, ic_c5.d, scoreGD)
636	633
637		// net
638		TTL_74107(ic_f3b, clk, 256H, 256HQ, high)
639		TTL_7400_NAND(ic_g3b, ic_f3b.QQ, 256H)
640		TTL_7427_NOR(ic_g2b, ic_g3b.Q, vblank, 4V)
641		ALIAS(net, ic_g2b.Q)
	634	TTL_7430_NAND(ic_d3, ic_d4a, ic_d5c, ic_c4c, ic_d5a, ic_d4c, ic_d4b, ic_d5b, high)
	635	ALIAS(score, ic_d3.Q) //FIXME
642	636
643		// ----------------------------------------------------------------------------------------
644		// video
645		// ----------------------------------------------------------------------------------------
	637	// net
	638	TTL_74107(ic_f3b, clk, 256H, 256HQ, high)
	639	TTL_7400_NAND(ic_g3b, ic_f3b.QQ, 256H)
	640	TTL_7427_NOR(ic_g2b, ic_g3b.Q, vblank, 4V)
	641	ALIAS(net, ic_g2b.Q)
646	642
647		TTL_7402_NOR(ic_g1b, hvidQ, vvidQ)
648		TTL_7425_NOR(ic_f2b, ic_g1b.Q, pad1, pad2, net)
649		TTL_7404_INVERT(ic_e4e, ic_f2b.Q)
650		ALIAS(video, ic_e4e.Q)
	643	// ----------------------------------------------------------------------------------------
	644	// video
	645	// ----------------------------------------------------------------------------------------
651	646
652		TTL_7486_XOR(ic_a4d, hsyncQ, vsyncQ)
653		TTL_7404_INVERT(ic_e4f, ic_a4d.Q)
	647	TTL_7402_NOR(ic_g1b, hvidQ, vvidQ)
	648	TTL_7425_NOR(ic_f2b, ic_g1b.Q, pad1, pad2, net)
	649	TTL_7404_INVERT(ic_e4e, ic_f2b.Q)
	650	ALIAS(video, ic_e4e.Q)
654	651
655		RES(RV1, RES_K(1))
656		RES(RV2, RES_K(1.2))
657		RES(RV3, RES_K(22))
658		NET_C(video, RV1.1)
659		NET_C(score, RV2.1)
660		NET_C(ic_e4f.Q, RV3.1)
661		NET_C(RV1.2, RV2.2)
662		NET_C(RV2.2, RV3.2)
	652	TTL_7486_XOR(ic_a4d, hsyncQ, vsyncQ)
	653	TTL_7404_INVERT(ic_e4f, ic_a4d.Q)
663	654
664		ALIAS(videomix, RV3.2)
	655	RES(RV1, RES_K(1))
	656	RES(RV2, RES_K(1.2))
	657	RES(RV3, RES_K(22))
	658	NET_C(video, RV1.1)
	659	NET_C(score, RV2.1)
	660	NET_C(ic_e4f.Q, RV3.1)
	661	NET_C(RV1.2, RV2.2)
	662	NET_C(RV2.2, RV3.2)
665	663
	664	ALIAS(videomix, RV3.2)
	665
666	666	NETLIST_END()
667	667
668	668	class pong_state : public driver_device
r29404	r29405
725	725	INCLUDE(pong_schematics)
726	726
727	727	//NETDEV_ANALOG_CALLBACK(sound_cb, sound, pong_state, sound_cb, "")
728		//NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	728	//NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
729	729
730	730	NETLIST_END()
731	731
r29404	r29405
733	733
734	734	static NETLIST_START(pongd)
735	735
736		INCLUDE(pongdoubles)
	736	INCLUDE(pongdoubles)
737	737
738		//NETDEV_ANALOG_CALLBACK(sound_cb, AUDIO, pong_state, sound_cb, "")
739		//NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	738	//NETDEV_ANALOG_CALLBACK(sound_cb, AUDIO, pong_state, sound_cb, "")
	739	//NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
740	740
741	741	NETLIST_END()
742	742	#endif
r29404	r29405
744	744	#ifdef TEST_SOUND
745	745	static NETLIST_START(test)
746	746
747		/*
748		* Astable multivibrator using two 7400 gates (or inverters)
749		*
750		*/
	747	/*
	748	* Astable multivibrator using two 7400 gates (or inverters)
	749	*
	750	*/
751	751
752		/* Standard stuff */
	752	/* Standard stuff */
753	753
754		SOLVER(Solver)
755		PARAM(Solver.FREQ, 48000)
	754	SOLVER(Solver)
	755	PARAM(Solver.FREQ, 48000)
756	756
757		//NETDEV_SOUND_IN(SND_IN)
758		//PARAM(SND_IN.CHAN0, "tin.IN")
	757	//NETDEV_SOUND_IN(SND_IN)
	758	//PARAM(SND_IN.CHAN0, "tin.IN")
759	759
760		ANALOG_INPUT(tin, 0)
	760	ANALOG_INPUT(tin, 0)
761	761
762		// astable NAND Multivibrator
763		RES(R1, 1000)
764		CAP(C1, 1e-6)
765		TTL_7400_NAND(n1,R1.1,R1.1)
766		TTL_7400_NAND(n2,R1.2,R1.2)
767		NET_C(n1.Q, R1.2)
768		NET_C(n2.Q, C1.1)
769		NET_C(C1.2, R1.1)
770		LOG(log1, n2.Q)
	762	// astable NAND Multivibrator
	763	RES(R1, 1000)
	764	CAP(C1, 1e-6)
	765	TTL_7400_NAND(n1,R1.1,R1.1)
	766	TTL_7400_NAND(n2,R1.2,R1.2)
	767	NET_C(n1.Q, R1.2)
	768	NET_C(n2.Q, C1.1)
	769	NET_C(C1.2, R1.1)
	770	LOG(log1, n2.Q)
771	771
772	772	#if 0
773		NETDEV_SOUND_OUT(CH0, 0)
774		NET_C(CH0.IN, n2.Q)
	773	NETDEV_SOUND_OUT(CH0, 0)
	774	NET_C(CH0.IN, n2.Q)
775	775
776		NETDEV_SOUND_OUT(CH1, 1)
777		NET_C(CH1.IN, tin.Q)
	776	NETDEV_SOUND_OUT(CH1, 1)
	777	NET_C(CH1.IN, tin.Q)
778	778	#endif
779	779
780	780	NETLIST_END()
r29404	r29405
809	809
810	810	static INPUT_PORTS_START( pong )
811	811	PORT_START( "PADDLE0" ) /* fake input port for player 1 paddle */
812		PORT_BIT( 0xff, 0x00, IPT_PADDLE ) PORT_SENSITIVITY(2) PORT_KEYDELTA(100) PORT_CENTERDELTA(0) NETLIST_ANALOG_PORT_CHANGED("maincpu", "pot0")
	812	PORT_BIT( 0xff, 0x00, IPT_PADDLE ) PORT_SENSITIVITY(2) PORT_KEYDELTA(100) PORT_CENTERDELTA(0) NETLIST_ANALOG_PORT_CHANGED("maincpu", "pot0")
813	813
814	814	PORT_START( "PADDLE1" ) /* fake input port for player 2 paddle */
815		PORT_BIT( 0xff, 0x00, IPT_PADDLE ) PORT_SENSITIVITY(2) PORT_KEYDELTA(100) PORT_CENTERDELTA(0) PORT_PLAYER(2) NETLIST_ANALOG_PORT_CHANGED("maincpu", "pot1")
	815	PORT_BIT( 0xff, 0x00, IPT_PADDLE ) PORT_SENSITIVITY(2) PORT_KEYDELTA(100) PORT_CENTERDELTA(0) PORT_PLAYER(2) NETLIST_ANALOG_PORT_CHANGED("maincpu", "pot1")
816	816
817	817	PORT_START("IN0") /* fake as well */
818	818	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 ) NETLIST_LOGIC_PORT_CHANGED("maincpu", "coinsw")
r29404	r29405
821	821	PORT_DIPSETTING( 0x00, "11" )
822	822	PORT_DIPSETTING( 0x06, "15" )
823	823
824		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SERVICE ) PORT_NAME("Antenna") NETLIST_LOGIC_PORT_CHANGED("maincpu", "antenna")
	824	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SERVICE ) PORT_NAME("Antenna") NETLIST_LOGIC_PORT_CHANGED("maincpu", "antenna")
825	825
826	826	PORT_START("VR1")
827	827	PORT_ADJUSTER( 50, "VR1 - 50k, Paddle 1 adjustment" ) NETLIST_ANALOG_PORT_CHANGED("maincpu", "vr0")
r29404	r29405
833	833	#if PONGD
834	834	static INPUT_PORTS_START( pongd )
835	835	#if 0
836		PORT_START( "PADDLE0" ) /* fake input port for player 1 paddle */
837		PORT_BIT( 0xff, 0x00, IPT_PADDLE ) PORT_SENSITIVITY(2) PORT_KEYDELTA(100) PORT_CENTERDELTA(0) NETLIST_ANALOG_PORT_CHANGED("maincpu", "pot0")
	836	PORT_START( "PADDLE0" ) /* fake input port for player 1 paddle */
	837	PORT_BIT( 0xff, 0x00, IPT_PADDLE ) PORT_SENSITIVITY(2) PORT_KEYDELTA(100) PORT_CENTERDELTA(0) NETLIST_ANALOG_PORT_CHANGED("maincpu", "pot0")
838	838
839		PORT_START( "PADDLE1" ) /* fake input port for player 2 paddle */
840		PORT_BIT( 0xff, 0x00, IPT_PADDLE ) PORT_SENSITIVITY(2) PORT_KEYDELTA(100) PORT_CENTERDELTA(0) PORT_PLAYER(2) NETLIST_ANALOG_PORT_CHANGED("maincpu", "pot1")
	839	PORT_START( "PADDLE1" ) /* fake input port for player 2 paddle */
	840	PORT_BIT( 0xff, 0x00, IPT_PADDLE ) PORT_SENSITIVITY(2) PORT_KEYDELTA(100) PORT_CENTERDELTA(0) PORT_PLAYER(2) NETLIST_ANALOG_PORT_CHANGED("maincpu", "pot1")
841	841	#endif
842	842
843		PORT_START("IN0") /* fake as well */
844		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 ) NETLIST_LOGIC_PORT_CHANGED("maincpu", "coinsw")
845		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START1 ) NETLIST_LOGIC_PORT_CHANGED("maincpu", "startsw")
	843	PORT_START("IN0") /* fake as well */
	844	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 ) NETLIST_LOGIC_PORT_CHANGED("maincpu", "coinsw")
	845	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START1 ) NETLIST_LOGIC_PORT_CHANGED("maincpu", "startsw")
846	846
847	847	#if 0
848		PORT_DIPNAME( 0x06, 0x00, "Game Won" ) PORT_DIPLOCATION("SW1A:1,SW1B:1") PORT_CHANGED_MEMBER(DEVICE_SELF, pong_state, input_changed, IC_SWITCH)
849		PORT_DIPSETTING( 0x00, "11" )
850		PORT_DIPSETTING( 0x06, "15" )
	848	PORT_DIPNAME( 0x06, 0x00, "Game Won" ) PORT_DIPLOCATION("SW1A:1,SW1B:1") PORT_CHANGED_MEMBER(DEVICE_SELF, pong_state, input_changed, IC_SWITCH)
	849	PORT_DIPSETTING( 0x00, "11" )
	850	PORT_DIPSETTING( 0x06, "15" )
851	851
852		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SERVICE ) PORT_NAME("Antenna") NETLIST_LOGIC_PORT_CHANGED("maincpu", "antenna")
	852	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SERVICE ) PORT_NAME("Antenna") NETLIST_LOGIC_PORT_CHANGED("maincpu", "antenna")
853	853
854		PORT_START("VR1")
855		PORT_ADJUSTER( 50, "VR1 - 50k, Paddle 1 adjustment" ) NETLIST_ANALOG_PORT_CHANGED("maincpu", "vr0")
856		PORT_START("VR2")
857		PORT_ADJUSTER( 50, "VR2 - 50k, Paddle 2 adjustment" ) NETLIST_ANALOG_PORT_CHANGED("maincpu", "vr1")
	854	PORT_START("VR1")
	855	PORT_ADJUSTER( 50, "VR1 - 50k, Paddle 1 adjustment" ) NETLIST_ANALOG_PORT_CHANGED("maincpu", "vr0")
	856	PORT_START("VR2")
	857	PORT_ADJUSTER( 50, "VR2 - 50k, Paddle 2 adjustment" ) NETLIST_ANALOG_PORT_CHANGED("maincpu", "vr1")
858	858	#endif
859	859	INPUT_PORTS_END
860	860
r29404	r29405
863	863	static MACHINE_CONFIG_START( pong, pong_state )
864	864
865	865	/* basic machine hardware */
866		MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
867		MCFG_NETLIST_SETUP(pong)
	866	MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
	867	MCFG_NETLIST_SETUP(pong)
868	868
869		MCFG_NETLIST_ANALOG_INPUT("maincpu", "vr0", "ic_b9_R.R")
870		MCFG_NETLIST_ANALOG_MULT_OFFSET(1.0 / 100.0 * RES_K(50), RES_K(56) )
871		MCFG_NETLIST_ANALOG_INPUT("maincpu", "vr1", "ic_a9_R.R")
872		MCFG_NETLIST_ANALOG_MULT_OFFSET(1.0 / 100.0 * RES_K(50), RES_K(56) )
873		MCFG_NETLIST_ANALOG_INPUT("maincpu", "pot0", "ic_b9_POT.DIAL")
874		MCFG_NETLIST_ANALOG_INPUT("maincpu", "pot1", "ic_a9_POT.DIAL")
875		MCFG_NETLIST_LOGIC_INPUT("maincpu", "sw1a", "sw1a.POS", 0, 0x01)
876		MCFG_NETLIST_LOGIC_INPUT("maincpu", "sw1b", "sw1b.POS", 0, 0x01)
877		MCFG_NETLIST_LOGIC_INPUT("maincpu", "coinsw", "coinsw.POS", 0, 0x01)
878		MCFG_NETLIST_LOGIC_INPUT("maincpu", "antenna", "antenna.IN", 0, 0x01)
	869	MCFG_NETLIST_ANALOG_INPUT("maincpu", "vr0", "ic_b9_R.R")
	870	MCFG_NETLIST_ANALOG_MULT_OFFSET(1.0 / 100.0 * RES_K(50), RES_K(56) )
	871	MCFG_NETLIST_ANALOG_INPUT("maincpu", "vr1", "ic_a9_R.R")
	872	MCFG_NETLIST_ANALOG_MULT_OFFSET(1.0 / 100.0 * RES_K(50), RES_K(56) )
	873	MCFG_NETLIST_ANALOG_INPUT("maincpu", "pot0", "ic_b9_POT.DIAL")
	874	MCFG_NETLIST_ANALOG_INPUT("maincpu", "pot1", "ic_a9_POT.DIAL")
	875	MCFG_NETLIST_LOGIC_INPUT("maincpu", "sw1a", "sw1a.POS", 0, 0x01)
	876	MCFG_NETLIST_LOGIC_INPUT("maincpu", "sw1b", "sw1b.POS", 0, 0x01)
	877	MCFG_NETLIST_LOGIC_INPUT("maincpu", "coinsw", "coinsw.POS", 0, 0x01)
	878	MCFG_NETLIST_LOGIC_INPUT("maincpu", "antenna", "antenna.IN", 0, 0x01)
879	879
880		MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "snd0", "sound", pong_state, sound_cb, "")
881		MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "vid0", "videomix", fixedfreq_device, update_vid, "fixfreq")
	880	MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "snd0", "sound", pong_state, sound_cb, "")
	881	MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "vid0", "videomix", fixedfreq_device, update_vid, "fixfreq")
882	882
883	883	/* video hardware */
884	884
r29404	r29405
890	890	MCFG_SPEAKER_STANDARD_MONO("mono")
891	891	MCFG_SOUND_ADD("dac", DAC, 48000)
892	892	#ifdef TEST_SOUND
893		MCFG_SOUND_ROUTE_EX(0, "snd_test", 1.0, 0)
	893	MCFG_SOUND_ROUTE_EX(0, "snd_test", 1.0, 0)
894	894	#else
895		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	895	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
896	896	#endif
897	897
898	898	#ifdef TEST_SOUND
899		MCFG_SOUND_ADD("snd_test", NETLIST_SOUND, 48000)
900		MCFG_NETLIST_SETUP(test)
901		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	899	MCFG_SOUND_ADD("snd_test", NETLIST_SOUND, 48000)
	900	MCFG_NETLIST_SETUP(test)
	901	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
902	902
903		MCFG_NETLIST_STREAM_INPUT("snd_test", 0, "tin.IN")
904		MCFG_NETLIST_ANALOG_MULT_OFFSET(0.001, 0.0)
	903	MCFG_NETLIST_STREAM_INPUT("snd_test", 0, "tin.IN")
	904	MCFG_NETLIST_ANALOG_MULT_OFFSET(0.001, 0.0)
905	905
906		//MCFG_NETLIST_STREAM_OUTPUT("snd_test", 0, "tin.Q", 100)
907		MCFG_NETLIST_STREAM_OUTPUT("snd_test", 0, "n2.Q")
908		MCFG_NETLIST_ANALOG_MULT_OFFSET(1000.0, 0.0)
909		MCFG_NETLIST_STREAM_OUTPUT("snd_test", 1, "tin.Q")
910		MCFG_NETLIST_ANALOG_MULT_OFFSET(1000.0, 0.0)
	906	//MCFG_NETLIST_STREAM_OUTPUT("snd_test", 0, "tin.Q", 100)
	907	MCFG_NETLIST_STREAM_OUTPUT("snd_test", 0, "n2.Q")
	908	MCFG_NETLIST_ANALOG_MULT_OFFSET(1000.0, 0.0)
	909	MCFG_NETLIST_STREAM_OUTPUT("snd_test", 1, "tin.Q")
	910	MCFG_NETLIST_ANALOG_MULT_OFFSET(1000.0, 0.0)
911	911
912	912	#endif
913	913
r29404	r29405
916	916	static MACHINE_CONFIG_DERIVED( pongf, pong )
917	917
918	918	/* basic machine hardware */
919		MCFG_DEVICE_MODIFY("maincpu")
	919	MCFG_DEVICE_MODIFY("maincpu")
920	920	MCFG_NETLIST_SETUP(pong_fast)
921	921
922	922	MACHINE_CONFIG_END
r29404	r29405
924	924	#if PONGD
925	925	static MACHINE_CONFIG_START( pongd, pong_state )
926	926
927		/* basic machine hardware */
928		MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
929		MCFG_NETLIST_SETUP(pongd)
	927	/* basic machine hardware */
	928	MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
	929	MCFG_NETLIST_SETUP(pongd)
930	930
931	931	#if 0
932		MCFG_NETLIST_ANALOG_INPUT("maincpu", "vr0", "ic_b9_R.R")
933		MCFG_NETLIST_ANALOG_INPUT_MULT_OFFSET(1.0 / 100.0 * RES_K(50), RES_K(56) )
934		MCFG_NETLIST_ANALOG_INPUT("maincpu", "vr1", "ic_a9_R.R")
935		MCFG_NETLIST_ANALOG_INPUT_MULT_OFFSET(1.0 / 100.0 * RES_K(50), RES_K(56) )
936		MCFG_NETLIST_ANALOG_INPUT("maincpu", "pot0", "ic_b9_POT.DIAL")
937		MCFG_NETLIST_ANALOG_INPUT("maincpu", "pot1", "ic_a9_POT.DIAL")
	932	MCFG_NETLIST_ANALOG_INPUT("maincpu", "vr0", "ic_b9_R.R")
	933	MCFG_NETLIST_ANALOG_INPUT_MULT_OFFSET(1.0 / 100.0 * RES_K(50), RES_K(56) )
	934	MCFG_NETLIST_ANALOG_INPUT("maincpu", "vr1", "ic_a9_R.R")
	935	MCFG_NETLIST_ANALOG_INPUT_MULT_OFFSET(1.0 / 100.0 * RES_K(50), RES_K(56) )
	936	MCFG_NETLIST_ANALOG_INPUT("maincpu", "pot0", "ic_b9_POT.DIAL")
	937	MCFG_NETLIST_ANALOG_INPUT("maincpu", "pot1", "ic_a9_POT.DIAL")
938	938	#endif
939		MCFG_NETLIST_LOGIC_INPUT("maincpu", "sw1a", "DIPSW1.POS", 0, 0x01)
940		MCFG_NETLIST_LOGIC_INPUT("maincpu", "sw1b", "DIPSW2.POS", 0, 0x01)
941		MCFG_NETLIST_LOGIC_INPUT("maincpu", "coinsw", "COIN_SW.POS", 0, 0x01)
942		MCFG_NETLIST_LOGIC_INPUT("maincpu", "startsw", "START_SW.POS", 0, 0x01)
	939	MCFG_NETLIST_LOGIC_INPUT("maincpu", "sw1a", "DIPSW1.POS", 0, 0x01)
	940	MCFG_NETLIST_LOGIC_INPUT("maincpu", "sw1b", "DIPSW2.POS", 0, 0x01)
	941	MCFG_NETLIST_LOGIC_INPUT("maincpu", "coinsw", "COIN_SW.POS", 0, 0x01)
	942	MCFG_NETLIST_LOGIC_INPUT("maincpu", "startsw", "START_SW.POS", 0, 0x01)
943	943	#if 0
944		MCFG_NETLIST_LOGIC_INPUT("maincpu", "antenna", "antenna.IN", 0, 0x01)
	944	MCFG_NETLIST_LOGIC_INPUT("maincpu", "antenna", "antenna.IN", 0, 0x01)
945	945	#endif
946	946
947		MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "snd0", "AUDIO", pong_state, sound_cb, "")
948		MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "vid0", "videomix", fixedfreq_device, update_vid, "fixfreq")
	947	MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "snd0", "AUDIO", pong_state, sound_cb, "")
	948	MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "vid0", "videomix", fixedfreq_device, update_vid, "fixfreq")
949	949
950		/* video hardware */
	950	/* video hardware */
951	951
952		//MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_ntsc720)
953		//MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_pongX2)
954		MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_pongd)
	952	//MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_ntsc720)
	953	//MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_pongX2)
	954	MCFG_FIXFREQ_ADD("fixfreq", "screen", fixedfreq_mode_pongd)
955	955
956		/* sound hardware */
957		MCFG_SPEAKER_STANDARD_MONO("mono")
958		MCFG_SOUND_ADD("dac", DAC, 48000)
959		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	956	/* sound hardware */
	957	MCFG_SPEAKER_STANDARD_MONO("mono")
	958	MCFG_SOUND_ADD("dac", DAC, 48000)
	959	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
960	960
961	961	MACHINE_CONFIG_END
962	962
r29404	r29405
970	970
971	971	ROM_START( pong ) /* dummy to satisfy game entry*/
972	972	ROM_REGION( 0x10000, "maincpu", 0 ) /* enough for netlist */
973		ROM_LOAD( "pong.netlist", 0x000000, 0x00457f, CRC(72d5e4fe) SHA1(7bb15828223c34915c5e2869dd7917532a4bb7b4) )
	973	ROM_LOAD( "pong.netlist", 0x000000, 0x00457f, CRC(72d5e4fe) SHA1(7bb15828223c34915c5e2869dd7917532a4bb7b4) )
974	974	ROM_END
975	975
976	976	ROM_START( pongf ) /* dummy to satisfy game entry*/
r29404	r29405
979	979
980	980	#if PONGD
981	981	ROM_START( pongd ) /* dummy to satisfy game entry*/
982		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	982	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
983	983	ROM_END
984	984	#endif
985	985

trunk/src/mame/drivers/popobear.c
r29404	r29405
110	110	required_shared_ptr<UINT16> m_vregs;
111	111	optional_device<gfxdecode_device> m_gfxdecode;
112	112	required_device<palette_device> m_palette;
113
	113
114	114	UINT16* m_vram;
115	115	UINT16* m_vram_rearranged;
116	116
r29404	r29405
661	661	MCFG_SPEAKER_STANDARD_MONO("mono")
662	662
663	663	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
664
	664
665	665	MCFG_SOUND_ADD("ymsnd", YM2413, XTAL_42MHz/16) // XTAL CORRECT, DIVISOR GUESSED
666	666	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
667	667

trunk/src/mame/drivers/gaiden.c
r29404	r29405
1511	1511	int i;
1512	1512	UINT8 *ROM = memregion("maincpu")->base();
1513	1513	size_t size = memregion("maincpu")->bytes();
1514
	1514
1515	1515	{
1516	1516	dynamic_buffer buffer(size);
1517	1517

trunk/src/mame/drivers/astrof.c
r29404	r29405
1311	1311
1312	1312	DRIVER_INIT_MEMBER(astrof_state,acombat3)
1313	1313	{
1314
1315	1314	/* set up protection handlers */
1316	1315	machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xa003, 0xa003, read8_delegate(FUNC(astrof_state::shoot_r),this));
1317	1316	machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xa004, 0xa004, read8_delegate(FUNC(astrof_state::abattle_coin_prot_r),this));

trunk/src/mame/drivers/kopunch.c
r29404	r29405
1	1	/********************************************************
2	2
3	3	KO Punch (c) 1981 Sega
4
	4
5	5	XTAL: ?
6	6	CPU: 8085 (proof: it uses SIM opcode)
7	7	Other: 4 x i8255 for all I/O
r29404	r29405
13	13
14	14
15	15	*********************************************************
16
	16
17	17	This is a simple boxing bag game, but for visual feedback
18	18	it has a small CRT instead of LEDs or a dial.
19
	19
20	20	Insert coin, select your weightclass (7 buttons on cab), and punch.
21
	21
22	22	Heavyweight - 300K
23	23	Middleweight - 260K
24	24	Welterweight - 230K

trunk/src/mame/drivers/segaybd.c
r29404	r29405
1189	1189	MCFG_SCREEN_PALETTE("palette")
1190	1190
1191	1191	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1192
	1192
1193	1193	MCFG_SEGA_SYS16B_SPRITES_ADD("bsprites")
1194	1194	MCFG_SEGA_YBOARD_SPRITES_ADD("ysprites")
1195	1195	MCFG_SEGAIC16VID_ADD("segaic16vid")

trunk/src/mame/drivers/igspoker.c
r29404	r29405
90	90	required_shared_ptr<UINT8> m_fg_color_ram;
91	91	required_device<gfxdecode_device> m_gfxdecode;
92	92	required_device<screen_device> m_screen;
93		required_device<palette_device> m_palette;
	93	required_device<palette_device> m_palette;
94	94	int m_nmi_enable;
95	95	int m_bg_enable;
96	96	int m_hopper;

trunk/src/mame/drivers/segaorun.c
r29404	r29405
404	404	const int center = 0x80;
405	405	const int right_limit = 0xe0;
406	406	const int tolerance = 2;
407
	407
408	408	if (pos <= left_limit + tolerance)
409	409	ret ^= 0x20;
410	410	else if (pos >= center - tolerance && pos <= center + tolerance)
r29404	r29405
428	428
429	429	if (data == 0)
430	430	return;
431
	431
432	432	m_bankmotor_delta = 8 - data;
433
	433
434	434	// convert to speed and direction for output
435	435	if (data < 8)
436	436	{
r29404	r29405
662	662	next_scanline = 65;
663	663	m_subcpu->set_input_line(4, CLEAR_LINE);
664	664	break;
665
	665
666	666	default:
667	667	break;
668	668	}
r29404	r29405
688	688	const int speed = 100;
689	689	const int left_limit = 0x2000;
690	690	const int right_limit = 0xe000;
691
	691
692	692	m_bankmotor_pos += speed * m_bankmotor_delta;
693	693	if (m_bankmotor_pos <= left_limit)
694	694	m_bankmotor_pos = left_limit;
r29404	r29405
729	729
730	730	case 0x60/2:
731	731	return watchdog_reset_r(space, 0);
732
	732
733	733	default:
734	734	break;
735	735	}
r29404	r29405
781	781	case 0x70/2:
782	782	m_sprites->draw_write(space, offset, data, mem_mask);
783	783	return;
784
	784
785	785	default:
786	786	break;
787	787	}
r29404	r29405
814	814	static const char *const ports[] = { "ADC0", "ADC1", "ADC2", "ADC3" };
815	815	return ioport(ports[m_adc_select])->read_safe(0x0010);
816	816	}
817
	817
818	818	default:
819	819	break;
820	820	}
r29404	r29405
866	866	case 0x3020/2:
867	867	// ADC trigger
868	868	return;
869
	869
870	870	default:
871	871	break;
872	872	}
r29404	r29405
1210	1210	MCFG_SCREEN_RAW_PARAMS(MASTER_CLOCK_25MHz/4, 400, 0, 320, 262, 0, 224)
1211	1211	MCFG_SCREEN_UPDATE_DRIVER(segaorun_state, screen_update_outrun)
1212	1212	MCFG_SCREEN_PALETTE("palette")
1213
	1213
1214	1214	MCFG_SEGAIC16VID_ADD("segaic16vid")
1215	1215	MCFG_SEGAIC16VID_GFXDECODE("gfxdecode")
1216	1216	MCFG_SEGAIC16_ROAD_ADD("segaic16road")

trunk/src/mame/drivers/mazerbla.c
r29404	r29405
1505	1505
1506	1506	MCFG_PALETTE_ADD("palette", 256+1)
1507	1507	MCFG_PALETTE_INIT_OWNER(mazerbla_state, mazerbla)
1508
	1508
1509	1509	/* sound hardware */
1510	1510	MACHINE_CONFIG_END
1511	1511

trunk/src/mame/drivers/acefruit.c
r29404	r29405
34	34	required_shared_ptr<UINT8> m_spriteram;
35	35	required_device<gfxdecode_device> m_gfxdecode;
36	36	required_device<screen_device> m_screen;
37		required_device<palette_device> m_palette;
	37	required_device<palette_device> m_palette;
38	38	emu_timer *m_refresh_timer;
39	39	DECLARE_WRITE8_MEMBER(acefruit_colorram_w);
40	40	DECLARE_WRITE8_MEMBER(acefruit_coin_w);

trunk/src/mame/drivers/itgambl3.c
r29404	r29405
483	483	ROM_LOAD( "xfivejs.u29", 0x00000, 0x80000, CRC(67d51cb4) SHA1(9182a63473a32a9ad91a7a6a47d5a5d965e3cb03) )
484	484	ROM_END
485	485
486		ROM_START( queenotg )
	486	ROM_START( queenotg )
487	487	ROM_REGION( 0x1000000, "maincpu", 0 ) /* all the program code is in here */
488	488	ROM_LOAD( "queenotg_m30624fgafp.mcu", 0x00000, 0x4000, NO_DUMP )
489	489
490		ROM_REGION( 0x200000, "gfx1", 0 )
	490	ROM_REGION( 0x200000, "gfx1", 0 )
491	491	ROM_LOAD( "u22.bin", 0x000000, 0x200000, CRC(b9bd0fac) SHA1(ce6a6d85e9ae47860cc6d270d8d563df58146b74) )
492	492
493		ROM_REGION( 0x80000, "oki", 0 )
	493	ROM_REGION( 0x80000, "oki", 0 )
494	494	ROM_LOAD( "u3.bin", 0x00000, 0x20000, CRC(f318927e) SHA1(f47ec9eb995b28403066fb2b66aad98c044676bc) )
495	495	ROM_END
496	496
497	497
498		ROM_START( ejollyx9 )
	498	ROM_START( ejollyx9 )
499	499	ROM_REGION( 0x1000000, "maincpu", 0 ) /* all the program code is in here */
500	500	ROM_LOAD( "ejollyx9_m30624fgafp.mcu", 0x00000, 0x4000, NO_DUMP )
501	501
502		ROM_REGION( 0x200000, "gfx1", 0 )
	502	ROM_REGION( 0x200000, "gfx1", 0 )
503	503	ROM_LOAD( "nm.u22", 0x000000, 0x200000, CRC(86b86a98) SHA1(cff4e79aaacad79e17e4dc52f2c14755424a2567) )
504	504
505		ROM_REGION( 0x80000, "oki", 0 )
	505	ROM_REGION( 0x80000, "oki", 0 )
506	506	ROM_LOAD( "nm.u3", 0x00000, 0x80000, CRC(0529696b) SHA1(7e182051baae0b7de1f5a2c18f1b68b695f339d8) )
507	507	ROM_END
508	508
r29404	r29405
518	518	GAME( 200?, x5jokers, 0, itgambl3, itgambl3, driver_device, 0, ROT0, "Electronic Projects", "X Five Jokers (Version 1.12)", GAME_IS_SKELETON )
519	519	GAME( 200?, queenotg, 0, itgambl3, itgambl3, driver_device, 0, ROT0, "<unknown>", "Queen of the Games", GAME_IS_SKELETON )
520	520	GAME( 200?, ejollyx9, 0, itgambl3, itgambl3, driver_device, 0, ROT0, "Solar Games", "Euro Jolly X9", GAME_IS_SKELETON )
521

trunk/src/mame/drivers/88games.c
r29404	r29405
372	372	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
373	373
374	374	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
375
	375
376	376	MCFG_K052109_ADD("k052109", _88games_k052109_intf)
377	377	MCFG_K052109_GFXDECODE("gfxdecode")
378		MCFG_K052109_PALETTE("palette")
	378	MCFG_K052109_PALETTE("palette")
379	379	MCFG_K051960_ADD("k051960", _88games_k051960_intf)
380	380	MCFG_K051960_GFXDECODE("gfxdecode")
381		MCFG_K051960_PALETTE("palette")
	381	MCFG_K051960_PALETTE("palette")
382	382	MCFG_K051316_ADD("k051316", _88games_k051316_intf)
383	383	MCFG_K051316_GFXDECODE("gfxdecode")
384	384	MCFG_K051316_PALETTE("palette")

trunk/src/mame/drivers/a1supply.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	A-1 Supply discrete hardware games
4
	4
5	5	TV 21 (197?)
6	6	TV 21 III (197?)
7	7	TV Poker (197?)
8	8
9		These actually seem to use Intel 4040 as a CPU + a lot of discrete circuitry...
	9	These actually seem to use Intel 4040 as a CPU + a lot of discrete circuitry...
10	10	to be checked!
11	11
12	12	***************************************************************************/
r29404	r29405
48	48	public:
49	49	a1supply_state(const machine_config &mconfig, device_type type, const char *tag)
50	50	: driver_device(mconfig, type, tag),
51		m_maincpu(*this, "maincpu"),
52		m_video(*this, "fixfreq")
	51	m_maincpu(*this, "maincpu"),
	52	m_video(*this, "fixfreq")
53	53	{
54	54	}
55
	55
56	56	// devices
57	57	required_device<netlist_mame_device_t> m_maincpu;
58	58	required_device<fixedfreq_device> m_video;
59
	59
60	60	protected:
61
	61
62	62	// driver_device overrides
63	63	virtual void machine_start();
64	64	virtual void machine_reset();
65
	65
66	66	virtual void video_start();
67
	67
68	68	private:
69
	69
70	70	};
71	71
72	72
73	73	static NETLIST_START(a1supply)
74	74	SOLVER(Solver, 48000)
75		// PARAM(Solver.FREQ, 48000)
	75	// PARAM(Solver.FREQ, 48000)
76	76	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
77	77
78	78	// schematics
79	79	//...
80	80
81		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
82		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	81	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	82	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
83	83	NETLIST_END()
84	84
85	85
r29404	r29405
109	109
110	110
111	111	/***************************************************************************
112
	112
113	113	Game driver(s)
114
	114
115	115	***************************************************************************/
116	116
117	117

trunk/src/mame/drivers/goldstar.c
r29404	r29405
155	155	output_set_lamp_value(4, (data >> 4) & 1); /* Stop 2 / Big / Bonus */
156	156	output_set_lamp_value(5, (data >> 5) & 1); /* Start / Stop All / Card 4 */
157	157
158		// popmessage("lamps: %02X", data);
	158	// popmessage("lamps: %02X", data);
159	159	}
160	160
161	161	WRITE8_MEMBER(goldstar_state::cb3_lamps_w)
r29404	r29405
176	176	output_set_lamp_value(4, (data >> 4) & 1); /* Stop 3 / Small / Info */
177	177	output_set_lamp_value(5, (data >> 5) & 1); /* Start / Stop All */
178	178
179		// popmessage("lamps: %02X", data);
	179	// popmessage("lamps: %02X", data);
180	180	}
181	181
182	182
r29404	r29405
244	244
245	245	AM_RANGE(0xf830, 0xf830) AM_DEVREADWRITE("aysnd", ay8910_device, data_r, data_w)
246	246	AM_RANGE(0xf840, 0xf840) AM_DEVWRITE("aysnd", ay8910_device, address_w)
247		AM_RANGE(0xf850, 0xf850) AM_WRITE(cb3_lamps_w) /* Control Set 1 lamps */
248		AM_RANGE(0xf860, 0xf860) AM_WRITE(cb3_lamps_w) /* Control Set 2 lamps */
	247	AM_RANGE(0xf850, 0xf850) AM_WRITE(cb3_lamps_w) /* Control Set 1 lamps */
	248	AM_RANGE(0xf860, 0xf860) AM_WRITE(cb3_lamps_w) /* Control Set 2 lamps */
249	249	AM_RANGE(0xf870, 0xf870) AM_DEVWRITE("snsnd", sn76489_device, write) /* guess... device is initialized, but doesn't seems to be used.*/
250	250	ADDRESS_MAP_END
251	251
r29404	r29405
296	296	AM_RANGE(0x0000, 0xb7ff) AM_ROM
297	297	AM_RANGE(0xb800, 0xbfff) AM_RAM AM_SHARE("nvram")
298	298	AM_RANGE(0xc000, 0xc7ff) AM_ROM
299
	299
300	300	/* Video RAM and reels stuff are there just as placeholder, and obviously in wrong offset */
301	301	AM_RANGE(0xc800, 0xcfff) AM_RAM_WRITE(goldstar_fg_vidram_w ) AM_SHARE("fg_vidram")
302	302	AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE(goldstar_fg_atrram_w ) AM_SHARE("fg_atrram")
r29404	r29405
307	307	AM_RANGE(0xf080, 0xf0bf) AM_RAM AM_SHARE("reel2_scroll")
308	308	AM_RANGE(0xf0c0, 0xf0ff) AM_RAM AM_SHARE("reel3_scroll")
309	309
310		/* Not really PPI's... They are emulated/simulated inside the CPLDs */
	310	/* Not really PPI's... They are emulated/simulated inside the CPLDs */
311	311	AM_RANGE(0xf600, 0xf603) AM_DEVREADWRITE("ppi8255_0", i8255_device, read, write) /* Input Ports */
312	312	AM_RANGE(0xf610, 0xf613) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write) /* Input Ports */
313	313	AM_RANGE(0xf620, 0xf623) AM_DEVREADWRITE("ppi8255_2", i8255_device, read, write) /* Input/Output Ports */
314	314
315	315	AM_RANGE(0xf630, 0xf630) AM_DEVREADWRITE("aysnd", ay8910_device, data_r, data_w)
316	316	AM_RANGE(0xf640, 0xf640) AM_DEVWRITE("aysnd", ay8910_device, address_w)
317		AM_RANGE(0xf650, 0xf650) AM_WRITENOP // AM_WRITE(output_w) // unknown register: 0x3e
318		AM_RANGE(0xf660, 0xf660) AM_WRITENOP // AM_WRITE(output_w) // unknown register: 0x3e
	317	AM_RANGE(0xf650, 0xf650) AM_WRITENOP // AM_WRITE(output_w) // unknown register: 0x3e
	318	AM_RANGE(0xf660, 0xf660) AM_WRITENOP // AM_WRITE(output_w) // unknown register: 0x3e
319	319	AM_RANGE(0xf670, 0xf670) AM_DEVWRITE("snsnd", sn76489_device, write) /* guess... device is initialized, but doesn't seems to be used.*/
320	320
321	321	AM_RANGE(0xf800, 0xffff) AM_RAM
r29404	r29405
1714	1714
1715	1715	static INPUT_PORTS_START( goldstar )
1716	1716	PORT_START("IN0")
1717		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // appear in the input test but seems that lack of functions.
1718		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // appear in the input test but seems that lack of functions.
	1717	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // appear in the input test but seems that lack of functions.
	1718	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // appear in the input test but seems that lack of functions.
1719	1719	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V) PORT_NAME("Bet Red / 2")
1720	1720	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SLOT_STOP3 ) PORT_CODE(KEYCODE_C) PORT_NAME("Stop 3 / Small / 1 / Info")
1721	1721	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B) PORT_NAME("Bet Blue / D-UP / 3")
r29404	r29405
6507	6507	/* basic machine hardware */
6508	6508	MCFG_CPU_ADD("maincpu", Z80, CPU_CLOCK)
6509	6509	MCFG_CPU_PROGRAM_MAP(goldstar_map)
6510		// MCFG_CPU_PROGRAM_MAP(nfm_map)
	6510	// MCFG_CPU_PROGRAM_MAP(nfm_map)
6511	6511	MCFG_CPU_IO_MAP(goldstar_readport)
6512		// MCFG_CPU_IO_MAP(unkch_portmap)
	6512	// MCFG_CPU_IO_MAP(unkch_portmap)
6513	6513	MCFG_CPU_VBLANK_INT_DRIVER("screen", goldstar_state, irq0_line_hold)
6514	6514
6515	6515	/* video hardware */
r29404	r29405
7703	7703	ROM_CONTINUE( 0x0000, 0x08000) /* Discarding 2nd quarter 0xff filled*/
7704	7704	ROM_CONTINUE( 0x0000, 0x08000) /* Discarding 3nd quarter 0xff filled*/
7705	7705
7706		ROM_REGION( 0x40000, "oki", 0 ) // Audio ADPCM
	7706	ROM_REGION( 0x40000, "oki", 0 ) // Audio ADPCM
7707	7707	ROM_LOAD( "27c1000.u57", 0x0000, 0x20000, CRC(9d58960f) SHA1(c68edf95743e146398aabf6b9617d18e1f9bf25b) )
7708	7708	ROM_END
7709	7709
7710	7710
7711	7711	/*
7712		Super Nove by Playmark
7713
7714		bp 2db
7715		the next call ($0C33) hangs the game
7716		since there are ascii strings there
7717		instead of code.
7718
	7712	Super Nove by Playmark
	7713
	7714	bp 2db
	7715	the next call ($0C33) hangs the game
	7716	since there are ascii strings there
	7717	instead of code.
	7718
7719	7719	*/
7720	7720	ROM_START( super9 )
7721	7721	ROM_REGION( 0x10000, "maincpu", 0 )
7722	7722	ROM_LOAD( "27e010.30", 0x0000, 0x10000, CRC(1aaea8d3) SHA1(71395a6d74a7cd55606daa57d17ff4628aa5f577) )
7723		ROM_IGNORE( 0x10000) /* Discarding 2nd half */
7724		// ROM_LOAD( "27e010.30", 0x0000, 0x10000, CRC(1aaea8d3) SHA1(71395a6d74a7cd55606daa57d17ff4628aa5f577) )
7725		// ROM_CONTINUE( 0x0000, 0x10000) /* Discarding 1st half */
7726
	7723	ROM_IGNORE( 0x10000) /* Discarding 2nd half */
	7724	// ROM_LOAD( "27e010.30", 0x0000, 0x10000, CRC(1aaea8d3) SHA1(71395a6d74a7cd55606daa57d17ff4628aa5f577) )
	7725	// ROM_CONTINUE( 0x0000, 0x10000) /* Discarding 1st half */
	7726
7727	7727	ROM_REGION( 0x20000, "gfx1", 0 )
7728	7728	ROM_LOAD( "nearcpu.bin", 0x00000, 0x20000, CRC(643cff6f) SHA1(305ca9182c3f6d69e09be38b854b3d7bdfa75439) )
7729	7729
r29404	r29405
7732	7732	ROM_CONTINUE( 0x0000, 0x08000) // Discarding 1nd quarter 0xff filled
7733	7733	ROM_CONTINUE( 0x0000, 0x08000) // Discarding 2nd quarter 0xff filled
7734	7734	ROM_CONTINUE( 0x0000, 0x08000) // Discarding 3nd quarter 0xff filled
7735
	7735
7736	7736	ROM_REGION( 0x40000, "oki", 0 ) /* Audio ADPCM */
7737	7737	ROM_LOAD( "27c1001.27", 0x0000, 0x20000, CRC(9d58960f) SHA1(c68edf95743e146398aabf6b9617d18e1f9bf25b) )
7738	7738	ROM_END
r29404	r29405
7872	7872	ROM_LOAD( "4.5h", 0x06000, 0x02000, CRC(cbcc6bfb) SHA1(5bafc934fef1f50d8c182c39d3a7ce795c89d175) )
7873	7873
7874	7874	ROM_REGION( 0x0200, "proms", 0 )
7875		ROM_LOAD_NIB_LOW( "n82s129.13g", 0x0000, 0x0100, CRC(59ac98e4) SHA1(5fc0f1a48c49c956cdb8826e20663dc57a9175e4) ) // 1st bank colors, low 4 bits.
7876		ROM_LOAD_NIB_HIGH( "n82s129.14g", 0x0000, 0x0100, CRC(0d8f35bd) SHA1(0c2a0145cdaaf9beabdce241731a36b0c65f18a2) ) // 1st bank colors, high 4 bits.
7877		ROM_LOAD( "dm74s288.13d", 0x0080, 0x0020, CRC(77a85e21) SHA1(3b41e0ab7cc55c5d78914d23e8289383f5bd5654) ) // 2nd bank colors
	7875	ROM_LOAD_NIB_LOW( "n82s129.13g", 0x0000, 0x0100, CRC(59ac98e4) SHA1(5fc0f1a48c49c956cdb8826e20663dc57a9175e4) ) // 1st bank colors, low 4 bits.
	7876	ROM_LOAD_NIB_HIGH( "n82s129.14g", 0x0000, 0x0100, CRC(0d8f35bd) SHA1(0c2a0145cdaaf9beabdce241731a36b0c65f18a2) ) // 1st bank colors, high 4 bits.
	7877	ROM_LOAD( "dm74s288.13d", 0x0080, 0x0020, CRC(77a85e21) SHA1(3b41e0ab7cc55c5d78914d23e8289383f5bd5654) ) // 2nd bank colors
7878	7878	ROM_END
7879	7879
7880	7880
r29404	r29405
7885	7885	5x 8 DIP switches.
7886	7886	1x 12 MHz xtal.
7887	7887
7888		ROM 3v202 is the prg.
	7888	ROM 3v202 is the prg.
7889	7889	*/
7890	7890	ROM_START( cb3e )
7891	7891	ROM_REGION( 0x10000, "maincpu", 0 )
r29404	r29405
7899	7899
7900	7900	ROM_REGION( 0x0200, "proms", 0 )
7901	7901	ROM_LOAD( "82s147.u1", 0x00000, 0x0100, CRC(d4eaa276) SHA1(b6598ee64ac3d41ca979c8667de8576cfb304451) )
7902		ROM_CONTINUE( 0x00000, 0x0100) // 2nd half has the data.
	7902	ROM_CONTINUE( 0x00000, 0x0100) // 2nd half has the data.
7903	7903	ROM_END
7904	7904
7905	7905
r29404	r29405
11614	11614	ROM_LOAD( "wincherrya.ic9", 0x00000, 0x08000, CRC(919bd692) SHA1(1aeb66f1e4555b731858833445000593e613f74d) )
11615	11615
11616	11616	ROM_REGION( 0x0200, "proms", 0 )
11617		ROM_LOAD( "am27c29pc", 0x00000, 0x0200, BAD_DUMP CRC(5c8f2b8f) SHA1(67d2121e75813dd85d83858c5fc5ec6ad9cc2a7d) ) // borrowed from other game.
	11617	ROM_LOAD( "am27c29pc", 0x00000, 0x0200, BAD_DUMP CRC(5c8f2b8f) SHA1(67d2121e75813dd85d83858c5fc5ec6ad9cc2a7d) ) // borrowed from other game.
11618	11618	ROM_END
11619	11619
11620	11620
r29404	r29405
12259	12259	UINT8 *src = memregion("gfx1")->base();
12260	12260	for (i = 0;i < 0x20000;i++)
12261	12261	{
12262		// src[i] = BITSWAP8(src[i], 7,4,2,1,6,5,3,0);
12263		// src[i] = BITSWAP8(src[i], 7,3,2,6,1,5,4,0);
	12262	// src[i] = BITSWAP8(src[i], 7,4,2,1,6,5,3,0);
	12263	// src[i] = BITSWAP8(src[i], 7,3,2,6,1,5,4,0);
12264	12264	src[i] = BITSWAP8(src[i], 7,3,2,6,5,1,4,0);
12265	12265	}
12266	12266
12267	12267	UINT8 *src2 = memregion("gfx2")->base();
12268	12268	for (i = 0;i < 0x8000;i++)
12269	12269	{
12270		// src2[i] = BITSWAP8(src2[i], 7,4,2,1,6,5,3,0);
12271		// src2[i] = BITSWAP8(src2[i], 7,3,2,6,1,5,4,0);
12272		src2[i] = BITSWAP8(src2[i], 3,7,6,2,5,1,0,4); // endianess
	12270	// src2[i] = BITSWAP8(src2[i], 7,4,2,1,6,5,3,0);
	12271	// src2[i] = BITSWAP8(src2[i], 7,3,2,6,1,5,4,0);
	12272	src2[i] = BITSWAP8(src2[i], 3,7,6,2,5,1,0,4); // endianess
12273	12273	}
12274	12274
12275	12275	}
r29404	r29405
12289	12289	}
12290	12290
12291	12291	/* bank 1 graphics */
12292		// int i;
	12292	// int i;
12293	12293	UINT8 *src = memregion("gfx1")->base();
12294	12294	for (i = 0; i < 0x20000; i++)
12295	12295	{
12296		src[i] = BITSWAP8(src[i], 4, 3, 2, 5, 1, 6, 0, 7); // OK
	12296	src[i] = BITSWAP8(src[i], 4, 3, 2, 5, 1, 6, 0, 7); // OK
12297	12297	}
12298	12298
12299	12299	/* bank 2 graphics */
12300	12300	UINT8 *src2 = memregion("gfx2")->base();
12301	12301	for (i = 0; i < 0x8000; i++)
12302	12302	{
12303		src2[i] = BITSWAP8(src2[i], 3, 4, 2, 5, 1, 6, 0, 7); // OK
	12303	src2[i] = BITSWAP8(src2[i], 3, 4, 2, 5, 1, 6, 0, 7); // OK
12304	12304	}
12305	12305	}
12306	12306
r29404	r29405
12311	12311	UINT8 *src = memregion("gfx1")->base();
12312	12312	for (i = 0; i < 0x20000; i++)
12313	12313	{
12314		src[i] = BITSWAP8(src[i], 4, 3, 2, 5, 1, 6, 0, 7); // OK
	12314	src[i] = BITSWAP8(src[i], 4, 3, 2, 5, 1, 6, 0, 7); // OK
12315	12315	}
12316	12316
12317	12317	/* bank 2 graphics */
12318	12318	UINT8 *src2 = memregion("gfx2")->base();
12319	12319	for (i = 0; i < 0x8000; i++)
12320	12320	{
12321		src2[i] = BITSWAP8(src2[i], 3, 4, 2, 5, 1, 6, 0, 7); // OK
	12321	src2[i] = BITSWAP8(src2[i], 3, 4, 2, 5, 1, 6, 0, 7); // OK
12322	12322	}
12323	12323	}
12324	12324
r29404	r29405
12333	12333	GAME( 199?, moonlght, goldstar, moonlght, goldstar, driver_device, 0, ROT0, "bootleg", "Moon Light (bootleg of Golden Star)", 0 )
12334	12334	GAME( 199?, chrygld, 0, chrygld, chrygld, goldstar_state, chrygld, ROT0, "bootleg", "Cherry Gold I", 0 )
12335	12335	GAME( 199?, chry10, 0, chrygld, chry10, goldstar_state, chry10, ROT0, "bootleg", "Cherry 10 (bootleg with PIC16F84)", 0 )
12336		GAME( 199?, goldfrui, goldstar, goldfrui, goldstar, driver_device, 0, ROT0, "bootleg", "Gold Fruit", 0 ) // maybe fullname should be 'Gold Fruit (main 40%)'
12337		GAME( 2001, super9, goldstar, super9, goldstar, goldstar_state, super9, ROT0, "Playmark", "Super Nove (Playmark)", GAME_NOT_WORKING) // need to decode gfx and see the program loops/reset...
	12336	GAME( 199?, goldfrui, goldstar, goldfrui, goldstar, driver_device, 0, ROT0, "bootleg", "Gold Fruit", 0 ) // maybe fullname should be 'Gold Fruit (main 40%)'
	12337	GAME( 2001, super9, goldstar, super9, goldstar, goldstar_state, super9, ROT0, "Playmark", "Super Nove (Playmark)", GAME_NOT_WORKING) // need to decode gfx and see the program loops/reset...
12338	12338	GAME( 2001, wcherry, 0, wcherry, chrygld, goldstar_state, wcherry, ROT0, "bootleg", "Win Cherry (ver 0.16 - 19990219)", GAME_NOT_WORKING)
12339	12339
12340	12340

trunk/src/mame/drivers/20pacgal.c
r29404	r29405
206	206	// likewise the sound table.. is it being uploaded in a different format at 0x0c000?
207	207	// we also need the palette data because there is only a single rom on this pcb?
208	208	static ADDRESS_MAP_START( 25pacman_map, AS_PROGRAM, 8, _25pacman_state )
209
	209
210	210	AM_RANGE(0x04000, 0x047ff) AM_RAM AM_SHARE("video_ram")
211	211
212	212	AM_RANGE(0x04800, 0x05fff) AM_RAM
213	213
214	214	AM_RANGE(0x06000, 0x06fff) AM_WRITEONLY AM_SHARE("char_gfx_ram")
215	215	AM_RANGE(0x07000, 0x0717f) AM_WRITE(sprite_ram_w)
216		// AM_RANGE(0x08000, 0x09fff) AM_READ_BANK("bank1") AM_WRITE(ram_48000_w)
	216	// AM_RANGE(0x08000, 0x09fff) AM_READ_BANK("bank1") AM_WRITE(ram_48000_w)
217	217	AM_RANGE(0x08000, 0x09fff) AM_WRITENOP
218	218	AM_RANGE(0x0a000, 0x0bfff) AM_WRITE(sprite_gfx_w)
219	219
r29404	r29405
270	270	AM_RANGE(0x85, 0x86) AM_WRITEONLY AM_SHARE("stars_seed") /* stars: rng seed (lo/hi) */
271	271	AM_RANGE(0x87, 0x87) AM_READ( _25pacman_io_87_r ) // not eeprom on this
272	272	AM_RANGE(0x87, 0x87) AM_WRITENOP
273		// AM_RANGE(0x88, 0x88) AM_WRITE(ram_bank_select_w)
	273	// AM_RANGE(0x88, 0x88) AM_WRITE(ram_bank_select_w)
274	274	AM_RANGE(0x89, 0x89) AM_DEVWRITE("dac", dac_device, write_signed8)
275	275	AM_RANGE(0x8a, 0x8a) AM_WRITEONLY AM_SHARE("stars_ctrl") /* stars: bits 3-4 = active set; bit 5 = enable */
276	276	AM_RANGE(0x8b, 0x8b) AM_WRITEONLY AM_SHARE("flip")

trunk/src/mame/drivers/seicross.c
r29404	r29405
52	52
53	53	void seicross_state::nvram_init(nvram_device &nvram, void *data, size_t size)
54	54	{
55		static const UINT8 init[32] = {
	55	static const UINT8 init[32] = {
56	56	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
57	57	0, 1, 0, 1, 0, 1, 0, 3, 0, 1, 0, 0, 0, 0, 0, 0, };
58
	58
59	59	memset(data, 0x00, size);
60	60	memcpy(data, init, sizeof(init));
61	61	}

trunk/src/mame/drivers/system16.c
r29404	r29405
2025	2025
2026	2026	/* sound hardware */
2027	2027	MCFG_SOUND_ADD("7759", UPD7759, UPD7759_STANDARD_CLOCK)
2028		MCFG_UPD7759_DRQ_CALLBACK(WRITELINE(segas1x_bootleg_state,sound_cause_nmi))
	2028	MCFG_UPD7759_DRQ_CALLBACK(WRITELINE(segas1x_bootleg_state,sound_cause_nmi))
2029	2029	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.48)
2030	2030	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.48)
2031	2031	MACHINE_CONFIG_END

trunk/src/mame/drivers/nyny.c
r29404	r29405
121	121	required_device<mc6845_device> m_mc6845;
122	122	required_device<pia6821_device> m_pia1;
123	123	required_device<pia6821_device> m_pia2;
124
	124
125	125	pen_t m_pens[NUM_PENS];
126	126	DECLARE_WRITE8_MEMBER(audio_1_command_w);
127	127	DECLARE_WRITE8_MEMBER(audio_1_answer_w);

trunk/src/mame/drivers/big10.c
r29404	r29405
159	159	static INPUT_PORTS_START( big10 )
160	160
161	161	PORT_START("SYSTEM")
162		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_TOGGLE /* Service Mode */
	162	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_TOGGLE /* Service Mode */
163	163	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_CODE(KEYCODE_R) PORT_NAME("Reset")
164	164	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) PORT_NAME("Payout")
165	165	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
166		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // in test mode, go to the game whilst keep pressed.
167		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // in test mode, go to the game whilst keep pressed.
	166	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // in test mode, go to the game whilst keep pressed.
	167	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // in test mode, go to the game whilst keep pressed.
168	168	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
169	169	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2)
170	170

trunk/src/mame/drivers/stuntair.c
r29404	r29405
93	93	m_bgattrram(*this, "bgattrram"),
94	94	m_sprram(*this, "sprram"),
95	95	m_gfxdecode(*this, "gfxdecode"),
96		m_palette(*this, "palette")
	96	m_palette(*this, "palette")
97	97	{ }
98	98
99	99	required_device<cpu_device> m_maincpu;

trunk/src/mame/drivers/model1.c
r29404	r29405
1521	1521	MCFG_NVRAM_ADD_0FILL("nvram")
1522	1522
1523	1523	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1524
	1524
1525	1525	MCFG_S24TILE_DEVICE_ADD("tile", 0x3fff)
1526	1526	MCFG_S24TILE_DEVICE_GFXDECODE("gfxdecode")
1527	1527	MCFG_S24TILE_DEVICE_PALETTE("palette")
r29404	r29405
1565	1565	MCFG_NVRAM_ADD_0FILL("nvram")
1566	1566
1567	1567	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1568
	1568
1569	1569	MCFG_S24TILE_DEVICE_ADD("tile", 0x3fff)
1570	1570	MCFG_S24TILE_DEVICE_GFXDECODE("gfxdecode")
1571	1571	MCFG_S24TILE_DEVICE_PALETTE("palette")

trunk/src/mame/drivers/taito_b.c
r29404	r29405
1983	1983	MCFG_GFXDECODE_ADD("gfxdecode", "palette", taito_b)
1984	1984	MCFG_PALETTE_ADD("palette", 4096)
1985	1985	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
1986
	1986
1987	1987	MCFG_VIDEO_START_OVERRIDE(taitob_state,taitob_color_order0)
1988	1988
1989	1989	MCFG_TC0180VCU_ADD("tc0180vcu", color0_tc0180vcu_intf)
r29404	r29405
2059	2059
2060	2060	MCFG_CPU_MODIFY("maincpu")
2061	2061	MCFG_CPU_PROGRAM_MAP(tetrist_map)
2062
	2062
2063	2063	MCFG_PALETTE_MODIFY("palette")
2064	2064	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
2065	2065	MACHINE_CONFIG_END
r29404	r29405
2354	2354	MCFG_TC0640FIO_READ_2_CB(IOPORT("START"))
2355	2355	MCFG_TC0640FIO_READ_3_CB(IOPORT("P1_P2_A"))
2356	2356	MCFG_TC0640FIO_READ_7_CB(IOPORT("P1_P2_B"))
2357
	2357
2358	2358	MCFG_DEVICE_ADD("mb87078", MB87078, 0)
2359	2359	MCFG_MB87078_GAIN_CHANGED_CB(WRITE8(taitob_state, mb87078_gain_changed))
2360	2360
r29404	r29405
2798	2798	MCFG_TC0510NIO_READ_2_CB(IOPORT("JOY"))
2799	2799	MCFG_TC0510NIO_READ_3_CB(IOPORT("START"))
2800	2800	MCFG_TC0510NIO_READ_7_CB(IOPORT("PHOTOSENSOR"))
2801
	2801
2802	2802	/* video hardware */
2803	2803	MCFG_SCREEN_ADD("screen", RASTER)
2804	2804	MCFG_SCREEN_REFRESH_RATE(60)
r29404	r29405
2854	2854	MCFG_TC0510NIO_READ_2_CB(IOPORT("IN0"))
2855	2855	MCFG_TC0510NIO_READ_3_CB(IOPORT("IN1"))
2856	2856	MCFG_TC0510NIO_READ_7_CB(IOPORT("IN2"))
2857
	2857
2858	2858	/* video hardware */
2859	2859	MCFG_SCREEN_ADD("screen", RASTER)
2860	2860	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mame/drivers/btime.c
r29404	r29405
1319	1319	MCFG_MACHINE_RESET_OVERRIDE(btime_state,btime)
1320	1320
1321	1321	MCFG_GFXDECODE_ADD("gfxdecode", "palette", btime)
1322
	1322
1323	1323	MCFG_PALETTE_ADD("palette", 16)
1324	1324	MCFG_PALETTE_INIT_OWNER(btime_state,btime)
1325	1325	MCFG_PALETTE_FORMAT(BBGGGRRR)

trunk/src/mame/drivers/m14.c
r29404	r29405
77	77	/* devices */
78	78	required_device<cpu_device> m_maincpu;
79	79	required_device<gfxdecode_device> m_gfxdecode;
80
	80
81	81	DECLARE_WRITE8_MEMBER(m14_vram_w);
82	82	DECLARE_WRITE8_MEMBER(m14_cram_w);
83	83	DECLARE_READ8_MEMBER(m14_rng_r);
r29404	r29405
346	346	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 08, 288-1)
347	347	MCFG_SCREEN_UPDATE_DRIVER(m14_state, screen_update_m14)
348	348	MCFG_SCREEN_PALETTE("palette")
349
	349
350	350	MCFG_GFXDECODE_ADD("gfxdecode", "palette", m14)
351	351	MCFG_PALETTE_ADD("palette", 0x20)
352	352	MCFG_PALETTE_INIT_OWNER(m14_state, m14)

trunk/src/mame/drivers/cps1.c
r29404	r29405
951	951	PORT_DIPSETTING( 0x30, "30K, 60K and every 70K" )
952	952	PORT_DIPSETTING( 0x00, "40K, 70K and every 80K" )
953	953	/* Manuals states the following bonus settings
954		PORT_DIPSETTING( 0x20, "20K, 50K and every 70K" )
955		PORT_DIPSETTING( 0x10, "10K, 30K and every 30K" )
956		PORT_DIPSETTING( 0x30, "40K, 70K and every 80K" )
957		PORT_DIPSETTING( 0x00, "30K, 60K and every 70K" )
	954	PORT_DIPSETTING( 0x20, "20K, 50K and every 70K" )
	955	PORT_DIPSETTING( 0x10, "10K, 30K and every 30K" )
	956	PORT_DIPSETTING( 0x30, "40K, 70K and every 80K" )
	957	PORT_DIPSETTING( 0x00, "30K, 60K and every 70K" )
958	958	*/
959	959	/* Debug Dip Switches */
960	960	PORT_DIPNAME( 0x07, 0x07, "Starting Weapon" ) PORT_CONDITION("DSWC", 0x80, EQUALS, 0x00) PORT_DIPLOCATION("SW(B):1,2,3")
r29404	r29405
1077	1077	PORT_DIPSETTING( 0x20, "30K, 50K then every 70K" )
1078	1078	PORT_DIPSETTING( 0x10, "20K & 60K only" )
1079	1079	PORT_DIPSETTING( 0x00, "30K & 60K only" )
1080		/* According to manual, these are the proper settings
1081		PORT_DIPSETTING( 0x30, "40K, 70K then every 80K" )
1082		PORT_DIPSETTING( 0x20, "20K, 50K then every 70K" )
1083		PORT_DIPSETTING( 0x10, "10k, 30k then every 30k" )
1084		PORT_DIPSETTING( 0x00, "30K, 60k then every 70k" )
	1080	/* According to manual, these are the proper settings
	1081	PORT_DIPSETTING( 0x30, "40K, 70K then every 80K" )
	1082	PORT_DIPSETTING( 0x20, "20K, 50K then every 70K" )
	1083	PORT_DIPSETTING( 0x10, "10k, 30k then every 30k" )
	1084	PORT_DIPSETTING( 0x00, "30K, 60k then every 70k" )
1085	1085	*/
1086	1086
1087	1087	PORT_DIPNAME( 0xc0, 0x80, "Internal Diff. on Life Loss" ) PORT_DIPLOCATION("SW(B):7,8")
r29404	r29405
8633	8633	Original 88622-c-2 C board
8634	8634
8635	8635	Bootleg B board with
8636		PIC16c55 near PRG roms seem protected
8637		8 dipswith near both sound roms and gfx roms
8638		1,4,5,8 ON
8639		2,3,6,7 OFF
	8636	PIC16c55 near PRG roms seem protected
	8637	8 dipswith near both sound roms and gfx roms
	8638	1,4,5,8 ON
	8639	2,3,6,7 OFF
8640	8640
8641	8641	Sound rom match various romset
8642	8642	*/
r29404	r29405
8652	8652	ROM_LOAD16_BYTE( "prg34.bin", 0x80001, 0x20000, CRC(f06a12f2) SHA1(ddc431ce01392d4a7562760743abd9ea73b06cf3) )
8653	8653	ROM_LOAD16_BYTE( "prg28.bin", 0xc0000, 0x40000, CRC(b7ad5214) SHA1(17b05e0aa9a4eb5f1aaafe35fa029d2a9aea530d) )
8654	8654	ROM_LOAD16_BYTE( "prg33.bin", 0xc0001, 0x40000, CRC(6340b914) SHA1(443e37a06058548c8ce7a15ecd10a6635e69d09f) )
8655
	8655
8656	8656	ROM_REGION( 0x600000, "gfx", 0 )
8657	8657	ROMX_LOAD( "24.bin", 0x000000, 0x40000, CRC(a8b5633a) SHA1(6548a89d616910d06db126eb1a9c6b5979baff03) , ROM_SKIP(7) )
8658	8658	ROMX_LOAD( "14.bin", 0x000001, 0x40000, CRC(5db24ca7) SHA1(0543e89174fecc866a08e0ecc7c31a6efca15da5) , ROM_SKIP(7) )
r29404	r29405
8688	8688	ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
8689	8689	ROM_LOAD( "s92_18.bin", 0x00000, 0x20000, CRC(7f162009) SHA1(346bf42992b4c36c593e21901e22c87ae4a7d86d) )
8690	8690	ROM_LOAD( "s92_19.bin", 0x20000, 0x20000, CRC(beade53f) SHA1(277c397dc12752719ec6b47d2224750bd1c07f79) )
8691
8692		ROM_REGION( 0x2000, "protectin_pic", 0 )
	8691
	8692	ROM_REGION( 0x2000, "protectin_pic", 0 )
8693	8693	ROM_LOAD( "pic16c55", 0x00000, 0x2000, BAD_DUMP CRC(f22e2311) SHA1(320edfba140728599e91c01e863a8b6d071e4bbf) )
8694	8694	ROM_END
8695	8695

trunk/src/mame/drivers/vp101.c
r29404	r29405
93	93	MCFG_SCREEN_SIZE(320, 240)
94	94	MCFG_SCREEN_VISIBLE_AREA(0, 319, 0, 239)
95	95	MCFG_SCREEN_PALETTE("palette")
96
	96
97	97	MCFG_PALETTE_ADD("palette", 32768)
98	98	MACHINE_CONFIG_END
99	99

trunk/src/mame/drivers/scobra.c
r29404	r29405
1273	1273
1274	1274	ROM_REGION( 0x0020, "proms", 0 )
1275	1275	ROM_LOAD( "mni6331.e6", 0x0000, 0x0020, CRC(aa1f7f5e) SHA1(311dd17aa11490a1173c76223e4ccccf8ea29850) )
1276
	1276
1277	1277	ROM_REGION( 0x0800, "unk", 0 )
1278	1278	ROM_LOAD( "top.c5", 0x0000, 0x0800, CRC(88226086) SHA1(fe2da172313063e5b056fc8c8d8b2a5c64db5179) )
1279		ROM_END
	1279	ROM_END
1280	1280	ROM_START( mimonkey )
1281	1281	ROM_REGION( 0x10000, "maincpu", 0 )
1282	1282	ROM_LOAD( "mm1.2e", 0x0000, 0x1000, CRC(9019f1b1) SHA1(0c45f64e39b9a182f6162ab520ced6ef0686466c) )

trunk/src/mame/drivers/galaxian.c
r29404	r29405
7001	7001	ROM_LOAD( "gal09.ic13", 0x2400, 0x0400, CRC(5876f695) SHA1(e8c0d13066cfe4a409293b9e1380513099b35330) )
7002	7002
7003	7003	ROM_REGION( 0x0400, "unknown", 0 )
7004		ROM_LOAD( "gal00eg.ic4", 0x0000, 0x0400, CRC(1038467f) SHA1(e34cc53a1203335cf9c9a94c3f96cab5a444a34a) ) // the first 0x100 bytes of this is ic41, the rest is different? should it bank in somehow to give extra features??
7005
	7004	ROM_LOAD( "gal00eg.ic4", 0x0000, 0x0400, CRC(1038467f) SHA1(e34cc53a1203335cf9c9a94c3f96cab5a444a34a) ) // the first 0x100 bytes of this is ic41, the rest is different? should it bank in somehow to give extra features??
	7005
7006	7006	ROM_REGION( 0x1000, "gfx1", 0 )
7007	7007	ROM_LOAD( "galaxian.1h", 0x0000, 0x0800, CRC(39fb43a4) SHA1(4755609bd974976f04855d51e08ec0d62ab4bc07) )
7008	7008	ROM_LOAD( "galaxian.1k", 0x0800, 0x0800, CRC(7e3f56a2) SHA1(a9795d8b7388f404f3b0e2c6ce15d713a4c5bafa) )

trunk/src/mame/drivers/othello.c
r29404	r29405
81	81	mc6845_device *m_mc6845;
82	82	device_t *m_n7751;
83	83	required_device<palette_device> m_palette;
84
	84
85	85	DECLARE_READ8_MEMBER(unk_87_r);
86	86	DECLARE_WRITE8_MEMBER(unk_8a_w);
87	87	DECLARE_WRITE8_MEMBER(unk_8c_w);

trunk/src/mame/drivers/calomega.c
r29404	r29405
2682	2682	MCFG_SOUND_CONFIG(sys905_ay8912_intf)
2683	2683
2684	2684	MCFG_DEVICE_REMOVE("acia6850_0")
2685
	2685
2686	2686	MCFG_DEVICE_REMOVE("aciabaud")
2687	2687	MACHINE_CONFIG_END
2688	2688
r29404	r29405
2706	2706	MCFG_SOUND_CONFIG(sys905_ay8912_intf)
2707	2707
2708	2708	MCFG_DEVICE_REMOVE("acia6850_0")
2709
	2709
2710	2710	MCFG_DEVICE_REMOVE("aciabaud")
2711	2711	MACHINE_CONFIG_END
2712	2712
r29404	r29405
2738	2738	MCFG_SOUND_CONFIG(sys906_ay8912_intf)
2739	2739
2740	2740	MCFG_DEVICE_REMOVE("acia6850_0")
2741
	2741
2742	2742	MCFG_DEVICE_REMOVE("aciabaud")
2743	2743	MACHINE_CONFIG_END
2744	2744
r29404	r29405
3879	3879	BPR[x] = 0x04; /* blue background */
3880	3880	}
3881	3881	m_palette->update();
3882
	3882
3883	3883	/* Injecting missing Start and NMI vectors...
3884	3884	Start = $2042; NMI = $26f8;
3885	3885	Also a fake vector at $3ff8-$3ff9. The code checks these values to continue.

trunk/src/mame/drivers/gstream.c
r29404	r29405
1	1	/********************************************************************
2	2
3	3	G-Stream (c)2002 Oriental Soft Japan
4		X2222 (prototype) (c)2000 Oriental Soft
	4	X2222 (prototype) (c)2000 Oriental Soft
5	5
6		---
7		X2222 has corrupt boss graphics because the program roms we use don't match the sprite roms.
8		--
	6	---
	7	X2222 has corrupt boss graphics because the program roms we use don't match the sprite roms.
	8	--
9	9
10	10	Hyperstone based hardware
11	11
12	12	Simple Sprites (16x16x8bpp tiles)
13	13	3 Simple Tilemaps (32x32x8bpp tiles)
14	14
15		X2222 uses raw 16bpp palette data instead of 8bpp indexed colours.
	15	X2222 uses raw 16bpp palette data instead of 8bpp indexed colours.
16	16
17	17	todo: sprite lag (sprites need buffering?)
18	18	sprite wraparound is imperfect
19	19
20	20	The following is confirmed on G-Stream only
21		---
	21	---
22	22
23	23	CPU: E1-32XT
24	24	Sound: 2x AD-65 (OKIM6295 clone)
r29404	r29405
41	41	---
42	42
43	43	Dump Notes:::
44
	44
45	45	G-Stream 2020, 2002 Oriental Soft Japan
46	46
47	47	Shooter from Oriental soft, heavy influence from XII Stag
r29404	r29405
146	146	m_workram(*this, "workram"),
147	147	m_vram(*this, "vram"),
148	148	m_gfxdecode(*this, "gfxdecode"),
149		m_palette(*this, "palette")
	149	m_palette(*this, "palette")
150	150	{
151	151	m_toggle = 0;
152	152	}
r29404	r29405
172	172	/* misc */
173	173	int m_oki_bank_1;
174	174	int m_oki_bank_2;
175		int m_toggle;
176		int m_xoffset;
	175	int m_toggle;
	176	int m_xoffset;
177	177
178	178	DECLARE_WRITE32_MEMBER(gstream_vram_w);
179	179	DECLARE_WRITE32_MEMBER(gstream_tilemap1_scrollx_w);
r29404	r29405
201	201
202	202	void rearrange_sprite_data(UINT8* ROM, UINT32* NEW, UINT32* NEW2);
203	203	void rearrange_tile_data(UINT8* ROM, UINT32* NEW, UINT32* NEW2);
204
	204
205	205	required_device<gfxdecode_device> m_gfxdecode;
206	206	required_device<palette_device> m_palette;
207	207	};
r29404	r29405
599	599	code %= gfx->elements();
600	600
601	601	// render
602
	602
603	603	do {
604	604	g_profiler.start(PROFILER_DRAWGFX);
605	605	do {
606
607	606	const UINT8 srcdata, srcdata2;
608	607	INT32 destendx, destendy;
609	608	INT32 srcx, srcy;
r29404	r29405
695	694	{
696	695	UINT32 srcdata = (srcptr[0]);
697	696	UINT32 srcdata2 = (srcptr2[0]);
698
	697
699	698	UINT32 fullval = (srcdata \| (srcdata2 << 8));
700	699	UINT32 r = ((fullval >> 0) & 0x1f) << 3;
701	700	UINT32 g = ((fullval >> 5) & 0x3f) << 2;
r29404	r29405
703	702	UINT32 full = (r << 16) \| (g << 8) \| (b << 0);
704	703	if (full != 0)
705	704	destptr[0] = full;
706
	705
707	706	srcptr++;
708	707	srcptr2++;
709	708	destptr++;
r29404	r29405
729	728	{
730	729	UINT32 srcdata = (srcptr[0]);
731	730	UINT32 srcdata2 = (srcptr2[0]);
732
	731
733	732	UINT32 fullval = (srcdata \| (srcdata2 << 8));
734	733	UINT32 r = ((fullval >> 0) & 0x1f) << 3;
735	734	UINT32 g = ((fullval >> 5) & 0x3f) << 2;
r29404	r29405
737	736	UINT32 full = (r << 16) \| (g << 8) \| (b << 0);
738	737	if (full != 0)
739	738	destptr[0] = full;
740
	739
741	740	srcptr--;
742	741	srcptr2--;
743	742	destptr++;
r29404	r29405
766	765	int vram_data = (ram[(basex&0x0f)+((basey&0x0f)*0x10)]);
767	766	int pal = (vram_data & 0xc0000000) >> 30;
768	767	int code = (vram_data & 0x0fff0000) >> 16;
769
	768
770	769	pal += palbase;
771	770
772	771	if (m_gfxdecode->gfx(map+5))
r29404	r29405
806	805
807	806
808	807	draw_bg_gstream(bitmap, cliprect, m_tmap3_scrollx >> 16, m_tmap3_scrolly >> 16, 2, m_vram + 0x800/4, 0x18);
809		draw_bg_gstream(bitmap, cliprect, m_tmap2_scrollx >> 16, m_tmap2_scrolly >> 16, 1, m_vram + 0x400/4, 0x14);
	808	draw_bg_gstream(bitmap, cliprect, m_tmap2_scrollx >> 16, m_tmap2_scrolly >> 16, 1, m_vram + 0x400/4, 0x14);
810	809	draw_bg_gstream(bitmap, cliprect, m_tmap1_scrollx >> 16, m_tmap1_scrolly >> 16, 0, m_vram + 0x000/4, 0x10); // move on top for x2222 , check
811	810
812	811
r29404	r29405
907	906	MCFG_CPU_VBLANK_INT_DRIVER("screen", gstream_state, irq0_line_hold)
908	907
909	908
910		// MCFG_NVRAM_ADD_1FILL("nvram")
	909	// MCFG_NVRAM_ADD_1FILL("nvram")
911	910
912	911	/* video hardware */
913	912	MCFG_SCREEN_ADD("screen", RASTER)
r29404	r29405
979	978
980	979	ROM_REGION32_BE( 0x0200000, "misc", 0 ) /* other code */
981	980	ROM_LOAD( "test.hye", 0x000000, 0x0112dda, CRC(c1142b2f) SHA1(5807930820a53604013a6ac66e4d4ebe3628e1fc) ) // the above binary was built from this
982
	981
983	982	/* x2222 uses raw rgb16 data rather than 8bpp indexed, in order to use the same gfx decodes with a custom draw routine we arrange the data into 2 8bpp regions on init */
984	983	ROM_REGION( 0x800000, "gfx1", ROMREGION_ERASE00 ) /* sprite tiles (16x16x8) */
985	984	/* filled in at init*/
r29404	r29405
1041	1040
1042	1041	ROM_REGION32_BE( 0x0200000, "misc", 0 ) /* other code */
1043	1042	ROM_LOAD( "older.hye", 0x000000, 0x010892f, CRC(cf3a004e) SHA1(1cba64cfa235b9540f33a5ee0cc02dfd267e00fc) ) // this corresponds to the older.bin we're using, for reference
1044
	1043
1045	1044	/* x2222 uses raw rgb16 data rather than 8bpp indexed, in order to use the same gfx decodes with a custom draw routine we arrange the data into 2 8bpp regions on init */
1046	1045	ROM_REGION( 0x800000, "gfx1", ROMREGION_ERASE00 ) /* sprite tiles (16x16x8) */
1047	1046	/* filled in at init*/

trunk/src/mame/drivers/toaplan1.c
r29404	r29405
2035	2035	MCFG_SCREEN_UPDATE_DRIVER(toaplan1_state, screen_update_toaplan1)
2036	2036	MCFG_SCREEN_VBLANK_DRIVER(toaplan1_state, screen_eof_toaplan1)
2037	2037	MCFG_SCREEN_PALETTE("palette")
2038
	2038
2039	2039	MCFG_GFXDECODE_ADD("gfxdecode", "palette", toaplan1)
2040	2040	MCFG_PALETTE_ADD("palette", (6416)+(6416))
2041	2041	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)

trunk/src/mame/drivers/dacholer.c
r29404	r29405
62	62	optional_device<msm5205_device> m_msm;
63	63	required_device<gfxdecode_device> m_gfxdecode;
64	64	required_device<palette_device> m_palette;
65
	65
66	66	/* video-related */
67	67	tilemap_t *m_bg_tilemap;
68	68	tilemap_t *m_fg_tilemap;

trunk/src/mame/drivers/pgm.c
r29404	r29405
4219	4219	GAME( 2004, kovlsqh2, kovshp, pgm_arm_type1, kovsh, pgm_arm_type1_state, kovlsqh2, ROT0, "bootleg", "Knights of Valour: Luan Shi Quan Huang 2 / Sangoku Senki: Luan Shi Quan Huang 2 (ver. 200CN)", GAME_IMPERFECT_SOUND \| GAME_UNEMULATED_PROTECTION \| GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE ) /* need internal rom of IGS027A */
4220	4220	GAME( 2004, kovlsjb, kovshp, pgm_arm_type1, kovsh, pgm_arm_type1_state, kovlsqh2, ROT0, "bootleg", "Knights of Valour: Luan Shi Jie Ba / Sangoku Senki: Luan Shi Jie Ba (ver. 200CN, set 1)", GAME_IMPERFECT_SOUND \| GAME_UNEMULATED_PROTECTION \| GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE ) /* need internal rom of IGS027A */
4221	4221	GAME( 2004, kovlsjba, kovshp, pgm_arm_type1, kovsh, pgm_arm_type1_state, kovlsqh2, ROT0, "bootleg", "Knights of Valour: Luan Shi Jie Ba / Sangoku Senki: Luan Shi Jie Ba (ver. 200CN, set 2)", GAME_IMPERFECT_SOUND \| GAME_UNEMULATED_PROTECTION \| GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE ) /* need internal rom of IGS027A */
4222

trunk/src/mame/drivers/model3.c
r29404	r29405
2941	2941	ROM_END
2942	2942
2943	2943	/*
2944		In Mame getbass is marked as GET BASS STD, while my pcb came from a DLX cab.
	2944	In Mame getbass is marked as GET BASS STD, while my pcb came from a DLX cab.
2945	2945	Rom board 833-13317
2946	2946	834-13318 sticker is on rom board too.
2947	2947	On cage the follow sticker are present
2948	2948	BSS-4500-CVT2
2949	2949	833-13317 GAME BD BSS-CVT2
2950
	2950
2951	2951	I/O board 837-13283 (GET BASS MEC CONT BD in manual) 171-7558c
2952	2952
2953	2953	epr20690.ic11 is controller board prg
r29404	r29405
5442	5442	MCFG_SCREEN_SIZE(512, 400)
5443	5443	MCFG_SCREEN_UPDATE_DRIVER(model3_state, screen_update_model3)
5444	5444	MCFG_SCREEN_PALETTE("palette")
5445
	5445
5446	5446	MCFG_PALETTE_ADD_RRRRRGGGGGBBBBB("palette")
5447	5447
5448	5448

trunk/src/mame/drivers/funkyjet.c
r29404	r29405
345	345	MCFG_DECO16IC_ADD("tilegen1", funkyjet_deco16ic_tilegen1_intf)
346	346	MCFG_DECO16IC_GFXDECODE("gfxdecode")
347	347	MCFG_DECO16IC_PALETTE("palette")
348
	348
349	349	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
350	350	decospr_device::set_gfx_region(*device, 2);
351	351	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")

trunk/src/mame/drivers/cps3.c
r29404	r29405
2583	2583	MCFG_PALETTE_ADD("palette", 0x10000) // actually 0x20000 ...
2584	2584
2585	2585	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
2586
	2586
2587	2587	/* sound hardware */
2588	2588	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
2589	2589

trunk/src/mame/drivers/mlanding.c
r29404	r29405
108	108	required_shared_ptr<UINT16> m_cha_ram;
109	109	required_shared_ptr<UINT16> m_dot_ram;
110	110	required_shared_ptr<UINT8> m_power_ram;
111
	111
112	112	required_device<palette_device> m_palette;
113	113
114	114	UINT16 *m_dma_ram;

trunk/src/mame/drivers/boxer.c
r29404	r29405
51	51	required_device<gfxdecode_device> m_gfxdecode;
52	52	required_device<screen_device> m_screen;
53	53	required_device<palette_device> m_palette;
54
	54
55	55	DECLARE_READ8_MEMBER(boxer_input_r);
56	56	DECLARE_READ8_MEMBER(boxer_misc_r);
57	57	DECLARE_WRITE8_MEMBER(boxer_bell_w);
r29404	r29405
180	180
181	181	code = p[32 * l + 4 * i + j];
182	182
183
	183
184	184	m_gfxdecode->gfx(n)->transpen(bitmap,cliprect,
185	185	code,
186	186	0,
r29404	r29405
190	190
191	191	code = p[32 * r + 4 * i - j + 3];
192	192
193
	193
194	194	m_gfxdecode->gfx(n)->transpen(bitmap,cliprect,
195	195	code,
196	196	0,
r29404	r29405
215	215	{
216	216	UINT8 code = m_tile_ram[32 * i + j];
217	217
218
	218
219	219	m_gfxdecode->gfx(2)->transpen(bitmap,cliprect,
220	220	code,
221	221	0,

trunk/src/mame/drivers/namcos22.c
r29404	r29405
1596	1596	// reading random values in some games for example in timecris to determine
1597	1597	// where certain enemies will emerge.
1598	1598	// It works in combination with keycus_w, but not yet understood how.
1599
	1599
1600	1600	// printf("Hit keycus offs %x mask %x PC=%x\n", offset, mem_mask, space.device().safe_pc());
1601	1601
1602	1602	// protection (not used for all games)
r29404	r29405
1608	1608	case NAMCOS22_RIDGE_RACER2:
1609	1609	if (offset == 0) return 0x0172;
1610	1610	break;
1611
	1611
1612	1612	case NAMCOS22_ACE_DRIVER:
1613	1613	if (offset == 3) return 0x0173;
1614	1614	break;
1615
	1615
1616	1616	case NAMCOS22_CYBER_COMMANDO:
1617	1617	if (offset == 1) return 0x0185;
1618	1618	break;
r29404	r29405
1640	1640	case NAMCOS22_TOKYO_WARS:
1641	1641	if (offset == 4) return 0x01a8;
1642	1642	break;
1643
	1643
1644	1644	default:
1645	1645	break;
1646	1646	}
1647
	1647
1648	1648	// pick a random number, but don't pick the same twice in a row
1649	1649	UINT16 old_rng = m_keycus_rng;
1650	1650	do

trunk/src/mame/drivers/galaxold.c
r29404	r29405
2550	2550	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 28, 308-1)
2551	2551	MCFG_SCREEN_UPDATE_DRIVER(galaxold_state, screen_update_galaxold)
2552	2552	MCFG_SCREEN_PALETTE("palette")
2553
	2553
2554	2554	MCFG_PALETTE_ADD("palette", 64)
2555	2555	MCFG_PALETTE_INIT_OWNER(galaxold_state,rockclim)
2556	2556
r29404	r29405
2622	2622	MCFG_GFXDECODE_ADD("gfxdecode", "palette", galaxian)
2623	2623	MCFG_PALETTE_ADD("palette", 32)
2624	2624	MCFG_PALETTE_INIT_OWNER(galaxold_state,rockclim)
2625
	2625
2626	2626	MCFG_SCREEN_ADD("screen", RASTER)
2627	2627	MCFG_SCREEN_RAW_PARAMS(PIXEL_CLOCK, HTOTAL, HBEND, HBSTART, VTOTAL, VBEND, VBSTART)
2628	2628	MCFG_SCREEN_UPDATE_DRIVER(galaxold_state, screen_update_galaxold)

trunk/src/mame/drivers/cv1k.c
r29404	r29405
163	163
164	164	Blitter Timing
165	165	- Correct slowdown emulation and flags (depends on blit mode, and speed of RAM) - could do with the recompiler or alt idle skips on the busy flag wait looops
166		- End of Blit IRQ? (one game has a valid irq routine that looks like it was used for profiling, but nothing depends on it)
	166	- End of Blit IRQ? (one game has a valid irq routine that looks like it was used for profiling, but nothing depends on it)
167	167
168	168	*/
169	169
r29404	r29405
204	204
205	205	INTERRUPT_GEN_MEMBER(cv1k_interrupt);
206	206	UINT32 screen_update_cv1k(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
207
	207
208	208	DECLARE_MACHINE_RESET( cv1k );
209	209
210	210	/* game specific */
211		DECLARE_READ64_MEMBER(mushisam_speedup_r);
212		DECLARE_READ64_MEMBER(mushisama_speedup_r);
213		DECLARE_READ64_MEMBER(espgal2_speedup_r);
214		DECLARE_DRIVER_INIT(mushisam);
215		DECLARE_DRIVER_INIT(mushisama);
216		DECLARE_DRIVER_INIT(espgal2);
	211	DECLARE_READ64_MEMBER(mushisam_speedup_r);
	212	DECLARE_READ64_MEMBER(mushisama_speedup_r);
	213	DECLARE_READ64_MEMBER(espgal2_speedup_r);
	214	DECLARE_DRIVER_INIT(mushisam);
	215	DECLARE_DRIVER_INIT(mushisama);
	216	DECLARE_DRIVER_INIT(espgal2);
217	217	};
218	218
219	219
r29404	r29405
237	237
238	238	READ64_MEMBER( cv1k_state::cv1k_flash_port_e_r )
239	239	{
240		return ((m_serflash->flash_ready_r(space, offset) ? 0x20 : 0x00)) \| 0xdf;
	240	return ((m_serflash->flash_ready_r(space, offset) ? 0x20 : 0x00)) \| 0xdf;
241	241	}
242	242
243	243
r29404	r29405
324	324	AM_RANGE(0x10000000, 0x10000007) AM_READWRITE8(cv1k_flash_io_r, cv1k_flash_io_w, U64(0xffffffffffffffff))
325	325	AM_RANGE(0x10400000, 0x10400007) AM_DEVWRITE8("ymz770", ymz770_device, write, U64(0xffffffffffffffff))
326	326	AM_RANGE(0x10C00000, 0x10C00007) AM_READWRITE8(serial_rtc_eeprom_r, serial_rtc_eeprom_w, U64(0xffffffffffffffff))
327		// AM_RANGE(0x18000000, 0x18000057) // blitter, installed on reset
	327	// AM_RANGE(0x18000000, 0x18000057) // blitter, installed on reset
328	328	AM_RANGE(0xf0000000, 0xf0ffffff) AM_RAM // mem mapped cache (sh3 internal?)
329	329	ADDRESS_MAP_END
330	330
r29404	r29405
334	334	AM_RANGE(0x10000000, 0x10000007) AM_READWRITE8(cv1k_flash_io_r, cv1k_flash_io_w, U64(0xffffffffffffffff))
335	335	AM_RANGE(0x10400000, 0x10400007) AM_DEVWRITE8("ymz770", ymz770_device, write, U64(0xffffffffffffffff))
336	336	AM_RANGE(0x10C00000, 0x10C00007) AM_READWRITE8(serial_rtc_eeprom_r, serial_rtc_eeprom_w, U64(0xffffffffffffffff))
337		// AM_RANGE(0x18000000, 0x18000057) // blitter, installed on reset
	337	// AM_RANGE(0x18000000, 0x18000057) // blitter, installed on reset
338	338	AM_RANGE(0xf0000000, 0xf0ffffff) AM_RAM // mem mapped cache (sh3 internal?)
339	339	ADDRESS_MAP_END
340	340
r29404	r29405
349	349
350	350
351	351	static INPUT_PORTS_START( cv1k )
352		PORT_START("DSW") // 18000050.l (18000050.b + 3 i.e. MSB + 3, is shown as DIPSW)
	352	PORT_START("DSW") // 18000050.l (18000050.b + 3 i.e. MSB + 3, is shown as DIPSW)
353	353	// PORT_BIT( 0xfcfffffc, IP_ACTIVE_LOW, IPT_UNKNOWN )
354	354	PORT_DIPNAME( 0x00000002, 0x00000000, DEF_STR( Unknown ) )
355	355	PORT_DIPSETTING( 0x00000000, DEF_STR( Off ) )
r29404	r29405
357	357	PORT_SERVICE( 0x00000001, IP_ACTIVE_HIGH )
358	358
359	359	PORT_START("PORT_C")
360		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) // Service coin
361		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Test button copied here
362		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) // IMPLEMENT COIN ERROR!
	360	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) // Service coin
	361	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Test button copied here
	362	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) // IMPLEMENT COIN ERROR!
363	363	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN2 )
364	364	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
365	365	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
r29404	r29405
376	376	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
377	377
378	378	PORT_START("PORT_F")
379		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Test Push Button
	379	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Test Push Button
380	380	PORT_BIT( 0xfd, IP_ACTIVE_LOW, IPT_UNKNOWN )
381	381
382		PORT_START("PORT_L") // 4000134.b, 4000136.b
	382	PORT_START("PORT_L") // 4000134.b, 4000136.b
383	383	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
384	384	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
385	385	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
r29404	r29405
528	528
529	529	ROM_REGION( 0x8400000, "game", ROMREGION_ERASEFF)
530	530	ROM_LOAD("mushisamb_u2", 0x000000, 0x8400000, CRC(6cc9d1a9) SHA1(17907798dce1defadd10354cec6c8d364e045570) ) /* (2004/10/12 MASTER VER) */
531
	531
532	532	ROM_REGION( 0x800000, "ymz770", ROMREGION_ERASEFF)
533	533	ROM_LOAD16_WORD_SWAP("u23", 0x000000, 0x400000, CRC(138e2050) SHA1(9e86489a4e65af5efb5495adf6d4b3e01d5b2816) )
534	534	ROM_LOAD16_WORD_SWAP("u24", 0x400000, 0x400000, CRC(e3d05c9f) SHA1(130c3d62317da1729c85bd178bd51500edd73ada) )
r29404	r29405
798	798	int pc = m_maincpu->pc();
799	799	if ( pc == 0xc04a0aa ) m_maincpu->spin_until_time( attotime::from_usec(10)); // mushisam
800	800	else if (pc == 0xc04a0da) m_maincpu->spin_until_time( attotime::from_usec(10)); // mushitam
801		// else printf("read %08x\n", m_maincpu->pc());
	801	// else printf("read %08x\n", m_maincpu->pc());
802	802	return cv1k_ram[0x0022f0/8];
803	803	}
804	804
805	805	DRIVER_INIT_MEMBER(cv1k_state,mushisam)
806	806	{
807		m_maincpu->space(AS_PROGRAM).install_read_handler(0xc0022f0, 0xc0022f7, read64_delegate(FUNC(cv1k_state::mushisam_speedup_r),this));
	807	m_maincpu->space(AS_PROGRAM).install_read_handler(0xc0022f0, 0xc0022f7, read64_delegate(FUNC(cv1k_state::mushisam_speedup_r),this));
808	808	}
809	809
810	810	READ64_MEMBER( cv1k_state::mushisama_speedup_r )
811	811	{
812	812	if (m_maincpu->pc()== 0xc04a2aa ) m_maincpu->spin_until_time( attotime::from_usec(10)); // mushisam
813		// else printf("read %08x\n", m_maincpu->pc());
	813	// else printf("read %08x\n", m_maincpu->pc());
814	814	return cv1k_ram[0x00024d8/8];
815	815	}
816	816
817	817	DRIVER_INIT_MEMBER(cv1k_state,mushisama)
818	818	{
819		m_maincpu->space(AS_PROGRAM).install_read_handler(0xc0024d8, 0xc0024df, read64_delegate(FUNC(cv1k_state::mushisama_speedup_r),this));
	819	m_maincpu->space(AS_PROGRAM).install_read_handler(0xc0024d8, 0xc0024df, read64_delegate(FUNC(cv1k_state::mushisama_speedup_r),this));
820	820	}
821	821
822	822	READ64_MEMBER( cv1k_state::espgal2_speedup_r )
r29404	r29405
827	827	if ( pc == 0xc05176a ) m_maincpu->spin_until_time( attotime::from_usec(10)); // futari15 / futari15a / futari10 / futariblk / ibarablk / ibarablka / mmpork / mmmbanc
828	828	if ( pc == 0xc0519a2 ) m_maincpu->spin_until_time( attotime::from_usec(10)); // deathsml
829	829	if ( pc == 0xc1d1346 ) m_maincpu->spin_until_time( attotime::from_usec(10)); // dpddfk / dsmbl
830		// else printf("read %08x\n", m_maincpu->pc());
	830	// else printf("read %08x\n", m_maincpu->pc());
831	831	return cv1k_ram[0x002310/8];
832	832	}
833	833
834	834	DRIVER_INIT_MEMBER(cv1k_state,espgal2)
835	835	{
836		m_maincpu->space(AS_PROGRAM).install_read_handler(0xc002310, 0xc002317, read64_delegate(FUNC(cv1k_state::espgal2_speedup_r),this));
	836	m_maincpu->space(AS_PROGRAM).install_read_handler(0xc002310, 0xc002317, read64_delegate(FUNC(cv1k_state::espgal2_speedup_r),this));
837	837	}
838	838
839	839

trunk/src/mame/drivers/dec0.c
r29404	r29405
1487	1487	deco_mxc06_device::set_gfx_region(*device, 3);
1488	1488	MCFG_DECO_MXC06_GFXDECODE("gfxdecode")
1489	1489	MCFG_DECO_MXC06_PALETTE("palette")
1490
1491	1490
	1491
1492	1492	MCFG_PALETTE_ADD("palette", 1024)
1493	1493	MCFG_PALETTE_FORMAT(xxxxBBBBGGGGRRRR)
1494	1494	MCFG_GFXDECODE_ADD("gfxdecode", "palette", secretab)

trunk/src/mame/drivers/tceptor.c
r29404	r29405
383	383	MCFG_PALETTE_ADD("palette", 4096)
384	384	MCFG_PALETTE_INDIRECT_ENTRIES(1024)
385	385	MCFG_PALETTE_INIT_OWNER(tceptor_state, tceptor)
386
	386
387	387	MCFG_DEFAULT_LAYOUT(layout_horizont)
388	388
389	389	MCFG_NAMCO_C45_ROAD_ADD("c45_road")

trunk/src/mame/drivers/metro.c
r29404	r29405
1731	1731
1732	1732	puzzlet_io_device::puzzlet_io_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1733	1733	: device_t(mconfig, PUZZLET_IO, "Puzzlet Coin/Start I/O", tag, owner, clock, "puzzlet_io", __FILE__),
1734		data_cb(*this),
1735		port(*this, ":IN0")
	1734	data_cb(*this),
	1735	port(*this, ":IN0")
1736	1736	{
1737	1737	}
1738	1738
r29404	r29405
5316	5316	/* an 'Electronic Devices' manufactured board has been seen with the following roms. The data is 100% identical to the above set
5317	5317	but due to lazy manufacturing larger ROMs were used and the first half filled with 0xff
5318	5318
5319		ROM_LOAD16_BYTE( "ladyki_3.h9", 0x000000, 0x080000, CRC(c658f954) SHA1(d50043457e67a94feff1328fe9bf522aa3c124b6) ) // == e2.8g
5320		ROM_LOAD16_BYTE( "ladyki_2.h10", 0x000001, 0x080000, CRC(bf58e4db) SHA1(9d7f74dc348b0ccb3bcf1b618d6092292b6945b8) ) // == e3.10g
5321		ROM_LOAD( "ladyki_1.d1", 0x000000, 0x080000, CRC(3dca957c) SHA1(4b815b7cb124a38c639a4b425ed6e8b1f0946451) ) // == e8.1d
	5319	ROM_LOAD16_BYTE( "ladyki_3.h9", 0x000000, 0x080000, CRC(c658f954) SHA1(d50043457e67a94feff1328fe9bf522aa3c124b6) ) // == e2.8g
	5320	ROM_LOAD16_BYTE( "ladyki_2.h10", 0x000001, 0x080000, CRC(bf58e4db) SHA1(9d7f74dc348b0ccb3bcf1b618d6092292b6945b8) ) // == e3.10g
	5321	ROM_LOAD( "ladyki_1.d1", 0x000000, 0x080000, CRC(3dca957c) SHA1(4b815b7cb124a38c639a4b425ed6e8b1f0946451) ) // == e8.1d
5322	5322	*/
5323	5323
5324	5324	ROM_START( moegonta )

trunk/src/mame/drivers/hshavoc.c
r29404	r29405
222	222	}
223	223
224	224	DRIVER_INIT_CALL(megadriv);
225
	225
226	226	m_vdp->stop_timers();
227	227	}
228	228

trunk/src/mame/drivers/dunhuang.c
r29404	r29405
130	130	required_device<cpu_device> m_maincpu;
131	131	required_device<gfxdecode_device> m_gfxdecode;
132	132	required_device<screen_device> m_screen;
133		required_device<palette_device> m_palette;
	133	required_device<palette_device> m_palette;
134	134	};
135	135
136	136

trunk/src/mame/drivers/truco.c
r29404	r29405
83	83	- U15: 20-pin IC YES PLD PALCE16V8H-25 EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic.
84	84	- U16: 20-pin IC YES PLD PALCE16V8H-25 EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic.
85	85	- U17: 14-pin IC YES TTL HD74LS00P Quadruple 2-Input NAND Gates.
86		- U18: 14-pin IC YES TTL KS74HCTLS86N Quad 2−Input Exclusive OR Gate.
	86	- U18: 14-pin IC YES TTL KS74HCTLS86N Quad 2???Input Exclusive OR Gate.
87	87	- U19: 16-pin IC YES WATCHDOG MAXIM MAX691 Microprocessor Supervisory Circuits.
88	88	- U20: 16-pin IC YES DARLINGTON ULN2003 7 NPN Darlington transistor pairs with high voltage and current capability.
89	89

trunk/src/mame/drivers/vball.c
r29404	r29405
409	409	MCFG_SCREEN_RAW_PARAMS(PIXEL_CLOCK, 384, 0, 256, 272, 8, 248) /* based on ddragon driver */
410	410	MCFG_SCREEN_UPDATE_DRIVER(vball_state, screen_update_vb)
411	411	MCFG_SCREEN_PALETTE("palette")
412
	412
413	413	MCFG_GFXDECODE_ADD("gfxdecode", "palette", vb)
414	414	MCFG_PALETTE_ADD("palette", 256)
415	415

trunk/src/mame/drivers/naomi.c
r29404	r29405
2516	2516	MCFG_AICA_MASTER
2517	2517	MCFG_AICA_IRQ_CB(WRITELINE(naomi_state, aica_irq))
2518	2518	MCFG_AICA_MAIN_IRQ_CB(WRITELINE(naomi_state, sh4_aica_irq))
2519
	2519
2520	2520	MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
2521	2521	MCFG_SOUND_ROUTE(1, "rspeaker", 2.0)
2522	2522
r29404	r29405
3638	3638	ROM_START( f355twin )
3639	3639	F355_BIOS
3640	3640	NAOMI_DEFAULT_EEPROM
3641
	3641
3642	3642	ROM_REGION( 0xb000000, "rom_board", ROMREGION_ERASEFF)
3643	3643	ROM_LOAD( "epr-22848.ic22", 0x0000000, 0x400000, CRC(a29edec2) SHA1(21ab3b5805e5aac20f51d0c468bcef1a655194bb) )
3644	3644	ROM_LOAD( "mpr-22827.ic1", 0x0800000, 0x800000, CRC(eeb1b975) SHA1(929f453eaf5565ae3e660dbbb8f406ff8aa7897d) )
r29404	r29405
5463	5463
5464	5464	ROM_REGION( 4, "rom_key", 0 )
5465	5465	ROM_LOAD( "mushik2e-key.bin", 0, 4, CRC(b32a0633) SHA1(984c01e43cf359d8e8a0c6cb1a04c5dc3da47d39) )
5466
	5466
5467	5467	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x02))
5468	5468	ROM_END
5469	5469
r29404	r29405
5478	5478
5479	5479	ROM_REGION( 4, "rom_key", 0 )
5480	5480	ROM_LOAD( "mushik2e-key.bin", 0, 4, CRC(b32a0633) SHA1(984c01e43cf359d8e8a0c6cb1a04c5dc3da47d39) )
5481
	5481
5482	5482	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x82))
5483	5483	ROM_END
5484	5484
r29404	r29405
5492	5492
5493	5493	ROM_REGION( 4, "rom_key", 0 )
5494	5494	ROM_LOAD( "zunou-key.bin", 0, 4, CRC(cbe35afb) SHA1(78877655800aae27661bf720e1c37d6c6f2e3d1c) )
5495
	5495
5496	5496	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x02))
5497	5497	ROM_END
5498	5498
r29404	r29405
5508	5508
5509	5509	ROM_REGION( 4, "rom_key", 0 )
5510	5510	ROM_LOAD( "sl2007-key.bin", 0, 4, CRC(d5d1e807) SHA1(8a0cc371729c622bb05c5d26b3e39ec31d29ace1) )
5511
	5511
5512	5512	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x04))
5513	5513	ROM_END
5514	5514
r29404	r29405
5524	5524
5525	5525	ROM_REGION( 4, "rom_key", 0 )
5526	5526	ROM_LOAD( "asndynmt-key.bin", 0, 4, CRC(bf5396a9) SHA1(0b27fdc800143fb977cb2f1e937078d7a7006939) )
5527
	5527
5528	5528	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x04))
5529	5529	ROM_END
5530	5530
r29404	r29405
5540	5540
5541	5541	ROM_REGION( 4, "rom_key", 0 )
5542	5542	ROM_LOAD( "illvelo-key.bin", 0, 4, CRC(e164952f) SHA1(6c0dfe567640e1e843a5d7bf858a24c101dfcf95) )
5543
	5543
5544	5544	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x04))
5545	5545	ROM_END
5546	5546
r29404	r29405
5556	5556
5557	5557	ROM_REGION( 4, "rom_key", 0 )
5558	5558	ROM_LOAD( "mamonoro-key.bin", 0x000000, 0x000004, CRC(264ca27a) SHA1(3b81b9794d86697f8eac7ea6945d992564ad6199) )
5559
	5559
5560	5560	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x04))
5561	5561	ROM_END
5562	5562
r29404	r29405
5574	5574
5575	5575	ROM_REGION( 4, "rom_key", 0 )
5576	5576	ROM_LOAD( "mbaa-key.bin", 0x000000, 0x000004, CRC(f4ad909f) SHA1(27ba44592c2642b5862a24f68c755ad4115e6047) )
5577
	5577
5578	5578	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x06))
5579	5579	ROM_END
5580	5580
r29404	r29405
5593	5593
5594	5594	ROM_REGION( 4, "rom_key", 0 )
5595	5595	ROM_LOAD( "mbaa-key.bin", 0x000000, 0x000004, CRC(f4ad909f) SHA1(27ba44592c2642b5862a24f68c755ad4115e6047) )
5596
	5596
5597	5597	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x86))
5598	5598	ROM_END
5599	5599
r29404	r29405
5608	5608
5609	5609	ROM_REGION( 4, "rom_key", 0 )
5610	5610	ROM_LOAD( "radirgyn-key.bin", 0x000000, 0x000004, CRC(c158cf3b) SHA1(c128646d7fee79fc10bf7bbaa23121f347df77f4) )
5611
	5611
5612	5612	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x04))
5613	5613	ROM_END
5614	5614
r29404	r29405
5623	5623
5624	5624	ROM_REGION( 4, "rom_key", 0 )
5625	5625	ROM_LOAD( "ausfache-key.bin", 0, 4, CRC(93cdc793) SHA1(f0a0c321a3bdf8ca87cbd840a168a9057c08f16a) )
5626
	5626
5627	5627	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x04))
5628	5628	ROM_END
5629	5629
r29404	r29405
5633	5633
5634	5634	ROM_REGION( 0x14000000, "rom_board", ROMREGION_ERASEFF)
5635	5635	ROM_LOAD( "fpr-24408.ic8", 0x00000000, 0x4000000, CRC(cc6c722d) SHA1(5a3deb5c4e3e0c518f71fe76d8c1f9ffdf6c527d) )
5636		ROM_LOAD( "fpr-24372.ic9", 0x04000000, 0x4000000, CRC(869eb096) SHA1(60135ecc2b48c748ba98c26a3a266e7f5622971a) )
5637		ROM_LOAD( "fpr-24373.ic10", 0x08000000, 0x4000000, CRC(60a1cf35) SHA1(35d0f6cc7f8d3c0330e3ee0e23a24c7f94c1b607) )
5638		ROM_LOAD( "fpr-24374.ic11", 0x0c000000, 0x4000000, CRC(57023e31) SHA1(5191728a9c717150d694e6709fe84ec800b0eac9) )
5639		ROM_LOAD( "fpr-24375.ic12", 0x10000000, 0x4000000, CRC(959c5396) SHA1(d0f5b96c0e20a7d91fcf6961a5eb9f36f143a590) )
	5636	ROM_LOAD( "fpr-24372.ic9", 0x04000000, 0x4000000, CRC(869eb096) SHA1(60135ecc2b48c748ba98c26a3a266e7f5622971a) )
	5637	ROM_LOAD( "fpr-24373.ic10", 0x08000000, 0x4000000, CRC(60a1cf35) SHA1(35d0f6cc7f8d3c0330e3ee0e23a24c7f94c1b607) )
	5638	ROM_LOAD( "fpr-24374.ic11", 0x0c000000, 0x4000000, CRC(57023e31) SHA1(5191728a9c717150d694e6709fe84ec800b0eac9) )
	5639	ROM_LOAD( "fpr-24375.ic12", 0x10000000, 0x4000000, CRC(959c5396) SHA1(d0f5b96c0e20a7d91fcf6961a5eb9f36f143a590) )
5640	5640
5641	5641	ROM_REGION( 0x200000, "ioboard", 0) // touch screen I/O board, program disassembles as little-endian SH-4
5642	5642	ROM_LOAD( "fpr24351.ic14", 0x000000, 0x200000, CRC(4d1b7b89) SHA1(965b8c6b5a2e7b3f1b1e2eac19c86000c3b66754) )
5643	5643
5644	5644	ROM_REGION( 4, "rom_key", 0 )
5645	5645	ROM_LOAD( "pokasuka-key.bin", 0, 4, CRC(f00bcd61) SHA1(b8315b851656c2e0b7853979988d1c44eab0886b) )
5646
	5646
5647	5647	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x05))
5648	5648	ROM_END
5649	5649
r29404	r29405
5663	5663
5664	5664	ROM_REGION( 4, "rom_key", 0 )
5665	5665	ROM_LOAD( "pokasuka-key.bin", 0, 4, CRC(f00bcd61) SHA1(b8315b851656c2e0b7853979988d1c44eab0886b) )
5666
	5666
5667	5667	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x05))
5668	5668	ROM_END
5669	5669
r29404	r29405
5761	5761	ROM_LOAD( "bhf1ma13.6n", 0xd000000, 0x1000000, CRC(055718ad) SHA1(355c4780231a4361aa6237dd34819b60d9df0fc7) )
5762	5762	ROM_LOAD( "bhf1ma14.6m", 0xe000000, 0x1000000, CRC(d06c9bd7) SHA1(54668a2fd31059976890da92709c18f308634887) )
5763	5763	ROM_LOAD( "bhf1ma15.6l", 0xf000000, 0x1000000, CRC(db3c396b) SHA1(da0e125d627ce890906ca100081ab0685e11c0ef) )
5764
	5764
5765	5765	ROM_REGION( 4, "rom_key", 0 )
5766	5766	ROM_LOAD( "bhf1-key.bin", 0x0000000, 0x0000004, CRC(9899e931) SHA1(c0837262b9069b33d0e72b418e80b5f0da8b9251) )
5767	5767	ROM_END
r29404	r29405
6280	6280	NAOMI_DEFAULT_EEPROM
6281	6281
6282	6282	ROM_REGION( 0x4800000, "rom_board", ROMREGION_ERASEFF)
6283		ROM_LOAD( "epr-23625.ic22", 0x000000, 0x0400000, CRC(7300bc6c) SHA1(f0bfff190c9f02895cc1f98eb695f327c948fca3) )
	6283	ROM_LOAD( "epr-23625.ic22", 0x000000, 0x0400000, CRC(7300bc6c) SHA1(f0bfff190c9f02895cc1f98eb695f327c948fca3) )
6284	6284	ROM_RELOAD( 0x400000, 0x400000)
6285		ROM_LOAD( "mpr-23231.ic1", 0x0800000, 0x1000000, CRC(e41ddc53) SHA1(f565d68d8ce4010a2181b0343fa49bfdc81ba4cf) )
6286		ROM_LOAD( "mpr-23232.ic2", 0x1800000, 0x1000000, CRC(30f963a0) SHA1(dc56203ceae20f7a7354e505dd7f27cbce5c70e0) )
6287		ROM_LOAD( "mpr-23233.ic3", 0x2800000, 0x1000000, CRC(d6451cab) SHA1(6508e27d0370b19df01150da7baf4875479c166a) )
6288		ROM_LOAD( "mpr-23234.ic4", 0x3800000, 0x1000000, CRC(44044c14) SHA1(4934cb8d5f9b4085ffb5ddc711343f488aae4c4d) )
	6285	ROM_LOAD( "mpr-23231.ic1", 0x0800000, 0x1000000, CRC(e41ddc53) SHA1(f565d68d8ce4010a2181b0343fa49bfdc81ba4cf) )
	6286	ROM_LOAD( "mpr-23232.ic2", 0x1800000, 0x1000000, CRC(30f963a0) SHA1(dc56203ceae20f7a7354e505dd7f27cbce5c70e0) )
	6287	ROM_LOAD( "mpr-23233.ic3", 0x2800000, 0x1000000, CRC(d6451cab) SHA1(6508e27d0370b19df01150da7baf4875479c166a) )
	6288	ROM_LOAD( "mpr-23234.ic4", 0x3800000, 0x1000000, CRC(44044c14) SHA1(4934cb8d5f9b4085ffb5ddc711343f488aae4c4d) )
6289	6289
6290	6290	// this dump can't be used as main_eeprom, because that's exactly 0x80 bytes
6291	6291	ROM_REGION(0x84, "some_eeprom", 0)
6292		ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(951684e4) SHA1(0beaf5827064252293223b946c04b8698e7207bb) )
	6292	ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(951684e4) SHA1(0beaf5827064252293223b946c04b8698e7207bb) )
6293	6293	ROM_END
6294	6294
6295	6295	ROM_START( starhrct )
r29404	r29405
6297	6297	NAOMI_DEFAULT_EEPROM
6298	6298
6299	6299	ROM_REGION( 0x9800000, "rom_board", ROMREGION_ERASEFF)
6300		ROM_LOAD( "epr-23626.ic22", 0x0000000, 0x200000, CRC(d5893a19) SHA1(861624ef3e5061b6ed9d6c4714e35fa508643b05) )
	6300	ROM_LOAD( "epr-23626.ic22", 0x0000000, 0x200000, CRC(d5893a19) SHA1(861624ef3e5061b6ed9d6c4714e35fa508643b05) )
6301	6301	ROM_RELOAD( 0x400000, 0x200000)
6302		ROM_LOAD( "ic1s.bin", 0x0800000, 0x800000, CRC(e45ab26f) SHA1(1e40ae9778a026b0f4c3c9681cf5d08397b72c48) )
6303		ROM_LOAD( "ic2s.bin", 0x1000000, 0x800000, CRC(4d0e4e64) SHA1(4fe1c35f4cf34391eb1e4486bde92bd6104f05f2) )
6304		ROM_LOAD( "ic3s.bin", 0x1800000, 0x800000, CRC(a18c7ce7) SHA1(1e4fb63c0d8f901b077590ccc0af4bba3135f56c) )
6305		ROM_LOAD( "ic4s.bin", 0x2000000, 0x800000, CRC(82001b50) SHA1(d06e70d2ae4cf0635872663c5b6f1dbbd12897e0) )
6306		ROM_LOAD( "ic5s.bin", 0x2800000, 0x800000, CRC(5e4af8b2) SHA1(98598a0f5932cf79f54ff79cfa03632550dee373) )
6307		ROM_LOAD( "ic6s.bin", 0x3000000, 0x800000, CRC(2950c543) SHA1(041548e79afcadc1b0e3524432ed52320f395f3e) )
6308		ROM_LOAD( "ic7s.bin", 0x3800000, 0x800000, CRC(a2bb8ebb) SHA1(c5329cedf5f746c0d684d8dea301a0786909ea1d) )
6309		ROM_LOAD( "ic8s.bin", 0x4000000, 0x800000, CRC(fde9b537) SHA1(b186da26bef43b483fd32c486bb018dc631bf485) )
6310		ROM_LOAD( "ic9s.bin", 0x4800000, 0x800000, CRC(4db3e79a) SHA1(de2480792e7dfc01195000607be90fd4b29fdcc0) )
6311		ROM_LOAD( "ic10s.bin", 0x5000000, 0x800000, CRC(37167167) SHA1(e379d20bcda84e6aaa0b930dce95d97812cd45d6) )
6312		ROM_LOAD( "ic11s.bin", 0x5800000, 0x800000, CRC(927f1edb) SHA1(64f2f2f4546cc6b45ee78aeae68ce829cb57a124) )
6313		ROM_LOAD( "ic12s.bin", 0x6000000, 0x800000, CRC(05de610d) SHA1(715124a3e7a23589c4ca9f0dccd55a21f7d48123) )
6314		ROM_LOAD( "ic13s.bin", 0x6800000, 0x800000, CRC(17ed44c3) SHA1(ec34276006c3be7bd6d23c11314b0369a082e1ef) )
6315		ROM_LOAD( "ic14s.bin", 0x7000000, 0x800000, CRC(66d7e2a1) SHA1(69178d4995ac3c2d73d953544101d23da1812f65) )
6316		ROM_LOAD( "ic15s.bin", 0x7800000, 0x800000, CRC(0c701416) SHA1(6c9e882e2a00768f5e0a28d38a5695c65594d8dd) )
6317		ROM_LOAD( "ic16s.bin", 0x8000000, 0x800000, CRC(5d8e6e8d) SHA1(03045f3a9257632c325eba9752855b42355dff6c) )
6318		ROM_LOAD( "ic17s.bin", 0x8800000, 0x800000, CRC(b4c40606) SHA1(4f187dfe44bd89c90b6fa4b90f16222bc0a74d22) )
	6302	ROM_LOAD( "ic1s.bin", 0x0800000, 0x800000, CRC(e45ab26f) SHA1(1e40ae9778a026b0f4c3c9681cf5d08397b72c48) )
	6303	ROM_LOAD( "ic2s.bin", 0x1000000, 0x800000, CRC(4d0e4e64) SHA1(4fe1c35f4cf34391eb1e4486bde92bd6104f05f2) )
	6304	ROM_LOAD( "ic3s.bin", 0x1800000, 0x800000, CRC(a18c7ce7) SHA1(1e4fb63c0d8f901b077590ccc0af4bba3135f56c) )
	6305	ROM_LOAD( "ic4s.bin", 0x2000000, 0x800000, CRC(82001b50) SHA1(d06e70d2ae4cf0635872663c5b6f1dbbd12897e0) )
	6306	ROM_LOAD( "ic5s.bin", 0x2800000, 0x800000, CRC(5e4af8b2) SHA1(98598a0f5932cf79f54ff79cfa03632550dee373) )
	6307	ROM_LOAD( "ic6s.bin", 0x3000000, 0x800000, CRC(2950c543) SHA1(041548e79afcadc1b0e3524432ed52320f395f3e) )
	6308	ROM_LOAD( "ic7s.bin", 0x3800000, 0x800000, CRC(a2bb8ebb) SHA1(c5329cedf5f746c0d684d8dea301a0786909ea1d) )
	6309	ROM_LOAD( "ic8s.bin", 0x4000000, 0x800000, CRC(fde9b537) SHA1(b186da26bef43b483fd32c486bb018dc631bf485) )
	6310	ROM_LOAD( "ic9s.bin", 0x4800000, 0x800000, CRC(4db3e79a) SHA1(de2480792e7dfc01195000607be90fd4b29fdcc0) )
	6311	ROM_LOAD( "ic10s.bin", 0x5000000, 0x800000, CRC(37167167) SHA1(e379d20bcda84e6aaa0b930dce95d97812cd45d6) )
	6312	ROM_LOAD( "ic11s.bin", 0x5800000, 0x800000, CRC(927f1edb) SHA1(64f2f2f4546cc6b45ee78aeae68ce829cb57a124) )
	6313	ROM_LOAD( "ic12s.bin", 0x6000000, 0x800000, CRC(05de610d) SHA1(715124a3e7a23589c4ca9f0dccd55a21f7d48123) )
	6314	ROM_LOAD( "ic13s.bin", 0x6800000, 0x800000, CRC(17ed44c3) SHA1(ec34276006c3be7bd6d23c11314b0369a082e1ef) )
	6315	ROM_LOAD( "ic14s.bin", 0x7000000, 0x800000, CRC(66d7e2a1) SHA1(69178d4995ac3c2d73d953544101d23da1812f65) )
	6316	ROM_LOAD( "ic15s.bin", 0x7800000, 0x800000, CRC(0c701416) SHA1(6c9e882e2a00768f5e0a28d38a5695c65594d8dd) )
	6317	ROM_LOAD( "ic16s.bin", 0x8000000, 0x800000, CRC(5d8e6e8d) SHA1(03045f3a9257632c325eba9752855b42355dff6c) )
	6318	ROM_LOAD( "ic17s.bin", 0x8800000, 0x800000, CRC(b4c40606) SHA1(4f187dfe44bd89c90b6fa4b90f16222bc0a74d22) )
6319	6319	// .18s chip is not present but is tested for an FF fill (pull-up resistors on the PCB's data bus presumably accomplish this)
6320	6320
6321	6321	// this dump can't be used as main_eeprom, because that's exactly 0x80 bytes
6322	6322	ROM_REGION(0x84, "some_eeprom", 0)
6323		ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(1557297e) SHA1(41e8a7a8eaf5076b124d378afdf97e328d100e72) )
	6323	ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(1557297e) SHA1(41e8a7a8eaf5076b124d378afdf97e328d100e72) )
6324	6324	ROM_END
6325	6325
6326	6326	ROM_START( starhrcl )
r29404	r29405
6328	6328	NAOMI_DEFAULT_EEPROM
6329	6329
6330	6330	ROM_REGION( 0x7000000, "rom_board", ROMREGION_ERASEFF)
6331		ROM_LOAD( "epr-23627.ic22", 0x0000000, 0x0400000, CRC(7caccc5e) SHA1(86bff30b76b4b02467b37341582062de5c507a39) )
6332		ROM_LOAD( "mpr-23275.ic1", 0x0800000, 0x1000000, CRC(ffc62eab) SHA1(bb9dd3cc6540de1c194df99d5629583216f4c557) )
6333		ROM_LOAD( "mpr-23276.ic2", 0x1800000, 0x1000000, CRC(8b7ce666) SHA1(2848786659349598e019fbb05c92ed3ce6e2ec11) )
6334		ROM_LOAD( "mpr-23277.ic3", 0x2800000, 0x1000000, CRC(47a6f9c5) SHA1(9af5c3129a44fcffb87b1b021d8812e0b695967f) )
6335		ROM_LOAD( "mpr-23278.ic4", 0x3800000, 0x1000000, CRC(c12b189c) SHA1(7743500400a4e23a5e97a53ee16775c32d9abd5d) )
6336		ROM_LOAD( "mpr-23279.ic5", 0x4800000, 0x1000000, CRC(b8b39559) SHA1(082c9b6926557654c3f3bf00d741f32c560b50ce) )
6337		ROM_LOAD( "mpr-23280.ic6", 0x5800000, 0x1000000, CRC(b1c8daa2) SHA1(a05fb374156ea013e35502abccc92f5117c39daa) )
6338		ROM_LOAD( "mpr-23281.ic7", 0x6800000, 0x0800000, CRC(c0378369) SHA1(c728a181eddb01b9f8574669d4550baed559a5a4) )
	6331	ROM_LOAD( "epr-23627.ic22", 0x0000000, 0x0400000, CRC(7caccc5e) SHA1(86bff30b76b4b02467b37341582062de5c507a39) )
	6332	ROM_LOAD( "mpr-23275.ic1", 0x0800000, 0x1000000, CRC(ffc62eab) SHA1(bb9dd3cc6540de1c194df99d5629583216f4c557) )
	6333	ROM_LOAD( "mpr-23276.ic2", 0x1800000, 0x1000000, CRC(8b7ce666) SHA1(2848786659349598e019fbb05c92ed3ce6e2ec11) )
	6334	ROM_LOAD( "mpr-23277.ic3", 0x2800000, 0x1000000, CRC(47a6f9c5) SHA1(9af5c3129a44fcffb87b1b021d8812e0b695967f) )
	6335	ROM_LOAD( "mpr-23278.ic4", 0x3800000, 0x1000000, CRC(c12b189c) SHA1(7743500400a4e23a5e97a53ee16775c32d9abd5d) )
	6336	ROM_LOAD( "mpr-23279.ic5", 0x4800000, 0x1000000, CRC(b8b39559) SHA1(082c9b6926557654c3f3bf00d741f32c560b50ce) )
	6337	ROM_LOAD( "mpr-23280.ic6", 0x5800000, 0x1000000, CRC(b1c8daa2) SHA1(a05fb374156ea013e35502abccc92f5117c39daa) )
	6338	ROM_LOAD( "mpr-23281.ic7", 0x6800000, 0x0800000, CRC(c0378369) SHA1(c728a181eddb01b9f8574669d4550baed559a5a4) )
6339	6339
6340	6340	// this dump can't be used as main_eeprom, because that's exactly 0x80 bytes
6341	6341	ROM_REGION(0x84, "some_eeprom", 0)
6342		ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(4929e940) SHA1(f8c4277ca0ae5e36b2eed033cc731b8fc4fccafc) )
	6342	ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(4929e940) SHA1(f8c4277ca0ae5e36b2eed033cc731b8fc4fccafc) )
6343	6343	ROM_END
6344	6344
6345	6345	ROM_START( starhrsp )
r29404	r29405
6364	6364	NAOMI_DEFAULT_EEPROM
6365	6365
6366	6366	ROM_REGION( 0xc000000, "rom_board", ROMREGION_ERASEFF)
6367		ROM_LOAD32_WORD( "ic17s.bin", 0x01000000, 0x800000, CRC(f51ce63b) SHA1(7642d5a78d103986ebe7bf9ecea7602490fcdfa2) )
6368		ROM_LOAD32_WORD( "ic18s.bin", 0x01000002, 0x800000, CRC(7109decc) SHA1(91481f427d4d28c3ff1805eb00b63deb9d691b27) )
6369		ROM_LOAD32_WORD( "ic19s.bin", 0x02000000, 0x800000, CRC(a58efa9c) SHA1(ff83c25ef4094c1033b906bd048569927b0828c2) )
6370		ROM_LOAD32_WORD( "ic20s.bin", 0x02000002, 0x800000, CRC(6dee24b2) SHA1(ef6eb8aa239af6b02169618dd2594fc9c62086dc) )
6371		ROM_LOAD32_WORD( "ic21s.bin", 0x03000000, 0x800000, CRC(9a0564c2) SHA1(71fa98fd4815a119ff2cbe07298fefc25a2cde79) )
6372		ROM_LOAD32_WORD( "ic22s.bin", 0x03000002, 0x800000, CRC(df692133) SHA1(9433010ca070003d59a18239cd2637e6f9bffeae) )
6373		ROM_LOAD32_WORD( "ic23s.bin", 0x04000000, 0x800000, CRC(61c98256) SHA1(a1e4e6fa7c2672d49ff6a0a5a239d9f405797248) )
6374		ROM_LOAD32_WORD( "ic24s.bin", 0x04000002, 0x800000, CRC(c7e8ec24) SHA1(7cf7fc4954caff3fe2bb14964889d79250e6e4db) )
6375		ROM_LOAD32_WORD( "ic25s.bin", 0x05000000, 0x800000, CRC(2cb47ef5) SHA1(3f6cea2ca7857bd441f9632cd295c5f57a3d59fc) )
6376		ROM_LOAD32_WORD( "ic26s.bin", 0x05000002, 0x800000, CRC(f5b477d5) SHA1(f79d65bee22800dce2964666278c285d15c059e7) )
6377		ROM_LOAD32_WORD( "ic27s.bin", 0x06000000, 0x800000, CRC(22c07470) SHA1(4e64b632a4dad2d6a565d90aa34a00739a2a4ad4) )
6378		ROM_LOAD32_WORD( "ic28s.bin", 0x06000002, 0x800000, CRC(018233e0) SHA1(168430d66c59db49d113b65ae6dac9ddb9919661) )
6379		ROM_LOAD32_WORD( "ic29s.bin", 0x07000000, 0x800000, CRC(96101b95) SHA1(b818f24b551eaf3a35d8eb23b7e7df2af5ceef5f) )
6380		ROM_LOAD32_WORD( "ic30s.bin", 0x07000002, 0x800000, CRC(16dff39b) SHA1(b3899ab22056015ed3fd4ee06f687d9dca540ece) )
6381		ROM_LOAD32_WORD( "ic31s.bin", 0x08000000, 0x800000, CRC(510c03dd) SHA1(1488a574590be8927bc8c403105b6fb72c829177) )
6382		ROM_LOAD32_WORD( "ic32s.bin", 0x08000002, 0x800000, CRC(b184e263) SHA1(5089b13c160708c4ddee36e4fb89110ab6281690) )
6383		ROM_LOAD32_WORD( "ic33s.bin", 0x09000000, 0x800000, CRC(be2a164b) SHA1(a1d93e84e7e35ec55e738dc27069295cd0610f27) )
6384		ROM_LOAD32_WORD( "ic34s.bin", 0x09000002, 0x800000, CRC(01e0a163) SHA1(7730ce21e9041c70d39700d4ea2ff3adf54a315e) )
6385		ROM_LOAD32_WORD( "ic35s.bin", 0x0a000000, 0x800000, CRC(ae0c1caa) SHA1(548c5e6cb0c99ba8f0a758bb66fb8d949b2da1a0) )
6386		ROM_LOAD32_WORD( "ic36s.bin", 0x0a000002, 0x800000, CRC(6de8d5c7) SHA1(896520ab7cf458fddeacdad7a535976445048d8f) )
6387		ROM_LOAD32_WORD( "ic37s.bin", 0x0b000000, 0x800000, CRC(fc89454c) SHA1(f0550e17930c71d81050f18eceb312fe82c084c2) )
6388		ROM_LOAD32_WORD( "ic38s.bin", 0x0b000002, 0x800000, CRC(86954476) SHA1(ba2b31032321abf5ddfe7cff7803ae4fa944812c) )
	6367	ROM_LOAD32_WORD( "ic17s.bin", 0x01000000, 0x800000, CRC(f51ce63b) SHA1(7642d5a78d103986ebe7bf9ecea7602490fcdfa2) )
	6368	ROM_LOAD32_WORD( "ic18s.bin", 0x01000002, 0x800000, CRC(7109decc) SHA1(91481f427d4d28c3ff1805eb00b63deb9d691b27) )
	6369	ROM_LOAD32_WORD( "ic19s.bin", 0x02000000, 0x800000, CRC(a58efa9c) SHA1(ff83c25ef4094c1033b906bd048569927b0828c2) )
	6370	ROM_LOAD32_WORD( "ic20s.bin", 0x02000002, 0x800000, CRC(6dee24b2) SHA1(ef6eb8aa239af6b02169618dd2594fc9c62086dc) )
	6371	ROM_LOAD32_WORD( "ic21s.bin", 0x03000000, 0x800000, CRC(9a0564c2) SHA1(71fa98fd4815a119ff2cbe07298fefc25a2cde79) )
	6372	ROM_LOAD32_WORD( "ic22s.bin", 0x03000002, 0x800000, CRC(df692133) SHA1(9433010ca070003d59a18239cd2637e6f9bffeae) )
	6373	ROM_LOAD32_WORD( "ic23s.bin", 0x04000000, 0x800000, CRC(61c98256) SHA1(a1e4e6fa7c2672d49ff6a0a5a239d9f405797248) )
	6374	ROM_LOAD32_WORD( "ic24s.bin", 0x04000002, 0x800000, CRC(c7e8ec24) SHA1(7cf7fc4954caff3fe2bb14964889d79250e6e4db) )
	6375	ROM_LOAD32_WORD( "ic25s.bin", 0x05000000, 0x800000, CRC(2cb47ef5) SHA1(3f6cea2ca7857bd441f9632cd295c5f57a3d59fc) )
	6376	ROM_LOAD32_WORD( "ic26s.bin", 0x05000002, 0x800000, CRC(f5b477d5) SHA1(f79d65bee22800dce2964666278c285d15c059e7) )
	6377	ROM_LOAD32_WORD( "ic27s.bin", 0x06000000, 0x800000, CRC(22c07470) SHA1(4e64b632a4dad2d6a565d90aa34a00739a2a4ad4) )
	6378	ROM_LOAD32_WORD( "ic28s.bin", 0x06000002, 0x800000, CRC(018233e0) SHA1(168430d66c59db49d113b65ae6dac9ddb9919661) )
	6379	ROM_LOAD32_WORD( "ic29s.bin", 0x07000000, 0x800000, CRC(96101b95) SHA1(b818f24b551eaf3a35d8eb23b7e7df2af5ceef5f) )
	6380	ROM_LOAD32_WORD( "ic30s.bin", 0x07000002, 0x800000, CRC(16dff39b) SHA1(b3899ab22056015ed3fd4ee06f687d9dca540ece) )
	6381	ROM_LOAD32_WORD( "ic31s.bin", 0x08000000, 0x800000, CRC(510c03dd) SHA1(1488a574590be8927bc8c403105b6fb72c829177) )
	6382	ROM_LOAD32_WORD( "ic32s.bin", 0x08000002, 0x800000, CRC(b184e263) SHA1(5089b13c160708c4ddee36e4fb89110ab6281690) )
	6383	ROM_LOAD32_WORD( "ic33s.bin", 0x09000000, 0x800000, CRC(be2a164b) SHA1(a1d93e84e7e35ec55e738dc27069295cd0610f27) )
	6384	ROM_LOAD32_WORD( "ic34s.bin", 0x09000002, 0x800000, CRC(01e0a163) SHA1(7730ce21e9041c70d39700d4ea2ff3adf54a315e) )
	6385	ROM_LOAD32_WORD( "ic35s.bin", 0x0a000000, 0x800000, CRC(ae0c1caa) SHA1(548c5e6cb0c99ba8f0a758bb66fb8d949b2da1a0) )
	6386	ROM_LOAD32_WORD( "ic36s.bin", 0x0a000002, 0x800000, CRC(6de8d5c7) SHA1(896520ab7cf458fddeacdad7a535976445048d8f) )
	6387	ROM_LOAD32_WORD( "ic37s.bin", 0x0b000000, 0x800000, CRC(fc89454c) SHA1(f0550e17930c71d81050f18eceb312fe82c084c2) )
	6388	ROM_LOAD32_WORD( "ic38s.bin", 0x0b000002, 0x800000, CRC(86954476) SHA1(ba2b31032321abf5ddfe7cff7803ae4fa944812c) )
6389	6389
6390	6390	ROM_COPY( "rom_board", 0x01000000, 0x400000, 0xc00000 )
6391	6391
r29404	r29405
6394	6394
6395	6395	// this dump can't be used as main_eeprom, because that's exactly 0x80 bytes
6396	6396	ROM_REGION(0x84, "some_eeprom", 0)
6397		ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(17150bc9) SHA1(c3af7d91e12141938d2b9e67eb9f5ff961cd09ff) )
	6397	ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(17150bc9) SHA1(c3af7d91e12141938d2b9e67eb9f5ff961cd09ff) )
6398	6398	ROM_END
6399	6399
6400	6400	/* GD-ROM titles - a PIC supplies a decryption key
r29404	r29405
7536	7536	ROM_REGION( 0x4000, "pic", ROMREGION_ERASEFF)
7537	7537	//PIC16C621A (317-0567-EXP)
7538	7538	//(sticker 253-5508-0567)
7539		ROM_LOAD("317-0567-exp.pic", 0x00, 0x4000, NO_DUMP )
	7539	ROM_LOAD("317-0567-exp.pic", 0x00, 0x4000, NO_DUMP )
7540	7540	ROM_END
7541	7541
7542	7542
r29404	r29405
7731	7731	NAOMI_DEFAULT_EEPROM
7732	7732
7733	7733	ROM_REGION( 0xb000000, "rom_board", ROMREGION_ERASEFF)
7734		ROM_LOAD( "epr-24083.ic11", 0x000000, 0x400000, CRC(2733e65a) SHA1(4a5d109d0531bebd8e8f585789adce98cac2ab93) )
	7734	ROM_LOAD( "epr-24083.ic11", 0x000000, 0x400000, CRC(2733e65a) SHA1(4a5d109d0531bebd8e8f585789adce98cac2ab93) )
7735	7735
7736	7736	ROM_REGION( 0x40000, "flash", ROMREGION_ERASEFF)
7737		ROM_LOAD( "315-6358a.ic2", 0x000000, 0x020008, CRC(ef442e67) SHA1(70ac91e2ca1ff2dfba48d566e4de68bd8b82f282) )
	7737	ROM_LOAD( "315-6358a.ic2", 0x000000, 0x020008, CRC(ef442e67) SHA1(70ac91e2ca1ff2dfba48d566e4de68bd8b82f282) )
7738	7738
7739	7739	// this dump can't be used as main_eeprom, because that's exactly 0x80 bytes
7740	7740	ROM_REGION(0x84, "some_eeprom", 0)
7741		ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(ddedf494) SHA1(f1529615711a9871051cd09c2a9b95c90d356874) )
	7741	ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(ddedf494) SHA1(f1529615711a9871051cd09c2a9b95c90d356874) )
7742	7742	ROM_END
7743	7743
7744	7744	ROM_START( clubkrte )
r29404	r29405
7790	7790	NAOMI_DEFAULT_EEPROM
7791	7791
7792	7792	ROM_REGION( 0x9000000, "rom_board", ROMREGION_ERASEFF)
7793		ROM_LOAD( "epr-24065.ic11", 0x000000, 0x400000, CRC(7c331cb8) SHA1(f7e1cffbad576482a91bc1dc9129c689f0bebb25) )
7794		ROM_LOAD32_WORD( "opr-24066.17s", 0x1000000, 0x800000, CRC(b22cfa7b) SHA1(e0f795dc9d3a2dd1869f85f3eedd0f8d703a1be8) )
7795		ROM_LOAD32_WORD( "opr-24067.18", 0x1000002, 0x800000, CRC(0d2d1290) SHA1(a26fa82fc87d6ed60095b2e778b649fcbb8bb1ee) )
7796		ROM_LOAD32_WORD( "opr-24068.19s", 0x2000000, 0x800000, CRC(d320009b) SHA1(76677eacd18770d091fc19e31be3d84410ed3256) )
7797		ROM_LOAD32_WORD( "opr-24069.20", 0x2000002, 0x800000, CRC(56145c73) SHA1(a74a97a431a315f86a1b25d1fc9cc1fb93146776) )
7798		ROM_LOAD32_WORD( "opr-24070.21s", 0x3000000, 0x800000, CRC(10a0c315) SHA1(337902393e215d94954f123c6b016925486c3374) )
7799		ROM_LOAD32_WORD( "opr-24071.22", 0x3000002, 0x800000, CRC(040e1329) SHA1(cebf8bc48a745811bcc6bce0ad880eca392428f9) )
7800		ROM_LOAD32_WORD( "opr-24072.23s", 0x4000000, 0x800000, CRC(1e9834e4) SHA1(a226689190739a39016b78c881f92b9bbb8d830e) )
7801		ROM_LOAD32_WORD( "opr-24073.24", 0x4000002, 0x800000, CRC(51fb7d42) SHA1(fb0bffeb181b1f3efcfa22aabda1bea926d9048b) )
7802		ROM_LOAD32_WORD( "opr-24074.25s", 0x5000000, 0x800000, CRC(636625fe) SHA1(fffd766cf14e66d10071a342573535ac708f87b7) )
7803		ROM_LOAD32_WORD( "opr-24075.26", 0x5000002, 0x800000, CRC(9eee9689) SHA1(831ac7713cc4f47679609361f0e1c67bb028e795) )
7804		ROM_LOAD32_WORD( "opr-24076.27s", 0x6000000, 0x800000, CRC(a89a5555) SHA1(c2c0eeb50f1afe6c7c3d978a99c6eaac96062bf0) )
7805		ROM_LOAD32_WORD( "opr-24077.28", 0x6000002, 0x800000, CRC(1e11d0aa) SHA1(1cc4dd05e1fbd0fde669b40aa49098c14eafd035) )
7806		ROM_LOAD32_WORD( "opr-24078.29", 0x7000000, 0x800000, CRC(a83f5f88) SHA1(ef0787cf84847e74fa3bb38d7133d87607df84fb) )
7807		ROM_LOAD32_WORD( "opr-24079.30s", 0x7000002, 0x800000, CRC(57efa68f) SHA1(5dd863dfb035489de3bbb3c3f72ee5d87ec322be) )
7808		ROM_LOAD32_WORD( "opr-24080.31", 0x8000000, 0x800000, CRC(307c480e) SHA1(6e52f252f557988e52c42d495713a374507b5895) )
7809		ROM_LOAD32_WORD( "opr-24081.32s", 0x8000002, 0x800000, CRC(61085bdc) SHA1(48fe7f34bb5f50825b3c77d587e07f3adab1cf86) )
	7793	ROM_LOAD( "epr-24065.ic11", 0x000000, 0x400000, CRC(7c331cb8) SHA1(f7e1cffbad576482a91bc1dc9129c689f0bebb25) )
	7794	ROM_LOAD32_WORD( "opr-24066.17s", 0x1000000, 0x800000, CRC(b22cfa7b) SHA1(e0f795dc9d3a2dd1869f85f3eedd0f8d703a1be8) )
	7795	ROM_LOAD32_WORD( "opr-24067.18", 0x1000002, 0x800000, CRC(0d2d1290) SHA1(a26fa82fc87d6ed60095b2e778b649fcbb8bb1ee) )
	7796	ROM_LOAD32_WORD( "opr-24068.19s", 0x2000000, 0x800000, CRC(d320009b) SHA1(76677eacd18770d091fc19e31be3d84410ed3256) )
	7797	ROM_LOAD32_WORD( "opr-24069.20", 0x2000002, 0x800000, CRC(56145c73) SHA1(a74a97a431a315f86a1b25d1fc9cc1fb93146776) )
	7798	ROM_LOAD32_WORD( "opr-24070.21s", 0x3000000, 0x800000, CRC(10a0c315) SHA1(337902393e215d94954f123c6b016925486c3374) )
	7799	ROM_LOAD32_WORD( "opr-24071.22", 0x3000002, 0x800000, CRC(040e1329) SHA1(cebf8bc48a745811bcc6bce0ad880eca392428f9) )
	7800	ROM_LOAD32_WORD( "opr-24072.23s", 0x4000000, 0x800000, CRC(1e9834e4) SHA1(a226689190739a39016b78c881f92b9bbb8d830e) )
	7801	ROM_LOAD32_WORD( "opr-24073.24", 0x4000002, 0x800000, CRC(51fb7d42) SHA1(fb0bffeb181b1f3efcfa22aabda1bea926d9048b) )
	7802	ROM_LOAD32_WORD( "opr-24074.25s", 0x5000000, 0x800000, CRC(636625fe) SHA1(fffd766cf14e66d10071a342573535ac708f87b7) )
	7803	ROM_LOAD32_WORD( "opr-24075.26", 0x5000002, 0x800000, CRC(9eee9689) SHA1(831ac7713cc4f47679609361f0e1c67bb028e795) )
	7804	ROM_LOAD32_WORD( "opr-24076.27s", 0x6000000, 0x800000, CRC(a89a5555) SHA1(c2c0eeb50f1afe6c7c3d978a99c6eaac96062bf0) )
	7805	ROM_LOAD32_WORD( "opr-24077.28", 0x6000002, 0x800000, CRC(1e11d0aa) SHA1(1cc4dd05e1fbd0fde669b40aa49098c14eafd035) )
	7806	ROM_LOAD32_WORD( "opr-24078.29", 0x7000000, 0x800000, CRC(a83f5f88) SHA1(ef0787cf84847e74fa3bb38d7133d87607df84fb) )
	7807	ROM_LOAD32_WORD( "opr-24079.30s", 0x7000002, 0x800000, CRC(57efa68f) SHA1(5dd863dfb035489de3bbb3c3f72ee5d87ec322be) )
	7808	ROM_LOAD32_WORD( "opr-24080.31", 0x8000000, 0x800000, CRC(307c480e) SHA1(6e52f252f557988e52c42d495713a374507b5895) )
	7809	ROM_LOAD32_WORD( "opr-24081.32s", 0x8000002, 0x800000, CRC(61085bdc) SHA1(48fe7f34bb5f50825b3c77d587e07f3adab1cf86) )
7810	7810
7811	7811	ROM_COPY( "rom_board", 0x1000000, 0x400000, 0xc00000 )
7812	7812
7813	7813	// this dump can't be used as main_eeprom, because that's exactly 0x80 bytes
7814	7814	ROM_REGION(0x84, "some_eeprom", 0)
7815		ROM_LOAD( "at25010.ic3s", 0x000000, 0x000084, CRC(0142d8be) SHA1(5922b6c47b12b19e1fa7bbe9aae391905038a7ff) )
	7815	ROM_LOAD( "at25010.ic3s", 0x000000, 0x000084, CRC(0142d8be) SHA1(5922b6c47b12b19e1fa7bbe9aae391905038a7ff) )
7816	7816
7817		ROM_REGION( 4, "rom_key", 0 ) // 317-0368-COM
7818		ROM_LOAD( "clubkprz-key.bin", 0x000000, 0x000004, CRC(c9ed13c1) SHA1(2907985375cd5b04846e7214d200926be64d06fd) )
	7817	ROM_REGION( 4, "rom_key", 0 ) // 317-0368-COM
	7818	ROM_LOAD( "clubkprz-key.bin", 0x000000, 0x000004, CRC(c9ed13c1) SHA1(2907985375cd5b04846e7214d200926be64d06fd) )
7819	7819	ROM_END
7820	7820
7821	7821	ROM_START( clubkpzb )
r29404	r29405
7823	7823	NAOMI_DEFAULT_EEPROM
7824	7824
7825	7825	ROM_REGION( 0x9000000, "rom_board", ROMREGION_ERASEFF)
7826		ROM_LOAD( "epr-24149.ic11", 0x000000, 0x400000, CRC(175b57a5) SHA1(de8ddd140c39d62a10d90ec46060d84c3b226c6b) )
7827		ROM_LOAD32_WORD( "opr-24178.ic17s", 0x1000000, 0x800000, CRC(836764ca) SHA1(e91cf7abeb27013d33726029d060075fa6352610) )
7828		ROM_LOAD32_WORD( "opr-24179.ic18", 0x1000002, 0x800000, CRC(03a0eb5b) SHA1(3f377d5a13d54c40c521f0faf6d50dc4fc077bb7) )
7829		ROM_LOAD32_WORD( "opr-24180.ic19s", 0x2000000, 0x800000, CRC(6a6c41f4) SHA1(3b01476b0483ce5e2f7e208e618ad56769b5c064) )
7830		ROM_LOAD32_WORD( "opr-24181.ic20", 0x2000002, 0x800000, CRC(38fd96fd) SHA1(c26ffc01529b4533c5e1448a774fa6e5f7e08080) )
7831		ROM_LOAD32_WORD( "opr-24182.ic21s", 0x3000000, 0x800000, CRC(b1116d71) SHA1(c840ae3602055528e4282283e5bc99465c6b5d28) )
7832		ROM_LOAD32_WORD( "opr-24183.ic22", 0x3000002, 0x800000, CRC(c1aef164) SHA1(e9a830a3a4bac4f5b2b40615bc43036aa0dd0a56) )
7833		ROM_LOAD32_WORD( "opr-24184.ic23s", 0x4000000, 0x800000, CRC(4ce1b902) SHA1(41b2fb02e3b9a0bb6ea8c7d77a9fb92248d62bcc) )
7834		ROM_LOAD32_WORD( "opr-24185.ic24", 0x4000002, 0x800000, CRC(94a4e6ab) SHA1(8738fcc75becf2acd5bc2c1be75e9a5c35359973) )
7835		ROM_LOAD32_WORD( "opr-24186.ic25s", 0x5000000, 0x800000, CRC(6884d0e9) SHA1(74ef002a752fcd377c5e6e6c17334ca22e561c76) )
7836		ROM_LOAD32_WORD( "opr-24187.ic26", 0x5000002, 0x800000, CRC(87c79534) SHA1(ab6e5246c388d0839ea6a45c8d2db035b33cd1d2) )
7837		ROM_LOAD32_WORD( "opr-24188.ic27s", 0x6000000, 0x800000, CRC(cfe107a2) SHA1(2f98bc00aa2b2eea0a26452542098c389f5e836c) )
7838		ROM_LOAD32_WORD( "opr-24189.ic28", 0x6000002, 0x800000, CRC(302de147) SHA1(442204439c509a6aa7dd25156bf17fb3853ae632) )
7839		ROM_LOAD32_WORD( "opr-24190.ic29", 0x7000000, 0x800000, CRC(71551313) SHA1(4b43d754b9511ae2d73ec04d7baf0e466337a82f) )
7840		ROM_LOAD32_WORD( "opr-24191.ic30s", 0x7000002, 0x800000, CRC(200cbeaf) SHA1(ccca2b873177d148a391cfcc8b1632856bd0e3b4) )
7841		ROM_LOAD32_WORD( "opr-24192.ic31", 0x8000000, 0x800000, CRC(869ef0ce) SHA1(227189dedfa72c56d9eedf5faeed9a4fd0a8393f) )
7842		ROM_LOAD32_WORD( "opr-24193.ic32s", 0x8000002, 0x800000, CRC(fb39946d) SHA1(d9fa077869709c6fda640bd4be18cf3db7ebe1d1) )
	7826	ROM_LOAD( "epr-24149.ic11", 0x000000, 0x400000, CRC(175b57a5) SHA1(de8ddd140c39d62a10d90ec46060d84c3b226c6b) )
	7827	ROM_LOAD32_WORD( "opr-24178.ic17s", 0x1000000, 0x800000, CRC(836764ca) SHA1(e91cf7abeb27013d33726029d060075fa6352610) )
	7828	ROM_LOAD32_WORD( "opr-24179.ic18", 0x1000002, 0x800000, CRC(03a0eb5b) SHA1(3f377d5a13d54c40c521f0faf6d50dc4fc077bb7) )
	7829	ROM_LOAD32_WORD( "opr-24180.ic19s", 0x2000000, 0x800000, CRC(6a6c41f4) SHA1(3b01476b0483ce5e2f7e208e618ad56769b5c064) )
	7830	ROM_LOAD32_WORD( "opr-24181.ic20", 0x2000002, 0x800000, CRC(38fd96fd) SHA1(c26ffc01529b4533c5e1448a774fa6e5f7e08080) )
	7831	ROM_LOAD32_WORD( "opr-24182.ic21s", 0x3000000, 0x800000, CRC(b1116d71) SHA1(c840ae3602055528e4282283e5bc99465c6b5d28) )
	7832	ROM_LOAD32_WORD( "opr-24183.ic22", 0x3000002, 0x800000, CRC(c1aef164) SHA1(e9a830a3a4bac4f5b2b40615bc43036aa0dd0a56) )
	7833	ROM_LOAD32_WORD( "opr-24184.ic23s", 0x4000000, 0x800000, CRC(4ce1b902) SHA1(41b2fb02e3b9a0bb6ea8c7d77a9fb92248d62bcc) )
	7834	ROM_LOAD32_WORD( "opr-24185.ic24", 0x4000002, 0x800000, CRC(94a4e6ab) SHA1(8738fcc75becf2acd5bc2c1be75e9a5c35359973) )
	7835	ROM_LOAD32_WORD( "opr-24186.ic25s", 0x5000000, 0x800000, CRC(6884d0e9) SHA1(74ef002a752fcd377c5e6e6c17334ca22e561c76) )
	7836	ROM_LOAD32_WORD( "opr-24187.ic26", 0x5000002, 0x800000, CRC(87c79534) SHA1(ab6e5246c388d0839ea6a45c8d2db035b33cd1d2) )
	7837	ROM_LOAD32_WORD( "opr-24188.ic27s", 0x6000000, 0x800000, CRC(cfe107a2) SHA1(2f98bc00aa2b2eea0a26452542098c389f5e836c) )
	7838	ROM_LOAD32_WORD( "opr-24189.ic28", 0x6000002, 0x800000, CRC(302de147) SHA1(442204439c509a6aa7dd25156bf17fb3853ae632) )
	7839	ROM_LOAD32_WORD( "opr-24190.ic29", 0x7000000, 0x800000, CRC(71551313) SHA1(4b43d754b9511ae2d73ec04d7baf0e466337a82f) )
	7840	ROM_LOAD32_WORD( "opr-24191.ic30s", 0x7000002, 0x800000, CRC(200cbeaf) SHA1(ccca2b873177d148a391cfcc8b1632856bd0e3b4) )
	7841	ROM_LOAD32_WORD( "opr-24192.ic31", 0x8000000, 0x800000, CRC(869ef0ce) SHA1(227189dedfa72c56d9eedf5faeed9a4fd0a8393f) )
	7842	ROM_LOAD32_WORD( "opr-24193.ic32s", 0x8000002, 0x800000, CRC(fb39946d) SHA1(d9fa077869709c6fda640bd4be18cf3db7ebe1d1) )
7843	7843
7844	7844	ROM_COPY( "rom_board", 0x1000000, 0x400000, 0xc00000 )
7845	7845
7846	7846	ROM_REGION( 4, "rom_key", ROMREGION_ERASE00 )
7847		ROM_LOAD( "clubkprz-key.bin", 0x000000, 0x000004, CRC(c9ed13c1) SHA1(2907985375cd5b04846e7214d200926be64d06fd) )
	7847	ROM_LOAD( "clubkprz-key.bin", 0x000000, 0x000004, CRC(c9ed13c1) SHA1(2907985375cd5b04846e7214d200926be64d06fd) )
7848	7848
7849	7849	// this dump can't be used as main_eeprom, because that's exactly 0x80 bytes
7850	7850	ROM_REGION(0x84, "some_eeprom", 0)
7851		ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(afff6471) SHA1(c1e1d349ff25191eba09cd7d7186fbe2c6565b81) )
	7851	ROM_LOAD( "sflash.bin", 0x000000, 0x000084, CRC(afff6471) SHA1(c1e1d349ff25191eba09cd7d7186fbe2c6565b81) )
7852	7852	ROM_END
7853	7853
7854	7854	// needs verification is this dump really from 840-0139C cart, mask rom labels not known
r29404	r29405
8188	8188
8189	8189	ROM_REGION( 0x4000, "pic", ROMREGION_ERASEFF)
8190	8190	//PIC16C621A (317-0406-COM)
8191		//(sticker 253-5508-0406)
	8191	//(sticker 253-5508-0406)
8192	8192	ROM_LOAD("317-0406-com.pic", 0x00, 0x4000, NO_DUMP )
8193	8193	ROM_END
8194	8194
r29404	r29405
8757	8757	/* 0087 */ GAME( 2002, kingrt66, naomi2, naomi2, naomi, naomi_state, naomi2, ROT0, "Sega", "King of Route 66 (Rev A)", GAME_FLAGS )
8758	8758	/* 0095 */ GAME( 2002, soulsurf, naomi2, naomi2, naomi, naomi_state, naomi2, ROT0, "Sega", "Soul Surfer (Rev A)", GAME_FLAGS )
8759	8759	/* 0106 */ GAME( 2002, vf4evoct, naomi2, naomi2m1, naomi, naomi_state, vf4evoct, ROT0, "Sega", "Virtua Fighter 4 Evolution (Cartridge)", GAME_FLAGS )
8760		/* 0129 */ GAME( 2003, clubkprz, naomi2, naomi2m1, naomi, naomi_state, naomi2, ROT0, "Sega", "Club Kart Prize", GAME_FLAGS )
	8760	/* 0129 */ GAME( 2003, clubkprz, naomi2, naomi2m1, naomi, naomi_state, naomi2, ROT0, "Sega", "Club Kart Prize", GAME_FLAGS )
8761	8761	/* Note: the game's full name is exactly "Club Kart Prize Ver. B". The "Ver. B" does not denote a new revision of Club Kart Prize; the different 840- number confirms this. */
8762	8762	/* 0137 */ GAME( 2004, clubkpzb, naomi2, naomi2m1, naomi, naomi_state, naomi2, ROT0, "Sega", "Club Kart Prize Ver. B", GAME_FLAGS )
8763	8763	// needs verification is this dump really from 840-0139C cart

trunk/src/mame/drivers/jackie.c
r29404	r29405
76	76	required_device<gfxdecode_device> m_gfxdecode;
77	77	required_device<screen_device> m_screen;
78	78	required_device<palette_device> m_palette;
79
	79
80	80	int m_exp_bank;
81	81	tilemap_t *m_fg_tilemap;
82	82	tilemap_t *m_reel1_tilemap;

trunk/src/mame/drivers/bnstars.c
r29404	r29405
1259	1259	AM_RANGE(0x00000000, 0x001fffff) AM_ROM
1260	1260
1261	1261	AM_RANGE(0xfc800000, 0xfc800003) AM_WRITE(ms32_sound_w)
1262
	1262
1263	1263	AM_RANGE(0xfcc00004, 0xfcc00007) AM_READ(bnstars1_r )
1264	1264	AM_RANGE(0xfcc00008, 0xfcc0000b) AM_READ_PORT("IN4")
1265	1265	AM_RANGE(0xfcc00010, 0xfcc00013) AM_READ_PORT("IN5")
r29404	r29405
1282	1282	AM_RANGE(0xfce00e00, 0xfce00e03) AM_WRITE(bnstars1_mahjong_select_w) // ?
1283	1283
1284	1284	AM_RANGE(0xfd000000, 0xfd000003) AM_READ(ms32_sound_r)
1285
	1285
1286	1286	/* wrote together */
1287	1287	AM_RANGE(0xfd040000, 0xfd047fff) AM_RAM // priority ram
1288	1288	AM_RANGE(0xfd080000, 0xfd087fff) AM_RAM

trunk/src/mame/drivers/blackt96.c
r29404	r29405
329	329	AM_RANGE(0x207000, 0x207fff) AM_RAM_WRITE(bg_videoram7_w) AM_SHARE("spriteram7")
330	330
331	331
332		AM_RANGE(0x400000, 0x400fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
	332	AM_RANGE(0x400000, 0x400fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
333	333	AM_RANGE(0xc00000, 0xc03fff) AM_RAM // main ram
334	334
335	335	ADDRESS_MAP_END

trunk/src/mame/drivers/3x3puzzl.c
r29404	r29405
72	72	required_device<okim6295_device> m_oki;
73	73	required_device<gfxdecode_device> m_gfxdecode;
74	74	required_device<screen_device> m_screen;
75
	75
76	76	// screen updates
77	77	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
78	78

trunk/src/mame/drivers/realbrk.c
r29404	r29405
788	788	static MACHINE_CONFIG_DERIVED( pkgnsh, realbrk )
789	789	MCFG_CPU_MODIFY("maincpu")
790	790	MCFG_CPU_PROGRAM_MAP(pkgnsh_mem)
791
	791
792	792	MCFG_DEVICE_MODIFY("tmp68301")
793	793	MCFG_TMP68301_OUT_PARALLEL_CB(NULL)
794	794	MACHINE_CONFIG_END

trunk/src/mame/drivers/arcadia.c
r29404	r29405
18	18	World Darts
19	19	Xenon
20	20	World Trophy Soccer
21		Delta Command (N.Y Warriors)
22		Blastaball
23		Aaargh
24		Pharaohs Match
	21	Delta Command (N.Y Warriors)
	22	Blastaball
	23	Aaargh
	24	Pharaohs Match
25	25
26	26	Other Arcadia games (not dumped):
27	27
r29404	r29405
218	218	AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE(amiga_custom_r, amiga_custom_w) AM_SHARE("custom_regs")
219	219	AM_RANGE(0xe80000, 0xe8ffff) AM_READWRITE(amiga_autoconfig_r, amiga_autoconfig_w)
220	220	AM_RANGE(0xf80000, 0xffffff) AM_ROM AM_REGION("user1", 0) /* Kickstart BIOS */
221
	221
222	222	AM_RANGE(0x800000, 0x97ffff) AM_ROMBANK("bank2") AM_REGION("user3", 0)
223	223	AM_RANGE(0x980000, 0x9fbfff) AM_ROM AM_REGION("user2", 0)
224	224	AM_RANGE(0x9fc000, 0x9ffffd) AM_RAM AM_SHARE("nvram")
r29404	r29405
235	235	AM_RANGE(0xf80000, 0xffffff) AM_ROM AM_REGION("user1", 0) /* Kickstart BIOS */
236	236
237	237	AM_RANGE(0x800000, 0x97ffff) AM_ROMBANK("bank2") AM_REGION("user3", 0)
238		// AM_RANGE(0x980000, 0x9fefff) AM_ROM AM_REGION("user3", 0)
	238	// AM_RANGE(0x980000, 0x9fefff) AM_ROM AM_REGION("user3", 0)
239	239	AM_RANGE(0x9ff000, 0x9fffff) AM_RAM AM_SHARE("nvram")
240	240	AM_RANGE(0xf00000, 0xf7ffff) AM_ROM AM_REGION("user3", 0)
241	241	ADDRESS_MAP_END
r29404	r29405
915	915	#if 0
916	916	{
917	917	UINT8 *ROM = memregion(tag)->base();
918		// int size = memregion(tag)->bytes();
	918	// int size = memregion(tag)->bytes();
919	919
920	920	FILE *fp;
921	921	char filename[256];
r29404	r29405
962	962
963	963	/* OnePlay bios is encrypted, TenPlay is not */
964	964	biosrom = (UINT16 *)memregion("user2")->base();
965
	965
966	966	if (biosrom)
967	967	if (biosrom[0] != 0x4afc)
968	968	generic_decode("user2", 6, 1, 0, 2, 3, 4, 5, 7);

trunk/src/mame/drivers/supercrd.c
r29404	r29405
411	411	//static MC6845_INTERFACE( mc6845_intf )
412	412	//{
413	413	// false,
414		// 0,0,0,0, /* visarea adjustment */
	414	// 0,0,0,0, /* visarea adjustment */
415	415	// 4, /* number of pixels per video memory address */
416	416	// NULL, /* before pixel update callback */
417	417	// NULL, /* row update callback */

trunk/src/mame/drivers/gatron.c
r29404	r29405
19	19
20	20
21	21	* PCB1: PULL TABS.
22
	22
23	23	Board silkscreend:
24	24
25	25	GAME-A-TRON CORP.
r29404	r29405
72	72	Identified the unknown writes as a init sequence for 1x PSG sound device.
73	73	The type/class is unknown due to almost all devices are plastic covered.
74	74
75
	75
76	76	* PCB 3: BINGO.
77	77
78	78	The PCB doesn't looks like an official Game-A-Tron board. Maybe it's a bootleg,
r29404	r29405
190	190	Press "LADY LUCK TICKET" (key X) to play with Lady Luck (center) Ticket.
191	191	Press "BIG BAR TICKET" (key C) to play with Big Bar (right) Ticket.
192	192
193
	193
194	194	* Bingo:
195	195
196	196	Pressing SERVICE 1 (key 9) you enter the Test/Settings Mode. You can test
r29404	r29405
213	213	Press "CHANGE CARD" (key Z) to change for another card with a different set of numbers.
214	214	Press "START" (key X) to start the game.
215	215	Press "CHANGE GAME" (key C) to switch between games X-L-T-C-N-U.
216
217		Note that letters in games X-L-T-C-N-U are just references to the shape of the special
	216
	217	Note that letters in games X-L-T-C-N-U are just references to the shape of the special
218	218	numbers group inside the card, which will play.
219	219
220	220	You must setup double-ups to something different of 0 (default), to play with these
r29404	r29405
253	253
254	254	[2014-02-04]
255	255	- Added Bingo (1983). PCB seems bootleg, but the game looks legit.
256		- Worked from the scratch a whole set of inputs and button-lamps support for this game.
	256	- Worked from the scratch a whole set of inputs and button-lamps support for this game.
257	257	- Changed the poker41 description to Four in One Poker (as seen in the official brochure).
258		- Added game and technical notes.
	258	- Added game and technical notes.
259	259
260	260	[2008-10-14]
261	261	- Improved the button-lamps layouts to look more realistic.
r29404	r29405
625	625	GAMEL( 1983, poker41, 0, gat, poker41, driver_device, 0, ROT0, "Game-A-Tron", "Four in One Poker", 0, layout_poker41 )
626	626	GAMEL( 1983, pulltabs, 0, gat, pulltabs, driver_device, 0, ROT0, "Game-A-Tron", "Pull Tabs", 0, layout_pulltabs )
627	627	GAMEL( 1983, bingo, 0, gat, bingo, driver_device, 0, ROT0, "Game-A-Tron?", "Bingo", 0, layout_bingo )
628

trunk/src/mame/drivers/dreamwld.c
r29404	r29405
223	223	{
224	224	for (xct = 0; xct < xsize; xct++)
225	225	{
226		gfx->transpen(bitmap,cliprect, redirect[tileno], colour, xflip, yflip, xpos + xct * xinc, ypos + yct * yinc, 0);
227		gfx->transpen(bitmap,cliprect, redirect[tileno], colour, xflip, yflip, (xpos + xct * xinc) - 0x200, ypos + yct * yinc, 0);
228		gfx->transpen(bitmap,cliprect, redirect[tileno], colour, xflip, yflip, (xpos + xct * xinc) - 0x200, (ypos + yct * yinc) - 0x200, 0);
229		gfx->transpen(bitmap,cliprect, redirect[tileno], colour, xflip, yflip, xpos + xct * xinc, (ypos + yct * yinc) - 0x200 , 0);
	226	gfx->transpen(bitmap,cliprect, redirect[tileno], colour, xflip, yflip, xpos + xct * xinc, ypos + yct * yinc, 0);
	227	gfx->transpen(bitmap,cliprect, redirect[tileno], colour, xflip, yflip, (xpos + xct * xinc) - 0x200, ypos + yct * yinc, 0);
	228	gfx->transpen(bitmap,cliprect, redirect[tileno], colour, xflip, yflip, (xpos + xct * xinc) - 0x200, (ypos + yct * yinc) - 0x200, 0);
	229	gfx->transpen(bitmap,cliprect, redirect[tileno], colour, xflip, yflip, xpos + xct * xinc, (ypos + yct * yinc) - 0x200 , 0);
230	230
231	231	tileno++;
232	232	}

trunk/src/mame/drivers/firefox.c
r29404	r29405
730	730
731	731
732	732	MCFG_LASERDISC_22VP931_ADD("laserdisc")
733		MCFG_LASERDISC_OVERLAY_DRIVER(64*8, 525, firefox_state, screen_update_firefox)
	733	MCFG_LASERDISC_OVERLAY_DRIVER(64*8, 525, firefox_state, screen_update_firefox)
734	734	MCFG_LASERDISC_OVERLAY_CLIP(78, 538-1, 44, 480+44)
735	735	MCFG_LASERDISC_OVERLAY_PALETTE("palette")
736	736

trunk/src/mame/drivers/galaga.c
r29404	r29405
1623	1623
1624	1624	MCFG_NAMCO_50XX_ADD("50xx_1", MASTER_CLOCK/6/2) /* 1.536 MHz */
1625	1625	MCFG_NAMCO_50XX_ADD("50xx_2", MASTER_CLOCK/6/2) /* 1.536 MHz */
1626		MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2) /* 1.536 MHz */
	1626	MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2) /* 1.536 MHz */
1627	1627	MCFG_NAMCO_51XX_INPUT_0_CB(IOPORT("IN0L"))
1628	1628	MCFG_NAMCO_51XX_INPUT_1_CB(IOPORT("IN0H"))
1629	1629	MCFG_NAMCO_51XX_INPUT_2_CB(IOPORT("IN1L"))
1630	1630	MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("IN1H"))
1631	1631	MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(galaga_state,out_0))
1632	1632	MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(galaga_state,out_1))
1633
1634
	1633
	1634
1635	1635	MCFG_NAMCO_52XX_ADD("52xx", MASTER_CLOCK/6/2) /* 1.536 MHz */
1636	1636	MCFG_NAMCO_52XX_DISCRETE("discrete")
1637	1637	MCFG_NAMCO_52XX_BASENODE(NODE_04)
r29404	r29405
1642	1642	MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/6/2) /* 1.536 MHz */
1643	1643	MCFG_NAMCO_54XX_DISCRETE("discrete")
1644	1644	MCFG_NAMCO_54XX_BASENODE(NODE_01)
1645
	1645
1646	1646	MCFG_NAMCO_06XX_ADD("06xx_0", MASTER_CLOCK/6/64)
1647	1647	MCFG_NAMCO_06XX_MAINCPU("maincpu")
1648	1648	MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read))
1649		MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
	1649	MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
1650	1650	MCFG_NAMCO_06XX_READ_2_CB(DEVREAD8("50xx_1", namco_50xx_device, read))
1651	1651	MCFG_NAMCO_06XX_READ_REQUEST_2_CB(DEVWRITELINE("50xx_1", namco_50xx_device, read_request))
1652		MCFG_NAMCO_06XX_WRITE_2_CB(DEVWRITE8("50xx_1", namco_50xx_device, write))
	1652	MCFG_NAMCO_06XX_WRITE_2_CB(DEVWRITE8("50xx_1", namco_50xx_device, write))
1653	1653	MCFG_NAMCO_06XX_WRITE_3_CB(DEVWRITE8("54xx", namco_54xx_device, write))
1654
	1654
1655	1655	MCFG_NAMCO_06XX_ADD("06xx_1", MASTER_CLOCK/6/64)
1656	1656	MCFG_NAMCO_06XX_MAINCPU("sub")
1657	1657	MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("50xx_2", namco_50xx_device, read))
1658	1658	MCFG_NAMCO_06XX_READ_REQUEST_0_CB(DEVWRITELINE("50xx_2", namco_50xx_device, read_request))
1659		MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("50xx_2", namco_50xx_device, write))
	1659	MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("50xx_2", namco_50xx_device, write))
1660	1660	MCFG_NAMCO_06XX_WRITE_1_CB(DEVWRITE8("52xx", namco_52xx_device, write))
1661	1661
1662	1662	MCFG_WATCHDOG_VBLANK_INIT(8)
r29404	r29405
1712	1712	MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("IN1H"))
1713	1713	MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(galaga_state,out_0))
1714	1714	MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(galaga_state,out_1))
1715
	1715
1716	1716	MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/6/2) /* 1.536 MHz */
1717	1717	MCFG_NAMCO_54XX_DISCRETE("discrete")
1718	1718	MCFG_NAMCO_54XX_BASENODE(NODE_01)
r29404	r29405
1720	1720	MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64)
1721	1721	MCFG_NAMCO_06XX_MAINCPU("maincpu")
1722	1722	MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read))
1723		MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
	1723	MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
1724	1724	MCFG_NAMCO_06XX_WRITE_3_CB(DEVWRITE8("54xx", namco_54xx_device, write))
1725
	1725
1726	1726	MCFG_WATCHDOG_VBLANK_INIT(8)
1727	1727	MCFG_QUANTUM_TIME(attotime::from_hz(6000)) /* 100 CPU slices per frame - an high value to ensure proper */
1728	1728	/* synchronization of the CPUs */
r29404	r29405
1766	1766	MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64)
1767	1767	MCFG_NAMCO_06XX_MAINCPU("maincpu")
1768	1768	MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read))
1769		MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
1770
	1769	MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
	1770
1771	1771	MCFG_CPU_ADD("sub3", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
1772	1772	MCFG_CPU_PROGRAM_MAP(galaga_mem4)
1773	1773
r29404	r29405
1798	1798	MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("IN1H"))
1799	1799	MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(galaga_state,out_0))
1800	1800	MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(galaga_state,out_1))
1801
	1801
1802	1802	MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/6/2) /* 1.536 MHz */
1803	1803	MCFG_NAMCO_54XX_DISCRETE("discrete")
1804	1804	MCFG_NAMCO_54XX_BASENODE(NODE_01)
r29404	r29405
1806	1806	MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64)
1807	1807	MCFG_NAMCO_06XX_MAINCPU("maincpu")
1808	1808	MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read))
1809		MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
	1809	MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
1810	1810	MCFG_NAMCO_06XX_READ_2_CB(DEVREAD8("50xx", namco_50xx_device, read))
1811	1811	MCFG_NAMCO_06XX_READ_REQUEST_2_CB(DEVWRITELINE("50xx", namco_50xx_device, read_request))
1812		MCFG_NAMCO_06XX_WRITE_2_CB(DEVWRITE8("50xx", namco_50xx_device, write))
	1812	MCFG_NAMCO_06XX_WRITE_2_CB(DEVWRITE8("50xx", namco_50xx_device, write))
1813	1813	MCFG_NAMCO_06XX_WRITE_3_CB(DEVWRITE8("54xx", namco_54xx_device, write))
1814	1814
1815	1815	MCFG_WATCHDOG_VBLANK_INIT(8)
r29404	r29405
1855	1855	MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64)
1856	1856	MCFG_NAMCO_06XX_MAINCPU("maincpu")
1857	1857	MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read))
1858		MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
	1858	MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
1859	1859
1860	1860	MCFG_CPU_ADD("sub3", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
1861	1861	MCFG_CPU_PROGRAM_MAP(battles_mem4)
r29404	r29405
1897	1897	MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("IN1H"))
1898	1898	MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(galaga_state,out_0))
1899	1899	MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(galaga_state,out_1))
1900
	1900
1901	1901	MCFG_NAMCO_53XX_ADD("53xx", MASTER_CLOCK/6/2) /* 1.536 MHz */
1902	1902	MCFG_NAMCO_53XX_K_CB(READ8(galaga_state,custom_mod_r))
1903	1903	MCFG_NAMCO_53XX_INPUT_0_CB(IOPORT("DSWA"))
r29404	r29405
1908	1908	MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64)
1909	1909	MCFG_NAMCO_06XX_MAINCPU("maincpu")
1910	1910	MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read))
1911		MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
	1911	MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write))
1912	1912	MCFG_NAMCO_06XX_READ_1_CB(DEVREAD8("53xx", namco_53xx_device, read))
1913	1913	MCFG_NAMCO_06XX_READ_REQUEST_1_CB(DEVWRITELINE("53xx", namco_53xx_device, read_request))
1914	1914

trunk/src/mame/drivers/panicr.c
r29404	r29405
618	618	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
619	619	MCFG_SCREEN_SIZE(328, 328)
620	620	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
621		MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 28, 308-1)
	621	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 28, 308-1)
622	622	MCFG_SCREEN_UPDATE_DRIVER(panicr_state, screen_update_panicr)
623	623	MCFG_SCREEN_PALETTE("palette")
624	624

trunk/src/mame/drivers/xyonix.c
r29404	r29405
238	238
239	239	MCFG_SOUND_ADD("sn1", SN76496, 16000000/4)
240	240	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
241
	241
242	242	MCFG_SOUND_ADD("sn2", SN76496, 16000000/4)
243	243	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
244	244	MACHINE_CONFIG_END

trunk/src/mame/drivers/wardner.c
r29404	r29405
164	164	static ADDRESS_MAP_START( main_program_map, AS_PROGRAM, 8, wardner_state )
165	165	AM_RANGE(0x0000, 0x6fff) AM_ROM
166	166	AM_RANGE(0x7000, 0x7fff) AM_RAM
167		AM_RANGE(0x8000, 0x8fff) AM_WRITE(wardner_sprite_w) // AM_SHARE("spriteram8")
168		AM_RANGE(0xa000, 0xafff) AM_DEVWRITE("palette", palette_device, write) // AM_SHARE("palette")
	167	AM_RANGE(0x8000, 0x8fff) AM_WRITE(wardner_sprite_w) // AM_SHARE("spriteram8")
	168	AM_RANGE(0xa000, 0xafff) AM_DEVWRITE("palette", palette_device, write) // AM_SHARE("palette")
169	169	AM_RANGE(0xc000, 0xc7ff) AM_WRITEONLY AM_SHARE("sharedram")
170	170	AM_RANGE(0x8000, 0xffff) AM_DEVREAD("membank", address_map_bank_device, read8)
171	171	ADDRESS_MAP_END

trunk/src/mame/drivers/mirage.c
r29404	r29405
340	340	MCFG_DECO16IC_ADD("tilegen1", mirage_deco16ic_tilegen1_intf)
341	341	MCFG_DECO16IC_GFXDECODE("gfxdecode")
342	342	MCFG_DECO16IC_PALETTE("palette")
343
	343
344	344	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
345	345	decospr_device::set_gfx_region(*device, 2);
346	346	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")

trunk/src/mame/drivers/sidearms.c
r29404	r29405
719	719	MCFG_SCREEN_PALETTE("palette")
720	720
721	721	MCFG_GFXDECODE_ADD("gfxdecode", "palette", turtship)
722
	722
723	723	MCFG_PALETTE_ADD("palette", 1024)
724	724	MCFG_PALETTE_FORMAT(xxxxBBBBRRRRGGGG)
725	725

trunk/src/mame/drivers/kingobox.c
r29404	r29405
490	490	MCFG_SCREEN_SIZE(328, 328)
491	491	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 28, 308-1)
492	492	MCFG_SCREEN_UPDATE_DRIVER(kingofb_state, screen_update_kingofb)
493		MCFG_SCREEN_PALETTE("palette")
	493	MCFG_SCREEN_PALETTE("palette")
494	494
495	495	MCFG_GFXDECODE_ADD("gfxdecode", "palette", kingobox)
496	496	MCFG_PALETTE_ADD("palette", 256+8*2)

trunk/src/mame/drivers/galivan.c
r29404	r29405
441	441	MCFG_PALETTE_ADD("palette", 816+1616+256*16)
442	442	MCFG_PALETTE_INDIRECT_ENTRIES(256)
443	443	MCFG_PALETTE_INIT_OWNER(galivan_state, galivan)
444
	444
445	445	MCFG_VIDEO_START_OVERRIDE(galivan_state,galivan)
446	446
447	447	/* sound hardware */

trunk/src/mame/drivers/f1gp.c
r29404	r29405
186	186
187	187	static ADDRESS_MAP_START( f1gpb_cpu2_map, AS_PROGRAM, 16, f1gp_state )
188	188	AM_RANGE(0x000000, 0x01ffff) AM_ROM
189		AM_RANGE(0xff8000, 0xffbfff) AM_RAM
	189	AM_RANGE(0xff8000, 0xffbfff) AM_RAM
190	190	AM_RANGE(0xffc000, 0xffcfff) AM_RAM AM_SHARE("sharedram")
191	191	AM_RANGE(0xfff030, 0xfff031) AM_NOP //?
192	192	ADDRESS_MAP_END
r29404	r29405
442	442	MCFG_VSYSTEM_SPR2_SET_PRITYPE(2)
443	443	MCFG_VSYSTEM_SPR2_GFXDECODE("gfxdecode")
444	444	MCFG_VSYSTEM_SPR2_PALETTE("palette")
445
	445
446	446	MCFG_DEVICE_ADD("vsystem_spr_ol2", VSYSTEM_SPR2, 0)
447	447	MCFG_VSYSTEM_SPR2_SET_TILE_INDIRECT( f1gp_state, f1gp_ol2_tile_callback )
448	448	MCFG_VSYSTEM_SPR2_SET_GFXREGION(2)

trunk/src/mame/drivers/chicago.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	Chicago Coin discrete hardware games
4
	4
5	5	Game Name Model #
6		-----------------------------------------
	6	-----------------------------------------
7	7	Demolition Derby (1976) #466
8	8	Super Flipper (1975) #458
9	9	Olympic TV Football (1973) #429-A
r29404	r29405
12	12	TV Ping Pong (1973) #424
13	13	TV Pin Game (1975) #451
14	14	TV Tennis (1973) #427
15
	15
16	16	***************************************************************************/
17	17
18	18
r29404	r29405
52	52	public:
53	53	chicago_state(const machine_config &mconfig, device_type type, const char *tag)
54	54	: driver_device(mconfig, type, tag),
55		m_maincpu(*this, "maincpu"),
56		m_video(*this, "fixfreq")
	55	m_maincpu(*this, "maincpu"),
	56	m_video(*this, "fixfreq")
57	57	{
58	58	}
59
	59
60	60	// devices
61	61	required_device<netlist_mame_device_t> m_maincpu;
62	62	required_device<fixedfreq_device> m_video;
63
	63
64	64	protected:
65
	65
66	66	// driver_device overrides
67	67	virtual void machine_start();
68	68	virtual void machine_reset();
69
	69
70	70	virtual void video_start();
71
	71
72	72	private:
73
	73
74	74	};
75	75
76	76
77	77	static NETLIST_START(chicago)
78	78	SOLVER(Solver, 48000)
79		// PARAM(Solver.FREQ, 48000)
	79	// PARAM(Solver.FREQ, 48000)
80	80	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
81	81
82	82	// schematics
83	83	//...
84	84
85		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
86		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	85	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	86	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
87	87	NETLIST_END()
88	88
89	89
r29404	r29405
113	113
114	114
115	115	/***************************************************************************
116
	116
117	117	Game driver(s)
118
	118
119	119	***************************************************************************/
120	120
121	121

trunk/src/mame/drivers/m63.c
r29404	r29405
347	347	flipy = !flipy;
348	348	}
349	349
350
	350
351	351	m_gfxdecode->gfx(2)->transpen(bitmap,cliprect,
352	352	code, color,
353	353	flipx, flipy,
r29404	r29405
356	356	/* sprite wrapping - verified on real hardware*/
357	357	if (sx > 0xf0)
358	358	{
359
360	359	m_gfxdecode->gfx(2)->transpen(bitmap,cliprect,
361	360	code, color,
362	361	flipx, flipy,

trunk/src/mame/drivers/blstroid.c
r29404	r29405
183	183
184	184	/* video hardware */
185	185	MCFG_GFXDECODE_ADD("gfxdecode", "palette", blstroid)
186
	186
187	187	MCFG_PALETTE_ADD("palette", 512)
188	188	MCFG_PALETTE_FORMAT(xRRRRRGGGGGBBBBB)
189	189

trunk/src/mame/drivers/dotrikun.c
r29404	r29405
43	43	virtual void machine_reset();
44	44	UINT32 screen_update_dotrikun(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
45	45	required_device<cpu_device> m_maincpu;
46		required_device<screen_device> m_screen;
	46	required_device<screen_device> m_screen;
47	47	};
48	48
49	49

trunk/src/mame/drivers/flipjack.c
r29404	r29405
98	98	m_vram(*this, "vram"),
99	99	m_cram(*this, "cram"),
100	100	m_gfxdecode(*this, "gfxdecode"),
101		m_palette(*this, "palette")
	101	m_palette(*this, "palette")
102	102	{
103	103	m_soundlatch = 0;
104	104	m_bank = 0;
r29404	r29405
112	112	required_shared_ptr<UINT8> m_fbram;
113	113	required_shared_ptr<UINT8> m_vram;
114	114	required_shared_ptr<UINT8> m_cram;
115
	115
116	116	required_device<gfxdecode_device> m_gfxdecode;
117	117	required_device<palette_device> m_palette;
118	118
r29404	r29405
204	204	int tile = m_bank << 8 \| m_vram[x+y*0x100];
205	205	int color = m_cram[x+y*0x100] & 0x3f;
206	206
207		gfx->transpen(bitmap,cliprect, tile, color, 0, 0, x8, y8, 0);
	207	gfx->transpen(bitmap,cliprect, tile, color, 0, 0, x8, y8, 0);
208	208	}
209	209	}
210	210

trunk/src/mame/drivers/bladestl.c
r29404	r29405
334	334	MCFG_K007342_GFXNUM(0)
335	335	MCFG_K007342_CALLBACK_OWNER(bladestl_state, bladestl_tile_callback)
336	336	MCFG_K007342_GFXDECODE("gfxdecode")
337
	337
338	338	MCFG_K007420_ADD("k007420")
339	339	MCFG_K007420_BANK_LIMIT(0x3ff)
340		MCFG_K007420_CALLBACK_OWNER(bladestl_state, bladestl_sprite_callback)
	340	MCFG_K007420_CALLBACK_OWNER(bladestl_state, bladestl_sprite_callback)
341	341	MCFG_K007420_PALETTE("palette")
342
	342
343	343	MCFG_K051733_ADD("k051733")
344	344
345	345	/* sound hardware */

trunk/src/mame/drivers/funworld.c
r29404	r29405
6	6	65C02 + 2x PIAs + M6845 CRTC + AY8910
7	7
8	8	Also from Amatic, CMC, Dino4 encrypted, and Leopard 4.
9
	9
10	10	Driver by Roberto Fresca.
11	11	Based on a preliminary work of Curt Coder & Peter Trauner.
12	12
r29404	r29405
159	159	complex operations for each byte nibble. See DRIVER_INIT for the final algorithm.
160	160	- Saloon (french) use bitswaps to address & data in program, graphics and color PROM.
161	161	- Dino4 hardware games have address/data bitswap in program, and data bitswap (sometimes
162		with extra boolean XOR operations) in graphics.
	162	with extra boolean XOR operations) in graphics.
163	163
164	164	- Microcontroller. Some games (like Soccer New and Mongolfier New are using an extra MCU mainly
165	165	for protection.
166
	166
167	167	- Mirrored video and color RAM. A derivative of CMC hardware uses this trick to avoid ROM swaps.
168	168	If you run Luna Park in a regular CMC board, you'll get an unplayable mess of graphics.
169	169
r29404	r29405
226	226	Also PRG rom higher address line is connected to DIP switch #1 so it should have 2 games
227	227	in the same PCB (2 revisions?).
228	228
229
	229
230	230	There is at least one missing game in the family... 'Hyppo Family', also from C.M.C.
231	231	This game should be located and dumped.
232	232
r29404	r29405
416	416
417	417	Press DEAL/DRAW to exit the mode.
418	418
419
	419
420	420	* Unknown Royal Card on Dino4 hardware....
421
	421
422	422	This one is really strange. The game is running in a Dino4 hardware, plus a daughterboard
423	423	with a mexican Rockwell R65C02 + an unknown PLCC. The program/gfx are totally decrypted.
424	424	The game vectors are $C122 (RESET) and $C20F (IRQ)
425
	425
426	426	The code starts...
427
	427
428	428	C122: A2 FF LDX #$FF ; load 0xFF to reg X
429	429	C124: 9A TXS ; transfer to the stack
430	430	C125: 78 SEI ; set interrupts
r29404	r29405
437	437	C132: A9 C2 LDA #$C2 ; /
438	438	C134: 8D 02 00 STA $0002 ;/
439	439	C137: 4C DC 48 JMP $48DC ; jump to $48DC...
440
	440
441	441	48DC: 93 NOP ;\
442	442	48DD: 00 BRK ; \
443	443	48DE: B7 4B SMB3 $4B ; \
r29404	r29405
446	446	48E3: B7 4D SMB3 $4B ; /
447	447	48E5: 05 B7 ORA $B7 ;/
448	448	48E7: 4C 05 76 JMP $7605 ; jump to $7605 (no code there)
449
	449
450	450	And the IRQ vector pointed code... does nothing!
451
	451
452	452	C20F: 40 RTI ; return from interrupt
453
	453
454	454	And the code pointed from $0000...
455
	455
456	456	C210: 48 PHA ; transfer accumulator to stack
457	457	C211: AD 01 0A LDA $0A01 ; read the PIA #2 input
458	458	C214: 29 F7 AND #$F7 ; \ compare with 0xF7
r29404	r29405
472	472	Maybe mnemonic 93 is AXA (ab),Y (93 ab) instead of NOP (as seen in some sources)??...
473	473
474	474	Tooo much obscure/darkness here
475
	475
476	476	So... No idea what's wrong here.
477	477	If someone could figure a possible transform, please let me know.
478
479
	478
	479
480	480	***********************************************************************************
481	481
482	482
r29404	r29405
530	530	rcdino4: 0x7C 0x60 0x65 0x08 0x21 0x08 0x1F 0x1F 0x00 0x07 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00.
531	531	chinatow: 0x7C 0x60 0x65 0x08 0x21 0x08 0x1F 0x1F 0x00 0x07 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00.
532	532
533
	533
534	534	***********************************************************************************
535	535
536	536
r29404	r29405
1147	1147	AM_RANGE(0x0e01, 0x0e01) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
1148	1148	AM_RANGE(0x2000, 0x2000) AM_READNOP /* some unknown reads */
1149	1149	AM_RANGE(0x3e00, 0x3fff) AM_RAM /* some games use $3e03-05 range for protection */
1150		AM_RANGE(0x4000, 0x5fff) AM_ROM /* used by rcdino4 (dino4 hw ) */
	1150	AM_RANGE(0x4000, 0x5fff) AM_ROM /* used by rcdino4 (dino4 hw ) */
1151	1151	AM_RANGE(0x6000, 0x6fff) AM_RAM_WRITE(funworld_videoram_w) AM_SHARE("videoram")
1152	1152	AM_RANGE(0x7000, 0x7fff) AM_RAM_WRITE(funworld_colorram_w) AM_SHARE("colorram")
1153	1153	AM_RANGE(0x8000, 0xffff) AM_ROM
r29404	r29405
1158	1158	{
1159	1159	logerror("read from 0x32f0 at offset %02X\n",offset);
1160	1160	switch (offset)
1161		{
1162		case 0: return 0xfe;
1163
1164		}
	1161	{
	1162	case 0: return 0xfe;
	1163
	1164	}
1165	1165	return 0xff;
1166	1166	}
1167	1167
r29404	r29405
1175	1175	AM_RANGE(0x0e01, 0x0e01) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
1176	1176	AM_RANGE(0x2000, 0x2000) AM_READNOP /* some unknown reads */
1177	1177	AM_RANGE(0x32f0, 0x32ff) AM_READ(chinatow_r_32f0)
1178		AM_RANGE(0x4000, 0x5fff) AM_ROM /* used by rcdino4 (dino4 hw ) */
	1178	AM_RANGE(0x4000, 0x5fff) AM_ROM /* used by rcdino4 (dino4 hw ) */
1179	1179	AM_RANGE(0x6000, 0x6fff) AM_RAM_WRITE(funworld_videoram_w) AM_SHARE("videoram")
1180	1180	AM_RANGE(0x7000, 0x7fff) AM_RAM_WRITE(funworld_colorram_w) AM_SHARE("colorram")
1181	1181	AM_RANGE(0x8000, 0xffff) AM_ROM
1182	1182	ADDRESS_MAP_END
1183	1183
1184		static ADDRESS_MAP_START( lunapark_map, AS_PROGRAM, 8, funworld_state ) // mirrored video RAM 4000/5000 to 6000/7000
	1184	static ADDRESS_MAP_START( lunapark_map, AS_PROGRAM, 8, funworld_state ) // mirrored video RAM 4000/5000 to 6000/7000
1185	1185	AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("nvram")
1186	1186	AM_RANGE(0x0800, 0x0803) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
1187	1187	AM_RANGE(0x0a00, 0x0a03) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
r29404	r29405
2024	2024	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2025	2025
2026	2026	/* the following one seems to be disconnected
2027		to avoid the use of remote credits or direct payout */
	2027	to avoid the use of remote credits or direct payout */
2028	2028	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
2029	2029
2030	2030	/* the following one is connected to 1st DSW and is meant
2031		for switch between different programs stored in different
2032		halves of the program ROM */
	2031	for switch between different programs stored in different
	2032	halves of the program ROM */
2033	2033	PORT_START("SELDSW")
2034	2034	PORT_DIPNAME( 0x01, 0x00, "Game Selector" ) PORT_DIPLOCATION("SW1:1")
2035	2035	PORT_DIPSETTING( 0x00, "PROGRAM 1, (5 TIRI LIRE 500, ABILITA VINTE)" )
r29404	r29405
2622	2622	INPUT_PORTS_END
2623	2623
2624	2624	static INPUT_PORTS_START( chinatow )
2625		PORT_START("IN0")
2626		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* no remote credits */
2627		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_HOLD1 ) PORT_NAME("Stop 1 / Switch Bet (1-Max)")
2628		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_CANCEL ) PORT_NAME("Clear / Bet / Prendi (Take)")
2629		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME("Start / Gioca (Play) / Gmable")
2630		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD5 ) PORT_NAME("Stop 5 / Half Gamble / Super Game")
2631		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 )
2632		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE2 )
2633		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_POKER_HOLD4 ) PORT_NAME("Stop 4 / Alta (High)")
2634
2635		PORT_START("IN1")
2636		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_HOLD2 ) PORT_NAME("Stop 2 / Bassa (Low)")
2637		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_HOLD3 ) PORT_NAME("Stop 3")
2638		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Ticket") PORT_CODE(KEYCODE_8)
2639		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Hopper") PORT_CODE(KEYCODE_H)
2640		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2641		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
2642		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2643		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT )
2644
2645		PORT_START("IN2")
2646		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
2647		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN )
2648		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
2649		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN )
2650		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2651		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
2652		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2653		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
2654
2655		PORT_START("DSW")
2656		PORT_DIPNAME( 0x01, 0x01, "Test Mode" ) PORT_DIPLOCATION("SW1:8")
2657		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
2658		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2659		PORT_DIPNAME( 0x02, 0x02, "Counter" ) PORT_DIPLOCATION("SW1:7")
2660		PORT_DIPSETTING( 0x02, "X10" )
2661		PORT_DIPSETTING( 0x00, "X1" )
2662		PORT_DIPNAME( 0x04, 0x04, "Royal Flush" ) PORT_DIPLOCATION("SW1:6")
2663		PORT_DIPSETTING( 0x04, "With" )
2664		PORT_DIPSETTING( 0x00, "Without" )
2665		PORT_DIPNAME( 0x08, 0x08, "5 of a kind" ) PORT_DIPLOCATION("SW1:5")
2666		PORT_DIPSETTING( 0x08, "With" )
2667		PORT_DIPSETTING( 0x00, "Without" )
2668		PORT_DIPNAME( 0x60, 0x60, "Payout type" ) PORT_DIPLOCATION("SW1:3,2")
2669		PORT_DIPSETTING( 0x00, "Ticket + Hopper" )
2670		PORT_DIPSETTING( 0x20, "Ticket" )
2671		PORT_DIPSETTING( 0x40, "Hopper" )
2672		PORT_DIPSETTING( 0x60, "Ticket + Hopper" )
2673		PORT_DIPNAME( 0x90, 0x90, "Coin/Credit ratio" ) PORT_DIPLOCATION("SW1:1,4")
2674		PORT_DIPSETTING( 0x00, "1 coin 1 credit" )
2675		PORT_DIPSETTING( 0x10, "1 coin 1 credit" )
2676		PORT_DIPSETTING( 0x80, "1 coin 5 credits" )
2677		PORT_DIPSETTING( 0x90, "1 coin 10 credits" )
2678		INPUT_PORTS_END
	2625	PORT_START("IN0")
	2626	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* no remote credits */
	2627	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_HOLD1 ) PORT_NAME("Stop 1 / Switch Bet (1-Max)")
	2628	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_CANCEL ) PORT_NAME("Clear / Bet / Prendi (Take)")
	2629	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME("Start / Gioca (Play) / Gmable")
	2630	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD5 ) PORT_NAME("Stop 5 / Half Gamble / Super Game")
	2631	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 )
	2632	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE2 )
	2633	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_POKER_HOLD4 ) PORT_NAME("Stop 4 / Alta (High)")
2679	2634
	2635	PORT_START("IN1")
	2636	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_HOLD2 ) PORT_NAME("Stop 2 / Bassa (Low)")
	2637	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_HOLD3 ) PORT_NAME("Stop 3")
	2638	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Ticket") PORT_CODE(KEYCODE_8)
	2639	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Hopper") PORT_CODE(KEYCODE_H)
	2640	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2641	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
	2642	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2643	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT )
	2644
	2645	PORT_START("IN2")
	2646	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
	2647	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	2648	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2649	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	2650	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2651	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	2652	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2653	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	2654
	2655	PORT_START("DSW")
	2656	PORT_DIPNAME( 0x01, 0x01, "Test Mode" ) PORT_DIPLOCATION("SW1:8")
	2657	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	2658	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	2659	PORT_DIPNAME( 0x02, 0x02, "Counter" ) PORT_DIPLOCATION("SW1:7")
	2660	PORT_DIPSETTING( 0x02, "X10" )
	2661	PORT_DIPSETTING( 0x00, "X1" )
	2662	PORT_DIPNAME( 0x04, 0x04, "Royal Flush" ) PORT_DIPLOCATION("SW1:6")
	2663	PORT_DIPSETTING( 0x04, "With" )
	2664	PORT_DIPSETTING( 0x00, "Without" )
	2665	PORT_DIPNAME( 0x08, 0x08, "5 of a kind" ) PORT_DIPLOCATION("SW1:5")
	2666	PORT_DIPSETTING( 0x08, "With" )
	2667	PORT_DIPSETTING( 0x00, "Without" )
	2668	PORT_DIPNAME( 0x60, 0x60, "Payout type" ) PORT_DIPLOCATION("SW1:3,2")
	2669	PORT_DIPSETTING( 0x00, "Ticket + Hopper" )
	2670	PORT_DIPSETTING( 0x20, "Ticket" )
	2671	PORT_DIPSETTING( 0x40, "Hopper" )
	2672	PORT_DIPSETTING( 0x60, "Ticket + Hopper" )
	2673	PORT_DIPNAME( 0x90, 0x90, "Coin/Credit ratio" ) PORT_DIPLOCATION("SW1:1,4")
	2674	PORT_DIPSETTING( 0x00, "1 coin 1 credit" )
	2675	PORT_DIPSETTING( 0x10, "1 coin 1 credit" )
	2676	PORT_DIPSETTING( 0x80, "1 coin 5 credits" )
	2677	PORT_DIPSETTING( 0x90, "1 coin 10 credits" )
	2678	INPUT_PORTS_END
	2679
2680	2680	static INPUT_PORTS_START( royal )
2681	2681	PORT_START("IN0")
2682	2682	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* no remote credits */
r29404	r29405
2993	2993	MCFG_CPU_PROGRAM_MAP(magicrd2_map)
2994	2994	MCFG_CPU_VBLANK_INT_DRIVER("screen", funworld_state, nmi_line_pulse)
2995	2995	MCFG_VIDEO_START_OVERRIDE(funworld_state, magicrd2)
2996
	2996
2997	2997	MCFG_DEVICE_REMOVE("crtc")
2998	2998	MCFG_MC6845_ADD("crtc", MC6845, "screen", CRTC_CLOCK, magicrd2_mc6845_intf)
2999	2999
r29404	r29405
3048	3048
3049	3049	static MACHINE_CONFIG_DERIVED( lunapark, fw1stpal )
3050	3050	MCFG_CPU_REPLACE("maincpu", R65C02, CPU_CLOCK) /* 2MHz */
3051		MCFG_CPU_PROGRAM_MAP(lunapark_map) // mirrored video RAM (4000/5000 to 6000/7000).
	3051	MCFG_CPU_PROGRAM_MAP(lunapark_map) // mirrored video RAM (4000/5000 to 6000/7000).
3052	3052	MCFG_CPU_VBLANK_INT_DRIVER("screen", funworld_state, nmi_line_pulse)
3053	3053	MCFG_MACHINE_START_OVERRIDE(funworld_state, lunapark)
3054	3054	MCFG_MACHINE_RESET_OVERRIDE(funworld_state, lunapark)
r29404	r29405
3460	3460
3461	3461	then service1+service2 and reset,
3462	3462	then another reset.
3463
	3463
3464	3464	Q is remote (x100)
3465	3465	W is payout.
3466	3466	*/
r29404	r29405
3489	3489
3490	3490	then service1+service2 and reset,
3491	3491	then another reset.
3492
	3492
3493	3493	This set has spam graphics, but seems
3494	3494	used by another program.
3495
	3495
3496	3496	*/
3497	3497	ROM_START( jolycdie ) /* Bootleg PCB, NON encrypted graphics */
3498	3498	ROM_REGION( 0x10000, "maincpu", 0 )
r29404	r29405
4114	4114	ROM_START( pool10f )
4115	4115	ROM_REGION( 0x10000, "maincpu", 0 )
4116	4116	ROM_LOAD( "cmc-pool10+a+.u2", 0x8000, 0x8000, CRC(e8087fb8) SHA1(c012a81f561978bd97708a52f656e7b13e41a3e2) )
4117
	4117
4118	4118	ROM_REGION( 0x10000, "gfx1", 0 )
4119	4119	ROM_LOAD( "cmc-pool10-b.u21", 0x0000, 0x8000, CRC(99c8c074) SHA1(f8082b08e895cbcd028a2b7cd961a7a2c8b2762c) )
4120	4120	ROM_LOAD( "cmc-pool10-c.u20", 0x8000, 0x8000, CRC(9abedd0c) SHA1(f184a82e8ec2387069d631bcb77e890acd44b3f5) )
r29404	r29405
4168	4168	ROM_REGION( 0x10000, "maincpu", 0 )
4169	4169	ROM_LOAD( "a.u2", 0x8000, 0x8000, CRC(566bc05d) SHA1(eec88c8ba6cb664f38ebf8b71f99b4e7d04a9601) )
4170	4170	ROM_IGNORE( 0x8000 ) /* Identical halves. Discarding 2nd half */
4171
	4171
4172	4172	ROM_REGION( 0x10000, "gfx1", 0 )
4173	4173	ROM_LOAD( "b.u21", 0x0000, 0x8000, CRC(581c4878) SHA1(5ae61af090feea1745e22f46b33b2c01e6013fbe) )
4174	4174	ROM_IGNORE( 0x8000 ) /* Identical halves. Discarding 2nd half */
4175	4175	ROM_LOAD( "c.u20", 0x8000, 0x8000, CRC(3bdf1106) SHA1(fa21cbd49bb27ea4a784cf4e4b3fbd52650a285b) )
4176	4176	ROM_IGNORE( 0x8000 ) /* Identical halves. Discarding 2nd half */
4177
	4177
4178	4178	ROM_REGION( 0x0800, "nvram", 0 ) /* default NVRAM */
4179	4179	ROM_LOAD( "pool10l_nvram.bin", 0x0000, 0x0800, CRC(89cbee4b) SHA1(ff8031a96ee40e1e62abbae7a0b3d9dc2122759f) )
4180	4180
r29404	r29405
4338	4338
4339	4339	The second set, has the same programs, but the strings on the first half
4340	4340	were changed to match the second program.
4341
	4341
4342	4342	*/
4343	4343	/* The following two have mirrored video RAM 4000/5000 to 6000/7000. */
4344	4344	ROM_START( lunapark )
4345		ROM_REGION( 0x10000, "maincpu", 0 ) /* Two different programs. Selectable through a DIP switch */
	4345	ROM_REGION( 0x10000, "maincpu", 0 ) /* Two different programs. Selectable through a DIP switch */
4346	4346	ROM_LOAD( "lunapark-425-95n003.u2", 0x0000, 0x10000, CRC(b3a620ee) SHA1(67b3498edf7b536e22c4d97c1f6ad5a71521e68f) )
4347	4347
4348	4348	ROM_REGION( 0x10000, "gfx1", 0 )
4349	4349	ROM_LOAD( "lunapark-425-95n002.u21", 0x0000, 0x8000, CRC(2bededb7) SHA1(b8d7e6fe307d347d762adf35d361ade620aab37b) )
4350		ROM_CONTINUE( 0x0000, 0x8000) /* Discarding 1nd half 0xff filled*/
	4350	ROM_CONTINUE( 0x0000, 0x8000) /* Discarding 1nd half 0xff filled*/
4351	4351	ROM_LOAD( "lunapark-425-95n001.u20", 0x8000, 0x8000, CRC(7d91ce1f) SHA1(7e9bfad76f305d5787faffe3a07b218beb37fda8) )
4352		ROM_CONTINUE( 0x8000, 0x8000) /* Discarding 1nd half 0xff filled*/
	4352	ROM_CONTINUE( 0x8000, 0x8000) /* Discarding 1nd half 0xff filled*/
4353	4353
4354	4354	ROM_REGION( 0x0800, "nvram", 0 ) /* default NVRAM */
4355	4355	ROM_LOAD( "lunapark_nvram.bin", 0x0000, 0x0800, CRC(f99e749b) SHA1(fafd4205dfaacb4c21215af6997d06ab419c9281) )
r29404	r29405
4359	4359	ROM_END
4360	4360
4361	4361	ROM_START( lunaparkb )
4362		ROM_REGION( 0x10000, "maincpu", 0 ) /* Two different programs. Selectable through a DIP switch */
	4362	ROM_REGION( 0x10000, "maincpu", 0 ) /* Two different programs. Selectable through a DIP switch */
4363	4363	ROM_LOAD( "lunapark-number-03_lunaparkb.u2", 0x0000, 0x10000, CRC(cb819bb7) SHA1(c7fb25eab093de2f644445a713d99ee8024d8499) )
4364	4364
4365	4365	ROM_REGION( 0x10000, "gfx1", 0 )
4366		ROM_LOAD( "27512.u21", 0x0000, 0x8000, CRC(d64ac315) SHA1(c67d9e67a988036844efd4f980d47a90c022ba18) ) /* only the first 2 bytes different */
4367		ROM_CONTINUE( 0x0000, 0x8000) /* Discarding 1nd half 0xff filled*/
	4366	ROM_LOAD( "27512.u21", 0x0000, 0x8000, CRC(d64ac315) SHA1(c67d9e67a988036844efd4f980d47a90c022ba18) ) /* only the first 2 bytes different */
	4367	ROM_CONTINUE( 0x0000, 0x8000) /* Discarding 1nd half 0xff filled*/
4368	4368	ROM_LOAD( "27512.u20", 0x8000, 0x8000, CRC(7d91ce1f) SHA1(7e9bfad76f305d5787faffe3a07b218beb37fda8 ) )
4369		ROM_CONTINUE( 0x8000, 0x8000) /* Discarding 1nd half 0xff filled*/
	4369	ROM_CONTINUE( 0x8000, 0x8000) /* Discarding 1nd half 0xff filled*/
4370	4370
4371	4371	ROM_REGION( 0x0800, "nvram", 0 ) /* default NVRAM */
4372	4372	ROM_LOAD( "lunaparkb_nvram.bin", 0x0000, 0x0800, CRC(f99e749b) SHA1(fafd4205dfaacb4c21215af6997d06ab419c9281) )
r29404	r29405
5684	5684
5685	5685	ROM_REGION( 0x10000, "gfx1", 0 )
5686	5686	ROM_LOAD( "27c512.u2", 0x0000, 0x8000, CRC(6ace221f) SHA1(d35a6621d9d9231a844d7043da78035855ebf572) )
5687		ROM_CONTINUE( 0x0000, 0x8000) /* Discarding 1nd half 0xff filled*/
	5687	ROM_CONTINUE( 0x0000, 0x8000) /* Discarding 1nd half 0xff filled*/
5688	5688	ROM_LOAD( "27c512.u20", 0x8000, 0x8000, CRC(efb7f1ec) SHA1(260005526fc9b4087ca03f7cc585e40b6fa007fb) )
5689		ROM_CONTINUE( 0x8000, 0x8000) /* Discarding 1nd half 0xff filled*/
5690
	5689	ROM_CONTINUE( 0x8000, 0x8000) /* Discarding 1nd half 0xff filled*/
	5690
5691	5691	ROM_REGION( 0x0800, "nvram", 0 ) /* default NVRAM */
5692	5692	ROM_LOAD( "chinatow_nvram.bin", 0x0000, 0x0800, CRC(eef4c5e7) SHA1(a2d9a9f617d35ccb99236114e5ce3257ad572f49) )
5693	5693
r29404	r29405
5787	5787	UINT8 *ROM = memregion("maincpu")->base();
5788	5788
5789	5789	ROM[0x9115] = 0xa5;
5790
	5790
5791	5791	/* prevent one test from triggering hardware error */
5792	5792	ROM[0xb8f3] = 0xff;
5793	5793	}
r29404	r29405
5801	5801	ROM[0x80b2] = 0xa9;
5802	5802	ROM[0x80b3] = 0x00;
5803	5803	ROM[0x9115] = 0xa5;
5804
	5804
5805	5805	/* prevent one test from triggering hardware error */
5806	5806	ROM[0xb8f3] = 0xff;
5807	5807	}
r29404	r29405
5867	5867	rom[a] = buffer[i];
5868	5868	}
5869	5869	}
5870
5871	5870
	5871
5872	5872	/******************************
5873	5873	* Graphics ROM decryption *
5874	5874	******************************/
r29404	r29405
6171	6171	}
6172	6172	}
6173	6173
6174
	6174
6175	6175	/******************************
6176	6176	* Graphics ROM decryption *
6177	6177	******************************/
r29404	r29405
6190	6190	}
6191	6191
6192	6192	/* d4-d5 data lines swap, plus a XOR with 0x81, implemented in two steps for an easy view */
6193
	6193
6194	6194	int x;
6195	6195	UINT8 *src = memregion( "gfx1" )->base();
6196	6196
r29404	r29405
6199	6199	src[x] = BITSWAP8(src[x], 7, 6, 4, 5, 3, 2, 1, 0);
6200	6200	src[x] = src[x] ^ 0x81;
6201	6201	}
6202
	6202
6203	6203	}
6204	6204
6205	6205	/**********************************************
r29404	r29405
6219	6219	GAMEL( 1985, sjcd2kx3, jollycrd, fw1stpal, funworld, driver_device, 0, ROT0, "M.P.", "Super Joly 2000 - 3x", 0, layout_jollycrd )
6220	6220	GAME( 1986, jolycdab, jollycrd, fw1stpal, funworld, driver_device, 0, ROT0, "Inter Games", "Jolly Card (Austrian, Fun World, bootleg)", GAME_NOT_WORKING )
6221	6221	GAMEL( 1992, jolycdsp, jollycrd, cuoreuno, jolycdit, funworld_state, ctunk, ROT0, "TAB Austria", "Jolly Card (Spanish, blue TAB board, encrypted)", 0, layout_royalcrd )
6222		GAMEL( 1990, jolycdid, jollycrd, cuoreuno, jolycdcr, driver_device, 0, ROT0, "bootleg", "Jolly Card (Italian, different colors, set 1)", 0, layout_jollycrd ) // italian, CPLD, different colors.
	6222	GAMEL( 1990, jolycdid, jollycrd, cuoreuno, jolycdcr, driver_device, 0, ROT0, "bootleg", "Jolly Card (Italian, different colors, set 1)", 0, layout_jollycrd ) // italian, CPLD, different colors.
6223	6223	GAMEL( 1990, jolycdie, jollycrd, cuoreuno, jolycdib, driver_device, 0, ROT0, "bootleg", "Jolly Card (Italian, different colors, set 2)", 0, layout_jollycrd ) // not from TAB blue PCB
6224	6224
6225	6225	// Bonus Card based...
r29404	r29405
6246	6246	GAMEL( 1996, potgame, 0, cuoreuno, cuoreuno, driver_device, 0, ROT0, "C.M.C.", "Pot Game (Italian)", 0, layout_jollycrd )
6247	6247	GAMEL( 1996, bottle10, 0, cuoreuno, cuoreuno, driver_device, 0, ROT0, "C.M.C.", "Bottle 10 (Italian, set 1)", 0, layout_jollycrd )
6248	6248	GAMEL( 1996, bottl10b, bottle10, cuoreuno, cuoreuno, driver_device, 0, ROT0, "C.M.C.", "Bottle 10 (Italian, set 2)", 0, layout_jollycrd )
6249		GAMEL( 1998, lunapark, 0, lunapark, lunapark, driver_device, 0, ROT0, "<unknown>", "Luna Park (set 1, dual program)", 0, layout_jollycrd ) // mirrored video RAM (4000/5000 to 6000/7000).
6250		GAMEL( 1998, lunaparkb, lunapark, lunapark, lunapark, driver_device, 0, ROT0, "<unknown>", "Luna Park (set 2, dual program)", 0, layout_jollycrd ) // mirrored video RAM (4000/5000 to 6000/7000).
6251		GAMEL( 1998, lunaparkc, lunapark, cuoreuno, cuoreuno, driver_device, 0, ROT0, "<unknown>", "Luna Park (set 3)", 0, layout_jollycrd ) // regular video RAM 6000/7000.
	6249	GAMEL( 1998, lunapark, 0, lunapark, lunapark, driver_device, 0, ROT0, "<unknown>", "Luna Park (set 1, dual program)", 0, layout_jollycrd ) // mirrored video RAM (4000/5000 to 6000/7000).
	6250	GAMEL( 1998, lunaparkb, lunapark, lunapark, lunapark, driver_device, 0, ROT0, "<unknown>", "Luna Park (set 2, dual program)", 0, layout_jollycrd ) // mirrored video RAM (4000/5000 to 6000/7000).
	6251	GAMEL( 1998, lunaparkc, lunapark, cuoreuno, cuoreuno, driver_device, 0, ROT0, "<unknown>", "Luna Park (set 3)", 0, layout_jollycrd ) // regular video RAM 6000/7000.
6252	6252	GAMEL( 1998, crystal, 0, cuoreuno, cuoreuno, driver_device, 0, ROT0, "J.C.D. srl", "Crystal Colours (CMC hardware)", 0, layout_jollycrd )
6253	6253
6254	6254	// Royal Card based...

trunk/src/mame/drivers/overdriv.c
r29404	r29405
350	350	MCFG_PALETTE_ENABLE_SHADOWS()
351	351
352	352	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
353
	353
354	354	MCFG_K053246_ADD("k053246", overdriv_k053246_intf)
355	355	MCFG_K053246_GFXDECODE("gfxdecode")
356	356	MCFG_K053246_PALETTE("palette")
r29404	r29405
363	363	MCFG_K053251_ADD("k053251")
364	364	MCFG_K053250_ADD("k053250_1", "palette", "screen", 0, 0)
365	365	MCFG_K053250_ADD("k053250_2", "palette", "screen", 0, 0)
366
	366
367	367	MCFG_DEVICE_ADD("k053252", K053252, 24000000/4)
368	368	MCFG_K053252_OFFSETS(138, 28)
369	369

trunk/src/mame/drivers/gsword.c
r29404	r29405
703	703	MCFG_CPU_VBLANK_INT_DRIVER("screen", gsword_state, irq0_line_hold)
704	704
705	705	MCFG_MACHINE_RESET_OVERRIDE(gsword_state,josvolly)
706
	706
707	707	MCFG_JOSVOLLY8741_ADD("josvolly_8741")
708	708	MCFG_JOSVOLLY8741_CONNECT(1,0,0,0)
709	709	MCFG_JOSVOLLY8741_PORT_HANDLERS(IOPORT("DSW1"),IOPORT("DSW2"),IOPORT("DSW1"),IOPORT("DSW2"))

trunk/src/mame/drivers/nmg5.c
r29404	r29405
267	267	required_device<cpu_device> m_soundcpu;
268	268	required_device<okim6295_device> m_oki;
269	269	required_device<gfxdecode_device> m_gfxdecode;
270
	270
271	271	DECLARE_WRITE16_MEMBER(fg_videoram_w);
272	272	DECLARE_WRITE16_MEMBER(bg_videoram_w);
273	273	DECLARE_WRITE16_MEMBER(nmg5_soundlatch_w);

trunk/src/mame/drivers/nbmj8900.c
r29404	r29405
316	316	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 8, 248-1)
317	317	MCFG_SCREEN_UPDATE_DRIVER(nbmj8900_state, screen_update_nbmj8900)
318	318	MCFG_SCREEN_PALETTE("palette")
319
	319
320	320	MCFG_PALETTE_ADD("palette", 256)
321	321
322	322

trunk/src/mame/drivers/xmen.c
r29404	r29405
359	359	MCFG_SCREEN_VISIBLE_AREA(138, (64-13)8-1, 28, 308-1 ) /* correct, same issue of TMNT2 */
360	360	MCFG_SCREEN_UPDATE_DRIVER(xmen_state, screen_update_xmen)
361	361	MCFG_SCREEN_PALETTE("palette")
362
	362
363	363	MCFG_PALETTE_ADD("palette", 2048)
364	364	MCFG_PALETTE_ENABLE_SHADOWS()
365	365	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
r29404	r29405
436	436	MCFG_K052109_ADD("k052109", xmen_k052109_intf)
437	437	MCFG_K052109_GFXDECODE("gfxdecode")
438	438	MCFG_K052109_PALETTE("palette")
439		MCFG_K053246_ADD("k053246", xmen6p_k053246_intf)
	439	MCFG_K053246_ADD("k053246", xmen6p_k053246_intf)
440	440	MCFG_K053246_SET_SCREEN("screen")
441	441	MCFG_K053246_GFXDECODE("gfxdecode")
442	442	MCFG_K053246_PALETTE("palette")

trunk/src/mame/drivers/lethal.c
r29404	r29405
598	598	MCFG_K053244_PALETTE("palette")
599	599	MACHINE_CONFIG_END
600	600
601		ROM_START( lethalen ) // US version UAE
602		ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
	601	ROM_START( lethalen ) // US version UAE
	602	ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
603	603	ROM_LOAD( "191uae01.u4", 0x00000, 0x40000, CRC(dca340e3) SHA1(8efbba0e3a459bcfe23c75c584bf3a4ce25148bb) )
604	604
605		ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
	605	ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
606	606	ROM_LOAD( "191a02.f4", 0x00000, 0x10000, CRC(72b843cc) SHA1(b44b2f039358c26fa792d740639b66a5c8bf78e7) )
607	607
608		ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
	608	ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
609	609	ROM_LOAD32_WORD( "191a08", 0x000002, 0x100000, CRC(555bd4db) SHA1(d2e55796b4ab2306ae549fa9e7288e41eaa8f3de) )
610	610	ROM_LOAD32_WORD( "191a10", 0x000000, 0x100000, CRC(2fa9bf51) SHA1(1e4ec56b41dfd8744347a7b5799e3ebce0939adc) )
611	611	ROM_LOAD32_WORD( "191a07", 0x200002, 0x100000, CRC(1dad184c) SHA1(b2c4a8e48084005056aef2c8eaccb3d2eca71b73) )
612	612	ROM_LOAD32_WORD( "191a09", 0x200000, 0x100000, CRC(e2028531) SHA1(63ccce7855d829763e9e248a6c3eb6ea89ab17ee) )
613	613
614		ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
	614	ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
615	615	ROM_LOAD( "191a04", 0x000000, 0x100000, CRC(5c3eeb2b) SHA1(33ea8b3968b78806334b5a0aab3a2c24e45c604e) )
616	616	ROM_LOAD( "191a05", 0x100000, 0x100000, CRC(f2e3b58b) SHA1(0bbc2fe87a4fd00b5073a884bcfebcf9c2c402ad) )
617	617	ROM_LOAD( "191a06", 0x200000, 0x100000, CRC(ee11fc08) SHA1(ec6dd684e8261b181d65b8bf1b9e97da5c4468f7) )
r29404	r29405
622	622	ROM_REGION( 0x200000, "gfx4", ROMREGION_ERASE00 )
623	623	ROM_COPY("gfx2",0x200000,0, 0x200000)
624	624
625		ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
	625	ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
626	626	ROM_LOAD( "191a03", 0x000000, 0x200000, CRC(9b13fbe8) SHA1(19b02dbd9d6da54045b0ba4dfe7b282c72745c9c))
627	627
628	628	ROM_REGION16_BE( 0x80, "eeprom", 0 )
629	629	ROM_LOAD( "lethalenue.nv", 0x0000, 0x0080, CRC(6e7224e6) SHA1(86dea9262d55e58b573d397d0fea437c58728707) )
630	630	ROM_END
631	631
632		ROM_START( lethalenub ) // US version UAB
633		ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
	632	ROM_START( lethalenub ) // US version UAB
	633	ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
634	634	ROM_LOAD( "191uab01.u4", 0x00000, 0x40000, CRC(2afd7528) SHA1(65ce4a54fe96ad38d39d335b5d3a644a495c7e31) )
635	635
636		ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
	636	ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
637	637	ROM_LOAD( "191a02.f4", 0x00000, 0x10000, CRC(72b843cc) SHA1(b44b2f039358c26fa792d740639b66a5c8bf78e7) )
638	638
639		ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
	639	ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
640	640	ROM_LOAD32_WORD( "191a08", 0x000002, 0x100000, CRC(555bd4db) SHA1(d2e55796b4ab2306ae549fa9e7288e41eaa8f3de) )
641	641	ROM_LOAD32_WORD( "191a10", 0x000000, 0x100000, CRC(2fa9bf51) SHA1(1e4ec56b41dfd8744347a7b5799e3ebce0939adc) )
642	642	ROM_LOAD32_WORD( "191a07", 0x200002, 0x100000, CRC(1dad184c) SHA1(b2c4a8e48084005056aef2c8eaccb3d2eca71b73) )
643	643	ROM_LOAD32_WORD( "191a09", 0x200000, 0x100000, CRC(e2028531) SHA1(63ccce7855d829763e9e248a6c3eb6ea89ab17ee) )
644	644
645		ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
	645	ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
646	646	ROM_LOAD( "191a04", 0x000000, 0x100000, CRC(5c3eeb2b) SHA1(33ea8b3968b78806334b5a0aab3a2c24e45c604e) )
647	647	ROM_LOAD( "191a05", 0x100000, 0x100000, CRC(f2e3b58b) SHA1(0bbc2fe87a4fd00b5073a884bcfebcf9c2c402ad) )
648	648	ROM_LOAD( "191a06", 0x200000, 0x100000, CRC(ee11fc08) SHA1(ec6dd684e8261b181d65b8bf1b9e97da5c4468f7) )
r29404	r29405
653	653	ROM_REGION( 0x200000, "gfx4", ROMREGION_ERASE00 )
654	654	ROM_COPY("gfx2",0x200000,0, 0x200000)
655	655
656		ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
	656	ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
657	657	ROM_LOAD( "191a03", 0x000000, 0x200000, CRC(9b13fbe8) SHA1(19b02dbd9d6da54045b0ba4dfe7b282c72745c9c))
658	658
659	659	ROM_REGION16_BE( 0x80, "eeprom", 0 )
660	660	ROM_LOAD( "lethalenub.nv", 0x0000, 0x0080, CRC(14c6c6e5) SHA1(8a498b5322266df25fb24d1b7bd7937de459d207) )
661	661	ROM_END
662	662
663		ROM_START( lethalenua ) // US version UAA
664		ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
	663	ROM_START( lethalenua ) // US version UAA
	664	ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
665	665	ROM_LOAD( "191uaa01.u4", 0x00000, 0x40000, CRC(ab6b8f16) SHA1(8de6c429a6e71144270e79d18ad47b5aad13fe04) )
666	666
667		ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
	667	ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
668	668	ROM_LOAD( "191a02.f4", 0x00000, 0x10000, CRC(72b843cc) SHA1(b44b2f039358c26fa792d740639b66a5c8bf78e7) )
669	669
670		ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
	670	ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
671	671	ROM_LOAD32_WORD( "191a08", 0x000002, 0x100000, CRC(555bd4db) SHA1(d2e55796b4ab2306ae549fa9e7288e41eaa8f3de) )
672	672	ROM_LOAD32_WORD( "191a10", 0x000000, 0x100000, CRC(2fa9bf51) SHA1(1e4ec56b41dfd8744347a7b5799e3ebce0939adc) )
673	673	ROM_LOAD32_WORD( "191a07", 0x200002, 0x100000, CRC(1dad184c) SHA1(b2c4a8e48084005056aef2c8eaccb3d2eca71b73) )
674	674	ROM_LOAD32_WORD( "191a09", 0x200000, 0x100000, CRC(e2028531) SHA1(63ccce7855d829763e9e248a6c3eb6ea89ab17ee) )
675	675
676		ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
	676	ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
677	677	ROM_LOAD( "191a04", 0x000000, 0x100000, CRC(5c3eeb2b) SHA1(33ea8b3968b78806334b5a0aab3a2c24e45c604e) )
678	678	ROM_LOAD( "191a05", 0x100000, 0x100000, CRC(f2e3b58b) SHA1(0bbc2fe87a4fd00b5073a884bcfebcf9c2c402ad) )
679	679	ROM_LOAD( "191a06", 0x200000, 0x100000, CRC(ee11fc08) SHA1(ec6dd684e8261b181d65b8bf1b9e97da5c4468f7) )
r29404	r29405
684	684	ROM_REGION( 0x200000, "gfx4", ROMREGION_ERASE00 )
685	685	ROM_COPY("gfx2",0x200000,0, 0x200000)
686	686
687		ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
	687	ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
688	688	ROM_LOAD( "191a03", 0x000000, 0x200000, CRC(9b13fbe8) SHA1(19b02dbd9d6da54045b0ba4dfe7b282c72745c9c))
689	689
690	690	ROM_REGION16_BE( 0x80, "eeprom", 0 )
691	691	ROM_LOAD( "lethalenua.nv", 0x0000, 0x0080, CRC(f71ad1c3) SHA1(04c7052d0895797af8a06183b8a877795bf2dbb3) )
692	692	ROM_END
693	693
694		ROM_START( lethalenux ) // US version ?, proto / hack?, very different to other sets
695		ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
	694	ROM_START( lethalenux ) // US version ?, proto / hack?, very different to other sets
	695	ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
696	696	ROM_LOAD( "191xxx01.u4", 0x00000, 0x40000, CRC(a3b9e790) SHA1(868b422850be129952c8b11c3c4aa730d8ea1544) ) // hacked? fails rom test, verified on multiple boards
697	697
698		ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
	698	ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
699	699	ROM_LOAD( "191a02.f4", 0x00000, 0x10000, CRC(72b843cc) SHA1(b44b2f039358c26fa792d740639b66a5c8bf78e7) )
700	700
701		ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
	701	ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
702	702	ROM_LOAD32_WORD( "191a08", 0x000002, 0x100000, CRC(555bd4db) SHA1(d2e55796b4ab2306ae549fa9e7288e41eaa8f3de) )
703	703	ROM_LOAD32_WORD( "191a10", 0x000000, 0x100000, CRC(2fa9bf51) SHA1(1e4ec56b41dfd8744347a7b5799e3ebce0939adc) )
704	704	ROM_LOAD32_WORD( "191a07", 0x200002, 0x100000, CRC(1dad184c) SHA1(b2c4a8e48084005056aef2c8eaccb3d2eca71b73) )
705	705	ROM_LOAD32_WORD( "191a09", 0x200000, 0x100000, CRC(e2028531) SHA1(63ccce7855d829763e9e248a6c3eb6ea89ab17ee) )
706	706
707		ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
	707	ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
708	708	ROM_LOAD( "191a04", 0x000000, 0x100000, CRC(5c3eeb2b) SHA1(33ea8b3968b78806334b5a0aab3a2c24e45c604e) )
709	709	ROM_LOAD( "191a05", 0x100000, 0x100000, CRC(f2e3b58b) SHA1(0bbc2fe87a4fd00b5073a884bcfebcf9c2c402ad) )
710	710	ROM_LOAD( "191a06", 0x200000, 0x100000, CRC(ee11fc08) SHA1(ec6dd684e8261b181d65b8bf1b9e97da5c4468f7) )
r29404	r29405
715	715	ROM_REGION( 0x200000, "gfx4", ROMREGION_ERASE00 )
716	716	ROM_COPY("gfx2",0x200000,0, 0x200000)
717	717
718		ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
	718	ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
719	719	ROM_LOAD( "191a03", 0x000000, 0x200000, CRC(9b13fbe8) SHA1(19b02dbd9d6da54045b0ba4dfe7b282c72745c9c))
720	720
721	721	ROM_REGION16_BE( 0x80, "eeprom", 0 )
722	722	ROM_LOAD( "lethalenux.nv", 0x0000, 0x0080, CRC(5d69c39d) SHA1(e468df829ee5094792289f9166d7e39b638ab70d) )
723	723	ROM_END
724	724
725		ROM_START( lethaleneab ) // Euro ver. EAB
726		ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
	725	ROM_START( lethaleneab ) // Euro ver. EAB
	726	ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
727	727	ROM_LOAD( "191eab01.u4", 0x00000, 0x40000, CRC(d7ce111e) SHA1(e56137a0ba7664f09b5d05bb39ec6eb4d1e412c7) )
728	728
729		ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
	729	ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
730	730	ROM_LOAD( "191a02.f4", 0x00000, 0x10000, CRC(72b843cc) SHA1(b44b2f039358c26fa792d740639b66a5c8bf78e7) )
731	731
732		ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
	732	ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
733	733	ROM_LOAD32_WORD( "191a08", 0x000002, 0x100000, CRC(555bd4db) SHA1(d2e55796b4ab2306ae549fa9e7288e41eaa8f3de) )
734	734	ROM_LOAD32_WORD( "191a10", 0x000000, 0x100000, CRC(2fa9bf51) SHA1(1e4ec56b41dfd8744347a7b5799e3ebce0939adc) )
735	735	ROM_LOAD32_WORD( "191a07", 0x200002, 0x100000, CRC(1dad184c) SHA1(b2c4a8e48084005056aef2c8eaccb3d2eca71b73) )
736	736	ROM_LOAD32_WORD( "191a09", 0x200000, 0x100000, CRC(e2028531) SHA1(63ccce7855d829763e9e248a6c3eb6ea89ab17ee) )
737	737
738		ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
	738	ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
739	739	ROM_LOAD( "191a04", 0x000000, 0x100000, CRC(5c3eeb2b) SHA1(33ea8b3968b78806334b5a0aab3a2c24e45c604e) )
740	740	ROM_LOAD( "191a05", 0x100000, 0x100000, CRC(f2e3b58b) SHA1(0bbc2fe87a4fd00b5073a884bcfebcf9c2c402ad) )
741	741	ROM_LOAD( "191a06", 0x200000, 0x100000, CRC(ee11fc08) SHA1(ec6dd684e8261b181d65b8bf1b9e97da5c4468f7) )
r29404	r29405
746	746	ROM_REGION( 0x200000, "gfx4", ROMREGION_ERASE00 )
747	747	ROM_COPY("gfx2",0x200000,0, 0x200000)
748	748
749		ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
	749	ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
750	750	ROM_LOAD( "191a03", 0x000000, 0x200000, CRC(9b13fbe8) SHA1(19b02dbd9d6da54045b0ba4dfe7b282c72745c9c))
751	751
752	752	ROM_REGION16_BE( 0x80, "eeprom", 0 )
753	753	ROM_LOAD( "lethaleneab.nv", 0x0000, 0x0080, CRC(4e9bb34d) SHA1(9502583bc9f5f6fc5bba333869398b24bf154b73) )
754	754	ROM_END
755	755
756		ROM_START( lethaleneae ) // Euro ver. EAE
757		ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
	756	ROM_START( lethaleneae ) // Euro ver. EAE
	757	ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
758	758	ROM_LOAD( "191eae01.u4", 0x00000, 0x40000, CRC(c6a3c6ac) SHA1(96a209a3a5b4af40af36bd7090c59a74f8c8df59) )
759	759
760		ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
	760	ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
761	761	ROM_LOAD( "191a02.f4", 0x00000, 0x10000, CRC(72b843cc) SHA1(b44b2f039358c26fa792d740639b66a5c8bf78e7) )
762	762
763		ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
	763	ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
764	764	ROM_LOAD32_WORD( "191a08", 0x000002, 0x100000, CRC(555bd4db) SHA1(d2e55796b4ab2306ae549fa9e7288e41eaa8f3de) )
765	765	ROM_LOAD32_WORD( "191a10", 0x000000, 0x100000, CRC(2fa9bf51) SHA1(1e4ec56b41dfd8744347a7b5799e3ebce0939adc) )
766	766	ROM_LOAD32_WORD( "191a07", 0x200002, 0x100000, CRC(1dad184c) SHA1(b2c4a8e48084005056aef2c8eaccb3d2eca71b73) )
767	767	ROM_LOAD32_WORD( "191a09", 0x200000, 0x100000, CRC(e2028531) SHA1(63ccce7855d829763e9e248a6c3eb6ea89ab17ee) )
768	768
769		ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
	769	ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
770	770	ROM_LOAD( "191a04", 0x000000, 0x100000, CRC(5c3eeb2b) SHA1(33ea8b3968b78806334b5a0aab3a2c24e45c604e) )
771	771	ROM_LOAD( "191a05", 0x100000, 0x100000, CRC(f2e3b58b) SHA1(0bbc2fe87a4fd00b5073a884bcfebcf9c2c402ad) )
772	772	ROM_LOAD( "191a06", 0x200000, 0x100000, CRC(ee11fc08) SHA1(ec6dd684e8261b181d65b8bf1b9e97da5c4468f7) )
r29404	r29405
777	777	ROM_REGION( 0x200000, "gfx4", ROMREGION_ERASE00 )
778	778	ROM_COPY("gfx2",0x200000,0, 0x200000)
779	779
780		ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
	780	ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
781	781	ROM_LOAD( "191a03", 0x000000, 0x200000, CRC(9b13fbe8) SHA1(19b02dbd9d6da54045b0ba4dfe7b282c72745c9c))
782	782
783	783	ROM_REGION16_BE( 0x80, "eeprom", 0 )
784	784	ROM_LOAD( "lethaleneae.nv", 0x0000, 0x0080, CRC(eb369a67) SHA1(6c67294669614e96de5efb38372dbed435ee04d3) )
785	785	ROM_END
786	786
787		ROM_START( lethalenj ) // Japan version JAD
788		ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
	787	ROM_START( lethalenj ) // Japan version JAD
	788	ROM_REGION( 0x40000, "maincpu", 0 ) /* main program */
789	789	ROM_LOAD( "191jad01.u4", 0x00000, 0x40000, CRC(160a25c0) SHA1(1d3ed5a158e461a73c079fe24a8e9d5e2a87e126) )
790	790
791		ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
	791	ROM_REGION( 0x10000, "soundcpu", 0 ) /* Z80 sound program */
792	792	ROM_LOAD( "191a02.f4", 0x00000, 0x10000, CRC(72b843cc) SHA1(b44b2f039358c26fa792d740639b66a5c8bf78e7) )
793	793
794		ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
	794	ROM_REGION( 0x400000, "gfx1", 0 ) /* tilemaps */
795	795	ROM_LOAD32_WORD( "191a08", 0x000002, 0x100000, CRC(555bd4db) SHA1(d2e55796b4ab2306ae549fa9e7288e41eaa8f3de) )
796	796	ROM_LOAD32_WORD( "191a10", 0x000000, 0x100000, CRC(2fa9bf51) SHA1(1e4ec56b41dfd8744347a7b5799e3ebce0939adc) )
797	797	ROM_LOAD32_WORD( "191a07", 0x200002, 0x100000, CRC(1dad184c) SHA1(b2c4a8e48084005056aef2c8eaccb3d2eca71b73) )
798	798	ROM_LOAD32_WORD( "191a09", 0x200000, 0x100000, CRC(e2028531) SHA1(63ccce7855d829763e9e248a6c3eb6ea89ab17ee) )
799	799
800		ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
	800	ROM_REGION( 0x400000, "gfx2", ROMREGION_ERASE00 ) /* sprites - fake 6bpp decode is done from here */
801	801	ROM_LOAD( "191a04", 0x000000, 0x100000, CRC(5c3eeb2b) SHA1(33ea8b3968b78806334b5a0aab3a2c24e45c604e) )
802	802	ROM_LOAD( "191a05", 0x100000, 0x100000, CRC(f2e3b58b) SHA1(0bbc2fe87a4fd00b5073a884bcfebcf9c2c402ad) )
803	803	ROM_LOAD( "191a06", 0x200000, 0x100000, CRC(ee11fc08) SHA1(ec6dd684e8261b181d65b8bf1b9e97da5c4468f7) )
r29404	r29405
808	808	ROM_REGION( 0x200000, "gfx4", ROMREGION_ERASE00 )
809	809	ROM_COPY("gfx2",0x200000,0, 0x200000)
810	810
811		ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
	811	ROM_REGION( 0x200000, "k054539", 0 ) /* K054539 samples */
812	812	ROM_LOAD( "191a03", 0x000000, 0x200000, CRC(9b13fbe8) SHA1(19b02dbd9d6da54045b0ba4dfe7b282c72745c9c))
813	813
814	814	ROM_REGION16_BE( 0x80, "eeprom", 0 )

trunk/src/mame/drivers/exprraid.c
r29404	r29405
509	509
510	510	/* video hardware */
511	511	MCFG_SCREEN_ADD("screen", RASTER)
512		// MCFG_SCREEN_REFRESH_RATE(60)
513		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
514		// MCFG_SCREEN_SIZE(328, 328)
515		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
	512	// MCFG_SCREEN_REFRESH_RATE(60)
	513	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
	514	// MCFG_SCREEN_SIZE(328, 328)
	515	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
516	516	MCFG_SCREEN_RAW_PARAMS(XTAL_12MHz/2, 384, 0, 256, 262, 8, 256-8) /* not accurate */
517	517	MCFG_SCREEN_UPDATE_DRIVER(exprraid_state, screen_update_exprraid)
518	518	MCFG_SCREEN_PALETTE("palette")

trunk/src/mame/drivers/tumbleb.c
r29404	r29405
2067	2067
2068	2068	MCFG_GFXDECODE_ADD("gfxdecode", "palette", tumbleb)
2069	2069	MCFG_PALETTE_ADD("palette", 1024)
2070		MCFG_PALETTE_FORMAT(xxxxBBBBGGGGRRRR)
	2070	MCFG_PALETTE_FORMAT(xxxxBBBBGGGGRRRR)
2071	2071
2072	2072	MCFG_VIDEO_START_OVERRIDE(tumbleb_state,tumblepb)
2073	2073

trunk/src/mame/drivers/bmcpokr.c
r29404	r29405
242	242	MCFG_SCREEN_SIZE(648, 328)
243	243	MCFG_SCREEN_VISIBLE_AREA(08, 648-1, 08, 328-1)
244	244	MCFG_SCREEN_PALETTE("palette")
245
	245
246	246	MCFG_PALETTE_ADD("palette", 256)
247	247	MCFG_GFXDECODE_ADD("gfxdecode", "palette", bmcpokr)
248	248

trunk/src/mame/drivers/dfruit.c
r29404	r29405
403	403
404	404	MCFG_GFXDECODE_ADD("gfxdecode", "palette", dfruit )
405	405	MCFG_PALETTE_ADD("palette", 0x100)
406
	406
407	407	MCFG_DEVICE_ADD("tc0091lvc", TC0091LVC, 0)
408	408	MCFG_TC0091LVC_GFXDECODE("gfxdecode")
409	409	MCFG_TC0091LVC_PALETTE("palette")
410
	410
411	411	MCFG_I8255A_ADD( "ppi8255_0", ppi8255_intf )
412	412
413	413	/* sound hardware */

trunk/src/mame/drivers/micro3d.c
r29404	r29405
328	328	MCFG_MC68681_B_TX_CALLBACK(WRITELINE(micro3d_state, duart_txb))
329	329	MCFG_MC68681_INPORT_CALLBACK(READ8(micro3d_state, duart_input_r))
330	330	MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(micro3d_state, duart_output_w))
331
	331
332	332	MCFG_DEVICE_ADD("mc68901", MC68901, 4000000)
333	333	MCFG_MC68901_TIMER_CLOCK(4000000)
334	334	MCFG_MC68901_RX_CLOCK(0)

trunk/src/mame/drivers/tugboat.c
r29404	r29405
49	49	required_device<gfxdecode_device> m_gfxdecode;
50	50	required_device<screen_device> m_screen;
51	51	required_device<palette_device> m_palette;
52
	52
53	53	UINT8 m_hd46505_0_reg[18];
54	54	UINT8 m_hd46505_1_reg[18];
55	55	int m_reg0;

trunk/src/mame/drivers/bailey.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	Bailey International discrete hardware games
4
	4
5	5	Fun Four (1976)
6
	6
7	7	***************************************************************************/
8	8
9	9
r29404	r29405
43	43	public:
44	44	bailey_state(const machine_config &mconfig, device_type type, const char *tag)
45	45	: driver_device(mconfig, type, tag),
46		m_maincpu(*this, "maincpu"),
47		m_video(*this, "fixfreq")
	46	m_maincpu(*this, "maincpu"),
	47	m_video(*this, "fixfreq")
48	48	{
49	49	}
50
	50
51	51	// devices
52	52	required_device<netlist_mame_device_t> m_maincpu;
53	53	required_device<fixedfreq_device> m_video;
54
	54
55	55	protected:
56
	56
57	57	// driver_device overrides
58	58	virtual void machine_start();
59	59	virtual void machine_reset();
60
	60
61	61	virtual void video_start();
62
	62
63	63	private:
64
	64
65	65	};
66	66
67	67
68	68	static NETLIST_START(bailey)
69	69	SOLVER(Solver, 48000)
70		// PARAM(Solver.FREQ, 48000)
	70	// PARAM(Solver.FREQ, 48000)
71	71	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
72	72
73	73	// schematics
74	74	//...
75	75
76		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
77		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	76	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	77	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
78	78	NETLIST_END()
79	79
80	80
r29404	r29405
104	104
105	105
106	106	/***************************************************************************
107
	107
108	108	Game driver(s)
109
	109
110	110	***************************************************************************/
111	111
112	112

trunk/src/mame/drivers/pzletime.c
r29404	r29405
342	342	MCFG_SCREEN_VISIBLE_AREA(08, 488-1, 08, 288-1)
343	343	MCFG_SCREEN_UPDATE_DRIVER(pzletime_state, screen_update_pzletime)
344	344	MCFG_SCREEN_PALETTE("palette")
345
	345
346	346	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pzletime)
347	347	MCFG_PALETTE_ADD("palette", 0x300 + 32768)
348	348	MCFG_PALETTE_FORMAT(xRRRRRGGGGGBBBBB)
349	349	MCFG_PALETTE_INIT_OWNER(pzletime_state, pzletime)
350
	350
351	351	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
352	352
353	353

trunk/src/mame/drivers/gei.c
r29404	r29405
1196	1196
1197	1197	MCFG_CPU_MODIFY("maincpu")
1198	1198	MCFG_CPU_PROGRAM_MAP(quizvid_map)
1199
	1199
1200	1200	MCFG_PALETTE_MODIFY("palette")
1201	1201	MCFG_PALETTE_INIT_OWNER(gei_state,quizvid)
1202	1202	MACHINE_CONFIG_END

trunk/src/mame/drivers/konendev.c
r29404	r29405
109	109	MCFG_CPU_PROGRAM_MAP(konendev_map)
110	110
111	111	/* video hardware */
112		MCFG_PALETTE_ADD_RRRRRGGGGGBBBBB("palette")
	112	MCFG_PALETTE_ADD_RRRRRGGGGGBBBBB("palette")
113	113
114	114	MCFG_SCREEN_ADD("screen", RASTER)
115	115	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mame/drivers/ecoinf2.c
r29404	r29405
21	21	public:
22	22	ecoinf2_state(const machine_config &mconfig, device_type type, const char *tag)
23	23	: driver_device(mconfig, type, tag),
24		m_maincpu(*this, "maincpu"),
	24	m_maincpu(*this, "maincpu"),
25	25	m_coins(*this, "COINS"),
26	26	m_key(*this, "PERKEY"),
27	27	m_panel(*this, "PANEL")
r29404	r29405
38	38	UINT16 m_lamps[16];
39	39	UINT16 m_leds[16];
40	40	//UINT16 m_chars[14];
41		// void update_display();
	41	// void update_display();
42	42	int m_optic_pattern;
43	43	int strobe_addr;
44	44	int strobe_amount;
r29404	r29405
89	89	}
90	90	DECLARE_WRITE8_MEMBER(ppi8255_ic10_write_c_strobe)
91	91	{
92		// if (data>=0xf0)
	92	// if (data>=0xf0)
93	93	{
94	94	strobe_addr = data & 0xf;
95	95
r29404	r29405
100	100	update_lamps();
101	101	update_leds();
102	102	}
103		// else logerror("%04x - ppi8255_ic10_(used)write_c %02x (UNUSUAL?)\n", m_maincpu->pcbase(), data);
	103	// else logerror("%04x - ppi8255_ic10_(used)write_c %02x (UNUSUAL?)\n", m_maincpu->pcbase(), data);
104	104	}
105	105
106	106
r29404	r29405
149	149	return 0x00;
150	150	}
151	151
152		// return m_misc->read();
	152	// return m_misc->read();
153	153	}
154	154
155	155
r29404	r29405
177	177	coin_lockout_w(machine(), 1, (data & 0x02) );
178	178	coin_lockout_w(machine(), 2, (data & 0x04) );
179	179	coin_lockout_w(machine(), 3, (data & 0x08) );
180		coin_lockout_w(machine(), 4, (data & 0x10) );
181
	180	coin_lockout_w(machine(), 4, (data & 0x10) );
	181
182	182	//int wdog = (data& 0x80);
183	183	}
184
185	184
186	185
187	186
	187
188	188	DECLARE_WRITE8_MEMBER(ppi8255_ic23_write_a_reel01)
189	189	{
190	190	stepper_update(0, data&0x0f);
r29404	r29405
254	254	DEVCB_DRIVER_MEMBER(ecoinf2_state,ppi8255_ic22_read_c_misc), /* Port C read (0x20 appears to be meter power)*/
255	255	DEVCB_NULL
256	256	};
257
	257
258	258	// IC24 is the workhorse of the Phoenix, it seems to handle meters, payslides, coin lamps, inhibits and the watchdog! */
259	259	static I8255_INTERFACE (ppi8255_ic24_intf)//coins and related
260	260	{
r29404	r29405
295	295	AM_RANGE(0x48, 0x4b) AM_DEVREADWRITE("ic22_inpt", i8255_device, read, write) //*
296	296	AM_RANGE(0x4c, 0x4f) AM_DEVREADWRITE("ic23_reel", i8255_device, read, write)
297	297	AM_RANGE(0x50, 0x53) AM_DEVREADWRITE("ic13_leds", i8255_device, read, write) //*
298		// AM_RANGE(0x54, 0x57) AM_DEVREADWRITE("ic25_dips", i8255_device, read, write) // is this an 8255, or a mirrored byte read?
	298	// AM_RANGE(0x54, 0x57) AM_DEVREADWRITE("ic25_dips", i8255_device, read, write) // is this an 8255, or a mirrored byte read?
299	299
300
301		// AM_RANGE(0x5c, 0x5c) AM_WRITE(ox_port5c_out_w)
	300
	301	// AM_RANGE(0x5c, 0x5c) AM_WRITE(ox_port5c_out_w)
302	302	ADDRESS_MAP_END
303	303
304	304
r29404	r29405
494	494	PORT_DIPNAME( 0x80, 0x80, "IN7:80" )
495	495	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
496	496	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
497
	497
498	498	PORT_START("PANEL")
499	499	PORT_DIPNAME( 0x01, 0x01, "IN8:01" )
500	500	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
r29404	r29405
561	561	MCFG_CPU_ADD("maincpu", Z180,4000000) // some of these hit invalid opcodes with a plain z80, some don't?
562	562	MCFG_CPU_PROGRAM_MAP(oxo_memmap)
563	563	MCFG_CPU_IO_MAP(oxo_portmap)
564
	564
565	565	MCFG_DEFAULT_LAYOUT(layout_ecoinf2)
566	566
567	567	MCFG_MACHINE_START_OVERRIDE(ecoinf2_state, ecoinf2 )
r29404	r29405
571	571	MCFG_I8255_ADD( "ic22_inpt", ppi8255_ic22_intf )
572	572	MCFG_I8255_ADD( "ic23_reel", ppi8255_ic23_intf )
573	573	MCFG_I8255_ADD( "ic13_leds", ppi8255_ic13_intf )
574		// MCFG_I8255_ADD( "ic25_dips", ppi8255_ic25_intf )
	574	// MCFG_I8255_ADD( "ic25_dips", ppi8255_ic25_intf )
575	575
576	576	MACHINE_CONFIG_END
577	577

trunk/src/mame/drivers/mystwarr.c
r29404	r29405
987	987	MCFG_QUANTUM_TIME(attotime::from_hz(1920))
988	988
989	989	MCFG_EEPROM_SERIAL_ER5911_8BIT_ADD("eeprom")
990
	990
991	991	MCFG_DEVICE_ADD("k053252", K053252, 6000000) // 6 MHz?
992	992	MCFG_K053252_OFFSETS(24, 16)
993
	993
994	994	MCFG_MACHINE_START_OVERRIDE(mystwarr_state,mystwarr)
995	995	MCFG_MACHINE_RESET_OVERRIDE(mystwarr_state,mystwarr)
996	996
r29404	r29405
1009	1009	MCFG_PALETTE_ENABLE_SHADOWS()
1010	1010	MCFG_PALETTE_ENABLE_HILIGHTS()
1011	1011
1012
	1012
1013	1013	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1014	1014	MCFG_K056832_ADD_NOINTF("k056832"/, mystwarr_k056832_intf/)
1015	1015	MCFG_K056832_GFXDECODE("gfxdecode")
r29404	r29405
1040	1040
1041	1041	MCFG_DEVICE_REPLACE("k053252", K053252, 16000000/2)
1042	1042	MCFG_K053252_OFFSETS(40, 16)
1043
	1043
1044	1044	/* basic machine hardware */
1045	1045	MCFG_CPU_MODIFY("maincpu")
1046	1046	MCFG_CPU_PROGRAM_MAP(viostorm_map)
r29404	r29405
1070	1070
1071	1071	MCFG_DEVICE_MODIFY("k053252")
1072	1072	MCFG_K053252_OFFSETS(24, 15)
1073
	1073
1074	1074	MCFG_K053250_ADD("k053250_1", "palette", "screen", -7, 0)
1075	1075
1076	1076	/* video hardware */
r29404	r29405
1122	1122
1123	1123	MCFG_DEVICE_MODIFY("k053252")
1124	1124	MCFG_K053252_OFFSETS(40, 16)
1125
	1125
1126	1126	MCFG_K054000_ADD("k054000")
1127	1127
1128	1128	MCFG_GFXDECODE_MODIFY("gfxdecode", gaiapols)

trunk/src/mame/drivers/halleys.c
r29404	r29405
247	247	offs_t m_collision_detection;
248	248	int m_latch_delay;
249	249	dynamic_array<UINT8> m_paletteram;
250
	250
251	251	DECLARE_WRITE8_MEMBER(bgtile_w);
252	252	DECLARE_READ8_MEMBER(blitter_status_r);
253	253	DECLARE_READ8_MEMBER(blitter_r);
r29404	r29405
1282	1282
1283	1283	m_alpha_table[(src<<8)+dst] = c \| BG_RGB;
1284	1284	}
1285
	1285
1286	1286	m_paletteram.resize(m_palette->entries());
1287	1287	m_palette->basemem().set(m_paletteram, ENDIANNESS_LITTLE, 1);
1288
	1288
1289	1289	m_bgcolor = m_palette->black_pen();
1290	1290	}
1291	1291

trunk/src/mame/drivers/peplus.c
r29404	r29405
204	204	m_maincpu(*this, "maincpu"),
205	205	m_i2cmem(*this, "i2cmem"),
206	206	m_gfxdecode(*this, "gfxdecode"),
207		m_palette(*this, "palette")
	207	m_palette(*this, "palette")
208	208	{
209	209	}
210	210
r29404	r29405
6846	6846
6847	6847	ROM_START( pexmp030 ) /* Superboard : 5-in-1 Wingboard (XMP00030) */
6848	6848	ROM_REGION( 0x10000, "maincpu", 0 )
6849		ROM_LOAD( "xmp00030.u67", 0x00000, 0x10000, CRC(da3fcb6f) SHA1(114e581e5ebb5c40c3f3da2784122d3281f269ee) ) /* 11/12/00 @ IGT L01-0197 */
	6849	ROM_LOAD( "xmp00030.u67", 0x00000, 0x10000, CRC(da3fcb6f) SHA1(114e581e5ebb5c40c3f3da2784122d3281f269ee) ) /* 11/12/00 @ IGT L01-0197 */
6850	6850
6851	6851	ROM_REGION( 0x10000, "user1", 0 )
6852	6852	ROM_LOAD( "x002066p.u66", 0x00000, 0x10000, CRC(01236011) SHA1(3edfee014705b3540386c5e42026ab93628b2597) ) /* Double Double Bonus Poker */

trunk/src/mame/drivers/triforce.c
r29404	r29405
194	194	DSW - 2-position DIP Switch, present only on Sega GDROM version PCB
195	195	PIC16C621 - DIP18 socket and 4MHz OSC on a 90-degrees-mounted small PCB for
196	196	Microchip PIC16C621A protection key chip
197
	197
198	198	ROM Board (attached to CN3 of Media Board, ONLY for use with Namco ROM cart version of the Media Board)
199	199	---------
200	200

trunk/src/mame/drivers/konamigx.c
r29404	r29405
1728	1728
1729	1729	MCFG_VIDEO_START_OVERRIDE(konamigx_state,konamigx_type3)
1730	1730
1731
	1731
1732	1732	MCFG_PALETTE_MODIFY("palette")
1733	1733	MCFG_PALETTE_ENTRIES(16384)
1734	1734	MCFG_PALETTE_ENABLE_SHADOWS()

trunk/src/mame/drivers/dorachan.c
r29404	r29405
38	38	virtual void machine_reset();
39	39	UINT32 screen_update_dorachan(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
40	40	required_device<cpu_device> m_maincpu;
41		required_device<screen_device> m_screen;
	41	required_device<screen_device> m_screen;
42	42	};
43	43
44	44

trunk/src/mame/drivers/carrera.c
r29404	r29405
352	352	MCFG_GFXDECODE_ADD("gfxdecode", "palette", carrera)
353	353	MCFG_PALETTE_ADD("palette", 32)
354	354	MCFG_PALETTE_INIT_OWNER(carrera_state, carrera)
355
	355
356	356	/* sound hardware */
357	357	MCFG_SPEAKER_STANDARD_MONO("mono")
358	358

trunk/src/mame/drivers/electra.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	Electra discrete hardware games
4
	4
5	5	Game Name
6	6	Avenger (1975) EG-1020
7	7	Eliminator IV (1976)
r29404	r29405
9	9	Pace Car Pro (1975) EG-1000
10	10	UFO Chase (1975) EG-1010
11	11	Wings (1976)
12
	12
13	13	***************************************************************************/
14	14
15	15
r29404	r29405
49	49	public:
50	50	electra_state(const machine_config &mconfig, device_type type, const char *tag)
51	51	: driver_device(mconfig, type, tag),
52		m_maincpu(*this, "maincpu"),
53		m_video(*this, "fixfreq")
	52	m_maincpu(*this, "maincpu"),
	53	m_video(*this, "fixfreq")
54	54	{
55	55	}
56
	56
57	57	// devices
58	58	required_device<netlist_mame_device_t> m_maincpu;
59	59	required_device<fixedfreq_device> m_video;
60
	60
61	61	protected:
62
	62
63	63	// driver_device overrides
64	64	virtual void machine_start();
65	65	virtual void machine_reset();
66
	66
67	67	virtual void video_start();
68
	68
69	69	private:
70
	70
71	71	};
72	72
73	73
74	74	static NETLIST_START(electra)
75	75	SOLVER(Solve, 48000)
76		// PARAM(Solver.FREQ, 48000)
	76	// PARAM(Solver.FREQ, 48000)
77	77	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
78	78
79	79	// schematics
80	80	//...
81	81
82		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
83		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	82	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	83	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
84	84	NETLIST_END()
85	85
86	86
r29404	r29405
110	110
111	111
112	112	/***************************************************************************
113
	113
114	114	Game driver(s)
115
	115
116	116	***************************************************************************/
117	117
118	118

trunk/src/mame/drivers/d9final.c
r29404	r29405
297	297	MCFG_SCREEN_REFRESH_RATE(60)
298	298	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
299	299	MCFG_SCREEN_SIZE(512, 256)
300		MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 16, 256-16-1)
	300	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 16, 256-16-1)
301	301	MCFG_SCREEN_UPDATE_DRIVER(d9final_state, screen_update_d9final)
302	302	MCFG_SCREEN_PALETTE("palette")
303	303

trunk/src/mame/drivers/rockrage.c
r29404	r29405
261	261	MCFG_K007342_GFXNUM(0)
262	262	MCFG_K007342_CALLBACK_OWNER(rockrage_state, rockrage_tile_callback)
263	263	MCFG_K007342_GFXDECODE("gfxdecode")
264
	264
265	265	MCFG_K007420_ADD("k007420")
266	266	MCFG_K007420_BANK_LIMIT(0x3ff)
267		MCFG_K007420_CALLBACK_OWNER(rockrage_state, rockrage_sprite_callback)
	267	MCFG_K007420_CALLBACK_OWNER(rockrage_state, rockrage_sprite_callback)
268	268	MCFG_K007420_PALETTE("palette")
269	269
270	270	MCFG_GFXDECODE_ADD("gfxdecode", "palette", rockrage)

trunk/src/mame/drivers/segac2.c
r29404	r29405
97	97	m_upd7759(*this, "upd"),
98	98	m_screen(*this, "screen"),
99	99	m_palette(*this, "palette") { }
100
	100
101	101	// for Print Club only
102	102	int m_cam_data;
103
	103
104	104	int m_segac2_enable_display;
105
	105
106	106	required_shared_ptr<UINT16> m_paletteram;
107
	107
108	108	/* internal states */
109	109	UINT8 m_misc_io_data[0x10]; /* holds values written to the I/O chip */
110
	110
111	111	/* protection-related tracking */
112	112	int (m_prot_func)(int in); / emulation of protection chip */
113	113	UINT8 m_prot_write_buf; /* remembers what was written */
114	114	UINT8 m_prot_read_buf; /* remembers what was returned */
115
	115
116	116	/* palette-related variables */
117	117	UINT8 m_segac2_alt_palette_mode;
118	118	UINT8 m_palbank;
119	119	UINT8 m_bg_palbase;
120	120	UINT8 m_sp_palbase;
121
	121
122	122	/* sound-related variables */
123	123	UINT8 m_sound_banks; /* number of sound banks */
124
	124
125	125	DECLARE_DRIVER_INIT(c2boot);
126	126	DECLARE_DRIVER_INIT(bloxeedc);
127	127	DECLARE_DRIVER_INIT(columns);
r29404	r29405
151	151	DECLARE_VIDEO_START(segac2_new);
152	152	DECLARE_MACHINE_START(segac2);
153	153	DECLARE_MACHINE_RESET(segac2);
154
	154
155	155	UINT32 screen_update_segac2_new(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
156	156	int m_segac2_bg_pal_lookup[4];
157	157	int m_segac2_sp_pal_lookup[4];
158	158	void recompute_palette_tables();
159
	159
160	160	DECLARE_WRITE_LINE_MEMBER(vdp_sndirqline_callback_c2);
161	161	DECLARE_WRITE_LINE_MEMBER(vdp_lv6irqline_callback_c2);
162	162	DECLARE_WRITE_LINE_MEMBER(vdp_lv4irqline_callback_c2);
163
	163
164	164	DECLARE_WRITE16_MEMBER( segac2_upd7759_w );
165	165	DECLARE_READ16_MEMBER( palette_r );
166	166	DECLARE_WRITE16_MEMBER( palette_w );
r29404	r29405
177	177	optional_device<upd7759_device> m_upd7759;
178	178	optional_device<screen_device> m_screen;
179	179	required_device<palette_device> m_palette;
180
	180
181	181	};
182	182
183	183
r29404	r29405
195	195	save_item(NAME(m_misc_io_data));
196	196	save_item(NAME(m_prot_write_buf));
197	197	save_item(NAME(m_prot_read_buf));
198
	198
199	199	m_vdp->stop_timers();
200	200	}
201	201

trunk/src/mame/drivers/mugsmash.c
r29404	r29405
408	408	MCFG_SCREEN_VISIBLE_AREA(08, 408-1, 18, 318-1)
409	409	MCFG_SCREEN_UPDATE_DRIVER(mugsmash_state, screen_update_mugsmash)
410	410	MCFG_SCREEN_PALETTE("palette")
411
	411
412	412	MCFG_GFXDECODE_ADD("gfxdecode", "palette", mugsmash)
413	413
414	414	MCFG_PALETTE_ADD("palette", 0x300)

trunk/src/mame/drivers/gladiatr.c
r29404	r29405
711	711	MCFG_TAITO8741_MODES(TAITO8741_MASTER,TAITO8741_SLAVE,TAITO8741_PORT,TAITO8741_PORT)
712	712	MCFG_TAITO8741_CONNECT(1,0,0,0)
713	713	MCFG_TAITO8741_PORT_HANDLERS(READ8(gladiatr_state,gladiator_dsw1_r),READ8(gladiatr_state,gladiator_dsw2_r),READ8(gladiatr_state,gladiator_button3_r),READ8(gladiatr_state,gladiator_controls_r))
714
	714
715	715	/* video hardware */
716	716	MCFG_SCREEN_ADD("screen", RASTER)
717	717	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mame/drivers/puckpkmn.c
r29404	r29405
221	221	AM_RANGE(0x700022, 0x700023) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
222	222	AM_RANGE(0xa04000, 0xa04003) AM_READWRITE8(megadriv_68k_YM2612_read, megadriv_68k_YM2612_write, 0xffff)
223	223	AM_RANGE(0xc00000, 0xc0001f) AM_DEVREADWRITE("gen_vdp", sega315_5313_device, vdp_r, vdp_w)
224
	224
225	225	AM_RANGE(0xe00000, 0xe0ffff) AM_RAM AM_MIRROR(0x1f0000)
226	226
227	227	/* Unknown reads/writes: */
r29404	r29405
453	453	ROM_END
454	454
455	455
456		ROM_START( puckpkmnb )
	456	ROM_START( puckpkmnb )
457	457	ROM_REGION( 0x400000, "maincpu", 0 )
458	458	ROM_LOAD16_BYTE( "200061.u5", 0x000000, 0x080000, CRC(502a5093) SHA1(6dc1c79d52ebb653cb2e4388f74fd975ec323566) )
459	459	ROM_LOAD16_BYTE( "200060.u4", 0x000001, 0x080000, CRC(5f160c18) SHA1(5a5ce1b9a81afe836e435e9d6f16cf57b63cbd31) )

trunk/src/mame/drivers/seabattl.c
r29404	r29405
99	99	UINT8 m_collision;
100	100	required_device<gfxdecode_device> m_gfxdecode;
101	101	required_device<screen_device> m_screen;
102		required_device<palette_device> m_palette;
	102	required_device<palette_device> m_palette;
103	103	};
104	104
105	105

trunk/src/mame/drivers/vendetta.c
r29404	r29405
443	443
444	444	m_paletteram.resize(0x1000);
445	445	m_palette->basemem().set(m_paletteram, ENDIANNESS_BIG, 2);
446
	446
447	447	save_item(NAME(m_paletteram));
448	448	save_item(NAME(m_irq_enabled));
449	449	save_item(NAME(m_sprite_colorbase));

trunk/src/mame/drivers/pktgaldx.c
r29404	r29405
394	394
395	395	MCFG_PALETTE_ADD("palette", 4096)
396	396	MCFG_PALETTE_FORMAT(XBGR)
397
	397
398	398	MCFG_GFXDECODE_ADD("gfxdecode", "palette", bootleg)
399	399
400	400	/* sound hardware */

trunk/src/mame/drivers/atarigx2.c
r29404	r29405
168	168	in those regions precludes applying the same kind of analysis.
169	169
170	170	int parameters3[16][2] = {
171		{0x003a, 0x0032},
172		{0x0076, 0x0064},
173		{0x00ee, 0x00c8},
174		{0x01dc, 0x0190},
175		{0x01b0, 0x012A},
176		{0x0168, 0x005C},
177		{0x00d8, 0x00b8},
178		{0x01b0, 0x0172},
179		{0x016a, 0x00ee},
180		{0x00de, 0x01de},
181		{0x01be, 0x01b6},
182		{0x0174, 0x0164},
183		{0x00e2, 0x00c0},
184		{0x01c6, 0x0180},
185		{0x0186, 0x010a},
186		{0x0104, 0x001c}
	171	{0x003a, 0x0032},
	172	{0x0076, 0x0064},
	173	{0x00ee, 0x00c8},
	174	{0x01dc, 0x0190},
	175	{0x01b0, 0x012A},
	176	{0x0168, 0x005C},
	177	{0x00d8, 0x00b8},
	178	{0x01b0, 0x0172},
	179	{0x016a, 0x00ee},
	180	{0x00de, 0x01de},
	181	{0x01be, 0x01b6},
	182	{0x0174, 0x0164},
	183	{0x00e2, 0x00c0},
	184	{0x01c6, 0x0180},
	185	{0x0186, 0x010a},
	186	{0x0104, 0x001c}
187	187	};
188	188
189	189	// every output bit is a linear function on the input bits except by
190	190	// a quadratic term always involving bit #0 of the input
191	191	UINT32 ftest4(UINT32 num)
192	192	{
193		UINT32 accum = 0;
194
195		for (int i=0; i<16; ++i)
196		{
197		int b1 = weight(num&parameters3[i][0])&1; // <- linear function (parameters3[i][0] acts as a mask determining which bits are added)
198		int b2 = weight(num&parameters3[i][1])&1; // <- idem
199		b2 &= BIT(num, 0); // quadratic term
200		int b3 = b1 ^ b2;
201
202		accum ^= (b3 << i);
203		}
204
205		return accum;
	193	UINT32 accum = 0;
	194
	195	for (int i=0; i<16; ++i)
	196	{
	197	int b1 = weight(num&parameters3[i][0])&1; // <- linear function (parameters3[i][0] acts as a mask determining which bits are added)
	198	int b2 = weight(num&parameters3[i][1])&1; // <- idem
	199	b2 &= BIT(num, 0); // quadratic term
	200	int b3 = b1 ^ b2;
	201
	202	accum ^= (b3 << i);
	203	}
	204
	205	return accum;
206	206	}
207	207
208	208	*********************/

trunk/src/mame/drivers/nwk-tr.c
r29404	r29405
775	775	MCFG_PALETTE_ADD("palette", 65536)
776	776
777	777	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
778
	778
779	779	MCFG_K001604_ADD("k001604", racingj_k001604_intf)
780	780	MCFG_K001604_GFXDECODE("gfxdecode")
781	781	MCFG_K001604_PALETTE("palette")

trunk/src/mame/drivers/pkscram.c
r29404	r29405
52	52	DECLARE_WRITE_LINE_MEMBER(irqhandler);
53	53	required_device<cpu_device> m_maincpu;
54	54	required_device<gfxdecode_device> m_gfxdecode;
55		required_device<screen_device> m_screen;
	55	required_device<screen_device> m_screen;
56	56	};
57	57
58	58

trunk/src/mame/drivers/taotaido.c
r29404	r29405
356	356	MCFG_VSYSTEM_SPR_SET_GFXREGION(0)
357	357	MCFG_VSYSTEM_SPR_GFXDECODE("gfxdecode")
358	358	MCFG_VSYSTEM_SPR_PALETTE("palette")
359
	359
360	360	/* sound hardware */
361	361	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
362	362

trunk/src/mame/drivers/ninjaw.c
r29404	r29405
854	854	MCFG_TC0110PCR_PALETTE("palette2")
855	855	MCFG_TC0110PCR_ADD("tc0110pcr_3")
856	856	MCFG_TC0110PCR_PALETTE("palette3")
857
	857
858	858	/* sound hardware */
859	859	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
860	860

trunk/src/mame/drivers/pacman.c
r29404	r29405
4246	4246	ROM_LOAD( "5f", 0x1000, 0x1000, CRC(615af909) SHA1(fd6a1dde780b39aea76bf1c4befa5882573c2ef4) ) // 6.5f
4247	4247
4248	4248	ROM_REGION( 0x0120, "proms", 0 )
4249		ROM_LOAD( "mb7051.7f", 0x0000, 0x0020, CRC(ff344446) SHA1(45eb37533da8912645a089b014f3b3384702114a) )
	4249	ROM_LOAD( "mb7051.7f", 0x0000, 0x0020, CRC(ff344446) SHA1(45eb37533da8912645a089b014f3b3384702114a) )
4250	4250	ROM_LOAD( "82s126.4a", 0x0020, 0x0100, CRC(3eb3a8e4) SHA1(19097b5f60d1030f8b82d9f1d3a241f93e5c75d6) ) // m82s129n.4a
4251	4251
4252	4252	ROM_REGION( 0x0200, "namco", 0 ) /* sound PROMs */
r29404	r29405
4629	4629	ROM_LOAD( "cr4.5j", 0x1800, 0x0800, CRC(d35d1caf) SHA1(65dd7861e05651485626465dc97215fed58db551) )
4630	4630
4631	4631	// the set with the above 'crushbl3' program roms and these gfx roms just seems to be a bad dump (some bad maze tiles?)
4632		// ROM_REGION( 0x2000, "gfx1", 0 )
4633		// ROM_LOAD( "cr1.bin", 0x0000, 0x0800, CRC(cc31c649) SHA1(a0640d2abc21872b0e680e8e31e3bcb7e7a07953) )
4634		// ROM_LOAD( "cr3.bin", 0x0800, 0x0800, CRC(14c121d8) SHA1(05f900a2e2a67401ab357340c1fb36153f365f1b) )
4635		// ROM_LOAD( "cr2.bin", 0x1000, 0x0800, CRC(882dc667) SHA1(5ea01d9c692b3061a0e39e2227fbc6af4baaab11) ) /* copyright sign was removed */
4636		// ROM_LOAD( "cr4.bin", 0x1800, 0x0800, CRC(0d3877c4) SHA1(0a6f4098181480aa85225324129e37bba375252d) )
	4632	// ROM_REGION( 0x2000, "gfx1", 0 )
	4633	// ROM_LOAD( "cr1.bin", 0x0000, 0x0800, CRC(cc31c649) SHA1(a0640d2abc21872b0e680e8e31e3bcb7e7a07953) )
	4634	// ROM_LOAD( "cr3.bin", 0x0800, 0x0800, CRC(14c121d8) SHA1(05f900a2e2a67401ab357340c1fb36153f365f1b) )
	4635	// ROM_LOAD( "cr2.bin", 0x1000, 0x0800, CRC(882dc667) SHA1(5ea01d9c692b3061a0e39e2227fbc6af4baaab11) ) /* copyright sign was removed */
	4636	// ROM_LOAD( "cr4.bin", 0x1800, 0x0800, CRC(0d3877c4) SHA1(0a6f4098181480aa85225324129e37bba375252d) )
4637	4637
4638	4638	ROM_REGION( 0x0120, "proms", 0 )
4639	4639	ROM_LOAD( "74s288.8a", 0x0000, 0x0020, CRC(ff344446) SHA1(45eb37533da8912645a089b014f3b3384702114a) )

trunk/src/mame/drivers/chqflag.c
r29404	r29405
300	300
301	301	m_paletteram.resize(m_palette->entries() * 2);
302	302	m_palette->basemem().set(m_paletteram, ENDIANNESS_BIG, 2);
303
	303
304	304	save_item(NAME(m_paletteram));
305	305	save_item(NAME(m_k051316_readroms));
306	306	save_item(NAME(m_last_vreg));

trunk/src/mame/drivers/sf.c
r29404	r29405
835	835	MCFG_SCREEN_PALETTE("palette")
836	836
837	837	MCFG_GFXDECODE_ADD("gfxdecode", "palette", sf)
838
	838
839	839	MCFG_PALETTE_ADD("palette", 1024)
840	840	MCFG_PALETTE_FORMAT(xxxxRRRRGGGGBBBB)
841	841

trunk/src/mame/drivers/dooyong.c
r29404	r29405
1661	1661	ROM_LOAD( "ftiger_2.4h", 0x08000, 0x08000, CRC(ca9d6713) SHA1(645cccc06c7f6744b25e7917f414956856419b8a) )
1662	1662	ROM_CONTINUE( 0x00000, 0x8000 )
1663	1663
1664		ROM_REGION( 0x80000, "gfx2", 0 ) /* sprites */
	1664	ROM_REGION( 0x80000, "gfx2", 0 ) /* sprites */
1665	1665	ROM_LOAD16_BYTE( "ftiger_16.4h", 0x00000, 0x20000, CRC(8a158b95) SHA1(ed09d9c40b76a27e06601381e463a00b16555f1e) )
1666	1666	ROM_LOAD16_BYTE( "ftiger_15.2h", 0x00001, 0x20000, CRC(399f6043) SHA1(ea0debd6d0f8c61f0078809c2828734fc15e891d) )
1667	1667	ROM_LOAD16_BYTE( "ftiger_14.4k", 0x40000, 0x20000, CRC(df66b6f3) SHA1(3a29ae69a09306c5a2a2786acbf227832b408152) )

trunk/src/mame/drivers/rcorsair.c
r29404	r29405
139	139	MCFG_SCREEN_ADD("screen", RASTER)
140	140	MCFG_SCREEN_REFRESH_RATE(60)
141	141	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
142		MCFG_SCREEN_UPDATE_DRIVER(rcorsair_state, screen_update)
	142	MCFG_SCREEN_UPDATE_DRIVER(rcorsair_state, screen_update)
143	143	MCFG_SCREEN_SIZE(256, 256)
144	144	MCFG_SCREEN_VISIBLE_AREA(0, 256-1, 0, 256-1)
145	145	MCFG_SCREEN_PALETTE("palette")

trunk/src/mame/drivers/s7.c
r29404	r29405
442	442	MCFG_SPEAKER_STANDARD_MONO("speech")
443	443	MCFG_SOUND_ADD("hc55516", HC55516, 0)
444	444	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speech", 0.50)
445
	445
446	446	MCFG_DEVICE_ADD("pias", PIA6821, 0)
447	447	MCFG_PIA_READPB_HANDLER(READ8(s7_state, dac_r))
448	448	MCFG_PIA_WRITEPA_HANDLER(WRITE8(s7_state, dac_w))

trunk/src/mame/drivers/cubeqst.c
r29404	r29405
44	44	required_device<cquestrot_cpu_device> m_rotatecpu;
45	45	required_device<cquestlin_cpu_device> m_linecpu;
46	46	required_device<cquestsnd_cpu_device> m_soundcpu;
47		required_device<screen_device> m_screen;
	47	required_device<screen_device> m_screen;
48	48	rgb_t *m_colormap;
49	49	DECLARE_WRITE16_MEMBER(palette_w);
50	50	DECLARE_READ16_MEMBER(line_r);

trunk/src/mame/drivers/wolfpack.c
r29404	r29405
313	313	MCFG_SCREEN_UPDATE_DRIVER(wolfpack_state, screen_update_wolfpack)
314	314	MCFG_SCREEN_VBLANK_DRIVER(wolfpack_state, screen_eof_wolfpack)
315	315	MCFG_SCREEN_PALETTE("palette")
316
	316
317	317	MCFG_GFXDECODE_ADD("gfxdecode", "palette", wolfpack)
318	318	MCFG_PALETTE_ADD("palette", 12)
319	319	MCFG_PALETTE_INDIRECT_ENTRIES(8)

trunk/src/mame/drivers/exerion.c
r29404	r29405
400	400	MCFG_SCREEN_RAW_PARAMS(EXERION_PIXEL_CLOCK, EXERION_HTOTAL, EXERION_HBEND, EXERION_HBSTART, EXERION_VTOTAL, EXERION_VBEND, EXERION_VBSTART)
401	401	MCFG_SCREEN_UPDATE_DRIVER(exerion_state, screen_update_exerion)
402	402	MCFG_SCREEN_PALETTE("palette")
403
	403
404	404	MCFG_GFXDECODE_ADD("gfxdecode", "palette", exerion)
405	405	MCFG_PALETTE_ADD("palette", 256*3)
406	406	MCFG_PALETTE_INDIRECT_ENTRIES(32)

trunk/src/mame/drivers/segas18.c
r29404	r29405
145	145	m_vdp->set_vdp_pal(FALSE);
146	146	m_vdp->set_framerate(60);
147	147	m_vdp->set_total_scanlines(262);
148		m_vdp->stop_timers(); // 315-5124 timers
	148	m_vdp->stop_timers(); // 315-5124 timers
149	149
150	150	// save state
151	151	save_item(NAME(m_mcu_data));

trunk/src/mame/drivers/subs.c
r29404	r29405
187	187
188	188	MCFG_PALETTE_ADD("palette", 4)
189	189	MCFG_PALETTE_INIT_OWNER(subs_state, subs)
190
	190
191	191	MCFG_DEFAULT_LAYOUT(layout_dualhsxs)
192	192
193	193	MCFG_SCREEN_ADD("lscreen", RASTER)

trunk/src/mame/drivers/cobra.c
r29404	r29405
624	624	required_device<ata_interface_device> m_ata;
625	625	required_device<screen_device> m_screen;
626	626	required_device<palette_device> m_palette;
627
	627
628	628	DECLARE_READ64_MEMBER(main_comram_r);
629	629	DECLARE_WRITE64_MEMBER(main_comram_w);
630	630	DECLARE_READ64_MEMBER(main_fifo_r);

trunk/src/mame/drivers/nycaptor.c
r29404	r29405
922	922	// pin 1 SOLO 8' not mapped
923	923	// pin 2 SOLO 16' not mapped
924	924	// pin 22 Noise Output not mapped
925
	925
926	926	MCFG_DAC_ADD("dac")
927	927	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
928	928	MACHINE_CONFIG_END
r29404	r29405
981	981	// pin 1 SOLO 8' not mapped
982	982	// pin 2 SOLO 16' not mapped
983	983	// pin 22 Noise Output not mapped
984
	984
985	985	MCFG_DAC_ADD("dac")
986	986	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
987	987	MACHINE_CONFIG_END

trunk/src/mame/drivers/mitchell.c
r29404	r29405
1092	1092	MCFG_SCREEN_PALETTE("palette")
1093	1093
1094	1094	MCFG_GFXDECODE_ADD("gfxdecode", "palette", mgakuen)
1095
	1095
1096	1096	MCFG_PALETTE_ADD("palette", 1024) /* less colors than the others */
1097	1097	MCFG_PALETTE_FORMAT(xxxxRRRRGGGGBBBB)
1098	1098

trunk/src/mame/drivers/crystal.c
r29404	r29405
1076	1076	{
1077	1077	// patches based on analysis of PIC dump
1078	1078	UINT16 Rom = (UINT16) memregion("user1")->base();
1079		/*
1080		PIC Protection data:
1081		- RAM ADDR - --PATCH--
1082		62 0f 02 02 fc 90 01 90
1083		68 6a 02 02 04 90 01 90
1084		2c cf 03 02 e9 df c2 c3
1085		00 e0 03 02 01 90 00 92
	1079	/*
	1080	PIC Protection data:
	1081	- RAM ADDR - --PATCH--
	1082	62 0f 02 02 fc 90 01 90
	1083	68 6a 02 02 04 90 01 90
	1084	2c cf 03 02 e9 df c2 c3
	1085	00 e0 03 02 01 90 00 92
1086	1086	*/
1087	1087
1088		Rom[WORD_XOR_LE(0x12d7a/2)]=0x90FC; //PUSH R7-R6-R5-R4-R3-R2
1089		Rom[WORD_XOR_LE(0x12d7c/2)]=0x9001; //PUSH R0
	1088	Rom[WORD_XOR_LE(0x12d7a/2)]=0x90FC; //PUSH R7-R6-R5-R4-R3-R2
	1089	Rom[WORD_XOR_LE(0x12d7c/2)]=0x9001; //PUSH R0
1090	1090
1091		Rom[WORD_XOR_LE(0x18880/2)]=0x9004; //PUSH R2
1092		Rom[WORD_XOR_LE(0x18882/2)]=0x9001; //PUSH R0
	1091	Rom[WORD_XOR_LE(0x18880/2)]=0x9004; //PUSH R2
	1092	Rom[WORD_XOR_LE(0x18882/2)]=0x9001; //PUSH R0
1093	1093
1094		Rom[WORD_XOR_LE(0x2fe18/2)]=0x9001; //PUSH R0
1095		Rom[WORD_XOR_LE(0x2fe1a/2)]=0x9200; //PUSH SR
	1094	Rom[WORD_XOR_LE(0x2fe18/2)]=0x9001; //PUSH R0
	1095	Rom[WORD_XOR_LE(0x2fe1a/2)]=0x9200; //PUSH SR
1096	1096
1097		Rom[WORD_XOR_LE(0x2ED44/2)]=0xDFE9; //CALL 0x3cf00
1098		Rom[WORD_XOR_LE(0x2ED46/2)]=0xC3C2; //MOV %SR0,%DR1
	1097	Rom[WORD_XOR_LE(0x2ED44/2)]=0xDFE9; //CALL 0x3cf00
	1098	Rom[WORD_XOR_LE(0x2ED46/2)]=0xC3C2; //MOV %SR0,%DR1
1099	1099
1100	1100	}
1101	1101
r29404	r29405
1105	1105	UINT16 Rom = (UINT16) memregion("user1")->base();
1106	1106
1107	1107	/*
1108		PIC Protection data:
1109		- RAM ADDR - --PATCH--
1110		0a 83 01 02 1c 90 01 90
1111		50 85 01 02 7c 90 01 90
1112		4c 99 05 02 04 90 01 90
1113		3a c1 01 02 1c 90 01 90
	1108	PIC Protection data:
	1109	- RAM ADDR - --PATCH--
	1110	0a 83 01 02 1c 90 01 90
	1111	50 85 01 02 7c 90 01 90
	1112	4c 99 05 02 04 90 01 90
	1113	3a c1 01 02 1c 90 01 90
1114	1114	*/
1115	1115
1116		Rom[WORD_XOR_LE(0x9c9e/2)]=0x901C; //PUSH R4-R3-R2
1117		Rom[WORD_XOR_LE(0x9ca0/2)]=0x9001; //PUSH R0
	1116	Rom[WORD_XOR_LE(0x9c9e/2)]=0x901C; //PUSH R4-R3-R2
	1117	Rom[WORD_XOR_LE(0x9ca0/2)]=0x9001; //PUSH R0
1118	1118
1119		Rom[WORD_XOR_LE(0x9EE4/2)]=0x907C; //PUSH R6-R5-R4-R3-R2
1120		Rom[WORD_XOR_LE(0x9EE6/2)]=0x9001; //PUSH R0
	1119	Rom[WORD_XOR_LE(0x9EE4/2)]=0x907C; //PUSH R6-R5-R4-R3-R2
	1120	Rom[WORD_XOR_LE(0x9EE6/2)]=0x9001; //PUSH R0
1121	1121
1122		Rom[WORD_XOR_LE(0x4B2E0/2)]=0x9004; //PUSH R2
1123		Rom[WORD_XOR_LE(0x4B2E2/2)]=0x9001; //PUSH R0
	1122	Rom[WORD_XOR_LE(0x4B2E0/2)]=0x9004; //PUSH R2
	1123	Rom[WORD_XOR_LE(0x4B2E2/2)]=0x9001; //PUSH R0
1124	1124
1125		Rom[WORD_XOR_LE(0xDACE/2)]=0x901c; //PUSH R4-R3-R2
1126		Rom[WORD_XOR_LE(0xDAD0/2)]=0x9001; //PUSH R0
	1125	Rom[WORD_XOR_LE(0xDACE/2)]=0x901c; //PUSH R4-R3-R2
	1126	Rom[WORD_XOR_LE(0xDAD0/2)]=0x9001; //PUSH R0
1127	1127	}
1128	1128
1129	1129	DRIVER_INIT_MEMBER(crystal_state, donghaer)
1130	1130	{
1131	1131	UINT16 Rom = (UINT16)memregion("user1")->base();
1132	1132
1133		Rom[WORD_XOR_LE(0x037A2 / 2)] = 0x9004; // PUSH %R2
1134		Rom[WORD_XOR_LE(0x037A4 / 2)] = 0x8202; // LD (%SP,0x8),%R2
	1133	Rom[WORD_XOR_LE(0x037A2 / 2)] = 0x9004; // PUSH %R2
	1134	Rom[WORD_XOR_LE(0x037A4 / 2)] = 0x8202; // LD (%SP,0x8),%R2
1135	1135
1136		Rom[WORD_XOR_LE(0x03834 / 2)] = 0x9001; // PUSH %R0
1137		Rom[WORD_XOR_LE(0x03836 / 2)] = 0x9200; // PUSH %SR
	1136	Rom[WORD_XOR_LE(0x03834 / 2)] = 0x9001; // PUSH %R0
	1137	Rom[WORD_XOR_LE(0x03836 / 2)] = 0x9200; // PUSH %SR
1138	1138
1139		Rom[WORD_XOR_LE(0x0AC9E / 2)] = 0x9004; // PUSH %R2
1140		Rom[WORD_XOR_LE(0x0ACA0 / 2)] = 0x4081; // LERI 0x81
	1139	Rom[WORD_XOR_LE(0x0AC9E / 2)] = 0x9004; // PUSH %R2
	1140	Rom[WORD_XOR_LE(0x0ACA0 / 2)] = 0x4081; // LERI 0x81
1141	1141
1142		Rom[WORD_XOR_LE(0x19C70 / 2)] = 0x900C; // PUSH %R2-%R3
1143		Rom[WORD_XOR_LE(0x19C72 / 2)] = 0x9001; // PUSH %R0
	1142	Rom[WORD_XOR_LE(0x19C70 / 2)] = 0x900C; // PUSH %R2-%R3
	1143	Rom[WORD_XOR_LE(0x19C72 / 2)] = 0x9001; // PUSH %R0
1144	1144	}
1145	1145
1146	1146

trunk/src/mame/drivers/meadwttl.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	Meadows Discrete Game List
4
	4
5	5	Bombs Away (1976)
6	6	Ckidzo (1976)
7	7	Cobra Gunship (1976)
8	8	Drop Zone 4 (1975)
9	9	Flim Flam (1974)
10	10	4 in 1 Meadows (197?)
11
	11
12	12	***************************************************************************/
13	13
14	14
r29404	r29405
48	48	public:
49	49	meadwttl_state(const machine_config &mconfig, device_type type, const char *tag)
50	50	: driver_device(mconfig, type, tag),
51		m_maincpu(*this, "maincpu"),
52		m_video(*this, "fixfreq")
	51	m_maincpu(*this, "maincpu"),
	52	m_video(*this, "fixfreq")
53	53	{
54	54	}
55
	55
56	56	// devices
57	57	required_device<netlist_mame_device_t> m_maincpu;
58	58	required_device<fixedfreq_device> m_video;
59
	59
60	60	protected:
61
	61
62	62	// driver_device overrides
63	63	virtual void machine_start();
64	64	virtual void machine_reset();
65
	65
66	66	virtual void video_start();
67
	67
68	68	private:
69
	69
70	70	};
71	71
72	72
73	73	static NETLIST_START(meadows)
74	74	SOLVER(Solver, 48000)
75		// PARAM(Solver.FREQ, 48000)
	75	// PARAM(Solver.FREQ, 48000)
76	76	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
77	77
78	78	// schematics
79	79	//...
80	80
81		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
82		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	81	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	82	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
83	83	NETLIST_END()
84	84
85	85
r29404	r29405
109	109
110	110
111	111	/***************************************************************************
112
	112
113	113	Game driver(s)
114
	114
115	115	***************************************************************************/
116	116
117	117

trunk/src/mame/drivers/ramtek.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	Ramtek Discrete Games List
4
	4
5	5	Game Name DATA Board #
6	6	--------------------------------------------
7	7	(Deluxe) Baseball (1974) YES
r29404	r29405
14	14	Trivia (1976) YES
15	15	Volly/Volley (1973) YES
16	16	Wipe Out (1974) YES
17
	17
18	18	***************************************************************************/
19	19
20	20
r29404	r29405
54	54	public:
55	55	ramtek_state(const machine_config &mconfig, device_type type, const char *tag)
56	56	: driver_device(mconfig, type, tag),
57		m_maincpu(*this, "maincpu"),
58		m_video(*this, "fixfreq")
	57	m_maincpu(*this, "maincpu"),
	58	m_video(*this, "fixfreq")
59	59	{
60	60	}
61
	61
62	62	// devices
63	63	required_device<netlist_mame_device_t> m_maincpu;
64	64	required_device<fixedfreq_device> m_video;
65
	65
66	66	protected:
67
	67
68	68	// driver_device overrides
69	69	virtual void machine_start();
70	70	virtual void machine_reset();
71
	71
72	72	virtual void video_start();
73
	73
74	74	private:
75
	75
76	76	};
77	77
78	78
79	79	static NETLIST_START(ramtek)
80	80	SOLVER(Solver, 48000)
81		// PARAM(Solver.FREQ, 48000)
	81	// PARAM(Solver.FREQ, 48000)
82	82	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
83	83
84	84	// schematics
85	85	//...
86	86
87		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
88		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	87	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	88	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
89	89	NETLIST_END()
90	90
91	91
r29404	r29405
115	115
116	116
117	117	/***************************************************************************
118
	118
119	119	Game driver(s)
120
	120
121	121	***************************************************************************/
122	122
123	123
r29404	r29405
138	138	ROM_END
139	139
140	140
141		// The board number for Clean Sweep is 501082, and the letter to the right would be the revision letter (A, B, C, D).
142		// Ramtek had revisions A, B, C, D, noted with a sticker that shows the letter for each specific revision.
	141	// The board number for Clean Sweep is 501082, and the letter to the right would be the revision letter (A, B, C, D).
	142	// Ramtek had revisions A, B, C, D, noted with a sticker that shows the letter for each specific revision.
143	143	// Revisions A,B,C have been dumped and rom content is the same (only diff is the location of some chips on the rev B pcb)
144	144	ROM_START( cleanswp )
145	145	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
146	146
147	147	ROM_REGION( 0x0020, "roms", ROMREGION_ERASE00 )
148		ROM_LOAD( "501075.c6", 0x0000, 0x0020, CRC(be02b5f5) SHA1(f1c616a73c6c2915ea3d0252543b0806704ab2e9) ) // shape of paddle
149		ROM_LOAD( "501076.d7", 0x0000, 0x0020, CRC(be40b153) SHA1(07fb64ea8caee601e3e3bd6c69beea619dd0489d) ) // ball control memory
150		ROM_LOAD( "501074.k3", 0x0000, 0x0020, CRC(515a34ba) SHA1(471ca9d99851591ff11a87d18b88871edd7fd268) ) // number character generation
	148	ROM_LOAD( "501075.c6", 0x0000, 0x0020, CRC(be02b5f5) SHA1(f1c616a73c6c2915ea3d0252543b0806704ab2e9) ) // shape of paddle
	149	ROM_LOAD( "501076.d7", 0x0000, 0x0020, CRC(be40b153) SHA1(07fb64ea8caee601e3e3bd6c69beea619dd0489d) ) // ball control memory
	150	ROM_LOAD( "501074.k3", 0x0000, 0x0020, CRC(515a34ba) SHA1(471ca9d99851591ff11a87d18b88871edd7fd268) ) // number character generation
151	151	ROM_END
152	152
153	153
154		ROM_START( ramtek3 ) // maybe Hockey?
	154	ROM_START( ramtek3 ) // maybe Hockey?
155	155	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
156	156
157	157	ROM_REGION( 0x0020, "roms", ROMREGION_ERASE00 )

trunk/src/mame/drivers/aerofgt.c
r29404	r29405
1489	1489	MCFG_VSYSTEM_SPR2_SET_GFXREGION(2)
1490	1490	MCFG_VSYSTEM_SPR2_GFXDECODE("gfxdecode")
1491	1491	MCFG_VSYSTEM_SPR2_PALETTE("palette")
1492
	1492
1493	1493	MCFG_DEVICE_ADD("vsystem_spr_ol2", VSYSTEM_SPR2, 0)
1494	1494	MCFG_VSYSTEM_SPR2_SET_TILE_INDIRECT( aerofgt_state, aerofgt_ol2_tile_callback )
1495	1495	MCFG_VSYSTEM_SPR2_SET_GFXREGION(3)
r29404	r29405
1542	1542	MCFG_VSYSTEM_SPR2_SET_GFXREGION(2)
1543	1543	MCFG_VSYSTEM_SPR2_GFXDECODE("gfxdecode")
1544	1544	MCFG_VSYSTEM_SPR2_PALETTE("palette")
1545
	1545
1546	1546	MCFG_DEVICE_ADD("vsystem_spr_ol2", VSYSTEM_SPR2, 0)
1547	1547	MCFG_VSYSTEM_SPR2_SET_TILE_INDIRECT( aerofgt_state, aerofgt_ol2_tile_callback ) // rom lookup
1548	1548	MCFG_VSYSTEM_SPR2_SET_PRITYPE(1)
r29404	r29405
1596	1596	MCFG_VSYSTEM_SPR2_SET_GFXREGION(2)
1597	1597	MCFG_VSYSTEM_SPR2_GFXDECODE("gfxdecode")
1598	1598	MCFG_VSYSTEM_SPR2_PALETTE("palette")
1599
	1599
1600	1600	MCFG_DEVICE_ADD("vsystem_spr_ol2", VSYSTEM_SPR2, 0)
1601	1601	MCFG_VSYSTEM_SPR2_SET_TILE_INDIRECT( aerofgt_state, aerofgt_ol2_tile_callback )
1602	1602	MCFG_VSYSTEM_SPR2_SET_GFXREGION(3)
r29404	r29405
1650	1650	MCFG_VSYSTEM_SPR2_SET_GFXREGION(2)
1651	1651	MCFG_VSYSTEM_SPR2_GFXDECODE("gfxdecode")
1652	1652	MCFG_VSYSTEM_SPR2_PALETTE("palette")
1653
1654		MCFG_DEVICE_ADD("vsystem_spr_ol2", VSYSTEM_SPR2, 0)
	1653
	1654	MCFG_DEVICE_ADD("vsystem_spr_ol2", VSYSTEM_SPR2, 0)
1655	1655	MCFG_VSYSTEM_SPR2_SET_TILE_INDIRECT( aerofgt_state, aerofgt_ol2_tile_callback )
1656	1656	MCFG_VSYSTEM_SPR2_SET_GFXREGION(3)
1657	1657	MCFG_VSYSTEM_SPR2_GFXDECODE("gfxdecode")
r29404	r29405
1806	1806	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
1807	1807	MCFG_SCREEN_SIZE(648, 648)
1808	1808	MCFG_SCREEN_VISIBLE_AREA(08+14, 448-1+4, 08, 308-1)
1809		MCFG_SCREEN_UPDATE_DRIVER(aerofgt_state, screen_update_wbbc97)
	1809	MCFG_SCREEN_UPDATE_DRIVER(aerofgt_state, screen_update_wbbc97)
1810	1810
1811	1811	MCFG_GFXDECODE_ADD("gfxdecode", "palette", wbbc97)
1812	1812	MCFG_PALETTE_ADD("palette", 2048)

trunk/src/mame/drivers/coinmstr.c
r29404	r29405
18	18
19	19	Technical notes....
20	20
21
	21
22	22	There are at least 2 different boards.
23
	23
24	24	A) Unknown, with 2x 6264 RAM, mapped $C000-$DFFF and $E000-$FFFF.
25	25	B) 'PCB-001-POK', with 3x 6116 RAM, mapped $E000-$E7FF, $E800-$EFFF, and $F000-$F7FF.
26	26
r29404	r29405
40	40
41	41	AY-3-8912
42	42	---------
43
	43
44	44	- IO pins connected to DIP switches bank.
45	45	- Data pin connected to CPU data pin.
46	46	- BC1 goes to PAL IC12 pin 12
r29404	r29405
50	50
51	51	PIAs
52	52	----
53
	53
54	54	PIA0 (IC24) Port A --> Input.
55	55	PIA0 (IC24) Port B --> Output.
56	56
r29404	r29405
58	58	PB0 to PB6 go to ULN2003 (IC19) then on PCB connector.
59	59	PB7 goes to ULM2003 (IC40) pin 1 then on PCB connector.
60	60
61
	61
62	62	PIA1 (IC39) Port A --> Output.
63	63	PIA1 (IC39) Port B --> Output.
64	64
65	65	PA0-PA7 go to 22 KOhm resistor, then a "pull up" capacitor, and then into the base of a transistor.
66		Collector connected to +5V, emitter is the output (1 KOhm pulldown), it goes into an ULN2803
67		and then to PCB connector. 3 of that transistors outputs (input of the ULN) are connected
68		together and connected to another circuit that generate 2 more outputs on PCB connector.
69		(them seem unused no solder on the pcb connector)
	66	Collector connected to +5V, emitter is the output (1 KOhm pulldown), it goes into an ULN2803
	67	and then to PCB connector. 3 of that transistors outputs (input of the ULN) are connected
	68	together and connected to another circuit that generate 2 more outputs on PCB connector.
	69	(them seem unused no solder on the pcb connector)
70	70
71	71	PB0 to PB6 goes to ULN2003 (IC34) then on PCB connector.
72	72	PB7 goes to ULM2003 (IC40) pin 2 then on PCB connector.
r29404	r29405
78	78	PB0 to PB6 go to ULN2003 (IC31) then on PCB connector.
79	79	PB7 goes to ULM2003 (IC40) pin 3 then on PCB connector.
80	80
81
	81
82	82	====================================================================================
83	83
84	84	Notes by game....
r29404	r29405
91	91
92	92	DIP switch #1 changes the minimal hand between "Jacks or Better" and
93	93	"Pair of Aces".
94
	94
95	95	There are two bookkeeping modes. I think these are for different levels
96	96	like operator and manager/supervisor. With the DIP switch #4 you can
97	97	switch between them. Is possible that this input would be meant to be
r29404	r29405
114	114
115	115	Pressing DEAL/START, you can get the winning hands, occurence of
116	116	spades, diamonds, clubs and hearts. also number of jokers dealt.
117
	117
118	118	With DIP switch #8 ON, you can enter a sort of test mode, where you
119	119	can set the cards using the HOLD buttons, and test the winning hands.
120	120
r29404	r29405
335	335	/* 2x 6462 hardware C000-DFFF & E000-FFFF */
336	336	static ADDRESS_MAP_START( jpcoin_map, AS_PROGRAM, 8, coinmstr_state )
337	337	AM_RANGE(0x0000, 0xbfff) AM_ROM
338		AM_RANGE(0xc000, 0xdfff) AM_RAM /* 2x 6462 hardware */
	338	AM_RANGE(0xc000, 0xdfff) AM_RAM /* 2x 6462 hardware */
339	339	AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE(quizmstr_bg_w) AM_SHARE("videoram")
340	340	AM_RANGE(0xe800, 0xefff) AM_RAM_WRITE(quizmstr_attr1_w) AM_SHARE("attr_ram1")
341	341	AM_RANGE(0xf000, 0xf7ff) AM_RAM_WRITE(quizmstr_attr2_w) AM_SHARE("attr_ram2")
r29404	r29405
345	345	/* 3x 6116 hardware E000-E800, E800-EFFF & F000-F7FF */
346	346	static ADDRESS_MAP_START( jpcoin2_map, AS_PROGRAM, 8, coinmstr_state )
347	347	AM_RANGE(0x0000, 0xbfff) AM_ROM
348		AM_RANGE(0xc000, 0xdfff) AM_RAM /* only for the 2x 6462 hardware */
	348	AM_RANGE(0xc000, 0xdfff) AM_RAM /* only for the 2x 6462 hardware */
349	349	AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE(quizmstr_bg_w) AM_SHARE("videoram")
350	350	AM_RANGE(0xe800, 0xefff) AM_RAM_WRITE(quizmstr_attr1_w) AM_SHARE("attr_ram1")
351	351	AM_RANGE(0xf000, 0xf7ff) AM_RAM_WRITE(quizmstr_attr2_w) AM_SHARE("attr_ram2")
r29404	r29405
486	486	AM_RANGE(0xc8, 0xcb) AM_DEVREADWRITE("pia0", pia6821_device, read, write) /* confirmed */
487	487	AM_RANGE(0xd0, 0xd3) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
488	488	AM_RANGE(0xd8, 0xdb) AM_DEVREADWRITE("pia2", pia6821_device, read, write) /* confirmed */
489		// AM_RANGE(0xc0, 0xc1) AM_READ(ff_r) /* needed to boot */
	489	// AM_RANGE(0xc0, 0xc1) AM_READ(ff_r) /* needed to boot */
490	490	AM_RANGE(0xc4, 0xc4) AM_READ(ff_r) /* needed to boot */
491	491	ADDRESS_MAP_END
492	492
r29404	r29405
820	820	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
821	821	INPUT_PORTS_END
822	822
823		static INPUT_PORTS_START( supnudg2 ) /* need to find the button 'B' to be playable */
	823	static INPUT_PORTS_START( supnudg2 ) /* need to find the button 'B' to be playable */
824	824	PORT_START("PIA0.A")
825		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("1 Pound (5 credits)") // coin x 5
826		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("50 Pence (2.5 credits)") // coin x 2.5
827		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_NAME("20 Pence (1 credit)") // coin x 1
828		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_NAME("10 Pence (0.5 credit)") // coin x 0.5
	825	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("1 Pound (5 credits)") // coin x 5
	826	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("50 Pence (2.5 credits)") // coin x 2.5
	827	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_NAME("20 Pence (1 credit)") // coin x 1
	828	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_NAME("10 Pence (0.5 credit)") // coin x 0.5
829	829	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A) PORT_NAME("PIA0.A_0x10")
830	830	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) PORT_NAME("PIA0.A_0x20")
831	831	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D) PORT_NAME("PIA0.A_0x40")
r29404	r29405
992	992	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
993	993	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
994	994	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
995		/* PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
996		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
997		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
998		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
999		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1000		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1001		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1002		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	995	/* PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
	996	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	997	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	998	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	999	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1000	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1001	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1002	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1003	1003	*/
1004	1004	PORT_START("PIA2.B")
1005	1005	PORT_DIPNAME( 0x01, 0x01, "PIA2.B" )
r29404	r29405
1525	1525	MCFG_CPU_MODIFY("maincpu")
1526	1526	MCFG_CPU_PROGRAM_MAP(jpcoin_map)
1527	1527	MCFG_CPU_IO_MAP(jpcoin_io_map)
1528		// MCFG_NVRAM_ADD_0FILL("attr_ram3")
	1528	// MCFG_NVRAM_ADD_0FILL("attr_ram3")
1529	1529	MACHINE_CONFIG_END
1530	1530
1531	1531	static MACHINE_CONFIG_DERIVED( jpcoin2, coinmstr )
1532	1532	MCFG_CPU_MODIFY("maincpu")
1533	1533	MCFG_CPU_PROGRAM_MAP(jpcoin2_map)
1534	1534	MCFG_CPU_IO_MAP(jpcoin2_io_map)
1535		// MCFG_NVRAM_ADD_0FILL("attr_ram3")
	1535	// MCFG_NVRAM_ADD_0FILL("attr_ram3")
1536	1536	MACHINE_CONFIG_END
1537	1537
1538	1538	/*
r29404	r29405
1691	1691
1692	1692	/*
1693	1693	Looks like the 2x 6264, since checks C000-DFFF
1694
	1694
1695	1695	BP 1D0 (PIAS init)
1696	1696	BP 1102 (calls)
1697
	1697
1698	1698	Output C0
1699	1699	Input C1
1700
	1700
1701	1701	Input C8
1702	1702	Output C9 (masked)
1703	1703	Output CA
1704
	1704
1705	1705	Input D0
1706	1706	Output D1
1707	1707	Output D2
1708	1708	Input D3
1709	1709	Output DA
1710
	1710
1711	1711	Output E0 CRTC
1712	1712	Output E1 CRTC
1713	1713
r29404	r29405
1753	1753	ROM_LOAD( "jp88-1.ic9", 0x0000, 0x4000, CRC(60d31daf) SHA1(204537887388f1a174d1a09331186182be31e8ee) )
1754	1754
1755	1755	ROM_REGION( 0x4000, "gfx1", 0 )
1756		ROM_LOAD( "jp88-3.ic45", 0x0000, 0x2000, CRC(f2f92a7e) SHA1(ce6f6fd5af0049269357527650b51a1016caf636) )
1757		ROM_LOAD( "jp88-2.ic41", 0x2000, 0x2000, CRC(57db61b2) SHA1(a3bc2056866cbb9fdca52e62f2ff4a952d1d7484) )
	1756	ROM_LOAD( "jp88-3.ic45", 0x0000, 0x2000, CRC(f2f92a7e) SHA1(ce6f6fd5af0049269357527650b51a1016caf636) )
	1757	ROM_LOAD( "jp88-2.ic41", 0x2000, 0x2000, CRC(57db61b2) SHA1(a3bc2056866cbb9fdca52e62f2ff4a952d1d7484) )
1758	1758	ROM_END
1759	1759
1760	1760

trunk/src/mame/drivers/docastle.c
r29404	r29405
626	626
627	627	/* video hardware */
628	628	MCFG_MC6845_ADD("crtc", H46505, "screen", XTAL_9_828MHz / 16, crtc_intf)
629
	629
630	630	MCFG_SCREEN_ADD("screen", RASTER)
631	631	MCFG_SCREEN_RAW_PARAMS(XTAL_9_828MHz/2, 0x138, 8, 0x100-8, 0x108, 0, 0xc0) // from crtc
632	632	MCFG_SCREEN_UPDATE_DRIVER(docastle_state, screen_update_docastle)

trunk/src/mame/drivers/bzone.c
r29404	r29405
560	560	MCFG_SCREEN_VISIBLE_AREA(0, 580, 0, 400)
561	561	MCFG_SCREEN_UPDATE_DEVICE("vector", vector_device, screen_update)
562	562
563		MCFG_DEVICE_ADD("avg", AVG_BZONE, 0)
	563	MCFG_DEVICE_ADD("avg", AVG_BZONE, 0)
564	564	MCFG_AVGDVG_VECTOR("vector")
565	565
566	566	/* Drivers */

trunk/src/mame/drivers/cntsteer.c
r29404	r29405
73	73	required_device<cpu_device> m_subcpu;
74	74	required_device<gfxdecode_device> m_gfxdecode;
75	75	required_device<palette_device> m_palette;
76
	76
77	77	DECLARE_WRITE8_MEMBER(zerotrgt_vregs_w);
78	78	DECLARE_WRITE8_MEMBER(cntsteer_vregs_w);
79	79	DECLARE_WRITE8_MEMBER(cntsteer_foreground_vram_w);

trunk/src/mame/drivers/dblewing.c
r29404	r29405
394	394	MCFG_DECO16IC_ADD("tilegen1", dblewing_deco16ic_tilegen1_intf)
395	395	MCFG_DECO16IC_GFXDECODE("gfxdecode")
396	396	MCFG_DECO16IC_PALETTE("palette")
397
	397
398	398	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
399	399	decospr_device::set_gfx_region(*device, 2);
400	400	decospr_device::set_pri_callback(*device, dblwings_pri_callback);

trunk/src/mame/drivers/hornet.c
r29404	r29405
1002	1002	MCFG_PALETTE_ADD("palette", 65536)
1003	1003
1004	1004	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1005
	1005
1006	1006	MCFG_K037122_ADD("k037122_1", "screen", 0)
1007	1007	MCFG_K037122_GFXDECODE("gfxdecode")
1008	1008	MCFG_K037122_PALETTE("palette")
r29404	r29405
1077	1077	MCFG_K037122_ADD("k037122_1", "lscreen", 0)
1078	1078	MCFG_K037122_GFXDECODE("gfxdecode")
1079	1079	MCFG_K037122_PALETTE("palette")
1080
	1080
1081	1081	MCFG_K037122_ADD("k037122_2", "rscreen", 1)
1082	1082	MCFG_K037122_GFXDECODE("gfxdecode")
1083	1083	MCFG_K037122_PALETTE("palette")

trunk/src/mame/drivers/ddragon3.c
r29404	r29405
802	802	{
803	803	m_paletteram.resize(m_palette->entries());
804	804	m_palette->basemem().set(m_paletteram, ENDIANNESS_BIG, 2);
805
	805
806	806	save_item(NAME(m_vreg));
807	807	save_item(NAME(m_bg_scrollx));
808	808	save_item(NAME(m_bg_scrolly));
r29404	r29405
879	879
880	880	MCFG_PALETTE_MODIFY("palette")
881	881	MCFG_PALETTE_FORMAT(xxxxBBBBGGGGRRRR)
882
	882
883	883	MCFG_SCREEN_MODIFY("screen")
884	884	MCFG_SCREEN_UPDATE_DRIVER(ddragon3_state, screen_update_ctribe)
885	885

trunk/src/mame/drivers/discoboy.c
r29404	r29405
487	487	static MACHINE_CONFIG_START( discoboy, discoboy_state )
488	488
489	489	/* basic machine hardware */
490		MCFG_CPU_ADD("maincpu", Z80, XTAL_12MHz/2) /* 6 MHz? */
	490	MCFG_CPU_ADD("maincpu", Z80, XTAL_12MHz/2) /* 6 MHz? */
491	491	MCFG_CPU_PROGRAM_MAP(discoboy_map)
492	492	MCFG_CPU_IO_MAP(io_map)
493	493	MCFG_CPU_VBLANK_INT_DRIVER("screen", discoboy_state, irq0_line_hold)
494	494
495		MCFG_CPU_ADD("audiocpu", Z80, XTAL_10MHz/2) /* 5 MHz? */
	495	MCFG_CPU_ADD("audiocpu", Z80, XTAL_10MHz/2) /* 5 MHz? */
496	496	MCFG_CPU_PROGRAM_MAP(sound_map)
497	497	MCFG_CPU_PERIODIC_INT_DRIVER(discoboy_state, nmi_line_pulse, 32*60)
498	498
r29404	r29405
513	513	/* sound hardware */
514	514	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
515	515
516		MCFG_SOUND_ADD("ymsnd", YM3812, XTAL_10MHz/4) /* 2.5 MHz? */
	516	MCFG_SOUND_ADD("ymsnd", YM3812, XTAL_10MHz/4) /* 2.5 MHz? */
517	517	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.6)
518	518	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.6)
519	519

trunk/src/mame/drivers/gaplus.c
r29404	r29405
549	549	MCFG_NAMCO56XX_IN_3_CB(IOPORT("BUTTONS"))
550	550	MCFG_NAMCO56XX_OUT_0_CB(WRITE8(gaplus_state, out_lamps0))
551	551	MCFG_NAMCO56XX_OUT_1_CB(WRITE8(gaplus_state, out_lamps1))
552
	552
553	553	MCFG_DEVICE_ADD("namcoio_2", NAMCO58XX, 0)
554	554	MCFG_NAMCO58XX_IN_0_CB(IOPORT("DSWA_HIGH"))
555	555	MCFG_NAMCO58XX_IN_1_CB(IOPORT("DSWB_LOW"))
556	556	MCFG_NAMCO58XX_IN_2_CB(IOPORT("DSWB_HIGH"))
557	557	MCFG_NAMCO58XX_IN_3_CB(IOPORT("DSWA_LOW"))
558
	558
559	559	MCFG_NAMCO_62XX_ADD("62xx", 24576000/6/2) /* totally made up - TODO: fix */
560	560	//MCFG_NAMCO_62XX_INPUT_0_CB(IOPORT("IN0L"))
561	561	//MCFG_NAMCO_62XX_INPUT_1_CB(IOPORT("IN0H"))
r29404	r29405
563	563	//MCFG_NAMCO_62XX_INPUT_3_CB(IOPORT("IN1H"))
564	564	//MCFG_NAMCO_62XX_OUTPUT_0_CB(WRITE8(gaplus_state,out_0))
565	565	//MCFG_NAMCO_62XX_OUTPUT_1_CB(WRITE8(gaplus_state,out_1))
566
	566
567	567	/* video hardware */
568	568	MCFG_SCREEN_ADD("screen", RASTER)
569	569	MCFG_SCREEN_REFRESH_RATE(60.606060)
r29404	r29405
597	597	MCFG_NAMCO58XX_IN_1_CB(IOPORT("P1"))
598	598	MCFG_NAMCO58XX_IN_2_CB(IOPORT("P2"))
599	599	MCFG_NAMCO58XX_IN_3_CB(IOPORT("BUTTONS"))
600
	600
601	601	MCFG_DEVICE_REPLACE("namcoio_2", NAMCO56XX, 0)
602	602	MCFG_NAMCO56XX_IN_0_CB(IOPORT("DSWA_HIGH"))
603	603	MCFG_NAMCO56XX_IN_1_CB(IOPORT("DSWB_LOW"))
r29404	r29405
616	616	MCFG_NAMCO56XX_IN_1_CB(IOPORT("P1"))
617	617	MCFG_NAMCO56XX_IN_2_CB(IOPORT("P2"))
618	618	MCFG_NAMCO56XX_IN_3_CB(IOPORT("BUTTONS"))
619
	619
620	620	MCFG_DEVICE_REPLACE("namcoio_2", NAMCO58XX, 0)
621	621	MCFG_NAMCO58XX_IN_0_CB(IOPORT("DSWA_HIGH"))
622	622	MCFG_NAMCO58XX_IN_1_CB(IOPORT("DSWB_LOW"))

trunk/src/mame/drivers/5clown.c
r29404	r29405
462	462	m_audiocpu(*this, "audiocpu"),
463	463	m_ay8910(*this, "ay8910"),
464	464	m_gfxdecode(*this, "gfxdecode"),
465		m_palette(*this, "palette")
	465	m_palette(*this, "palette")
466	466	{
467	467	}
468	468

trunk/src/mame/drivers/exedexes.c
r29404	r29405
236	236	MCFG_SCREEN_PALETTE("palette")
237	237
238	238	MCFG_GFXDECODE_ADD("gfxdecode", "palette", exedexes)
239
	239
240	240	MCFG_PALETTE_ADD("palette", 644+644+1616+1616)
241	241	MCFG_PALETTE_INDIRECT_ENTRIES(256)
242	242	MCFG_PALETTE_INIT_OWNER(exedexes_state, exedexes)

trunk/src/mame/drivers/witch.c
r29404	r29405
221	221	#define MAIN_CLOCK XTAL_12MHz
222	222	#define CPU_CLOCK MAIN_CLOCK / 4
223	223	#define YM2203_CLOCK MAIN_CLOCK / 4
224		#define ES8712_CLOCK 8000 // 8Khz, it's the only clock for sure (pin13) it come from pin14 of M5205.
	224	#define ES8712_CLOCK 8000 // 8Khz, it's the only clock for sure (pin13) it come from pin14 of M5205.
225	225
226	226
227	227	#include "emu.h"
r29404	r29405
249	249	tilemap_t *m_gfx0a_tilemap;
250	250	tilemap_t *m_gfx0b_tilemap;
251	251	tilemap_t *m_gfx1_tilemap;
252
	252
253	253	required_device<cpu_device> m_maincpu;
254	254	required_device<cpu_device> m_subcpu;
255	255	required_device<gfxdecode_device> m_gfxdecode;
256
	256
257	257	required_shared_ptr<UINT8> m_gfx0_vram;
258	258	required_shared_ptr<UINT8> m_gfx0_cram;
259	259	required_shared_ptr<UINT8> m_gfx1_vram;
260	260	required_shared_ptr<UINT8> m_gfx1_cram;
261	261	required_shared_ptr<UINT8> m_sprite_ram;
262	262	required_device<palette_device> m_palette;
263
	263
264	264	int m_scrollx;
265	265	int m_scrolly;
266	266	UINT8 m_reg_a002;
r29404	r29405
305	305	}
306	306
307	307	SET_TILE_INFO_MEMBER(1,
308		code, //tiles beyond 0x7ff only for sprites?
	308	code, //tiles beyond 0x7ff only for sprites?
309	309	color & 0x0f,
310	310	0);
311	311	}
r29404	r29405
833	833	MCFG_CPU_ADD("sub", Z80, CPU_CLOCK) /* 3 MHz */
834	834	MCFG_CPU_PROGRAM_MAP(map_sub)
835	835	MCFG_CPU_VBLANK_INT_DRIVER("screen", witch_state, irq0_line_assert)
836
	836
837	837	MCFG_QUANTUM_TIME(attotime::from_hz(6000))
838	838
839	839	MCFG_NVRAM_ADD_0FILL("nvram")
r29404	r29405
854	854	/* sound hardware */
855	855	MCFG_SPEAKER_STANDARD_MONO("mono")
856	856
857		MCFG_ES8712_ADD("essnd", ES8712_CLOCK) /* 8Khz, it's the only clock for sure (pin13) it comes from pin14 of M5205 */
	857	MCFG_ES8712_ADD("essnd", ES8712_CLOCK) /* 8Khz, it's the only clock for sure (pin13) it comes from pin14 of M5205 */
858	858	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
859	859
860		MCFG_SOUND_ADD("ym1", YM2203, YM2203_CLOCK) /* 3 MHz */
	860	MCFG_SOUND_ADD("ym1", YM2203, YM2203_CLOCK) /* 3 MHz */
861	861	MCFG_YM2203_AY8910_INTF(&ay8910_config_1)
862	862	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.5)
863	863
864		MCFG_SOUND_ADD("ym2", YM2203, YM2203_CLOCK) /* 3 MHz */
	864	MCFG_SOUND_ADD("ym2", YM2203, YM2203_CLOCK) /* 3 MHz */
865	865	MCFG_YM2203_AY8910_INTF(&ay8910_config_2)
866	866	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.5)
867	867

trunk/src/mame/drivers/multfish_boot.c
r29404	r29405
11	11	Sets below are bootleg / hacked sets, descriptions of what has been modified are provided where known
12	12	-- use of these sets may present a risk to the operator, you should always ensure you're using original Igrosoft program roms on your PCB!
13	13
14		--------------------------------
	14	--------------------------------
15	15
16	16	The sets which differs from the originals by 5-6 bytes are bootlegs that simply change
17	17	the banking address. Usually to convert a Crazy Monkey PCB which use the address "F9".

trunk/src/mame/drivers/volfied.c
r29404	r29405
274	274	MCFG_PC090OJ_ADD("pc090oj", volfied_pc090oj_intf)
275	275	MCFG_PC090OJ_GFXDECODE("gfxdecode")
276	276	MCFG_PC090OJ_PALETTE("palette")
277
	277
278	278	/* sound hardware */
279	279	MCFG_SPEAKER_STANDARD_MONO("mono")
280	280

trunk/src/mame/drivers/deco32.c
r29404	r29405
1759	1759	MCFG_DECO16IC_ADD("tilegen1", captaven_deco16ic_tilegen1_intf)
1760	1760	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1761	1761	MCFG_DECO16IC_PALETTE("palette")
1762
	1762
1763	1763	MCFG_DECO16IC_ADD("tilegen2", captaven_deco16ic_tilegen2_intf)
1764	1764	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1765	1765	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
1834	1834	MCFG_DECO16IC_ADD("tilegen1", fghthist_deco16ic_tilegen1_intf)
1835	1835	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1836	1836	MCFG_DECO16IC_PALETTE("palette")
1837
	1837
1838	1838	MCFG_DECO16IC_ADD("tilegen2", fghthist_deco16ic_tilegen2_intf)
1839	1839	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1840	1840	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
1896	1896	MCFG_DECO16IC_ADD("tilegen1", fghthist_deco16ic_tilegen1_intf)
1897	1897	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1898	1898	MCFG_DECO16IC_PALETTE("palette")
1899
	1899
1900	1900	MCFG_DECO16IC_ADD("tilegen2", fghthist_deco16ic_tilegen2_intf)
1901	1901	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1902	1902	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
2021	2021	MCFG_DECO16IC_ADD("tilegen1", dragngun_deco16ic_tilegen1_intf)
2022	2022	MCFG_DECO16IC_GFXDECODE("gfxdecode")
2023	2023	MCFG_DECO16IC_PALETTE("palette")
2024
	2024
2025	2025	MCFG_DECO16IC_ADD("tilegen2", dragngun_deco16ic_tilegen2_intf)
2026	2026	MCFG_DECO16IC_GFXDECODE("gfxdecode")
2027	2027	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
2108	2108	MCFG_DECO16IC_ADD("tilegen1", lockload_deco16ic_tilegen1_intf)
2109	2109	MCFG_DECO16IC_GFXDECODE("gfxdecode")
2110	2110	MCFG_DECO16IC_PALETTE("palette")
2111
	2111
2112	2112	MCFG_DECO16IC_ADD("tilegen2", lockload_deco16ic_tilegen2_intf)
2113	2113	MCFG_DECO16IC_GFXDECODE("gfxdecode")
2114	2114	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
2197	2197	MCFG_DECO16IC_ADD("tilegen1", tattass_deco16ic_tilegen1_intf)
2198	2198	MCFG_DECO16IC_GFXDECODE("gfxdecode")
2199	2199	MCFG_DECO16IC_PALETTE("palette")
2200
	2200
2201	2201	MCFG_DECO16IC_ADD("tilegen2", tattass_deco16ic_tilegen2_intf)
2202	2202	MCFG_DECO16IC_GFXDECODE("gfxdecode")
2203	2203	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
2245	2245	MCFG_SCREEN_REFRESH_RATE(60)
2246	2246	MCFG_SCREEN_SIZE(428, 328)
2247	2247	MCFG_SCREEN_VISIBLE_AREA(08, 408-1, 18, 318-1)
2248		MCFG_SCREEN_UPDATE_DRIVER(deco32_state, screen_update_nslasher)
	2248	MCFG_SCREEN_UPDATE_DRIVER(deco32_state, screen_update_nslasher)
2249	2249
2250	2250	MCFG_DECO16IC_ADD("tilegen1", tattass_deco16ic_tilegen1_intf)
2251	2251	MCFG_DECO16IC_GFXDECODE("gfxdecode")
2252	2252	MCFG_DECO16IC_PALETTE("palette")
2253
	2253
2254	2254	MCFG_DECO16IC_ADD("tilegen2", tattass_deco16ic_tilegen2_intf)
2255	2255	MCFG_DECO16IC_GFXDECODE("gfxdecode")
2256	2256	MCFG_DECO16IC_PALETTE("palette")

trunk/src/mame/drivers/zaxxon.c
r29404	r29405
1011	1011	MCFG_PALETTE_MODIFY("palette")
1012	1012	MCFG_PALETTE_ENTRIES(512)
1013	1013	MCFG_PALETTE_INIT_OWNER(zaxxon_state, zaxxon)
1014
	1014
1015	1015	MCFG_VIDEO_START_OVERRIDE(zaxxon_state,congo)
1016	1016	MCFG_SCREEN_MODIFY("screen")
1017	1017	MCFG_SCREEN_UPDATE_DRIVER(zaxxon_state, screen_update_congo)

trunk/src/mame/drivers/fungames.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	Fun Games discrete hardware games
4
	4
5	5	Biplane (1975)
6	6	Biplane 4 (1976)
7	7	King
r29404	r29405
9	9	Take 5 (1975)
10	10	Take 7 (1975)
11	11	Tankers (1975)
12
	12
13	13	***************************************************************************/
14	14
15	15
r29404	r29405
49	49	public:
50	50	fungames_state(const machine_config &mconfig, device_type type, const char *tag)
51	51	: driver_device(mconfig, type, tag),
52		m_maincpu(*this, "maincpu"),
53		m_video(*this, "fixfreq")
	52	m_maincpu(*this, "maincpu"),
	53	m_video(*this, "fixfreq")
54	54	{
55	55	}
56
	56
57	57	// devices
58	58	required_device<netlist_mame_device_t> m_maincpu;
59	59	required_device<fixedfreq_device> m_video;
60
	60
61	61	protected:
62
	62
63	63	// driver_device overrides
64	64	virtual void machine_start();
65	65	virtual void machine_reset();
66
	66
67	67	virtual void video_start();
68
	68
69	69	private:
70
	70
71	71	};
72	72
73	73
74	74	static NETLIST_START(fungames)
75	75	SOLVER(Solver, 48000)
76		// PARAM(Solver.FREQ, 48000)
	76	// PARAM(Solver.FREQ, 48000)
77	77	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
78	78
79	79	// schematics
80	80	//...
81	81
82		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
83		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	82	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	83	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
84	84	NETLIST_END()
85	85
86	86
r29404	r29405
110	110
111	111
112	112	/***************************************************************************
113
	113
114	114	Game driver(s)
115
	115
116	116	***************************************************************************/
117	117
118	118

trunk/src/mame/drivers/enigma2.c
r29404	r29405
82	82	/* devices */
83	83	required_device<cpu_device> m_maincpu;
84	84	required_device<cpu_device> m_audiocpu;
85		required_device<screen_device> m_screen;
	85	required_device<screen_device> m_screen;
86	86	DECLARE_READ8_MEMBER(dip_switch_r);
87	87	DECLARE_WRITE8_MEMBER(sound_data_w);
88	88	DECLARE_WRITE8_MEMBER(enigma2_flip_screen_w);

trunk/src/mame/drivers/mil4000.c
r29404	r29405
314	314	{
315	315	/* Damn thing!
316	316	708010-708011 communicate with the MCU.
317		The returned value is critical to the reels.
318
319		Writes to MCU:
320
321		0x11 --> seems quiet or null.
322		0x1A --> command for reels state/gfx. Two bytes (command + parameter).
	317	The returned value is critical to the reels.
	318
	319	Writes to MCU:
	320
	321	0x11 --> seems quiet or null.
	322	0x1A --> command for reels state/gfx. Two bytes (command + parameter).
323	323	The second value will be the parameter to feed.
324	324	The MCU will respond with one value (see table below).
325	325
326		bits:
327		7654-3210
328		---- ---- = cherries.
329		---- ---x = single bar.
	326	bits:
	327	7654-3210
	328	---- ---- = cherries.
	329	---- ---x = single bar.
330	330	---- --x- = double bars.
331	331	---- --xx = triple bars.
332		---- -x-- = unknown (combinations produce reset).
333		---- x--- = sevens.
334		---- x--x = double plums.
335		---- x-x- = plums.
336		---- x-xx = bells.
337		---x ---- = blanks.
338		-xx- ---- = some kind of gfx retrace.
339		x--- ---- = reset the game
	332	---- -x-- = unknown (combinations produce reset).
	333	---- x--- = sevens.
	334	---- x--x = double plums.
	335	---- x-x- = plums.
	336	---- x-xx = bells.
	337	---x ---- = blanks.
	338	-xx- ---- = some kind of gfx retrace.
	339	x--- ---- = reset the game
340	340
341	341	There are other commands, like:
342	342	0x1B (+4 parameters)
r29404	r29405
344	344	0x1D (+2 parameters)
345	345	0x1E (+1 parameter)
346	346
347		You can find a 1E-18 at start.
348
	347	You can find a 1E-18 at start.
	348
349	349	*/
350		switch( mcucomm ) /* MCU command */
	350	switch( mcucomm ) /* MCU command */
351	351	{
352		case 0x11: /* Idle - Null */
	352	case 0x11: /* Idle - Null */
353	353	{
354	354	logerror("Writes idle command 0x11 to MCU");
355		return (machine().rand() & 0x0b); // otherwise got corrupt gfx...
	355	return (machine().rand() & 0x0b); // otherwise got corrupt gfx...
356	356	}
357	357
358		case 0x1a: /* Reels state - Control */
	358	case 0x1a: /* Reels state - Control */
359	359	{
360	360	logerror("MCU feedback to command 0x1a with data: %02x\n", mcudata);
361	361	return (machine().rand() & 0x0b);
362	362	}
363	363
364		case 0x1b: /* Unknown */
	364	case 0x1b: /* Unknown */
365	365	{
366	366	logerror("MCU feedback to command 0x1b with data: %02x\n", mcudata);
367	367	return 0x00;
368	368	}
369	369
370		case 0x1c: /* Unknown. Always 00's? */
	370	case 0x1c: /* Unknown. Always 00's? */
371	371	{
372	372	logerror("MCU feedback to command 0x1c with data: %02x\n", mcudata);
373	373	return 0x00;
374	374	}
375	375
376		case 0x1d: /* Unknown */
	376	case 0x1d: /* Unknown */
377	377	{
378	378	logerror("MCU feedback to command 0x1d with data: %02x\n", mcudata);
379	379	return 0x00;
380	380	}
381	381
382		case 0x1e: /* Unknown, only one at boot (1e 18) */
	382	case 0x1e: /* Unknown, only one at boot (1e 18) */
383	383	{
384	384	logerror("MCU feedback to command 0x1e with data: %02x\n", mcudata);
385	385	return 0x00;
r29404	r29405
387	387	}
388	388
389	389	logerror("MCU feedback to unknown command: %02x\n", mcucomm);
390		return (machine().rand() & 0x0b); // otherwise got corrupt gfx...
	390	return (machine().rand() & 0x0b); // otherwise got corrupt gfx...
391	391	}
392	392
393	393	WRITE16_MEMBER(mil4000_state::chewheel_mcu_w)
r29404	r29405
407	407
408	408	READ16_MEMBER(mil4000_state::unk_r)
409	409	{
410		// reads: 51000C-0E. touch screen?
	410	// reads: 51000C-0E. touch screen?
411	411	return 0xff;
412	412	}
413	413
414	414	WRITE16_MEMBER(mil4000_state::unk_w)
415	415	{
416		// writes: 510000-02-04-06-08-0A-0C-0E
417		// logerror("unknown writes from address %04x\n", offset);
	416	// writes: 510000-02-04-06-08-0A-0C-0E
	417	// logerror("unknown writes from address %04x\n", offset);
418	418	}
419	419
420	420
r29404	r29405
444	444	AM_RANGE(0x508000, 0x50bfff) AM_RAM_WRITE(sc2_vram_w) AM_SHARE("sc2_vram") // V62C518256L-35P (U8).
445	445	AM_RANGE(0x50c000, 0x50ffff) AM_RAM_WRITE(sc3_vram_w) AM_SHARE("sc3_vram") // V62C518256L-35P (U8).
446	446
447		AM_RANGE(0x51000c, 0x51000f) AM_READ(unk_r) // no idea what's mapped here.
448		AM_RANGE(0x510000, 0x51000f) AM_WRITE(unk_w) // no idea what's mapped here.
	447	AM_RANGE(0x51000c, 0x51000f) AM_READ(unk_r) // no idea what's mapped here.
	448	AM_RANGE(0x510000, 0x51000f) AM_WRITE(unk_w) // no idea what's mapped here.
449	449
450	450	AM_RANGE(0x708000, 0x708001) AM_READ_PORT("IN0")
451	451	AM_RANGE(0x708002, 0x708003) AM_READ_PORT("IN1")
r29404	r29405
456	456	AM_RANGE(0x70801e, 0x70801f) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
457	457
458	458	AM_RANGE(0x780000, 0x780fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
459		AM_RANGE(0xff0000, 0xff3fff) AM_RAM AM_SHARE("nvram") // V62C51864L-70P (U77).
460		AM_RANGE(0xffc000, 0xffffff) AM_RAM // V62C51864L-70P (U78).
	459	AM_RANGE(0xff0000, 0xff3fff) AM_RAM AM_SHARE("nvram") // V62C51864L-70P (U77).
	460	AM_RANGE(0xffc000, 0xffffff) AM_RAM // V62C51864L-70P (U78).
461	461
462	462	ADDRESS_MAP_END
463	463
r29404	r29405
702	702	Similar hardware to TOP XXI
703	703
704	704	But...
705		2x V62C518256L-35P. 32K x 8 Static RAM. (U7-U8)
	705	2x V62C518256L-35P. 32K x 8 Static RAM. (U7-U8)
706	706	2x V62C51864L-70P. 8K x 8 Static RAM. (U77-U78)
707	707
708	708	Only U77 is tied to the battery.

trunk/src/mame/drivers/gticlub.c
r29404	r29405
260	260	required_device<adsp21062_device> m_dsp;
261	261	optional_device<cpu_device> m_dsp2;
262	262	required_device<k056800_device> m_k056800;
263		required_device<adc1038_device> m_adc1038;
	263	required_device<adc1038_device> m_adc1038;
264	264	required_device<eeprom_serial_93cxx_device> m_eeprom;
265	265	required_device<palette_device> m_palette;
266	266
r29404	r29405
1108	1108	MCFG_SCREEN_UPDATE_DRIVER(gticlub_state, screen_update_hangplt)
1109	1109
1110	1110	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1111
	1111
1112	1112	MCFG_K001604_ADD("k001604_1", hangplt_k001604_intf_l)
1113	1113	MCFG_K001604_GFXDECODE("gfxdecode")
1114	1114	MCFG_K001604_PALETTE("palette")
1115
	1115
1116	1116	MCFG_K001604_ADD("k001604_2", hangplt_k001604_intf_r)
1117	1117	MCFG_K001604_GFXDECODE("gfxdecode")
1118	1118	MCFG_K001604_PALETTE("palette")

trunk/src/mame/drivers/dkong.c
r29404	r29405
752	752	}
753	753
754	754	WRITE8_MEMBER(dkong_state::dkong_z80dma_rdy_w)
755		{
	755	{
756	756	m_z80dma->rdy_w(data & 0x01);
757	757	}
758	758
r29404	r29405
1731	1731	MCFG_SCREEN_UPDATE_DRIVER(dkong_state, screen_update_dkong)
1732	1732	MCFG_SCREEN_PALETTE("palette")
1733	1733
1734		MCFG_GFXDECODE_ADD("gfxdecode", "palette", dkong)
	1734	MCFG_GFXDECODE_ADD("gfxdecode", "palette", dkong)
1735	1735	MCFG_PALETTE_ADD("palette", DK3_PALETTE_LENGTH)
1736	1736
1737	1737	MCFG_PALETTE_INIT_OWNER(dkong_state,dkong3)
r29404	r29405
1763	1763
1764	1764	static MACHINE_CONFIG_DERIVED( dkong3b, dkongjr )
1765	1765
1766		/* basic machine hardware */
	1766	/* basic machine hardware */
1767	1767	MCFG_PALETTE_MODIFY("palette")
1768	1768	MCFG_PALETTE_INIT_OWNER(dkong_state,dkong3)
1769	1769	MACHINE_CONFIG_END

trunk/src/mame/drivers/ddenlovr.c
r29404	r29405
9785	9785
9786	9786	/* devices */
9787	9787	// MCFG_DEVICE_ADD("rtc", MSM6242, XTAL_32_768kHz)
9788		// MCFG_MSM6242_OUT_INT_HANDLER(WRITELINE(ddenlovr_state, hanakanz_rtc_irq))
	9788	// MCFG_MSM6242_OUT_INT_HANDLER(WRITELINE(ddenlovr_state, hanakanz_rtc_irq))
9789	9789	MACHINE_CONFIG_END
9790	9790
9791	9791	static MACHINE_CONFIG_DERIVED( kotbinsp, kotbinyo )

trunk/src/mame/drivers/kaneko16.c
r29404	r29405
1666	1666
1667	1667	/* video hardware */
1668	1668	MCFG_SCREEN_ADD("screen", RASTER)
1669		// MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK) // mangled sprites otherwise
	1669	// MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK) // mangled sprites otherwise
1670	1670	MCFG_SCREEN_REFRESH_RATE(60)
1671	1671	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
1672	1672	MCFG_SCREEN_SIZE(256, 256)
1673	1673	MCFG_SCREEN_VISIBLE_AREA(0, 256-1, 16, 240-1)
1674	1674	MCFG_SCREEN_UPDATE_DRIVER(kaneko16_berlwall_state, screen_update_berlwall)
1675		// MCFG_SCREEN_PALETTE("palette")
	1675	// MCFG_SCREEN_PALETTE("palette")
1676	1676
1677	1677	MCFG_GFXDECODE_ADD("gfxdecode", "palette", 1x4bit_1x4bit)
1678		MCFG_PALETTE_ADD("palette", 2048 )
	1678	MCFG_PALETTE_ADD("palette", 2048 )
1679	1679	MCFG_PALETTE_FORMAT(xGGGGGRRRRRBBBBB)
1680	1680
1681	1681	MCFG_PALETTE_ADD("bgpalette", 32768) /* 32768 static colors for the bg */
r29404	r29405
1688	1688	MCFG_KANEKO_TMAP_GFXDECODE("gfxdecode")
1689	1689
1690	1690	MCFG_DEVICE_ADD_VU002_SPRITES
1691		// kaneko16_sprite_device::set_altspacing(*device, 1);
	1691	// kaneko16_sprite_device::set_altspacing(*device, 1);
1692	1692	MCFG_KANEKO16_SPRITE_GFXDECODE("gfxdecode")
1693	1693
1694	1694	MCFG_VIDEO_START_OVERRIDE(kaneko16_berlwall_state,berlwall)
r29404	r29405
1741	1741	kaneko_view2_tilemap_device::set_gfx_region(*device, 1);
1742	1742	kaneko_view2_tilemap_device::set_offset(*device, 0x5b, -0x8, 256, 240);
1743	1743	MCFG_KANEKO_TMAP_GFXDECODE("gfxdecode")
1744
	1744
1745	1745	MCFG_DEVICE_ADD("view2_1", KANEKO_TMAP, 0)
1746	1746	kaneko_view2_tilemap_device::set_gfx_region(*device, 2);
1747	1747	kaneko_view2_tilemap_device::set_offset(*device, 0x5b, -0x8, 256, 240);
r29404	r29405
1809	1809	MCFG_GFXDECODE_ADD("gfxdecode", "palette", 1x4bit_1x4bit)
1810	1810	MCFG_PALETTE_ADD("palette", 2048)
1811	1811	MCFG_PALETTE_FORMAT(xGGGGGRRRRRBBBBB)
1812
	1812
1813	1813	MCFG_DEVICE_ADD("view2_0", KANEKO_TMAP, 0)
1814	1814	kaneko_view2_tilemap_device::set_gfx_region(*device, 1);
1815	1815	kaneko_view2_tilemap_device::set_offset(*device, 0x33, 0x8, 320, 240);

trunk/src/mame/drivers/mpu4.c
r29404	r29405
34	34	ROM_END
35	35
36	36	ROM_START( m4rltst )
37		ROM_REGION( 0x10000, "maincpu", 0 )
	37	ROM_REGION( 0x10000, "maincpu", 0 )
38	38	ROM_LOAD( "rtv.p1", 0x08000, 0x08000, CRC(7b78f3f2) SHA1(07ef8e6a08fd70ee48e4463672a1230ecc669532) )
39	39	ROM_END
40	40
r29404	r29405
2729	2729
2730	2730
2731	2731
2732		GAME(198?, m4funh , 0 , mod4oki ,mpu4 , mpu4_state, m4default , 0, "<unknown>", "Fun House (unknown) (MPU4)", GAME_FLAGS ) // TUNE ALARM (was in the SC1 Fun House set)
	2732	GAME(198?, m4funh , 0 , mod4oki ,mpu4 , mpu4_state, m4default , 0, "<unknown>", "Fun House (unknown) (MPU4)", GAME_FLAGS ) // TUNE ALARM (was in the SC1 Fun House set)
2733	2733
2734	2734
2735	2735	GAME(199?, m4sunseta ,m4sunset ,mod4oki ,mpu4 , mpu4_state,m4default ,ROT0, "Barcrest","Sunset Boulevard (Barcrest) (MPU4) (B25 1.2, set 1)",GAME_FLAGS )

trunk/src/mame/drivers/skylncr.c
r29404	r29405
29	29	****************************************************************************************************
30	30
31	31	Settings:
32
	32
33	33	Pressing F2, you can enter the DIP switches settings.
34	34	Here the translated items:
35	35
r29404	r29405
47	47	\| \|
48	48	'---------------------------------------'
49	49
50		'Special Bonus' and 'Super Star' appearance, are per 1000.
	50	'Special Bonus' and 'Super Star' appearance, are per 1000.
51	51	You also can find the MAME DIP switches menu already translated.
52	52	The <unknown> items still need translation.
53	53
54	54	Press START (key 1) to exit the mode.
55	55
56
	56
57	57	Bookkeeping:
58	58
59	59	Pressing BOOKKEEPING (key 0), you enter the Record Mode.
r29404	r29405
199	199	{
200	200	UINT8 bank = 1;
201	201	UINT16 code = m_reeltiles_1_ram[ tile_index ] + (m_reeltileshigh_1_ram[ tile_index ] << 8);
202		// if (code > 0x200)
203		// bank = 2;
	202	// if (code > 0x200)
	203	// bank = 2;
204	204	SET_TILE_INFO_MEMBER(bank, code, 0, TILE_FLIPYX( 0 ));
205	205	}
206	206
r29404	r29405
516	516	884
517	517	};
518	518
519		static const gfx_layout layout8x8x8_alt = /* for sstar97 */
	519	static const gfx_layout layout8x8x8_alt = /* for sstar97 */
520	520	{
521	521	8,8,
522	522	RGN_FRAC(1,2),
r29404	r29405
572	572	8328/2
573	573	};
574	574
575		static const gfx_layout layout8x32x8_alt = /* for sstar97 */
	575	static const gfx_layout layout8x32x8_alt = /* for sstar97 */
576	576	{
577	577	8,32,
578	578	RGN_FRAC(1,2),
r29404	r29405
1146	1146	ROM_START( sstar97 )
1147	1147	ROM_REGION( 0x80000, "maincpu", 0 )
1148	1148	ROM_LOAD( "27256.u15", 0x0000, 0x8000, CRC(a5da4f92) SHA1(82ac70bd379649f130db017aa226d0247db0f3cd) )
1149		ROM_LOAD( "unknown.u48", 0x8000, 0x8000, BAD_DUMP CRC(9f4c02e3) SHA1(05975184130ea7dd3bb5d32eff77b585bd53e6b5) ) // palette borrowed from other game
	1149	ROM_LOAD( "unknown.u48", 0x8000, 0x8000, BAD_DUMP CRC(9f4c02e3) SHA1(05975184130ea7dd3bb5d32eff77b585bd53e6b5) ) // palette borrowed from other game
1150	1150
1151		ROM_REGION( 0x40000, "gfx1", 0 ) // All ROMs are 28-pins mask ROMs dumped as 27512. Should be dumped as Fujitsu MB831000 or TC531000 (mask ROM).
	1151	ROM_REGION( 0x40000, "gfx1", 0 ) // All ROMs are 28-pins mask ROMs dumped as 27512. Should be dumped as Fujitsu MB831000 or TC531000 (mask ROM).
1152	1152	ROM_LOAD16_BYTE( "bor_dun_4.u23", 0x00000, 0x10000, BAD_DUMP CRC(82c9db19) SHA1(3611fb59bb7c962c7fabe7a29fa72b632fa69bed) )
1153	1153	ROM_LOAD16_BYTE( "bor_dun_2.u25", 0x00001, 0x10000, BAD_DUMP CRC(42ee9b7a) SHA1(b39f677f58072ea7dcd7f49208be1a7b70bdc5e5) )
1154	1154	ROM_LOAD16_BYTE( "bor_dun_3.u24", 0x20000, 0x10000, BAD_DUMP CRC(6d70879b) SHA1(83cbe67cda95e5f3d95065015f6b1b2044b88989) )
1155	1155	ROM_LOAD16_BYTE( "bor_dun_1.u26", 0x20001, 0x10000, BAD_DUMP CRC(1b8b84ac) SHA1(b914bad0b1fb58cf581d1227e8127c6afb906fb7) )
1156	1156
1157		ROM_REGION( 0x40000, "gfx2", 0 ) // All ROMs are 28-pins mask ROMs dumped as 27512. Should be dumped as Fujitsu MB831000 or TC531000 (mask ROM).
	1157	ROM_REGION( 0x40000, "gfx2", 0 ) // All ROMs are 28-pins mask ROMs dumped as 27512. Should be dumped as Fujitsu MB831000 or TC531000 (mask ROM).
1158	1158	ROM_LOAD16_BYTE( "bor_dun_8.u19", 0x00000, 0x10000, BAD_DUMP CRC(daf651a7) SHA1(d4e472aa90aa2b52c997b2f2272007b139e3cbc2) )
1159	1159	ROM_LOAD16_BYTE( "bor_dun_6.u21", 0x00001, 0x10000, BAD_DUMP CRC(1d88bc70) SHA1(49246d96a4ce2b8e9b10e928d7dd13973feac883) )
1160	1160	ROM_LOAD16_BYTE( "bor_dun_7.u20", 0x20000, 0x10000, BAD_DUMP CRC(7e28ba2f) SHA1(ac8d4e95efce87456f569a71650bd7afcb59095e) )

trunk/src/mame/drivers/4enlinea.c
r29404	r29405
188	188	#define SEC_CLOCK XTAL_8MHz
189	189	#define HCGA_CLOCK XTAL_14_31818MHz
190	190
191		#define PRG_CPU_CLOCK MAIN_CLOCK /2 /* 8 MHz. (measured) */
	191	#define PRG_CPU_CLOCK MAIN_CLOCK /2 /* 8 MHz. (measured) */
192	192	#define SND_CPU_CLOCK SEC_CLOCK /2 /* 4 MHz. (measured) */
193	193	#define SND_AY_CLOCK SEC_CLOCK /4 /* 2 MHz. (measured) */
194	194	#define CRTC_CLOCK SEC_CLOCK /2 /* 8 MHz. (measured) */
r29404	r29405
321	321	}
322	322	}
323	323
324		// astring tempstring;
325		// m_chr_gen_base = memregion(subtag(tempstring, "gfx1"))->base();
326		// m_chr_gen = m_chr_gen_base + m_chr_gen_offset[1];
	324	// astring tempstring;
	325	// m_chr_gen_base = memregion(subtag(tempstring, "gfx1"))->base();
	326	// m_chr_gen = m_chr_gen_base + m_chr_gen_offset[1];
327	327	}
328	328
329	329
r29404	r29405
346	346
347	347	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, _4enlinea_state )
348	348	AM_RANGE(0x0000, 0x7fff) AM_ROM
349		// AM_RANGE(0x8000, 0xbfff) AM_RAM // CGA VRAM
	349	// AM_RANGE(0x8000, 0xbfff) AM_RAM // CGA VRAM
350	350	AM_RANGE(0xc000, 0xdfff) AM_RAM
351	351
352	352	AM_RANGE(0xe000, 0xe001) AM_READ(serial_r)
r29404	r29405
355	355	static ADDRESS_MAP_START( main_portmap, AS_IO, 8, _4enlinea_state )
356	356	ADDRESS_MAP_GLOBAL_MASK(0x3ff)
357	357
358		// AM_RANGE(0x3d4, 0x3df) CGA regs
	358	// AM_RANGE(0x3d4, 0x3df) CGA regs
359	359	AM_RANGE(0x3bf, 0x3bf) AM_WRITENOP // CGA mode control, TODO
360	360	ADDRESS_MAP_END
361	361
r29404	r29405
455	455
456	456	void _4enlinea_state::machine_start()
457	457	{
458
459	458	}
460	459
461	460	void _4enlinea_state::machine_reset()
462	461	{
463
464	462	}
465	463
466	464
r29404	r29405
535	533	MCFG_CPU_PROGRAM_MAP(main_map)
536	534	MCFG_CPU_IO_MAP(main_portmap)
537	535	MCFG_CPU_PERIODIC_INT_DRIVER(_4enlinea_state, _4enlinea_irq, 60) //TODO
538		// MCFG_CPU_PERIODIC_INT_DRIVER(_4enlinea_state, irq0_line_hold, 4*35)
	536	// MCFG_CPU_PERIODIC_INT_DRIVER(_4enlinea_state, irq0_line_hold, 4*35)
539	537
540	538	MCFG_CPU_ADD("audiocpu", Z80, SND_CPU_CLOCK)
541	539	MCFG_CPU_PROGRAM_MAP(audio_map)
r29404	r29405
550	548	CRTC_CLOCK is 8MHz, entering for pin 1 of UM487F. This clock is used
551	549	only for UM6845R embedded mode. The frequency divisor is unknown.
552	550
553		CRTC_CLOCK / 4.0 = 66.961296 Hz.
554		CRTC_CLOCK / 4.5 = 59.521093 Hz.
	551	CRTC_CLOCK / 4.0 = 66.961296 Hz.
	552	CRTC_CLOCK / 4.5 = 59.521093 Hz.
555	553	CRTC_CLOCK / 5.0 = 53.569037 Hz.
556	554	*/
557	555

trunk/src/mame/drivers/mcr3.c
r29404	r29405
1636	1636	ROM_END
1637	1637
1638	1638
1639		/* Spy Hunter labels look like this
	1639	/* Spy Hunter labels look like this
1640	1640	SPY-HUNTER
1641	1641	C.P.U.
1642	1642	PG3
1643		2/9/84
	1643	2/9/84
1644	1644	*/
1645	1645
1646	1646	ROM_START( spyhunt )

trunk/src/mame/drivers/polepos.c
r29404	r29405
856	856	MCFG_NAMCO_51XX_INPUT_2_CB(IOPORT("DSWB"))
857	857	MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("DSWB_HI"))
858	858	MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(polepos_state,out_0))
859		MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(polepos_state,out_1))
	859	MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(polepos_state,out_1))
860	860
861	861	MCFG_NAMCO_52XX_ADD("52xx", MASTER_CLOCK/8/2) /* 1.536 MHz */
862	862	MCFG_NAMCO_52XX_DISCRETE("discrete")
863	863	MCFG_NAMCO_52XX_BASENODE(NODE_04)
864	864	MCFG_NAMCO_52XX_ROMREAD_CB(READ8(polepos_state,namco_52xx_rom_r))
865	865	MCFG_NAMCO_52XX_SI_CB(READ8(polepos_state,namco_52xx_si_r))
866
	866
867	867	MCFG_NAMCO_53XX_ADD("53xx", MASTER_CLOCK/8/2) /* 1.536 MHz */
868	868	MCFG_NAMCO_53XX_K_CB(READ8(polepos_state,namco_53xx_k_r))
869	869	MCFG_NAMCO_53XX_INPUT_0_CB(READ8(polepos_state,steering_changed_r))
870	870	MCFG_NAMCO_53XX_INPUT_1_CB(READ8(polepos_state,steering_delta_r))
871	871	MCFG_NAMCO_53XX_INPUT_2_CB(IOPORT("DSWA"))
872	872	MCFG_NAMCO_53XX_INPUT_3_CB(IOPORT("DSWA_HI"))
873
	873
874	874	MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/8/2) /* 1.536 MHz */
875	875	MCFG_NAMCO_54XX_DISCRETE("discrete")
876	876	MCFG_NAMCO_54XX_BASENODE(NODE_01)
r29404	r29405
946	946	they probably simulate some of the logic */
947	947	MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/8/2) /* 1.536 MHz */
948	948	MCFG_NAMCO_51XX_INPUT_1_CB(IOPORT("IN0H"))
949
	949
950	950	MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/8/64)
951	951	MCFG_NAMCO_06XX_MAINCPU("maincpu")
952	952	MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read))

trunk/src/mame/drivers/pinkiri8.c
r29404	r29405
169	169	attr = m_janshi_back_vram[count + 2] ^ 0xf0;
170	170	col = (attr >> 4) \| 0x10;
171	171
172		gfx->transpen(bitmap,cliprect, tile, col, 0, 0, x * 16, y * 8, 0);
	172	gfx->transpen(bitmap,cliprect, tile, col, 0, 0, x * 16, y * 8, 0);
173	173
174	174	count += 4;
175	175	}

trunk/src/mame/drivers/vaportra.c
r29404	r29405
256	256	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
257	257	MCFG_SCREEN_UPDATE_DRIVER(vaportra_state, screen_update_vaportra)
258	258	MCFG_SCREEN_PALETTE("palette")
259
	259
260	260	MCFG_GFXDECODE_ADD("gfxdecode", "palette", vaportra)
261	261	MCFG_PALETTE_ADD("palette", 1280)
262	262

trunk/src/mame/drivers/chanbara.c
r29404	r29405
84	84	required_device<cpu_device> m_maincpu;
85	85	required_device<gfxdecode_device> m_gfxdecode;
86	86	required_device<palette_device> m_palette;
87
	87
88	88	DECLARE_WRITE8_MEMBER(chanbara_videoram_w);
89	89	DECLARE_WRITE8_MEMBER(chanbara_colorram_w);
90	90	DECLARE_WRITE8_MEMBER(chanbara_videoram2_w);

trunk/src/mame/drivers/qdrmfgp.c
r29404	r29405
625	625	MCFG_K056832_ADD("k056832", qdrmfgp_k056832_intf)
626	626	MCFG_K056832_GFXDECODE("gfxdecode")
627	627	MCFG_K056832_PALETTE("palette")
628
	628
629	629	MCFG_DEVICE_ADD("k053252", K053252, XTAL_32MHz/4)
630	630	MCFG_K053252_OFFSETS(40, 16)
631	631
r29404	r29405
669	669	MCFG_K056832_ADD("k056832", qdrmfgp2_k056832_intf)
670	670	MCFG_K056832_GFXDECODE("gfxdecode")
671	671	MCFG_K056832_PALETTE("palette")
672
	672
673	673	MCFG_DEVICE_ADD("k053252", K053252, XTAL_32MHz/4)
674	674	MCFG_K053252_OFFSETS(40, 16)
675	675

trunk/src/mame/drivers/wiz.c
r29404	r29405
335	335	ADDRESS_MAP_END
336	336
337	337	static ADDRESS_MAP_START( stinger_main_map, AS_PROGRAM, 8, wiz_state )
338		// AM_RANGE(0xf008, 0xf00f) AM_WRITENOP // ?
	338	// AM_RANGE(0xf008, 0xf00f) AM_WRITENOP // ?
339	339	AM_RANGE(0xf800, 0xf800) AM_READ(watchdog_reset_r)
340	340	AM_RANGE(0xf808, 0xf808) AM_WRITE(stinger_explosion_w)
341	341	AM_RANGE(0xf80a, 0xf80a) AM_WRITE(stinger_shot_w)
r29404	r29405
751	751	save_item(NAME(m_sound_nmi_mask));
752	752	save_item(NAME(m_dsc0));
753	753	save_item(NAME(m_dsc1));
754
	754
755	755	save_item(NAME(m_sprite_bank));
756	756	save_item(NAME(m_charbank));
757	757	save_item(NAME(m_palbank));

trunk/src/mame/drivers/gaelco3d.c
r29404	r29405
991	991	MCFG_QUANTUM_TIME(attotime::from_hz(6000))
992	992
993	993	MCFG_TIMER_DRIVER_ADD("adsp_timer", gaelco3d_state, adsp_autobuffer_irq)
994
	994
995	995	MCFG_DEVICE_ADD("serial", GAELCO_SERIAL, 0)
996	996	MCFG_GAELCO_SERIAL_IRQ_HANDLER(WRITELINE(gaelco3d_state, ser_irq))
997	997

trunk/src/mame/drivers/highvdeo.c
r29404	r29405
1626	1626	ROM_LOAD( "sound-magic-bomb-hmb-vers1-memory-4m.ic16", 0x00000, 0x80000, CRC(45b2b53a) SHA1(983bcc5869d84938ba278f26339dd72c17ed1d00) )
1627	1627	ROM_END
1628	1628
1629		ROM_START( record ) // do checks and expect something... pc=e8044
	1629	ROM_START( record ) // do checks and expect something... pc=e8044
1630	1630	ROM_REGION( 0x100000, "user1", 0 ) /* V30 Code */
1631	1631	ROM_LOAD16_BYTE( "record-vrc-i17-vers1-video-map.ic7", 0x00000, 0x80000, CRC(d0e59a64) SHA1(5f51448a4cdefd335e19affa4b47df7b428b0e7c) )
1632	1632	ROM_LOAD16_BYTE( "record-vrc-i17-vers1-video-map.ic8", 0x00001, 0x80000, CRC(823d1c25) SHA1(3104567b2b05708d1b5218f9f0e64bfa3d0df46b) )
r29404	r29405
1644	1644	switch(offset*2)
1645	1645	{
1646	1646	case 0:
1647		resetpulse^=0x15; // and 0x07, cmp with 0x05
	1647	resetpulse^=0x15; // and 0x07, cmp with 0x05
1648	1648	return 0 \| resetpulse;
1649		case 2: return 0x15; // unknown
	1649	case 2: return 0x15; // unknown
1650	1650	}
1651	1651
1652	1652	return 0;

trunk/src/mame/drivers/fcrash.c
r29404	r29405
1301	1301	PORT_DIPNAME( 0x40, 0x40, "2 Coins to Start, 1 to Continue" ) PORT_DIPLOCATION("SW(A):7")
1302	1302	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1303	1303	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1304		PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW(A):8" ) //sort of debug mode...
	1304	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW(A):8" ) //sort of debug mode...
1305	1305	//depnding (???) of other DSW setting get different
1306	1306	//"game" mode, autoplay, bonus round, ecc...
1307	1307	PORT_START("DSWB")
r29404	r29405
2482	2482	MCFG_SCREEN_UPDATE_DRIVER(cps_state, screen_update_fcrash)
2483	2483	MCFG_SCREEN_VBLANK_DRIVER(cps_state, screen_eof_cps1)
2484	2484	MCFG_SCREEN_PALETTE("palette")
2485
	2485
2486	2486	MCFG_GFXDECODE_ADD("gfxdecode", "palette", cps1)
2487	2487	MCFG_PALETTE_ADD("palette", 0xc00)
2488	2488	MCFG_VIDEO_START_OVERRIDE(cps_state,cps1)

trunk/src/mame/drivers/atetris.c
r29404	r29405
335	335
336	336	MCFG_PALETTE_ADD("palette", 256)
337	337	MCFG_PALETTE_FORMAT(RRRGGGBB)
338
	338
339	339	MCFG_SCREEN_ADD("screen", RASTER)
340	340	/* note: these parameters are from published specs, not derived */
341	341	/* the board uses an SOS-2 chip to generate video signals */

trunk/src/mame/drivers/model2.c
r29404	r29405
1955	1955	MCFG_TIMER_PTR((FPTR)3)
1956	1956
1957	1957	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1958
	1958
1959	1959	MCFG_S24TILE_DEVICE_ADD("tile", 0x3fff)
1960	1960	MCFG_S24TILE_DEVICE_GFXDECODE("gfxdecode")
1961	1961	MCFG_S24TILE_DEVICE_PALETTE("palette")

trunk/src/mame/drivers/bmcbowl.c
r29404	r29405
326	326	AM_RANGE(0x000000, 0x01ffff) AM_ROM
327	327
328	328	AM_RANGE(0x090000, 0x090001) AM_WRITE(bmc_RAMDAC_offset_w) AM_SHARE("colorram")
329		AM_RANGE(0x090002, 0x090003) AM_WRITE(bmc_RAMDAC_color_w)
	329	AM_RANGE(0x090002, 0x090003) AM_WRITE(bmc_RAMDAC_color_w)
330	330	AM_RANGE(0x090004, 0x090005) AM_WRITENOP//RAMDAC
331	331
332	332	AM_RANGE(0x090800, 0x090803) AM_WRITENOP
r29404	r29405
489	489	MCFG_NVRAM_ADD_1FILL("nvram")
490	490
491	491	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
492
	492
493	493	MCFG_SOUND_ADD("ymsnd", YM2413, XTAL_3_579545MHz ) // guessed chip type, clock not verified
494	494	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
495	495	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)

trunk/src/mame/drivers/popeye.c
r29404	r29405
29	29	*/
30	30
31	31	static NETLIST_START(nl_popeye_imp_changer)
32		RES(R62, 510000)
33		RES(R63, 100)
34		RES(R64, 510000)
35		RES(R65, 2100)
36		RES(R66, 330)
37		RES(R67, 51)
	32	RES(R62, 510000)
	33	RES(R63, 100)
	34	RES(R64, 510000)
	35	RES(R65, 2100)
	36	RES(R66, 330)
	37	RES(R67, 51)
38	38
39		QBJT_EB(Q8, "2SC1815")
40		QBJT_EB(Q9, "2SA1015")
	39	QBJT_EB(Q8, "2SC1815")
	40	QBJT_EB(Q9, "2SA1015")
41	41
42		NET_C(V5, R62.1, Q8.C, R66.1)
43		NET_C(R62.2, R64.1, R63.1, C7.2)
44		NET_C(R63.2, Q8.B)
45		NET_C(Q8.E, R65.1, Q9.B)
46		NET_C(R66.2, Q9.E, R67.1)
	42	NET_C(V5, R62.1, Q8.C, R66.1)
	43	NET_C(R62.2, R64.1, R63.1, C7.2)
	44	NET_C(R63.2, Q8.B)
	45	NET_C(Q8.E, R65.1, Q9.B)
	46	NET_C(R66.2, Q9.E, R67.1)
47	47
48		NET_C(GND, Q9.C, R65.2, R64.2)
	48	NET_C(GND, Q9.C, R65.2, R64.2)
49	49	NETLIST_END()
50	50
51	51	static NETLIST_START(nl_popeye)
52	52
53		/* Standard stuff */
	53	/* Standard stuff */
54	54
55		SOLVER(Solver, 48000)
56		PARAM(Solver.ACCURACY, 1e-5)
57		ANALOG_INPUT(V5, 5)
	55	SOLVER(Solver, 48000)
	56	PARAM(Solver.ACCURACY, 1e-5)
	57	ANALOG_INPUT(V5, 5)
58	58
59		/* AY 8910 internal resistors */
	59	/* AY 8910 internal resistors */
60	60
61		RES(R_AY1_1, 1000);
62		RES(R_AY1_2, 1000);
63		RES(R_AY1_3, 1000);
	61	RES(R_AY1_1, 1000);
	62	RES(R_AY1_2, 1000);
	63	RES(R_AY1_3, 1000);
64	64
65		RES(R52, 2000)
66		RES(R55, 2000)
67		RES(R58, 2000)
68		RES(R53, 2000)
69		RES(R56, 2000)
70		RES(R59, 2000)
71		RES(R51, 20000)
72		RES(R57, 30000)
73		RES(R60, 30000)
	65	RES(R52, 2000)
	66	RES(R55, 2000)
	67	RES(R58, 2000)
	68	RES(R53, 2000)
	69	RES(R56, 2000)
	70	RES(R59, 2000)
	71	RES(R51, 20000)
	72	RES(R57, 30000)
	73	RES(R60, 30000)
74	74
75		RES(R61, 120000)
	75	RES(R61, 120000)
76	76
77		RES(ROUT, 5000)
	77	RES(ROUT, 5000)
78	78
79		CAP(C4, 0.047e-6)
80		CAP(C5, 330e-12)
81		CAP(C6, 330e-12)
82		CAP(C7, 3.3e-6)
83		CAP(C40, 680e-12)
	79	CAP(C4, 0.047e-6)
	80	CAP(C5, 330e-12)
	81	CAP(C6, 330e-12)
	82	CAP(C7, 3.3e-6)
	83	CAP(C40, 680e-12)
84	84
85		NET_C(V5, R_AY1_1.1, R_AY1_2.1, R_AY1_3.1)
	85	NET_C(V5, R_AY1_1.1, R_AY1_2.1, R_AY1_3.1)
86	86
87		NET_C(R_AY1_1.2, R52.1, R53.1)
88		NET_C(R_AY1_2.2, R55.1, R56.1)
89		NET_C(R_AY1_3.2, R58.1, R59.1)
	87	NET_C(R_AY1_1.2, R52.1, R53.1)
	88	NET_C(R_AY1_2.2, R55.1, R56.1)
	89	NET_C(R_AY1_3.2, R58.1, R59.1)
90	90
91		NET_C(R53.2, R51.1, C4.1)
92		NET_C(R56.2, R57.1, C5.1)
93		NET_C(R59.2, R60.1, C6.1)
	91	NET_C(R53.2, R51.1, C4.1)
	92	NET_C(R56.2, R57.1, C5.1)
	93	NET_C(R59.2, R60.1, C6.1)
94	94
95		NET_C(R51.2, R57.2, R60.2, R61.1, C40.1, C7.1)
	95	NET_C(R51.2, R57.2, R60.2, R61.1, C40.1, C7.1)
96	96
97		NET_C(GND, R52.2, R55.2, R58.2, C4.2, C5.2, C6.2, R61.2, C40.2)
	97	NET_C(GND, R52.2, R55.2, R58.2, C4.2, C5.2, C6.2, R61.2, C40.2)
98	98
99		INCLUDE(nl_popeye_imp_changer)
	99	INCLUDE(nl_popeye_imp_changer)
100	100
101		/* output resistor (actually located in TV */
	101	/* output resistor (actually located in TV */
102	102
103		NET_C(R67.2, ROUT.1)
	103	NET_C(R67.2, ROUT.1)
104	104
105		NET_C(GND, ROUT.2)
	105	NET_C(GND, ROUT.2)
106	106
107	107	NETLIST_END()
108	108
r29404	r29405
112	112	{
113	113	m_field ^= 1;
114	114	/* NMIs are enabled by the I register?? How can that be? */
115		if (device.state().state_int(Z80_I) & 1) /* skyskipr: 0/1, popeye: 2/3 but also 0/1 */
	115	if (device.state().state_int(Z80_I) & 1) /* skyskipr: 0/1, popeye: 2/3 but also 0/1 */
116	116	device.execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
117	117	}
118	118
r29404	r29405
458	458	/* Does Sky Skipper have the same filtering? */
459	459	static const ay8910_interface ay8910_nl_config =
460	460	{
461		AY8910_RESISTOR_OUTPUT,
462		AY8910_DEFAULT_LOADS,
463		DEVCB_INPUT_PORT("DSW0"),
464		DEVCB_NULL,
465		DEVCB_NULL,
466		DEVCB_DRIVER_MEMBER(popeye_state,popeye_portB_w)
	461	AY8910_RESISTOR_OUTPUT,
	462	AY8910_DEFAULT_LOADS,
	463	DEVCB_INPUT_PORT("DSW0"),
	464	DEVCB_NULL,
	465	DEVCB_NULL,
	466	DEVCB_DRIVER_MEMBER(popeye_state,popeye_portB_w)
467	467	};
468	468
469	469	static MACHINE_CONFIG_START( skyskipr, popeye_state )
r29404	r29405
501	501
502	502	MCFG_SOUND_MODIFY("aysnd")
503	503	MCFG_SOUND_ROUTES_RESET()
504		MCFG_SOUND_CONFIG(ay8910_nl_config)
505		MCFG_SOUND_ROUTE_EX(0, "snd_nl", 1.0, 0)
506		MCFG_SOUND_ROUTE_EX(1, "snd_nl", 1.0, 1)
507		MCFG_SOUND_ROUTE_EX(2, "snd_nl", 1.0, 2)
	504	MCFG_SOUND_CONFIG(ay8910_nl_config)
	505	MCFG_SOUND_ROUTE_EX(0, "snd_nl", 1.0, 0)
	506	MCFG_SOUND_ROUTE_EX(1, "snd_nl", 1.0, 1)
	507	MCFG_SOUND_ROUTE_EX(2, "snd_nl", 1.0, 2)
508	508
509		/* NETLIST configuration using internal AY8910 resistor values */
	509	/* NETLIST configuration using internal AY8910 resistor values */
510	510
511		MCFG_SOUND_ADD("snd_nl", NETLIST_SOUND, 48000)
512		MCFG_NETLIST_SETUP(nl_popeye)
513		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	511	MCFG_SOUND_ADD("snd_nl", NETLIST_SOUND, 48000)
	512	MCFG_NETLIST_SETUP(nl_popeye)
	513	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
514	514
515		MCFG_NETLIST_STREAM_INPUT("snd_nl", 0, "R_AY1_1.R")
516		MCFG_NETLIST_STREAM_INPUT("snd_nl", 1, "R_AY1_2.R")
517		MCFG_NETLIST_STREAM_INPUT("snd_nl", 2, "R_AY1_3.R")
	515	MCFG_NETLIST_STREAM_INPUT("snd_nl", 0, "R_AY1_1.R")
	516	MCFG_NETLIST_STREAM_INPUT("snd_nl", 1, "R_AY1_2.R")
	517	MCFG_NETLIST_STREAM_INPUT("snd_nl", 2, "R_AY1_3.R")
518	518
519		MCFG_NETLIST_STREAM_OUTPUT("snd_nl", 0, "ROUT.1")
520		MCFG_NETLIST_ANALOG_MULT_OFFSET(30000.0, -65000.0)
	519	MCFG_NETLIST_STREAM_OUTPUT("snd_nl", 0, "ROUT.1")
	520	MCFG_NETLIST_ANALOG_MULT_OFFSET(30000.0, -65000.0)
521	521
522	522	MCFG_VIDEO_START_OVERRIDE(popeye_state,popeye)
523	523	MACHINE_CONFIG_END

trunk/src/mame/drivers/igs017.c
r29404	r29405
79	79	optional_device<igs022_device> m_igs022; // Mj Shuang Long Qiang Zhu 2
80	80	required_device<gfxdecode_device> m_gfxdecode;
81	81	required_device<screen_device> m_screen;
82		required_device<palette_device> m_palette;
	82	required_device<palette_device> m_palette;
83	83	void igs025_to_igs022_callback( void );
84	84
85	85	int m_toggle;

trunk/src/mame/drivers/hyperspt.c
r29404	r29405
345	345	MCFG_CPU_PROGRAM_MAP(roadf_map)
346	346	MCFG_GFXDECODE_MODIFY("gfxdecode", roadf)
347	347	MCFG_VIDEO_START_OVERRIDE(hyperspt_state,roadf)
348
	348
349	349	MCFG_CPU_MODIFY("audiocpu")
350	350	MCFG_CPU_PROGRAM_MAP(roadf_sound_map)
351	351	MCFG_DEVICE_REMOVE("vlm")

trunk/src/mame/drivers/namcos12.c
r29404	r29405
1580	1580	MCFG_LINE_DISPATCH_ADD("clk_dispatch", 2)
1581	1581	MCFG_LINE_DISPATCH_FWD_CB(0, 2, DEVWRITELINE(":rtc", rtc4543_device, clk_w)) MCFG_DEVCB_INVERT
1582	1582	MCFG_LINE_DISPATCH_FWD_CB(1, 2, DEVWRITELINE(":namco_settings", namco_settings_device, clk_w))
1583
	1583
1584	1584	MCFG_DEVICE_MODIFY("sub:sci1")
1585	1585	MCFG_H8_SCI_TX_CALLBACK(DEVWRITELINE(":namco_settings", namco_settings_device, data_w))
1586	1586	MCFG_H8_SCI_CLK_CALLBACK(DEVWRITELINE(":clk_dispatch", devcb2_line_dispatch_device<2>, in_w))
1587
	1587
1588	1588	MCFG_AT28C16_ADD("at28c16", NULL)
1589	1589
1590	1590	/* video hardware */
r29404	r29405
1964	1964
1965	1965	ROM_REGION32_LE( 0x00800000, "user2", 0 ) /* main data */
1966	1966	ROM_LOAD16_BYTE( "kdt1rom0l.ic12", 0x000000, 0x400000, BAD_DUMP CRC(8e2d5d9e) SHA1(6f703e27a19740af4094004b783b3cc2974c3de0) ) // These probably should be 64MBIT
1967		ROM_LOAD16_BYTE( "kdt1rom0u.ic11", 0x000001, 0x400000, BAD_DUMP CRC(49ec5dbd) SHA1(336db6d3e361938850a9234b6b64070dbdc36d45) ) //
	1967	ROM_LOAD16_BYTE( "kdt1rom0u.ic11", 0x000001, 0x400000, BAD_DUMP CRC(49ec5dbd) SHA1(336db6d3e361938850a9234b6b64070dbdc36d45) ) //
1968	1968
1969	1969	ROM_REGION( 0x0080000, "sub", 0 ) /* sound prg */
1970	1970	ROM_LOAD16_WORD_SWAP( "ktd1vera.11s", 0x000000, 0x080000, CRC(c2ff1971) SHA1(32ee2afe08e92049d8139c9324a0ea1a3b7ee5a1) )

trunk/src/mame/drivers/raiden2.c
r29404	r29405
797	797	#define ZEROTEAM_MASK_Y (0x1ff)
798	798
799	799
800
	800
801	801	gfx->transpen(
802	802	bitmap,
803	803	cliprect,
r29404	r29405
806	806	yflip,xflip,
807	807	(sx+xstepxtiles)&ZEROTEAM_MASK_X,(sy+ystepytiles)&ZEROTEAM_MASK_Y,15);
808	808
809
	809
810	810	gfx->transpen(
811	811	bitmap,
812	812	cliprect,
r29404	r29405
815	815	yflip,xflip,
816	816	((sx+xstepxtiles)&ZEROTEAM_MASK_X)-0x200,(sy+ystepytiles)&ZEROTEAM_MASK_Y,15);
817	817
818
	818
819	819	gfx->transpen(
820	820	bitmap,
821	821	cliprect,
r29404	r29405
824	824	yflip,xflip,
825	825	(sx+xstepxtiles)&ZEROTEAM_MASK_X,((sy+ystepytiles)&ZEROTEAM_MASK_Y)-0x200,15);
826	826
827
	827
828	828	gfx->transpen(
829	829	bitmap,
830	830	cliprect,
r29404	r29405
1858	1858	GFXDECODE_ENTRY( "gfx3", 0x00000, raiden2_spritelayout, 0x000, 128 )
1859	1859	GFXDECODE_END
1860	1860
1861
	1861
1862	1862	/* MACHINE DRIVERS */
1863	1863
1864	1864	static MACHINE_CONFIG_START( raiden2, raiden2_state )
r29404	r29405
1881	1881	MCFG_SCREEN_VISIBLE_AREA(08, 408-1, 0, 30*8-1)
1882	1882	MCFG_SCREEN_UPDATE_DRIVER(raiden2_state, screen_update_raiden2)
1883	1883	MCFG_SCREEN_PALETTE("palette")
1884
	1884
1885	1885	MCFG_GFXDECODE_ADD("gfxdecode", "palette", raiden2)
1886	1886	MCFG_PALETTE_ADD("palette", 2048)
1887	1887	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
r29404	r29405
1939	1939	MCFG_SCREEN_RAW_PARAMS(XTAL_32MHz/4,546,0,408,264,0,328) /* hand-tuned to match ~55.47 */
1940	1940	MCFG_SCREEN_UPDATE_DRIVER(raiden2_state, screen_update_raiden2)
1941	1941	MCFG_SCREEN_PALETTE("palette")
1942
	1942
1943	1943	MCFG_GFXDECODE_ADD("gfxdecode", "palette", raiden2)
1944	1944	MCFG_PALETTE_ADD("palette", 2048)
1945	1945	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)

trunk/src/mame/drivers/scramble.c
r29404	r29405
2142	2142
2143	2143	ROM_START( hunchbks2 )
2144	2144	ROM_REGION( 0x8000, "maincpu", 0 )
2145		ROM_LOAD( "hb01.bin", 0x0000, 0x0800, CRC(fec3466a) SHA1(d8ec3b432f7037e99bf1ac1ba7911a34eff6869d) )
	2145	ROM_LOAD( "hb01.bin", 0x0000, 0x0800, CRC(fec3466a) SHA1(d8ec3b432f7037e99bf1ac1ba7911a34eff6869d) )
2146	2146	ROM_LOAD( "2e_hb02.bin", 0x0800, 0x0800, CRC(07de4229) SHA1(9f333509ae3d6c579f6d96caa172a0abe9eefb30) )
2147	2147	ROM_LOAD( "2f_hb03.bin", 0x2000, 0x0800, CRC(b75a0dfc) SHA1(c60c833f28c6de027d46f5a2a54ad5646ec58453) )
2148	2148	ROM_LOAD( "hb04.bin", 0x2800, 0x0800, CRC(731e349b) SHA1(cfa1ac322cdfe1d4d112b0a4dd85d3552a6e33d0) )

trunk/src/mame/drivers/taitojc.c
r29404	r29405
1269	1269	MCFG_TC0640FIO_READ_2_CB(IOPORT("START"))
1270	1270	MCFG_TC0640FIO_READ_3_CB(IOPORT("UNUSED"))
1271	1271	MCFG_TC0640FIO_READ_7_CB(IOPORT("BUTTONS"))
1272
	1272
1273	1273	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1274
	1274
1275	1275	/* video hardware */
1276	1276	MCFG_SCREEN_ADD("screen", RASTER)
1277	1277	MCFG_SCREEN_RAW_PARAMS(PIXEL_CLOCK, HTOTAL, HBEND, HBSTART, VTOTAL, VBEND, VBSTART)

trunk/src/mame/drivers/ddealer.c
r29404	r29405
225	225	UINT16 tile = (src[count] & 0x0fff);
226	226	UINT16 colr = (src[count] & 0xf000) >> 12;
227	227	count++;
228		gfx->transpen(bitmap,cliprect, tile, colr, 0, flipy, (x * 16) - sx, (y * 16) - sy, 15);
	228	gfx->transpen(bitmap,cliprect, tile, colr, 0, flipy, (x * 16) - sx, (y * 16) - sy, 15);
229	229	}
230	230	}
231	231	count = 0;
r29404	r29405
238	238	UINT16 tile = (src[count] & 0x0fff);
239	239	UINT16 colr = (src[count] & 0xf000) >> 12;
240	240	count++;
241		gfx->transpen(bitmap,cliprect, tile, colr, 0, flipy, (x * 16) - sx, (y * 16) - sy, 15);
	241	gfx->transpen(bitmap,cliprect, tile, colr, 0, flipy, (x * 16) - sx, (y * 16) - sy, 15);
242	242	}
243	243	}
244	244	}
r29404	r29405
257	257	UINT16 tile = (src[count] & 0x0fff);
258	258	UINT16 colr = (src[count] & 0xf000) >> 12;
259	259	count++;
260		gfx->transpen(bitmap,cliprect, tile, colr, flipy, flipy, (x * 16) + sx, (y * 16) + sy, 15);
	260	gfx->transpen(bitmap,cliprect, tile, colr, flipy, flipy, (x * 16) + sx, (y * 16) + sy, 15);
261	261	}
262	262	}
263	263	count = 0;
r29404	r29405
270	270	UINT16 tile = (src[count] & 0x0fff);
271	271	UINT16 colr = (src[count] & 0xf000) >> 12;
272	272	count++;
273		gfx->transpen(bitmap,cliprect, tile, colr, flipy, flipy, (x * 16) + sx, (y * 16) + sy, 15);
	273	gfx->transpen(bitmap,cliprect, tile, colr, flipy, flipy, (x * 16) + sx, (y * 16) + sy, 15);
274	274	}
275	275	}
276	276	}

trunk/src/mame/drivers/photon.c
r29404	r29405
216	216	MCFG_SCREEN_VISIBLE_AREA(0, 256+32-1, 0, 192+32-1)
217	217	MCFG_SCREEN_UPDATE_DRIVER(photon_state, screen_update_photon)
218	218	MCFG_SCREEN_PALETTE("palette")
219
	219
220	220	MCFG_PALETTE_ADD("palette", 16)
221	221	MCFG_PALETTE_INIT_OWNER(pk8000_base_state, pk8000)
222	222

trunk/src/mame/drivers/spy.c
r29404	r29405
488	488
489	489	m_paletteram.resize(0x800);
490	490	m_palette->basemem().set(m_paletteram, ENDIANNESS_BIG, 2);
491
	491
492	492	memset(m_pmcram, 0, sizeof(m_pmcram));
493	493
494	494	save_item(NAME(m_paletteram));

trunk/src/mame/drivers/itgamble.c
r29404	r29405
65	65	itgamble_state(const machine_config &mconfig, device_type type, const char *tag)
66	66	: driver_device(mconfig, type, tag),
67	67	m_maincpu(*this, "maincpu"),
68		m_palette(*this, "palette")
	68	m_palette(*this, "palette")
69	69	{ }
70	70
71	71	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

trunk/src/mame/drivers/pengadvb.c
r29404	r29405
39	39	{ }
40	40
41	41	required_device<cpu_device> m_maincpu;
42
	42
43	43	address_map_bank_device *m_page[4];
44	44	memory_bank *m_bank[4];
45	45	UINT8 m_primary_slot_reg;
r29404	r29405
48	48	DECLARE_READ8_MEMBER(mem_r);
49	49	DECLARE_WRITE8_MEMBER(mem_w);
50	50	DECLARE_WRITE8_MEMBER(megarom_bank_w);
51
	51
52	52	DECLARE_WRITE8_MEMBER(pengadvb_psg_port_b_w);
53	53	DECLARE_READ8_MEMBER(pengadvb_ppi_port_a_r);
54	54	DECLARE_WRITE8_MEMBER(pengadvb_ppi_port_a_w);
r29404	r29405
91	91	static ADDRESS_MAP_START( bank_mem, AS_PROGRAM, 8, pengadvb_state )
92	92	// slot 0, MSX BIOS
93	93	AM_RANGE(0x00000, 0x07fff) AM_ROM AM_REGION("maincpu", 0)
94
	94
95	95	// slot 1, MegaROM
96	96	AM_RANGE(0x14000, 0x15fff) AM_ROMBANK("bank0")
97	97	AM_RANGE(0x16000, 0x17fff) AM_ROMBANK("bank1")
r29404	r29405
184	184	{
185	185	case 0x0:
186	186	return ioport("IN1")->read();
187
	187
188	188	default:
189	189	break;
190		}
	190	}
191	191
192	192	return 0xff;
193	193	}
r29404	r29405
327	327	{
328	328	pengadvb_decrypt("maincpu");
329	329	pengadvb_decrypt("game");
330
	330
331	331	// init banks
332	332	static const char * const pagenames[] = { "page0", "page1", "page2", "page3" };
333	333	static const char * const banknames[] = { "bank0", "bank1", "bank2", "bank3" };

trunk/src/mame/drivers/ikki.c
r29404	r29405
254	254	MCFG_SCREEN_REFRESH_RATE(60)
255	255	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
256	256	MCFG_SCREEN_SIZE(328, 328+3*8)
257		MCFG_SCREEN_VISIBLE_AREA(18, 318-1, 28, 308-1)
	257	MCFG_SCREEN_VISIBLE_AREA(18, 318-1, 28, 308-1)
258	258	MCFG_SCREEN_UPDATE_DRIVER(ikki_state, screen_update_ikki)
259	259	MCFG_SCREEN_PALETTE("palette")
260	260

trunk/src/mame/drivers/megaphx.c
r29404	r29405
1		/*
	1	/*
2	2	Dinamic / Inder arcade hardware
3	3
4	4	Mega Phoenix
5
	5
6	6	also known to exist on this hardware:
7	7	Hammer Boy
8	8	Nonamed 2 (ever finished? only code seen has 1991 date and is vastly incomplete) (versions exist for Amstrad CPC, MSX and Spectrum)
r29404	r29405
22	22	I/O:
23	23	- port_c_r / port_c_w should go through the 8255 but I don't see how to hook them up that way? various bits of the writes are lost?
24	24
25
	25
26	26	--
27	27
28	28
r29404	r29405
33	33	TS68000CP8
34	34	TMS34010FNL-40
35	35	TMP82C55AP-2
36
	36
37	37	Bt478KPJ35 Palette / RAMDAC
38	38
39	39	Actel A1010A-PL68C (custom blitter maybe?)
r29404	r29405
45	45	ST Z8430AB1
46	46
47	47	custom INDER badged chip 40 pin? (probably just a z80 - it's in the sound section)
48		MODELO: MEGA PHOENIX
49		KIT NO. 1.034
50		FECHA FABRICACION 08.10.91
51		LA MANIPULCION DE LA ETIQUETA O DE LA PLACA ANULA SU SARANTIA
52		(this sticker is also present on the other PCB)
	48	MODELO: MEGA PHOENIX
	49	KIT NO. 1.034
	50	FECHA FABRICACION 08.10.91
	51	LA MANIPULCION DE LA ETIQUETA O DE LA PLACA ANULA SU SARANTIA
	52	(this sticker is also present on the other PCB)
53	53
54	54
55	55	*/
r29404	r29405
77	77	m_indersb(*this, "inder_sb"),
78	78	m_indervid(*this, "inder_vid")
79	79
80		{
81
	80	{
82	81	}
83	82
84	83	required_device<cpu_device> m_maincpu;
r29404	r29405
126	125	AM_RANGE(0x060004, 0x060005) AM_READ8( port_c_r, 0x00ff )
127	126	AM_RANGE(0x060006, 0x060007) AM_WRITE8( port_c_w, 0x00ff )
128	127	AM_RANGE(0x060000, 0x060003) AM_DEVREADWRITE8("ppi8255_0", i8255_device, read, write, 0x00ff)
129
	128
130	129	AM_RANGE(0x800000, 0x83ffff) AM_ROM AM_REGION("roms01", 0x00000) // code + bg gfx are in here
131	130	AM_RANGE(0x840000, 0x87ffff) AM_ROM AM_REGION("roms23", 0x00000) // bg gfx are in here
132	131	AM_RANGE(0x880000, 0x8bffff) AM_ROM AM_REGION("roms45", 0x00000) // bg gfx + title screen in here
r29404	r29405
210	209	PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Demo_Sounds ) )
211	210	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
212	211	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
213		PORT_SERVICE( 0x0002, IP_ACTIVE_HIGH )
	212	PORT_SERVICE( 0x0002, IP_ACTIVE_HIGH )
214	213	PORT_DIPNAME( 0x001c, 0x0010, "Difficulty?" ) // in hammer boy at least..
215	214	PORT_DIPSETTING( 0x0000, "0" )
216	215	PORT_DIPSETTING( 0x0004, "1" )
r29404	r29405
240	239
241	240	READ8_MEMBER(megaphx_state::port_c_r)
242	241	{
243
244	242	//printf("read port c - write value was %02x\n", port_c_value);
245	243
246		// int pc = machine().device("maincpu")->safe_pc();
	244	// int pc = machine().device("maincpu")->safe_pc();
247	245	UINT8 ret = 0;
248	246
249		// printf("(%06x) port_c_r (thru 8255)\n", pc);
250
	247	// printf("(%06x) port_c_r (thru 8255)\n", pc);
	248
251	249	if (m_pic_clock == 1) ret \|= 0x08;
252	250	if (m_pic_readbit == 1) ret \|= 0x02;
253		// return ioport("SYS")->read();
	251	// return ioport("SYS")->read();
254	252	return ret;
255	253	}
256	254
257	255
258	256	WRITE8_MEMBER(megaphx_state::port_c_w)
259	257	{
260
261
262
263		// int pc = machine().device("maincpu")->safe_pc();
	258	// int pc = machine().device("maincpu")->safe_pc();
264	259	port_c_value = (data & 0x0f);
265	260
266	261	if (port_c_value == 0x9)
267	262	{
268		// printf("Assert PIC reset line\n");
	263	// printf("Assert PIC reset line\n");
269	264	m_pic_is_reset = 1;
270	265	}
271	266	else if (port_c_value == 0x8)
272	267	{
273		// printf("Clear PIC reset line\n");
	268	// printf("Clear PIC reset line\n");
274	269	m_pic_is_reset = 0;
275
	270
276	271	m_pic_shift_pos = 0;
277	272	m_pic_data = 0;
278	273	m_pic_data_bit = 0;
r29404	r29405
282	277	}
283	278	else if (port_c_value == 0xd)
284	279	{
285		// printf("Set PIC data line\n");
	280	// printf("Set PIC data line\n");
286	281	m_pic_data_bit = 1;
287	282	}
288	283	else if (port_c_value == 0xc)
289	284	{
290		// printf("Clear PIC data line\n");
	285	// printf("Clear PIC data line\n");
291	286	m_pic_data_bit = 0;
292	287	}
293	288	else if (port_c_value == 0xf)
294	289	{
295	290	if (m_pic_clock == 0)
296	291	{
297		// printf("Set PIC clock line \| pos %d \| bit %d\n", m_pic_shift_pos, m_pic_data_bit);
298
	292	// printf("Set PIC clock line \| pos %d \| bit %d\n", m_pic_shift_pos, m_pic_data_bit);
299	293
300	294
301	295
302	296
	297
303	298	m_pic_clock = 1;
304
	299
305	300	}
306	301	}
307	302	else if (port_c_value == 0xe)
308	303	{
309
310	304	if (m_pic_clock == 1)
311	305	{
312	306	m_pic_data \|= m_pic_data_bit << m_pic_shift_pos;
r29404	r29405
339	333	m_pic_shift_pos++;
340	334
341	335
342		// printf("Clear PIC clock line\n");
	336	// printf("Clear PIC clock line\n");
343	337	m_pic_clock = 0;
344	338	}
345	339	}
346	340	else
347	341	{
348		// printf("Unknown write to PIC %02x (PC %06x)\n", port_c_value, pc);
	342	// printf("Unknown write to PIC %02x (PC %06x)\n", port_c_value, pc);
349	343	}
350	344
351	345

trunk/src/mame/drivers/mpoker.c
r29404	r29405
205	205	UINT32 screen_update_mpoker(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
206	206	required_device<cpu_device> m_maincpu;
207	207	required_device<gfxdecode_device> m_gfxdecode;
208		required_device<palette_device> m_palette;
	208	required_device<palette_device> m_palette;
209	209	};
210	210
211	211

trunk/src/mame/drivers/beathead.c
r29404	r29405
377	377	MCFG_SCREEN_SIZE(42*8, 262)
378	378	MCFG_SCREEN_VISIBLE_AREA(08, 428-1, 08, 308-1)
379	379	MCFG_SCREEN_PALETTE("palette")
380
	380
381	381	MCFG_PALETTE_ADD("palette", 32768)
382	382
383	383	/* sound hardware */

trunk/src/mame/drivers/lastbank.c
r29404	r29405
480	480
481	481	MCFG_GFXDECODE_ADD("gfxdecode", "palette", lastbank )
482	482	MCFG_PALETTE_ADD("palette", 0x100)
483
	483
484	484	MCFG_DEVICE_ADD("tc0091lvc", TC0091LVC, 0)
485	485	MCFG_TC0091LVC_GFXDECODE("gfxdecode")
486	486	MCFG_TC0091LVC_PALETTE("palette")

trunk/src/mame/drivers/pcxt.c
r29404	r29405
137	137	public:
138	138	// construction/destruction
139	139	isa8_cga_filetto_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
140
	140
141	141	virtual const rom_entry *device_rom_region() const;
142	142	};
143	143
r29404	r29405
149	149
150	150	isa8_cga_filetto_device::isa8_cga_filetto_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
151	151	isa8_cga_device( mconfig, ISA8_CGA_FILETTO, "ISA8_CGA_FILETTO", tag, owner, clock, "filetto_cga", __FILE__)
152		{
	152	{
153	153	}
154	154
155	155	ROM_START( filetto_cga )
r29404	r29405
169	169	public:
170	170	// construction/destruction
171	171	isa8_cga_tetriskr_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
172
	172
173	173	virtual UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
174	174	virtual void device_start();
175	175	virtual const rom_entry *device_rom_region() const;
176
	176
177	177	DECLARE_READ8_MEMBER(bg_bank_r);
178	178	DECLARE_WRITE8_MEMBER(bg_bank_w);
179	179	private:
r29404	r29405
190	190
191	191	isa8_cga_tetriskr_device::isa8_cga_tetriskr_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
192	192	isa8_cga_superimpose_device( mconfig, ISA8_CGA_TETRISKR, "ISA8_CGA_TETRISKR", tag, owner, clock, "tetriskr_cga", __FILE__)
193		{
	193	{
194	194	}
195	195
196	196
r29404	r29405
788	788
789	789	static MACHINE_CONFIG_START( tetriskr, pcxt_state )
790	790	MCFG_FRAGMENT_ADD( pcxt )
791
	791
792	792	MCFG_CPU_MODIFY("maincpu")
793	793	MCFG_CPU_IO_MAP(tetriskr_io)
794	794

trunk/src/mame/drivers/toaplan2.c
r29404	r29405
3275	3275	MCFG_DEVICE_ADD_VDP0
3276	3276	MCFG_GP9001_VDP_GFXDECODE("gfxdecode")
3277	3277	MCFG_GP9001_VDP_PALETTE("palette")
3278
	3278
3279	3279	MCFG_DEVICE_ADD_VDP1
3280	3280	MCFG_GP9001_VDP_GFXDECODE("gfxdecode")
3281	3281	MCFG_GP9001_VDP_PALETTE("palette")
r29404	r29405
3713	3713	MCFG_DEVICE_ADD_VDP0
3714	3714	MCFG_GP9001_VDP_GFXDECODE("gfxdecode")
3715	3715	MCFG_GP9001_VDP_PALETTE("palette")
3716
	3716
3717	3717	MCFG_DEVICE_ADD_VDP1
3718	3718	MCFG_GP9001_VDP_GFXDECODE("gfxdecode")
3719	3719	MCFG_GP9001_VDP_PALETTE("palette")
r29404	r29405
4598	4598
4599	4599	ROM_REGION( 0x1000, "plds", 0 ) /* Logic for mixing output of both GP9001 GFX controllers */
4600	4600	ROM_LOAD( "tp030_u19_gal16v8b-15.bin", 0x0000, 0x117, CRC(f71669e8) SHA1(ec1fbe04605fee864af4b01f001af227938c9f21) )
4601		// ROM_LOAD( "tp030_u19_gal16v8b-15.jed", 0x0000, 0x991, CRC(31be54a2) SHA1(06278942a9a2ea858c0352b2ef5a65bf329b7b82) )
	4601	// ROM_LOAD( "tp030_u19_gal16v8b-15.jed", 0x0000, 0x991, CRC(31be54a2) SHA1(06278942a9a2ea858c0352b2ef5a65bf329b7b82) )
4602	4602	ROM_END
4603	4603
4604	4604

trunk/src/mame/drivers/subsino.c
r29404	r29405
3853	3853	DRIVER_INIT_MEMBER(subsino_state,tesorone230)
3854	3854	{
3855	3855	#if 1
3856		UINT8 *rom = memregion( "maincpu" )->base(); //check this patch!!!!
	3856	UINT8 *rom = memregion( "maincpu" )->base(); //check this patch!!!!
3857	3857	rom[0x10a8] = 0x18; //patch protection check ("ERROR 08073"):
3858	3858	rom[0x10a9] = 0x11;
3859	3859	rom[0x8ba] = 0x18; //patch "winning protection" check

trunk/src/mame/drivers/wecleman.c
r29404	r29405
1157	1157	MCFG_K051316_ADD("k051316_1", hotchase_k051316_intf_0)
1158	1158	MCFG_K051316_GFXDECODE("gfxdecode")
1159	1159	MCFG_K051316_PALETTE("palette")
1160
	1160
1161	1161	MCFG_K051316_ADD("k051316_2", hotchase_k051316_intf_1)
1162	1162	MCFG_K051316_GFXDECODE("gfxdecode")
1163	1163	MCFG_K051316_PALETTE("palette")

trunk/src/mame/drivers/cmmb.c
r29404	r29405
338	338	MCFG_SCREEN_PALETTE("palette")
339	339
340	340	MCFG_GFXDECODE_ADD("gfxdecode", "palette", cmmb)
341
	341
342	342	MCFG_PALETTE_ADD("palette", 512)
343	343	MCFG_PALETTE_FORMAT(RRRGGGBB)
344	344

trunk/src/mame/drivers/flyball.c
r29404	r29405
57	57	required_device<gfxdecode_device> m_gfxdecode;
58	58	required_device<screen_device> m_screen;
59	59	required_device<palette_device> m_palette;
60
	60
61	61	DECLARE_READ8_MEMBER(flyball_input_r);
62	62	DECLARE_READ8_MEMBER(flyball_scanline_r);
63	63	DECLARE_READ8_MEMBER(flyball_potsense_r);

trunk/src/mame/drivers/xybots.c
r29404	r29405
190	190
191	191	/* video hardware */
192	192	MCFG_GFXDECODE_ADD("gfxdecode", "palette", xybots)
193
	193
194	194	MCFG_PALETTE_ADD("palette", 1024)
195	195	MCFG_PALETTE_FORMAT(IIIIRRRRGGGGBBBB)
196	196

trunk/src/mame/drivers/centiped.c
r29404	r29405
2052	2052	ROM_END
2053	2053
2054	2054
2055		ROM_START( magworma )
	2055	ROM_START( magworma )
2056	2056	ROM_REGION( 0x10000, "maincpu", 0 )
2057	2057	ROM_LOAD( "h41.1d", 0x2000, 0x0800, CRC(773a3da6) SHA1(577ae0578231df83a768d6a50b86dcaf715a32d7) )
2058	2058	ROM_LOAD( "h42.1e", 0x2800, 0x0800, CRC(482c7808) SHA1(6d274a988e603d33131cb6ffbfe2cdd22fabf25b) )

trunk/src/mame/drivers/welltris.c
r29404	r29405
742	742	MCFG_SCREEN_VISIBLE_AREA(15, 335-1, 0, 224-1)
743	743
744	744	MCFG_DEVICE_MODIFY("vsystem_spr_old")
745		MCFG_VSYSTEM_SPR2_SET_OFFSETS(6, 1)
	745	MCFG_VSYSTEM_SPR2_SET_OFFSETS(6, 1)
746	746	MACHINE_CONFIG_END
747	747
748	748

trunk/src/mame/drivers/taitoair.c
r29404	r29405
716	716	MCFG_SCREEN_VISIBLE_AREA(016, 3216-1, 316, 2816-1)
717	717	MCFG_SCREEN_UPDATE_DRIVER(taitoair_state, screen_update_taitoair)
718	718	MCFG_SCREEN_PALETTE("palette")
719
	719
720	720	MCFG_GFXDECODE_ADD("gfxdecode", "palette", airsys)
721	721
722	722	MCFG_PALETTE_ADD_INIT_BLACK("palette", 51216+51216)

trunk/src/mame/drivers/nightgal.c
r29404	r29405
129	129	required_ioport m_io_dswb;
130	130	required_ioport m_io_dswc;
131	131	required_device<palette_device> m_palette;
132
	132
133	133	UINT8 nightgal_gfx_nibble( int niboffset );
134	134	void plot_nightgal_gfx_pixel( UINT8 pix, int x, int y );
135	135	};

trunk/src/mame/drivers/neptunp2.c
r29404	r29405
104	104	MCFG_SCREEN_SIZE(328, 328)
105	105	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 28, 308-1)
106	106	MCFG_SCREEN_PALETTE("palette")
107
	107
108	108	MCFG_GFXDECODE_ADD("gfxdecode", "palette", neptunp2)
109	109	MCFG_PALETTE_ADD("palette", 512)
110	110

trunk/src/mame/drivers/littlerb.c
r29404	r29405
155	155
156	156	static INPUT_PORTS_START( littlerb )
157	157	PORT_START("DSW") /* 16bit */
158		PORT_DIPNAME( 0x0003, 0x0001, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW1:8,7")
	158	PORT_DIPNAME( 0x0003, 0x0001, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW1:8,7")
159	159	PORT_DIPSETTING( 0x0003, "2" )
160	160	PORT_DIPSETTING( 0x0001, "3" )
161	161	PORT_DIPSETTING( 0x0002, "4" )
162	162	PORT_DIPSETTING( 0x0000, "5" )
163		PORT_DIPNAME( 0x001c, 0x0004, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:6,5,4")
	163	PORT_DIPNAME( 0x001c, 0x0004, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:6,5,4")
164	164	PORT_DIPSETTING( 0x0000, DEF_STR( 5C_1C ) )
165	165	PORT_DIPSETTING( 0x0010, DEF_STR( 4C_1C ) )
166	166	PORT_DIPSETTING( 0x0008, DEF_STR( 3C_1C ) )
r29404	r29405
169	169	PORT_DIPSETTING( 0x0014, DEF_STR( 1C_2C ) )
170	170	PORT_DIPSETTING( 0x000c, DEF_STR( 1C_3C ) )
171	171	PORT_DIPSETTING( 0x001c, DEF_STR( 1C_4C ) )
172		PORT_DIPNAME( 0x00e0, 0x0020, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:3,2,1")
	172	PORT_DIPNAME( 0x00e0, 0x0020, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:3,2,1")
173	173	PORT_DIPSETTING( 0x0000, DEF_STR( 5C_1C ) )
174	174	PORT_DIPSETTING( 0x0080, DEF_STR( 4C_1C ) )
175	175	PORT_DIPSETTING( 0x0040, DEF_STR( 3C_1C ) )
r29404	r29405
178	178	PORT_DIPSETTING( 0x00a0, DEF_STR( 1C_2C ) )
179	179	PORT_DIPSETTING( 0x0060, DEF_STR( 1C_3C ) )
180	180	PORT_DIPSETTING( 0x00e0, DEF_STR( 1C_4C ) )
181		PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:8")
	181	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:8")
182	182	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
183	183	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
184		PORT_DIPNAME( 0x0600, 0x0600, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:7,6")
	184	PORT_DIPNAME( 0x0600, 0x0600, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:7,6")
185	185	PORT_DIPSETTING( 0x0600, "Every 150,000" )
186	186	PORT_DIPSETTING( 0x0200, "Every 200,000" )
187	187	PORT_DIPSETTING( 0x0400, "Every 300,000" )
188	188	PORT_DIPSETTING( 0x0000, DEF_STR( None ) )
189		PORT_DIPNAME( 0x3800, 0x2800, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:5,4,3")
	189	PORT_DIPNAME( 0x3800, 0x2800, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:5,4,3")
190	190	PORT_DIPSETTING( 0x3800, DEF_STR( Easy ) )
191	191	PORT_DIPSETTING( 0x1800, DEF_STR( Medium_Easy ) )
192	192	PORT_DIPSETTING( 0x2800, DEF_STR( Normal ) )
r29404	r29405
196	196	PORT_DIPSETTING( 0x2000, DEF_STR( Very_Hard ) )
197	197	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
198	198	PORT_SERVICE_DIPLOC( 0x4000, IP_ACTIVE_LOW, "SW2:2" )
199		PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:1")
	199	PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:1")
200	200	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
201	201	PORT_DIPSETTING( 0x8000, DEF_STR( On ) )
202	202

trunk/src/mame/drivers/mpu4misc.c
r29404	r29405
373	373	GAME_CUSTOM( 199?, m4shkwav__a, m4shkwav, "swave_v210_11376_0bb3_nlv.bin", 0x0000, 0x040000, CRC(3fcaf973) SHA1(28258c8c60e6b542e1789cd8a4cfd530d1ed6084), "Qps","Shockwave (Qps) (MPU4) (set 2)" )
374	374	GAME_CUSTOM( 199?, m4shkwav__b, m4shkwav, "swsplv.bin", 0x0000, 0x040000, CRC(1e33e93f) SHA1(3e87f8ed35da776e1968c9574c140cc3984ea8de), "Qps","Shockwave (Qps) (MPU4) (set 3)" )
375	375	//This rom is possibly bad, data content isn't multiple of 0x800, padding with low bits rather than high
376		ROM_START( m4shkwav__c )
377		ROM_REGION( 0x080000, "maincpu", 0 )
378		ROM_LOAD( "sho1_0lv.bin", 0x0000, 0x080000, BAD_DUMP CRC(a76d8544) SHA1(8277a2ce311840b8405a087d3dc0bbf97054ad87) )
379		M4SHKWAV_EXTRA_ROMS
380		ROM_END
	376	ROM_START( m4shkwav__c )
	377	ROM_REGION( 0x080000, "maincpu", 0 )
	378	ROM_LOAD( "sho1_0lv.bin", 0x0000, 0x080000, BAD_DUMP CRC(a76d8544) SHA1(8277a2ce311840b8405a087d3dc0bbf97054ad87) )
	379	M4SHKWAV_EXTRA_ROMS
	380	ROM_END
381	381	GAME(199?, m4shkwav__c, m4shkwav ,mod4oki ,mpu4 , mpu4_state,m4default_big ,ROT0,"Qps","Shockwave (Qps) (MPU4) (set 4)",GAME_FLAGS )
382	382	GAME_CUSTOM( 199?, m4shkwav__d, m4shkwav, "swave_v300_1552_13ed_nlv.bin", 0x0000, 0x040000, CRC(b0e03f04) SHA1(fdd113af30fd9e87b171ecdf3be7e720366476b3), "Qps","Shockwave (Qps) (MPU4) (set 5)" )
383	383	GAME_CUSTOM( 199?, m4shkwav__e, m4shkwav, "swave_v300_1555_119d_lv.bin", 0x0000, 0x040000, CRC(45b786d4) SHA1(24fd4fdea684103334385ca329f384796b496e2c), "Qps","Shockwave (Qps) (MPU4) (set 6)" )

trunk/src/mame/drivers/warpwarp.c
r29404	r29405
772	772	MCFG_SCREEN_PALETTE("palette")
773	773
774	774	MCFG_GFXDECODE_ADD("gfxdecode", "palette", color)
775
	775
776	776	MCFG_PALETTE_ADD("palette", 2*256+1)
777	777	MCFG_PALETTE_INIT_OWNER(warpwarp_state,warpwarp)
778	778	MCFG_VIDEO_START_OVERRIDE(warpwarp_state,warpwarp)

trunk/src/mame/drivers/taitottl.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	Taito Discrete Hardware Games
4
5
	4
	5
6	6	Game Name(s) Part #'s Data PROM/ROM Chip Numbers
7	7	------------------------------------------+-----------+---------+---------------------------------------
8		Acrobat (1978) UNKNOWN
	8	Acrobat (1978) UNKNOWN
9	9	Astro Race (1973) UNKNOWN
10	10	Avenger (1976) - Vertical EG-1020 UNKNOWN
11	11	Attack (1976) UNKNOWN
r29404	r29405
37	37	Wall Block (1978) UNKNOWN
38	38	Western Gun (1975) UNKNOWN
39	39	Zun Zun Block (1979) YES 3 - (2 x 512bytes, 1 x 32bytes)
40
	40
41	41	***************************************************************************/
42	42
43	43
r29404	r29405
77	77	public:
78	78	taitottl_state(const machine_config &mconfig, device_type type, const char *tag)
79	79	: driver_device(mconfig, type, tag),
80		m_maincpu(*this, "maincpu"),
81		m_video(*this, "fixfreq")
	80	m_maincpu(*this, "maincpu"),
	81	m_video(*this, "fixfreq")
82	82	{
83	83	}
84
	84
85	85	// devices
86	86	required_device<netlist_mame_device_t> m_maincpu;
87	87	required_device<fixedfreq_device> m_video;
88
	88
89	89	protected:
90
	90
91	91	// driver_device overrides
92	92	virtual void machine_start();
93	93	virtual void machine_reset();
94
	94
95	95	virtual void video_start();
96
	96
97	97	private:
98
	98
99	99	};
100	100
101	101
102	102	static NETLIST_START(taitottl)
103	103	SOLVER(Solver, 48000)
104		// PARAM(Solver.FREQ, 48000)
	104	// PARAM(Solver.FREQ, 48000)
105	105	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
106	106
107	107	// schematics
108	108	//...
109	109
110		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
111		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	110	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	111	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
112	112	NETLIST_END()
113	113
114	114
r29404	r29405
138	138
139	139
140	140	/***************************************************************************
141
	141
142	142	Game driver(s)
143
	143
144	144	***************************************************************************/
145	145
146	146	/*
147
148		label loc. Part #
	147
	148	label loc. Part #
149	149	==========================================================
150		CR11 N5 74s287 yes, it says CRxx not GNxx
151		GN10 H5 5623
152		GN09 N6 soldered in
153		GN08 J7 IM5200CJG
154		GN07 L9 soldered in
155		GN06 H6 7621
156		GN05 G9 74s287
157		GN04 F9 7643
158		GN03 D9 7621
159		GN02 C9 74s287
160		GN01 B9 7643
161
	150	CR11 N5 74s287 yes, it says CRxx not GNxx
	151	GN10 H5 5623
	152	GN09 N6 soldered in
	153	GN08 J7 IM5200CJG
	154	GN07 L9 soldered in
	155	GN06 H6 7621
	156	GN05 G9 74s287
	157	GN04 F9 7643
	158	GN03 D9 7621
	159	GN02 C9 74s287
	160	GN01 B9 7643
	161
162	162	*/
163	163
164	164	ROM_START( gunman )
r29404	r29405
180	180	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
181	181
182	182	ROM_REGION( 0x0800, "roms", ROMREGION_ERASE00 )
183		ROM_LOAD( "tl01.4a", 0x0000, 0x0800, CRC(65b730f7) SHA1(f82931c9a128021c97d1d41b5eac05df55dd5994) ) // MMI 6353
	183	ROM_LOAD( "tl01.4a", 0x0000, 0x0800, CRC(65b730f7) SHA1(f82931c9a128021c97d1d41b5eac05df55dd5994) ) // MMI 6353
184	184	ROM_END
185	185
186	186

trunk/src/mame/drivers/cbuster.c
r29404	r29405
322	322	MCFG_DECO16IC_ADD("tilegen1", twocrude_deco16ic_tilegen1_intf)
323	323	MCFG_DECO16IC_GFXDECODE("gfxdecode")
324	324	MCFG_DECO16IC_PALETTE("palette")
325
	325
326	326	MCFG_DECO16IC_ADD("tilegen2", twocrude_deco16ic_tilegen2_intf)
327	327	MCFG_DECO16IC_GFXDECODE("gfxdecode")
328	328	MCFG_DECO16IC_PALETTE("palette")

trunk/src/mame/drivers/ghosteo.c
r29404	r29405
273	273	case 0xFF :
274	274	{
275	275	nand.mode = NAND_M_INIT;
276		m_s3c2410->frnb_w(1);
	276	m_s3c2410->frnb_w(1);
277	277	}
278	278	break;
279	279	case 0x00 :

trunk/src/mame/drivers/onetwo.c
r29404	r29405
72	72	required_device<cpu_device> m_audiocpu;
73	73	required_device<gfxdecode_device> m_gfxdecode;
74	74	required_device<palette_device> m_palette;
75
	75
76	76	DECLARE_WRITE8_MEMBER(onetwo_fgram_w);
77	77	DECLARE_WRITE8_MEMBER(onetwo_cpubank_w);
78	78	DECLARE_WRITE8_MEMBER(onetwo_coin_counters_w);

trunk/src/mame/drivers/nbmj8891.c
r29404	r29405
13	13	two don't run on the same hardware. mjcamera is in nbmj8688.c.
14	14
15	15	- In mjfocus(Medal Type), sometimes CPU's hands are forced out from the screen.
16		This is correct behaviour.
17
	16	This is correct behaviour.
	17
18	18	TODO:
19	19
20	20	- Telmajan cannot set to JAMMA type. I don't know why.

trunk/src/mame/drivers/gunsmoke.c
r29404	r29405
313	313	MCFG_SCREEN_PALETTE("palette")
314	314
315	315	MCFG_GFXDECODE_ADD("gfxdecode", "palette", gunsmoke)
316
	316
317	317	MCFG_PALETTE_ADD("palette", 324+1616+16*16)
318	318	MCFG_PALETTE_INDIRECT_ENTRIES(256)
319	319	MCFG_PALETTE_INIT_OWNER(gunsmoke_state, gunsmoke)

trunk/src/mame/drivers/deco_ld.c
r29404	r29405
141	141	required_device<gfxdecode_device> m_gfxdecode;
142	142	required_device<screen_device> m_screen;
143	143	required_device<palette_device> m_palette;
144
	144
145	145	UINT8 m_laserdisc_data;
146	146	int m_nmimask;
147	147	DECLARE_WRITE8_MEMBER(rblaster_sound_w);
r29404	r29405
266	266	/* same as Burger Time HW */
267	267	WRITE8_MEMBER(deco_ld_state::decold_palette_w)
268	268	{
269		m_palette->write(space, offset, UINT8(~data));
	269	m_palette->write(space, offset, UINT8(~data));
270	270	}
271	271
272	272	/* unknown, but certainly related to audiocpu somehow */

trunk/src/mame/drivers/seta.c
r29404	r29405
2208	2208	AM_RANGE(0x500000, 0x500001) AM_READ_PORT("P1") // P1
2209	2209	AM_RANGE(0x500002, 0x500003) AM_READ_PORT("P2") // P2
2210	2210	AM_RANGE(0x500004, 0x500005) AM_READ_PORT("COINS") // Coins
2211		// AM_RANGE(0xa00000, 0xa03fff) AM_DEVREADWRITE("x1snd", x1_010_device, word_r, word_w) // Sound - not on this bootleg
	2211	// AM_RANGE(0xa00000, 0xa03fff) AM_DEVREADWRITE("x1snd", x1_010_device, word_r, word_w) // Sound - not on this bootleg
2212	2212	AM_RANGE(0xb00000, 0xb003ff) AM_RAM AM_SHARE("paletteram") // Palette
2213	2213	AM_RANGE(0xc00000, 0xc03fff) AM_RAM AM_DEVREADWRITE("spritegen", seta001_device, spritecode_r16, spritecode_w16) // Sprites Code + X + Attr
2214	2214	/**/AM_RANGE(0xd00000, 0xd00001) AM_RAM // ? 0x4000
r29404	r29405
8036	8036	static ADDRESS_MAP_START( blockcarb_sound_portmap, AS_IO, 8, seta_state )
8037	8037	ADDRESS_MAP_UNMAP_HIGH
8038	8038	ADDRESS_MAP_GLOBAL_MASK(0xff)
8039		// AM_RANGE(0x00, 0x01) AM_MIRROR(0x3e) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
8040		// AM_RANGE(0xc0, 0xc0) AM_MIRROR(0x3f) AM_READ(wiggie_soundlatch_r)
	8039	// AM_RANGE(0x00, 0x01) AM_MIRROR(0x3e) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
	8040	// AM_RANGE(0xc0, 0xc0) AM_MIRROR(0x3f) AM_READ(wiggie_soundlatch_r)
8041	8041	ADDRESS_MAP_END
8042	8042
8043	8043	static MACHINE_CONFIG_DERIVED( blockcarb, blockcar )
r29404	r29405
10101	10101	ROM_LOAD16_BYTE( "tl5.bin", 0x080001, 0x040000, CRC(9369e8dc) SHA1(645ae72a8b49ec43c26cdee5b6cb8cca5f46e542) )
10102	10102
10103	10103	ROM_REGION( 0x100000, "oki", 0 ) /* 6295 samples */
10104		ROM_LOAD( "tl7.bin", 0x000000, 0x040000, CRC(41e899dc) SHA1(36c8161dcb68cdc312c7d1177dbcfb9b62b18f05) ) // == so2_09.12b mercs Mercs (World 900302)
	10104	ROM_LOAD( "tl7.bin", 0x000000, 0x040000, CRC(41e899dc) SHA1(36c8161dcb68cdc312c7d1177dbcfb9b62b18f05) ) // == so2_09.12b mercs Mercs (World 900302)
10105	10105
10106	10106	ROM_REGION( 0x10000, "audiocpu", 0 )
10107		ROM_LOAD( "tl8.bin", 0x000000, 0x010000, CRC(d09d7c7a) SHA1(8e8532be08818c855d9c3ce45716eb07cfab5767) ) //cpu prg
	10107	ROM_LOAD( "tl8.bin", 0x000000, 0x010000, CRC(d09d7c7a) SHA1(8e8532be08818c855d9c3ce45716eb07cfab5767) ) //cpu prg
10108	10108	ROM_END
10109	10109
10110	10110

trunk/src/mame/drivers/rohga.c
r29404	r29405
840	840	MCFG_DECO16IC_ADD("tilegen1", rohga_deco16ic_tilegen1_intf)
841	841	MCFG_DECO16IC_GFXDECODE("gfxdecode")
842	842	MCFG_DECO16IC_PALETTE("palette")
843
	843
844	844	MCFG_DECO16IC_ADD("tilegen2", rohga_deco16ic_tilegen2_intf)
845	845	MCFG_DECO16IC_GFXDECODE("gfxdecode")
846	846	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
889	889	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529))
890	890	MCFG_SCREEN_SIZE(408, 328)
891	891	MCFG_SCREEN_VISIBLE_AREA(08, 408-1, 18, 318-1)
892		MCFG_SCREEN_UPDATE_DRIVER(rohga_state, screen_update_wizdfire)
	892	MCFG_SCREEN_UPDATE_DRIVER(rohga_state, screen_update_wizdfire)
893	893
894	894	MCFG_GFXDECODE_ADD("gfxdecode", "palette", wizdfire)
895	895	MCFG_PALETTE_ADD("palette", 2048)
r29404	r29405
900	900	MCFG_DECO16IC_ADD("tilegen1", rohga_deco16ic_tilegen1_intf)
901	901	MCFG_DECO16IC_GFXDECODE("gfxdecode")
902	902	MCFG_DECO16IC_PALETTE("palette")
903
	903
904	904	MCFG_DECO16IC_ADD("tilegen2", rohga_deco16ic_tilegen2_intf)
905	905	MCFG_DECO16IC_GFXDECODE("gfxdecode")
906	906	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
968	968	MCFG_DECO16IC_ADD("tilegen1", nitrobal_deco16ic_tilegen1_intf)
969	969	MCFG_DECO16IC_GFXDECODE("gfxdecode")
970	970	MCFG_DECO16IC_PALETTE("palette")
971
	971
972	972	MCFG_DECO16IC_ADD("tilegen2", nitrobal_deco16ic_tilegen2_intf)
973	973	MCFG_DECO16IC_GFXDECODE("gfxdecode")
974	974	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
1040	1040	MCFG_DECO16IC_ADD("tilegen1", rohga_deco16ic_tilegen1_intf)
1041	1041	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1042	1042	MCFG_DECO16IC_PALETTE("palette")
1043
	1043
1044	1044	MCFG_DECO16IC_ADD("tilegen2", rohga_deco16ic_tilegen2_intf)
1045	1045	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1046	1046	MCFG_DECO16IC_PALETTE("palette")

trunk/src/mame/drivers/asteroid.c
r29404	r29405
645	645
646	646	MCFG_DEVICE_ADD("dvg", DVG, 0)
647	647	MCFG_AVGDVG_VECTOR("vector")
648
	648
649	649	/* sound hardware */
650	650	MCFG_SPEAKER_STANDARD_MONO("mono")
651	651

trunk/src/mame/drivers/megatech.c
r29404	r29405
88	88	TIMER_Z80_RUN_STATE,
89	89	TIMER_Z80_STOP_STATE
90	90	};
91
	91
92	92	mtech_state(const machine_config &mconfig, device_type type, const char *tag)
93	93	: md_base_state(mconfig, type, tag),
94	94	m_vdp1(*this, "vdp1"),
95	95	m_bioscpu(*this, "mtbios")
96	96	{ }
97
	97
98	98	DECLARE_WRITE_LINE_MEMBER( snd_int_callback );
99	99	DECLARE_WRITE_LINE_MEMBER( bios_int_callback );
100	100	DECLARE_READ8_MEMBER(cart_select_r);
r29404	r29405
113	113	DECLARE_READ8_MEMBER(sms_count_r);
114	114	DECLARE_READ8_MEMBER(sms_ioport_dc_r);
115	115	DECLARE_READ8_MEMBER(sms_ioport_dd_r);
116		DECLARE_WRITE8_MEMBER(mt_sms_standard_rom_bank_w);
117
	116	DECLARE_WRITE8_MEMBER(mt_sms_standard_rom_bank_w);
	117
118	118	DECLARE_DRIVER_INIT(mt_crt);
119	119	DECLARE_DRIVER_INIT(mt_slot);
120	120	DECLARE_MACHINE_RESET(megatech);
r29404	r29405
122	122	UINT32 screen_update_main(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
123	123	UINT32 screen_update_menu(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
124	124	void screen_eof_main(screen_device &screen, bool state);
125
	125
126	126	protected:
127	127	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
128
129		private:
	128
	129	private:
130	130	UINT8 m_mt_cart_select_reg;
131	131	UINT32 m_bios_port_ctrl;
132	132	int m_current_game_is_sms; // is the current game SMS based (running on genesis z80, in VDP compatibility mode)
133	133	UINT32 m_bios_ctrl_inputs;
134	134	UINT8 m_bios_ctrl[6];
135	135	int m_mt_bank_addr;
136
	136
137	137	int m_cart_is_genesis[8];
138
	138
139	139	void set_genz80_as_md();
140	140	void set_genz80_as_sms();
141
	141
142	142	TIMER_CALLBACK_MEMBER(z80_run_state);
143	143	TIMER_CALLBACK_MEMBER(z80_stop_state);
144
	144
145	145	UINT8* m_banked_ram;
146	146	UINT8* sms_mainram;
147	147	UINT8* sms_rom;
148
	148
149	149	required_device<sega315_5124_device> m_vdp1;
150		required_device<cpu_device> m_bioscpu;
	150	required_device<cpu_device> m_bioscpu;
151	151	};
152	152
153	153
r29404	r29405
328	328	{
329	329	int bank = data & 0x1f;
330	330	//logerror("bank w %02x %02x\n", offset, data);
331
	331
332	332	sms_mainram[0x1ffc + offset] = data;
333	333	switch (offset)
334	334	{
r29404	r29405
347	347	case 3:
348	348	memcpy(sms_rom+0x8000, space.machine().root_device().memregion("maincpu")->base()+bank*0x4000, 0x4000);
349	349	break;
350
	350
351	351	}
352	352	}
353	353
r29404	r29405
356	356	address_space &prg = machine().device("genesis_snd_z80")->memory().space(AS_PROGRAM);
357	357	address_space &io = machine().device("genesis_snd_z80")->memory().space(AS_IO);
358	358	sn76496_base_device *sn = machine().device<sn76496_base_device>("snsnd");
359
	359
360	360	// main ram area
361	361	sms_mainram = (UINT8 *)prg.install_ram(0xc000, 0xdfff, 0, 0x2000);
362	362	memset(sms_mainram,0x00,0x2000);
363
	363
364	364	// fixed rom bank area
365	365	sms_rom = (UINT8 *)prg.install_rom(0x0000, 0xbfff, NULL);
366
	366
367	367	memcpy(sms_rom, machine().root_device().memregion("maincpu")->base(), 0xc000);
368
	368
369	369	prg.install_write_handler(0xfffc, 0xffff, write8_delegate(FUNC(mtech_state::mt_sms_standard_rom_bank_w),this));
370
	370
371	371	// ports
372	372	io.install_read_handler (0x40, 0x41, 0xff, 0x3e, read8_delegate(FUNC(mtech_state::sms_count_r),this));
373	373	io.install_write_handler (0x40, 0x41, 0xff, 0x3e, write8_delegate(FUNC(sn76496_device::write),sn));
374	374	io.install_readwrite_handler (0x80, 0x80, 0xff, 0x3e, read8_delegate(FUNC(sega315_5124_device::vram_read),(sega315_5124_device )m_vdp), write8_delegate(FUNC(sega315_5124_device::vram_write),(sega315_5124_device )m_vdp));
375	375	io.install_readwrite_handler (0x81, 0x81, 0xff, 0x3e, read8_delegate(FUNC(sega315_5124_device::register_read),(sega315_5124_device )m_vdp), write8_delegate(FUNC(sega315_5124_device::register_write),(sega315_5124_device )m_vdp));
376
	376
377	377	io.install_read_handler (0x10, 0x10, read8_delegate(FUNC(mtech_state::sms_ioport_dd_r),this)); // super tetris
378
	378
379	379	io.install_read_handler (0xdc, 0xdc, read8_delegate(FUNC(mtech_state::sms_ioport_dc_r),this));
380	380	io.install_read_handler (0xdd, 0xdd, read8_delegate(FUNC(mtech_state::sms_ioport_dd_r),this));
381	381	io.install_read_handler (0xde, 0xde, read8_delegate(FUNC(mtech_state::sms_ioport_dd_r),this));
r29404	r29405
391	391
392	392	prg.install_readwrite_bank(0x0000, 0x1fff, "bank1");
393	393	machine().root_device().membank("bank1")->set_base(m_genz80.z80_prgram);
394
	394
395	395	prg.install_ram(0x0000, 0x1fff, m_genz80.z80_prgram);
396	396
397	397	prg.install_readwrite_handler(0x4000, 0x4003, read8_delegate(FUNC(ym2612_device::read),ym2612), write8_delegate(FUNC(ym2612_device::write),ym2612));
r29404	r29405
558	558	READ8_MEMBER(mtech_state::bios_joypad_r )
559	559	{
560	560	UINT8 retdata = 0;
561
	561
562	562	if (m_bios_port_ctrl == 0x55)
563	563	{
564	564	/* A keys */
r29404	r29405
570	570	retdata = (m_io_pad_3b[0]->read() & 0x3f) \| ((m_io_pad_3b[1]->read() & 0x03) << 6);
571	571	else
572	572	retdata = ((m_io_pad_3b[1]->read() & 0x3c) >> 2) \| 0xf0;
573
	573
574	574	}
575	575	return retdata;
576	576	}
r29404	r29405
637	637	{
638	638	UINT32* lineptr = &bitmap.pix32(y);
639	639	UINT32* srcptr = &m_vdp->get_bitmap().pix32(y + SEGA315_5124_TBORDER_START + SEGA315_5124_NTSC_224_TBORDER_HEIGHT);
640
	640
641	641	for (int x = 0; x < SEGA315_5124_WIDTH; x++)
642	642	lineptr[x] = srcptr[x];
643		}
	643	}
644	644	#endif
645	645	}
646	646	return 0;

trunk/src/mame/drivers/vamphalf.c
r29404	r29405
90	90	optional_shared_ptr<UINT16> m_wram;
91	91	optional_shared_ptr<UINT32> m_tiles32;
92	92	optional_shared_ptr<UINT32> m_wram32;
93
	93
94	94	required_device<cpu_device> m_maincpu;
95	95	optional_device<qs1000_device> m_qs1000;
96	96	optional_device<okim6295_device> m_oki;
r29404	r29405
98	98	required_device<eeprom_serial_93cxx_device> m_eeprom;
99	99	required_device<gfxdecode_device> m_gfxdecode;
100	100	required_device<palette_device> m_palette;
101
	101
102	102	int m_flip_bit;
103	103	int m_flipscreen;
104	104	int m_palshift;

trunk/src/mame/drivers/1942.c
r29404	r29405
72	72	#include "includes/1942.h"
73	73
74	74	#define NLFILT(RA, R1, C1, R2) \
75		NET_C(RA.1, V5) \
76		NET_C(RA.2, R1.1) \
77		NET_C(R1.2, GND) \
78		NET_C(R1.1, C1.1) \
79		NET_C(C1.2, R2.1)
	75	NET_C(RA.1, V5) \
	76	NET_C(RA.2, R1.1) \
	77	NET_C(R1.2, GND) \
	78	NET_C(R1.1, C1.1) \
	79	NET_C(C1.2, R2.1)
80	80
81	81	static NETLIST_START(nl_1942)
82	82
83		/* Standard stuff */
	83	/* Standard stuff */
84	84
85		SOLVER(Solver, 48000)
86		ANALOG_INPUT(V5, 5)
	85	SOLVER(Solver, 48000)
	86	ANALOG_INPUT(V5, 5)
87	87
88		/* AY 8910 internal resistors */
	88	/* AY 8910 internal resistors */
89	89
90		RES(R_AY1_1, 1000);
91		RES(R_AY1_2, 1000);
92		RES(R_AY1_3, 1000);
93		RES(R_AY2_1, 1000);
94		RES(R_AY2_2, 1000);
95		RES(R_AY2_3, 1000);
	90	RES(R_AY1_1, 1000);
	91	RES(R_AY1_2, 1000);
	92	RES(R_AY1_3, 1000);
	93	RES(R_AY2_1, 1000);
	94	RES(R_AY2_2, 1000);
	95	RES(R_AY2_3, 1000);
96	96
97		RES(R2, 220000)
98		RES(R3, 220000)
99		RES(R4, 220000)
100		RES(R5, 220000)
101		RES(R6, 220000)
102		RES(R7, 220000)
	97	RES(R2, 220000)
	98	RES(R3, 220000)
	99	RES(R4, 220000)
	100	RES(R5, 220000)
	101	RES(R6, 220000)
	102	RES(R7, 220000)
103	103
104		RES(R11, 10000)
105		RES(R12, 10000)
106		RES(R13, 10000)
107		RES(R14, 10000)
108		RES(R15, 10000)
109		RES(R16, 10000)
	104	RES(R11, 10000)
	105	RES(R12, 10000)
	106	RES(R13, 10000)
	107	RES(R14, 10000)
	108	RES(R15, 10000)
	109	RES(R16, 10000)
110	110
111		CAP(CC7, 10e-6)
112		CAP(CC8, 10e-6)
113		CAP(CC9, 10e-6)
114		CAP(CC10, 10e-6)
115		CAP(CC11, 10e-6)
116		CAP(CC12, 10e-6)
	111	CAP(CC7, 10e-6)
	112	CAP(CC8, 10e-6)
	113	CAP(CC9, 10e-6)
	114	CAP(CC10, 10e-6)
	115	CAP(CC11, 10e-6)
	116	CAP(CC12, 10e-6)
117	117
118		NLFILT(R_AY2_3, R13, CC7, R2)
119		NLFILT(R_AY2_2, R15, CC8, R3)
120		NLFILT(R_AY2_1, R11, CC9, R4)
	118	NLFILT(R_AY2_3, R13, CC7, R2)
	119	NLFILT(R_AY2_2, R15, CC8, R3)
	120	NLFILT(R_AY2_1, R11, CC9, R4)
121	121
122		NLFILT(R_AY1_3, R12, CC10, R5)
123		NLFILT(R_AY1_2, R14, CC11, R6)
124		NLFILT(R_AY1_1, R16, CC12, R7)
	122	NLFILT(R_AY1_3, R12, CC10, R5)
	123	NLFILT(R_AY1_2, R14, CC11, R6)
	124	NLFILT(R_AY1_1, R16, CC12, R7)
125	125
126		POT(VR, 2000)
127		NET_C(VR.3, GND)
	126	POT(VR, 2000)
	127	NET_C(VR.3, GND)
128	128
129		NET_C(R2.2, VR.1)
130		NET_C(R3.2, VR.1)
131		NET_C(R4.2, VR.1)
132		NET_C(R5.2, VR.1)
133		NET_C(R6.2, VR.1)
134		NET_C(R7.2, VR.1)
	129	NET_C(R2.2, VR.1)
	130	NET_C(R3.2, VR.1)
	131	NET_C(R4.2, VR.1)
	132	NET_C(R5.2, VR.1)
	133	NET_C(R6.2, VR.1)
	134	NET_C(R7.2, VR.1)
135	135
136		CAP(CC6, 10e-6)
137		RES(R1, 100000)
	136	CAP(CC6, 10e-6)
	137	RES(R1, 100000)
138	138
139		NET_C(CC6.1, VR.2)
140		NET_C(CC6.2, R1.1)
141		NET_C(R1.2, GND)
	139	NET_C(CC6.1, VR.2)
	140	NET_C(CC6.2, R1.1)
	141	NET_C(R1.2, GND)
142	142
143	143	NETLIST_END()
144	144
r29404	r29405
519	519
520	520	static const ay8910_interface ay8910_config =
521	521	{
522		AY8910_RESISTOR_OUTPUT,
523		AY8910_DEFAULT_LOADS,
524		DEVCB_NULL,
525		DEVCB_NULL,
526		DEVCB_NULL,
527		DEVCB_NULL
	522	AY8910_RESISTOR_OUTPUT,
	523	AY8910_DEFAULT_LOADS,
	524	DEVCB_NULL,
	525	DEVCB_NULL,
	526	DEVCB_NULL,
	527	DEVCB_NULL
528	528	};
529	529
530	530	static MACHINE_CONFIG_START( 1942, _1942_state )
r29404	r29405
541	541
542	542	/* video hardware */
543	543	MCFG_GFXDECODE_ADD("gfxdecode", "palette", 1942)
544
	544
545	545	MCFG_PALETTE_ADD("palette", 644+4328+1616)
546	546	MCFG_PALETTE_INDIRECT_ENTRIES(256)
547	547	MCFG_PALETTE_INIT_OWNER(_1942_state, 1942)
r29404	r29405
557	557	/* sound hardware */
558	558	MCFG_SPEAKER_STANDARD_MONO("mono")
559	559
560		MCFG_SOUND_ADD("ay1", AY8910, AUDIO_CLOCK) /* 1.5 MHz */
561		MCFG_SOUND_CONFIG(ay8910_config)
562		MCFG_SOUND_ROUTE_EX(0, "snd_nl", 1.0, 0)
563		MCFG_SOUND_ROUTE_EX(1, "snd_nl", 1.0, 1)
564		MCFG_SOUND_ROUTE_EX(2, "snd_nl", 1.0, 2)
565		MCFG_SOUND_ADD("ay2", AY8910, AUDIO_CLOCK) /* 1.5 MHz */
566		MCFG_SOUND_CONFIG(ay8910_config)
567		MCFG_SOUND_ROUTE_EX(0, "snd_nl", 1.0, 3)
568		MCFG_SOUND_ROUTE_EX(1, "snd_nl", 1.0, 4)
569		MCFG_SOUND_ROUTE_EX(2, "snd_nl", 1.0, 5)
	560	MCFG_SOUND_ADD("ay1", AY8910, AUDIO_CLOCK) /* 1.5 MHz */
	561	MCFG_SOUND_CONFIG(ay8910_config)
	562	MCFG_SOUND_ROUTE_EX(0, "snd_nl", 1.0, 0)
	563	MCFG_SOUND_ROUTE_EX(1, "snd_nl", 1.0, 1)
	564	MCFG_SOUND_ROUTE_EX(2, "snd_nl", 1.0, 2)
	565	MCFG_SOUND_ADD("ay2", AY8910, AUDIO_CLOCK) /* 1.5 MHz */
	566	MCFG_SOUND_CONFIG(ay8910_config)
	567	MCFG_SOUND_ROUTE_EX(0, "snd_nl", 1.0, 3)
	568	MCFG_SOUND_ROUTE_EX(1, "snd_nl", 1.0, 4)
	569	MCFG_SOUND_ROUTE_EX(2, "snd_nl", 1.0, 5)
570	570
571		/* NETLIST configuration using internal AY8910 resistor values */
	571	/* NETLIST configuration using internal AY8910 resistor values */
572	572
573		MCFG_SOUND_ADD("snd_nl", NETLIST_SOUND, 48000)
574		MCFG_NETLIST_SETUP(nl_1942)
575		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 5.0)
	573	MCFG_SOUND_ADD("snd_nl", NETLIST_SOUND, 48000)
	574	MCFG_NETLIST_SETUP(nl_1942)
	575	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 5.0)
576	576
577		MCFG_NETLIST_STREAM_INPUT("snd_nl", 0, "R_AY1_1.R")
578		MCFG_NETLIST_STREAM_INPUT("snd_nl", 1, "R_AY1_2.R")
579		MCFG_NETLIST_STREAM_INPUT("snd_nl", 2, "R_AY1_3.R")
580		MCFG_NETLIST_STREAM_INPUT("snd_nl", 3, "R_AY2_1.R")
581		MCFG_NETLIST_STREAM_INPUT("snd_nl", 4, "R_AY2_2.R")
582		MCFG_NETLIST_STREAM_INPUT("snd_nl", 5, "R_AY2_3.R")
	577	MCFG_NETLIST_STREAM_INPUT("snd_nl", 0, "R_AY1_1.R")
	578	MCFG_NETLIST_STREAM_INPUT("snd_nl", 1, "R_AY1_2.R")
	579	MCFG_NETLIST_STREAM_INPUT("snd_nl", 2, "R_AY1_3.R")
	580	MCFG_NETLIST_STREAM_INPUT("snd_nl", 3, "R_AY2_1.R")
	581	MCFG_NETLIST_STREAM_INPUT("snd_nl", 4, "R_AY2_2.R")
	582	MCFG_NETLIST_STREAM_INPUT("snd_nl", 5, "R_AY2_3.R")
583	583
584		MCFG_NETLIST_STREAM_OUTPUT("snd_nl", 0, "R1.1")
585		MCFG_NETLIST_ANALOG_MULT_OFFSET(100000.0, 0.0)
	584	MCFG_NETLIST_STREAM_OUTPUT("snd_nl", 0, "R1.1")
	585	MCFG_NETLIST_ANALOG_MULT_OFFSET(100000.0, 0.0)
586	586
587	587	MACHINE_CONFIG_END
588	588

trunk/src/mame/drivers/bloodbro.c
r29404	r29405
472	472	MCFG_DEVICE_ADD("crtc", SEIBU_CRTC, 0)
473	473	MCFG_SEIBU_CRTC_LAYER_EN_CB(WRITE16(bloodbro_state, layer_en_w))
474	474	MCFG_SEIBU_CRTC_LAYER_SCROLL_CB(WRITE16(bloodbro_state, layer_scroll_w))
475
476	475
	476
477	477	MCFG_GFXDECODE_ADD("gfxdecode", "palette", bloodbro)
478	478	MCFG_PALETTE_ADD("palette", 2048)
479	479	MCFG_PALETTE_FORMAT(xxxxBBBBGGGGRRRR)

trunk/src/mame/drivers/blockhl.c
r29404	r29405
187	187
188	188	m_paletteram.resize(m_palette->entries() * 2);
189	189	m_palette->basemem().set(m_paletteram, ENDIANNESS_BIG, 2);
190
	190
191	191	save_item(NAME(m_paletteram));
192	192	save_item(NAME(m_palette_selected));
193	193	save_item(NAME(m_rombank));

trunk/src/mame/drivers/dai3wksi.c
r29404	r29405
67	67	optional_device<sn76477_device> m_ic79;
68	68	optional_device<sn76477_device> m_ic80;
69	69	optional_device<sn76477_device> m_ic81;
70
	70
71	71	/* video */
72	72	required_shared_ptr<UINT8> m_dai3wksi_videoram;
73	73	int m_dai3wksi_flipscreen;
r29404	r29405
83	83	DECLARE_WRITE8_MEMBER(dai3wksi_audio_1_w);
84	84	DECLARE_WRITE8_MEMBER(dai3wksi_audio_2_w);
85	85	DECLARE_WRITE8_MEMBER(dai3wksi_audio_3_w);
86
	86
87	87	/* i/o ports */
88	88	required_ioport m_in2;
89
	89
90	90	virtual void machine_start();
91	91	virtual void machine_reset();
92	92	};

trunk/src/mame/drivers/aleisttl.c
r29404	r29405
1	1	/***************************************************************************
2
	2
3	3	Allied Leisure discrete hardware games
4
	4
5	5	Hesitation (1974) AL-6500?
6	6	Paddle Battle (1973)
7	7	Robot (1975) AL-7500
r29404	r29405
10	10	Super Soccer (1973)
11	11	Tennis Tourney (1973)
12	12	Zap (1974) AL-6500
13
	13
14	14	***************************************************************************/
15	15
16	16
r29404	r29405
50	50	public:
51	51	sburners_state(const machine_config &mconfig, device_type type, const char *tag)
52	52	: driver_device(mconfig, type, tag),
53		m_maincpu(*this, "maincpu"),
54		m_video(*this, "fixfreq")
	53	m_maincpu(*this, "maincpu"),
	54	m_video(*this, "fixfreq")
55	55	{
56	56	}
57
	57
58	58	// devices
59	59	required_device<netlist_mame_device_t> m_maincpu;
60	60	required_device<fixedfreq_device> m_video;
61
	61
62	62	protected:
63
	63
64	64	// driver_device overrides
65	65	virtual void machine_start();
66	66	virtual void machine_reset();
67
	67
68	68	virtual void video_start();
69
	69
70	70	private:
71
	71
72	72	};
73	73
74	74
75	75	static NETLIST_START(sburners)
76	76	SOLVER(Solver, 48000)
77		// PARAM(Solver.FREQ, 48000)
	77	// PARAM(Solver.FREQ, 48000)
78	78	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
79	79
80	80	// schematics
81	81	//...
82	82
83		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
84		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	83	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	84	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
85	85	NETLIST_END()
86	86
87	87
r29404	r29405
111	111
112	112
113	113	/***************************************************************************
114
	114
115	115	Game driver(s)
116
	116
117	117	***************************************************************************/
118	118
119	119

trunk/src/mame/drivers/m62.c
r29404	r29405
1045	1045
1046	1046	/* video hardware */
1047	1047	MCFG_GFXDECODE_MODIFY("gfxdecode", lotlot)
1048
	1048
1049	1049	MCFG_PALETTE_MODIFY("palette")
1050	1050	MCFG_PALETTE_ENTRIES(768)
1051	1051

trunk/src/mame/drivers/exidyttl.c
r29404	r29405
13	13	Super Death Chase (1977)
14	14	Table Football (1975)
15	15	Tv Pinball (1974)
16
	16
17	17	***************************************************************************/
18	18
19	19
r29404	r29405
53	53	public:
54	54	exidyttl_state(const machine_config &mconfig, device_type type, const char *tag)
55	55	: driver_device(mconfig, type, tag),
56		m_maincpu(*this, "maincpu"),
57		m_video(*this, "fixfreq")
	56	m_maincpu(*this, "maincpu"),
	57	m_video(*this, "fixfreq")
58	58	{
59	59	}
60	60
61	61	// devices
62	62	required_device<netlist_mame_device_t> m_maincpu;
63	63	required_device<fixedfreq_device> m_video;
64
	64
65	65	protected:
66	66
67	67	// driver_device overrides
r29404	r29405
77	77
78	78	static NETLIST_START(attack)
79	79	SOLVER(Solver, 48000)
80		// PARAM(Solver.FREQ, 48000)
	80	// PARAM(Solver.FREQ, 48000)
81	81	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
82	82
83	83	// schematics
84	84	//...
85	85
86		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
87		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	86	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, exidyttl_state, sound_cb, "")
	87	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
88	88	NETLIST_END()
89	89
90	90
r29404	r29405
105	105	static MACHINE_CONFIG_START( attack, exidyttl_state )
106	106
107	107	/* basic machine hardware */
108		MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
	108	MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
109	109	MCFG_NETLIST_SETUP(attack)
110	110
111	111	/* video hardware */
r29404	r29405
147	147	/***********
148	148
149	149	Exidy Death Race 1976
150
	150
151	151	Drawing Name
152	152	------------
153		6331-36.E7 32x8 Right Gremlin
154		6301-91.J10 256x4
155
156		6331-36.R7 32x8 Left Gremlin
157		6301-91.V10 256x4
158
159		6301-92.V5 P1 (left car)
	153	6331-36.E7 32x8 Right Gremlin
	154	6301-91.J10 256x4
	155
	156	6331-36.R7 32x8 Left Gremlin
	157	6301-91.V10 256x4
	158
	159	6301-92.V5 P1 (left car)
160	160	6331-35.T7
161
162		6301-92.J5 P2 (right car)
	161
	162	6301-92.J5 P2 (right car)
163	163	6331-35.G7
164
165		6301-97.M11 Image Generation
	164
	165	6301-97.M11 Image Generation
166	166	6301-98.L11
167	167	6301-99.K11
168	168	6301-100.J11
169
170		6331-33.P14 Score & Timer
171
172		6331-31.A11 Timing / Sync
	169
	170	6331-33.P14 Score & Timer
	171
	172	6331-31.A11 Timing / Sync
173	173	6331-32.C12
174
175		***********/
176	174
	175	***********/
177	176
	177
178	178	ROM_START( deathrac )
179	179	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
180	180

trunk/src/mame/drivers/dwarfd.c
r29404	r29405
307	307	: driver_device(mconfig, type, tag),
308	308	m_maincpu(*this,"maincpu"),
309	309	m_gfxdecode(*this, "gfxdecode"),
310		m_palette(*this, "palette")
	310	m_palette(*this, "palette")
311	311	{ }
312	312
313	313	/* video-related */
r29404	r29405
337	337	required_device<cpu_device> m_maincpu;
338	338	required_device<gfxdecode_device> m_gfxdecode;
339	339	required_device<palette_device> m_palette;
340
	340
341	341	DECLARE_WRITE8_MEMBER(i8275_preg_w);
342	342	DECLARE_READ8_MEMBER(i8275_preg_r);
343	343	DECLARE_WRITE8_MEMBER(i8275_creg_w);

trunk/src/mame/drivers/slapshot.c
r29404	r29405
533	533	MCFG_TC0640FIO_READ_2_CB(IOPORT("BUTTONS"))
534	534	MCFG_TC0640FIO_READ_3_CB(IOPORT("SYSTEM"))
535	535	MCFG_TC0640FIO_READ_7_CB(IOPORT("JOY"))
536
	536
537	537	/* video hardware */
538	538	MCFG_SCREEN_ADD("screen", RASTER)
539	539	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mame/drivers/koftball.c
r29404	r29405
179	179	AM_RANGE(0x2da000, 0x2da003) AM_DEVWRITE8("ymsnd", ym2413_device, write, 0xff00)
180	180
181	181	AM_RANGE(0x2db000, 0x2db001) AM_WRITE(bmc_RAMDAC_offset_w) AM_SHARE("colorram")
182		AM_RANGE(0x2db002, 0x2db003) AM_READWRITE(bmc_RAMDAC_color_r, bmc_RAMDAC_color_w)
	182	AM_RANGE(0x2db002, 0x2db003) AM_READWRITE(bmc_RAMDAC_color_r, bmc_RAMDAC_color_w)
183	183	AM_RANGE(0x2db004, 0x2db005) AM_WRITENOP
184	184	AM_RANGE(0x2dc000, 0x2dc001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0xff00)
185	185	AM_RANGE(0x2f0000, 0x2f0003) AM_READ_PORT("INPUTS")
r29404	r29405
254	254	MCFG_SCREEN_SIZE(648, 328)
255	255	MCFG_SCREEN_VISIBLE_AREA(08, 648-1, 08, 308-1)
256	256	MCFG_SCREEN_PALETTE("palette")
257
	257
258	258	MCFG_PALETTE_ADD("palette", 256)
259	259
260	260	MCFG_GFXDECODE_ADD("gfxdecode", "palette", koftball)
261	261
262	262	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
263
	263
264	264	MCFG_SOUND_ADD("ymsnd", YM2413, XTAL_3_579545MHz) // guessed chip type, clock not verified
265	265	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
266	266	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)

trunk/src/mame/drivers/cninja.c
r29404	r29405
960	960	MCFG_DECO16IC_ADD("tilegen1", cninja_deco16ic_tilegen1_intf)
961	961	MCFG_DECO16IC_GFXDECODE("gfxdecode")
962	962	MCFG_DECO16IC_PALETTE("palette")
963
	963
964	964	MCFG_DECO16IC_ADD("tilegen2", cninja_deco16ic_tilegen2_intf)
965	965	MCFG_DECO16IC_GFXDECODE("gfxdecode")
966	966	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
1028	1028	MCFG_DECO16IC_ADD("tilegen1", cninja_deco16ic_tilegen1_intf)
1029	1029	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1030	1030	MCFG_DECO16IC_PALETTE("palette")
1031
	1031
1032	1032	MCFG_DECO16IC_ADD("tilegen2", cninja_deco16ic_tilegen2_intf)
1033	1033	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1034	1034	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
1091	1091	MCFG_DECO16IC_ADD("tilegen1", cninja_deco16ic_tilegen1_intf)
1092	1092	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1093	1093	MCFG_DECO16IC_PALETTE("palette")
1094
	1094
1095	1095	MCFG_DECO16IC_ADD("tilegen2", cninja_deco16ic_tilegen2_intf)
1096	1096	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1097	1097	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
1141	1141	MCFG_DECO16IC_ADD("tilegen1", edrandy_deco16ic_tilegen1_intf)
1142	1142	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1143	1143	MCFG_DECO16IC_PALETTE("palette")
1144
	1144
1145	1145	MCFG_DECO16IC_ADD("tilegen2", edrandy_deco16ic_tilegen2_intf)
1146	1146	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1147	1147	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
1206	1206	MCFG_DECO16IC_ADD("tilegen1", robocop2_deco16ic_tilegen1_intf)
1207	1207	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1208	1208	MCFG_DECO16IC_PALETTE("palette")
1209
	1209
1210	1210	MCFG_DECO16IC_ADD("tilegen2", robocop2_deco16ic_tilegen2_intf)
1211	1211	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1212	1212	MCFG_DECO16IC_PALETTE("palette")
r29404	r29405
1276	1276	MCFG_DECO16IC_ADD("tilegen1", mutantf_deco16ic_tilegen1_intf)
1277	1277	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1278	1278	MCFG_DECO16IC_PALETTE("palette")
1279
	1279
1280	1280	MCFG_DECO16IC_ADD("tilegen2", mutantf_deco16ic_tilegen2_intf)
1281	1281	MCFG_DECO16IC_GFXDECODE("gfxdecode")
1282	1282	MCFG_DECO16IC_PALETTE("palette")

trunk/src/mame/drivers/nss.c
r29404	r29405
311	311	required_device<rp5h01_device> m_rp5h01;
312	312	required_device<screen_device> m_screen;
313	313	optional_device<palette_device> m_palette;
314
	314
315	315	UINT8 m_wram_wp_flag;
316	316	UINT8 *m_wram;
317	317	UINT8 m_nmi_enable;

trunk/src/mame/drivers/go2000.c
r29404	r29405
62	62	required_device<cpu_device> m_maincpu;
63	63	required_device<gfxdecode_device> m_gfxdecode;
64	64	required_device<screen_device> m_screen;
65		required_device<palette_device> m_palette;
	65	required_device<palette_device> m_palette;
66	66	};
67	67
68	68

trunk/src/mame/drivers/tumblep.c
r29404	r29405
312	312	MCFG_DECO16IC_ADD("tilegen1", tumblep_deco16ic_tilegen1_intf)
313	313	MCFG_DECO16IC_GFXDECODE("gfxdecode")
314	314	MCFG_DECO16IC_PALETTE("palette")
315
	315
316	316	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
317	317	decospr_device::set_gfx_region(*device, 2);
318	318	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")

trunk/src/mame/drivers/deshoros.c
r29404	r29405
275	275	MCFG_SCREEN_VISIBLE_AREA(08, 488-1, 08, 168-1)
276	276	MCFG_SCREEN_UPDATE_DRIVER(destiny_state, screen_update_destiny)
277	277	MCFG_SCREEN_PALETTE("palette")
278
	278
279	279	MCFG_PALETTE_ADD("palette", 16)
280	280
281	281

trunk/src/mame/drivers/igs_m027.c
r29404	r29405
203	203
204	204	void igs_m027_state::video_start_fearless()
205	205	{
206
207	206	}
208	207
209	208	UINT32 igs_m027_state::screen_update_igs_majhong(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)

trunk/src/mame/drivers/smsmcorp.c
r29404	r29405
249	249	DECLARE_MACHINE_START(sureshot);
250	250	UINT32 screen_update_sms(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
251	251	required_device<cpu_device> m_maincpu;
252		required_device<screen_device> m_screen;
	252	required_device<screen_device> m_screen;
253	253	};
254	254
255	255

trunk/src/mame/drivers/subsino2.c
r29404	r29405
591	591	layer_t *l = &m_layers[i];
592	592
593	593	l->tmap = &machine().tilemap().create(m_gfxdecode, i ?
594		tilemap_get_info_delegate(FUNC(subsino2_state::ss9601_get_tile_info_1),this) :
595		tilemap_get_info_delegate(FUNC(subsino2_state::ss9601_get_tile_info_0),this),
596		TILEMAP_SCAN_ROWS, 8,8, 0x80,0x40);
	594	tilemap_get_info_delegate(FUNC(subsino2_state::ss9601_get_tile_info_1),this) :
	595	tilemap_get_info_delegate(FUNC(subsino2_state::ss9601_get_tile_info_0),this),
	596	TILEMAP_SCAN_ROWS, 8,8, 0x80,0x40);
597	597
598	598	l->tmap->set_transparent_pen(0);
599	599

trunk/src/mame/drivers/pgm2.c
r29404	r29405
1	1	/* PGM 2 hardware.
2	2
3		Motherboard is bare bones stuff, and does not contain any ROMs.
4		The IGS036 used by the games is an ARM based CPU, like IGS027A used on PGM1 it has internal ROM.
5		Decryption should be correct in most cases, but the ARM mode code at the start of the external
6		ROMs is a bit weird, with many BNV instructions rather than jumps. Maybe the ARM is customized,
7		the code has been 'NOPPED' out this way (BNV is Branch Never) or it's a different type of ARM?
8
9		- Some of the THUMB code looks like THUMB2 code
10		eg
11		f004 BL (HI) 00004000
12		e51f B #fffffa3e
13		0434 LSL R4, R6, 16
14		0000 LSL R0, R0, 0
	3	Motherboard is bare bones stuff, and does not contain any ROMs.
	4	The IGS036 used by the games is an ARM based CPU, like IGS027A used on PGM1 it has internal ROM.
	5	Decryption should be correct in most cases, but the ARM mode code at the start of the external
	6	ROMs is a bit weird, with many BNV instructions rather than jumps. Maybe the ARM is customized,
	7	the code has been 'NOPPED' out this way (BNV is Branch Never) or it's a different type of ARM?
15	8
16		should be a 32-bit branch instruction with the 2nd dword used as data.
	9	- Some of the THUMB code looks like THUMB2 code
	10	eg
	11	f004 BL (HI) 00004000
	12	e51f B #fffffa3e
	13	0434 LSL R4, R6, 16
	14	0000 LSL R0, R0, 0
17	15
	16	should be a 32-bit branch instruction with the 2nd dword used as data.
18	17
19		We need to determine where VRAM etc. map in order to attempt tests on the PCBs.
20	18
	19	We need to determine where VRAM etc. map in order to attempt tests on the PCBs.
21	20
22		PGM2 Motherboard Components:
23	21
24		IS61LV25616AL(SRAM)
25		IGS037(GFX PROCESSOR)
26		YMZ774-S(SOUND)
27		R5F21256SN(extra MCU for protection and ICcard communication)
28		- Appears to be refered to by the games as MPU
	22	PGM2 Motherboard Components:
29	23
30		Cartridges
31		IGS036 (MAIN CPU) (differs per game, internal code)
32		ROMs
33		Custom program ROM module (KOV3 only)
34		- on some games ROM socket contains Flash ROM + SRAM
	24	IS61LV25616AL(SRAM)
	25	IGS037(GFX PROCESSOR)
	26	YMZ774-S(SOUND)
	27	R5F21256SN(extra MCU for protection and ICcard communication)
	28	- Appears to be refered to by the games as MPU
35	29
36		QFP100 chip (Xlinx CPLD)
	30	Cartridges
	31	IGS036 (MAIN CPU) (differs per game, internal code)
	32	ROMs
	33	Custom program ROM module (KOV3 only)
	34	- on some games ROM socket contains Flash ROM + SRAM
37	35
38		~~Single~~ ~~PCB~~ ~~versions~~ of ~~some~~ ~~of t~~h~~e t~~i~~tles~~ ~~were a~~l~~so ava~~i~~lable~~
	36	QFP100 chip (Xlinx CPLD)
39	37
40		Only 5 Games were released for this platform, 3 of which are just updates / re-releases of older titles!
41		The platform has since been superseded by PGM3 (HD system uses flash cards etc.)
	38	Single PCB versions of some of the titles were also available
42	39
43		Oriental Legend 2
44		The King of Fighters '98 - Ultimate Match - Hero (NOT DUMPED)
45		Knights of Valour 2 New Legend
46		Dodonpachi Daioujou Tamashii
47		Knights of Valour 3
	40	Only 5 Games were released for this platform, 3 of which are just updates / re-releases of older titles!
	41	The platform has since been superseded by PGM3 (HD system uses flash cards etc.)
48	42
49		These were only released as single board PGM2 based hardware, seen for sale in Japan for around $250-$300
	43	Oriental Legend 2
	44	The King of Fighters '98 - Ultimate Match - Hero (NOT DUMPED)
	45	Knights of Valour 2 New Legend
	46	Dodonpachi Daioujou Tamashii
	47	Knights of Valour 3
50	48
51		Jigsaw World Arena
52		Puzzle of Ocha / Ochainu No Pazuru
	49	These were only released as single board PGM2 based hardware, seen for sale in Japan for around $250-$300
53	50
	51	Jigsaw World Arena
	52	Puzzle of Ocha / Ochainu No Pazuru
	53
54	54	*/
55	55
56	56	#include "emu.h"
r29404	r29405
511	511	// The King of Fighters '98 - Ultimate Match - Hero
512	512	// Jigsaw World Arena
513	513	//Puzzle of Ocha / Ochainu No Pazuru
514

trunk/src/mame/drivers/dassault.c
r29404	r29405
516	516	MCFG_DECO16IC_ADD("tilegen1", dassault_deco16ic_tilegen1_intf)
517	517	MCFG_DECO16IC_GFXDECODE("gfxdecode")
518	518	MCFG_DECO16IC_PALETTE("palette")
519
	519
520	520	MCFG_DECO16IC_ADD("tilegen2", dassault_deco16ic_tilegen2_intf)
521	521	MCFG_DECO16IC_GFXDECODE("gfxdecode")
522	522	MCFG_DECO16IC_PALETTE("palette")

trunk/src/mame/drivers/supbtime.c
r29404	r29405
348	348	MCFG_DECO16IC_ADD("tilegen1", supbtime_deco16ic_tilegen1_intf)
349	349	MCFG_DECO16IC_GFXDECODE("gfxdecode")
350	350	MCFG_DECO16IC_PALETTE("palette")
351
	351
352	352	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
353	353	decospr_device::set_gfx_region(*device, 2);
354	354	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")
r29404	r29405
395	395	MCFG_DECO16IC_ADD("tilegen1", supbtime_deco16ic_tilegen1_intf)
396	396	MCFG_DECO16IC_GFXDECODE("gfxdecode")
397	397	MCFG_DECO16IC_PALETTE("palette")
398
	398
399	399	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
400	400	decospr_device::set_gfx_region(*device, 2);
401	401	MCFG_DECO_SPRITE_GFXDECODE("gfxdecode")

trunk/src/mame/drivers/ggconnie.c
r29404	r29405
31	31	{
32	32	public:
33	33	ggconnie_state(const machine_config &mconfig, device_type type, const char *tag)
34		: pce_common_state(mconfig, type, tag),
	34	: pce_common_state(mconfig, type, tag),
35	35	m_rtc(*this, "rtc"),
36	36	m_oki(*this, "oki")
37	37	{ }

trunk/src/mame/drivers/blmbycar.c
r29404	r29405
363	363	MCFG_SCREEN_VISIBLE_AREA(0, 0x180-1, 0, 0x100-1)
364	364	MCFG_SCREEN_UPDATE_DRIVER(blmbycar_state, screen_update_blmbycar)
365	365	MCFG_SCREEN_PALETTE("palette")
366
	366
367	367	MCFG_GFXDECODE_ADD("gfxdecode", "palette", blmbycar)
368	368	MCFG_PALETTE_ADD("palette", 0x300)
369	369

trunk/src/mame/drivers/gbusters.c
r29404	r29405
257	257
258	258	membank("bank1")->configure_entries(0, 16, &ROM[0x10000], 0x2000);
259	259	membank("bank1")->set_entry(0);
260
	260
261	261	m_paletteram.resize(0x800);
262	262	m_palette->basemem().set(m_paletteram, ENDIANNESS_BIG, 2);
263
	263
264	264	save_item(NAME(m_paletteram));
265	265	save_item(NAME(m_palette_selected));
266	266	save_item(NAME(m_priority));
r29404	r29405
298	298	MCFG_SCREEN_VISIBLE_AREA(148, (64-14)8-1, 28, 308-1 )
299	299	MCFG_SCREEN_UPDATE_DRIVER(gbusters_state, screen_update_gbusters)
300	300	MCFG_SCREEN_PALETTE("palette")
301
	301
302	302	MCFG_PALETTE_ADD("palette", 1024)
303	303	MCFG_PALETTE_ENABLE_SHADOWS()
304	304	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)

trunk/src/mame/drivers/megaplay.c
r29404	r29405
70	70	m_vdp1(*this, "vdp1"),
71	71	m_bioscpu(*this, "mtbios")
72	72	{ }
73
	73
74	74	DECLARE_READ16_MEMBER(extra_ram_r);
75	75	DECLARE_WRITE16_MEMBER(extra_ram_w);
76	76	DECLARE_READ8_MEMBER(bios_banksel_r);
r29404	r29405
92	92	DECLARE_WRITE8_MEMBER(game_w);
93	93	DECLARE_READ8_MEMBER(vdp_count_r);
94	94	DECLARE_WRITE_LINE_MEMBER(bios_int_callback);
95
	95
96	96	DECLARE_DRIVER_INIT(megaplay);
97	97	DECLARE_VIDEO_START(megplay);
98	98	DECLARE_MACHINE_RESET(megaplay);
99	99	UINT32 screen_update_megplay(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
100
	100
101	101	private:
102
	102
103	103	UINT32 m_bios_mode; // determines whether ROM banks or Game data is to read from 0x8000-0xffff
104
	104
105	105	UINT32 m_bios_bank; // ROM bank selection
106	106	UINT16 m_game_banksel; // Game bank selection
107	107	UINT32 m_readpos; // serial bank selection position (9-bit)
108	108	UINT32 m_bios_bank_addr;
109
	109
110	110	UINT32 m_bios_width; // determines the way the game info ROM is read
111	111	UINT8 m_bios_ctrl[6];
112	112	UINT8 m_bios_6600;
113	113	UINT8 m_bios_6403;
114	114	UINT8 m_bios_6404;
115
	115
116	116	UINT16 *m_ic36_ram;
117	117	UINT8* m_ic37_ram;
118
	118
119	119	required_shared_ptr<UINT8> m_ic3_ram;
120	120	optional_device<sega315_5124_device> m_vdp1;
121	121	required_device<cpu_device> m_bioscpu;
r29404	r29405
616	616	{
617	617	//printf("megplay vu\n");
618	618	screen_update_megadriv(screen, bitmap, cliprect);
619		// m_vdp->screen_update(screen, bitmap, cliprect);
	619	// m_vdp->screen_update(screen, bitmap, cliprect);
620	620
621	621	// overlay, only drawn for pixels != 0
622	622	for (int y = 0; y < 224; y++)
623	623	{
624	624	UINT32* lineptr = &bitmap.pix32(y);
625	625	UINT32* srcptr = &m_vdp->get_bitmap().pix32(y + SEGA315_5124_TBORDER_START + SEGA315_5124_NTSC_224_TBORDER_HEIGHT);
626
	626
627	627	for (int x = 0; x < SEGA315_5124_WIDTH; x++)
628	628	{
629	629	UINT32 src = srcptr[x] & 0xffffff;
630
	630
631	631	if (src)
632	632	lineptr[x] = src;
633	633	}
634		}
	634	}
635	635	return 0;
636	636	}
637	637
r29404	r29405
855	855
856	856	DRIVER_INIT_MEMBER(mplay_state,megaplay)
857	857	{
858		// copy game instruction rom to main map. maybe this should just be accessed
	858	// copy game instruction rom to main map. maybe this should just be accessed
859	859	// through a handler instead?
860	860	UINT8 *instruction_rom = memregion("user1")->base();
861	861	UINT8 *game_rom = memregion("maincpu")->base();
862
	862
863	863	for (int offs = 0; offs < 0x8000; offs++)
864	864	{
865	865	UINT8 dat = instruction_rom[offs];
866
	866
867	867	game_rom[0x300000 + offs * 2] = dat;
868	868	game_rom[0x300001 + offs * 2] = dat;
869	869	}
r29404	r29405
875	875	DRIVER_INIT_CALL(megadrij);
876	876	m_megadrive_io_read_data_port_ptr = read8_delegate(FUNC(md_base_state::megadrive_io_read_data_port_3button),this);
877	877	m_megadrive_io_write_data_port_ptr = write16_delegate(FUNC(md_base_state::megadrive_io_write_data_port_3button),this);
878
	878
879	879	// for now ...
880	880	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xa10000, 0xa1001f, read16_delegate(FUNC(mplay_state::mp_io_read),this), write16_delegate(FUNC(mplay_state::mp_io_write),this));
881	881

trunk/src/mame/drivers/ohmygod.c
r29404	r29405
332	332	MCFG_SCREEN_PALETTE("palette")
333	333
334	334	MCFG_GFXDECODE_ADD("gfxdecode", "palette", ohmygod)
335
	335
336	336	MCFG_PALETTE_ADD("palette", 1024)
337	337	MCFG_PALETTE_FORMAT(xGGGGGRRRRRBBBBB)
338	338

trunk/src/mame/drivers/jclub2.c
r29404	r29405
293	293	***************************************************************************/
294	294
295	295
296		WRITE32_MEMBER(darkhors_state::jclub2o_eeprom_w) //seiko s-2929 is used on old style pcb
	296	WRITE32_MEMBER(darkhors_state::jclub2o_eeprom_w) //seiko s-2929 is used on old style pcb
297	297	{
298	298	if (data & ~0xff000000)
299	299	logerror("%s: Unknown EEPROM bit written %08X\n",machine().describe_context(),data);
300
	300
301	301	if ( ACCESSING_BITS_24_31 )
302	302	{
303
304	303	// latch the bit
305	304	m_eeprom->di_write((data & 0x01000000) >> 24);
306	305
r29404	r29405
355	354
356	355	READ32_MEMBER(darkhors_state::darkhors_input_sel_r)
357	356	{
358
359	357	// from bit mask to bit number
360	358	int bit_p1 = mask_to_bit((m_input_sel & 0x00ff0000) >> 16);
361	359	int bit_p2 = mask_to_bit((m_input_sel & 0xff000000) >> 24);
r29404	r29405
371	369	{
372	370	UINT32 ret = ioport("580004")->read()& 0x00ffffff;
373	371	switch (m_input_sel_jc_2p){
374
375	372	case 0x01: return ret \| (ioport("580004-01")->read()<<24);
376	373	case 0x02: return ret \| (ioport("580004-02")->read()<<24);
377	374	case 0x04: return ret \| (ioport("580004-04")->read()<<24);
r29404	r29405
381	378	case 0x40: return ret \| (ioport("580004-40")->read()<<24);
382	379	case 0x80: return ret \| (ioport("580004-80")->read()<<24);
383	380	}
384
	381
385	382	return ret;
386	383	}
387	384
r29404	r29405
390	387	{
391	388	UINT32 ret = ioport("4E0000")->read()& 0x00ffffff;
392	389	switch (m_input_sel_jc_2p){
393
394	390	case 0x01: return ret \| (ioport("4E0000-01")->read()<<24);
395	391	case 0x02: return ret \| (ioport("4E0000-02")->read()<<24);
396	392	case 0x04: return ret \| (ioport("4E0000-04")->read()<<24);
r29404	r29405
456	452
457	453	static ADDRESS_MAP_START( jclub2_map, AS_PROGRAM, 32, darkhors_state )
458	454	AM_RANGE(0x000000, 0x1fffff) AM_ROM
459		AM_RANGE(0x400000, 0x41ffff) AM_RAM AM_SHARE("nvram") //all 68k ram is battery backup
	455	AM_RANGE(0x400000, 0x41ffff) AM_RAM AM_SHARE("nvram") //all 68k ram is battery backup
460	456	//AM_RANGE(0x400000, 0x41ffff) AM_RAM
461	457
462	458	AM_RANGE(0x490000, 0x490003) AM_WRITE(darkhors_eeprom_w)
463		AM_RANGE(0x4E0000, 0x4E0003) AM_READ(p_4e0000) //input 2p
	459	AM_RANGE(0x4E0000, 0x4E0003) AM_READ(p_4e0000) //input 2p
464	460	AM_RANGE(0x4E0000, 0x4E0003) AM_WRITE(jclub2_input_sel_w_p1)
465		AM_RANGE(0x580000, 0x580003) AM_READ_PORT("580000") //eeprom related?
466		AM_RANGE(0x580004, 0x580007) AM_READ(p_580004) //system + some 1p input here
467		AM_RANGE(0x580008, 0x58000b) AM_READ_PORT("580008") //input 1p + coins
	461	AM_RANGE(0x580000, 0x580003) AM_READ_PORT("580000") //eeprom related?
	462	AM_RANGE(0x580004, 0x580007) AM_READ(p_580004) //system + some 1p input here
	463	AM_RANGE(0x580008, 0x58000b) AM_READ_PORT("580008") //input 1p + coins
468	464	AM_RANGE(0x58000c, 0x58000f) AM_WRITE(jclub2_input_sel_w_p2)
469		AM_RANGE(0x580200, 0x580203) AM_READNOP //????
	465	AM_RANGE(0x580200, 0x580203) AM_READNOP //????
470	466
471	467	AM_RANGE(0x800000, 0x87ffff) AM_DEVREADWRITE16( "st0020_spr", st0020_device, st0020_sprram_r, st0020_sprram_w, 0xffffffff );
472	468
473	469	AM_RANGE(0x880000, 0x89ffff) AM_RAM AM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
474	470	AM_RANGE(0x8a0000, 0x8bffff) AM_RAM // this should still be palette ram!
475	471
476		// AM_RANGE(0x8C0000, 0x8C00ff) AM_DEVREADWRITE16( "st0020_spr", st0020_device, st0020_blitram_r, st0020_blitram_w, 0xffffffff );
	472	// AM_RANGE(0x8C0000, 0x8C00ff) AM_DEVREADWRITE16( "st0020_spr", st0020_device, st0020_blitram_r, st0020_blitram_w, 0xffffffff );
477	473	AM_RANGE(0x8E0000, 0x8E01ff) AM_RAM
478	474
479	475	AM_RANGE(0x900000, 0x9fffff) AM_DEVREADWRITE16( "st0020_spr", st0020_device, st0020_gfxram_r, st0020_gfxram_w, 0xffffffff );
r29404	r29405
483	479
484	480
485	481	static ADDRESS_MAP_START( jclub2o_map, AS_PROGRAM, 32, darkhors_state )
486
	482
487	483	AM_RANGE(0x000000, 0x1fffff) AM_ROM
488		AM_RANGE(0x400000, 0x41ffff) AM_RAM AM_SHARE("nvram") //all 68k ram is battery backup
	484	AM_RANGE(0x400000, 0x41ffff) AM_RAM AM_SHARE("nvram") //all 68k ram is battery backup
489	485	//AM_RANGE(0x400000, 0x41ffff) AM_RAM
490
491		AM_RANGE(0x490000, 0x490003) AM_WRITE(jclub2o_eeprom_w) //eeprom s2929 not 93c46
492		AM_RANGE(0x4E0000, 0x4E0003) AM_READ(p_4e0000) //input 2p
	486
	487	AM_RANGE(0x490000, 0x490003) AM_WRITE(jclub2o_eeprom_w) //eeprom s2929 not 93c46
	488	AM_RANGE(0x4E0000, 0x4E0003) AM_READ(p_4e0000) //input 2p
493	489	AM_RANGE(0x4E0000, 0x4E0003) AM_WRITE(jclub2_input_sel_w_p1)
494		AM_RANGE(0x580000, 0x580003) AM_READ_PORT("580000") //eeprom read
495		AM_RANGE(0x580004, 0x580007) AM_READ(p_580004) //system + some 1p keyboard input here
496		AM_RANGE(0x580008, 0x58000b) AM_READ_PORT("580008") //input 1p + coins
	490	AM_RANGE(0x580000, 0x580003) AM_READ_PORT("580000") //eeprom read
	491	AM_RANGE(0x580004, 0x580007) AM_READ(p_580004) //system + some 1p keyboard input here
	492	AM_RANGE(0x580008, 0x58000b) AM_READ_PORT("580008") //input 1p + coins
497	493	AM_RANGE(0x58000c, 0x58000f) AM_WRITE(jclub2_input_sel_w_p2)
498
499		AM_RANGE(0x580200, 0x580203) AM_READNOP //????
500	494
	495	AM_RANGE(0x580200, 0x580203) AM_READNOP //????
	496
501	497	AM_RANGE(0x600000, 0x67ffff) AM_DEVREADWRITE16( "st0020_spr", st0020_device, st0020_sprram_r, st0020_sprram_w, 0xffffffff );
502	498	AM_RANGE(0x680000, 0x69ffff) AM_RAM AM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
503	499	AM_RANGE(0x6a0000, 0x6bffff) AM_RAM
r29404	r29405
722	718
723	719	static INPUT_PORTS_START( jclub2 )
724	720
725
	721
726	722	PORT_START("580000")
727	723	PORT_BIT( 0x7fffffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
728	724	PORT_BIT( 0x80000000, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_93cxx_device, do_read)
729	725
730	726	PORT_START("580008")
731	727	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
732		PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Payout") PORT_CODE(KEYCODE_LCONTROL) // payout 1p
	728	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Payout") PORT_CODE(KEYCODE_LCONTROL) // payout 1p
733	729	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
734	730	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
735		PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_START1 ) // start 1p
	731	PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_START1 ) // start 1p
736	732	PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
737	733	PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
738		PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 coin out") PORT_CODE(KEYCODE_RSHIFT) //coin out 2p
739		PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 coin out") PORT_CODE(KEYCODE_LSHIFT) //coin out 1p
	734	PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 coin out") PORT_CODE(KEYCODE_RSHIFT) //coin out 2p
	735	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 coin out") PORT_CODE(KEYCODE_LSHIFT) //coin out 1p
740	736	PORT_BIT( 0x01000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
741	737	PORT_BIT( 0x02000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
742		PORT_BIT( 0x04000000, IP_ACTIVE_LOW, IPT_COIN1 ) //1p coin drop
743		PORT_BIT( 0x08000000, IP_ACTIVE_LOW, IPT_COIN3 ) //2p coin drop
744		PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_COIN1 ) //1p coin in s1
745		PORT_BIT( 0x20000000, IP_ACTIVE_LOW, IPT_COIN2 ) //1p coin in s2
746		PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_COIN3 ) //2p coin in s1
747		PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_COIN4 ) //2p coin in s2
	738	PORT_BIT( 0x04000000, IP_ACTIVE_LOW, IPT_COIN1 ) //1p coin drop
	739	PORT_BIT( 0x08000000, IP_ACTIVE_LOW, IPT_COIN3 ) //2p coin drop
	740	PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_COIN1 ) //1p coin in s1
	741	PORT_BIT( 0x20000000, IP_ACTIVE_LOW, IPT_COIN2 ) //1p coin in s2
	742	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_COIN3 ) //2p coin in s1
	743	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_COIN4 ) //2p coin in s2
748	744
749	745	PORT_START("580004")
750	746	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
751		PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_SERVICE2 ) //reset
752		PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_SERVICE3 ) //meter
753		PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_SERVICE4 ) //last game
	747	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_SERVICE2 ) //reset
	748	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_SERVICE3 ) //meter
	749	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_SERVICE4 ) //last game
754	750	PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Cancel") PORT_CODE(KEYCODE_LALT) // cancel 1p
755		PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) //test
	751	PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) //test
756	752	PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
757		PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 hopper full") PORT_CODE(KEYCODE_CLOSEBRACE) //hopper full 2p
758		PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 hopper full") PORT_CODE(KEYCODE_OPENBRACE) //hopper full 1p
759		PORT_BIT( 0x01000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
760		PORT_BIT( 0x02000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
761		PORT_BIT( 0x04000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
762		PORT_BIT( 0x08000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
763		PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
764		PORT_BIT( 0x20000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
765		PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
766		PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
767
768		PORT_START("580004-01") //1P
	753	PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 hopper full") PORT_CODE(KEYCODE_CLOSEBRACE) //hopper full 2p
	754	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 hopper full") PORT_CODE(KEYCODE_OPENBRACE) //hopper full 1p
	755	PORT_BIT( 0x01000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
	756	PORT_BIT( 0x02000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
	757	PORT_BIT( 0x04000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
	758	PORT_BIT( 0x08000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
	759	PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
	760	PORT_BIT( 0x20000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
	761	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
	762	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 1p
	763
	764	PORT_START("580004-01") //1P
769	765	PORT_BIT( 0x00, IP_ACTIVE_LOW, IPT_UNKNOWN )
770	766	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 1") PORT_CODE(KEYCODE_1_PAD)
771	767	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 2") PORT_CODE(KEYCODE_2_PAD)
r29404	r29405
776	772	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 7") PORT_CODE(KEYCODE_7_PAD)
777	773	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 8") PORT_CODE(KEYCODE_8_PAD)
778	774
779		PORT_START("580004-02") //1P
	775	PORT_START("580004-02") //1P
780	776	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
781	777	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 1-2") PORT_CODE(KEYCODE_Q)
782	778	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 1-3") PORT_CODE(KEYCODE_W)
r29404	r29405
785	781	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 1-6") PORT_CODE(KEYCODE_T)
786	782	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 1-7") PORT_CODE(KEYCODE_Y)
787	783	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 1-8") PORT_CODE(KEYCODE_U)
788
789	784
790		PORT_START("580004-04") //1P
	785
	786	PORT_START("580004-04") //1P
791	787	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNKNOWN )
792	788	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 2-3") PORT_CODE(KEYCODE_I)
793	789	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 2-4") PORT_CODE(KEYCODE_O)
r29404	r29405
795	791	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 2-6") PORT_CODE(KEYCODE_S)
796	792	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 2-7") PORT_CODE(KEYCODE_D)
797	793	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 2-8") PORT_CODE(KEYCODE_F)
798
799		PORT_START("580004-08") //1P
	794
	795	PORT_START("580004-08") //1P
800	796	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNKNOWN )
801	797	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 3-4") PORT_CODE(KEYCODE_G)
802	798	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 3-5") PORT_CODE(KEYCODE_H)
r29404	r29405
804	800	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 3-7") PORT_CODE(KEYCODE_K)
805	801	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 3-8") PORT_CODE(KEYCODE_L)
806	802
807		PORT_START("580004-10") //1P
	803	PORT_START("580004-10") //1P
808	804	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )
809	805	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 4-5") PORT_CODE(KEYCODE_Z)
810	806	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 4-6") PORT_CODE(KEYCODE_X)
811	807	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 4-7") PORT_CODE(KEYCODE_C)
812	808	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 4-8") PORT_CODE(KEYCODE_V)
813	809
814
815		PORT_START("580004-20") //1P
	810
	811	PORT_START("580004-20") //1P
816	812	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
817	813	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 5-6") PORT_CODE(KEYCODE_B)
818	814	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 5-7") PORT_CODE(KEYCODE_N)
819	815	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 5-8") PORT_CODE(KEYCODE_M)
820	816
821
822		PORT_START("580004-40") //1P
823		PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNKNOWN )
	817
	818	PORT_START("580004-40") //1P
	819	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNKNOWN )
824	820	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 6-7") PORT_CODE(KEYCODE_COMMA)
825	821	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 6-8") PORT_CODE(KEYCODE_STOP)
826	822
827
828		PORT_START("580004-80") //1P
	823
	824	PORT_START("580004-80") //1P
829	825	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN )
830	826	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 7-8") PORT_CODE(KEYCODE_SLASH)
831	827
832	828
833	829	PORT_START("4E0000") // 4E0000
834	830	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
835		PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Payout") PORT_CODE(KEYCODE_RCONTROL) // payout 2p
	831	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Payout") PORT_CODE(KEYCODE_RCONTROL) // payout 2p
836	832	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
837	833	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
838		PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_START2 ) // start 2p
	834	PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_START2 ) // start 2p
839	835	PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
840	836	PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
841		PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Cancel") PORT_CODE(KEYCODE_RALT) // cancel 2p
	837	PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Cancel") PORT_CODE(KEYCODE_RALT) // cancel 2p
842	838	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //unused???
843		PORT_BIT( 0x01000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
844		PORT_BIT( 0x02000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
845		PORT_BIT( 0x04000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
846		PORT_BIT( 0x08000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
847		PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
848		PORT_BIT( 0x20000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
849		PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
850		PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
851
852		PORT_START("4E0000-01") //2P
	839	PORT_BIT( 0x01000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
	840	PORT_BIT( 0x02000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
	841	PORT_BIT( 0x04000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
	842	PORT_BIT( 0x08000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
	843	PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
	844	PORT_BIT( 0x20000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
	845	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
	846	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) //keyboard input 2p
	847
	848	PORT_START("4E0000-01") //2P
853	849	PORT_BIT( 0x00, IP_ACTIVE_LOW, IPT_UNKNOWN )
854	850	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 1") PORT_CODE(KEYCODE_1_PAD)
855	851	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 2") PORT_CODE(KEYCODE_2_PAD)
r29404	r29405
860	856	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 7") PORT_CODE(KEYCODE_7_PAD)
861	857	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 8") PORT_CODE(KEYCODE_8_PAD)
862	858
863		PORT_START("4E0000-02") //2P
	859	PORT_START("4E0000-02") //2P
864	860	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
865	861	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 1-2") PORT_CODE(KEYCODE_Q)
866	862	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 1-3") PORT_CODE(KEYCODE_W)
r29404	r29405
869	865	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 1-6") PORT_CODE(KEYCODE_T)
870	866	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 1-7") PORT_CODE(KEYCODE_Y)
871	867	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 1-8") PORT_CODE(KEYCODE_U)
872
873	868
874		PORT_START("4E0000-04") //2P
	869
	870	PORT_START("4E0000-04") //2P
875	871	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNKNOWN )
876	872	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 2-3") PORT_CODE(KEYCODE_I)
877	873	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 2-4") PORT_CODE(KEYCODE_O)
r29404	r29405
879	875	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 2-6") PORT_CODE(KEYCODE_S)
880	876	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 2-7") PORT_CODE(KEYCODE_D)
881	877	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 2-8") PORT_CODE(KEYCODE_F)
882
883		PORT_START("4E0000-08") //2P
	878
	879	PORT_START("4E0000-08") //2P
884	880	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNKNOWN )
885	881	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 3-4") PORT_CODE(KEYCODE_G)
886	882	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 3-5") PORT_CODE(KEYCODE_H)
r29404	r29405
888	884	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 3-7") PORT_CODE(KEYCODE_K)
889	885	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 3-8") PORT_CODE(KEYCODE_L)
890	886
891		PORT_START("4E0000-10") //2P
	887	PORT_START("4E0000-10") //2P
892	888	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )
893	889	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 4-5") PORT_CODE(KEYCODE_Z)
894	890	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 4-6") PORT_CODE(KEYCODE_X)
895	891	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 4-7") PORT_CODE(KEYCODE_C)
896	892	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 4-8") PORT_CODE(KEYCODE_V)
897	893
898
899		PORT_START("4E0000-20") //2P
	894
	895	PORT_START("4E0000-20") //2P
900	896	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
901	897	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 5-6") PORT_CODE(KEYCODE_B)
902	898	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 5-7") PORT_CODE(KEYCODE_N)
903	899	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 5-8") PORT_CODE(KEYCODE_M)
904
905		PORT_START("4E0000-40") //2P
	900
	901	PORT_START("4E0000-40") //2P
906	902	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNKNOWN )
907	903	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 6-7") PORT_CODE(KEYCODE_COMMA)
908	904	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 6-8") PORT_CODE(KEYCODE_STOP)
909
910		PORT_START("4E0000-80") //2P
	905
	906	PORT_START("4E0000-80") //2P
911	907	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN )
912	908	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 7-8") PORT_CODE(KEYCODE_SLASH)
913	909	INPUT_PORTS_END
r29404	r29405
1023	1019	MCFG_SCREEN_PALETTE("palette")
1024	1020
1025	1021	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1026
	1022
1027	1023	// NOT an ST0020 but instead ST0032, ram format isn't compatible at least
1028	1024	MCFG_DEVICE_ADD("st0020_spr", ST0020_SPRITES, 0)
1029	1025	st0020_device::set_is_st0032(*device, 1);
r29404	r29405
1085	1081	MCFG_CPU_VBLANK_INT_DRIVER("screen", darkhors_state, irq0_line_hold)
1086	1082
1087	1083	MCFG_NVRAM_ADD_0FILL("nvram")
1088		MCFG_EEPROM_SERIAL_93C56_ADD("eeprom") //not correct
1089
	1084	MCFG_EEPROM_SERIAL_93C56_ADD("eeprom") //not correct
	1085
1090	1086	/* video hardware */
1091	1087	MCFG_SCREEN_ADD("screen", RASTER)
1092	1088	MCFG_SCREEN_REFRESH_RATE(60)
r29404	r29405
1098	1094
1099	1095	MCFG_PALETTE_ADD("palette", 0x10000)
1100	1096	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
1101
	1097
1102	1098	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1103
	1099
1104	1100	MCFG_DEVICE_ADD("st0020_spr", ST0020_SPRITES, 0)
1105	1101	st0020_device::set_is_jclub2o(*device, 1);
1106	1102	MCFG_ST0020_SPRITES_GFXDECODE("gfxdecode")
r29404	r29405
1220	1216	ROM_REGION( 0x80000, "misc", ROMREGION_ERASEFF )
1221	1217	ROM_LOAD( "gal16v8b-m88-03.bin", 0x000, 0x117, CRC(6d9c882e) SHA1(84cb95ab540290c2f8b740668360e9c643a67dcf) )
1222	1218	ROM_LOAD( "gal16v8b-m88-04.bin", 0x000, 0x117, CRC(5e79f292) SHA1(5e44c234e2b15d486a1af71fee986892aa245b4d) )
1223
	1219
1224	1220	ROM_REGION( 0x80, "eeprom", 0 ) // EEPROM
1225	1221	ROM_LOAD( "eeprom-jclub2.bin", 0x0000, 0x0080, CRC(1513cdc8) SHA1(22ff752f3e0f8f611c234a1dc4327aa360b4d6eb) )
1226	1222	ROM_END
r29404	r29405
1271	1267
1272	1268	ROM_REGION( 0x80000, "st0016", 0 ) // z80 core (used for sound?)
1273	1269	ROM_LOAD( "sx006-04.u87", 0x00000, 0x80000, CRC(a87adedd) SHA1(1cd5af2d03738fff2230b46241659179467c828c) )
1274
	1270
1275	1271	ROM_REGION( 0x100, "eeprom", 0 ) // eeprom 16 bit one!!!
1276		ROM_LOAD( "eeprom-jclub2o.bin", 0x0000, 0x100, CRC(dd1c88ec) SHA1(acb67e41e832f203361e0f93afcd4eaf963fd13e) ) //jclub2ob ones
	1272	ROM_LOAD( "eeprom-jclub2o.bin", 0x0000, 0x100, CRC(dd1c88ec) SHA1(acb67e41e832f203361e0f93afcd4eaf963fd13e) ) //jclub2ob ones
1277	1273	ROM_END
1278	1274
1279	1275	/*
1280	1276	Jockey Club II (26-mar-1997)
1281	1277	8 Horses, old style PCB.
1282	1278	Maybe upgraded to a release candidate software revision.
1283		*/
	1279	*/
1284	1280	ROM_START( jclub2ob )
1285	1281	ROM_REGION( 0x200000, "maincpu", 0 ) // 68EC020 code + compressed gfx
1286	1282	ROM_LOAD16_WORD_SWAP( "sx006a-01.u26",0x00000, 0x200000, CRC(55e249bc) SHA1(ed0f066ed17f047760b712cbbfba1a62d4b452ba) )
r29404	r29405
1292	1288
1293	1289	ROM_REGION( 0x80000, "st0016", 0 ) // z80 core (used for sound?)
1294	1290	ROM_LOAD( "sx006-04.u87", 0x00000, 0x80000, CRC(a87adedd) SHA1(1cd5af2d03738fff2230b46241659179467c828c) )
1295
	1291
1296	1292	ROM_REGION( 0x100, "eeprom", 0 ) // eeprom 16 bit one!!!
1297	1293	ROM_LOAD( "eeprom-jclub2o.bin", 0x0000, 0x100, CRC(dd1c88ec) SHA1(acb67e41e832f203361e0f93afcd4eaf963fd13e) )
1298	1294	ROM_END
r29404	r29405
1325	1321	temp[i] = eeprom[BITSWAP8(i,7,5,4,3,2,1,0,6)];
1326	1322
1327	1323	memcpy(eeprom, temp, len);
1328
	1324
1329	1325	}
1330	1326	}
1331	1327
r29404	r29405
1336	1332	GAME( 2001, darkhors, jclub2, darkhors,darkhors,darkhors_state, darkhors,ROT0, "bootleg", "Dark Horse (bootleg of Jockey Club II)", GAME_IMPERFECT_GRAPHICS )
1337	1333
1338	1334
1339		//test boot = test mode
	1335	//test boot = test mode
1340	1336	//reset +start 1p at boot, when msg on screen press test without release other key = setup
1341	1337	//reset +cancel 1p = backup all clear
1342	1338	//reset, test, meter and last game are keys so once you turn them they stay "active"
r29404	r29405
1347	1343	- 0 + left alt (reset + p1 cancel) to clear data
1348	1344	- 0 + 1 + f1 (IIRC) to write ID
1349	1345	*/
1350

trunk/src/mame/drivers/zr107.c
r29404	r29405
776	776	MCFG_VIDEO_START_OVERRIDE(zr107_state,zr107)
777	777
778	778	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
779
	779
780	780	MCFG_K056832_ADD("k056832", zr107_k056832_intf)
781	781	MCFG_K056832_GFXDECODE("gfxdecode")
782	782	MCFG_K056832_PALETTE("palette")
r29404	r29405
840	840	MCFG_VIDEO_START_OVERRIDE(zr107_state,jetwave)
841	841
842	842	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
843
	843
844	844	MCFG_K001604_ADD("k001604", jetwave_k001604_intf)
845	845	MCFG_K001604_GFXDECODE("gfxdecode")
846	846	MCFG_K001604_PALETTE("palette")
r29404	r29405
1107	1107	GAME( 1996, jetwave, 0, jetwave, jetwave, zr107_state, jetwave, ROT0, "Konami", "Jet Wave (EAB, Euro v1.04)", GAME_IMPERFECT_GRAPHICS )
1108	1108	GAME( 1996, waveshrk, jetwave, jetwave, jetwave, zr107_state, jetwave, ROT0, "Konami", "Wave Shark (UAB, USA v1.04)", GAME_IMPERFECT_GRAPHICS )
1109	1109	GAME( 1996, jetwavej, jetwave, jetwave, jetwave, zr107_state, jetwave, ROT0, "Konami", "Jet Wave (JAB, Japan v1.04)", GAME_IMPERFECT_GRAPHICS )
1110

trunk/src/mame/drivers/dominob.c
r29404	r29405
139	139	{
140	140	for (x = 0; x < 256 / 32; x++)
141	141	{
142
143	142	m_gfxdecode->gfx(1)->opaque(bitmap,
144	143	cliprect,
145	144	m_bgram[index] + 256 * (m_bgram[index + 1] & 0xf),
r29404	r29405
154	153	{
155	154	for (x = 0; x < 32; x++)
156	155	{
157
158	156	m_gfxdecode->gfx(0)->transpen(bitmap,
159	157	cliprect,
160	158	m_videoram[(y * 32 + x) * 2 + 1] + (m_videoram[(y * 32 + x) * 2] & 7) * 256,

trunk/src/mame/drivers/fantland.c
r29404	r29405
996	996	MCFG_MSM5205_VCLK_CB(WRITELINE(fantland_state, borntofi_adpcm_int_0)) /* IRQ handler */
997	997	MCFG_MSM5205_PRESCALER_SELECTOR(MSM5205_S48_4B) /* 8 kHz, 4 Bits */
998	998	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
999
	999
1000	1000	MCFG_SOUND_ADD("msm2", MSM5205, 384000)
1001	1001	MCFG_MSM5205_VCLK_CB(WRITELINE(fantland_state, borntofi_adpcm_int_1)) /* IRQ handler */
1002	1002	MCFG_MSM5205_PRESCALER_SELECTOR(MSM5205_S48_4B) /* 8 kHz, 4 Bits */

trunk/src/mame/drivers/albazc.c
r29404	r29405
288	288	MCFG_SCREEN_PALETTE("palette")
289	289
290	290	MCFG_GFXDECODE_ADD("gfxdecode", "palette", hanaroku)
291
	291
292	292	MCFG_PALETTE_ADD("palette", 0x200)
293	293	MCFG_PALETTE_INIT_OWNER(albazc_state, albazc)
294	294

trunk/src/mame/drivers/aristmk4.c
r29404	r29405
17	17	* Press PB4, PB5 and PB6 keys simultaneously (Z+X+C keys by default)
18	18	* A value (displayed below) will appear next to RF/AMT on the right of the screen
19	19	* Key out both the Jackpot and Audit Keys
20
21	20
	21
22	22	This method works with the following games:
23	23	3bagflnz 200
24	24	3bagflvt 200
r29404	r29405
68	68	eforest
69	69	fhunter
70	70	fhuntera
71
	71
72	72	Technical Notes:
73	73
74	74	68B09EP Motorola Processor
r29404	r29405
303	303	required_device<ay8910_device> m_ay1;
304	304	required_device<ay8910_device> m_ay2;
305	305	required_device<samples_device> m_samples;
306
	306
307	307	required_shared_ptr<UINT8> m_mkiv_vram;
308	308	required_device<gfxdecode_device> m_gfxdecode;
309	309	required_device<palette_device> m_palette;
310
	310
311	311	int m_rtc_address_strobe;
312	312	int m_rtc_data_strobe;
313	313	UINT8 *m_shapeRomPtr;
r29404	r29405
2381	2381	ROM_START( gunnrose ) // MK2.5
2382	2382	ROM_REGION(0x10000, "maincpu", 0 )
2383	2383	/* VIDEO AND SOUND EPROM */
2384		ROM_LOAD("gnr.u7", 0x06000, 0x2000, CRC(fe7d0ea4) SHA1(3F3F4809534065C33ECA2CFFF0D1D2A3E3992406)) // 1VL/SH136 RED AND BLACK
	2384	ROM_LOAD("gnr.u7", 0x06000, 0x2000, CRC(fe7d0ea4) SHA1(3F3F4809534065C33ECA2CFFF0D1D2A3E3992406)) // 1VL/SH136 RED AND BLACK
2385	2385
2386	2386	/* GAME EPROMS */
2387		ROM_LOAD("gnr.u9", 0x08000, 0x8000, CRC(4fb5f757) SHA1(A4129BCA7E573FAAC0D11DE41A9BF8EA144091EE)) // E/C606191SMP
	2387	ROM_LOAD("gnr.u9", 0x08000, 0x8000, CRC(4fb5f757) SHA1(A4129BCA7E573FAAC0D11DE41A9BF8EA144091EE)) // E/C606191SMP
2388	2388
2389	2389	/* SHAPE EPROMS */
2390	2390	ROM_REGION(0xc000, "tile_gfx", 0 )
2391		ROM_LOAD("gnr.u8", 0x00000, 0x2000, CRC(dec9e695) SHA1(A596C4243D6D39E0611FF714E19E14188C90B6F1)) // 1VL/SH136 RED AND BLACK
2392		ROM_LOAD("gnr.u10", 0x02000, 0x2000, CRC(e83b8e79) SHA1(595F41A5F59F938581A57B445370AA716C6B1409)) // 1VL/SH136 RED AND BLACK
2393		ROM_LOAD("gnr.u12", 0x04000, 0x2000, CRC(9134d029) SHA1(D698FB91D8F5FA78FFD056149421008D3F12C456)) // 1VL/SH136 RED AND BLACK
2394		ROM_LOAD("gnr.u9t", 0x06000, 0x2000, CRC(73a0c2cd) SHA1(662056D570EAA069483D378B77EFCFB42EFF6D0D)) // E/C606191SMP
2395		ROM_LOAD("gnr.u11", 0x08000, 0x2000, CRC(c50adffe) SHA1(A7C4A3CDD4D5D31A1420E47859408CAA75CE2636)) // 1VL/SH136 RED AND BLACK
2396		ROM_LOAD("gnr.u13", 0x0a000, 0x2000, CRC(e0a6bfc5) SHA1(07E4C8191503F0EA2DE4F7CE18FE6290D20EF80E)) // 1VL/SH136 RED AND BLACK
	2391	ROM_LOAD("gnr.u8", 0x00000, 0x2000, CRC(dec9e695) SHA1(A596C4243D6D39E0611FF714E19E14188C90B6F1)) // 1VL/SH136 RED AND BLACK
	2392	ROM_LOAD("gnr.u10", 0x02000, 0x2000, CRC(e83b8e79) SHA1(595F41A5F59F938581A57B445370AA716C6B1409)) // 1VL/SH136 RED AND BLACK
	2393	ROM_LOAD("gnr.u12", 0x04000, 0x2000, CRC(9134d029) SHA1(D698FB91D8F5FA78FFD056149421008D3F12C456)) // 1VL/SH136 RED AND BLACK
	2394	ROM_LOAD("gnr.u9t", 0x06000, 0x2000, CRC(73a0c2cd) SHA1(662056D570EAA069483D378B77EFCFB42EFF6D0D)) // E/C606191SMP
	2395	ROM_LOAD("gnr.u11", 0x08000, 0x2000, CRC(c50adffe) SHA1(A7C4A3CDD4D5D31A1420E47859408CAA75CE2636)) // 1VL/SH136 RED AND BLACK
	2396	ROM_LOAD("gnr.u13", 0x0a000, 0x2000, CRC(e0a6bfc5) SHA1(07E4C8191503F0EA2DE4F7CE18FE6290D20EF80E)) // 1VL/SH136 RED AND BLACK
2397	2397
2398	2398	/* COLOR PROM */
2399	2399	ROM_REGION(0x200, "proms", 0 ) /* are either of these correct? They are taken from different games */
2400	2400	//ROM_LOAD("2cm07.u71", 0x0000, 0x0200, CRC(1e3f402a) SHA1(f38da1ad6607df38add10c69febf7f5f8cd21744)) // Using 2CM07 until a correct PROM is confirmed
2401	2401	ROM_LOAD("1cm48.u71", 0x0000, 0x0200, BAD_DUMP CRC(81daeeb0) SHA1(7dfe198c6def5c4ae4ecac488d65c2911fb3a890))
2402
	2402
2403	2403	ROM_END
2404	2404
2405	2405	GAMEL( 1985, 86lions, 0, 86lions, aristmk4, aristmk4_state, aristmk4, ROT0, "Aristocrat", "86 Lions", GAME_NOT_WORKING, layout_topgear )

trunk/src/mame/drivers/mcr68.c
r29404	r29405
773	773	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
774	774	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
775	775	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
776		PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
	776	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
777	777	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
778	778	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
779	779	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
r29404	r29405
1511	1511
1512	1512	ROM_START( archrivlb ) /* Reports as rev 2.0 5/03/89 */
1513	1513	ROM_REGION( 0x40000, "maincpu", 0 )
1514		ROM_LOAD16_BYTE( "4.bin", 0x00000, 0x10000, CRC(1d99cce6) SHA1(738d651de0bf1b4a1524a1d8835a060bfc4649a8) )
	1514	ROM_LOAD16_BYTE( "4.bin", 0x00000, 0x10000, CRC(1d99cce6) SHA1(738d651de0bf1b4a1524a1d8835a060bfc4649a8) )
1515	1515	ROM_LOAD16_BYTE( "2.bin", 0x00001, 0x10000, CRC(5d58a77b) SHA1(9a42bb89acd4e6b603215b14b4d411d14615f412) )
1516	1516	ROM_LOAD16_BYTE( "3.bin", 0x20000, 0x10000, CRC(d6d08ff7) SHA1(bbbd4b5c3218c9bb461b17e536191d40ab39f67c) )
1517	1517	ROM_LOAD16_BYTE( "1.bin", 0x20001, 0x10000, CRC(92f3a43d) SHA1(45fdcbacd65f5898d54cc2ac95639b7ee2c097e6) )
1518	1518
1519	1519	ROM_REGION( 0x90000, "cvsd:cpu", 0 ) /* Audio System board */
1520		ROM_LOAD( "13.bin", 0x10000, 0x08000, CRC(96b3c652) SHA1(1bb576d0bf6b6b8df24e7b9352a33e97dd8ebdcb) )
	1520	ROM_LOAD( "13.bin", 0x10000, 0x08000, CRC(96b3c652) SHA1(1bb576d0bf6b6b8df24e7b9352a33e97dd8ebdcb) )
1521	1521	ROM_RELOAD( 0x18000, 0x08000 )
1522	1522	ROM_RELOAD( 0x20000, 0x08000 )
1523	1523	ROM_RELOAD( 0x28000, 0x08000 )
r29404	r29405
1531	1531	ROM_RELOAD( 0x68000, 0x08000 )
1532	1532
1533	1533	ROM_REGION( 0x20000, "gfx1", ROMREGION_INVERT )
1534		ROM_LOAD( "5.bin", 0x00000, 0x10000, CRC(7eb3d7c6) SHA1(8544d04929cdb36fa7f0dcb67e0b7fd8c7b0fc2b) )
	1534	ROM_LOAD( "5.bin", 0x00000, 0x10000, CRC(7eb3d7c6) SHA1(8544d04929cdb36fa7f0dcb67e0b7fd8c7b0fc2b) )
1535	1535	ROM_LOAD( "6.bin", 0x10000, 0x10000, CRC(31e68050) SHA1(e25871beb08a8706af70d277fa7305a1f4d7d3e2) )
1536	1536
1537	1537	ROM_REGION( 0x80000, "gfx2", 0 )

trunk/src/mame/drivers/thunderx.c
r29404	r29405
597	597	{
598	598	m_paletteram.resize(0x800);
599	599	m_palette->basemem().set(m_paletteram, ENDIANNESS_BIG, 2);
600
	600
601	601	save_item(NAME(m_paletteram));
602	602	save_item(NAME(m_priority));
603	603	save_item(NAME(m_1f98_data));

trunk/src/mame/drivers/galaxi.c
r29404	r29405
103	103	required_device<cpu_device> m_maincpu;
104	104	required_device<gfxdecode_device> m_gfxdecode;
105	105	required_device<screen_device> m_screen;
106		required_device<palette_device> m_palette;
	106	required_device<palette_device> m_palette;
107	107	};
108	108
109	109

trunk/src/mame/drivers/tecmo16.c
r29404	r29405
382	382	MCFG_SCREEN_UPDATE_DRIVER(tecmo16_state, screen_update_tecmo16)
383	383
384	384	MCFG_GFXDECODE_ADD("gfxdecode", "palette", tecmo16)
385		MCFG_PALETTE_ADD_INIT_BLACK("palette", 4096)
	385	MCFG_PALETTE_ADD_INIT_BLACK("palette", 4096)
386	386	MCFG_PALETTE_FORMAT(xxxxBBBBGGGGRRRR)
387	387
388	388

trunk/src/mame/drivers/murogmbl.c
r29404	r29405
114	114	for (x = 0; x < 32; x++)
115	115	{
116	116	int tile = m_video[count];
117		gfx->opaque(bitmap,cliprect, tile, 0, 0, 0, x * 8, y * 8);
	117	gfx->opaque(bitmap,cliprect, tile, 0, 0, 0, x * 8, y * 8);
118	118
119	119	count++;
120	120	}

trunk/src/mame/drivers/amusco.c
r29404	r29405
24	24	1x MOS 6845 (U27) CRT Controller.
25	25	2x P8255 Programmable Peripheral Interface (I/O).
26	26
27		2x SRM2264 8k X 8 CMOS Static RAM.
	27	2x SRM2264 8k X 8 CMOS Static RAM.
28	28
29		1x 27128 (U35) ROM. Handwritten sticker: Char A U35.
30		1x 27128 (U36) ROM. Handwritten sticker: Char B U36.
31		1x 27128 (U37) ROM. Handwritten sticker: Char C U37.
32		1x 27256 (U42) ROM. Handwritten sticker: PK V1.4 U42.
	29	1x 27128 (U35) ROM. Handwritten sticker: Char A U35.
	30	1x 27128 (U36) ROM. Handwritten sticker: Char B U36.
	31	1x 27128 (U37) ROM. Handwritten sticker: Char C U37.
	32	1x 27256 (U42) ROM. Handwritten sticker: PK V1.4 U42.
33	33
34		1x TI SN76489 Digital Complex Sound Generator (DCSG).
	34	1x TI SN76489 Digital Complex Sound Generator (DCSG).
35	35
36	36	3x MMI PAL16L8ACN (U47, U48, U50)
37	37	1x MMI PAL16R4 (U49) <-- couldn't get a consistent read
r29404	r29405
62	62	*******************************************************************************/
63	63
64	64
65		#define MASTER_CLOCK XTAL_22_1184MHz /* confirmed */
66		#define SECOND_CLOCK XTAL_15MHz /* confirmed */
	65	#define MASTER_CLOCK XTAL_22_1184MHz /* confirmed */
	66	#define SECOND_CLOCK XTAL_15MHz /* confirmed */
67	67
68		#define CPU_CLOCK MASTER_CLOCK / 4 /* guess */
69		#define CRTC_CLOCK SECOND_CLOCK / 8 /* guess */
70		#define SND_CLOCK SECOND_CLOCK / 8 /* guess */
	68	#define CPU_CLOCK MASTER_CLOCK / 4 /* guess */
	69	#define CRTC_CLOCK SECOND_CLOCK / 8 /* guess */
	70	#define SND_CLOCK SECOND_CLOCK / 8 /* guess */
71	71
72	72
73	73	#include "emu.h"
r29404	r29405
120	120
121	121	WRITE16_MEMBER(amusco_state::amusco_videoram_w)
122	122	{
123
124	123	}
125	124
126	125	PALETTE_INIT_MEMBER(amusco_state, amusco_palette_init)
r29404	r29405
180	179
181	180	static ADDRESS_MAP_START( amusco_mem_map, AS_PROGRAM, 16, amusco_state )
182	181	AM_RANGE(0x00000, 0x0ffff) AM_RAM
183		AM_RANGE(0xec000, 0xecfff) AM_RAM AM_SHARE("videoram") // placeholder
	182	AM_RANGE(0xec000, 0xecfff) AM_RAM AM_SHARE("videoram") // placeholder
184	183	AM_RANGE(0xf8000, 0xfffff) AM_ROM
185	184	ADDRESS_MAP_END
186	185
r29404	r29405
213	212	{
214	213	m_videoram[m_video_update_address] = data;
215	214	m_bg_tilemap->mark_tile_dirty(m_video_update_address);
216		// printf("%04x %04x\n",m_video_update_address,data);
	215	// printf("%04x %04x\n",m_video_update_address,data);
217	216	}
218	217
219	218	static ADDRESS_MAP_START( amusco_io_map, AS_IO, 16, amusco_state )
220	219	AM_RANGE(0x0000, 0x0001) AM_READWRITE8(mc6845_r, mc6845_w, 0xffff)
221		// AM_RANGE(0x0000, 0x0001) AM_DEVREADWRITE8("crtc", mc6845_device, status_r, address_w, 0x00ff)
222		// AM_RANGE(0x0000, 0x0001) AM_DEVREADWRITE8("crtc", mc6845_device, register_r, register_w, 0xff00)
	220	// AM_RANGE(0x0000, 0x0001) AM_DEVREADWRITE8("crtc", mc6845_device, status_r, address_w, 0x00ff)
	221	// AM_RANGE(0x0000, 0x0001) AM_DEVREADWRITE8("crtc", mc6845_device, register_r, register_w, 0xff00)
223	222	AM_RANGE(0x0010, 0x0011) AM_DEVREADWRITE8("pic8259", pic8259_device, read, write, 0xffff ) //PPI 8255
224	223
225		AM_RANGE(0x0060, 0x0061) AM_DEVWRITE8("sn", sn76489_device, write, 0x00ff) /* sound */
	224	AM_RANGE(0x0060, 0x0061) AM_DEVWRITE8("sn", sn76489_device, write, 0x00ff) /* sound */
226	225	AM_RANGE(0x0070, 0x0071) AM_WRITE(vram_w)
227		// AM_RANGE(0x0010, 0x0011) AM_READ_PORT("IN1")
228		// AM_RANGE(0x0012, 0x0013) AM_READ_PORT("IN3")
	226	// AM_RANGE(0x0010, 0x0011) AM_READ_PORT("IN1")
	227	// AM_RANGE(0x0012, 0x0013) AM_READ_PORT("IN3")
229	228	AM_RANGE(0x0030, 0x0031) AM_READ_PORT("DSW1") AM_WRITENOP // lamps?
230	229	AM_RANGE(0x0040, 0x0041) AM_READ_PORT("DSW2")
231	230	ADDRESS_MAP_END
r29404	r29405
485	484
486	485	MC6845_ON_UPDATE_ADDR_CHANGED(crtc_addr)
487	486	{
488		// amusco_state *state = device->machine().driver_data<amusco_state>();
489		// state->m_video_update_address = address;
	487	// amusco_state *state = device->machine().driver_data<amusco_state>();
	488	// state->m_video_update_address = address;
490	489	}
491	490
492	491	static MC6845_INTERFACE( mc6845_intf )
r29404	r29405
537	536	MCFG_SCREEN_ADD("screen", RASTER)
538	537	MCFG_SCREEN_REFRESH_RATE(60)
539	538	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
540		MCFG_SCREEN_SIZE(888, 2710) // screen size: 888 2710
541		MCFG_SCREEN_VISIBLE_AREA(08, 748-1, 010, 2410-1) // visible scr: 748 2410
	539	MCFG_SCREEN_SIZE(888, 2710) // screen size: 888 2710
	540	MCFG_SCREEN_VISIBLE_AREA(08, 748-1, 010, 2410-1) // visible scr: 748 2410
542	541	MCFG_SCREEN_UPDATE_DRIVER(amusco_state, screen_update_amusco)
543	542
544	543	MCFG_SCREEN_PALETTE("palette")
r29404	r29405
568	567	ROM_LOAD( "char_a_u35.u35", 0x0000, 0x4000, CRC(ded67ef6) SHA1(da7326c190211e956e5a5f763d5045615bb8ffb3) )
569	568	ROM_LOAD( "char_b_u36.u36", 0x4000, 0x4000, CRC(55523513) SHA1(97fd221c298698628d4f6564389d96eb89e55927) )
570	569	ROM_LOAD( "char_c_u37.u37", 0x8000, 0x4000, CRC(d26f3b94) SHA1(e58af4f6f1a9091c23827997d03b91f02bb07856) )
571		// ROM_LOAD( "char_a_u35.u35", 0x8000, 0x4000, CRC(ded67ef6) SHA1(da7326c190211e956e5a5f763d5045615bb8ffb3) )
572		// ROM_LOAD( "char_b_u36.u36", 0x4000, 0x4000, CRC(55523513) SHA1(97fd221c298698628d4f6564389d96eb89e55927) )
573		// ROM_LOAD( "char_c_u37.u37", 0x0000, 0x4000, CRC(d26f3b94) SHA1(e58af4f6f1a9091c23827997d03b91f02bb07856) )
	570	// ROM_LOAD( "char_a_u35.u35", 0x8000, 0x4000, CRC(ded67ef6) SHA1(da7326c190211e956e5a5f763d5045615bb8ffb3) )
	571	// ROM_LOAD( "char_b_u36.u36", 0x4000, 0x4000, CRC(55523513) SHA1(97fd221c298698628d4f6564389d96eb89e55927) )
	572	// ROM_LOAD( "char_c_u37.u37", 0x0000, 0x4000, CRC(d26f3b94) SHA1(e58af4f6f1a9091c23827997d03b91f02bb07856) )
574	573
575	574	ROM_REGION( 0x0800, "plds", 0 )
576	575	ROM_LOAD( "pal16l8a.u47", 0x0000, 0x0104, CRC(554b4286) SHA1(26bc991f2cc58644cd2d9ce5c1867a94455b95a8) )

trunk/src/mame/drivers/toypop.c
r29404	r29405
532	532	MCFG_NAMCO58XX_IN_1_CB(IOPORT("P1_RIGHT"))
533	533	MCFG_NAMCO58XX_IN_2_CB(IOPORT("P2_RIGHT"))
534	534	MCFG_NAMCO58XX_IN_3_CB(IOPORT("BUTTONS"))
535
	535
536	536	MCFG_DEVICE_ADD("56xx_1", NAMCO56XX, 0)
537	537	MCFG_NAMCO56XX_IN_0_CB(READ8(toypop_state, dipA_h))
538	538	MCFG_NAMCO56XX_IN_1_CB(READ8(toypop_state, dipB_l))
539	539	MCFG_NAMCO56XX_IN_2_CB(READ8(toypop_state, dipB_h))
540	540	MCFG_NAMCO56XX_IN_3_CB(READ8(toypop_state, dipA_l))
541	541	MCFG_NAMCO56XX_OUT_0_CB(WRITE8(toypop_state, flip))
542
	542
543	543	MCFG_DEVICE_ADD("56xx_2", NAMCO56XX, 0)
544	544	MCFG_NAMCO56XX_IN_1_CB(IOPORT("P1_LEFT"))
545	545	MCFG_NAMCO56XX_IN_2_CB(IOPORT("P2_LEFT"))
546	546	MCFG_NAMCO56XX_IN_3_CB(IOPORT("SERVICE"))
547
	547
548	548	/* video hardware */
549	549	MCFG_SCREEN_ADD("screen", RASTER)
550	550	MCFG_SCREEN_REFRESH_RATE(60.606060)

trunk/src/mame/drivers/cd32.c
r29404	r29405
864	864	Harem Challenge \| \| 1995
865	865	Laser Quiz \| \| 1995
866	866	Laser Quiz 2 "Italy" \| 1.0 \| 1995
867		Laser Strixx \| \| 1995
	867	Laser Strixx \| \| 1995
868	868	Laser Strixx 2 \| \| 1995
869	869	Magic Premium \| 1.1 \| 1996
870	870	Laser Quiz France \| 1.0 \| 1995

trunk/src/mame/drivers/olibochu.c
r29404	r29405
200	200	flipy = !flipy;
201	201	}
202	202
203
	203
204	204	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
205	205	code, color,
206	206	flipx, flipy,
r29404	r29405
226	226	flipy = !flipy;
227	227	}
228	228
229
	229
230	230	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect,
231	231	code, color,
232	232	flipx, flipy,

trunk/src/mame/drivers/taitogn.c
r29404	r29405
81	81	CAT702 - Protection chip labelled 'TT10' (DIP20)
82	82	* - Unpopulated position for additional KM416V1204BT-L5 RAMs
83	83	NEC_78081G503 - NEC uPD78081 MCU, 5MHz
84
	84
85	85	Video syncs are 59.8260Hz and 15.4333kHz
86	86
87	87
r29404	r29405
420	420	{
421	421	// 20 = watchdog
422	422	m_mb3773->write_line_ck((data & 0x20) >> 5);
423
	423
424	424	// 10 = sound hw reset, but make sure it's only booted on games that use it
425	425	if (m_has_zoom)
426	426	{
r29404	r29405
429	429	if (~data & m_control & 0x10)
430	430	{
431	431	logerror("control_w Zoom reset\n");
432
	432
433	433	m_zoom->reset();
434	434
435	435	// assume that this also readys the sound flash chips
r29404	r29405
489	489	m_v = m_v ^ 8;
490	490	// Probably something to do with MCU
491	491	return m_v;
492
	492
493	493	default:
494	494	break;
495	495	}
r29404	r29405
550	550	case 0x08: return ioport("KEY1")->read();
551	551	case 0x40: return ioport("KEY2")->read();
552	552	case 0x80: return ioport("KEY3")->read();
553
	553
554	554	default:
555	555	break;
556	556	}
r29404	r29405
587	587	{
588	588	// halt sound CPU since it has no valid program at start
589	589	m_mn10200->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
590
	590
591	591	m_control = 0x10;
592	592	}
593	593
r29404	r29405
661	661	MCFG_DEVICE_ADD("maincpu:sio0:znsec1", ZNSEC, 0)
662	662	MCFG_DEVICE_ADD("maincpu:sio0:zndip", ZNDIP, 0)
663	663	MCFG_ZNDIP_DATA_HANDLER(IOPORT(":DSW"))
664
	664
665	665	MCFG_AT28C16_ADD( "at28c16", 0 )
666	666	MCFG_DEVICE_ADD("rf5c296", RF5C296, 0)
667	667	MCFG_RF5C296_SLOT(":pccard")

trunk/src/mame/drivers/r2dx_v33.c
r29404	r29405
743	743	MCFG_SCREEN_VISIBLE_AREA(08, 408-1, 0, 32*8-1)
744	744	MCFG_SCREEN_UPDATE_DRIVER(r2dx_v33_state, screen_update_rdx_v33)
745	745	MCFG_SCREEN_PALETTE("palette")
746
	746
747	747	MCFG_GFXDECODE_ADD("gfxdecode", "palette", rdx_v33)
748	748	MCFG_PALETTE_ADD("palette", 2048)
749	749	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)

trunk/src/mame/drivers/vega.c
r29404	r29405
582	582
583	583	// if(color==0) color=0xf;
584	584
585		m_gfxdecode->gfx(0)->transpen(bitmap,cliprect, character, color, 0, 0, x7, y10,0);
	585	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect, character, color, 0, 0, x7, y10,0);
586	586
587	587	++idx;
588	588	}
r29404	r29405
603	603	{
604	604	//for(int x=0;x<4;++x)
605	605	{
606		m_gfxdecode->gfx(2)->transpen(bitmap,cliprect, num, 0, 1, flip?1:0, x4+x0, (flip?(3-y):y)8+y0, 0);
	606	m_gfxdecode->gfx(2)->transpen(bitmap,cliprect, num, 0, 1, flip?1:0, x4+x0, (flip?(3-y):y)8+y0, 0);
607	607	++num;
608	608	}
609	609	}
r29404	r29405
643	643
644	644	for(int y=0;y<4;++y)
645	645	{
646		m_gfxdecode->gfx(3)->transpen(bitmap,cliprect, strip_num, 0, !xor_line, 0, x4+x0, y8+y0, 0);
	646	m_gfxdecode->gfx(3)->transpen(bitmap,cliprect, strip_num, 0, !xor_line, 0, x4+x0, y8+y0, 0);
647	647	++strip_num;
648	648	}
649	649	}

trunk/src/mame/drivers/mappy.c
r29404	r29405
1723	1723	MCFG_NAMCO56XX_IN_1_CB(IOPORT("P1"))
1724	1724	MCFG_NAMCO56XX_IN_2_CB(IOPORT("P2"))
1725	1725	MCFG_NAMCO56XX_IN_3_CB(IOPORT("BUTTONS"))
1726
	1726
1727	1727	MCFG_DEVICE_ADD("namcoio_2", NAMCO56XX, 0)
1728	1728	MCFG_NAMCO56XX_IN_0_CB(READ8(mappy_state, dipB_mux))
1729	1729	MCFG_NAMCO56XX_IN_1_CB(READ8(mappy_state, dipA_l))
r29404	r29405
1745	1745	MCFG_NAMCO56XX_IN_2_CB(IOPORT("P2"))
1746	1746	MCFG_NAMCO56XX_IN_3_CB(IOPORT("BUTTONS"))
1747	1747	MCFG_NAMCO56XX_OUT_0_CB(WRITE8(mappy_state, out_lamps))
1748
	1748
1749	1749	MCFG_DEVICE_ADD("namcoio_2", NAMCO59XX, 0)
1750	1750	MCFG_NAMCO59XX_IN_0_CB(READ8(mappy_state, dipB_mux))
1751	1751	MCFG_NAMCO59XX_IN_1_CB(READ8(mappy_state, dipA_l))
r29404	r29405
1767	1767	MCFG_NAMCO58XX_IN_1_CB(IOPORT("P1"))
1768	1768	MCFG_NAMCO58XX_IN_2_CB(IOPORT("P2"))
1769	1769	MCFG_NAMCO58XX_IN_3_CB(IOPORT("BUTTONS"))
1770
	1770
1771	1771	MCFG_DEVICE_ADD("namcoio_2", NAMCO56XX, 0)
1772	1772	MCFG_NAMCO56XX_IN_0_CB(READ8(mappy_state, dipB_mux))
1773	1773	MCFG_NAMCO56XX_IN_1_CB(READ8(mappy_state, dipA_l))
r29404	r29405
1807	1807	MCFG_NAMCO58XX_IN_1_CB(IOPORT("P1"))
1808	1808	MCFG_NAMCO58XX_IN_2_CB(IOPORT("P2"))
1809	1809	MCFG_NAMCO58XX_IN_3_CB(IOPORT("BUTTONS"))
1810
	1810
1811	1811	MCFG_DEVICE_ADD("namcoio_2", NAMCO56XX, 0)
1812	1812	MCFG_NAMCO56XX_IN_0_CB(READ8(mappy_state, dipB_muxi))
1813	1813	MCFG_NAMCO56XX_IN_1_CB(READ8(mappy_state, dipA_l))
1814	1814	MCFG_NAMCO56XX_IN_2_CB(READ8(mappy_state, dipA_h))
1815	1815	MCFG_NAMCO56XX_IN_3_CB(IOPORT("DSW0"))
1816	1816	MCFG_NAMCO56XX_OUT_0_CB(WRITE8(mappy_state, out_mux))
1817
	1817
1818	1818	/* video hardware */
1819	1819	MCFG_GFXDECODE_ADD("gfxdecode", "palette", phozon)
1820	1820	MCFG_PALETTE_ADD("palette", 644+644)
r29404	r29405
1884	1884	MCFG_NAMCO58XX_IN_1_CB(IOPORT("P1"))
1885	1885	MCFG_NAMCO58XX_IN_2_CB(IOPORT("P2"))
1886	1886	MCFG_NAMCO58XX_IN_3_CB(IOPORT("BUTTONS"))
1887
	1887
1888	1888	MCFG_DEVICE_ADD("namcoio_2", NAMCO58XX, 0)
1889	1889	MCFG_NAMCO58XX_IN_0_CB(READ8(mappy_state, dipB_mux))
1890	1890	MCFG_NAMCO58XX_IN_1_CB(READ8(mappy_state, dipA_l))
r29404	r29405
1907	1907	MCFG_NAMCO58XX_IN_1_CB(IOPORT("P1"))
1908	1908	MCFG_NAMCO58XX_IN_2_CB(IOPORT("P2"))
1909	1909	MCFG_NAMCO58XX_IN_3_CB(IOPORT("BUTTONS"))
1910
	1910
1911	1911	MCFG_DEVICE_ADD("namcoio_2", NAMCO56XX, 0)
1912	1912	MCFG_NAMCO56XX_IN_0_CB(READ8(mappy_state, dipB_mux))
1913	1913	MCFG_NAMCO56XX_IN_1_CB(READ8(mappy_state, dipA_l))
r29404	r29405
1937	1937	MCFG_NAMCO56XX_IN_2_CB(IOPORT("P2"))
1938	1938	MCFG_NAMCO56XX_IN_3_CB(IOPORT("BUTTONS"))
1939	1939	MCFG_NAMCO56XX_OUT_0_CB(WRITE8(mappy_state, out_lamps))
1940
	1940
1941	1941	MCFG_DEVICE_ADD("namcoio_2", NAMCO56XX, 0)
1942	1942	MCFG_NAMCO56XX_IN_0_CB(READ8(mappy_state, dipB_mux))
1943	1943	MCFG_NAMCO56XX_IN_1_CB(READ8(mappy_state, dipA_l))

trunk/src/mame/drivers/safarir.c
r29404	r29405
410	410	/* video hardware */
411	411	MCFG_PALETTE_ADD("palette", 2*8)
412	412	MCFG_PALETTE_INIT_OWNER(safarir_state, safarir)
413
	413
414	414	MCFG_GFXDECODE_ADD("gfxdecode", "palette", safarir)
415	415
416	416	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/mame/drivers/uapce.c
r29404	r29405
321	321	MCFG_CPU_PROGRAM_MAP(z80_map)
322	322
323	323	MCFG_QUANTUM_TIME(attotime::from_hz(60))
324
	324
325	325	/* video hardware */
326	326	MCFG_SCREEN_ADD("screen", RASTER)
327	327	MCFG_SCREEN_RAW_PARAMS(PCE_MAIN_CLOCK, HUC6260_WPF, 64, 64 + 1024 + 64, HUC6260_LPF, 18, 18 + 242)

trunk/src/mame/drivers/rltennis.c
r29404	r29405
185	185	MCFG_SCREEN_VISIBLE_AREA(0,319, 0, 239)
186	186	MCFG_SCREEN_UPDATE_DRIVER(rltennis_state, screen_update_rltennis)
187	187	MCFG_SCREEN_PALETTE("palette")
188
	188
189	189	MCFG_PALETTE_ADD("palette", 256)
190	190
191	191	MCFG_NVRAM_ADD_0FILL("nvram")

trunk/src/mame/drivers/cavepc.c
r29404	r29405
134	134
135	135	Deathshmiles II (2009/10/14 MASTER VER 4.00)
136	136
137		CAVE's venture into PC based hardware platforms. The game did not
138		sell that well and was plagued by BSODs and hardware issues. The
	137	CAVE's venture into PC based hardware platforms. The game did not
	138	sell that well and was plagued by BSODs and hardware issues. The
139	139	motherboard bios version that shipped out with the game is F2 on
140	140	a Gigabyte GA-MA78GPM-UD2H board
141	141	( http://www.gigabyte.com/products/product-page.aspx?pid=3016#ov )
r29404	r29405
143	143	The following versions are known to have existed.
144	144
145	145	1.00 - released 2009/05/14
146		2.00
	146	2.00
147	147	3.00 - sometimes scrolls the text "2ND UPDATE MASTER VER 3.00" at
148	148	the bottom of the title screen
149	149
150	150	The archive contains the following:
151	151
152		./images, documentaiton
	152	./images, documentaiton
153	153	./cf_card_2gb, a dd image of the 2GB CF FLASH card
154	154	./usb_drive, the game is updated using a USB drive and will not
155	155	start if it is not present

trunk/src/mame/drivers/metalmx.c
r29404	r29405
726	726	MCFG_CPU_CONFIG(gsp_config)
727	727	MCFG_CPU_PROGRAM_MAP(gsp_map)
728	728
729		MCFG_CPU_ADD("dsp32c_1", DSP32C, 40000000) /* Unverified */
	729	MCFG_CPU_ADD("dsp32c_1", DSP32C, 40000000) /* Unverified */
730	730	MCFG_CPU_PROGRAM_MAP(dsp32c_1_map)
731	731
732	732	MCFG_CPU_ADD("dsp32c_2", DSP32C, 40000000) /* Unverified */

trunk/src/mame/drivers/slapfght.c
r29404	r29405
9	9	Guardian / Get Star
10	10	Performan
11	11	Tiger Heli
12
	12
13	13	TODO:
14	14	- proper MCU emulation (mame/machine/slapfght.c)
15	15	- alcon cocktail/flipscreen, it doesn't write to the flipscreen reg
r29404	r29405
358	358	WRITE8_MEMBER(slapfght_state::irq_enable_w)
359	359	{
360	360	m_main_irq_enabled = offset ? true : false;
361
	361
362	362	if (!m_main_irq_enabled)
363	363	m_maincpu->set_input_line(0, CLEAR_LINE);
364	364	}
r29404	r29405
366	366	WRITE8_MEMBER(slapfght_state::sound_reset_w)
367	367	{
368	368	m_audiocpu->set_input_line(INPUT_LINE_RESET, offset ? CLEAR_LINE : ASSERT_LINE);
369
	369
370	370	if (offset == 0)
371	371	m_sound_nmi_enabled = false;
372	372	}
r29404	r29405
482	482	/***************************************************************************
483	483
484	484	MCU Memory Maps
485
	485
486	486	NOTE: handlers and simulation are in the src/mame/machine folder
487	487
488	488	***************************************************************************/
r29404	r29405
834	834	{
835	835	// don't boot the mcu since we don't have a dump yet
836	836	m_mcu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
837
	837
838	838	machine_reset();
839	839	}
840	840
r29404	r29405
844	844	{
845	845	UINT8 *ROM = memregion("maincpu")->base();
846	846	membank("bank1")->configure_entries(0, 2, &ROM[0x10000], 0x4000);
847
	847
848	848	membank("bank1")->set_entry(0);
849	849	}
850	850
r29404	r29405
1087	1087	MCFG_CPU_MODIFY("maincpu")
1088	1088	MCFG_CPU_PROGRAM_MAP(tigerhb1_map)
1089	1089	MCFG_CPU_IO_MAP(tigerhb_io_map)
1090
	1090
1091	1091	MCFG_DEVICE_REMOVE("mcu")
1092	1092	MACHINE_CONFIG_END
1093	1093
r29404	r29405
1167	1167	MCFG_CPU_MODIFY("maincpu")
1168	1168	MCFG_CPU_PROGRAM_MAP(getstar_map)
1169	1169	MCFG_CPU_IO_MAP(getstar_io_map)
1170
	1170
1171	1171	MCFG_MACHINE_RESET_OVERRIDE(slapfght_state, getstar)
1172	1172	MACHINE_CONFIG_END
1173	1173

trunk/src/mame/drivers/1945kiii.c
r29404	r29405
120	120	ypos = (source[0] & 0x00ff) >> 0;
121	121	tileno = (source2[0] & 0x7ffe) >> 1;
122	122	xpos \|= (source2[0] & 0x0001) << 8;
123		gfx->transpen(bitmap,cliprect, tileno, 1, 0, 0, xpos, ypos, 0);
124		gfx->transpen(bitmap,cliprect, tileno, 1, 0, 0, xpos, ypos - 0x100, 0); // wrap
125		gfx->transpen(bitmap,cliprect, tileno, 1, 0, 0, xpos - 0x200, ypos, 0); // wrap
126		gfx->transpen(bitmap,cliprect, tileno, 1, 0, 0, xpos - 0x200, ypos - 0x100, 0); // wrap
	123	gfx->transpen(bitmap,cliprect, tileno, 1, 0, 0, xpos, ypos, 0);
	124	gfx->transpen(bitmap,cliprect, tileno, 1, 0, 0, xpos, ypos - 0x100, 0); // wrap
	125	gfx->transpen(bitmap,cliprect, tileno, 1, 0, 0, xpos - 0x200, ypos, 0); // wrap
	126	gfx->transpen(bitmap,cliprect, tileno, 1, 0, 0, xpos - 0x200, ypos - 0x100, 0); // wrap
127	127
128	128	source++;
129	129	source2++;

trunk/src/mame/drivers/astinvad.c
r29404	r29405
74	74
75	75	required_device<samples_device> m_samples;
76	76	required_device<screen_device> m_screen;
77
	77
78	78	DECLARE_WRITE8_MEMBER(color_latch_w);
79	79	DECLARE_WRITE8_MEMBER(spaceint_videoram_w);
80	80	DECLARE_READ8_MEMBER(kamikaze_ppi_r);

trunk/src/mame/drivers/boogwing.c
r29404	r29405
364	364	MCFG_DECO16IC_ADD("tilegen1", boogwing_deco16ic_tilegen1_intf)
365	365	MCFG_DECO16IC_GFXDECODE("gfxdecode")
366	366	MCFG_DECO16IC_PALETTE("palette")
367
	367
368	368	MCFG_DECO16IC_ADD("tilegen2", boogwing_deco16ic_tilegen2_intf)
369	369	MCFG_DECO16IC_GFXDECODE("gfxdecode")
370	370	MCFG_DECO16IC_PALETTE("palette")

trunk/src/mame/drivers/offtwall.c
r29404	r29405
376	376	MCFG_ATARI_VAD_MOB(offtwall_state::s_mob_config, "gfxdecode")
377	377
378	378	MCFG_SCREEN_ADD("screen", RASTER)
379		MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
	379	MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
380	380	/* note: these parameters are from published specs, not derived */
381	381	/* the board uses a VAD chip to generate video signals */
382	382	MCFG_SCREEN_RAW_PARAMS(ATARI_CLOCK_14MHz/2, 456, 0, 336, 262, 0, 240)
r29404	r29405
422	422	ROM_REGION( 0x800, "eeprom:eeprom", 0 )
423	423	ROM_LOAD( "offtwall-eeprom.17l", 0x0000, 0x800, CRC(5eaf2d5b) SHA1(934a76a23960e6ed2cc33c359f9735caee762145) )
424	424
425		ROM_REGION(0x022f, "jsa:plds", 0)
426		ROM_LOAD("136085-1038.17c.bin", 0x0000, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
427		ROM_LOAD("136085-1039.20c.bin", 0x0118, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
	425	ROM_REGION(0x022f, "jsa:plds", 0)
	426	ROM_LOAD("136085-1038.17c.bin", 0x0000, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
	427	ROM_LOAD("136085-1039.20c.bin", 0x0118, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
428	428
429		ROM_REGION(0x2591, "main:plds", 0)
430		ROM_LOAD("136090-1001.14l.bin", 0x0000, 0x201d, NO_DUMP ) /* GAL6001-35P is read protected */
431		ROM_LOAD("136090-1002.11r.bin", 0x201e, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
432		ROM_LOAD("136090-1003.15f.bin", 0x2135, 0x0117, CRC(5e723b46) SHA1(e686920d0af342e33f836fec15b6e8b5ef1b8be5)) /* GAL16V8A-25LP */
433		ROM_LOAD("136090-1005.5n.bin", 0x224c, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
434		ROM_LOAD("136090-1006.5f.bin", 0x2363, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
435		ROM_LOAD("136090-1007.3f.bin", 0x247a, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
	429	ROM_REGION(0x2591, "main:plds", 0)
	430	ROM_LOAD("136090-1001.14l.bin", 0x0000, 0x201d, NO_DUMP ) /* GAL6001-35P is read protected */
	431	ROM_LOAD("136090-1002.11r.bin", 0x201e, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
	432	ROM_LOAD("136090-1003.15f.bin", 0x2135, 0x0117, CRC(5e723b46) SHA1(e686920d0af342e33f836fec15b6e8b5ef1b8be5)) /* GAL16V8A-25LP */
	433	ROM_LOAD("136090-1005.5n.bin", 0x224c, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
	434	ROM_LOAD("136090-1006.5f.bin", 0x2363, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
	435	ROM_LOAD("136090-1007.3f.bin", 0x247a, 0x0117, NO_DUMP ) /* GAL16V8A-25LP is read protected */
436	436	ROM_END
437	437
438	438

trunk/src/mame/drivers/firetrk.c
r29404	r29405
49	49	TIMER_DEVICE_CALLBACK_MEMBER(firetrk_state::firetrk_scanline)
50	50	{
51	51	int scanline = param;
52
	52
53	53	// periodic IRQs are generated by inverse 16V signal
54	54	if ((scanline & 0x1f) == 0)
55	55	generic_pulse_irq_line(m_maincpu, 0, 1);
56
	56
57	57	// vblank interrupt
58	58	// NMIs are disabled during service mode
59	59	if (!m_in_service_mode && scanline == 240)

trunk/src/mame/drivers/segas16a.c
r29404	r29405
1979	1979
1980	1980	/*
1981	1981	static MACHINE_CONFIG_DERIVED( system16a_i8751_no7751, system16a_i8751 )
1982		MCFG_DEVICE_REMOVE("n7751")
1983		MCFG_DEVICE_REMOVE("dac")
	1982	MCFG_DEVICE_REMOVE("n7751")
	1983	MCFG_DEVICE_REMOVE("dac")
1984	1984
1985		MCFG_SOUND_REPLACE("ymsnd", YM2151, 4000000)
1986		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	1985	MCFG_SOUND_REPLACE("ymsnd", YM2151, 4000000)
	1986	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1987	1987	MACHINE_CONFIG_END
1988	1988	*/
1989	1989
r29404	r29405
2514	2514	ROM_LOAD16_BYTE( "epr-7384.24", 0x020001, 0x8000, CRC(fd909341) SHA1(2f1e01eb7d7b330c9c0dd98e5f8ed4973f0e93fb) )
2515	2515
2516	2516	ROM_REGION( 0x18000, "gfx1", 0 ) // tiles
2517		ROM_LOAD( "epr-7388.95", 0x00000, 0x08000, CRC(8eb02f6b) SHA1(80511b944b57541669010bd5a0ca52bc98eabd62) )
	2517	ROM_LOAD( "epr-7388.95", 0x00000, 0x08000, CRC(8eb02f6b) SHA1(80511b944b57541669010bd5a0ca52bc98eabd62) )
2518	2518	ROM_LOAD( "epr-7389.94", 0x08000, 0x08000, CRC(2f4f71b8) SHA1(ceb39e95cd43904b8e4f89c7227491e139fb3ca6) )
2519	2519	ROM_LOAD( "epr-7390.93", 0x10000, 0x08000, CRC(d90609c6) SHA1(4232f6ecb21f242c0c8d81e06b88bc742668609f) )
2520	2520
r29404	r29405
2540	2540	ROM_LOAD16_BYTE( "epr-7387.41", 0x020000, 0x8000, CRC(0acd335d) SHA1(f39566a2069eefa7682c57c6521ea7a328738d06) ) // missing - assumed to be the same because the rom below is
2541	2541	ROM_LOAD16_BYTE( "ic24-prg20-2f57.bin", 0x020001, 0x8000, CRC(fd909341) SHA1(2f1e01eb7d7b330c9c0dd98e5f8ed4973f0e93fb) ) // MATCH
2542	2542
2543		ROM_REGION( 0x18000, "gfx1", 0 ) // tiles
	2543	ROM_REGION( 0x18000, "gfx1", 0 ) // tiles
2544	2544	ROM_LOAD( "ic95-1413.bin", 0x00000, 0x08000, CRC(158af770) SHA1(a02c500920770a987c9d8c78e0313cb3434c1873) ) // 96.661377%
2545	2545	ROM_LOAD( "ic94-3e96.bin", 0x08000, 0x08000, CRC(2fea4fe7) SHA1(891dbf163378e9ef55b97b4cb8ac02dab05f206c) ) // 96.710205%
2546	2546	ROM_LOAD( "ic93-de1b.bin", 0x10000, 0x08000, BAD_DUMP CRC(335fe57a) SHA1(93cfcfd1d06daa03b1b000460c4e0ff54aa9f317) ) // 72.341919%

trunk/src/mame/drivers/neogeo.c
r29404	r29405
210	210	. NEO-MVS PROGSS3
211	211	. NEO-MVS PROGTOP
212	212	. NEO-MVS PROGSF1 (1998.6.17)
213		. NEO-MVS PROGSF1E (1998.6.18)
	213	. NEO-MVS PROGSF1E (1998.6.18)
214	214	. NEO-MVS PROGEOP (1999.2.2)
215	215	. NEO-MVS PROGLBA (1999.4.12) - LBA-SUB (2000.2.24)
216	216	. NEO-MVS PROGBK1 (1994)
r29404	r29405
787	787	READ16_MEMBER(neogeo_state::memcard_r)
788	788	{
789	789	m_maincpu->eat_cycles(2); // insert waitstate
790
	790
791	791	UINT16 ret;
792	792
793	793	if (memcard_present(machine()) != -1)
r29404	r29405
1810	1810	MCFG_CPU_ADD("audiocpu", Z80, NEOGEO_AUDIO_CPU_CLOCK)
1811	1811	MCFG_CPU_PROGRAM_MAP(audio_map)
1812	1812	MCFG_CPU_IO_MAP(audio_io_map)
1813
	1813
1814	1814	/* video hardware */
1815	1815	MCFG_DEFAULT_LAYOUT(layout_neogeo)
1816	1816
r29404	r29405
11558	11558	/* N.C.I - LE CORTEX */
11559	11559	// Bang Bang Busters (c)2010 - MVS?/AES
11560	11560	// Treasure of the Caribbean (c)2011 - MVS?/AES
11561

trunk/src/mame/drivers/statriv2.c
r29404	r29405
88	88	m_videoram(*this, "videoram"),
89	89	m_question_offset(*this, "question_offset"),
90	90	m_gfxdecode(*this, "gfxdecode"),
91		m_palette(*this, "palette")
	91	m_palette(*this, "palette")
92	92	{ }
93	93
94	94	required_device<cpu_device> m_maincpu;

trunk/src/mame/drivers/ultraman.c
r29404	r29405
230	230	MCFG_PALETTE_ENABLE_SHADOWS()
231	231
232	232	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
233
	233
234	234	MCFG_K051960_ADD("k051960", ultraman_k051960_intf)
235	235	MCFG_K051960_GFXDECODE("gfxdecode")
236	236	MCFG_K051960_PALETTE("palette")
237
	237
238	238	MCFG_K051316_ADD("k051316_1", ultraman_k051316_intf_0)
239	239	MCFG_K051316_GFXDECODE("gfxdecode")
240	240	MCFG_K051316_PALETTE("palette")
241
	241
242	242	MCFG_K051316_ADD("k051316_2", ultraman_k051316_intf_1)
243	243	MCFG_K051316_GFXDECODE("gfxdecode")
244	244	MCFG_K051316_PALETTE("palette")
245
	245
246	246	MCFG_K051316_ADD("k051316_3", ultraman_k051316_intf_2)
247	247	MCFG_K051316_GFXDECODE("gfxdecode")
248	248	MCFG_K051316_PALETTE("palette")

trunk/src/mame/drivers/atarittl.c
r29404	r29405
2	2
3	3	Atari / Kee Games Driver - Discrete Games made in the 1970's
4	4
5
	5
6	6	Atari / Kee Games List and Data based, in part from:
7
	7
8	8	- Andy's collection of Bronzeage Atari Video Arcade PCB's"
9	9	http://www.andysarcade.net/personal/bronzeage/index.htm
10
	10
11	11	- "Atari's Technical Manual Log"
12	12	http://www.atarigames.com/manuals.txt
13
	13
14	14	Suspected "same games" are grouped together. These are usually the exact same game but different cabinet/name.
15
16
	15
	16
17	17	Technical Manual #s Game Name(s) Atari Part #'s Data PROM/ROM Chip Numbers
18	18	-------------------+----------------------------------------------------+----------------------------------+---------+---------------------------------------
19	19	TM-025 Anti-Aircraft (1975) A000951 YES 003127
20	20	TM-058 Breakout/Breakout Cocktail (1976) A004533 NO
21		TM-048 Crash 'N Score/Stock Car (1975) A004256 YES 003186(x2), 003187(x2), 004248, 004247
	21	TM-048 Crash 'N Score/Stock Car (1975) A004256 YES 003186(x2), 003187(x2), 004248, 004247
22	22	TM-030 Crossfire (1975)
23	23	TM-003,005,011,020 Gran Trak 10/Trak 10/Formula K/Race Circuit (1974) A000872,A000872 K3RT YES 74186 Racetrack Prom (K5)
24	24	TM-004,021 Gran Trak 20/Trak 20/Twin Racer (1974) A001791(RT20),A001793(A20-K4DRTA) YES 74186 Racetrack prom (K5)
r29404	r29405
33	33	TM-040 Outlaw (1976) A003213 YES 003323 - ROM (8205 @ J4)
34	34	TM-007 Pin Pong (1974) A001660 NO
35	35	TM-013 Pong/Super Pong (1972) A001433,A000423 NO
36		TM-015 Pong Cocktail (1974) NO
	36	TM-015 Pong Cocktail (1974) NO
37	37	TM-014 Pong Doubles/Coupe Davis (1974) A000785 NO
38	38	TM-018 Pursuit (1975) K8P-B 90128 NO
39	39	TM-012,022,034 Quadrapong/Elimination (1974) A000845 NO
r29404	r29405
46	46	TM-057 Stunt Cycle (1976) A004128 YES 004275 ROM Motorcycle/Bus (1F), 004811 ROM Score Translator (D7)
47	47	TM-010,036,049 Tank/Tank Cocktail/Tank II (1974/1975) A003111 (K5T-F 90124) YES 90-2006
48	48	TM-002 Touch Me (1974) NO
49
	49
50	50	- Not Known to be released or produced, but at least announced.
51
	51
52	52	TM-024 Qwakers (Not Produced/Released)
53	53	TM-017 World Cup Football (Not Produced/Released)
54
55
	54
	55
56	56	***************************************************************************/
57	57
58	58
r29404	r29405
94	94	public:
95	95	atarikee_state(const machine_config &mconfig, device_type type, const char *tag)
96	96	: driver_device(mconfig, type, tag),
97		m_maincpu(*this, "maincpu"),
98		m_video(*this, "fixfreq")
	97	m_maincpu(*this, "maincpu"),
	98	m_video(*this, "fixfreq")
99	99	{
100	100	}
101
	101
102	102	// devices
103	103	required_device<netlist_mame_device_t> m_maincpu;
104	104	required_device<fixedfreq_device> m_video;
105	105
106	106	protected:
107
	107
108	108	// driver_device overrides
109	109	virtual void machine_start();
110	110	virtual void machine_reset();
111
	111
112	112	virtual void video_start();
113
	113
114	114	private:
115
	115
116	116	};
117	117
118	118
119	119
120	120	static NETLIST_START(atarikee)
121	121	SOLVER(Solver, 48000)
122		// PARAM(Solver.FREQ, 48000)
	122	// PARAM(Solver.FREQ, 48000)
123	123	PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
124	124
125	125	// schematics
126	126	//...
127	127
128		// NETDEV_ANALOG_CALLBACK(sound_cb, sound, atarikee_state, sound_cb, "")
129		// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
	128	// NETDEV_ANALOG_CALLBACK(sound_cb, sound, atarikee_state, sound_cb, "")
	129	// NETDEV_ANALOG_CALLBACK(video_cb, videomix, fixedfreq_device, update_vid, "fixfreq")
130	130	NETLIST_END()
131	131
132	132
r29404	r29405
147	147	static MACHINE_CONFIG_START( atarikee, atarikee_state )
148	148
149	149	/* basic machine hardware */
150		MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
	150	MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
151	151	MCFG_NETLIST_SETUP(atarikee)
152	152
153	153	/* video hardware */
r29404	r29405
309	309	ROM_END
310	310
311	311
312		/* // NO DUMPED ROMS
	312	/* // NO DUMPED ROMS
313	313
314	314	// Astroturf
315	315	ROM_START( astrotrf )
316		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
317
318		ROM_REGION( 0x0400, "gfx", ROMREGION_ERASE00 ) // Region Size unknown, dump size unknown
319		ROM_LOAD( "003774.c8", 0x0000, 0x0100, NO_DUMP ) // Bugle
320		ROM_LOAD( "003773-02.c4", 0x0100, 0x0100, NO_DUMP ) // Graphics (Astroturf - Rev.A)
	316	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	317
	318	ROM_REGION( 0x0400, "gfx", ROMREGION_ERASE00 ) // Region Size unknown, dump size unknown
	319	ROM_LOAD( "003774.c8", 0x0000, 0x0100, NO_DUMP ) // Bugle
	320	ROM_LOAD( "003773-02.c4", 0x0100, 0x0100, NO_DUMP ) // Graphics (Astroturf - Rev.A)
321	321	ROM_END
322	322
323	323	// Crossfire
r29404	r29405
327	327
328	328	// Gran Trak 10
329	329	ROM_START( gtrak10 ) // Unknown size, assumed 2K Bytes
330		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
331
332		ROM_REGION( 0x0800, "racetrack", ROMREGION_ERASE00 )
333		ROM_LOAD( "74168.k5", 0x0000, 0x0800, NO_DUMP) // Racetrack
	330	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	331
	332	ROM_REGION( 0x0800, "racetrack", ROMREGION_ERASE00 )
	333	ROM_LOAD( "74168.k5", 0x0000, 0x0800, NO_DUMP) // Racetrack
334	334	ROM_END
335
	335
336	336	// Gran Trak 20
337	337	ROM_START( gtrak20 ) // Unknown size, assumed 2K Bytes
338		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
339
340		ROM_REGION( 0x0800, "racetrack", ROMREGION_ERASE00 )
341		ROM_LOAD( "74168.k5", 0x0000, 0x0800, NO_DUMP) // Racetrack
	338	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	339
	340	ROM_REGION( 0x0800, "racetrack", ROMREGION_ERASE00 )
	341	ROM_LOAD( "74168.k5", 0x0000, 0x0800, NO_DUMP) // Racetrack
342	342	ROM_END
343	343
344	344	// LeMans
345	345	ROM_START( lemans )
346		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
347
348		ROM_REGION( 0x0400, "gfx", ROMREGION_ERASE00 ) // Region Size unknown, dump size unknown
349		ROM_LOAD( "005837-01.n5", 0x0000, 0x0100, NO_DUMP ) // Rom 1
350		ROM_LOAD( "005838-01.n4", 0x0100, 0x0100, NO_DUMP ) // Rom 2
351		ROM_LOAD( "005839-01.n6", 0x0200, 0x0100, NO_DUMP ) // Rom 3
	346	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	347
	348	ROM_REGION( 0x0400, "gfx", ROMREGION_ERASE00 ) // Region Size unknown, dump size unknown
	349	ROM_LOAD( "005837-01.n5", 0x0000, 0x0100, NO_DUMP ) // Rom 1
	350	ROM_LOAD( "005838-01.n4", 0x0100, 0x0100, NO_DUMP ) // Rom 2
	351	ROM_LOAD( "005839-01.n6", 0x0200, 0x0100, NO_DUMP ) // Rom 3
352	352	ROM_END
353
354		// Qwak!
	353
	354	// Qwak!
355	355	ROM_START( qwak )
356		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
357
358		ROM_REGION( 0x0200, "gfx", ROMREGION_ERASE00 ) // Region Size unknown, dump size unknown
359		ROM_LOAD( "37-2530n.k9", 0x0000, 0x0200, NO_DUMP ) // Custom Rom (2530 N)
	356	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	357
	358	ROM_REGION( 0x0200, "gfx", ROMREGION_ERASE00 ) // Region Size unknown, dump size unknown
	359	ROM_LOAD( "37-2530n.k9", 0x0000, 0x0200, NO_DUMP ) // Custom Rom (2530 N)
360	360	ROM_END
361
	361
362	362	*/
363	363
364	364
365		/* // 100% TTL - NO ROMS
366
	365	/* // 100% TTL - NO ROMS
	366
367	367	ROM_START( breakout )
368		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	368	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
369	369	ROM_END
370	370
371	371	ROM_START( goal4 )
372		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	372	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
373	373	ROM_END
374	374
375	375	ROM_START( gotcha )
376		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	376	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
377	377	ROM_END
378	378
379	379	ROM_START( gotchac )
380		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	380	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
381	381	ROM_END
382	382
383	383	ROM_START( highway )
384		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	384	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
385	385	ROM_END
386	386
387	387	ROM_START( pinpong )
388		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	388	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
389	389	ROM_END
390	390
391	391	ROM_START( pongdbl )
392		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	392	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
393	393	ROM_END
394	394
395	395	ROM_START( pursuit )
396		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	396	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
397	397	ROM_END
398	398
399	399	ROM_START( quadpong )
400		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	400	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
401	401	ROM_END
402	402
403	403	ROM_START( rebound )
404		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	404	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
405	405	ROM_END
406	406
407	407	ROM_START( spacrace )
408		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	408	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
409	409	ROM_END
410	410
411	411	ROM_START( touchme )
412		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
	412	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
413	413	ROM_END
414
	414
415	415	*/
416	416
417	417

trunk/src/mame/drivers/quantum.c
r29404	r29405
308	308	MCFG_SCREEN_VISIBLE_AREA(0, 900, 0, 600)
309	309	MCFG_SCREEN_UPDATE_DEVICE("vector", vector_device, screen_update)
310	310
311		MCFG_DEVICE_ADD("avg", AVG_QUANTUM, 0)
	311	MCFG_DEVICE_ADD("avg", AVG_QUANTUM, 0)
312	312	MCFG_AVGDVG_VECTOR("vector")
313	313
314	314	/* sound hardware */

trunk/src/mame/drivers/taito_f2.c
r29404	r29405
3260	3260
3261	3261	MCFG_PALETTE_MODIFY("palette")
3262	3262	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3263
	3263
3264	3264	/* video hardware */
3265	3265	MCFG_VIDEO_START_OVERRIDE(taitof2_state,taitof2_gunfront)
3266	3266	MCFG_SCREEN_MODIFY("screen")
r29404	r29405
3388	3388
3389	3389	MCFG_PALETTE_MODIFY("palette")
3390	3390	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3391
	3391
3392	3392	/* video hardware */
3393	3393	MCFG_GFXDECODE_MODIFY("gfxdecode", yuyugogo)
3394	3394	MCFG_VIDEO_START_OVERRIDE(taitof2_state,taitof2_yuyugogo)
r29404	r29405
3585	3585	MCFG_VIDEO_START_OVERRIDE(taitof2_state,taitof2_dinorex)
3586	3586	MCFG_SCREEN_MODIFY("screen")
3587	3587	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3588
	3588
3589	3589	MCFG_PALETTE_MODIFY("palette")
3590	3590	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3591	3591
r29404	r29405
3607	3607	MCFG_VIDEO_START_OVERRIDE(taitof2_state,taitof2_quiz)
3608	3608	MCFG_SCREEN_MODIFY("screen")
3609	3609	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3610
	3610
3611	3611	MCFG_PALETTE_MODIFY("palette")
3612	3612	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3613	3613
r29404	r29405
3629	3629	MCFG_VIDEO_START_OVERRIDE(taitof2_state,taitof2_quiz)
3630	3630	MCFG_SCREEN_MODIFY("screen")
3631	3631	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3632
	3632
3633	3633	MCFG_PALETTE_MODIFY("palette")
3634	3634	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3635	3635
r29404	r29405
3651	3651	MCFG_VIDEO_START_OVERRIDE(taitof2_state,taitof2_quiz)
3652	3652	MCFG_SCREEN_MODIFY("screen")
3653	3653	MCFG_SCREEN_UPDATE_DRIVER(taitof2_state, screen_update_taitof2_pri)
3654
	3654
3655	3655	MCFG_PALETTE_MODIFY("palette")
3656	3656	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
3657	3657

trunk/src/mame/drivers/goldnpkr.c
r29404	r29405
3410	3410	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3411	3411
3412	3412	/* the following one is connected to DIP switches and is meant
3413		for switch between different programs stored in different
3414		halves of the program ROM */
	3413	for switch between different programs stored in different
	3414	halves of the program ROM */
3415	3415	PORT_START("SELDSW")
3416	3416	PORT_DIPNAME( 0x01, 0x00, "Game Selector" )
3417	3417	PORT_DIPSETTING( 0x00, "Game 1 (Italian" )
r29404	r29405
4048	4048	ROM_END
4049	4049
4050	4050	ROM_START( videtron2 )
4051		ROM_REGION( 0x10000, "maincpu", 0 ) /* different from videtron */
	4051	ROM_REGION( 0x10000, "maincpu", 0 ) /* different from videtron */
4052	4052	ROM_LOAD( "4.bin", 0x5000, 0x1000, CRC(4a7dab42) SHA1(7fcdab985b783d90879a99b2a53a6814ca4278eb) )
4053	4053	ROM_LOAD( "5.bin", 0x6000, 0x1000, CRC(c70e8127) SHA1(7db2d4a29cba7c336f254393955fad71f30a539a) )
4054	4054	ROM_LOAD( "6.bin", 0x7000, 0x1000, CRC(490c7304) SHA1(1a6c6112571fd0e35b640ed58f66582a2d99c58b) )
r29404	r29405
10335	10335	GAME( 198?, pokerduc, 0, goldnpkr, goldnpkr, goldnpkr_state, icp1db, ROT0, "<unknown>", "unknown encrypted poker game", GAME_NOT_WORKING ) // encrypted.
10336	10336
10337	10337	GAMEL( 198?, bchancep, 0, bchancep, goldnpkr, goldnpkr_state, bchancep, ROT0, "<unknown>", "Bonne Chance! (Golden Poker prequel HW)", GAME_NOT_WORKING, layout_goldnpkr )
10338		GAME( 1987, pokermon, 0, mondial, mondial, driver_device, 0, ROT0, "<unknown>", "Mundial/Mondial (Italian/French)", 0 ) // banked selectable program
10339		GAME( 198?, pokersis, 0, bchancep, goldnpkr, driver_device, 0, ROT0, "Sisteme France", "unknown Sisteme France Poker", GAME_NOT_WORKING ) // fix banking (4 prgs?)...
	10338	GAME( 1987, pokermon, 0, mondial, mondial, driver_device, 0, ROT0, "<unknown>", "Mundial/Mondial (Italian/French)", 0 ) // banked selectable program
	10339	GAME( 198?, pokersis, 0, bchancep, goldnpkr, driver_device, 0, ROT0, "Sisteme France", "unknown Sisteme France Poker", GAME_NOT_WORKING ) // fix banking (4 prgs?)...

trunk/src/mame/drivers/cswat.c
r29404	r29405
4	4	mirrors and motors to move a spotlight(s) on a large projection screen,
5	5	similar to Namco Shoot Away/Shoot Away II.
6	6	The CRT is just used for showing status and keeping scores.
7
	7
8	8	X1 18.432MHz
9	9	HD68A09EP - Hitachi M6809 CPU
10	10	2 * M58725P - Mitsubishi 2KB SRAM
r29404	r29405
134	134	static ADDRESS_MAP_START( cswat_map, AS_PROGRAM, 8, cswat_state )
135	135	AM_RANGE(0x0000, 0x0bff) AM_RAM_WRITE(videoram_w) AM_SHARE("videoram")
136	136	AM_RANGE(0x0c00, 0x0fff) AM_RAM
137		// AM_RANGE(0x1800, 0x1800) AM_READNOP // ? reads here after writing to $4000
	137	// AM_RANGE(0x1800, 0x1800) AM_READNOP // ? reads here after writing to $4000
138	138	AM_RANGE(0x2000, 0x2000) AM_WRITE(irq_ack_w) // writes 1 at end of vblank irq, 0 at gamestart
139	139	AM_RANGE(0x2000, 0x2001) AM_READ(dipswitch_r)
140	140	AM_RANGE(0x2002, 0x2002) AM_WRITE(irq_ack_w) // writes 0 at start of vblank irq
141	141	AM_RANGE(0x2002, 0x2002) AM_READ(sensors_r)
142	142	AM_RANGE(0x2003, 0x2003) AM_READ_PORT("IN0")
143		// AM_RANGE(0x4000, 0x4009) AM_NOP // ?
	143	// AM_RANGE(0x4000, 0x4009) AM_NOP // ?
144	144	AM_RANGE(0x8000, 0xffff) AM_ROM
145	145	ADDRESS_MAP_END
146	146

trunk/src/mame/drivers/hng64.c
r29404	r29405
650	650
651	651	switch (offset*4)
652	652	{
653		case 0x000: return 0x00000400;
	653	case 0x000: return 0x00000400;
654	654	case 0x004: return ioport("SYSTEM")->read();
655	655	case 0x008: return ioport("P1_P2")->read();
656	656	case 0x600: return m_no_machine_error_code;
r29404	r29405
919	919	{
920	920	//if(data & 2) // swap buffers
921	921	//{
922		// clear3d();
	922	// clear3d();
923	923	//}
924	924
925		// printf("%02x\n",data);
	925	// printf("%02x\n",data);
926	926
927		// if(data & 1) // process DMA from 3d FIFO to framebuffer
	927	// if(data & 1) // process DMA from 3d FIFO to framebuffer
928	928
929	929	// if(data & 4) // reset buffer count
930	930	}
r29404	r29405
984	984	*/
985	985	READ32_MEMBER(hng64_state::unk_vreg_r)
986	986	{
987		// m_unk_vreg_toggle^=0x8000;
	987	// m_unk_vreg_toggle^=0x8000;
988	988
989	989	return 0;
990	990
991		// return ++m_unk_vreg_toggle;
	991	// return ++m_unk_vreg_toggle;
992	992	}
993	993
994	994	/*** I don't think there is a soundram2, having it NOT hooked up causes xrally to copy the sound program to the expected location, see memory map note ***/
r29404	r29405
1890	1890
1891	1891	switch(scanline)
1892	1892	{
1893		case 224*2: m_set_irq(0x0001); break; // lv 0 vblank irq
1894		// case 0*2: m_set_irq(0x0002); break; // lv 1
1895		// case 32*2: m_set_irq(0x0008); break; // lv 2
1896		// case 64*2: m_set_irq(0x0008); break; // lv 2
1897		case 128*2: m_set_irq(0x0800); break; // lv 11 network irq?
	1893	case 224*2: m_set_irq(0x0001); break; // lv 0 vblank irq
	1894	// case 0*2: m_set_irq(0x0002); break; // lv 1
	1895	// case 32*2: m_set_irq(0x0008); break; // lv 2
	1896	// case 64*2: m_set_irq(0x0008); break; // lv 2
	1897	case 128*2: m_set_irq(0x0800); break; // lv 11 network irq?
1898	1898	}
1899	1899	}
1900	1900
r29404	r29405
1923	1923	m_audiocpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
1924	1924	m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
1925	1925
1926		// m_comm->set_input_line(INPUT_LINE_RESET, PULSE_LINE); // reset the CPU and let 'er rip
	1926	// m_comm->set_input_line(INPUT_LINE_RESET, PULSE_LINE); // reset the CPU and let 'er rip
1927	1927	// m_comm->set_input_line(INPUT_LINE_HALT, ASSERT_LINE); // hold on there pardner...
1928	1928
1929	1929	// "Display List" init - ugly
1930		// m_activeBuffer = 0;
	1930	// m_activeBuffer = 0;
1931	1931
1932	1932	/* For simulate MCU stepping */
1933	1933	m_mcu_fake_time = 0;
r29404	r29405
1955	1955	MCFG_CPU_IO_MAP(hng_comm_io_map)
1956	1956
1957	1957	MCFG_NVRAM_ADD_0FILL("nvram")
1958
	1958
1959	1959	MCFG_DEVICE_ADD("rtc", MSM6242, XTAL_32_768kHz)
1960	1960
1961	1961	MCFG_GFXDECODE_ADD("gfxdecode", "palette", hng64)

trunk/src/mame/drivers/cabal.c
r29404	r29405
473	473	MCFG_SCREEN_REFRESH_RATE(59.60) /* verified on pcb */
474	474	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
475	475	MCFG_SCREEN_SIZE(256, 256)
476		MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 28, 308-1)
	476	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 28, 308-1)
477	477	MCFG_SCREEN_UPDATE_DRIVER(cabal_state, screen_update_cabal)
478	478	MCFG_SCREEN_PALETTE("palette")
479	479

trunk/src/mame/drivers/turrett.c
r29404	r29405
366	366	MCFG_SCREEN_RAW_PARAMS(4000000, 512, 0, 336, 259, 0, 244)
367	367	MCFG_SCREEN_UPDATE_DRIVER(turrett_state, screen_update)
368	368	MCFG_SCREEN_PALETTE("palette")
369
	369
370	370	MCFG_PALETTE_ADD_RRRRRGGGGGBBBBB("palette")
371	371
372	372	/* sound hardware */

trunk/src/mame/drivers/destroyr.c
r29404	r29405
56	56	required_device<gfxdecode_device> m_gfxdecode;
57	57	required_device<screen_device> m_screen;
58	58	required_device<palette_device> m_palette;
59
	59
60	60	DECLARE_WRITE8_MEMBER(destroyr_misc_w);
61	61	DECLARE_WRITE8_MEMBER(destroyr_cursor_load_w);
62	62	DECLARE_WRITE8_MEMBER(destroyr_interrupt_ack_w);

trunk/src/mame/drivers/feversoc.c
r29404	r29405
256	256	MCFG_SCREEN_REFRESH_RATE(60)
257	257	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
258	258	MCFG_SCREEN_SIZE(408, 328)
259		MCFG_SCREEN_VISIBLE_AREA(08, 408-1, 08, 308-1) //dynamic resolution?
	259	MCFG_SCREEN_VISIBLE_AREA(08, 408-1, 08, 308-1) //dynamic resolution?
260	260	MCFG_SCREEN_UPDATE_DRIVER(feversoc_state, screen_update_feversoc)
261	261	MCFG_SCREEN_PALETTE("palette")
262	262

trunk/src/mame/drivers/multfish_ref.c
r29404	r29405
624	624	//GAME( 2008, fcockt2_2, fcockt2_parent, igrosoft_gamble, igrosoft_gamble, driver_device, 0, ROT0, "Igrosoft", "Fruit Cocktail 2 (080904 Russia)", GAME_SUPPORTS_SAVE ) /* Russia */
625	625
626	626	#endif
627
628

trunk/src/mame/drivers/gunpey.c
r29404	r29405
202	202	m_maincpu(*this, "maincpu"),
203	203	m_oki(*this, "oki"),
204	204	m_wram(*this, "wram"),
205		m_palette(*this, "palette")
	205	m_palette(*this, "palette")
206	206	{ }
207	207
208	208	required_device<cpu_device> m_maincpu;

trunk/src/mame/drivers/superwng.c
r29404	r29405
39	39	m_colorram_bg(*this, "colorrabg"),
40	40	m_colorram_fg(*this, "colorrafg"),
41	41	m_gfxdecode(*this, "gfxdecode"),
42		m_palette(*this, "palette")
	42	m_palette(*this, "palette")
43	43	{ }
44	44
45	45	required_device<cpu_device> m_maincpu;

trunk/src/mame/drivers/dblcrown.c
r29404	r29405
5	5	Double Crown (c) 1997 Cadence Technology / Dyna
6	6
7	7	Driver by Angelo Salese
8		Additional work by Roberto Fresca.
	8	Additional work by Roberto Fresca.
9	9
10	10	TODO:
11	11	- Bogus "Hole" in main screen display;
r29404	r29405
35	35	4 * dipsw 8pos
36	36	YMZ284-D (ay8910, but without i/o ports)
37	37	MAXIM MAX693ACPE is a "Microprocessor Supervisory Circuit", for watchdog
38		and for nvram functions.
	38	and for nvram functions.
39	39
40	40	***************************************************************************/
41	41
42	42
43		#define MAIN_CLOCK XTAL_28_63636MHz
44		#define CPU_CLOCK MAIN_CLOCK / 6
45		#define SND_CLOCK MAIN_CLOCK / 12
	43	#define MAIN_CLOCK XTAL_28_63636MHz
	44	#define CPU_CLOCK MAIN_CLOCK / 6
	45	#define SND_CLOCK MAIN_CLOCK / 12
46	46
47	47	#include "emu.h"
48	48	#include "cpu/z80/z80.h"
r29404	r29405
298	298	x-x- --xx unknown
299	299	*/
300	300
301		coin_counter_w(machine(), 0, data & 0x10); /* Coin In counter pulse */
302		coin_counter_w(machine(), 1 ,data & 0x08); /* Payout counter pulse */
303		// popmessage("out: %02x", data);
	301	coin_counter_w(machine(), 0, data & 0x10); /* Coin In counter pulse */
	302	coin_counter_w(machine(), 1 ,data & 0x08); /* Payout counter pulse */
	303	// popmessage("out: %02x", data);
304	304	}
305	305
306	306

trunk/src/mame/drivers/cball.c
r29404	r29405
36	36	required_device<gfxdecode_device> m_gfxdecode;
37	37	required_device<screen_device> m_screen;
38	38	required_device<palette_device> m_palette;
39
	39
40	40	DECLARE_WRITE8_MEMBER(cball_vram_w);
41	41	DECLARE_READ8_MEMBER(cball_wram_r);
42	42	DECLARE_WRITE8_MEMBER(cball_wram_w);

trunk/src/mame/drivers/vlc.c
r29404	r29405
327	327	void nevada_state::nvram_init(nvram_device &nvram, void *data, size_t size)
328	328	{
329	329	memset(data, 0x00, size);
330		if (memregion("defaults")->base())
	330	if (memregion("defaults")->base())
331	331	memcpy(data, memregion("defaults")->base(), memregion("defaults")->bytes());
332	332	}
333	333
r29404	r29405
649	649	MCFG_MC68681_INPORT_CALLBACK(IOPORT("DSW3"))
650	650
651	651	MCFG_MICROTOUCH_SERIAL_ADD( "microtouch", 9600, DEVWRITELINE("duart40_68681", mc68681_device, rx_a_w) )
652
	652
653	653	/* devices */
654	654	MCFG_DEVICE_ADD("rtc", MSM6242, XTAL_32_768kHz)
655	655	MCFG_MSM6242_OUT_INT_HANDLER(WRITELINE(nevada_state, nevada_rtc_irq))

trunk/src/mame/drivers/tourtabl.c
r29404	r29405
178	178	MCFG_DEVICE_ADD("tia_video", TIA_NTSC_VIDEO, 0)
179	179	MCFG_TIA_READ_INPUT_PORT_CB(READ16(tourtabl_state, tourtabl_read_input_port))
180	180	MCFG_TIA_DATABUS_CONTENTS_CB(READ8(tourtabl_state, tourtabl_get_databus_contents))
181
	181
182	182	MCFG_SCREEN_ADD("screen", RASTER)
183	183	MCFG_SCREEN_RAW_PARAMS( MASTER_CLOCK, 228, 34, 34 + 160, 262, 46, 46 + 200 )
184	184	MCFG_SCREEN_UPDATE_DEVICE("tia_video", tia_video_device, screen_update)

trunk/src/mame/drivers/asuka.c
r29404	r29405
888	888	MCFG_TC0100SCN_PALETTE("palette")
889	889	MCFG_TC0110PCR_ADD("tc0110pcr")
890	890	MCFG_TC0110PCR_PALETTE("palette")
891
	891
892	892	/* sound hardware */
893	893	MCFG_SPEAKER_STANDARD_MONO("mono")
894	894
r29404	r29405
920	920	MCFG_TC0220IOC_READ_2_CB(IOPORT("IN0"))
921	921	MCFG_TC0220IOC_READ_3_CB(IOPORT("IN1"))
922	922	MCFG_TC0220IOC_READ_7_CB(IOPORT("IN2"))
923
	923
924	924	/* video hardware */
925	925	MCFG_SCREEN_ADD("screen", RASTER)
926	926	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mame/drivers/hvyunit.c
r29404	r29405
111	111	required_device<kaneko_pandora_device> m_pandora;
112	112	required_device<gfxdecode_device> m_gfxdecode;
113	113	required_device<palette_device> m_palette;
114
	114
115	115	DECLARE_WRITE8_MEMBER(trigger_nmi_on_slave_cpu);
116	116	DECLARE_WRITE8_MEMBER(master_bankswitch_w);
117	117	DECLARE_WRITE8_MEMBER(mermaid_data_w);

trunk/src/mame/drivers/rollerg.c
r29404	r29405
282	282	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
283	283
284	284	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
285
	285
286	286	MCFG_K053244_ADD("k053244", rollerg_k05324x_intf)
287	287	MCFG_K053244_GFXDECODE("gfxdecode")
288	288	MCFG_K053244_PALETTE("palette")
289
	289
290	290	MCFG_K051316_ADD("k051316", rollerg_k051316_intf)
291	291	MCFG_K051316_GFXDECODE("gfxdecode")
292	292	MCFG_K051316_PALETTE("palette")
293
	293
294	294	MCFG_DEVICE_ADD("k053252", K053252, 3000000*2)
295	295	MCFG_K053252_INT1_ACK_CB(WRITELINE(rollerg_state,rollerg_irq_ack_w))
296	296	MCFG_K053252_OFFSETS(148, 28)

trunk/src/mame/drivers/backfire.c
r29404	r29405
526	526	MCFG_SCREEN_PALETTE("palette")
527	527
528	528
529		MCFG_DECO16IC_ADD("tilegen1", backfire_deco16ic_tilegen1_intf)
	529	MCFG_DECO16IC_ADD("tilegen1", backfire_deco16ic_tilegen1_intf)
530	530	MCFG_DECO16IC_SET_SCREEN("lscreen")
531	531	MCFG_DECO16IC_GFXDECODE("gfxdecode")
532	532	MCFG_DECO16IC_PALETTE("palette")
533
	533
534	534	MCFG_DECO16IC_ADD("tilegen2", backfire_deco16ic_tilegen2_intf)
535	535	MCFG_DECO16IC_SET_SCREEN("lscreen")
536	536	MCFG_DECO16IC_GFXDECODE("gfxdecode")

trunk/src/mame/drivers/ltcasino.c
r29404	r29405
658	658	MCFG_SCREEN_REFRESH_RATE(60)
659	659	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
660	660	MCFG_SCREEN_SIZE(648, 328)
661		MCFG_SCREEN_VISIBLE_AREA(68, 588-1, 0, 32*8-1)
	661	MCFG_SCREEN_VISIBLE_AREA(68, 588-1, 0, 32*8-1)
662	662	MCFG_SCREEN_UPDATE_DRIVER(ltcasino_state, screen_update_ltcasino)
663	663	MCFG_SCREEN_PALETTE("palette")
664	664

trunk/src/mame/drivers/coolridr.c
r29404	r29405
3546	3546
3547	3547	WRITE8_MEMBER(coolridr_state::scsp_irq)
3548	3548	{
3549		m_soundcpu->set_input_line(offset, data);
	3549	m_soundcpu->set_input_line(offset, data);
3550	3550	}
3551	3551
3552	3552	WRITE_LINE_MEMBER(coolridr_state::scsp1_to_sh1_irq)

trunk/src/mame/drivers/mpu4hw.c
r29404	r29405
2094	2094	LOG_CHR(("Characteriser read data %02X \n",m_current_chr_table[m_prot_col].response));
2095	2095	return m_current_chr_table[m_prot_col].response;
2096	2096	}
2097
	2097
2098	2098	if (offset == 3)
2099	2099	{
2100	2100	LOG_CHR(("Characteriser read data off 3 %02X \n",m_current_chr_table[m_lamp_col+64].response));
r29404	r29405
2395	2395	// 6 0 7 0 8 0 7 0 0 8
2396	2396	//request 36 42 27 42 09 42 27 42 42 09
2397	2397	//verify 00 04 04 0C 0C 1C 14 2C 5C 2C
2398
	2398
2399	2399	DRIVER_INIT_MEMBER(mpu4_state,m_oldtmr)
2400	2400	{
2401	2401	m_reel_mux=SIX_REEL_1TO8;

trunk/src/mame/drivers/intrscti.c
r29404	r29405
24	24	m_subcpu(*this,"subcpu"),
25	25	m_vram(*this, "vram"),
26	26	m_gfxdecode(*this, "gfxdecode"),
27		m_palette(*this, "palette")
	27	m_palette(*this, "palette")
28	28	{ }
29	29
30	30	required_device<cpu_device> m_maincpu;

trunk/src/mame/drivers/mgolf.c
r29404	r29405
40	40	required_device<gfxdecode_device> m_gfxdecode;
41	41	required_device<screen_device> m_screen;
42	42	required_device<palette_device> m_palette;
43
	43
44	44	DECLARE_WRITE8_MEMBER(mgolf_vram_w);
45	45	DECLARE_READ8_MEMBER(mgolf_wram_r);
46	46	DECLARE_READ8_MEMBER(mgolf_dial_r);

trunk/src/mame/drivers/rungun.c
r29404	r29405
402	402	MCFG_K055673_ADD("k055673", rng_k055673_intf)
403	403	MCFG_K055673_GFXDECODE("gfxdecode")
404	404	MCFG_K055673_PALETTE("palette")
405
	405
406	406	MCFG_DEVICE_ADD("k053252", K053252, 16000000/2)
407	407	MCFG_K053252_OFFSETS(9*8, 24)
408	408

trunk/src/mame/mame.lst
r29404	r29405
165	165	galaxiant // (c) Taito
166	166	galaxiani // (c) Irem
167	167	galaxrf // bootleg (Recreativos Franco)
168		galaxrfgg // bootleg (Recreativos Franco)
	168	galaxrfgg // bootleg (Recreativos Franco)
169	169	superg // hack
170	170	galapx // hack
171	171	moonaln // [Nichibutsu] (Karateco license) or hack
r29404	r29405
177	177	starfght // hack
178	178	galaxbsf // hack
179	179	galaxianbl // bootleg
180		galaxbsf2 // bootleg
	180	galaxbsf2 // bootleg
181	181	kamakazi3 // Video Games (UK) Ltd., hack or bootleg?
182	182	tst_galx // Galaxian Test ROM
183	183	gmgalax // bootleg
r29404	r29405
338	338	hotshockb // bootleg
339	339	conquer // (c) 1982 ????
340	340	hunchbks // (c) 1983 Century
341		hunchbks2 // bootleg
	341	hunchbks2 // bootleg
342	342	hncholms // (c) 1984 Century
343	343	cavelon // (c) 1983 Jetsoft
344	344	sfx // (c) 1983 Nichibutsu
r29404	r29405
380	380	hustlerb // bootleg
381	381	hustlerb2 // bootleg
382	382	hustlerb3 // bootleg
383		hustlerb4 // bootleg
	383	hustlerb4 // bootleg
384	384	frogger // GX392 (c) 1981 Konami
385	385	froggers1 // (c) 1981 Sega
386	386	froggers2 // 834-0068 (c) 1981 Sega
r29404	r29405
1654	1654	blasted // (c) 1988
1655	1655	archrivl // (c) 1989
1656	1656	archrivla // (c) 1989
1657		archrivlb // bootleg
	1657	archrivlb // bootleg
1658	1658	trisport // (c) 1989
1659	1659	pigskin // (c) 1990
1660	1660	pigskina // (c) 1990
r29404	r29405
1866	1866	gunforc2 // (c) 1994 Irem
1867	1867	geostorm // (c) 1994 Irem (Japan)
1868	1868	// M107
1869		airass // (c) 1993 Irem (World)
	1869	airass // (c) 1993 Irem (World)
1870	1870	firebarr // (c) 1993 Irem (Japan)
1871	1871	dsoccr94 // (c) 1994 Irem (Data East Corporation license)
1872	1872	kftgoal // (c) 1994 Jaleco
r29404	r29405
2246	2246	masterw // B72 (c) 1989 Taito Corporation Japan (World)
2247	2247	masterwu // B72 (c) 1989 Taito America Corporation (US)
2248	2248	masterwj // B72 (c) 1989 Taito Corporation (Japan)
2249		yukiwo // prototype
	2249	yukiwo // prototype
2250	2250	nastar // B81 (c) 1988 Taito Corporation Japan (World)
2251	2251	nastarw // B81 (c) 1988 Taito America Corporation (US)
2252	2252	rastsag2 // B81 (c) 1988 Taito Corporation (Japan)
r29404	r29405
2286	2286	contcircj // B33 (c) 1987 Taito Corporation (Japan)
2287	2287	chasehq // B52 (c) 1988 Taito Corporation Japan (World)
2288	2288	chasehqj // B52 (c) 1988 Taito Corporation (Japan)
2289		chasehqju // B52 (c) 1988 Taito Corporation (Japan)
	2289	chasehqju // B52 (c) 1988 Taito Corporation (Japan)
2290	2290	chasehqu // B52 (c) 1988 Taito America Corporation (US)
2291	2291	enforce // B58 (c) 1988 Taito Corporation Japan (World)
2292	2292	enforcej // B58 (c) 1988 Taito Corporation (Japan)
r29404	r29405
2581	2581	twincobru // B30 / TP-011 (c) 1987 Taito America Corporation + Romstar license (US)
2582	2582	ktiger // B30 / TP-011 (c) 1987 Taito Corporation (Japan)
2583	2583	gulfwar2 // (c) 1991 Comad
2584		gulfwar2a //
	2584	gulfwar2a //
2585	2585	rallybik // B45 / TP-O12 (c) 1988 Taito
2586	2586	truxton // B65 / TP-O13B (c) 1988 Taito
2587	2587	hellfire // B90 / TP-??? (c) 1989 Toaplan + Taito license
r29404	r29405
2674	2674	batsuguna // TP-030 (c) 1993 Toaplan
2675	2675	batsugunsp // TP-030 (c) 1993 Toaplan
2676	2676	snowbro2 // TP-033 (c) 1994 Hanafram
2677		snowbro2b //
	2677	snowbro2b //
2678	2678	pwrkick // (c) 1994 Sunwise
2679	2679	othldrby // (c) 1995 Sunwise
2680	2680	sstriker // (c) 1993 Raizing
r29404	r29405
2796	2796	crusherm // (c) 1999 Takumi
2797	2797	tjumpman // (c) 1999 Namco
2798	2798
2799		mushisam
	2799	mushisam
2800	2800	mushisama
2801	2801	mushisamb
2802		espgal2
2803		ibara
2804		ibarablk
2805		ibarablka
2806		mushitam
	2802	espgal2
	2803	ibara
	2804	ibarablk
	2805	ibarablka
	2806	mushitam
2807	2807	mushitama
2808		futari15
2809		futari15a
2810		futari10
2811		futaribl
2812		pinkswts
2813		pinkswtsa
	2808	futari15
	2809	futari15a
	2810	futari10
	2811	futaribl
	2812	pinkswts
	2813	pinkswtsa
2814	2814	pinkswtsb
2815		pinkswtsx
2816		deathsml
2817		mmpork
	2815	pinkswtsx
	2816	deathsml
	2817	mmpork
2818	2818	mmmbanc
2819	2819	ddpdfk
2820	2820	ddpdfk10
r29404	r29405
2943	2943	trojana // 4/1986 (c) 1986 (US)
2944	2944	trojanr // 4/1986 (c) 1986 + Romstar
2945	2945	trojanj // 4/1986 (c) 1986 (Japan)
2946		trojanb // bootleg
	2946	trojanb // bootleg
2947	2947	srumbler // 9/1986 (c) 1986
2948	2948	srumbler2 // 9/1986 (c) 1986
2949	2949	srumbler3 // 9/1986 (c) 1986 + Tecfri
r29404	r29405
3133	3133	sf2v004 // hack
3134	3134	sf2acc // hack
3135	3135	sf2acca // hack
3136		sf2ceblp // hack
	3136	sf2ceblp // hack
3137	3137	sf2accp2 // hack
3138	3138	sf2amf // bootleg
3139		sf2amf2 // bootleg
	3139	sf2amf2 // bootleg
3140	3140	sf2dkot2 // hack
3141	3141	sf2m1 // hack
3142	3142	sf2m2 // hack
r29404	r29405
3151	3151	sf2dongb // hack
3152	3152	sf2mdt // bootleg
3153	3153	sf2mdta // bootleg
3154		sf2mdtb // bootleg
	3154	sf2mdtb // bootleg
3155	3155	cworld2j // 11/06/1992 (c) 1992 (Japan)
3156	3156	varth // 14/07/1992 (c) 1992 (World)
3157	3157	varthr1 // 12/06/1992 (c) 1992 (World)
r29404	r29405
3315	3315	mshh // 17/11/1995 (c) 1995 (Hispanic)
3316	3316	mshb // 17/11/1995 (c) 1995 (Brazil)
3317	3317	19xx // 07/12/1995 (c) 1996 (USA)
3318		19xxj // 04/01/1996 (c) 1996 (Japan)
	3318	19xxj // 04/01/1996 (c) 1996 (Japan)
3319	3319	19xxjr1 // 25/12/1995 (c) 1996 (Japan)
3320	3320	19xxjr2 // 07/12/1995 (c) 1996 (Japan)
3321	3321	19xxa // 07/12/1995 (c) 1996 (Asia)
r29404	r29405
3503	3503	warzardr1 // 23/10/1996 (c) 1996 (Japan)
3504	3504	sfiii // 04/02/1997 (c) 1997 (Euro)
3505	3505	sfiiiu // 04/02/1997 (c) 1997 (USA)
3506		sfiiia // 04/02/1997 (c) 1997 (Asia)
	3506	sfiiia // 04/02/1997 (c) 1997 (Asia)
3507	3507	sfiiij // 04/02/1997 (c) 1997 (Japan)
3508	3508	sfiiih // 04/02/1997 (c) 1997 (Hispanic)
3509	3509	sfiii2 // 30/09/1997 (c) 1997 (USA)
r29404	r29405
3521	3521	jojoba // 27/09/1999 (c) 1999 (Japan)
3522	3522	jojobar1 // 13/09/1999 (c) 1999 (Japan)
3523	3523	sfiiin // 04/02/1997 (c) 1997 (Asia)
3524		sfiiina // 04/02/1997 (c) 1997 (Asia)
	3524	sfiiina // 04/02/1997 (c) 1997 (Asia)
3525	3525	sfiii2n // 30/09/1997 (c) 1997 (Asia)
3526	3526	jojon // 28/01/1999 (c) 1998 (Asia)
3527	3527	jojonr1 // 08/01/1999 (c) 1998 (Asia)
r29404	r29405
3534	3534	jojobaner1 // 13/09/1999 (c) 1999 (Euro)
3535	3535	cps3boot // bootleg
3536	3536	cps3boota // bootleg
3537		cps3bs32 //
3538		cps3bs32a //
	3537	cps3bs32 //
	3538	cps3bs32a //
3539	3539
3540	3540	// Capcom ZN1
3541	3541	cpzn1
r29404	r29405
3774	3774	golgo13 // 2000.03 Golgo 13 (GLG1/VER.A, Japan)
3775	3775	sws2000 // 2000.03 Super World Stadium 2000 (SS01/VER.A, Japan)
3776	3776	truckk // 2000.06 Truck Kyousoukyoku (Metro)
3777		kartduel // 2000.07 Kart Duel
	3777	kartduel // 2000.07 Kart Duel
3778	3778	// 2000.08 Teknowerk
3779	3779	g13knd // 2000.10 Golgo 13 Kiseki no Dandou (GLS1/VER.A, Japan)
3780	3780	sws2001 // 2001.04 Super World Stadium 2001 (SS11/VER.A, Japan)
r29404	r29405
4465	4465	fantzone // (c) 1986 (Unprotected Rev A)
4466	4466	fantzone1 // (c) 1986 (Unprotected)
4467	4467	fantzonep // (c) 1986 (NEC 0317-5000, encrypted)
4468		fantzonepr //
	4468	fantzonepr //
4469	4469	sdi // (c) 1987 (FD1089B, decrypted)
4470	4470	shinobi // (c) 1987 (Unprotected)
4471	4471	shinobi1 // (c) 1987 (FD1094, decrypted)
r29404	r29405
4741	4741	radrj // 1991.07 Rad Rally (Japan)
4742	4742	spidman // 1991.?? Spiderman (World)
4743	4743	spidmanu // 1991.09 Spiderman (US)
4744		spidmanj // 1991.09 Spiderman (Japan)
	4744	spidmanj // 1991.09 Spiderman (Japan)
4745	4745	f1en // 1991.?? F-1 Exhaust Note (World)
4746	4746	// 1992.01 F-1 Exhaust Note (US)
4747	4747	// 1991.11 F-1 Exhaust Note (Japan)
r29404	r29405
5419	5419	initdv2jo // 2002.12 Initial D Arcade Stage Ver. 2 (Japan)
5420	5420	initdv2e // 2002.12 Initial D Arcade Stage Ver. 2 (export)
5421	5421	vf4evo // 2002.12 Virtua Fighter 4 Evolution Ver.B
5422		clubk2k3 // 2003.?? Club Kart: European Session 2003
	5422	clubk2k3 // 2003.?? Club Kart: European Session 2003
5423	5423	clubk2kf
5424	5424	initdexp // 2002.?? Initial D Arcade Stage (Export)
5425	5425	// 2002.?? Sega Driving Simulator
r29404	r29405
5706	5706	afire // Rene Pierre
5707	5707	acombat // bootleg
5708	5708	acombato // bootleg
5709		acombat3 // bootleg
	5709	acombat3 // bootleg
5710	5710	sstarbtl // bootleg
5711	5711	spfghmk2 // (c) [1979] Data East Corporation
5712	5712	spfghmk22 // (c) [1979] Data East Corporation
r29404	r29405
5770	5770	pcktgal2 // (c) 1989 Data East Corporation (World?)
5771	5771	pcktgal2j // (c) 1989 Data East Corporation (World?)
5772	5772	pokechmp // Korean hack of Pocket Gal
5773		billlist //
	5773	billlist //
5774	5774	spool3 // (c) 1989 Data East Corporation (World?)
5775	5775	spool3i // (c) 1990 Data East Corporation + I-Vics license
5776	5776	battlera // (c) 1988 Data East Corporation (World)
r29404	r29405
6199	6199	rockragej // GX620 (c) 1986 (Japan)
6200	6200	mx5000 // GX669 (c) 1987
6201	6201	flkatck // GX669 (c) 1987 (Japan)
6202		flkatcka // GX669 (c) 1987 (Japan)
	6202	flkatcka // GX669 (c) 1987 (Japan)
6203	6203	fastlane // GX752 (c) 1987
6204	6204	tricktrp // GX771 (c) 1987
6205	6205	labyrunr // GX771 (c) 1987 (Japan)
r29404	r29405
6662	6662	mtrap // (c) 1981
6663	6663	mtrap3 // (c) 1981
6664	6664	mtrap4 // (c) 1981
6665		mtrapb // bootleg
	6665	mtrapb // bootleg
6666	6666	pepper2 // (c) 1982
6667	6667	pepper27 // (c) 1982
6668	6668	hardhat // (c) 1982
r29404	r29405
8255	8255	raiden2e // (c) 1993 Seibu Kaihatsu
8256	8256	raiden2f // (c) 1993 Seibu Kaihatsu + Fabtek license
8257	8257	raiden2g // (c) 1993 Seibu Kaihatsu
8258		raiden2nl // (c) 1993 Seibu Kaihatsu
	8258	raiden2nl // (c) 1993 Seibu Kaihatsu
8259	8259	raidendx // (c) 1994 Seibu Kaihatsu
8260	8260	raidendxj // (c) 1994 Seibu Kaihatsu
8261	8261	raidendxu // (c) 1994 Seibu Kaihatsu + Fabtek license
8262	8262	raidendxa1 // (c) 1994 Seibu Kaihatsu + Metrotainment license
8263	8263	raidendxa2 // (c) 1994 Seibu Kaihatsu + Metrotainment license
8264	8264	raidendxg // (c) 1994 Seibu Kaihatsu + Tuning license
8265		raidendxnl // (c) 1994 Seibu Kaihatsu
	8265	raidendxnl // (c) 1994 Seibu Kaihatsu
8266	8266	zeroteam // (c) 1993 Seibu Kaihatsu + Fabtek license
8267	8267	zeroteama // (c) 1993 Seibu Kaihatsu
8268	8268	zeroteamb // (c) 1993 Seibu Kaihatsu
r29404	r29405
8287	8287	batlballu // (c) 1995 Seibu Kaihatsu (Fabtek license)
8288	8288
8289	8289	viprp1 // (c) 1995 Seibu Kaihatsu
8290		viprp1k // (c) 1995 Seibu Kaihatsu (Dream Island license)
	8290	viprp1k // (c) 1995 Seibu Kaihatsu (Dream Island license)
8291	8291	viprp1u // (c) 1995 Seibu Kaihatsu (Fabtek license)
8292	8292	viprp1ua // (c) 1995 Seibu Kaihatsu (Fabtek license)
8293	8293	viprp1j // (c) 1995 Seibu Kaihatsu
r29404	r29405
8724	8724	galsnewk // (c) 1990 Kaneko
8725	8725	galpani2 // (c) 1993 Kaneko
8726	8726	galpani2e // (c) 1993 Kaneko
8727		galpani2e2 // (c) 1993 Kaneko
	8727	galpani2e2 // (c) 1993 Kaneko
8728	8728	galpani2g // (c) 1993 Kaneko
8729	8729	galpani2t // (c) 1993 Kaneko
8730	8730	galpani2i // (c) 1993 Kaneko
8731		galpani2gs // (c) 1993 Kaneko
	8731	galpani2gs // (c) 1993 Kaneko
8732	8732	galpani2j // (c) 1993 Kaneko
8733	8733	gp2quiz // (c) 1993 Kaneko
8734	8734	gp2se // (c) 1994 Kaneko
r29404	r29405
8737	8737	galpani3 // (c) 1995 Kaneko (World)
8738	8738	galpani3j // (c) 1995 Kaneko (Japan)
8739	8739	galpani3k // (c) 1995 Kaneko (Korea)
8740		galpani3hk // (c) 1995 Kaneko (Hong Kong)
	8740	galpani3hk // (c) 1995 Kaneko (Hong Kong)
8741	8741
8742	8742	// Kaneko "AX System" games
8743	8743	berlwall // (c) 1991 Kaneko
r29404	r29405
8838	8838	blandia // (c) 1992 Allumer
8839	8839	blandiap // (c) 1992 Allumer
8840	8840	blockcar // (c) 1992 Visco
8841		blockcarb // bootleg
	8841	blockcarb // bootleg
8842	8842	qzkklogy // (c) 1992 Tecmo
8843	8843	neobattl // (c) 1992 Banpresto / Sotsu Agency. Sunrise
8844	8844	umanclub // (c) 1992 Tsuburaya Prod. / Banpresto
r29404	r29405
9066	9066	lastdaya // (c) 1990 Dooyong
9067	9067	gulfstrm // (c) 1991 Dooyong
9068	9068	gulfstrma // (c) 1991 Dooyong
9069		gulfstrmb // (c) 1991 Dooyong
	9069	gulfstrmb // (c) 1991 Dooyong
9070	9070	gulfstrmm // (c) 1991 Dooyong + distributed by Media Shoji
9071	9071	pollux // (c) 1991 Dooyong
9072	9072	polluxa // (c) 1991 Dooyong
9073	9073	polluxa2 // (c) 1991 Dooyong
9074	9074	flytiger // (c) 1992 Dooyong
9075		flytigera // (c) 1992 Dooyong
	9075	flytigera // (c) 1992 Dooyong
9076	9076	bluehawk // (c) 1993 Dooyong
9077	9077	bluehawkn // (c) 1993 NTC
9078	9078	sadari // (c) 1993 NTC
r29404	r29405
9117	9117	fantsia2 // (c) 1997 Comad
9118	9118	fantsia2a // (c) 1997 Comad
9119	9119	wownfant // (c) 2002 Comad
9120		pgalvip // (c) 1996 ACE International (Afega stickers on ROMs)
9121		pgalvipa //
	9120	pgalvip // (c) 1996 ACE International (Afega stickers on ROMs)
	9121	pgalvipa //
9122	9122	galhustl // (c) 1997 ACE International
9123	9123
9124	9124	// Playmark games
r29404	r29405
9245	9245	bombkick // (c) 1998 Yun Sung
9246	9246	bombkicka // (c) 1998 Yun Sung
9247	9247	nmg5 // (c) 1998 Yun Sung
9248		nmg5a // (c) 1998 Yun Sung
	9248	nmg5a // (c) 1998 Yun Sung
9249	9249	nmg5e // (c) 1998 Yun Sung
9250	9250	searchey // (c) 1999 Yun Sung
9251	9251	searchp2 // (c) 1999 Yun Sung
r29404	r29405
9672	9672	oldsplus // (c) 2004 Oriental Legend Super Plus
9673	9673	killbldp // (c) 2004 Killing Blade Plus
9674	9674	happy6 // (c) 2004 Happy 6
9675		happy6101 //
	9675	happy6101 //
9676	9676	svg // (c) 2003 Spectral vs Generation
9677	9677	svgpcb //
9678	9678	ket // (c) 2002 Ketsui
r29404	r29405
9690	9690	orleg2o //
9691	9691	kov2nl // (c) 2008
9692	9692	kov2nlo //
9693		ddpdojh //
9694		kov3 //
	9693	ddpdojh //
	9694	kov3 //
9695	9695
9696	9696	// IGS PC based HW
9697	9697	speeddrv // (c) 2004
r29404	r29405
10105	10105	nostk // (c) 1993 Face
10106	10106	4enraya // (c) 1990 IDSA
10107	10107	4enrayaa //
10108		4enlinea // (c) 1991 System Compumatic
	10108	4enlinea // (c) 1991 System Compumatic
10109	10109	unkpacg // (c) 19?? ???
10110	10110	oneshot // no copyright notice
10111	10111	maddonna // (c) 1995 Tuning
r29404	r29405
10123	10123	9ballsht2 // (c) 1993 E-Scape EnterMedia + "marketed by Bundra Games"
10124	10124	9ballsht3 // (c) 1993 E-Scape EnterMedia + "marketed by Bundra Games"
10125	10125	9ballshtc // (c) 1993 E-Scape EnterMedia + "marketed by Bundra Games"
10126		megaphx // (c) 1991 Dinamic / Inder
	10126	megaphx // (c) 1991 Dinamic / Inder
10127	10127	gumbo // (c) 1994 Min Corp.
10128	10128	mspuzzleg // (c) 1994 Min Corp.
10129	10129	mspuzzle // (c) 1994 Min Corp.
r29404	r29405
11081	11081	livequiz // (c) 1999 Andamiro
11082	11082	hammer // (c) 2000 Andamiro
11083	11083	discoboy // (c) 1993 Soft Art Co.
11084		discoboyp // (c) 1993 Soft Art Co. (Promat license?)
	11084	discoboyp // (c) 1993 Soft Art Co. (Promat license?)
11085	11085	pangofun // (c) 1995 InfoCube
11086	11086	koikoi // (c) 1983 Kiwako
11087	11087	good // (c) 1998
r29404	r29405
11089	11089	quizo // (c) 1985 Seoul Coin Corp.
11090	11090	quizoa // (c) 1985 Seoul Coin Corp.
11091	11091	gstream // (c) 2002, Oriental Soft Japan
11092		x2222 // (c) 2000, Oriental Soft
11093		x2222o // (c) 2000, Oriental Soft
	11092	x2222 // (c) 2000, Oriental Soft
	11093	x2222o // (c) 2000, Oriental Soft
11094	11094	miniboy7 // (c) 1983, Bonanza Enterprises
11095	11095	miniboy7a // (c) 1983, Bonanza Enterprises
11096	11096	miniboy7b // (c) 1983, Bonanza Enterprises
r29404	r29405
11252	11252	grandprx // (c) 200? 4fun
11253	11253	supjolly // (c) 200? unknown
11254	11254	x5jokers // (c) 200? Electronic Projects
11255		queenotg //
11256		ejollyx9 //
	11255	queenotg //
	11256	ejollyx9 //
11257	11257
11258	11258	// Astro Corp.
11259	11259	showhand // (c) 2000 Astro Corp.
r29404	r29405
29477	29477	ec_casmb // Casino Multi Bar (Concept - Electrocoin)
29478	29478	ec_supmb // Super Multi Bar (Concept - Electrocoin)
29479	29479	ec_stkex // Stake X (Concept - Electrocoin)
29480		ec_bar7 // Bar 7 (Concept)
	29480	ec_bar7 // Bar 7 (Concept)
29481	29481	ec_fltr // Flutter (Concept)
29482	29482	ec_gold7 // Golden 7 (Concept)
29483	29483	ec_mgbel // Megabell (Concept)
r29404	r29405
31258	31258	number1 // 1996 San Remo Games
31259	31259	gluck2 // 1992 Yung Yu / CYE
31260	31260
31261		amusco // 1987, Amusco.
		No newline at end of file
	31261	amusco // 1987, Amusco.

trunk/src/mame/audio/cclimber.c
r29404	r29405
41	41	MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":mono", 0.50)
42	42
43	43	MCFG_SAMPLES_ADD("samples", cclimber_samples_interface)
44		MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":mono", 0.5)
45		MACHINE_CONFIG_END
	44	MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":mono", 0.5)
	45	MACHINE_CONFIG_END
46	46
47	47	//**************************************************************************
48	48	// DEVICE DEFINITIONS
r29404	r29405
136	136
137	137	m_samples->start_raw(0,samplebuf,2 * len,freq);
138	138	}
139

trunk/src/mame/audio/cclimber.h
r29404	r29405
28	28	#define MCFG_CCLIMBER_AUDIO_ADD(_tag) \
29	29	MCFG_DEVICE_ADD(_tag, CCLIMBER_AUDIO, 0)
30	30
31
	31
32	32	// ======================> cclimber_audio_device
33	33
34	34	class cclimber_audio_device : public device_t
r29404	r29405
41	41	DECLARE_WRITE8_MEMBER( sample_rate_w );
42	42	DECLARE_WRITE8_MEMBER( sample_volume_w );
43	43	DECLARE_WRITE8_MEMBER( sample_select_w );
44
	44
45	45	protected:
46		// device level overrides
47		virtual void device_start();
	46	// device level overrides
	47	virtual void device_start();
48	48	virtual machine_config_constructor device_mconfig_additions() const;
49	49
50	50	void play_sample(int start,int freq,int volume);
51		private:
	51	private:
52	52	int m_sample_num;
53	53	int m_sample_freq;
54	54	int m_sample_volume;

trunk/src/mame/audio/namco52.c
r29404	r29405
166	166	m_basenode(0),
167	167	m_extclock(0),
168	168	m_romread(*this),
169		m_si(*this)
	169	m_si(*this)
170	170	{
171	171	}
172	172

trunk/src/mame/audio/namco52.h
r29404	r29405
23	23
24	24	#define MCFG_NAMCO_52XX_SI_CB(_devcb) \
25	25	devcb = &namco_52xx_device::set_si_callback(*device, DEVCB2_##_devcb);
26
27	26
	27
28	28	class namco_52xx_device : public device_t
29	29	{
30	30	public:
r29404	r29405
35	35	static void set_extclock(device_t &device, attoseconds_t clk) { downcast<namco_52xx_device &>(device).m_extclock = clk; }
36	36	template<class _Object> static devcb2_base &set_romread_callback(device_t &device, _Object object) { return downcast<namco_52xx_device &>(device).m_romread.set_callback(object); }
37	37	template<class _Object> static devcb2_base &set_si_callback(device_t &device, _Object object) { return downcast<namco_52xx_device &>(device).m_si.set_callback(object); }
38
	38
39	39	DECLARE_WRITE8_MEMBER(write);
40	40
41	41	DECLARE_READ8_MEMBER( K_r );
r29404	r29405
52	52	virtual void device_start();
53	53	virtual const rom_entry *device_rom_region() const;
54	54	virtual machine_config_constructor device_mconfig_additions() const;
55
	55
56	56	TIMER_CALLBACK_MEMBER( latch_callback );
57	57	TIMER_CALLBACK_MEMBER( irq_clear );
58	58	TIMER_CALLBACK_MEMBER( external_clock_pulse );
r29404	r29405
60	60	// internal state
61	61	required_device<mb88_cpu_device> m_cpu;
62	62	required_device<discrete_device> m_discrete;
63
	63
64	64	int m_basenode;
65	65	attoseconds_t m_extclock;
66	66	devcb2_read8 m_romread;
67	67	devcb2_read8 m_si;
68
	68
69	69	UINT8 m_latched_cmd;
70	70	UINT32 m_address;
71	71	};

trunk/src/mame/audio/taito_zm.c
r29404	r29405
55	55	void taito_zoom_device::device_start()
56	56	{
57	57	m_snd_shared_ram = auto_alloc_array_clear(machine(), UINT8, 0x100);
58
	58
59	59	// register for savestates
60	60	save_item(NAME(m_reg_address));
61	61	save_item(NAME(m_tms_ctrl));
r29404	r29405
69	69	void taito_zoom_device::device_reset()
70	70	{
71	71	m_reg_address = 0;
72
	72
73	73	m_zsg2->reset();
74	74	}
75	75
r29404	r29405
150	150	popmessage("ZOOM gain L %04X, contact MAMEdev", data);
151	151	m_zsg2->set_output_gain(0, (data & 0x3f) / 63.0);
152	152	break;
153
	153
154	154	case 0x05:
155	155	// zsg2+dsp global volume right
156	156	if (data & 0xc0c0)

trunk/src/mame/audio/taito_zm.h
r29404	r29405
27	27	virtual void device_reset();
28	28
29	29	private:
30
	30
31	31	// devices/pointers
32	32	required_device<mn10200_device> m_soundcpu;
33	33	required_device<zsg2_device> m_zsg2;
34
	34
35	35	// internal state
36	36	UINT16 m_reg_address;
37	37	UINT8 m_tms_ctrl;

trunk/src/mame/audio/cps3.c
r29404	r29405
73	73	-------- -------- xxxxxxxx xxxxxxxx end address high
74	74	7 xxxxxxxx xxxxxxxx -------- -------- volume right (signed?)
75	75	-------- -------- xxxxxxxx xxxxxxxx volume left (signed?)
76
	76
77	77	(*) reg 5 and 6 are always the same. One of them probably means loop-end address,
78	78	but we won't know which until we do tests on real hw.
79	79	*/
r29404	r29405
87	87
88	88	INT16 vol_l = (vptr->regs[7] & 0xffff);
89	89	INT16 vol_r = (vptr->regs[7] >> 16 & 0xffff);
90
	90
91	91	UINT32 pos = vptr->pos;
92	92	UINT32 frac = vptr->frac;
93
	93
94	94	/* TODO */
95	95	start -= 0x400000;
96	96	end -= 0x400000;
r29404	r29405
144	144	else if (offset == 0x80)
145	145	{
146	146	assert((mem_mask & 0xffff0000) == 0xffff0000); // doesn't happen
147
	147
148	148	UINT16 key = data >> 16;
149	149
150	150	for (int i = 0; i < CPS3_VOICES; i++)

trunk/src/mame/audio/namco54.c
r29404	r29405
58	58	}
59	59
60	60	READ8_MEMBER( namco_54xx_device::K_r )
61		{
	61	{
62	62	return m_latched_cmd >> 4;
63	63	}
64	64

trunk/src/mame/audio/taito_en.h
r29404	r29405
19	19	DECLARE_WRITE16_MEMBER( es5510_dsp_w );
20	20
21	21	DECLARE_WRITE_LINE_MEMBER(duart_irq_handler);
22
	22
23	23	DECLARE_WRITE8_MEMBER(mb87078_gain_changed);
24	24
25	25	protected:

trunk/src/mame/audio/namco54.h
r29404	r29405
24	24
25	25	static void set_discrete(device_t &device, const char *tag) { downcast<namco_54xx_device &>(device).m_discrete.set_tag(tag); }
26	26	static void set_basenote(device_t &device, int node) { downcast<namco_54xx_device &>(device).m_basenode = node; }
27
	27
28	28	DECLARE_READ8_MEMBER( K_r );
29	29	DECLARE_READ8_MEMBER( R0_r );
30	30	DECLARE_WRITE8_MEMBER( O_w );
31	31	DECLARE_WRITE8_MEMBER( R1_w );
32
	32
33	33	DECLARE_WRITE8_MEMBER( write );
34	34	protected:
35	35	// device-level overrides
r29404	r29405
43	43	// internal state
44	44	required_device<mb88_cpu_device> m_cpu;
45	45	required_device<discrete_device> m_discrete;
46
	46
47	47	int m_basenode;
48	48	UINT8 m_latched_cmd;
49	49	};

trunk/src/mame/machine/igs036crypt.c
r29404	r29405
8	8	non-trivial obfuscation layered upon a simple address-based XOR encryption
9	9	(similar to the ones found in previous IGS circuits).
10	10
11		The scheme works on 16-bits words and is probably designed to depend on 24 bits of
12		(word-) address; in what follows, we will refer to the 8 lowest ones simply as the
	11	The scheme works on 16-bits words and is probably designed to depend on 24 bits of
	12	(word-) address; in what follows, we will refer to the 8 lowest ones simply as the
13	13	lowest bits of the address, and the other 16 as the highest bits the address.
14	14
15	15	The address-based XOR is thought to be comprised of 16 one-bit XOR controlled
16	16	by a certain combination of one or two of the highest address bits (but only
17		15 of them are observed, probably due to the fact that no game uses more than
	17	15 of them are observed, probably due to the fact that no game uses more than
18	18	2^22 of the 2^24 address space). Every one of the one-bit XORs affects a different bit
19		of the word. The game key acts by masking on/off those XORs for every combination
20		of the lowest address bits. Thus, a complete key can be described by 256 16-bits values.
	19	of the word. The game key acts by masking on/off those XORs for every combination
	20	of the lowest address bits. Thus, a complete key can be described by 256 16-bits values.
21	21	This use of the key is pretty similar to the one found in previous instantiations of
22	22	IGS circuits.
23	23
r29404	r29405
48	48	that region appears to be hiding 20-bytes values (SHA-1 hashes?) located at
49	49	positions which vary per set. See the table below.
50	50
51		driver 20-bytes value position in the ROM
	51	driver 20-bytes value position in the ROM
52	52	--------- ----------------------------------
53	53	orleg2o $763984-$763997
54	54	orleg2 $76C77C-$76C78F
r29404	r29405
77	77	{
78	78	// key-independent manipulation
79	79	int aux = deobfuscate(cipherword, word_address);
80
	80
81	81	// key-dependent manipulation
82	82	for (int i=0; i<16; ++i)
83	83	{
r29404	r29405
87	87	aux ^= (1<<i);
88	88	}
89	89	}
90
	90
91	91	return aux^0x1a3a;
92	92	}
93	93
r29404	r29405
107	107	const int group14[] = {14, 9, 3, 2}; // 14 is a guess
108	108	const int group13[] = {13,10, 6, 1};
109	109	const int group12[] = {12, 8, 4, 0};
110
	110
111	111	// rotation depending on all the address bits
112	112	int enabled0 = rot_enabled(address, group15);
113	113	int rot = enabled0 * rot_group(address, group15) * 9;
114
	114
115	115	int enabled1 = enabled0 ^ rot_enabled(address, group14);
116	116	rot += enabled1 * rot_group(address, group14) * 1;
117
	117
118	118	int enabled2 = enabled0 ^ rot_enabled(address, group13);
119	119	rot += enabled2 * rot_group(address, group13) * 2;
120
	120
121	121	int enabled3 = enabled0 ^ rot_enabled(address, group12);
122	122	rot += enabled3 * rot_group(address, group12) * 4;
123	123
r29404	r29405
143	143	break;
144	144	}
145	145	}
146
	146
147	147	return enabled;
148	148	}
149	149
r29404	r29405
157	157	{
158	158	UINT16 r = num<<shift;
159	159	UINT16 l = num>>(16-shift);
160
	160
161	161	return r\|l;
162	162	}
163	163
r29404	r29405
175	175	// of function on the 8 lowest word-address bits. Some comments:
176	176	// * Bits #5 & #6 are unused so, in fact, they only depend on 6 address bits
177	177	// * The functions are clearly low-complexity boolean functions on those 6 bits
178		// rather than, say, random lookup tables
179		// * There are quite a number of functionally equivalent ways to implement
180		// those boolean functions, so the given implementation (by multiplexing
181		// over some simple functions) shouldn't be taken too seriously: while it's
	178	// rather than, say, random lookup tables
	179	// * There are quite a number of functionally equivalent ways to implement
	180	// those boolean functions, so the given implementation (by multiplexing
	181	// over some simple functions) shouldn't be taken too seriously: while it's
182	182	// functionally correct, it doesn't neccesarily represent the way the hardware
183	183	// is calculating them.
184	184
r29404	r29405
233	233	// if any. The only exception is DDPDOJ (see below).
234	234
235	235	const UINT16 orleg2_key[0x100] = {
236		0x8100, 0x9202, 0x3000, 0x1200, 0x0100, 0x0800, 0x2100, 0xab05,
237		0x130a, 0xba0a, 0x0308, 0x9200, 0x8306, 0xab0f, 0x200c, 0x0301,
238		0x9010, 0x1b13, 0x1310, 0x1b11, 0x8104, 0x0212, 0x8204, 0x8214,
239		0x8302, 0x1111, 0x8300, 0x1b19, 0x0110, 0x8202, 0x0310, 0x0301,
240		0x8322, 0xb202, 0xb200, 0x9121, 0x8222, 0x0a26, 0x2000, 0x0321,
241		0xb000, 0x0020, 0x9328, 0x3909, 0x230a, 0x8929, 0x8224, 0x2204,
242		0x0322, 0x9b33, 0x0300, 0x9311, 0x8120, 0x8810, 0x0330, 0x0004,
243		0x832a, 0x8a0a, 0x0100, 0x1131, 0x0138, 0x093d, 0x8128, 0x081c,
244		0xe342, 0x8101, 0xf140, 0x0000, 0x6144, 0x2004, 0x8204, 0x4044,
245		0xa302, 0xdb4b, 0x1000, 0xa200, 0xc044, 0xe044, 0x010c, 0x0204,
246		0x1212, 0xdb53, 0xd050, 0xcb41, 0x4150, 0xc347, 0x4340, 0x0101,
247		0x5252, 0xd959, 0x1310, 0xc040, 0xc252, 0xc959, 0x4340, 0x8919,
248		0x2202, 0x3800, 0xe340, 0x2101, 0x0326, 0x2307, 0x4360, 0x8321,
249		0x3000, 0xbb0b, 0x5068, 0xf848, 0x436a, 0xab0b, 0xa10c, 0xe240,
250		0xc140, 0xc363, 0x8300, 0x4961, 0x0004, 0xc860, 0x0324, 0x0000,
251		0xd070, 0x8101, 0xd070, 0x1331, 0x0104, 0x4a6e, 0x4348, 0x4a78,
252		0xa282, 0xb282, 0x0200, 0x2200, 0x8180, 0x8080, 0x8080, 0x0800,
253		0x1302, 0x9989, 0x2008, 0x2000, 0xa386, 0x0b0f, 0x828c, 0xa280,
254		0x9392, 0x9292, 0x1010, 0x8080, 0x0206, 0x8383, 0x8294, 0x0911,
255		0x8382, 0x0a0a, 0x9190, 0x1010, 0x0008, 0x0b0b, 0x8098, 0x8b9d,
256		0x1120, 0x0820, 0x2200, 0xa080, 0x81a4, 0xa286, 0xa380, 0xaa80,
257		0x0120, 0x1020, 0xb088, 0x1020, 0x2000, 0x0b2b, 0x2100, 0x2a0c,
258		0x9292, 0x98b0, 0x1330, 0x8880, 0x8396, 0x0b17, 0x8080, 0x0325,
259		0x0000, 0x99b9, 0x92b0, 0x82a0, 0x8184, 0x0020, 0x0330, 0x0818,
260		0xe1c0, 0xa981, 0xd1c0, 0xd0c0, 0x6140, 0x4242, 0xc2c4, 0x6345,
261		0xb088, 0x7141, 0x4040, 0xa181, 0x220e, 0xe0c4, 0x4144, 0x6a4c,
262		0xd0d0, 0x9a92, 0x1310, 0xd9d1, 0x8392, 0xc0c4, 0x8284, 0x8890,
263		0xc0c0, 0x8282, 0x8280, 0x9090, 0x4342, 0x0a0a, 0x4240, 0xc1d5,
264		0xb080, 0xb282, 0xc1e0, 0x90a0, 0xa084, 0x4b63, 0x81a0, 0xeac0,
265		0x7242, 0x5363, 0x7348, 0x0321, 0x022a, 0x6949, 0x4360, 0x8aa8,
266		0x8282, 0x0303, 0x8180, 0x1331, 0x83a2, 0x4b53, 0x4364, 0x83b1,
267		0x121a, 0x80a0, 0x1238, 0x0000, 0x82ba, 0x0030, 0xc0c0, 0x4264,
	236	0x8100, 0x9202, 0x3000, 0x1200, 0x0100, 0x0800, 0x2100, 0xab05,
	237	0x130a, 0xba0a, 0x0308, 0x9200, 0x8306, 0xab0f, 0x200c, 0x0301,
	238	0x9010, 0x1b13, 0x1310, 0x1b11, 0x8104, 0x0212, 0x8204, 0x8214,
	239	0x8302, 0x1111, 0x8300, 0x1b19, 0x0110, 0x8202, 0x0310, 0x0301,
	240	0x8322, 0xb202, 0xb200, 0x9121, 0x8222, 0x0a26, 0x2000, 0x0321,
	241	0xb000, 0x0020, 0x9328, 0x3909, 0x230a, 0x8929, 0x8224, 0x2204,
	242	0x0322, 0x9b33, 0x0300, 0x9311, 0x8120, 0x8810, 0x0330, 0x0004,
	243	0x832a, 0x8a0a, 0x0100, 0x1131, 0x0138, 0x093d, 0x8128, 0x081c,
	244	0xe342, 0x8101, 0xf140, 0x0000, 0x6144, 0x2004, 0x8204, 0x4044,
	245	0xa302, 0xdb4b, 0x1000, 0xa200, 0xc044, 0xe044, 0x010c, 0x0204,
	246	0x1212, 0xdb53, 0xd050, 0xcb41, 0x4150, 0xc347, 0x4340, 0x0101,
	247	0x5252, 0xd959, 0x1310, 0xc040, 0xc252, 0xc959, 0x4340, 0x8919,
	248	0x2202, 0x3800, 0xe340, 0x2101, 0x0326, 0x2307, 0x4360, 0x8321,
	249	0x3000, 0xbb0b, 0x5068, 0xf848, 0x436a, 0xab0b, 0xa10c, 0xe240,
	250	0xc140, 0xc363, 0x8300, 0x4961, 0x0004, 0xc860, 0x0324, 0x0000,
	251	0xd070, 0x8101, 0xd070, 0x1331, 0x0104, 0x4a6e, 0x4348, 0x4a78,
	252	0xa282, 0xb282, 0x0200, 0x2200, 0x8180, 0x8080, 0x8080, 0x0800,
	253	0x1302, 0x9989, 0x2008, 0x2000, 0xa386, 0x0b0f, 0x828c, 0xa280,
	254	0x9392, 0x9292, 0x1010, 0x8080, 0x0206, 0x8383, 0x8294, 0x0911,
	255	0x8382, 0x0a0a, 0x9190, 0x1010, 0x0008, 0x0b0b, 0x8098, 0x8b9d,
	256	0x1120, 0x0820, 0x2200, 0xa080, 0x81a4, 0xa286, 0xa380, 0xaa80,
	257	0x0120, 0x1020, 0xb088, 0x1020, 0x2000, 0x0b2b, 0x2100, 0x2a0c,
	258	0x9292, 0x98b0, 0x1330, 0x8880, 0x8396, 0x0b17, 0x8080, 0x0325,
	259	0x0000, 0x99b9, 0x92b0, 0x82a0, 0x8184, 0x0020, 0x0330, 0x0818,
	260	0xe1c0, 0xa981, 0xd1c0, 0xd0c0, 0x6140, 0x4242, 0xc2c4, 0x6345,
	261	0xb088, 0x7141, 0x4040, 0xa181, 0x220e, 0xe0c4, 0x4144, 0x6a4c,
	262	0xd0d0, 0x9a92, 0x1310, 0xd9d1, 0x8392, 0xc0c4, 0x8284, 0x8890,
	263	0xc0c0, 0x8282, 0x8280, 0x9090, 0x4342, 0x0a0a, 0x4240, 0xc1d5,
	264	0xb080, 0xb282, 0xc1e0, 0x90a0, 0xa084, 0x4b63, 0x81a0, 0xeac0,
	265	0x7242, 0x5363, 0x7348, 0x0321, 0x022a, 0x6949, 0x4360, 0x8aa8,
	266	0x8282, 0x0303, 0x8180, 0x1331, 0x83a2, 0x4b53, 0x4364, 0x83b1,
	267	0x121a, 0x80a0, 0x1238, 0x0000, 0x82ba, 0x0030, 0xc0c0, 0x4264,
268	268	};
269	269
270	270	const UINT16 m312cn_key[0x100] = {

trunk/src/mame/machine/igs036crypt.h
r29404	r29405
10	10	void decrypter_rom(memory_region* region);
11	11	UINT16 decrypt(UINT16 cipherword, int word_address)const;
12	12	UINT16 deobfuscate(UINT16 cipherword, int word_address)const;
13
	13
14	14	private:
15	15	const UINT16* key;
16
	16
17	17	static int (*rot_enabling[16][4])(int);
18	18	static int (*rot_direction[4][8])(int);
19	19	static const UINT16 triggers[16][2];

trunk/src/mame/machine/namco50.c
r29404	r29405
176	176	}
177	177
178	178	void namco_50xx_device::irq_set()
179		{
	179	{
180	180	m_cpu->set_input_line(0, ASSERT_LINE);
181	181
182	182	// The execution time of one instruction is ~4us, so we must make sure to

trunk/src/mame/machine/inder_vid.c
r29404	r29405
13	13
14	14	inder_vid_device::inder_vid_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
15	15	: device_t(mconfig, INDER_VIDEO, "Inder / Dinamic TMS Video", tag, owner, clock, "indervd", __FILE__),
16		/* device_video_interface(mconfig, this, false), /
	16	/* device_video_interface(mconfig, this, false), /
17	17	m_vram(*this, "vram"),
18	18	m_palette(*this, "palette"),
19	19	m_tms(*this, "tms")
r29404	r29405
71	71
72	72	static void megaphx_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
73	73	{
74		// printf("write from shift regs address %08x (%08x)\n", address, TOWORD(address) * 2);
	74	// printf("write from shift regs address %08x (%08x)\n", address, TOWORD(address) * 2);
75	75
76	76	inder_vid_device state = (inder_vid_device)space.machine().device("inder_vid");
77	77
r29404	r29405
125	125
126	126
127	127	MCFG_PALETTE_ADD("palette", 256)
128
	128
129	129	MCFG_RAMDAC_ADD("ramdac", ramdac_intf, ramdac_map, "palette")
130	130
131	131
r29404	r29405
138	138
139	139	void inder_vid_device::device_start()
140	140	{
141
142	141	}
143	142
144	143	void inder_vid_device::device_reset()

trunk/src/mame/machine/namco50.h
r29404	r29405
14	14	{
15	15	public:
16	16	namco_50xx_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
17
	17
18	18	WRITE8_MEMBER( write );
19	19	WRITE_LINE_MEMBER(read_request);
20	20	READ8_MEMBER( read );
21
	21
22	22	READ8_MEMBER( K_r );
23	23	READ8_MEMBER( R0_r );
24	24	READ8_MEMBER( R2_r );
r29404	r29405
29	29	virtual void device_start();
30	30	virtual const rom_entry *device_rom_region() const;
31	31	virtual machine_config_constructor device_mconfig_additions() const;
32
	32
33	33	TIMER_CALLBACK_MEMBER( latch_callback );
34	34	TIMER_CALLBACK_MEMBER( readrequest_callback );
35	35	TIMER_CALLBACK_MEMBER( irq_clear );
36		void irq_set();
	36	void irq_set();
37	37	private:
38	38	// internal state
39	39	required_device<mb88_cpu_device> m_cpu;

trunk/src/mame/machine/inder_vid.h
r29404	r29405
20	20
21	21
22	22	class inder_vid_device : public device_t
23		/* public device_video_interface */
	23	/* public device_video_interface */
24	24	{
25	25	public:
26	26	// construction/destruction
r29404	r29405
29	29	required_shared_ptr<UINT16> m_vram;
30	30	required_device<palette_device> m_palette;
31	31	required_device<tms34010_device> m_tms;
32
	32
33	33	int m_shiftfull; // this might be a driver specific hack for a TMS bug.
34	34
35	35	protected:
r29404	r29405
44	44
45	45	};
46	46
47		#endif
		No newline at end of file
	47	#endif

trunk/src/mame/machine/asteroid.c
r29404	r29405
140	140	MACHINE_RESET_MEMBER(asteroid_state, llander)
141	141	{
142	142	m_dvg->reset_w(m_maincpu->space(AS_PROGRAM), 0, 0);
143		}
		No newline at end of file
	143	}

trunk/src/mame/machine/namco51.h
r29404	r29405
7	7
8	8
9	9	#define MCFG_NAMCO_51XX_ADD(_tag, _clock) \
10		MCFG_DEVICE_ADD(_tag, NAMCO_51XX, _clock)
	10	MCFG_DEVICE_ADD(_tag, NAMCO_51XX, _clock)
11	11
12	12	#define MCFG_NAMCO_51XX_INPUT_0_CB(_devcb) \
13	13	devcb = &namco_51xx_device::set_input_0_callback(*device, DEVCB2_##_devcb);
r29404	r29405
36	36	template<class _Object> static devcb2_base &set_input_1_callback(device_t &device, _Object object) { return downcast<namco_51xx_device &>(device).m_in_1.set_callback(object); }
37	37	template<class _Object> static devcb2_base &set_input_2_callback(device_t &device, _Object object) { return downcast<namco_51xx_device &>(device).m_in_2.set_callback(object); }
38	38	template<class _Object> static devcb2_base &set_input_3_callback(device_t &device, _Object object) { return downcast<namco_51xx_device &>(device).m_in_3.set_callback(object); }
39
	39
40	40	template<class _Object> static devcb2_base &set_output_0_callback(device_t &device, _Object object) { return downcast<namco_51xx_device &>(device).m_out_0.set_callback(object); }
41	41	template<class _Object> static devcb2_base &set_output_1_callback(device_t &device, _Object object) { return downcast<namco_51xx_device &>(device).m_out_1.set_callback(object); }
42
	42
43	43	DECLARE_WRITE8_MEMBER( write );
44	44	DECLARE_READ8_MEMBER( read );
45
	45
46	46	protected:
47	47	// device-level overrides
48	48	virtual void device_start();

trunk/src/mame/machine/megadriv.c
r29404	r29405
1048	1048	m_vdp->set_vdp_pal(FALSE);
1049	1049	m_vdp->set_framerate(60);
1050	1050	m_vdp->set_total_scanlines(262);
1051
1052		m_version_hi_nibble = 0x20; // JPN NTSC no-SCD
	1051
	1052	m_version_hi_nibble = 0x20; // JPN NTSC no-SCD
1053	1053	}
1054	1054
1055	1055
r29404	r29405
1064	1064	m_vdp->set_framerate(60);
1065	1065	m_vdp->set_total_scanlines(262);
1066	1066
1067		m_version_hi_nibble = 0xa0; // Export NTSC no-SCD
	1067	m_version_hi_nibble = 0xa0; // Export NTSC no-SCD
1068	1068	}
1069	1069
1070	1070	DRIVER_INIT_MEMBER(md_base_state, megadrij)
r29404	r29405
1076	1076	m_vdp->set_vdp_pal(FALSE);
1077	1077	m_vdp->set_framerate(60);
1078	1078	m_vdp->set_total_scanlines(262);
1079
1080		m_version_hi_nibble = 0x20; // JPN NTSC no-SCD
	1079
	1080	m_version_hi_nibble = 0x20; // JPN NTSC no-SCD
1081	1081	}
1082	1082
1083	1083	DRIVER_INIT_MEMBER(md_base_state, megadrie)
r29404	r29405
1090	1090	m_vdp->set_framerate(50);
1091	1091	m_vdp->set_total_scanlines(313);
1092	1092
1093		m_version_hi_nibble = 0xe0; // Export PAL no-SCD
	1093	m_version_hi_nibble = 0xe0; // Export PAL no-SCD
1094	1094	}
1095	1095
1096	1096	void md_base_state::screen_eof_megadriv(screen_device &screen, bool state)

trunk/src/mame/machine/namco53.c
r29404	r29405
69	69	READ8_MEMBER( namco_53xx_device::Rx_r )
70	70	{
71	71	switch(offset) {
72		case 0 : return m_in_0(0);
73		case 1 : return m_in_1(0);
74		case 2 : return m_in_2(0);
75		case 3 : return m_in_3(0);
	72	case 0 : return m_in_0(0);
	73	case 1 : return m_in_1(0);
	74	case 2 : return m_in_2(0);
	75	case 3 : return m_in_3(0);
76	76	default : return 0xff;
77	77	}
78
	78
79	79	}
80	80
81	81	WRITE8_MEMBER( namco_53xx_device::O_w )

trunk/src/mame/machine/namco53.h
r29404	r29405
26	26	#define MCFG_NAMCO_53XX_P_CB(_devcb) \
27	27	devcb = &namco_53xx_device::set_p_port_callback(*device, DEVCB2_##_devcb);
28	28
29
	29
30	30	class namco_53xx_device : public device_t
31	31	{
32	32	public:
r29404	r29405
36	36	template<class _Object> static devcb2_base &set_input_1_callback(device_t &device, _Object object) { return downcast<namco_53xx_device &>(device).m_in_1.set_callback(object); }
37	37	template<class _Object> static devcb2_base &set_input_2_callback(device_t &device, _Object object) { return downcast<namco_53xx_device &>(device).m_in_2.set_callback(object); }
38	38	template<class _Object> static devcb2_base &set_input_3_callback(device_t &device, _Object object) { return downcast<namco_53xx_device &>(device).m_in_3.set_callback(object); }
39
	39
40	40	template<class _Object> static devcb2_base &set_k_port_callback(device_t &device, _Object object) { return downcast<namco_53xx_device &>(device).m_k.set_callback(object); }
41	41	template<class _Object> static devcb2_base &set_p_port_callback(device_t &device, _Object object) { return downcast<namco_53xx_device &>(device).m_p.set_callback(object); }
42	42
r29404	r29405
44	44	DECLARE_READ8_MEMBER( Rx_r );
45	45	DECLARE_WRITE8_MEMBER( O_w );
46	46	DECLARE_WRITE8_MEMBER( P_w );
47
	47
48	48	DECLARE_WRITE_LINE_MEMBER(read_request);
49	49	DECLARE_READ8_MEMBER( read );
50	50
r29404	r29405
53	53	virtual void device_start();
54	54	virtual const rom_entry *device_rom_region() const;
55	55	virtual machine_config_constructor device_mconfig_additions() const;
56
	56
57	57	TIMER_CALLBACK_MEMBER( irq_clear );
58	58	private:
59	59	// internal state
60	60	required_device<mb88_cpu_device> m_cpu;
61	61	UINT8 m_portO;
62	62	devcb2_read8 m_k;
63		devcb2_read8 m_in_0;
64		devcb2_read8 m_in_1;
65		devcb2_read8 m_in_2;
66		devcb2_read8 m_in_3;
	63	devcb2_read8 m_in_0;
	64	devcb2_read8 m_in_1;
	65	devcb2_read8 m_in_2;
	66	devcb2_read8 m_in_3;
67	67	devcb2_write8 m_p;
68	68
69	69	};

trunk/src/mame/machine/cdi070.h
r29404	r29405
154	154
155	155	DECLARE_READ16_MEMBER(periphs_r);
156	156	DECLARE_WRITE16_MEMBER(periphs_w);
157
	157
158	158	DECLARE_READ16_MEMBER(uart_loopback_enable);
159	159
160	160	TIMER_CALLBACK_MEMBER( timer0_callback );

trunk/src/mame/machine/namco62.h
r29404	r29405
34	34	template<class _Object> static devcb2_base &set_input_1_callback(device_t &device, _Object object) { return downcast<namco_62xx_device &>(device).m_in_1.set_callback(object); }
35	35	template<class _Object> static devcb2_base &set_input_2_callback(device_t &device, _Object object) { return downcast<namco_62xx_device &>(device).m_in_2.set_callback(object); }
36	36	template<class _Object> static devcb2_base &set_input_3_callback(device_t &device, _Object object) { return downcast<namco_62xx_device &>(device).m_in_3.set_callback(object); }
37
	37
38	38	template<class _Object> static devcb2_base &set_output_0_callback(device_t &device, _Object object) { return downcast<namco_62xx_device &>(device).m_out_0.set_callback(object); }
39	39	template<class _Object> static devcb2_base &set_output_1_callback(device_t &device, _Object object) { return downcast<namco_62xx_device &>(device).m_out_1.set_callback(object); }
40
	40
41	41	DECLARE_READ8_MEMBER( read );
42	42	DECLARE_WRITE8_MEMBER( write );
43	43

trunk/src/mame/machine/gaelco3d.h
r29404	r29405
64	64	public:
65	65	gaelco_serial_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
66	66	~gaelco_serial_device() {}
67
	67
68	68	template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<gaelco_serial_device &>(device).m_irq_handler.set_callback(object); }
69	69
70	70	DECLARE_READ8_MEMBER( status_r);

trunk/src/mame/machine/naomim4.c
r29404	r29405
139	139	if (rombdid_tag && memregion(rombdid_tag) != NULL)
140	140	{
141	141	fpr_num = *memregion(rombdid_tag)->base() & 0x7f;
142
	142
143	143	}
144	144
145	145	if (((rom_cur_address >> 26) & 0x07) < fpr_num) {
r29404	r29405
210	210	if (rombdid_tag && memregion(rombdid_tag) != NULL)
211	211	{
212	212	epr_flag = *memregion(rombdid_tag)->base() & 0x80;
213
	213
214	214	}
215	215
216	216	return 0x5500 \| epr_flag;
r29404	r29405
222	222	cfi_mode = true;
223	223	if (((offset&0xffff) == 0x0000) && (data == 0x00f0))
224	224	cfi_mode = false;
225		}
		No newline at end of file
	225	}

trunk/src/mame/machine/slapfght.c
r29404	r29405
41	41	res \|= 0x02;
42	42	if (!m_mcu_sent)
43	43	res \|= 0x04;
44
	44
45	45	return res;
46	46	}
47	47

trunk/src/mame/machine/inder_sb.c
r29404	r29405
24	24
25	25
26	26	// hacks for test purposes, these are installed over the program rom so we know when irqs are actually taken
27		READ8_MEMBER(inder_sb_device::megaphx_02cc_hack_r) { /logerror("%04x audicpu IRQ hack 0x02cc\n", machine().device("audiocpu")->safe_pc());/ int bank = m_soundbank[0] & 7; membank("snddata")->set_entry(bank); return memregion("audiocpu")->base()[0x02cc]; };
28		READ8_MEMBER(inder_sb_device::megaphx_02e6_hack_r) { /logerror("%04x audicpu IRQ hack 0x02e6\n", machine().device("audiocpu")->safe_pc());/ int bank = m_soundbank[1] & 7; membank("snddata")->set_entry(bank); return memregion("audiocpu")->base()[0x02e6]; };
29		READ8_MEMBER(inder_sb_device::megaphx_0309_hack_r) { /logerror("%04x audicpu IRQ hack 0x0309\n", machine().device("audiocpu")->safe_pc());/ int bank = m_soundbank[2] & 7; membank("snddata")->set_entry(bank); return memregion("audiocpu")->base()[0x0309]; };
30		READ8_MEMBER(inder_sb_device::megaphx_0323_hack_r) { /logerror("%04x audicpu IRQ hack 0x0323\n", machine().device("audiocpu")->safe_pc());/ int bank = m_soundbank[3] & 7; membank("snddata")->set_entry(bank); return memregion("audiocpu")->base()[0x0323]; };
	27	READ8_MEMBER(inder_sb_device::megaphx_02cc_hack_r) { /logerror("%04x audicpu IRQ hack 0x02cc\n", machine().device("audiocpu")->safe_pc());/ int bank = m_soundbank[0] & 7; membank("snddata")->set_entry(bank); return memregion("audiocpu")->base()[0x02cc]; };
	28	READ8_MEMBER(inder_sb_device::megaphx_02e6_hack_r) { /logerror("%04x audicpu IRQ hack 0x02e6\n", machine().device("audiocpu")->safe_pc());/ int bank = m_soundbank[1] & 7; membank("snddata")->set_entry(bank); return memregion("audiocpu")->base()[0x02e6]; };
	29	READ8_MEMBER(inder_sb_device::megaphx_0309_hack_r) { /logerror("%04x audicpu IRQ hack 0x0309\n", machine().device("audiocpu")->safe_pc());/ int bank = m_soundbank[2] & 7; membank("snddata")->set_entry(bank); return memregion("audiocpu")->base()[0x0309]; };
	30	READ8_MEMBER(inder_sb_device::megaphx_0323_hack_r) { /logerror("%04x audicpu IRQ hack 0x0323\n", machine().device("audiocpu")->safe_pc());/ int bank = m_soundbank[3] & 7; membank("snddata")->set_entry(bank); return memregion("audiocpu")->base()[0x0323]; };
31	31
32	32
33	33
34	34	READ16_MEMBER(inder_sb_device::megaphx_0x050002_r)
35	35	{
36	36	space.machine().scheduler().synchronize();
37		// int pc = machine().device("maincpu")->safe_pc();
	37	// int pc = machine().device("maincpu")->safe_pc();
38	38	int ret = m_soundback;
39	39	m_soundback = 0;
40	40	//logerror("(%06x) megaphx_0x050002_r (from z80?) %04x\n", pc, mem_mask);
41		return ret;
	41	return ret;
42	42	}
43	43
44	44	WRITE16_MEMBER(inder_sb_device::megaphx_0x050000_w)
45	45	{
46		// int pc = machine().device("maincpu")->safe_pc();
	46	// int pc = machine().device("maincpu")->safe_pc();
47	47	space.machine().scheduler().synchronize();
48	48
49	49	//logerror("(%06x) megaphx_0x050000_w (to z80?) %04x %04x\n", pc, data, mem_mask);
r29404	r29405
69	69
70	70	WRITE_LINE_MEMBER(inder_sb_device::z80ctc_ch0)
71	71	{
72		// int bank = m_soundbank[0] & 7; membank("snddata")->set_entry(bank);
73		// m_audiocpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
	72	// int bank = m_soundbank[0] & 7; membank("snddata")->set_entry(bank);
	73	// m_audiocpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
74	74	if (state) m_soundirq \|= 0x1;
75	75	else m_soundirq &= ~0x1;
76	76
r29404	r29405
80	80
81	81	WRITE_LINE_MEMBER(inder_sb_device::z80ctc_ch1)
82	82	{
83		// int bank = m_soundbank[1] & 7; membank("snddata")->set_entry(bank);
84		// m_audiocpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
	83	// int bank = m_soundbank[1] & 7; membank("snddata")->set_entry(bank);
	84	// m_audiocpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
85	85	if (state) m_soundirq \|= 0x2;
86	86	else m_soundirq &= ~0x2;
87	87
r29404	r29405
91	91
92	92	WRITE_LINE_MEMBER(inder_sb_device::z80ctc_ch2)
93	93	{
94		// int bank = m_soundbank[2] & 7; membank("snddata")->set_entry(bank);
95		// m_audiocpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
	94	// int bank = m_soundbank[2] & 7; membank("snddata")->set_entry(bank);
	95	// m_audiocpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
96	96	if (state) m_soundirq \|= 0x4;
97	97	else m_soundirq &= ~0x4;
98	98
r29404	r29405
104	104
105	105	WRITE_LINE_MEMBER(inder_sb_device::z80ctc_ch3)
106	106	{
107		// int bank = m_soundbank[3] & 7; membank("snddata")->set_entry(bank);
108		// m_audiocpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
	107	// int bank = m_soundbank[3] & 7; membank("snddata")->set_entry(bank);
	108	// m_audiocpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
109	109	if (state) m_soundirq \|= 0x8;
110	110	else m_soundirq &= ~0x8;
111	111
112	112	update_sound_irqs();
113	113	}
114	114
115
116	115
117	116
	117
118	118	static Z80CTC_INTERFACE( z80ctc_intf ) // runs in IM2 , vector set to 0x20 , values there are 0xCC, 0x02, 0xE6, 0x02, 0x09, 0x03, 0x23, 0x03 (so 02cc, 02e6, 0309, 0323, all of which are valid irq handlers)
119	119	{
120	120	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, inder_sb_device, z80ctc_ch0), // for channel 0
r29404	r29405
152	152
153	153	WRITE8_MEMBER(inder_sb_device::megaphx_sound_to_68k_w)
154	154	{
155		// int pc = machine().device("audiocpu")->safe_pc();
	155	// int pc = machine().device("audiocpu")->safe_pc();
156	156	space.machine().scheduler().synchronize();
157	157	//logerror("(%04x) megaphx_sound_to_68k_w (to 68k?) %02x\n", pc, data);
158	158
r29404	r29405
161	161
162	162	WRITE8_MEMBER(inder_sb_device::dac0_value_write)
163	163	{
164		// printf("dac0_data_write %02x\n", data);
	164	// printf("dac0_data_write %02x\n", data);
165	165	m_dac0->write_unsigned8(data);
166	166	}
167	167
168	168	WRITE8_MEMBER(inder_sb_device::dac0_gain_write)
169	169	{
170		// printf("dac0_gain_write %02x\n", data);
	170	// printf("dac0_gain_write %02x\n", data);
171	171	dac_gain[0] = data;
172	172	}
173	173
174	174	WRITE8_MEMBER(inder_sb_device::dac1_value_write)
175	175	{
176		// printf("dac1_data_write %02x\n", data);
	176	// printf("dac1_data_write %02x\n", data);
177	177	m_dac1->write_unsigned8(data);
178	178	}
179	179
180	180	WRITE8_MEMBER(inder_sb_device::dac1_gain_write)
181	181	{
182		// printf("dac1_gain_write %02x\n", data);
	182	// printf("dac1_gain_write %02x\n", data);
183	183	dac_gain[1] = data;
184	184	}
185	185
186	186	WRITE8_MEMBER(inder_sb_device::dac2_value_write)
187	187	{
188		// printf("dac2_data_write %02x\n", data);
	188	// printf("dac2_data_write %02x\n", data);
189	189	m_dac2->write_unsigned8(data);
190	190	}
191	191
192	192	WRITE8_MEMBER(inder_sb_device::dac2_gain_write)
193	193	{
194		// printf("dac2_gain_write %02x\n", data);
	194	// printf("dac2_gain_write %02x\n", data);
195	195	dac_gain[2] = data;
196	196	}
197	197
198	198	WRITE8_MEMBER(inder_sb_device::dac3_value_write)
199	199	{
200		// printf("dac3_data_write %02x\n", data);
	200	// printf("dac3_data_write %02x\n", data);
201	201	m_dac3->write_unsigned8(data);
202	202	}
203	203
204	204	WRITE8_MEMBER(inder_sb_device::dac3_gain_write)
205	205	{
206		// printf("dac3_gain_write %02x\n", data);
	206	// printf("dac3_gain_write %02x\n", data);
207	207	dac_gain[3] = data;
208	208	}
209	209
r29404	r29405
211	211	{
212	212	m_soundbank[0] = data;
213	213
214		// printf("dac0_rombank_write %02x", data);
	214	// printf("dac0_rombank_write %02x", data);
215	215	}
216	216
217	217	WRITE8_MEMBER(inder_sb_device::dac1_rombank_write)
218	218	{
219	219	m_soundbank[1] = data;
220		// printf("dac1_rombank_write %02x", data);
	220	// printf("dac1_rombank_write %02x", data);
221	221
222	222	}
223	223
224	224	WRITE8_MEMBER(inder_sb_device::dac2_rombank_write)
225	225	{
226	226	m_soundbank[2] = data;
227		// printf("dac2_rombank_write %02x", data);
	227	// printf("dac2_rombank_write %02x", data);
228	228	}
229	229
230	230	WRITE8_MEMBER(inder_sb_device::dac3_rombank_write)
231	231	{
232	232	m_soundbank[3] = data;
233		// printf("dac3_rombank_write %02x", data);
	233	// printf("dac3_rombank_write %02x", data);
234	234
235	235	}
236	236
r29404	r29405
253	253	AM_RANGE(0x13, 0x13) AM_WRITE(dac3_rombank_write)
254	254
255	255
256
257	256
	257
258	258	AM_RANGE(0x20, 0x23) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
259
	259
260	260	AM_RANGE(0x30, 0x30) AM_READWRITE(megaphx_sound_cmd_r, megaphx_sound_to_68k_w)
261	261	AM_RANGE(0x31, 0x31) AM_READ(megaphx_sound_sent_r)
262	262	ADDRESS_MAP_END
r29404	r29405
271	271
272	272	MCFG_Z80CTC_ADD( "ctc", 4000000, z80ctc_intf ) // unk freq
273	273
274		MCFG_SPEAKER_STANDARD_MONO("mono")
	274	MCFG_SPEAKER_STANDARD_MONO("mono")
275	275	MCFG_DAC_ADD("dac0")
276	276	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
277	277	MCFG_DAC_ADD("dac1")

trunk/src/mame/machine/inder_sb.h
r29404	r29405
89	89
90	90	};
91	91
92		#endif
		No newline at end of file
	92	#endif

trunk/src/mame/machine/tait8741.c
r29404	r29405
97	97
98	98	void taito8741_4pack_device::device_reset()
99	99	{
100		for (int i=0;i<4;i++)
	100	for (int i=0;i<4;i++)
101	101	{
102	102	I8741 *st = &m_taito8741[i];
103	103	st->number = i;
r29404	r29405
305	305
306	306	UINT8 taito8741_4pack_device::port_read(int num, int offset)
307	307	{
308		switch(num)
	308	switch(num)
309	309	{
310	310	case 0 : return m_port_handler_0_r(offset);
311	311	case 1 : return m_port_handler_1_r(offset);
r29404	r29405
473	473
474	474	UINT8 josvolly8741_4pack_device::port_read(int num)
475	475	{
476		switch(num)
	476	switch(num)
477	477	{
478	478	case 0 : return m_port_handler_0_r(0);
479	479	case 1 : return m_port_handler_1_r(0);
r29404	r29405
482	482	default : return 0;
483	483	}
484	484	}
485

trunk/src/mame/machine/tait8741.h
r29404	r29405
17	17	#define MCFG_TAITO8741_PORT_HANDLERS(_devcb0, _devcb1, _devcb2, _devcb3) \
18	18	devcb = &taito8741_4pack_device::set_port_handler_0_callback(*device, DEVCB2_##_devcb0); \
19	19	devcb = &taito8741_4pack_device::set_port_handler_1_callback(*device, DEVCB2_##_devcb1); \
20		devcb = &taito8741_4pack_device::set_port_handler_2_callback(*device, DEVCB2_##_devcb2); \
	20	devcb = &taito8741_4pack_device::set_port_handler_2_callback(*device, DEVCB2_##_devcb2); \
21	21	devcb = &taito8741_4pack_device::set_port_handler_3_callback(*device, DEVCB2_##_devcb3);
22	22
23	23	#define MCFG_TAITO8741_MODES(_mode0, _mode1, _mode2, _mode3) \
24		taito8741_4pack_device::static_set_mode(*device, 0, _mode0); \
25		taito8741_4pack_device::static_set_mode(*device, 1, _mode1); \
26		taito8741_4pack_device::static_set_mode(*device, 2, _mode2); \
	24	taito8741_4pack_device::static_set_mode(*device, 0, _mode0); \
	25	taito8741_4pack_device::static_set_mode(*device, 1, _mode1); \
	26	taito8741_4pack_device::static_set_mode(*device, 2, _mode2); \
27	27	taito8741_4pack_device::static_set_mode(*device, 3, _mode3);
28	28
29	29
30	30	#define MCFG_TAITO8741_CONNECT(_con0, _con1, _con2, _con3) \
31		taito8741_4pack_device::static_set_connect(*device, 0, _con0); \
32		taito8741_4pack_device::static_set_connect(*device, 1, _con1); \
33		taito8741_4pack_device::static_set_connect(*device, 2, _con2); \
	31	taito8741_4pack_device::static_set_connect(*device, 0, _con0); \
	32	taito8741_4pack_device::static_set_connect(*device, 1, _con1); \
	33	taito8741_4pack_device::static_set_connect(*device, 2, _con2); \
34	34	taito8741_4pack_device::static_set_connect(*device, 3, _con3);
35	35
36
	36
37	37	class taito8741_4pack_device : public device_t
38	38	{
39	39	struct I8741 {
40		int number;
	40	int number;
41	41	UINT8 toData; /* to host data */
42	42	UINT8 fromData; /* from host data */
43	43	UINT8 fromCmd; /* from host command */
r29404	r29405
62	62	template<class _Object> static devcb2_base &set_port_handler_1_callback(device_t &device, _Object object) { return downcast<taito8741_4pack_device &>(device).m_port_handler_1_r.set_callback(object); }
63	63	template<class _Object> static devcb2_base &set_port_handler_2_callback(device_t &device, _Object object) { return downcast<taito8741_4pack_device &>(device).m_port_handler_2_r.set_callback(object); }
64	64	template<class _Object> static devcb2_base &set_port_handler_3_callback(device_t &device, _Object object) { return downcast<taito8741_4pack_device &>(device).m_port_handler_3_r.set_callback(object); }
65
66		static void static_set_mode(device_t &device, int num, UINT8 mode) { downcast<taito8741_4pack_device &>(device).m_taito8741[num].mode = mode; }
67		static void static_set_connect(device_t &device, int num, int conn) { downcast<taito8741_4pack_device &>(device).m_taito8741[num].connect = conn; }
68
	65
	66	static void static_set_mode(device_t &device, int num, UINT8 mode) { downcast<taito8741_4pack_device &>(device).m_taito8741[num].mode = mode; }
	67	static void static_set_connect(device_t &device, int num, int conn) { downcast<taito8741_4pack_device &>(device).m_taito8741[num].connect = conn; }
	68
69	69	DECLARE_READ8_MEMBER( read_0 ) { if(offset&1) return status_r(0); else return data_r(0); }
70	70	DECLARE_WRITE8_MEMBER( write_0 ) { if(offset&1) command_w(0,data); else data_w(0,data); }
71	71	DECLARE_READ8_MEMBER( read_1 ) { if(offset&1) return status_r(1); else return data_r(1); }
r29404	r29405
81	81	int data_r(int num);
82	82	void data_w(int num, int data);
83	83	void command_w(int num, int data);
84
	84
85	85	UINT8 port_read(int num, int offset);
86	86
87	87	protected:
r29404	r29405
96	96	void serial_rx(I8741 st,UINT8 data);
97	97
98	98	// internal state
99		I8741 m_taito8741[4];
	99	I8741 m_taito8741[4];
100	100
101	101	devcb2_read8 m_port_handler_0_r;
102	102	devcb2_read8 m_port_handler_1_r;
r29404	r29405
118	118	#define MCFG_JOSVOLLY8741_PORT_HANDLERS(_devcb0, _devcb1, _devcb2, _devcb3) \
119	119	devcb = &josvolly8741_4pack_device::set_port_handler_0_callback(*device, DEVCB2_##_devcb0); \
120	120	devcb = &josvolly8741_4pack_device::set_port_handler_1_callback(*device, DEVCB2_##_devcb1); \
121		devcb = &josvolly8741_4pack_device::set_port_handler_2_callback(*device, DEVCB2_##_devcb2); \
	121	devcb = &josvolly8741_4pack_device::set_port_handler_2_callback(*device, DEVCB2_##_devcb2); \
122	122	devcb = &josvolly8741_4pack_device::set_port_handler_3_callback(*device, DEVCB2_##_devcb3);
123	123
124	124	#define MCFG_JOSVOLLY8741_CONNECT(_con0, _con1, _con2, _con3) \
125		josvolly8741_4pack_device::static_set_connect(*device, 0, _con0); \
126		josvolly8741_4pack_device::static_set_connect(*device, 1, _con1); \
127		josvolly8741_4pack_device::static_set_connect(*device, 2, _con2); \
	125	josvolly8741_4pack_device::static_set_connect(*device, 0, _con0); \
	126	josvolly8741_4pack_device::static_set_connect(*device, 1, _con1); \
	127	josvolly8741_4pack_device::static_set_connect(*device, 2, _con2); \
128	128	josvolly8741_4pack_device::static_set_connect(*device, 3, _con3);
129	129
130
	130
131	131	class josvolly8741_4pack_device : public device_t
132	132	{
133	133	struct JV8741 {
r29404	r29405
148	148	template<class _Object> static devcb2_base &set_port_handler_1_callback(device_t &device, _Object object) { return downcast<josvolly8741_4pack_device &>(device).m_port_handler_1_r.set_callback(object); }
149	149	template<class _Object> static devcb2_base &set_port_handler_2_callback(device_t &device, _Object object) { return downcast<josvolly8741_4pack_device &>(device).m_port_handler_2_r.set_callback(object); }
150	150	template<class _Object> static devcb2_base &set_port_handler_3_callback(device_t &device, _Object object) { return downcast<josvolly8741_4pack_device &>(device).m_port_handler_3_r.set_callback(object); }
151
152		static void static_set_connect(device_t &device, int num, int conn) { downcast<josvolly8741_4pack_device &>(device).m_i8741[num].connect = conn; }
153
	151
	152	static void static_set_connect(device_t &device, int num, int conn) { downcast<josvolly8741_4pack_device &>(device).m_i8741[num].connect = conn; }
	153
154	154	DECLARE_READ8_MEMBER( read_0 ) { return read(0,offset); }
155	155	DECLARE_WRITE8_MEMBER( write_0 ) { write(0,offset,data); }
156	156	DECLARE_READ8_MEMBER( read_1 ) { return read(1,offset); }
157	157	DECLARE_WRITE8_MEMBER( write_1 ) { write(1,offset,data); }
158
159		DECLARE_WRITE8_HANDLER( nmi_enable_w ) { m_nmi_enable = 1; }
160	158
	159	DECLARE_WRITE8_HANDLER( nmi_enable_w ) { m_nmi_enable = 1; }
	160
161	161	TIMER_CALLBACK_MEMBER( tx );
162	162	protected:
163	163	// device-level overrides
r29404	r29405
173	173	// internal state
174	174	JV8741 m_i8741[4];
175	175	int m_nmi_enable;
176
	176
177	177	devcb2_read8 m_port_handler_0_r;
178	178	devcb2_read8 m_port_handler_1_r;
179	179	devcb2_read8 m_port_handler_2_r;

trunk/src/mame/machine/pcecommn.c
r29404	r29405
67	67	{
68	68	m_maincpu->set_input_line(0, state);
69	69	}
70

trunk/src/mame/machine/pcecommn.h
r29404	r29405
31	31	virtual UINT8 joy_read();
32	32	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
33	33	required_device<huc6260_device> m_huc6260;
34		DECLARE_WRITE_LINE_MEMBER(pce_irq_changed);
	34	DECLARE_WRITE_LINE_MEMBER(pce_irq_changed);
35	35	private:
36	36	UINT8 m_io_port_options; /driver-specific options for the PCE/
37	37	int m_joystick_port_select; /* internal index of joystick ports */

trunk/src/mame/machine/taitoio.h
r29404	r29405
21	21	template<class _Object> static devcb2_base &set_read_2_callback(device_t &device, _Object object) { return downcast<tc0220ioc_device &>(device).m_read_2_cb.set_callback(object); }
22	22	template<class _Object> static devcb2_base &set_read_3_callback(device_t &device, _Object object) { return downcast<tc0220ioc_device &>(device).m_read_3_cb.set_callback(object); }
23	23	template<class _Object> static devcb2_base &set_read_7_callback(device_t &device, _Object object) { return downcast<tc0220ioc_device &>(device).m_read_7_cb.set_callback(object); }
24
	24
25	25	DECLARE_READ8_MEMBER( read );
26	26	DECLARE_WRITE8_MEMBER( write );
27	27	DECLARE_READ8_MEMBER( port_r );
r29404	r29405
59	59	template<class _Object> static devcb2_base &set_read_2_callback(device_t &device, _Object object) { return downcast<tc0510nio_device &>(device).m_read_2_cb.set_callback(object); }
60	60	template<class _Object> static devcb2_base &set_read_3_callback(device_t &device, _Object object) { return downcast<tc0510nio_device &>(device).m_read_3_cb.set_callback(object); }
61	61	template<class _Object> static devcb2_base &set_read_7_callback(device_t &device, _Object object) { return downcast<tc0510nio_device &>(device).m_read_7_cb.set_callback(object); }
62
	62
63	63	DECLARE_READ8_MEMBER( read );
64	64	DECLARE_WRITE8_MEMBER( write );
65	65	DECLARE_READ16_MEMBER( halfword_r );
r29404	r29405
96	96	template<class _Object> static devcb2_base &set_read_2_callback(device_t &device, _Object object) { return downcast<tc0640fio_device &>(device).m_read_2_cb.set_callback(object); }
97	97	template<class _Object> static devcb2_base &set_read_3_callback(device_t &device, _Object object) { return downcast<tc0640fio_device &>(device).m_read_3_cb.set_callback(object); }
98	98	template<class _Object> static devcb2_base &set_read_7_callback(device_t &device, _Object object) { return downcast<tc0640fio_device &>(device).m_read_7_cb.set_callback(object); }
99
100
	99
	100
101	101	DECLARE_READ8_MEMBER( read );
102	102	DECLARE_WRITE8_MEMBER( write );
103	103	DECLARE_READ16_MEMBER( halfword_r );
r29404	r29405
133	133
134	134	#define MCFG_TC0220IOC_READ_1_CB(_devcb) \
135	135	devcb = &tc0220ioc_device::set_read_1_callback(*device, DEVCB2_##_devcb);
136
	136
137	137	#define MCFG_TC0220IOC_READ_2_CB(_devcb) \
138	138	devcb = &tc0220ioc_device::set_read_2_callback(*device, DEVCB2_##_devcb);
139
	139
140	140	#define MCFG_TC0220IOC_READ_3_CB(_devcb) \
141	141	devcb = &tc0220ioc_device::set_read_3_callback(*device, DEVCB2_##_devcb);
142
	142
143	143	#define MCFG_TC0220IOC_READ_7_CB(_devcb) \
144	144	devcb = &tc0220ioc_device::set_read_7_callback(*device, DEVCB2_##_devcb);
145
146	145
	146
147	147	#define MCFG_TC0510NIO_READ_0_CB(_devcb) \
148	148	devcb = &tc0510nio_device::set_read_0_callback(*device, DEVCB2_##_devcb);
149	149
150	150	#define MCFG_TC0510NIO_READ_1_CB(_devcb) \
151	151	devcb = &tc0510nio_device::set_read_1_callback(*device, DEVCB2_##_devcb);
152
	152
153	153	#define MCFG_TC0510NIO_READ_2_CB(_devcb) \
154	154	devcb = &tc0510nio_device::set_read_2_callback(*device, DEVCB2_##_devcb);
155
	155
156	156	#define MCFG_TC0510NIO_READ_3_CB(_devcb) \
157	157	devcb = &tc0510nio_device::set_read_3_callback(*device, DEVCB2_##_devcb);
158
	158
159	159	#define MCFG_TC0510NIO_READ_7_CB(_devcb) \
160	160	devcb = &tc0510nio_device::set_read_7_callback(*device, DEVCB2_##_devcb);
161	161
r29404	r29405
165	165
166	166	#define MCFG_TC0640FIO_READ_1_CB(_devcb) \
167	167	devcb = &tc0640fio_device::set_read_1_callback(*device, DEVCB2_##_devcb);
168
	168
169	169	#define MCFG_TC0640FIO_READ_2_CB(_devcb) \
170	170	devcb = &tc0640fio_device::set_read_2_callback(*device, DEVCB2_##_devcb);
171
	171
172	172	#define MCFG_TC0640FIO_READ_3_CB(_devcb) \
173	173	devcb = &tc0640fio_device::set_read_3_callback(*device, DEVCB2_##_devcb);
174
	174
175	175	#define MCFG_TC0640FIO_READ_7_CB(_devcb) \
176		devcb = &tc0640fio_device::set_read_7_callback(*device, DEVCB2_##_devcb);
	176	devcb = &tc0640fio_device::set_read_7_callback(*device, DEVCB2_##_devcb);
177	177
178
	178
179	179	#endif /* __TAITOIO_H__ */

trunk/src/mame/machine/atarigen.h
r29404	r29405
79	79	{ astring fulltag(device->tag(), ":mob"); device_t *device; \
80	80	MCFG_ATARI_MOTION_OBJECTS_ADD(fulltag, "^^screen", _config) \
81	81	MCFG_ATARI_MOTION_OBJECTS_GFXDECODE("^" _gfxtag) }
82
83	82
84	83
	84
85	85	#define MCFG_ATARI_EEPROM_2804_ADD(_tag) \
86	86	MCFG_DEVICE_ADD(_tag, ATARI_EEPROM_2804, 0)
87	87

trunk/src/mame/machine/atari.c
r29404	r29405
278	278	machine().save().save_pointer(NAME((UINT8 *) &antic.r), sizeof(antic.r));
279	279	machine().save().save_pointer(NAME((UINT8 *) &antic.w), sizeof(antic.w));
280	280	}
281

trunk/src/mame/machine/namco06.c
r29404	r29405
101	101
102	102
103	103	READ8_MEMBER( namco_06xx_device::data_r )
104		{
	104	{
105	105	UINT8 result = 0xff;
106	106
107	107	LOG(("%s: 06XX '%s' read offset %d\n",machine().describe_context(),tag(),offset));
r29404	r29405
122	122
123	123
124	124	WRITE8_MEMBER( namco_06xx_device::data_w )
125		{
	125	{
126	126	LOG(("%s: 06XX '%s' write offset %d = %02x\n",machine().describe_context(),tag(),offset,data));
127	127
128	128	if (m_control & 0x10)
r29404	r29405
138	138
139	139
140	140	READ8_MEMBER( namco_06xx_device::ctrl_r )
141		{
	141	{
142	142	LOG(("%s: 06XX '%s' ctrl_r\n",machine().describe_context(),tag()));
143	143	return m_control;
144	144	}
145	145
146	146	WRITE8_MEMBER( namco_06xx_device::ctrl_w )
147		{
	147	{
148	148	LOG(("%s: 06XX '%s' control %02x\n",space.machine().describe_context(),tag(),data));
149	149
150	150	m_control = data;
r29404	r29405
183	183	m_read_0(*this),
184	184	m_read_1(*this),
185	185	m_read_2(*this),
186		m_read_3(*this),
	186	m_read_3(*this),
187	187	m_readreq_0(*this),
188	188	m_readreq_1(*this),
189	189	m_readreq_2(*this),
190		m_readreq_3(*this),
	190	m_readreq_3(*this),
191	191	m_write_0(*this),
192	192	m_write_1(*this),
193	193	m_write_2(*this),
r29404	r29405
212	212	m_write_0.resolve();
213	213	m_write_1.resolve();
214	214	m_write_2.resolve();
215		m_write_3.resolve();
	215	m_write_3.resolve();
216	216	/* allocate a timer */
217	217	m_nmi_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namco_06xx_device::nmi_generate),this));
218	218

trunk/src/mame/machine/namco06.h
r29404	r29405
16	16
17	17	#define MCFG_NAMCO_06XX_ADD(_tag, _clock) \
18	18	MCFG_DEVICE_ADD(_tag, NAMCO_06XX, _clock)
19
	19
20	20	#define MCFG_NAMCO_06XX_MAINCPU(_tag) \
21	21	namco_06xx_device::set_maincpu(*device, "^" _tag);
22	22
r29404	r29405
44	44
45	45	#define MCFG_NAMCO_06XX_READ_REQUEST_3_CB(_devcb) \
46	46	devcb = &namco_06xx_device::set_read_request_3_callback(*device, DEVCB2_##_devcb);
47
48	47
	48
49	49	#define MCFG_NAMCO_06XX_WRITE_0_CB(_devcb) \
50	50	devcb = &namco_06xx_device::set_write_0_callback(*device, DEVCB2_##_devcb);
51	51
52	52	#define MCFG_NAMCO_06XX_WRITE_1_CB(_devcb) \
53	53	devcb = &namco_06xx_device::set_write_1_callback(*device, DEVCB2_##_devcb);
54
	54
55	55	#define MCFG_NAMCO_06XX_WRITE_2_CB(_devcb) \
56	56	devcb = &namco_06xx_device::set_write_2_callback(*device, DEVCB2_##_devcb);
57	57
58	58	#define MCFG_NAMCO_06XX_WRITE_3_CB(_devcb) \
59	59	devcb = &namco_06xx_device::set_write_3_callback(*device, DEVCB2_##_devcb);
60
61	60
	61
62	62	/* device get info callback */
63	63	class namco_06xx_device : public device_t
64	64	{
r29404	r29405
66	66	namco_06xx_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
67	67
68	68	static void set_maincpu(device_t &device, const char *tag) { downcast<namco_06xx_device &>(device).m_nmicpu.set_tag(tag); }
69
	69
70	70	template<class _Object> static devcb2_base &set_read_0_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_read_0.set_callback(object); }
71	71	template<class _Object> static devcb2_base &set_read_1_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_read_1.set_callback(object); }
72	72	template<class _Object> static devcb2_base &set_read_2_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_read_2.set_callback(object); }
73	73	template<class _Object> static devcb2_base &set_read_3_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_read_3.set_callback(object); }
74
	74
75	75	template<class _Object> static devcb2_base &set_read_request_0_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_readreq_0.set_callback(object); }
76	76	template<class _Object> static devcb2_base &set_read_request_1_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_readreq_1.set_callback(object); }
77	77	template<class _Object> static devcb2_base &set_read_request_2_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_readreq_2.set_callback(object); }
78	78	template<class _Object> static devcb2_base &set_read_request_3_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_readreq_3.set_callback(object); }
79
80	79
	80
81	81	template<class _Object> static devcb2_base &set_write_0_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_write_0.set_callback(object); }
82	82	template<class _Object> static devcb2_base &set_write_1_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_write_1.set_callback(object); }
83	83	template<class _Object> static devcb2_base &set_write_2_callback(device_t &device, _Object object) { return downcast<namco_06xx_device &>(device).m_write_2.set_callback(object); }
r29404	r29405
95	95	private:
96	96
97	97	TIMER_CALLBACK_MEMBER( nmi_generate );
98
99		// internal state
	98
	99	// internal state
100	100	UINT8 m_control;
101	101	emu_timer *m_nmi_timer;
102	102
r29404	r29405
106	106	devcb2_read8 m_read_1;
107	107	devcb2_read8 m_read_2;
108	108	devcb2_read8 m_read_3;
109
	109
110	110	devcb2_write_line m_readreq_0;
111	111	devcb2_write_line m_readreq_1;
112	112	devcb2_write_line m_readreq_2;
113	113	devcb2_write_line m_readreq_3;
114
	114
115	115	devcb2_write8 m_write_0;
116	116	devcb2_write8 m_write_1;
117	117	devcb2_write8 m_write_2;
118		devcb2_write8 m_write_3;
	118	devcb2_write8 m_write_3;
119	119	};
120	120
121	121	extern const device_type NAMCO_06XX;

trunk/src/mame/machine/namcoio.h
r29404	r29405
17	17	template<class _Object> static devcb2_base &set_in_3_callback(device_t &device, _Object object) { return downcast<namcoio_device &>(device).m_in_3_cb.set_callback(object); }
18	18	template<class _Object> static devcb2_base &set_out_0_callback(device_t &device, _Object object) { return downcast<namcoio_device &>(device).m_out_0_cb.set_callback(object); }
19	19	template<class _Object> static devcb2_base &set_out_1_callback(device_t &device, _Object object) { return downcast<namcoio_device &>(device).m_out_1_cb.set_callback(object); }
20
21
	20
	21
22	22	DECLARE_READ8_MEMBER( read );
23	23	DECLARE_WRITE8_MEMBER( write );
24	24
r29404	r29405
104	104
105	105	#define MCFG_NAMCO56XX_IN_2_CB(_devcb) \
106	106	devcb = &namco56xx_device::set_in_2_callback(*device, DEVCB2_##_devcb);
107
	107
108	108	#define MCFG_NAMCO56XX_IN_3_CB(_devcb) \
109	109	devcb = &namco56xx_device::set_in_3_callback(*device, DEVCB2_##_devcb);
110	110
r29404	r29405
113	113
114	114	#define MCFG_NAMCO56XX_OUT_1_CB(_devcb) \
115	115	devcb = &namco56xx_device::set_out_1_callback(*device, DEVCB2_##_devcb);
116
117	116
	117
118	118	#define MCFG_NAMCO58XX_IN_0_CB(_devcb) \
119	119	devcb = &namco58xx_device::set_in_0_callback(*device, DEVCB2_##_devcb);
120	120
r29404	r29405
123	123
124	124	#define MCFG_NAMCO58XX_IN_2_CB(_devcb) \
125	125	devcb = &namco58xx_device::set_in_2_callback(*device, DEVCB2_##_devcb);
126
	126
127	127	#define MCFG_NAMCO58XX_IN_3_CB(_devcb) \
128	128	devcb = &namco58xx_device::set_in_3_callback(*device, DEVCB2_##_devcb);
129	129
r29404	r29405
132	132
133	133	#define MCFG_NAMCO58XX_OUT_1_CB(_devcb) \
134	134	devcb = &namco58xx_device::set_out_1_callback(*device, DEVCB2_##_devcb);
135
136
	135
	136
137	137	#define MCFG_NAMCO59XX_IN_0_CB(_devcb) \
138	138	devcb = &namco59xx_device::set_in_0_callback(*device, DEVCB2_##_devcb);
139	139
r29404	r29405
142	142
143	143	#define MCFG_NAMCO59XX_IN_2_CB(_devcb) \
144	144	devcb = &namco59xx_device::set_in_2_callback(*device, DEVCB2_##_devcb);
145
	145
146	146	#define MCFG_NAMCO59XX_IN_3_CB(_devcb) \
147	147	devcb = &namco59xx_device::set_in_3_callback(*device, DEVCB2_##_devcb);
148	148
r29404	r29405
151	151
152	152	#define MCFG_NAMCO59XX_OUT_1_CB(_devcb) \
153	153	devcb = &namco59xx_device::set_out_1_callback(*device, DEVCB2_##_devcb);
154
	154
155	155	#endif /* __NAMCOIO_H__ */

trunk/src/mame/machine/namcos1.c
r29404	r29405
13	13
14	14	UINT8 namcos1_state::bank_r(address_space &space, offs_t offset, int bank)
15	15	{
16
17	16	return m_active_bank[bank].bank_handler_r(space, offset + m_active_bank[bank].bank_offset, 0xff);
18	17	}
19	18
r29404	r29405
641	640	"bank1", "bank2", "bank3", "bank4", "bank5", "bank6", "bank7", "bank8",
642	641	"bank9", "bank10", "bank11", "bank12", "bank13", "bank14", "bank15", "bank16"
643	642	};
644
	643
645	644	static const struct { read8_delegate func; } io_bank_handler_r[16] =
646	645	{
647	646	{ read8_delegate(FUNC(namcos1_state::bank1_r),this) }, { read8_delegate(FUNC(namcos1_state::bank2_r),this) }, { read8_delegate(FUNC(namcos1_state::bank3_r),this) }, { read8_delegate(FUNC(namcos1_state::bank4_r),this) },
r29404	r29405
660	659
661	660
662	661	static const char *const cputags[] = { "maincpu", "sub" };
663
	662
664	663	address_space &space = machine().device(cputags[(banknum >> 3) & 1])->memory().space(AS_PROGRAM);
665	664	int bankstart = (banknum & 7) * 0x2000;
666	665

trunk/src/mame/includes/fuukifg3.h
r29404	r29405
55	55	required_device<gfxdecode_device> m_gfxdecode;
56	56	required_device<screen_device> m_screen;
57	57	required_device<palette_device> m_palette;
58
59
	58
	59
60	60	DECLARE_READ32_MEMBER(snd_020_r);
61	61	DECLARE_WRITE32_MEMBER(snd_020_w);
62	62	DECLARE_WRITE32_MEMBER(fuuki32_vregs_w);

trunk/src/mame/includes/battlane.h
r29404	r29405
31	31	required_device<cpu_device> m_subcpu;
32	32	required_device<gfxdecode_device> m_gfxdecode;
33	33	required_device<palette_device> m_palette;
34
	34
35	35	DECLARE_WRITE8_MEMBER(battlane_cpu_command_w);
36	36	DECLARE_WRITE8_MEMBER(battlane_palette_w);
37	37	DECLARE_WRITE8_MEMBER(battlane_scrollx_w);

trunk/src/mame/includes/turbo.h
r29404	r29405
48	48	required_shared_ptr<UINT8> m_sprite_position;
49	49
50	50	required_device<samples_device> m_samples;
51
	51
52	52	required_device<gfxdecode_device> m_gfxdecode;
53	53	required_device<screen_device> m_screen;
54	54

trunk/src/mame/includes/rohga.h
r29404	r29405
58	58
59	59	optional_device<decospr_device> m_sprgen1;
60	60	optional_device<decospr_device> m_sprgen2;
61
	61
62	62	required_device<palette_device> m_palette;
63	63
64	64	DECLARE_READ16_MEMBER(rohga_irq_ack_r);

trunk/src/mame/includes/crimfght.h
r29404	r29405
34	34	required_device<k052109_device> m_k052109;
35	35	required_device<k051960_device> m_k051960;
36	36	required_device<palette_device> m_palette;
37
	37
38	38	DECLARE_WRITE8_MEMBER(crimfght_coin_w);
39	39	DECLARE_WRITE8_MEMBER(crimfght_sh_irqtrigger_w);
40	40	DECLARE_READ8_MEMBER(k052109_051960_r);

trunk/src/mame/includes/model3.h
r29404	r29405
36	36	required_device<cpu_device> m_audiocpu;
37	37	required_device<scsp_device> m_scsp1;
38	38	required_device<eeprom_serial_93cxx_device> m_eeprom;
39		required_device<screen_device> m_screen;
	39	required_device<screen_device> m_screen;
40	40
41	41	required_shared_ptr<UINT64> m_work_ram;
42	42	required_shared_ptr<UINT64> m_paletteram64;

trunk/src/mame/includes/darius.h
r29404	r29405
93	93	required_device<filter_volume_device> m_msm5205_r;
94	94	required_device<gfxdecode_device> m_gfxdecode;
95	95	required_device<palette_device> m_palette;
96
	96
97	97	DECLARE_WRITE16_MEMBER(cpua_ctrl_w);
98	98	DECLARE_WRITE16_MEMBER(darius_watchdog_w);
99	99	DECLARE_READ16_MEMBER(darius_ioc_r);

trunk/src/mame/includes/nitedrvr.h
r29404	r29405
50	50	required_device<discrete_device> m_discrete;
51	51	required_device<gfxdecode_device> m_gfxdecode;
52	52	required_device<palette_device> m_palette;
53
	53
54	54	DECLARE_READ8_MEMBER(nitedrvr_steering_reset_r);
55	55	DECLARE_WRITE8_MEMBER(nitedrvr_steering_reset_w);
56	56	DECLARE_READ8_MEMBER(nitedrvr_in0_r);

trunk/src/mame/includes/cchasm.h
r29404	r29405
35	35	required_device<dac_device> m_dac2;
36	36	required_device<vector_device> m_vector;
37	37	required_device<screen_device> m_screen;
38
	38
39	39	int m_sound_flags;
40	40	int m_coin_flag;
41	41	int m_channel_active[2];

trunk/src/mame/includes/nycaptor.h
r29404	r29405
63	63	required_device<msm5232_device> m_msm;
64	64	required_device<gfxdecode_device> m_gfxdecode;
65	65	required_device<palette_device> m_palette;
66
	66
67	67	DECLARE_WRITE8_MEMBER(sub_cpu_halt_w);
68	68	DECLARE_READ8_MEMBER(from_snd_r);
69	69	DECLARE_WRITE8_MEMBER(to_main_w);

trunk/src/mame/includes/mrflea.h
r29404	r29405
37	37	required_device<gfxdecode_device> m_gfxdecode;
38	38	required_device<screen_device> m_screen;
39	39	required_device<palette_device> m_palette;
40
	40
41	41	DECLARE_WRITE8_MEMBER(mrflea_main_w);
42	42	DECLARE_WRITE8_MEMBER(mrflea_io_w);
43	43	DECLARE_READ8_MEMBER(mrflea_main_r);

trunk/src/mame/includes/bublbobl.h
r29404	r29405
70	70	required_device<cpu_device> m_slave;
71	71	required_device<gfxdecode_device> m_gfxdecode;
72	72	required_device<palette_device> m_palette;
73
	73
74	74	DECLARE_WRITE8_MEMBER(bublbobl_bankswitch_w);
75	75	DECLARE_WRITE8_MEMBER(tokio_bankswitch_w);
76	76	DECLARE_WRITE8_MEMBER(tokio_videoctrl_w);

trunk/src/mame/includes/docastle.h
r29404	r29405
21	21	m_colorram(*this, "colorram"),
22	22	m_spriteram(*this, "spriteram"),
23	23	m_gfxdecode(*this, "gfxdecode"),
24		m_palette(*this, "palette")
	24	m_palette(*this, "palette")
25	25	{ }
26	26
27	27	/* devices */
r29404	r29405
35	35	required_shared_ptr<UINT8> m_videoram;
36	36	required_shared_ptr<UINT8> m_colorram;
37	37	required_shared_ptr<UINT8> m_spriteram;
38
	38
39	39	required_device<gfxdecode_device> m_gfxdecode;
40	40	required_device<palette_device> m_palette;
41
	41
42	42	/* video-related */
43	43	tilemap_t *m_do_tilemap;
44	44

trunk/src/mame/includes/snowbros.h
r29404	r29405
25	25	optional_shared_ptr<UINT16> m_bootleg_spriteram16;
26	26	required_device<gfxdecode_device> m_gfxdecode;
27	27	required_device<palette_device> m_palette;
28
	28
29	29	int m_sb3_music_is_playing;
30	30	int m_sb3_music;
31	31	UINT8 m_semicom_prot_offset;

trunk/src/mame/includes/lasso.h
r29404	r29405
49	49	optional_device<sn76489_device> m_sn_2;
50	50	required_device<gfxdecode_device> m_gfxdecode;
51	51	required_device<palette_device> m_palette;
52
	52
53	53	DECLARE_WRITE8_MEMBER(sound_command_w);
54	54	DECLARE_READ8_MEMBER(sound_status_r);
55	55	DECLARE_WRITE8_MEMBER(sound_select_w);

trunk/src/mame/includes/copsnrob.h
r29404	r29405
44	44	required_device<cpu_device> m_maincpu;
45	45	required_device<gfxdecode_device> m_gfxdecode;
46	46	required_device<screen_device> m_screen;
47		required_device<palette_device> m_palette;
	47	required_device<palette_device> m_palette;
48	48	};
49	49
50	50	/----------- defined in audio/copsnrob.c -----------/

trunk/src/mame/includes/multfish.h
r29404	r29405
113	113	MACHINE_CONFIG_EXTERN( igrosoft_gamble );
114	114	MACHINE_CONFIG_EXTERN( rollfr );
115	115	INPUT_PORTS_EXTERN( igrosoft_gamble );
116
117
118
119

trunk/src/mame/includes/m10.h
r29404	r29405
46	46	m_chargen(*this, "chargen"),
47	47	m_maincpu(*this, "maincpu"),
48	48	m_ic8j1(*this, "ic8j1"),
49		m_ic8j2(*this, "ic8j2"),
	49	m_ic8j2(*this, "ic8j2"),
50	50	m_samples(*this, "samples"),
51	51	m_gfxdecode(*this, "gfxdecode"),
52	52	m_screen(*this, "screen"),
r29404	r29405
81	81	optional_device<gfxdecode_device> m_gfxdecode;
82	82	required_device<screen_device> m_screen;
83	83	required_device<palette_device> m_palette;
84
	84
85	85	DECLARE_WRITE8_MEMBER(m10_ctrl_w);
86	86	DECLARE_WRITE8_MEMBER(m11_ctrl_w);
87	87	DECLARE_WRITE8_MEMBER(m15_ctrl_w);

trunk/src/mame/includes/labyrunr.h
r29404	r29405
33	33	required_shared_ptr<UINT8> m_spriteram;
34	34	required_shared_ptr<UINT8> m_videoram1;
35	35	required_shared_ptr<UINT8> m_videoram2;
36
	36
37	37	required_device<gfxdecode_device> m_gfxdecode;
38	38	required_device<screen_device> m_screen;
39	39	required_device<palette_device> m_palette;

trunk/src/mame/includes/ccastles.h
r29404	r29405
32	32	required_device<gfxdecode_device> m_gfxdecode;
33	33	required_device<screen_device> m_screen;
34	34	required_device<palette_device> m_palette;
35
	35
36	36	/* video-related */
37	37	const UINT8 *m_syncprom;
38	38	const UINT8 *m_wpprom;

trunk/src/mame/includes/djboy.h
r29404	r29405
56	56	required_device<kaneko_pandora_device> m_pandora;
57	57	required_device<gfxdecode_device> m_gfxdecode;
58	58	required_device<palette_device> m_palette;
59
	59
60	60	DECLARE_WRITE8_MEMBER(beast_data_w);
61	61	DECLARE_READ8_MEMBER(beast_data_r);
62	62	DECLARE_READ8_MEMBER(beast_status_r);

trunk/src/mame/includes/powerins.h
r29404	r29405
28	28	required_device<gfxdecode_device> m_gfxdecode;
29	29	required_device<screen_device> m_screen;
30	30	required_device<palette_device> m_palette;
31
	31
32	32	UINT16 *m_vctrl_1;
33	33	tilemap_t *m_tilemap_0;
34	34	tilemap_t *m_tilemap_1;

trunk/src/mame/includes/paradise.h
r29404	r29405
67	67	optional_device<okim6295_device> m_oki2;
68	68	required_device<gfxdecode_device> m_gfxdecode;
69	69	required_device<screen_device> m_screen;
70		required_device<palette_device> m_palette;
	70	required_device<palette_device> m_palette;
71	71	};

trunk/src/mame/includes/balsente.h
r29404	r29405
219	219	required_device<cpu_device> m_audiocpu;
220	220	optional_device<cpu_device> m_68k;
221	221	required_device<screen_device> m_screen;
222		required_device<palette_device> m_palette;
	222	required_device<palette_device> m_palette;
223	223	};
224	224
225	225

trunk/src/mame/includes/pushman.h
r29404	r29405
37	37	optional_device<cpu_device> m_mcu;
38	38	required_device<gfxdecode_device> m_gfxdecode;
39	39	required_device<palette_device> m_palette;
40
	40
41	41	DECLARE_WRITE16_MEMBER(pushman_flipscreen_w);
42	42	DECLARE_WRITE16_MEMBER(pushman_control_w);
43	43	DECLARE_READ16_MEMBER(pushman_68705_r);

trunk/src/mame/includes/undrfire.h
r29404	r29405
49	49	required_shared_ptr<UINT32> m_spriteram;
50	50	required_device<gfxdecode_device> m_gfxdecode;
51	51	required_device<palette_device> m_palette;
52
	52
53	53	DECLARE_WRITE32_MEMBER(color_ram_w);
54	54	DECLARE_READ32_MEMBER(undrfire_input_r);
55	55	DECLARE_WRITE32_MEMBER(undrfire_input_w);

trunk/src/mame/includes/zodiack.h
r29404	r29405
42	42	required_shared_ptr<UINT8> m_attributeram;
43	43	required_shared_ptr<UINT8> m_spriteram;
44	44	required_shared_ptr<UINT8> m_bulletsram;
45
	45
46	46	required_device<gfxdecode_device> m_gfxdecode;
47	47	required_device<palette_device> m_palette;
48	48

trunk/src/mame/includes/taitojc.h
r29404	r29405
70	70	required_shared_ptr<UINT32> m_main_ram;
71	71	required_shared_ptr<UINT16> m_dsp_shared_ram;
72	72	required_shared_ptr<UINT32> m_palette_ram;
73
	73
74	74	required_device<gfxdecode_device> m_gfxdecode;
75	75	required_device<screen_device> m_screen;
76	76	required_device<palette_device> m_palette;

trunk/src/mame/includes/fastfred.h
r29404	r29405
31	31	optional_shared_ptr<UINT8> m_imago_fg_videoram;
32	32	required_device<gfxdecode_device> m_gfxdecode;
33	33	required_device<palette_device> m_palette;
34
	34
35	35	UINT16 m_charbank;
36	36	UINT8 m_colorbank;
37	37	tilemap_t *m_bg_tilemap;

trunk/src/mame/includes/mcr68.h
r29404	r29405
127	127	required_device<cpu_device> m_maincpu;
128	128	required_device<gfxdecode_device> m_gfxdecode;
129	129	required_device<screen_device> m_screen;
130		required_device<palette_device> m_palette;
	130	required_device<palette_device> m_palette;
131	131	};

trunk/src/mame/includes/citycon.h
r29404	r29405
33	33	required_device<cpu_device> m_maincpu;
34	34	required_device<gfxdecode_device> m_gfxdecode;
35	35	required_device<palette_device> m_palette;
36
	36
37	37	DECLARE_READ8_MEMBER(citycon_in_r);
38	38	DECLARE_READ8_MEMBER(citycon_irq_ack_r);
39	39	DECLARE_WRITE8_MEMBER(citycon_videoram_w);

trunk/src/mame/includes/galpanic.h
r29404	r29405
20	20	required_device<gfxdecode_device> m_gfxdecode;
21	21	required_device<screen_device> m_screen;
22	22	required_device<palette_device> m_palette;
23
	23
24	24	DECLARE_WRITE16_MEMBER(galpanic_6295_bankswitch_w);
25	25	DECLARE_WRITE16_MEMBER(galpanica_6295_bankswitch_w);
26	26	DECLARE_WRITE16_MEMBER(galpanica_misc_w);

trunk/src/mame/includes/m107.h
r29404	r29405
32	32	required_device<gfxdecode_device> m_gfxdecode;
33	33	required_device<screen_device> m_screen;
34	34	required_device<palette_device> m_palette;
35
	35
36	36	UINT8 m_irq_vectorbase;
37	37	int m_sound_status;
38	38	UINT8 m_spritesystem;

trunk/src/mame/includes/namcona1.h
r29404	r29405
78	78	UINT8 m_mask_data[8];
79	79	UINT8 m_conv_data[9];
80	80
81
	81
82	82	DECLARE_READ16_MEMBER(custom_key_r);
83	83	DECLARE_WRITE16_MEMBER(custom_key_w);
84	84	DECLARE_READ16_MEMBER(namcona1_vreg_r);
r29404	r29405
111	111	DECLARE_WRITE16_MEMBER(namcona1_paletteram_w);
112	112	DECLARE_READ16_MEMBER(namcona1_gfxram_r);
113	113	DECLARE_WRITE16_MEMBER(namcona1_gfxram_w);
114		void pdraw_tile( screen_device &screen, bitmap_ind16 &dest_bmp, const rectangle &clip, UINT32 code, int color,
115		int sx, int sy, int flipx, int flipy, int priority, int bShadow, int bOpaque, int gfx_region );
	114	void pdraw_tile( screen_device &screen, bitmap_ind16 &dest_bmp, const rectangle &clip, UINT32 code, int color,
	115	int sx, int sy, int flipx, int flipy, int priority, int bShadow, int bOpaque, int gfx_region );
116	116	void draw_sprites(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
117	117	void draw_background(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int which, int primask );
118	118	DECLARE_READ16_MEMBER(snd_r);

trunk/src/mame/includes/metlclsh.h
r29404	r29405
38	38	required_device<cpu_device> m_subcpu;
39	39	required_device<gfxdecode_device> m_gfxdecode;
40	40	required_device<palette_device> m_palette;
41
	41
42	42	DECLARE_WRITE8_MEMBER(metlclsh_cause_irq);
43	43	DECLARE_WRITE8_MEMBER(metlclsh_ack_nmi);
44	44	DECLARE_WRITE8_MEMBER(metlclsh_cause_nmi2);

trunk/src/mame/includes/cave.h
r29404	r29405
240	240	optional_device<eeprom_serial_93cxx_device> m_eeprom;
241	241	required_device<gfxdecode_device> m_gfxdecode;
242	242	required_device<screen_device> m_screen;
243		required_device<palette_device> m_palette;
	243	required_device<palette_device> m_palette;
244	244	void update_irq_state();
245	245	void unpack_sprites(const char *region);
246	246	void ddonpach_unpack_sprites(const char *region);

trunk/src/mame/includes/kaneko16.h
r29404	r29405
32	32	m_view2_1(*this, "view2_1"),
33	33	m_kaneko_spr(*this, "kan_spr"),
34	34	m_pandora(*this, "pandora"),
35		m_palette(*this, "palette")
	35	m_palette(*this, "palette")
36	36	{ }
37	37
38	38	required_device<cpu_device> m_maincpu;
r29404	r29405
74	74	DECLARE_VIDEO_START(kaneko16);
75	75	DECLARE_MACHINE_RESET(mgcrystl);
76	76	UINT32 screen_update_kaneko16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
77
	77
78	78	template<class _BitmapClass>
79	79	UINT32 screen_update_common(screen_device &screen, _BitmapClass &bitmap, const rectangle &cliprect);
80	80
r29404	r29405
82	82
83	83	TIMER_DEVICE_CALLBACK_MEMBER(kaneko16_interrupt);
84	84	TIMER_DEVICE_CALLBACK_MEMBER(shogwarr_interrupt);
85
	85
86	86	template<class _BitmapClass>
87	87	void kaneko16_fill_bitmap(palette_device* palette, _BitmapClass &bitmap, const rectangle &cliprect);
88	88
r29404	r29405
123	123	: kaneko16_state(mconfig, type, tag),
124	124	m_bg15_reg(*this, "bg15_reg"),
125	125	m_bg15_select(*this, "bg15_select"),
126		m_bgpalette(*this, "bgpalette")
	126	m_bgpalette(*this, "bgpalette")
127	127
128	128	{
129	129	}

trunk/src/mame/includes/mcatadv.h
r29404	r29405
37	37	required_device<cpu_device> m_soundcpu;
38	38	required_device<gfxdecode_device> m_gfxdecode;
39	39	required_device<palette_device> m_palette;
40
	40
41	41	DECLARE_WRITE16_MEMBER(mcat_soundlatch_w);
42	42	DECLARE_WRITE16_MEMBER(mcat_coin_w);
43	43	DECLARE_READ16_MEMBER(mcat_wd_r);

trunk/src/mame/includes/dec8.h
r29404	r29405
44	44	/* memory pointers */
45	45	required_shared_ptr<UINT8> m_videoram;
46	46	optional_shared_ptr<UINT8> m_bg_data;
47
	47
48	48	required_device<gfxdecode_device> m_gfxdecode;
49	49	required_device<palette_device> m_palette;
50	50

trunk/src/mame/includes/seicross.h
r29404	r29405
21	21	required_shared_ptr<UINT8> m_row_scroll;
22	22	required_shared_ptr<UINT8> m_spriteram2;
23	23	required_shared_ptr<UINT8> m_colorram;
24
	24
25	25	UINT8 m_portb;
26	26	tilemap_t *m_bg_tilemap;
27	27	void nvram_init(nvram_device &nvram, void *data, size_t size);

trunk/src/mame/includes/system16.h
r29404	r29405
119	119	optional_device<msm5205_device> m_msm;
120	120	optional_device<upd7759_device> m_upd7759;
121	121	required_device<gfxdecode_device> m_gfxdecode;
122
	122
123	123	DECLARE_WRITE16_MEMBER(sound_command_nmi_w);
124	124	DECLARE_WRITE16_MEMBER(sound_command_w);
125	125	DECLARE_WRITE16_MEMBER(sys16_coinctrl_w);

trunk/src/mame/includes/atari.h
r29404	r29405
21	21	public:
22	22	atari_common_state(const machine_config &mconfig, device_type type, const char *tag)
23	23	: driver_device(mconfig, type, tag),
24		tv_artifacts(0) { }
	24	tv_artifacts(0) { }
25	25
26	26	void a600xl_mmu(UINT8 new_mmu);
27	27

trunk/src/mame/includes/munchmo.h
r29404	r29405
41	41	required_device<cpu_device> m_audiocpu;
42	42	required_device<gfxdecode_device> m_gfxdecode;
43	43	required_device<palette_device> m_palette;
44
	44
45	45	DECLARE_WRITE8_MEMBER(mnchmobl_nmi_enable_w);
46	46	DECLARE_WRITE8_MEMBER(mnchmobl_soundlatch_w);
47	47	DECLARE_WRITE8_MEMBER(sound_nmi_ack_w);

trunk/src/mame/includes/stadhero.h
r29404	r29405
21	21	required_shared_ptr<UINT16> m_spriteram;
22	22	required_shared_ptr<UINT16> m_pf1_data;
23	23	required_device<gfxdecode_device> m_gfxdecode;
24
	24
25	25	tilemap_t *m_pf1_tilemap;
26	26	int m_flipscreen;
27	27	DECLARE_READ16_MEMBER(stadhero_control_r);

trunk/src/mame/includes/galaga.h
r29404	r29405
32	32	required_device<namco_device> m_namco_sound;
33	33	required_device<gfxdecode_device> m_gfxdecode;
34	34	required_device<screen_device> m_screen;
35		required_device<palette_device> m_palette;
	35	required_device<palette_device> m_palette;
36	36	emu_timer *m_cpu3_interrupt_timer;
37	37	UINT8 m_custom_mod;
38	38

trunk/src/mame/includes/vaportra.h
r29404	r29405
38	38	required_device<deco_mxc06_device> m_spritegen;
39	39	required_device<buffered_spriteram16_device> m_spriteram;
40	40	required_device<palette_device> m_palette;
41
	41
42	42	DECLARE_WRITE16_MEMBER(vaportra_sound_w);
43	43	DECLARE_READ16_MEMBER(vaportra_control_r);
44	44	DECLARE_READ8_MEMBER(vaportra_soundlatch_r);

trunk/src/mame/includes/cninja.h
r29404	r29405
65	65	required_device<gfxdecode_device> m_gfxdecode;
66	66	required_device<screen_device> m_screen;
67	67	required_device<palette_device> m_palette;
68
	68
69	69	/* misc */
70	70	int m_scanline;
71	71	int m_irq_mask;

trunk/src/mame/includes/dbz.h
r29404	r29405
53	53	required_device<k053936_device> m_k053936_1;
54	54	required_device<k053936_device> m_k053936_2;
55	55	required_device<gfxdecode_device> m_gfxdecode;
56
	56
57	57	DECLARE_READ16_MEMBER(dbzcontrol_r);
58	58	DECLARE_WRITE16_MEMBER(dbzcontrol_w);
59	59	DECLARE_WRITE16_MEMBER(dbz_sound_command_w);

trunk/src/mame/includes/tceptor.h
r29404	r29405
68	68	required_device<screen_device> m_2dscreen;
69	69	required_device<gfxdecode_device> m_gfxdecode;
70	70	required_device<palette_device> m_palette;
71
	71
72	72	TILE_GET_INFO_MEMBER(get_tx_tile_info);
73	73	TILE_GET_INFO_MEMBER(get_bg1_tile_info);
74	74	TILE_GET_INFO_MEMBER(get_bg2_tile_info);

trunk/src/mame/includes/gaelco3d.h
r29404	r29405
79	79	required_device<cpu_device> m_tms;
80	80	required_device<gaelco_serial_device> m_serial;
81	81	required_device<screen_device> m_screen;
82
	82
83	83	UINT16 m_sound_data;
84	84	UINT8 m_sound_status;
85	85	offs_t m_tms_offset_xor;

trunk/src/mame/includes/hyprduel.h
r29404	r29405
69	69	required_device<gfxdecode_device> m_gfxdecode;
70	70	required_device<screen_device> m_screen;
71	71	required_device<palette_device> m_palette;
72
	72
73	73	DECLARE_READ16_MEMBER(hyprduel_irq_cause_r);
74	74	DECLARE_WRITE16_MEMBER(hyprduel_irq_cause_w);
75	75	DECLARE_WRITE16_MEMBER(hyprduel_subcpu_control_w);

trunk/src/mame/includes/calomega.h
r29404	r29405
12	12	m_videoram(*this, "videoram"),
13	13	m_colorram(*this, "colorram"),
14	14	m_gfxdecode(*this, "gfxdecode"),
15		m_palette(*this, "palette")
	15	m_palette(*this, "palette")
16	16	{
17	17	}
18	18

trunk/src/mame/includes/tubep.h
r29404	r29405
106	106	required_device<cpu_device> m_mcu;
107	107	optional_device<msm5205_device> m_msm;
108	108	required_device<screen_device> m_screen;
109
110	109
	110
111	111	protected:
112	112	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
113	113	};

trunk/src/mame/includes/exidy.h
r29404	r29405
66	66	optional_device<samples_device> m_samples;
67	67	required_device<gfxdecode_device> m_gfxdecode;
68	68	required_device<screen_device> m_screen;
69		required_device<palette_device> m_palette;
	69	required_device<palette_device> m_palette;
70	70
71	71	UINT8 m_last_dial;
72	72	UINT8 m_collision_mask;

trunk/src/mame/includes/lazercmd.h
r29404	r29405
37	37	required_device<dac_device> m_dac;
38	38	/* memory pointers */
39	39	required_shared_ptr<UINT8> m_videoram;
40
	40
41	41	required_device<gfxdecode_device> m_gfxdecode;
42	42	required_device<palette_device> m_palette;
43	43

trunk/src/mame/includes/spacefb.h
r29404	r29405
67	67	required_device<cpu_device> m_maincpu;
68	68	required_device<cpu_device> m_audiocpu;
69	69	required_device<samples_device> m_samples;
70		required_device<screen_device> m_screen;
	70	required_device<screen_device> m_screen;
71	71	};
72	72
73	73	/----------- defined in audio/spacefb.c -----------/

trunk/src/mame/includes/wiz.h
r29404	r29405
49	49	UINT8 m_main_nmi_mask;
50	50	UINT8 m_sound_nmi_mask;
51	51	UINT8 m_sprite_bank;
52
	52
53	53	int m_dsc0;
54	54	int m_dsc1;
55	55

trunk/src/mame/includes/scramble.h
r29404	r29405
49	49	DECLARE_WRITE8_MEMBER(mars_ppi8255_0_w);
50	50	DECLARE_WRITE8_MEMBER(mars_ppi8255_1_w);
51	51	DECLARE_WRITE8_MEMBER(ad2083_tms5110_ctrl_w);
52
	52
53	53	DECLARE_WRITE8_MEMBER(harem_portA_w);
54	54	DECLARE_WRITE8_MEMBER(harem_portB_w);
55	55

trunk/src/mame/includes/nemesis.h
r29404	r29405
80	80	required_device<gfxdecode_device> m_gfxdecode;
81	81	required_device<screen_device> m_screen;
82	82	required_device<palette_device> m_palette;
83
	83
84	84	DECLARE_WRITE16_MEMBER(gx400_irq1_enable_word_w);
85	85	DECLARE_WRITE16_MEMBER(gx400_irq2_enable_word_w);
86	86	DECLARE_WRITE16_MEMBER(gx400_irq4_enable_word_w);

trunk/src/mame/includes/gsword.h
r29404	r29405
48	48	DECLARE_READ8_MEMBER( gsword_8741_3_r );
49	49	DECLARE_WRITE8_MEMBER(gsword_adpcm_data_w);
50	50	DECLARE_DRIVER_INIT(gsword);
51		DECLARE_DRIVER_INIT(gsword2);
	51	DECLARE_DRIVER_INIT(gsword2);
52	52	TILE_GET_INFO_MEMBER(get_bg_tile_info);
53	53	virtual void video_start();
54	54	DECLARE_MACHINE_RESET(gsword);

trunk/src/mame/includes/sbasketb.h
r29404	r29405
35	35	required_device<vlm5030_device> m_vlm;
36	36	required_device<gfxdecode_device> m_gfxdecode;
37	37	required_device<palette_device> m_palette;
38
	38
39	39	/* video-related */
40	40	tilemap_t *m_bg_tilemap;
41	41

trunk/src/mame/includes/ironhors.h
r29404	r29405
39	39	required_device<cpu_device> m_soundcpu;
40	40	required_device<gfxdecode_device> m_gfxdecode;
41	41	required_device<palette_device> m_palette;
42
	42
43	43	DECLARE_WRITE8_MEMBER(ironhors_sh_irqtrigger_w);
44	44	DECLARE_WRITE8_MEMBER(ironhors_videoram_w);
45	45	DECLARE_WRITE8_MEMBER(ironhors_colorram_w);

trunk/src/mame/includes/bwing.h
r29404	r29405
58	58	required_device<cpu_device> m_audiocpu;
59	59	required_device<gfxdecode_device> m_gfxdecode;
60	60	required_device<palette_device> m_palette;
61
	61
62	62	DECLARE_WRITE8_MEMBER(bwp12_sharedram1_w);
63	63	DECLARE_WRITE8_MEMBER(bwp3_u8F_w);
64	64	DECLARE_WRITE8_MEMBER(bwp3_nmimask_w);

trunk/src/mame/includes/gridlee.h
r29404	r29405
38	38	required_device<cpu_device> m_maincpu;
39	39	required_device<screen_device> m_screen;
40	40	required_device<palette_device> m_palette;
41
	41
42	42	UINT8 m_last_analog_input[2];
43	43	UINT8 m_last_analog_output[2];
44	44	UINT8 *m_poly17;

trunk/src/mame/includes/lockon.h
r29404	r29405
92	92	required_device<gfxdecode_device> m_gfxdecode;
93	93	required_device<screen_device> m_screen;
94	94	required_device<palette_device> m_palette;
95
	95
96	96	DECLARE_READ16_MEMBER(lockon_crtc_r);
97	97	DECLARE_WRITE16_MEMBER(lockon_crtc_w);
98	98	DECLARE_WRITE16_MEMBER(lockon_char_w);

trunk/src/mame/includes/wecleman.h
r29404	r29405
24	24	m_k007232_3(*this, "k007232_3"),
25	25	m_gfxdecode(*this, "gfxdecode"),
26	26	m_palette(*this, "palette"),
27		m_screen(*this, "screen") { }
	27	m_screen(*this, "screen") { }
28	28
29	29	optional_shared_ptr<UINT16> m_videostatus;
30	30	optional_shared_ptr<UINT16> m_protection_ram;

trunk/src/mame/includes/crbaloon.h
r29404	r29405
32	32	required_device<sn76477_device> m_sn;
33	33	required_device<discrete_device> m_discrete;
34	34	required_device<gfxdecode_device> m_gfxdecode;
35
	35
36	36	UINT16 m_collision_address;
37	37	UINT8 m_collision_address_clear;
38	38	tilemap_t *m_bg_tilemap;

trunk/src/mame/includes/namcos1.h
r29404	r29405
34	34	required_device<dac_device> m_dac;
35	35	required_device<gfxdecode_device> m_gfxdecode;
36	36	required_device<palette_device> m_palette;
37
	37
38	38	int m_dac0_value;
39	39	int m_dac1_value;
40	40	int m_dac0_gain;

trunk/src/mame/includes/portrait.h
r29404	r29405
32	32	UINT32 screen_update_portrait(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
33	33	inline void get_tile_info( tile_data &tileinfo, int tile_index, const UINT8 *source );
34	34	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
35		required_device<cpu_device> m_maincpu;
	35	required_device<cpu_device> m_maincpu;
36	36	required_device<gfxdecode_device> m_gfxdecode;
37	37	required_device<palette_device> m_palette;
38	38	};

trunk/src/mame/includes/lastduel.h
r29404	r29405
30	30	required_shared_ptr<UINT16> m_scroll1;
31	31	required_shared_ptr<UINT16> m_scroll2;
32	32	required_shared_ptr<UINT16> m_paletteram;
33
	33
34	34	required_device<gfxdecode_device> m_gfxdecode;
35	35	required_device<palette_device> m_palette;
36
	36
37	37	/* video-related */
38	38	tilemap_t *m_bg_tilemap;
39	39	tilemap_t *m_fg_tilemap;

trunk/src/mame/includes/taito_h.h
r29404	r29405
34	34	required_device<tc0220ioc_device> m_tc0220ioc;
35	35	required_device<gfxdecode_device> m_gfxdecode;
36	36	required_device<palette_device> m_palette;
37
	37
38	38	DECLARE_READ8_MEMBER(syvalion_input_bypass_r);
39	39	DECLARE_WRITE8_MEMBER(sound_bankswitch_w);
40	40	virtual void machine_start();

trunk/src/mame/includes/centiped.h
r29404	r29405
94	94	optional_device<eeprom_serial_93cxx_device> m_eeprom;
95	95	required_device<gfxdecode_device> m_gfxdecode;
96	96	required_device<screen_device> m_screen;
97		required_device<palette_device> m_palette;
	97	required_device<palette_device> m_palette;
98	98	};

trunk/src/mame/includes/atarisy1.h
r29404	r29405
48	48	int m_next_timer_scanline;
49	49	required_device<timer_device> m_scanline_timer;
50	50	required_device<timer_device> m_int3off_timer;
51
	51
52	52	/* speech */
53	53	required_device<tms5220_device> m_tms;
54	54

trunk/src/mame/includes/irobot.h
r29404	r29405
98	98	required_device<cpu_device> m_maincpu;
99	99	required_device<gfxdecode_device> m_gfxdecode;
100	100	required_device<screen_device> m_screen;
101		required_device<palette_device> m_palette;
	101	required_device<palette_device> m_palette;
102	102	};

trunk/src/mame/includes/psikyo4.h
r29404	r29405
24	24	m_gfxdecode(*this, "gfxdecode"),
25	25	m_palette(*this, "lpalette"),
26	26	m_palette2(*this, "rpalette"),
27		m_screen(*this, "screen")
	27	m_screen(*this, "screen")
28	28	{ }
29	29
30	30	/* memory pointers */

trunk/src/mame/includes/taitosj.h
r29404	r29405
129	129	required_device<dac_device> m_dac;
130	130	required_device<gfxdecode_device> m_gfxdecode;
131	131	required_device<screen_device> m_screen;
132		required_device<palette_device> m_palette;
	132	required_device<palette_device> m_palette;
133	133	};

trunk/src/mame/includes/ms32.h
r29404	r29405
113	113	required_device<cpu_device> m_audiocpu;
114	114	required_device<gfxdecode_device> m_gfxdecode;
115	115	optional_device<screen_device> m_screen;
116		required_device<palette_device> m_palette;
	116	required_device<palette_device> m_palette;
117	117	};

trunk/src/mame/includes/fgoal.h
r29404	r29405
40	40	required_device<gfxdecode_device> m_gfxdecode;
41	41	required_device<screen_device> m_screen;
42	42	required_device<palette_device> m_palette;
43
	43
44	44	DECLARE_READ8_MEMBER(fgoal_analog_r);
45	45	DECLARE_READ8_MEMBER(fgoal_nmi_reset_r);
46	46	DECLARE_READ8_MEMBER(fgoal_irq_reset_r);

trunk/src/mame/includes/namcos2.h
r29404	r29405
227	227	optional_device<cpu_device> m_mcu;
228	228	required_device<gfxdecode_device> m_gfxdecode;
229	229	optional_device<screen_device> m_screen;
230		required_device<palette_device> m_palette;
	230	required_device<palette_device> m_palette;
231	231	};
232	232
233	233	class namcos2_state : public namcos2_shared_state

trunk/src/mame/includes/aztarac.h
r29404	r29405
23	23	required_device<vector_device> m_vector;
24	24	required_shared_ptr<UINT16> m_nvram;
25	25	required_shared_ptr<UINT16> m_vectorram;
26		required_device<screen_device> m_screen;
	26	required_device<screen_device> m_screen;
27	27
28	28	int m_sound_status;
29	29	int m_xcenter;

trunk/src/mame/includes/bigevglf.h
r29404	r29405
106	106	required_device<msm5232_device> m_msm;
107	107	required_device<gfxdecode_device> m_gfxdecode;
108	108	required_device<screen_device> m_screen;
109		required_device<palette_device> m_palette;
	109	required_device<palette_device> m_palette;
110	110	};

trunk/src/mame/includes/gyruss.h
r29404	r29405
38	38	required_device<gfxdecode_device> m_gfxdecode;
39	39	required_device<screen_device> m_screen;
40	40	required_device<palette_device> m_palette;
41
	41
42	42	tilemap_t *m_tilemap;
43	43	UINT8 m_master_nmi_mask;
44	44	UINT8 m_slave_irq_mask;

trunk/src/mame/includes/wgp.h
r29404	r29405
68	68	required_device<tc0220ioc_device> m_tc0220ioc;
69	69	required_device<gfxdecode_device> m_gfxdecode;
70	70	required_device<palette_device> m_palette;
71
	71
72	72	DECLARE_READ16_MEMBER(sharedram_r);
73	73	DECLARE_WRITE16_MEMBER(sharedram_w);
74	74	DECLARE_WRITE16_MEMBER(cpua_ctrl_w);

trunk/src/mame/includes/meadows.h
r29404	r29405
66	66	optional_device<samples_device> m_samples;
67	67	required_device<gfxdecode_device> m_gfxdecode;
68	68	required_device<screen_device> m_screen;
69		required_device<palette_device> m_palette;
	69	required_device<palette_device> m_palette;
70	70	};
71	71
72	72

trunk/src/mame/includes/cps1.h
r29404	r29405
129	129	UINT16 * m_cps2_buffered_obj;
130	130	// game-specific
131	131	UINT16 * m_gigaman2_dummyqsound_ram;
132		UINT16 sf2ceblp_prot;
	132	UINT16 sf2ceblp_prot;
133	133
134	134	/* video-related */
135	135	tilemap_t *m_bg_tilemap[3];
r29404	r29405
202	202	required_device<gfxdecode_device> m_gfxdecode;
203	203	required_device<screen_device> m_screen;
204	204	required_device<palette_device> m_palette;
205
	205
206	206	DECLARE_READ16_MEMBER(cps1_hack_dsw_r);
207	207	DECLARE_READ16_MEMBER(cps1_in1_r);
208	208	DECLARE_READ16_MEMBER(cps1_in2_r);

trunk/src/mame/includes/ssv.h
r29404	r29405
182	182	optional_ioport m_io_tracky;
183	183	required_device<gfxdecode_device> m_gfxdecode;
184	184	required_device<screen_device> m_screen;
185		required_device<palette_device> m_palette;
	185	required_device<palette_device> m_palette;
186	186	};

trunk/src/mame/includes/ojankohs.h
r29404	r29405
46	46	optional_device<gfxdecode_device> m_gfxdecode;
47	47	required_device<screen_device> m_screen;
48	48	required_device<palette_device> m_palette;
49
	49
50	50	DECLARE_WRITE8_MEMBER(ojankohs_rombank_w);
51	51	DECLARE_WRITE8_MEMBER(ojankoy_rombank_w);
52	52	DECLARE_WRITE8_MEMBER(ojankohs_msm5205_w);

trunk/src/mame/includes/thedeep.h
r29404	r29405
34	34	required_device<cpu_device> m_mcu;
35	35	required_device<gfxdecode_device> m_gfxdecode;
36	36	required_device<palette_device> m_palette;
37
	37
38	38	DECLARE_WRITE8_MEMBER(thedeep_nmi_w);
39	39	DECLARE_WRITE8_MEMBER(thedeep_sound_w);
40	40	DECLARE_WRITE8_MEMBER(thedeep_protection_w);

trunk/src/mame/includes/orbit.h
r29404	r29405
46	46	required_device<gfxdecode_device> m_gfxdecode;
47	47	required_device<screen_device> m_screen;
48	48	required_device<palette_device> m_palette;
49
	49
50	50	DECLARE_WRITE8_MEMBER(orbit_misc_w);
51	51	DECLARE_WRITE8_MEMBER(orbit_playfield_w);
52	52	TILE_GET_INFO_MEMBER(get_tile_info);

trunk/src/mame/includes/liberate.h
r29404	r29405
36	36	required_device<cpu_device> m_maincpu;
37	37	required_device<cpu_device> m_audiocpu;
38	38	required_device<gfxdecode_device> m_gfxdecode;
39		required_device<palette_device> m_palette;
	39	required_device<palette_device> m_palette;
40	40
41	41	DECLARE_READ8_MEMBER(deco16_bank_r);
42	42	DECLARE_READ8_MEMBER(deco16_io_r);

trunk/src/mame/includes/laserbat.h
r29404	r29405
23	23	m_s2636_3(*this, "s2636_3"),
24	24	m_sn(*this, "snsnd"),
25	25	m_gfxdecode(*this, "gfxdecode"),
26		m_palette(*this, "palette")
	26	m_palette(*this, "palette")
27	27	{
28	28	}
29	29

trunk/src/mame/includes/bfm_sc45.h
r29404	r29405
102	102
103	103
104	104	DECLARE_WRITE_LINE_MEMBER(bfmdm01_busy);
105
	105
106	106	DECLARE_READ16_MEMBER(sc4_mem_r);
107	107	DECLARE_WRITE16_MEMBER(sc4_mem_w);
108	108
r29404	r29405
112	112	DECLARE_WRITE_LINE_MEMBER(bfm_sc4_duart_txa);
113	113	DECLARE_READ8_MEMBER(bfm_sc4_duart_input_r);
114	114	DECLARE_WRITE8_MEMBER(bfm_sc4_duart_output_w);
115
	115
116	116	DECLARE_WRITE_LINE_MEMBER(m68307_duart_irq_handler);
117	117	DECLARE_WRITE_LINE_MEMBER(m68307_duart_txa);
118	118	DECLARE_READ8_MEMBER(m68307_duart_input_r);
119	119	DECLARE_WRITE8_MEMBER(m68307_duart_output_w);
120
	120
121	121	DECLARE_DRIVER_INIT(sc4);
122	122	DECLARE_DRIVER_INIT(sc4mbus);
123	123	DECLARE_DRIVER_INIT(sc4cvani);

trunk/src/mame/includes/ninjaw.h
r29404	r29405
61	61	required_device<filter_volume_device> m_2610_2r;
62	62	required_device<gfxdecode_device> m_gfxdecode;
63	63	required_device<palette_device> m_palette;
64
	64
65	65	DECLARE_WRITE16_MEMBER(cpua_ctrl_w);
66	66	DECLARE_WRITE8_MEMBER(sound_bankswitch_w);
67	67	DECLARE_WRITE16_MEMBER(ninjaw_sound_w);

trunk/src/mame/includes/warriorb.h
r29404	r29405
56	56	required_device<filter_volume_device> m_2610_2r;
57	57	required_device<gfxdecode_device> m_gfxdecode;
58	58	required_device<palette_device> m_palette;
59
	59
60	60	DECLARE_WRITE8_MEMBER(sound_bankswitch_w);
61	61	DECLARE_WRITE16_MEMBER(warriorb_sound_w);
62	62	DECLARE_READ16_MEMBER(warriorb_sound_r);

trunk/src/mame/includes/twin16.h
r29404	r29405
77	77	required_device<upd7759_device> m_upd7759;
78	78	required_device<gfxdecode_device> m_gfxdecode;
79	79	required_device<screen_device> m_screen;
80		required_device<palette_device> m_palette;
	80	required_device<palette_device> m_palette;
81	81	};
82	82
83	83	class cuebrickj_state : public twin16_state

trunk/src/mame/includes/tumbleb.h
r29404	r29405
49	49	required_device<okim6295_device> m_oki;
50	50	required_device<gfxdecode_device> m_gfxdecode;
51	51	required_device<palette_device> m_palette;
52
	52
53	53	UINT8 m_semicom_prot_offset;
54	54	UINT16 m_protbase;
55	55	DECLARE_WRITE16_MEMBER(tumblepb_oki_w);

trunk/src/mame/includes/micro3d.h
r29404	r29405
136	136	DECLARE_READ8_MEMBER(duart_input_r);
137	137	DECLARE_WRITE8_MEMBER(duart_output_w);
138	138	DECLARE_WRITE_LINE_MEMBER(duart_txb);
139
	139
140	140	required_device<cpu_device> m_maincpu;
141	141	required_device<i8051_device> m_audiocpu;
142	142	required_device<upd7759_device> m_upd7759;

trunk/src/mame/includes/m52.h
r29404	r29405
43	43	required_device<cpu_device> m_maincpu;
44	44	required_device<gfxdecode_device> m_gfxdecode;
45	45	required_device<screen_device> m_screen;
46		required_device<palette_device> m_palette;
	46	required_device<palette_device> m_palette;
47	47	};

trunk/src/mame/includes/amiga.h
r29404	r29405
432	432
433	433	required_device<screen_device> m_screen;
434	434	optional_device<palette_device> m_palette;
435
	435
436	436	address_space* m_maincpu_program_space;
437	437
438	438	const amiga_machine_interface *m_intf;
r29404	r29405
499	499	DECLARE_WRITE_LINE_MEMBER(amiga_cia_1_irq);
500	500	DECLARE_READ8_MEMBER( amiga_cia_0_portA_r );
501	501	DECLARE_WRITE8_MEMBER( amiga_cia_0_portA_w );
502
	502
503	503	DECLARE_READ16_MEMBER( amiga_clock_r );
504	504	DECLARE_WRITE16_MEMBER( amiga_clock_w );
505	505

trunk/src/mame/includes/gcpinbal.h
r29404	r29405
32	32	required_shared_ptr<UINT16> m_tilemapram;
33	33	required_shared_ptr<UINT16> m_spriteram;
34	34	required_shared_ptr<UINT16> m_ioc_ram;
35
	35
36	36	required_device<gfxdecode_device> m_gfxdecode;
37	37	required_device<palette_device> m_palette;
38	38	// UINT16 * m_paletteram; // currently this uses generic palette handling

trunk/src/mame/includes/lkage.h
r29404	r29405
59	59	optional_device<cpu_device> m_mcu;
60	60	required_device<gfxdecode_device> m_gfxdecode;
61	61	required_device<palette_device> m_palette;
62
	62
63	63	DECLARE_WRITE8_MEMBER(lkage_sound_command_w);
64	64	DECLARE_WRITE8_MEMBER(lkage_sh_nmi_disable_w);
65	65	DECLARE_WRITE8_MEMBER(lkage_sh_nmi_enable_w);

trunk/src/mame/includes/cvs.h
r29404	r29405
37	37	m_s2636_2(*this, "s2636_2"),
38	38	m_gfxdecode(*this, "gfxdecode"),
39	39	m_screen(*this, "screen"),
40		m_palette(*this, "palette")
	40	m_palette(*this, "palette")
41	41	{
42	42	}
43	43
r29404	r29405
81	81	required_device<gfxdecode_device> m_gfxdecode;
82	82	required_device<screen_device> m_screen;
83	83	required_device<palette_device> m_palette;
84
	84
85	85	/* memory */
86	86	UINT8 m_color_ram[0x400];
87	87	UINT8 m_palette_ram[0x10];

trunk/src/mame/includes/battlera.h
r29404	r29405
54	54	required_device<msm5205_device> m_msm;
55	55	required_device<gfxdecode_device> m_gfxdecode;
56	56	required_device<screen_device> m_screen;
57		required_device<palette_device> m_palette;
	57	required_device<palette_device> m_palette;
58	58	};

trunk/src/mame/includes/pooyan.h
r29404	r29405
28	28	required_device<cpu_device> m_maincpu;
29	29	required_device<gfxdecode_device> m_gfxdecode;
30	30	required_device<palette_device> m_palette;
31
	31
32	32	DECLARE_WRITE8_MEMBER(irq_enable_w);
33	33	DECLARE_WRITE8_MEMBER(pooyan_videoram_w);
34	34	DECLARE_WRITE8_MEMBER(pooyan_colorram_w);

trunk/src/mame/includes/stv.h
r29404	r29405
24	24	m_scudsp(*this, "scudsp"),
25	25	m_eeprom(*this, "eeprom"),
26	26	m_gfxdecode(*this, "gfxdecode"),
27		m_palette(*this, "palette")
	27	m_palette(*this, "palette")
28	28	{
29	29	}
30	30
r29404	r29405
644	644	DECLARE_WRITE_LINE_MEMBER(scudsp_end_w);
645	645	DECLARE_READ16_MEMBER(scudsp_dma_r);
646	646	DECLARE_WRITE16_MEMBER(scudsp_dma_w);
647
	647
648	648	// FROM smpc.c
649	649	TIMER_CALLBACK_MEMBER( stv_bankswitch_state );
650	650	void stv_select_game(int gameno);
r29404	r29405
671	671	void smpc_comreg_exec(address_space &space, UINT8 data, UINT8 is_stv);
672	672	DECLARE_READ8_MEMBER( stv_SMPC_r );
673	673	DECLARE_WRITE8_MEMBER( stv_SMPC_w );
674
	674
675	675	};
676	676
677	677	class stv_state : public saturn_state

trunk/src/mame/includes/equites.h
r29404	r29405
74	74	required_device<msm5232_device> m_msm;
75	75	required_device<dac_device> m_dac_1;
76	76	required_device<dac_device> m_dac_2;
77
	77
78	78	DECLARE_WRITE8_MEMBER(equites_c0f8_w);
79	79	DECLARE_WRITE8_MEMBER(equites_cymbal_ctrl_w);
80	80	DECLARE_WRITE8_MEMBER(equites_dac_latch_w);

trunk/src/mame/includes/ikki.h
r29404	r29405
24	24	required_shared_ptr<UINT8> m_videoram;
25	25	required_shared_ptr<UINT8> m_scroll;
26	26	required_shared_ptr<UINT8> m_spriteram;
27
	27
28	28	required_device<gfxdecode_device> m_gfxdecode;
29	29	required_device<screen_device> m_screen;
30	30	required_device<palette_device> m_palette;

trunk/src/mame/includes/othunder.h
r29404	r29405
78	78	required_device<filter_volume_device> m_2610_2r;
79	79	required_device<gfxdecode_device> m_gfxdecode;
80	80	required_device<palette_device> m_palette;
81
	81
82	82	DECLARE_WRITE16_MEMBER(irq_ack_w);
83	83	DECLARE_WRITE16_MEMBER(othunder_tc0220ioc_w);
84	84	DECLARE_READ16_MEMBER(othunder_tc0220ioc_r);

trunk/src/mame/includes/tail2nos.h
r29404	r29405
37	37	required_device<k051316_device> m_k051316;
38	38	required_device<gfxdecode_device> m_gfxdecode;
39	39	required_device<palette_device> m_palette;
40
	40
41	41	DECLARE_WRITE16_MEMBER(sound_command_w);
42	42	DECLARE_WRITE16_MEMBER(tail2nos_bgvideoram_w);
43	43	DECLARE_READ16_MEMBER(tail2nos_zoomdata_r);

trunk/src/mame/includes/slapshot.h
r29404	r29405
73	73	required_device<tc0640fio_device> m_tc0640fio;
74	74	required_device<gfxdecode_device> m_gfxdecode;
75	75	required_device<palette_device> m_palette;
76
	76
77	77	DECLARE_READ16_MEMBER(color_ram_word_r);
78	78	DECLARE_WRITE16_MEMBER(color_ram_word_w);
79	79	DECLARE_READ16_MEMBER(slapshot_service_input_r);

trunk/src/mame/includes/dkong.h
r29404	r29405
189	189	required_device<screen_device> m_screen;
190	190	required_device<palette_device> m_palette;
191	191	optional_device<z80dma_device> m_z80dma;
192
	192
193	193	/* radarscp_scanline */
194	194	int m_counter;
195	195

trunk/src/mame/includes/firetrk.h
r29404	r29405
64	64	optional_shared_ptr<UINT8> m_drone_rot;
65	65	required_device<gfxdecode_device> m_gfxdecode;
66	66	required_device<screen_device> m_screen;
67		required_device<palette_device> m_palette;
	67	required_device<palette_device> m_palette;
68	68
69	69	UINT8 m_in_service_mode;
70	70	UINT32 m_dial[2];

trunk/src/mame/includes/snes.h
r29404	r29405
452	452	UINT16 ver_offset;
453	453	UINT8 extbg;
454	454	} m_mode7;
455
	455
456	456	struct OAM
457	457	{
458	458	UINT16 tile;
r29404	r29405
577	577	UINT16 m_oam_ram; / Object Attribute Memory */
578	578	UINT16 m_cgram; / Palette RAM */
579	579	UINT8 m_vram; / Video RAM (TODO: Should be 16-bit, but it's easier this way) */
580
	580
581	581	snes_state *m_state;
582	582	};
583	583

trunk/src/mame/includes/rungun.h
r29404	r29405
38	38	/* memory pointers */
39	39	required_shared_ptr<UINT16> m_sysreg;
40	40	required_shared_ptr<UINT16> m_936_videoram;
41
	41
42	42	required_device<gfxdecode_device> m_gfxdecode;
43	43	required_device<palette_device> m_palette;
44	44	// UINT16 * m_paletteram; // currently this uses generic palette handling

trunk/src/mame/includes/esripsys.h
r29404	r29405
123	123	TIMER_CALLBACK_MEMBER(hblank_start_callback);
124	124	TIMER_CALLBACK_MEMBER(hblank_end_callback);
125	125	required_device<dac_device> m_dac;
126		required_device<screen_device> m_screen;
	126	required_device<screen_device> m_screen;
127	127	ESRIP_DRAW(esripsys_draw);
128	128	};
129	129

trunk/src/mame/includes/skyfox.h
r29404	r29405
30	30	required_device<cpu_device> m_maincpu;
31	31	required_device<gfxdecode_device> m_gfxdecode;
32	32	required_device<screen_device> m_screen;
33		required_device<palette_device> m_palette;
34
	33	required_device<palette_device> m_palette;
	34
35	35	DECLARE_READ8_MEMBER(skyfox_vregs_r);
36	36	DECLARE_WRITE8_MEMBER(skyfox_vregs_w);
37	37	DECLARE_INPUT_CHANGED_MEMBER(coin_inserted);

trunk/src/mame/includes/ladybug.h
r29404	r29405
49	49	required_device<cpu_device> m_maincpu;
50	50	required_device<gfxdecode_device> m_gfxdecode;
51	51	required_device<palette_device> m_palette;
52
	52
53	53	DECLARE_READ8_MEMBER(sraider_sound_low_r);
54	54	DECLARE_READ8_MEMBER(sraider_sound_high_r);
55	55	DECLARE_WRITE8_MEMBER(sraider_sound_low_w);

trunk/src/mame/includes/exidy440.h
r29404	r29405
32	32	required_device<exidy440_sound_device> m_custom;
33	33	required_device<screen_device> m_screen;
34	34	required_device<palette_device> m_palette;
35
	35
36	36	UINT8 m_bank;
37	37	const UINT8 *m_showdown_bank_data[2];
38	38	INT8 m_showdown_bank_select;

trunk/src/mame/includes/pcktgal.h
r29404	r29405
21	21	required_shared_ptr<UINT8> m_spriteram;
22	22	required_device<gfxdecode_device> m_gfxdecode;
23	23	required_device<palette_device> m_palette;
24
	24
25	25	DECLARE_WRITE8_MEMBER(pcktgal_bank_w);
26	26	DECLARE_WRITE8_MEMBER(pcktgal_sound_bank_w);
27	27	DECLARE_WRITE8_MEMBER(pcktgal_sound_w);

trunk/src/mame/includes/btime.h
r29404	r29405
63	63	required_device<gfxdecode_device> m_gfxdecode;
64	64	required_device<screen_device> m_screen;
65	65	required_device<palette_device> m_palette;
66
	66
67	67	DECLARE_WRITE8_MEMBER(audio_nmi_enable_w);
68	68	DECLARE_WRITE8_MEMBER(lnc_w);
69	69	DECLARE_WRITE8_MEMBER(mmonkey_w);

trunk/src/mame/includes/harddriv.h
r29404	r29405
379	379	DECLARE_WRITE16_MEMBER( hdds3_sdsp_control_w );
380	380	DECLARE_READ16_MEMBER( hdds3_xdsp_control_r );
381	381	DECLARE_WRITE16_MEMBER( hdds3_xdsp_control_w );
382
	382
383	383	void hdds3sdsp_reset_timer();
384	384	void hdds3xdsp_reset_timer();
385	385

trunk/src/mame/includes/cidelsa.h
r29404	r29405
65	65	DECLARE_WRITE_LINE_MEMBER( q_w );
66	66	DECLARE_WRITE_LINE_MEMBER( prd_w );
67	67	DECLARE_READ_LINE_MEMBER( cdp1869_pcb_r );
68
	68
69	69	CDP1869_CHAR_RAM_READ_MEMBER(cidelsa_charram_r);
70	70	CDP1869_CHAR_RAM_WRITE_MEMBER(cidelsa_charram_w);
71	71	CDP1869_PCB_READ_MEMBER(cidelsa_pcb_r);
r29404	r29405
104	104	DECLARE_WRITE8_MEMBER( psg_w );
105	105	DECLARE_WRITE8_MEMBER( out1_w );
106	106	DECLARE_WRITE8_MEMBER( psg_pb_w );
107
	107
108	108	CDP1869_CHAR_RAM_READ_MEMBER(draco_charram_r);
109	109	CDP1869_CHAR_RAM_WRITE_MEMBER(draco_charram_w);
110	110	CDP1869_PCB_READ_MEMBER(draco_pcb_r);

trunk/src/mame/includes/fcombat.h
r29404	r29405
54	54	required_device<cpu_device> m_maincpu;
55	55	required_device<gfxdecode_device> m_gfxdecode;
56	56	required_device<palette_device> m_palette;
57
	57
58	58	DECLARE_READ8_MEMBER(fcombat_protection_r);
59	59	DECLARE_READ8_MEMBER(fcombat_port01_r);
60	60	DECLARE_WRITE8_MEMBER(e900_w);

trunk/src/mame/includes/firetrap.h
r29404	r29405
51	51	required_device<msm5205_device> m_msm;
52	52	required_device<gfxdecode_device> m_gfxdecode;
53	53	required_device<palette_device> m_palette;
54
	54
55	55	DECLARE_WRITE8_MEMBER(firetrap_nmi_disable_w);
56	56	DECLARE_WRITE8_MEMBER(firetrap_bankselect_w);
57	57	DECLARE_READ8_MEMBER(firetrap_8751_bootleg_r);

trunk/src/mame/includes/timeplt.h
r29404	r29405
34	34	required_device<gfxdecode_device> m_gfxdecode;
35	35	required_device<screen_device> m_screen;
36	36	required_device<palette_device> m_palette;
37
	37
38	38	/* video-related */
39	39	tilemap_t *m_bg_tilemap;
40	40

trunk/src/mame/includes/topspeed.h
r29404	r29405
52	52	required_device<filter_volume_device> m_filter3;
53	53	required_device<gfxdecode_device> m_gfxdecode;
54	54	required_device<palette_device> m_palette;
55
	55
56	56	// Misc
57	57	UINT16 m_cpua_ctrl;
58	58	INT32 m_ioc220_port;

trunk/src/mame/includes/bladestl.h
r29404	r29405
55	55	K007342_CALLBACK_MEMBER(bladestl_tile_callback);
56	56	K007420_CALLBACK_MEMBER(bladestl_sprite_callback);
57	57	};
58

trunk/src/mame/includes/zac2650.h
r29404	r29405
21	21	required_device<gfxdecode_device> m_gfxdecode;
22	22	required_device<screen_device> m_screen;
23	23	required_device<palette_device> m_palette;
24
	24
25	25	bitmap_ind16 m_bitmap;
26	26	bitmap_ind16 m_spritebitmap;
27	27	int m_CollisionBackground;

trunk/src/mame/includes/gaplus.h
r29404	r29405
49	49	required_shared_ptr<UINT8> m_spriteram;
50	50	required_device<gfxdecode_device> m_gfxdecode;
51	51	required_device<screen_device> m_screen;
52		required_device<palette_device> m_palette;
	52	required_device<palette_device> m_palette;
53	53	namco58xx_device *m_namco58xx;
54	54	namco56xx_device *m_namco56xx;
55	55

trunk/src/mame/includes/thunderx.h
r29404	r29405
49	49	required_device<k052109_device> m_k052109;
50	50	required_device<k051960_device> m_k051960;
51	51	required_device<palette_device> m_palette;
52
	52
53	53	DECLARE_READ8_MEMBER(scontra_bankedram_r);
54	54	DECLARE_WRITE8_MEMBER(scontra_bankedram_w);
55	55	DECLARE_READ8_MEMBER(thunderx_bankedram_r);

trunk/src/mame/includes/homerun.h
r29404	r29405
32	32	required_device<gfxdecode_device> m_gfxdecode;
33	33	required_device<screen_device> m_screen;
34	34	required_device<palette_device> m_palette;
35
	35
36	36	UINT8 m_control;
37	37	UINT8 m_sample;
38	38

trunk/src/mame/includes/exprraid.h
r29404	r29405
28	28	required_shared_ptr<UINT8> m_spriteram;
29	29	required_shared_ptr<UINT8> m_videoram;
30	30	required_shared_ptr<UINT8> m_colorram;
31
	31
32	32	required_device<gfxdecode_device> m_gfxdecode;
33	33	required_device<palette_device> m_palette;
34	34

trunk/src/mame/includes/naughtyb.h
r29404	r29405
25	25	required_device<screen_device> m_screen;
26	26	required_device<palette_device> m_palette;
27	27
28
	28
29	29	UINT8 m_popflame_prot_seed;
30	30	int m_r_index;
31	31	int m_prot_count;

trunk/src/mame/includes/contra.h
r29404	r29405
76	76	required_device<cpu_device> m_maincpu;
77	77	required_device<gfxdecode_device> m_gfxdecode;
78	78	required_device<screen_device> m_screen;
79		required_device<palette_device> m_palette;
	79	required_device<palette_device> m_palette;
80	80	};

trunk/src/mame/includes/dcheese.h
r29404	r29405
40	40	/* devices */
41	41	required_device<cpu_device> m_maincpu;
42	42	required_device<cpu_device> m_audiocpu;
43		required_device<screen_device> m_screen;
	43	required_device<screen_device> m_screen;
44	44	device_t *m_bsmt;
45	45	DECLARE_WRITE16_MEMBER(eeprom_control_w);
46	46	DECLARE_WRITE16_MEMBER(sound_command_w);

trunk/src/mame/includes/m72.h
r29404	r29405
40	40	optional_device<m72_audio_device> m_audio;
41	41	required_device<gfxdecode_device> m_gfxdecode;
42	42	required_device<screen_device> m_screen;
43		required_device<palette_device> m_palette;
	43	required_device<palette_device> m_palette;
44	44
45	45	UINT16 *m_protection_ram;
46	46	emu_timer *m_scanline_timer;

trunk/src/mame/includes/mouser.h
r29404	r29405
20	20	/* memory pointers */
21	21	required_shared_ptr<UINT8> m_videoram;
22	22	required_shared_ptr<UINT8> m_colorram;
23		required_shared_ptr<UINT8> m_spriteram;
	23	required_shared_ptr<UINT8> m_spriteram;
24	24
25	25	/* misc */
26	26	UINT8 m_sound_byte;
r29404	r29405
31	31	required_device<cpu_device> m_audiocpu;
32	32	required_device<gfxdecode_device> m_gfxdecode;
33	33	required_device<palette_device> m_palette;
34
	34
35	35	DECLARE_WRITE8_MEMBER(mouser_nmi_enable_w);
36	36	DECLARE_WRITE8_MEMBER(mouser_sound_interrupt_w);
37	37	DECLARE_READ8_MEMBER(mouser_sound_byte_r);

trunk/src/mame/includes/deco32.h
r29404	r29405
91	91
92	92	required_device<deco16ic_device> m_deco_tilegen1;
93	93	required_device<deco16ic_device> m_deco_tilegen2;
94
	94
95	95	required_device<gfxdecode_device> m_gfxdecode;
96	96	required_device<screen_device> m_screen;
97	97	required_device<palette_device> m_palette;
98
	98
99	99	UINT8 m_irq_source;
100	100	DECLARE_WRITE_LINE_MEMBER(sound_irq_nslasher);
101	101	DECLARE_READ32_MEMBER(deco32_irq_controller_r);

trunk/src/mame/includes/playch10.h
r29404	r29405
34	34	required_shared_ptr<UINT8> m_timedata;
35	35	required_shared_ptr<UINT8> m_work_ram;
36	36	required_device<gfxdecode_device> m_gfxdecode;
37
	37
38	38	int m_up_8w;
39	39	int m_pc10_nmi_enable;
40	40	int m_pc10_dog_di;

trunk/src/mame/includes/seta.h
r29404	r29405
68	68	optional_shared_ptr<UINT16> m_kiwame_nvram;
69	69	optional_shared_ptr<UINT16> m_inttoote_key_select;
70	70	optional_shared_ptr<UINT16> m_inttoote_700000;
71
	71
72	72	required_device<gfxdecode_device> m_gfxdecode;
73	73	required_device<palette_device> m_palette;
74	74

trunk/src/mame/includes/tp84.h
r29404	r29405
31	31	required_shared_ptr<UINT8> m_spriteram;
32	32	required_device<gfxdecode_device> m_gfxdecode;
33	33	required_device<screen_device> m_screen;
34		required_device<palette_device> m_palette;
	34	required_device<palette_device> m_palette;
35	35	tilemap_t *m_bg_tilemap;
36	36	tilemap_t *m_fg_tilemap;
37	37

trunk/src/mame/includes/karnov.h
r29404	r29405
27	27	required_device<cpu_device> m_audiocpu;
28	28	required_device<buffered_spriteram16_device> m_spriteram;
29	29	required_device<deco_karnovsprites_device> m_spritegen;
30
	30
31	31	/* memory pointers */
32	32	required_shared_ptr<UINT16> m_ram;
33	33	required_shared_ptr<UINT16> m_videoram;
r29404	r29405
35	35
36	36	required_device<gfxdecode_device> m_gfxdecode;
37	37	required_device<palette_device> m_palette;
38
	38
39	39	/* video-related */
40	40	bitmap_ind16 *m_bitmap_f;
41	41	tilemap_t *m_fix_tilemap;
r29404	r29405
51	51	int m_microcontroller_id;
52	52	int m_coin_mask;
53	53	int m_latch;
54
	54
55	55	DECLARE_WRITE16_MEMBER(karnov_control_w);
56	56	DECLARE_READ16_MEMBER(karnov_control_r);
57	57	DECLARE_WRITE16_MEMBER(karnov_videoram_w);

trunk/src/mame/includes/slapfght.h
r29404	r29405
25	25	m_fixvideoram(*this, "fixvideoram"),
26	26	m_fixcolorram(*this, "fixcolorram")
27	27	{ }
28
	28
29	29	// devices, memory pointers
30	30	required_device<cpu_device> m_maincpu;
31	31	required_device<cpu_device> m_audiocpu;
r29404	r29405
137	137	DECLARE_DRIVER_INIT(getstarb1);
138	138	DECLARE_DRIVER_INIT(slapfigh);
139	139	DECLARE_DRIVER_INIT(getstarb2);
140
	140
141	141	TILE_GET_INFO_MEMBER(get_pf_tile_info);
142	142	TILE_GET_INFO_MEMBER(get_pf1_tile_info);
143	143	TILE_GET_INFO_MEMBER(get_fix_tile_info);

trunk/src/mame/includes/exerion.h
r29404	r29405
55	55	required_device<cpu_device> m_maincpu;
56	56	required_device<gfxdecode_device> m_gfxdecode;
57	57	required_device<screen_device> m_screen;
58		required_device<palette_device> m_palette;
59
	58	required_device<palette_device> m_palette;
	59
60	60	DECLARE_READ8_MEMBER(exerion_protection_r);
61	61	DECLARE_WRITE8_MEMBER(exerion_videoreg_w);
62	62	DECLARE_WRITE8_MEMBER(exerion_video_latch_w);

trunk/src/mame/includes/segas18.h
r29404	r29405
151	151	UINT8 m_wwally_last_y[3];
152	152	UINT8 m_lghost_value;
153	153	UINT8 m_lghost_select;
154
	154
155	155	required_device<gfxdecode_device> m_gfxdecode;
156	156	};

trunk/src/mame/includes/gradius3.h
r29404	r29405
43	43	required_device<k052109_device> m_k052109;
44	44	required_device<k051960_device> m_k051960;
45	45	required_device<gfxdecode_device> m_gfxdecode;
46
	46
47	47	DECLARE_READ16_MEMBER(k052109_halfword_r);
48	48	DECLARE_WRITE16_MEMBER(k052109_halfword_w);
49	49	DECLARE_READ16_MEMBER(k051937_halfword_r);

trunk/src/mame/includes/rainbow.h
r29404	r29405
43	43	optional_device<pc090oj_device> m_pc090oj;
44	44	required_device<gfxdecode_device> m_gfxdecode;
45	45	required_device<palette_device> m_palette;
46
	46
47	47	DECLARE_WRITE16_MEMBER(jumping_sound_w);
48	48	DECLARE_READ8_MEMBER(jumping_latch_r);
49	49	DECLARE_WRITE16_MEMBER(rbisland_cchip_ctrl_w);

trunk/src/mame/includes/tunhunt.h
r29404	r29405
37	37	required_device<cpu_device> m_maincpu;
38	38	required_device<gfxdecode_device> m_gfxdecode;
39	39	required_device<screen_device> m_screen;
40		required_device<palette_device> m_palette;
	40	required_device<palette_device> m_palette;
41	41	};

trunk/src/mame/includes/konamigx.h
r29404	r29405
54	54	optional_device<k054539_device> m_k054539_2;
55	55	required_device<gfxdecode_device> m_gfxdecode;
56	56	required_device<screen_device> m_screen;
57		required_device<palette_device> m_palette;
	57	required_device<palette_device> m_palette;
58	58
59	59	DECLARE_WRITE32_MEMBER(esc_w);
60	60	DECLARE_WRITE32_MEMBER(eeprom_w);

trunk/src/mame/includes/sprcros2.h
r29404	r29405
8	8	m_spriteram(*this, "spriteram"),
9	9	m_master(*this,"master"),
10	10	m_slave(*this,"slave"),
11		m_gfxdecode(*this, "gfxdecode"),
	11	m_gfxdecode(*this, "gfxdecode"),
12	12	m_palette(*this, "palette") { }
13	13
14	14	UINT8 m_s_port3;
r29404	r29405
23	23	required_device<cpu_device> m_slave;
24	24	required_device<gfxdecode_device> m_gfxdecode;
25	25	required_device<palette_device> m_palette;
26
	26
27	27	DECLARE_WRITE8_MEMBER(sprcros2_m_port7_w);
28	28	DECLARE_WRITE8_MEMBER(sprcros2_s_port3_w);
29	29	DECLARE_WRITE8_MEMBER(sprcros2_fgvideoram_w);

trunk/src/mame/includes/combatsc.h
r29404	r29405
58	58	optional_device<msm5205_device> m_msm5205;
59	59	required_device<gfxdecode_device> m_gfxdecode;
60	60	required_device<palette_device> m_palette;
61
	61
62	62	DECLARE_WRITE8_MEMBER(combatsc_vreg_w);
63	63	DECLARE_WRITE8_MEMBER(combatscb_sh_irqtrigger_w);
64	64	DECLARE_READ8_MEMBER(combatscb_io_r);

trunk/src/mame/includes/rockrage.h
r29404	r29405
37	37	required_device<vlm5030_device> m_vlm;
38	38	required_device<gfxdecode_device> m_gfxdecode;
39	39	required_device<palette_device> m_palette;
40
	40
41	41	DECLARE_WRITE8_MEMBER(rockrage_bankswitch_w);
42	42	DECLARE_WRITE8_MEMBER(rockrage_sh_irqtrigger_w);
43	43	DECLARE_WRITE8_MEMBER(rockrage_vreg_w);
r29404	r29405
53	53	K007420_CALLBACK_MEMBER(rockrage_sprite_callback);
54	54
55	55	};
56

trunk/src/mame/includes/toki.h
r29404	r29405
32	32	optional_device<msm5205_device> m_msm;
33	33	required_device<gfxdecode_device> m_gfxdecode;
34	34	required_device<screen_device> m_screen;
35		required_device<palette_device> m_palette;
	35	required_device<palette_device> m_palette;
36	36
37	37	int m_msm5205next;
38	38	int m_toggle;

trunk/src/mame/includes/pandoras.h
r29404	r29405
41	41	required_device<cpu_device> m_mcu;
42	42	required_device<gfxdecode_device> m_gfxdecode;
43	43	required_device<palette_device> m_palette;
44
	44
45	45	DECLARE_WRITE8_MEMBER(pandoras_int_control_w);
46	46	DECLARE_WRITE8_MEMBER(pandoras_cpua_irqtrigger_w);
47	47	DECLARE_WRITE8_MEMBER(pandoras_cpub_irqtrigger_w);

trunk/src/mame/includes/taito_f2.h
r29404	r29405
111	111	optional_device<tc0510nio_device> m_tc0510nio;
112	112	required_device<gfxdecode_device> m_gfxdecode;
113	113	required_device<palette_device> m_palette;
114
	114
115	115	DECLARE_WRITE16_MEMBER(growl_coin_word_w);
116	116	DECLARE_WRITE16_MEMBER(taitof2_4p_coin_word_w);
117	117	DECLARE_WRITE16_MEMBER(ninjak_coin_word_w);

trunk/src/mame/includes/gottlieb.h
r29404	r29405
233	233	required_shared_ptr<UINT8> m_videoram;
234	234	required_shared_ptr<UINT8> m_charram;
235	235	required_shared_ptr<UINT8> m_spriteram;
236
	236
237	237	required_device<gfxdecode_device> m_gfxdecode;
238	238	required_device<screen_device> m_screen;
239	239	required_device<palette_device> m_palette;
240
	240
241	241	UINT8 m_knocker_prev;
242	242	UINT8 m_joystick_select;
243	243	UINT8 m_track[2];

trunk/src/mame/includes/homedata.h
r29404	r29405
14	14	m_dac(*this, "dac"),
15	15	m_ymsnd(*this, "ymsnd"),
16	16	m_gfxdecode(*this, "gfxdecode"),
17		m_palette(*this, "palette")
	17	m_palette(*this, "palette")
18	18	{
19	19	}
20	20

trunk/src/mame/includes/deadang.h
r29404	r29405
30	30
31	31	required_device<gfxdecode_device> m_gfxdecode;
32	32	required_device<palette_device> m_palette;
33
	33
34	34	tilemap_t *m_pf3_layer;
35	35	tilemap_t *m_pf2_layer;
36	36	tilemap_t *m_pf1_layer;

trunk/src/mame/includes/mugsmash.h
r29404	r29405
27	27	required_device<cpu_device> m_audiocpu;
28	28	required_device<gfxdecode_device> m_gfxdecode;
29	29	required_device<palette_device> m_palette;
30
	30
31	31	DECLARE_WRITE16_MEMBER(mugsmash_reg2_w);
32	32	DECLARE_READ16_MEMBER(mugsmash_input_ports_r);
33	33	DECLARE_WRITE16_MEMBER(mugsmash_videoram1_w);

trunk/src/mame/includes/jackal.h
r29404	r29405
34	34	required_device<cpu_device> m_slavecpu;
35	35	required_device<gfxdecode_device> m_gfxdecode;
36	36	required_device<palette_device> m_palette;
37
	37
38	38	DECLARE_READ8_MEMBER(jackalr_rotary_r);
39	39	DECLARE_WRITE8_MEMBER(jackal_flipscreen_w);
40	40	DECLARE_READ8_MEMBER(jackal_zram_r);

trunk/src/mame/includes/macrossp.h
r29404	r29405
71	71	required_device<cpu_device> m_audiocpu;
72	72	required_device<gfxdecode_device> m_gfxdecode;
73	73	required_device<palette_device> m_palette;
74
	74
75	75	DECLARE_WRITE32_MEMBER(paletteram32_macrossp_w);
76	76	DECLARE_READ32_MEMBER(macrossp_soundstatus_r);
77	77	DECLARE_WRITE32_MEMBER(macrossp_soundcmd_w);

trunk/src/mame/includes/gladiatr.h
r29404	r29405
39	39	int m_fg_tile_bank;
40	40	int m_bg_tile_bank;
41	41
42
	42
43	43	DECLARE_READ8_MEMBER( gladiator_dsw1_r );
44	44	DECLARE_READ8_MEMBER( gladiator_dsw2_r );
45	45	DECLARE_READ8_MEMBER( gladiator_controls_r );
r29404	r29405
70	70	DECLARE_WRITE8_MEMBER(glad_adpcm_w);
71	71	DECLARE_READ8_MEMBER(f1_r);
72	72	DECLARE_DRIVER_INIT(gladiatr);
73		DECLARE_DRIVER_INIT(ppking);
	73	DECLARE_DRIVER_INIT(ppking);
74	74	TILE_GET_INFO_MEMBER(bg_get_tile_info);
75	75	TILE_GET_INFO_MEMBER(fg_get_tile_info);
76	76	DECLARE_MACHINE_RESET(ppking);

trunk/src/mame/includes/taito_o.h
r29404	r29405
24	24	required_device<tc0080vco_device> m_tc0080vco;
25	25	required_device<gfxdecode_device> m_gfxdecode;
26	26	required_device<palette_device> m_palette;
27
	27
28	28	DECLARE_WRITE16_MEMBER(io_w);
29	29	DECLARE_READ16_MEMBER(io_r);
30	30	virtual void machine_start();

trunk/src/mame/includes/1943.h
r29404	r29405
30	30	required_shared_ptr<UINT8> m_spriteram;
31	31	required_device<gfxdecode_device> m_gfxdecode;
32	32	required_device<palette_device> m_palette;
33
	33
34	34	/* video-related */
35	35	tilemap_t *m_fg_tilemap;
36	36	tilemap_t *m_bg_tilemap;

trunk/src/mame/includes/segas16b.h
r29404	r29405
200	200	UINT8 m_hwc_input_value;
201	201	UINT8 m_mj_input_num;
202	202	UINT8 m_mj_last_val;
203
	203
204	204	required_device<gfxdecode_device> m_gfxdecode;
205	205	};
206	206

trunk/src/mame/includes/pktgaldx.h
r29404	r29405
47	47	optional_device<decocomn_device> m_decocomn;
48	48	required_device<gfxdecode_device> m_gfxdecode;
49	49	required_device<palette_device> m_palette;
50
	50
51	51	DECLARE_READ16_MEMBER(pckgaldx_unknown_r);
52	52	DECLARE_READ16_MEMBER(pckgaldx_protection_r);
53	53	DECLARE_WRITE16_MEMBER(pktgaldx_oki_bank_w);

trunk/src/mame/includes/cop01.h
r29404	r29405
36	36	required_device<cpu_device> m_audiocpu;
37	37	required_device<gfxdecode_device> m_gfxdecode;
38	38	required_device<palette_device> m_palette;
39
	39
40	40	DECLARE_WRITE8_MEMBER(cop01_sound_command_w);
41	41	DECLARE_READ8_MEMBER(cop01_sound_command_r);
42	42	DECLARE_WRITE8_MEMBER(cop01_irq_ack_w);

trunk/src/mame/includes/fuukifg2.h
r29404	r29405
40	40
41	41	/* devices */
42	42	required_device<cpu_device> m_maincpu;
43		required_device<cpu_device> m_audiocpu;
	43	required_device<cpu_device> m_audiocpu;
44	44	DECLARE_WRITE16_MEMBER(fuuki16_vregs_w);
45	45	DECLARE_WRITE16_MEMBER(fuuki16_sound_command_w);
46	46	DECLARE_WRITE8_MEMBER(fuuki16_sound_rombank_w);

trunk/src/mame/includes/f1gp.h
r29404	r29405
42	42	optional_shared_ptr<UINT16> m_spriteram;
43	43	optional_shared_ptr<UINT16> m_fgregs;
44	44	optional_shared_ptr<UINT16> m_rozregs;
45
	45
46	46	optional_memory_bank m_z80bank;
47	47
48	48	/* devices referenced above */
r29404	r29405
74	74	optional_device<cpu_device> m_audiocpu;
75	75	optional_device<k053936_device> m_k053936;
76	76	required_device<palette_device> m_palette;
77
	77
78	78	DECLARE_WRITE8_MEMBER(f1gp_sh_bankswitch_w);
79	79	DECLARE_WRITE16_MEMBER(sound_command_w);
80	80	DECLARE_READ16_MEMBER(command_pending_r);

trunk/src/mame/includes/carpolo.h
r29404	r29405
65	65	required_device<ttl7474_device> m_ttl7474_1a_2;
66	66	required_device<gfxdecode_device> m_gfxdecode;
67	67	required_device<palette_device> m_palette;
68
	68
69	69	bitmap_ind16 *m_sprite_sprite_collision_bitmap1;
70	70	bitmap_ind16 *m_sprite_sprite_collision_bitmap2;
71	71	bitmap_ind16 *m_sprite_goal_collision_bitmap1;

trunk/src/mame/includes/matmania.h
r29404	r29405
60	60	required_device<gfxdecode_device> m_gfxdecode;
61	61	required_device<screen_device> m_screen;
62	62	required_device<palette_device> m_palette;
63
	63
64	64	DECLARE_WRITE8_MEMBER(matmania_sh_command_w);
65	65	DECLARE_WRITE8_MEMBER(maniach_sh_command_w);
66	66	DECLARE_WRITE8_MEMBER(matmania_paletteram_w);

trunk/src/mame/includes/volfied.h
r29404	r29405
41	41	required_device<cpu_device> m_audiocpu;
42	42	required_device<pc090oj_device> m_pc090oj;
43	43	required_device<screen_device> m_screen;
44
	44
45	45	DECLARE_WRITE16_MEMBER(volfied_cchip_ctrl_w);
46	46	DECLARE_WRITE16_MEMBER(volfied_cchip_bank_w);
47	47	DECLARE_WRITE16_MEMBER(volfied_cchip_ram_w);

trunk/src/mame/includes/crshrace.h
r29404	r29405
23	23	/* memory pointers */
24	24	required_shared_ptr<UINT16> m_videoram1;
25	25	required_shared_ptr<UINT16> m_videoram2;
26
	26
27	27	required_memory_bank m_z80bank;
28
	28
29	29	required_device<z80_device> m_audiocpu;
30	30	required_device<k053936_device> m_k053936;
31	31	required_device<buffered_spriteram16_device> m_spriteram;

trunk/src/mame/includes/airbustr.h
r29404	r29405
54	54	required_device<gfxdecode_device> m_gfxdecode;
55	55	required_device<screen_device> m_screen;
56	56	required_device<palette_device> m_palette;
57
	57
58	58	DECLARE_READ8_MEMBER(devram_r);
59	59	DECLARE_WRITE8_MEMBER(master_nmi_trigger_w);
60	60	DECLARE_WRITE8_MEMBER(master_bankswitch_w);

trunk/src/mame/includes/popeye.h
r29404	r29405
27	27	UINT8 m_bitmap_type;
28	28	tilemap_t *m_fg_tilemap;
29	29	UINT8 m_lastflip;
30		int m_field;
	30	int m_field;
31	31
32	32	DECLARE_READ8_MEMBER(protection_r);
33	33	DECLARE_WRITE8_MEMBER(protection_w);

trunk/src/mame/includes/itech32.h
r29404	r29405
196	196	optional_device<cpu_device> m_dsp1;
197	197	optional_device<cpu_device> m_dsp2;
198	198	required_device<screen_device> m_screen;
199		required_device<palette_device> m_palette;
	199	required_device<palette_device> m_palette;
200	200	};

trunk/src/mame/includes/m92.h
r29404	r29405
45	45	required_device<gfxdecode_device> m_gfxdecode;
46	46	required_device<screen_device> m_screen;
47	47	required_device<palette_device> m_palette;
48
	48
49	49	UINT16 m_sound_status;
50	50	UINT8 m_irq_vectorbase;
51	51	UINT32 m_raster_irq_position;

trunk/src/mame/includes/n8080.h
r29404	r29405
54	54	optional_device<sn76477_device> m_sn;
55	55	required_device<screen_device> m_screen;
56	56	required_device<palette_device> m_palette;
57
	57
58	58	DECLARE_WRITE8_MEMBER(n8080_shift_bits_w);
59	59	DECLARE_WRITE8_MEMBER(n8080_shift_data_w);
60	60	DECLARE_READ8_MEMBER(n8080_shift_r);

trunk/src/mame/includes/espial.h
r29404	r29405
43	43	required_device<cpu_device> m_audiocpu;
44	44	required_device<gfxdecode_device> m_gfxdecode;
45	45	required_device<palette_device> m_palette;
46
	46
47	47	DECLARE_WRITE8_MEMBER(espial_master_interrupt_mask_w);
48	48	DECLARE_WRITE8_MEMBER(espial_master_soundlatch_w);
49	49	DECLARE_WRITE8_MEMBER(espial_sound_nmi_mask_w);

trunk/src/mame/includes/lsasquad.h
r29404	r29405
43	43	optional_device<cpu_device> m_mcu;
44	44	required_device<gfxdecode_device> m_gfxdecode;
45	45	required_device<palette_device> m_palette;
46
	46
47	47	DECLARE_WRITE8_MEMBER(lsasquad_bankswitch_w);
48	48	DECLARE_WRITE8_MEMBER(lsasquad_sh_nmi_disable_w);
49	49	DECLARE_WRITE8_MEMBER(lsasquad_sh_nmi_enable_w);

trunk/src/mame/includes/grchamp.h
r29404	r29405
89	89	required_device<discrete_device> m_discrete;
90	90	required_device<gfxdecode_device> m_gfxdecode;
91	91	required_device<palette_device> m_palette;
92		required_device<screen_device> m_screen;
	92	required_device<screen_device> m_screen;
93	93	};
94	94
95	95	/* Discrete Sound Input Nodes */

trunk/src/mame/video/avgdvg.c
r29404	r29405
681	681	nvect = 0;
682	682	}
683	683
684
685		/*************************************
686		*
687		* Mhavoc handler functions
688		*
689		*************************************/
690	684
691		int avg_mhavoc_device::handler_1() // mhavoc_latch1
	685	/*************************************
	686	*
	687	* Mhavoc handler functions
	688	*
	689	*************************************/
	690
	691	int avg_mhavoc_device::handler_1() // mhavoc_latch1
692	692	{
693	693	/*
694	694	* Major Havoc just has ymin clipping
r29404	r29405
860	860	m_data = avgdvg_vectorram[m_pc];
861	861	}
862	862
863
	863
864	864	int avg_starwars_device::handler_6() // starwars_strobe2
865	865	{
866	866	if ((OP2 == 0) && (m_dvy12 == 0))
r29404	r29405
887	887	return cycles;
888	888	}
889	889
890		/*************************************
891		*
892		* Quantum handler functions
893		*
894		*************************************/
	890	/*************************************
	891	*
	892	* Quantum handler functions
	893	*
	894	*************************************/
895	895	void avg_quantum_device::update_databus() // quantum_data
896	896	{
897	897	m_data = ((UINT16 *)avgdvg_vectorram)[m_pc >> 1];
r29404	r29405
1054	1054	return cycles;
1055	1055	}
1056	1056
1057		/*************************************
1058		*
1059		* Bzone handler functions
1060		*
1061		*************************************/
	1057	/*************************************
	1058	*
	1059	* Bzone handler functions
	1060	*
	1061	*************************************/
1062	1062	int avg_bzone_device::handler_1() // bzone_latch1
1063	1063	{
1064	1064	/*
r29404	r29405
1133	1133	* Tomcat handler functions
1134	1134	*
1135	1135	*************************************/
1136
	1136
1137	1137	int avg_tomcat_device::handler_6() // starwars_strobe2
1138	1138	{
1139	1139	if ((OP2 == 0) && (m_dvy12 == 0))
r29404	r29405
1166	1166	* halt functions
1167	1167	*
1168	1168	*************************************/
1169
	1169
1170	1170	void avgdvg_device::vg_set_halt(int dummy)
1171	1171	{
1172	1172	m_halt = dummy;
r29404	r29405
1342	1342	avgdvg_vectorram_size = machine().root_device().memshare("vectorram")->bytes();
1343	1343
1344	1344	avgdvg_colorram = reinterpret_cast<UINT8 *>(machine().root_device().memshare("colorram")->ptr());
1345
	1345
1346	1346	xmin = visarea.min_x;
1347	1347	ymin = visarea.min_y;
1348	1348	xmax = visarea.max_x;
r29404	r29405
1371	1371	{
1372	1372	if(!m_vector->started())
1373	1373	throw device_missing_dependencies();
1374
	1374
1375	1375	const rectangle &visarea = machine().first_screen()->visible_area();
1376	1376
1377	1377	avgdvg_vectorram = reinterpret_cast<UINT8 *>(machine().root_device().memshare("vectorram")->ptr());
r29404	r29405
1384	1384
1385	1385	vg_halt_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(avgdvg_device::vg_set_halt_callback),this));
1386	1386	vg_run_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(avgdvg_device::run_state_machine),this));
1387
	1387
1388	1388	register_state();
1389	1389	}
1390	1390
r29404	r29405
1437	1437	m_clipy_min = 0;
1438	1438	m_clipx_max = 0;
1439	1439	m_clipy_max = 0;
1440
	1440
1441	1441	xmin = 0;
1442	1442	xmax = 0;
1443	1443	ymin = 0;
r29404	r29405
1446	1446	ycenter = 0;
1447	1447	flip_x = 0;
1448	1448	flip_y = 0;
1449		nvect = 0;
	1449	nvect = 0;
1450	1450	}
1451	1451
1452	1452	dvg_device::dvg_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :

trunk/src/mame/video/avgdvg.h
r29404	r29405
24	24	public:
25	25	// construction/destruction
26	26	avgdvg_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
27
	27
28	28	static void static_set_vector_tag(device_t &device, const char *tag);
29
	29
30	30	DECLARE_CUSTOM_INPUT_MEMBER(done_r);
31	31	DECLARE_WRITE8_MEMBER(go_w);
32	32	DECLARE_WRITE8_MEMBER(reset_w);
33
	33
34	34	DECLARE_WRITE16_MEMBER(go_word_w);
35	35	DECLARE_WRITE16_MEMBER(reset_word_w);
36	36
r29404	r29405
43	43	protected:
44	44	void apply_flipping(int x, int y);
45	45	void vg_set_halt(int dummy);
46
	46
47	47	void vg_flush();
48	48	void vg_add_point_buf(int x, int y, rgb_t color, int intensity);
49	49	void vg_add_clip (int xmin, int ymin, int xmax, int ymax);
r29404	r29405
52	52
53	53	UINT8 *avgdvg_vectorram;
54	54	size_t avgdvg_vectorram_size;
55
	55
56	56	UINT8 *avgdvg_colorram;
57
58
	57
	58
59	59	int xmin, xmax, ymin, ymax;
60	60	int xcenter, ycenter;
61	61	emu_timer vg_run_timer, vg_halt_timer;
r29404	r29405
64	64
65	65	int nvect;
66	66	vgvector vectbuf[MAXVECT];
67
68	67
	68
69	69	UINT16 m_pc;
70	70	UINT8 m_sp;
71	71	UINT16 m_dvx;
r29404	r29405
103	103	INT32 m_clipy_min;
104	104	INT32 m_clipx_max;
105	105	INT32 m_clipy_max;
106
107	106
108		virtual int handler_0() = 0;
109		virtual int handler_1() = 0;
110		virtual int handler_2() = 0;
111		virtual int handler_3() = 0;
112		virtual int handler_4() = 0;
113		virtual int handler_5() = 0;
114		virtual int handler_6() = 0;
115		virtual int handler_7() = 0;
	107
	108	virtual int handler_0() = 0;
	109	virtual int handler_1() = 0;
	110	virtual int handler_2() = 0;
	111	virtual int handler_3() = 0;
	112	virtual int handler_4() = 0;
	113	virtual int handler_5() = 0;
	114	virtual int handler_6() = 0;
	115	virtual int handler_7() = 0;
116	116	virtual UINT8 state_addr() = 0;
117	117	virtual void update_databus() = 0;
118	118	virtual void vggo() = 0;
119	119	virtual void vgrst() = 0;
120
	120
121	121	required_device<vector_device> m_vector;
122	122	};
123	123
r29404	r29405
126	126	public:
127	127	// construction/destruction
128	128	dvg_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
129
	129
130	130	void dvg_draw_to(int x, int y, int intensity);
131
132		virtual int handler_0();
133		virtual int handler_1();
134		virtual int handler_2();
135		virtual int handler_3();
136		virtual int handler_4();
137		virtual int handler_5();
138		virtual int handler_6();
139		virtual int handler_7();
	131
	132	virtual int handler_0();
	133	virtual int handler_1();
	134	virtual int handler_2();
	135	virtual int handler_3();
	136	virtual int handler_4();
	137	virtual int handler_5();
	138	virtual int handler_6();
	139	virtual int handler_7();
140	140	virtual UINT8 state_addr();
141	141	virtual void update_databus();
142	142	virtual void vggo();
143	143	virtual void vgrst();
144
	144
145	145	virtual void device_start();
146	146	};
147	147
r29404	r29405
158	158	int avg_common_strobe1();
159	159	int avg_common_strobe2();
160	160	int avg_common_strobe3();
161
162		virtual int handler_0();
163		virtual int handler_1();
164		virtual int handler_2();
165		virtual int handler_3();
166		virtual int handler_4();
167		virtual int handler_5();
168		virtual int handler_6();
169		virtual int handler_7();
	161
	162	virtual int handler_0();
	163	virtual int handler_1();
	164	virtual int handler_2();
	165	virtual int handler_3();
	166	virtual int handler_4();
	167	virtual int handler_5();
	168	virtual int handler_6();
	169	virtual int handler_7();
170	170	virtual UINT8 state_addr();
171	171	virtual void update_databus();
172	172	virtual void vggo();
173	173	virtual void vgrst();
174
	174
175	175	virtual void device_start();
176	176	void avg_start_common();
177	177	};
r29404	r29405
184	184	public:
185	185	// construction/destruction
186	186	avg_tempest_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
187
188		virtual int handler_6();
189		virtual int handler_7();
	187
	188	virtual int handler_6();
	189	virtual int handler_7();
190	190	virtual void vggo();
191	191	};
192	192
r29404	r29405
199	199	// construction/destruction
200	200	avg_mhavoc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
201	201
202		virtual int handler_1();
203		virtual int handler_6();
204		virtual int handler_7();
	202	virtual int handler_1();
	203	virtual int handler_6();
	204	virtual int handler_7();
205	205	virtual void update_databus();
206	206	virtual void vgrst();
207	207	};
r29404	r29405
214	214	public:
215	215	// construction/destruction
216	216	avg_starwars_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
217		virtual int handler_6();
218		virtual int handler_7();
	217	virtual int handler_6();
	218	virtual int handler_7();
219	219	virtual void update_databus();
220	220	};
221	221
r29404	r29405
227	227	public:
228	228	// construction/destruction
229	229	avg_quantum_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
230		virtual int handler_0();
231		virtual int handler_1();
232		virtual int handler_2();
233		virtual int handler_3();
234		virtual int handler_4();
235		virtual int handler_5();
236		virtual int handler_6();
237		virtual int handler_7();
	230	virtual int handler_0();
	231	virtual int handler_1();
	232	virtual int handler_2();
	233	virtual int handler_3();
	234	virtual int handler_4();
	235	virtual int handler_5();
	236	virtual int handler_6();
	237	virtual int handler_7();
238	238	virtual void update_databus();
239	239	virtual void vggo();
240	240	};
r29404	r29405
247	247	public:
248	248	// construction/destruction
249	249	avg_bzone_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
250		virtual int handler_1();
251		virtual int handler_6();
252		virtual int handler_7();
	250	virtual int handler_1();
	251	virtual int handler_6();
	252	virtual int handler_7();
253	253	};
254	254
255	255	// device type definition
r29404	r29405
260	260	public:
261	261	// construction/destruction
262	262	avg_tomcat_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
263
264		virtual int handler_6();
265		virtual int handler_7();
	263
	264	virtual int handler_6();
	265	virtual int handler_7();
266	266	};
267	267
268	268	// device type definition

trunk/src/mame/video/k053246_k053247_k055673.h
r29404	r29405
119	119	const char *m_memory_region;
120	120	required_device<gfxdecode_device> m_gfxdecode;
121	121	required_device<palette_device> m_palette;
122
	122
123	123	/* alt implementation - to be collapsed */
124	124	void alt_k055673_vh_start(running_machine &machine, const char *gfx_memory_region, int alt_layout, int dx, int dy,
125	125	void (callback)(running_machine &machine, int code,int color,int priority));

trunk/src/mame/video/canyon.c
r29404	r29405
39	39	int y = m_videoram[0x3d0 + 2 * i + 0x8];
40	40	int c = m_videoram[0x3d0 + 2 * i + 0x9];
41	41
42
	42
43	43	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
44	44	c >> 3,
45	45	i,

trunk/src/mame/video/sspeedr.c
r29404	r29405
196	196
197	197	y = 0xf0 - m_drones_vert[i >> 1];
198	198
199
	199
200	200	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
201	201	code[i] ^ m_toggle,
202	202	0,
r29404	r29405
226	226
227	227	y = 0xf0 - m_driver_vert;
228	228
229
	229
230	230	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect,
231	231	m_driver_pic,
232	232	0,

trunk/src/mame/video/wiz.c
r29404	r29405
121	121	UINT8 *cram = layer ? m_colorram2 : m_colorram;
122	122	gfx_element *gfx = m_gfxdecode->gfx(charbank);
123	123	int palbank = m_palbank[1] << 4 \| m_palbank[0] << 3;
124
	124
125	125	/* draw the tiles. They are characters, but draw them as sprites. */
126	126	for (int offs = 0x400-1; offs >= 0; offs--)
127	127	{
r29404	r29405
129	129	int sx = offs & 0x1f;
130	130	int sy = offs >> 5;
131	131	int color = aram[sx << 1 \| 1] & 7;
132
	132
133	133	// wiz/kungfut hw allows more color variety on screen
134	134	if (colortype)
135	135	color = layer ? (cram[offs] & 7) : ((color & 4) \| (code & 3));
r29404	r29405
154	154	UINT8 *sram = set ? m_spriteram2 : m_spriteram;
155	155	gfx_element *gfx = m_gfxdecode->gfx(charbank);
156	156	int palbank = m_palbank[1] << 4 \| m_palbank[0] << 3;
157
	157
158	158	for (int offs = 0x20-4; offs >= 0; offs -= 4)
159	159	{
160	160	int code = sram[offs + 1];
161	161	int sx = sram[offs + 3];
162	162	int sy = sram[offs];
163	163	int color = sram[offs + 2] & 7; // high bits unused
164
	164
165	165	if (!sx \|\| !sy) continue;
166
	166
167	167	// like on galaxian hw, the first three sprites match against y-1 (not on m_spriteram2)
168	168	if (set == 0 && offs <= 8)
169	169	sy += (m_flipy) ? 1 : -1;

trunk/src/mame/video/grchamp.c
r29404	r29405
121	121	if( which==0 )
122	122	{
123	123	/* draw the current player sprite into a work bitmap */
124
	124
125	125	m_gfxdecode->gfx(4)->opaque(m_work_bitmap,
126	126	m_work_bitmap.cliprect(),
127	127	m_cpu0_out[4]&0xf,
r29404	r29405
187	187	int sy = 240-source[0];
188	188	int color = source[2];
189	189	int code = source[1);
190
	190
191	191	gfx->transpen(bitmap,cliprect,
192	192	bank + (code & 0x3f),
193	193	color,

trunk/src/mame/video/kopunch.c
r29404	r29405
103	103	UINT32 kopunch_state::screen_update_kopunch(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
104	104	{
105	105	bitmap.fill(0, cliprect);
106
	106
107	107	// background does not wrap around horizontally
108	108	rectangle bg_clip = cliprect;
109	109	bg_clip.max_x = m_scrollx ^ 0xff;

trunk/src/mame/video/ladyfrog.c
r29404	r29405
131	131	m_paletteram_ext.resize(0x200);
132	132	m_palette->basemem().set(m_paletteram, ENDIANNESS_LITTLE, 1);
133	133	m_palette->extmem().set(m_paletteram_ext, ENDIANNESS_LITTLE, 1);
134
	134
135	135	m_bg_tilemap->set_scroll_cols(32);
136	136	m_bg_tilemap->set_scrolldy(15, 15);
137	137
138		save_pointer(NAME(m_spriteram), 160);
	138	save_pointer(NAME(m_spriteram), 160);
139	139	save_item(NAME(m_paletteram));
140	140	save_item(NAME(m_paletteram_ext));
141	141	}

trunk/src/mame/video/sidearms.c
r29404	r29405
185	185	y = (30 * 8) - y;
186	186	}
187	187
188
	188
189	189	gfx->transpen(bitmap,cliprect,
190	190	code, color,
191	191	flipx, flipy,

trunk/src/mame/video/k051316.h
r29404	r29405
68	68
69	69	#define MCFG_K051316_GFXDECODE(_gfxtag) \
70	70	k051316_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
71
	71
72	72	#define MCFG_K051316_PALETTE(_palette_tag) \
73	73	k051316_device::static_set_palette_tag(*device, "^" _palette_tag);
74	74	#endif

trunk/src/mame/video/tia.h
r29404	r29405
33	33
34	34	#define MCFG_TIA_DATABUS_CONTENTS_CB(_devcb) \
35	35	devcb = &tia_video_device::set_databus_contents_callback(*device, DEVCB2_##_devcb);
36
	36
37	37	#define MCFG_TIA_VSYNC_CB(_devcb) \
38	38	devcb = &tia_video_device::set_vsync_callback(*device, DEVCB2_##_devcb);
39	39
r29404	r29405
49	49	{
50	50	public:
51	51	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
52
	52
53	53	template<class _Object> static devcb2_base &set_read_input_port_callback(device_t &device, _Object object) { return downcast<tia_video_device &>(device).m_read_input_port_cb.set_callback(object); }
54	54	template<class _Object> static devcb2_base &set_databus_contents_callback(device_t &device, _Object object) { return downcast<tia_video_device &>(device).m_databus_contents_cb.set_callback(object); }
55	55	template<class _Object> static devcb2_base &set_vsync_callback(device_t &device, _Object object) { return downcast<tia_video_device &>(device).m_vsync_cb.set_callback(object); }

trunk/src/mame/video/gticlub.c
r29404	r29405
75	75	K001006_addr[i] = 0;
76	76	K001006_device_sel[i] = 0;
77	77	K001006_palette[i] = auto_alloc_array(machine, UINT32, 0x800);
78		memset(K001006_palette[i], 0, 0x800*sizeof(UINT32));
	78	memset(K001006_palette[i], 0, 0x800*sizeof(UINT32));
79	79	}
80	80	m_palette = palette;
81	81	}

trunk/src/mame/video/appoooh.c
r29404	r29405
219	219	sy = 239 - sy;
220	220	flipx = !flipx;
221	221	}
222
	222
223	223	gfx->transpen(dest_bmp,cliprect,
224	224	code,
225	225	color,
r29404	r29405
250	250	sy = 239 - sy;
251	251	flipx = !flipx;
252	252	}
253
	253
254	254	gfx->transpen(dest_bmp,cliprect,
255	255	code,
256	256	color,

trunk/src/mame/video/k007342.c
r29404	r29405
49	49	//m_regs[8],
50	50	//m_scrollx[2],
51	51	//m_scrolly[2],
52		m_gfxdecode(*this),
	52	m_gfxdecode(*this),
53	53	m_gfxnum(0)
54	54	{
55	55	}
r29404	r29405
74	74	throw device_missing_dependencies();
75	75
76	76	// bind the init function
77		m_callback.bind_relative_to(*owner());
78
	77	m_callback.bind_relative_to(*owner());
	78
79	79	m_tilemap[0] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(k007342_device::get_tile_info0),this), tilemap_mapper_delegate(FUNC(k007342_device::scan),this), 8, 8, 64, 32);
80	80	m_tilemap[1] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(k007342_device::get_tile_info1),this), tilemap_mapper_delegate(FUNC(k007342_device::scan),this), 8, 8, 64, 32);
81	81
r29404	r29405
281	281	flags = TILE_FLIPYX((color & 0x30) >> 4);
282	282
283	283	tileinfo.category = (color & 0x80) >> 7;
284
	284
285	285	if (!m_callback.isnull())
286	286	m_callback(layer, m_regs[1], &code, &color, &flags);
287
288	287
	288
289	289	SET_TILE_INFO_MEMBER(m_gfxnum,
290	290	code,
291	291	color,

trunk/src/mame/video/k007342.h
r29404	r29405
12	12
13	13	// static configuration
14	14	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
15		static void static_set_gfxnum(device_t &device, int gfxnum) { downcast<k007342_device &>(device).m_gfxnum = gfxnum; }
	15	static void static_set_gfxnum(device_t &device, int gfxnum) { downcast<k007342_device &>(device).m_gfxnum = gfxnum; }
16	16	static void static_set_callback(device_t &device, k007342_delegate callback) { downcast<k007342_device &>(device).m_callback = callback; }
17
	17
18	18	DECLARE_READ8_MEMBER( read );
19	19	DECLARE_WRITE8_MEMBER( write );
20	20	DECLARE_READ8_MEMBER( scroll_r );
r29404	r29405
56	56	extern const device_type K007342;
57	57
58	58	#define MCFG_K007342_ADD(_tag) \
59		MCFG_DEVICE_ADD(_tag, K007342, 0) \
60
	59	MCFG_DEVICE_ADD(_tag, K007342, 0)
61	60	#define MCFG_K007342_GFXDECODE(_gfxtag) \
62	61	k007342_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
63	62
r29404	r29405
68	67	k007342_device::static_set_callback(device, k007342_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
69	68
70	69	#define MCFG_K007342_CALLBACK_DEVICE(_tag, _class, _method) \
71		k007342_device::static_set_callback(*device, k007342_delegate(&_class::_method, #_class "::" #_method, _tag));
	70	k007342_device::static_set_callback(*device, k007342_delegate(&_class::_method, #_class "::" #_method, _tag));
72	71
73	72	// function definition for a callback
74		#define K007342_CALLBACK_MEMBER(_name) void _name(int layer, int bank, int code, int color, int *flags)
	73	#define K007342_CALLBACK_MEMBER(_name) void _name(int layer, int bank, int code, int color, int *flags)
75	74
76	75	#endif

trunk/src/mame/video/c45.c
r29404	r29405
232	232
233	233	void namco_c45_road_device::device_stop()
234	234	{
235
236	235	}
237	236
238	237

trunk/src/mame/video/atarimo.c
r29404	r29405
534	534	continue;
535	535
536	536	// draw the sprite
537		gfx->transpen_raw(bitmap,cliprect, code, color, hflip, vflip, sx, sy, m_transpen);
	537	gfx->transpen_raw(bitmap,cliprect, code, color, hflip, vflip, sx, sy, m_transpen);
538	538	mark_dirty(sx, sx + m_tilewidth - 1, sy, sy + m_tileheight - 1);
539	539	}
540	540	}
r29404	r29405
563	563	continue;
564	564
565	565	// draw the sprite
566		gfx->transpen_raw(bitmap,cliprect, code, color, hflip, vflip, sx, sy, m_transpen);
	566	gfx->transpen_raw(bitmap,cliprect, code, color, hflip, vflip, sx, sy, m_transpen);
567	567	mark_dirty(sx, sx + m_tilewidth - 1, sy, sy + m_tileheight - 1);
568	568	}
569	569	}

trunk/src/mame/video/decocomn.h
r29404	r29405
23	23
24	24	// static configuration
25	25	static void static_set_palette_tag(device_t &device, const char *tag);
26
	26
27	27	DECLARE_WRITE16_MEMBER( nonbuffered_palette_w );
28	28	DECLARE_WRITE16_MEMBER( buffered_palette_w );
29	29	DECLARE_WRITE16_MEMBER( palette_dma_w );
r29404	r29405
57	57
58	58	#define MCFG_DECOCOMN_PALETTE(_palette_tag) \
59	59	decocomn_device::static_set_palette_tag(*device, "^" _palette_tag);
60
	60
61	61	#endif

trunk/src/mame/video/c45.h
r29404	r29405
38	38	namco_c45_road_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
39	39
40	40	static void static_set_palette_tag(device_t &device, const char *tag);
41
	41
42	42	// read/write handlers
43	43	DECLARE_READ16_MEMBER( read );
44	44	DECLARE_WRITE16_MEMBER( write );
45
	45
46	46	// optional information overrides
47		virtual machine_config_constructor device_mconfig_additions() const;
	47	virtual machine_config_constructor device_mconfig_additions() const;
48	48
49	49	// C45 Land (Road) Emulation
50	50	void set_transparent_color(pen_t pen) { m_transparent_color = pen; }
r29404	r29405
58	58	// internal helpers
59	59	TILE_GET_INFO_MEMBER( get_road_info );
60	60
61		// internal state
	61	// internal state
62	62	pen_t m_transparent_color;
63	63	tilemap_t * m_tilemap;
64	64	UINT16 m_ram[0x20000/2]; // at 0x880000 in Final Lap; at 0xa00000 in Lucky&Wild

trunk/src/mame/video/bogeyman.c
r29404	r29405
63	63	WRITE8_MEMBER(bogeyman_state::bogeyman_paletteram_w)
64	64	{
65	65	/* RGB output is inverted */
66		m_palette->write(space, offset, UINT8(~data));
	66	m_palette->write(space, offset, UINT8(~data));
67	67	}
68	68
69	69	TILE_GET_INFO_MEMBER(bogeyman_state::get_bg_tile_info)
r29404	r29405
122	122	flipy = !flipy;
123	123	}
124	124
125
	125
126	126	m_gfxdecode->gfx(2)->transpen(bitmap,cliprect,
127	127	code, color,
128	128	flipx, flipy,
r29404	r29405
130	130
131	131	if (multi)
132	132	{
133
134	133	m_gfxdecode->gfx(2)->transpen(bitmap,cliprect,
135	134	code + 1, color,
136	135	flipx, flipy,

trunk/src/mame/video/stlforce.c
r29404	r29405
105	105
106	106	ypos = 512-ypos;
107	107
108
	108
109	109	gfx->transpen(bitmap,
110	110	cliprect,
111	111	num,

trunk/src/mame/video/tc0110pcr.c
r29404	r29405
46	46
47	47	void tc0110pcr_device::device_config_complete()
48	48	{
49
50	49	}
51	50
52	51	//-------------------------------------------------

trunk/src/mame/video/mermaid.c
r29404	r29405
208	208	sy = 240 - sy;
209	209	}
210	210
211
	211
212	212	m_gfxdecode->gfx(1)->transpen(bitmap,(flip_screen_x() ? flip_spritevisiblearea : spritevisiblearea), code, color, flipx, flipy, sx, sy, 0);
213	213	}
214	214	}

trunk/src/mame/video/tc0110pcr.h
r29404	r29405
15	15	DECLARE_WRITE16_MEMBER( step1_4bpg_word_w ); /* only 4 bits per color gun */
16	16
17	17	void restore_colors();
18
	18
19	19	static void static_set_palette_tag(device_t &device, const char *tag);
20
	20
21	21	protected:
22	22	// device-level overrides
23	23	virtual void device_config_complete();
r29404	r29405
28	28	UINT16 * m_ram;
29	29	int m_type;
30	30	int m_addr;
31		required_device<palette_device> m_palette;
	31	required_device<palette_device> m_palette;
32	32	};
33	33
34	34	extern const device_type TC0110PCR;
35	35
36	36	#define MCFG_TC0110PCR_ADD(_tag) \
37		MCFG_DEVICE_ADD(_tag, TC0110PCR, 0) \
38
	37	MCFG_DEVICE_ADD(_tag, TC0110PCR, 0)
39	38	#define MCFG_TC0110PCR_PALETTE(_palette_tag) \
40	39	tc0110pcr_device::static_set_palette_tag(*device, "^" _palette_tag);
41	40

trunk/src/mame/video/djmain.c
r29404	r29405
93	93	int zw = ox + (((x + 1) * xscale + (1 << 11)) >> 12) - sx;
94	94	int zh = oy + (((y + 1) * yscale + (1 << 11)) >> 12) - sy;
95	95
96
	96
97	97	m_gfxdecode->gfx(0)->zoom_transpen(bitmap,
98	98	cliprect,
99	99	c,
r29404	r29405
111	111	int sx = ox + (x << 4);
112	112	int sy = oy + (y << 4);
113	113
114
	114
115	115	m_gfxdecode->gfx(0)->transpen(bitmap,
116	116	cliprect,
117	117	c,

trunk/src/mame/video/decmxc06.c
r29404	r29405
96	96	if (sy >= 256) sy -= 512;
97	97	sx = 240 - sx;
98	98	sy = 240 - sy;
99
	99
100	100	if (machine.driver_data()->flip_screen())
101	101	{
102	102	sy = 240 - sy;
r29404	r29405
122	122	code += h-1;
123	123	incy = 1;
124	124	}
125
	125
126	126	for (y = 0; y < h; y++)
127	127	{
128	128	if (spriteram[offs] & 0x8000)

trunk/src/mame/video/decmxc06.h
r29404	r29405
5	5	{
6	6	public:
7	7	deco_mxc06_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
8
	8
9	9	// static configuration
10	10	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
11	11	static void static_set_palette_tag(device_t &device, const char *tag);
12	12	static void set_gfx_region(device_t &device, int region);
13
	13
14	14	void set_gfxregion(int region) { m_gfxregion = region; };
15	15	void draw_sprites( running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16* spriteram16, int pri_mask, int pri_val, int col_mask );
16	16	void draw_sprites_bootleg( running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16* spriteram, int pri_mask, int pri_val, int col_mask );

trunk/src/mame/video/tigeroad.c
r29404	r29405
96	96	flipy = !flipy;
97	97	}
98	98
99
	99
100	100	m_gfxdecode->gfx(2)->transpen(bitmap,cliprect,
101	101	tile_number,
102	102	color,

trunk/src/mame/video/decospr.h
r29404	r29405
9	9	decospr_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
10	10
11	11	// static configuration
12		static void static_set_gfxdecode_tag(device_t &device, const char *tag);
	12	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
13	13	static void static_set_palette_tag(device_t &device, const char *tag);
14	14	static void set_gfx_region(device_t &device, int gfxregion);
15	15	static void set_pri_callback(device_t &device, decospr_priority_callback_func callback);
r29404	r29405
89	89
90	90	#define MCFG_DECO_SPRITE_PALETTE(_palette_tag) \
91	91	decospr_device::static_set_palette_tag(*device, "^" _palette_tag);
92

trunk/src/mame/video/slapfght.c
r29404	r29405
60	60	{
61	61	m_pf1_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(slapfght_state::get_pf1_tile_info), this), TILEMAP_SCAN_ROWS, 8, 8, 64, 32);
62	62	m_fix_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(slapfght_state::get_fix_tile_info), this), TILEMAP_SCAN_ROWS, 8, 8, 64, 32);
63
	63
64	64	m_fix_tilemap->set_scrolldy(0, 15);
65	65	m_pf1_tilemap->set_scrolldy(0, 14);
66	66
r29404	r29405
135	135	void slapfght_state::draw_perfrman_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, int layer)
136	136	{
137	137	UINT8 *src = m_spriteram->buffer();
138
	138
139	139	for (int offs = 0; offs < m_spriteram->bytes(); offs += 4)
140	140	{
141	141	/*
142		0: xxxxxxxx - code
143		1: xxxxxxxx - x
144		2: x....... - priority over backdrop
145		.x...... - sprite-sprite priority (see point-pop sprites)
146		..x..... - ?
147		...xx... - no function?
148		.....xxx - color
149		3: xxxxxxxx - y
	142	0: xxxxxxxx - code
	143	1: xxxxxxxx - x
	144	2: x....... - priority over backdrop
	145	.x...... - sprite-sprite priority (see point-pop sprites)
	146	..x..... - ?
	147	...xx... - no function?
	148	.....xxx - color
	149	3: xxxxxxxx - y
150	150	*/
151
	151
152	152	int code = src[offs + 0];
153	153	int sy = src[offs + 3] - 1;
154	154	int sx = src[offs + 1] - 13;
155	155	int pri = src[offs + 2] >> 6 & 3;
156	156	int color = (src[offs + 2] >> 1 & 3) \| (src[offs + 2] << 2 & 4) \| (m_palette_bank << 3);
157	157	int fx = 0, fy = 0;
158
	158
159	159	if (flip_screen())
160	160	{
161	161	sy = 256 - sy;
162	162	sx = 240 - sx;
163	163	fx = fy = 1;
164	164	}
165
	165
166	166	if (layer == pri)
167	167	m_gfxdecode->gfx(1)->transpen(bitmap, cliprect, code, color, fx, fy, sx, sy, 0);
168	168	}
r29404	r29405
189	189	for (int offs = 0; offs < m_spriteram->bytes(); offs += 4)
190	190	{
191	191	/*
192		0: xxxxxxxx - code low
193		1: xxxxxxxx - x low
194		2: xx...... - code high
195		..x..... - no function?
196		...xxxx. - color
197		.......x - x high
198		3: xxxxxxxx - y
	192	0: xxxxxxxx - code low
	193	1: xxxxxxxx - x low
	194	2: xx...... - code high
	195	..x..... - no function?
	196	...xxxx. - color
	197	.......x - x high
	198	3: xxxxxxxx - y
199	199	*/
200
	200
201	201	int code = src[offs + 0] \| ((src[offs + 2] & 0xc0) << 2);
202	202	int sy = src[offs + 3];
203	203	int sx = (src[offs + 1] \| (src[offs + 2] << 8 & 0x100)) - 13;
r29404	r29405
210	210	sx = 284 - sx;
211	211	fx = fy = 1;
212	212	}
213
	213
214	214	m_gfxdecode->gfx(2)->transpen(bitmap, cliprect, code, color, fx, fy, sx, sy, 0);
215	215	}
216	216	}

trunk/src/mame/video/bfm_dm01.c
r29404	r29405
76	76	void bfmdm01_device::device_start()
77	77	{
78	78	m_busy_cb.resolve_safe();
79
	79
80	80	save_item(NAME(m_data_avail));
81	81	save_item(NAME(m_control));
82	82	save_item(NAME(m_xcounter));
r29404	r29405
100	100	m_control = 0;
101	101	m_xcounter = 0;
102	102	m_data_avail = 0;
103
	103
104	104	m_busy_cb(m_busy);
105	105	}
106	106

trunk/src/mame/video/bfm_dm01.h
r29404	r29405
16	16	public:
17	17	bfmdm01_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
18	18	~bfmdm01_device() {}
19
	19
20	20	template<class _Object> static devcb2_base &set_busy_callback(device_t &device, _Object object) { return downcast<bfmdm01_device &>(device).m_busy_cb.set_callback(object); }
21	21
22	22	DECLARE_READ8_MEMBER( control_r );
r29404	r29405
46	46
47	47	UINT8 m_scanline[DM_BYTESPERROW];
48	48	UINT8 m_comdata;
49
	49
50	50	devcb2_write_line m_busy_cb;
51	51
52	52	int read_data(void);

trunk/src/mame/video/gyruss.c
r29404	r29405
139	139	int flip_x = ~m_spriteram[offs + 2] & 0x40;
140	140	int flip_y = m_spriteram[offs + 2] & 0x80;
141	141
142		m_gfxdecode->gfx(gfx_bank)->transpen(bitmap,cliprect, code, color, flip_x, flip_y, x, y, 0);
	142	m_gfxdecode->gfx(gfx_bank)->transpen(bitmap,cliprect, code, color, flip_x, flip_y, x, y, 0);
143	143	}
144	144	}
145	145

trunk/src/mame/video/deckarn.h
r29404	r29405
6	6	deco_karnovsprites_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
7	7	void set_gfxregion(int region) { m_gfxregion = region; };
8	8	void draw_sprites( running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16* spriteram, int size, int priority );
9
	9
10	10	// static configuration
11	11	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
12	12	static void static_set_palette_tag(device_t &device, const char *tag);

trunk/src/mame/video/k053250.h
r29404	r29405
13	13	MCFG_VIDEO_SET_SCREEN(_screen_tag) \
14	14	k053250_device::static_set_offsets(*device, offx, offy);
15	15
16		class k053250_device : public device_t,
	16	class k053250_device : public device_t,
17	17	public device_gfx_interface,
18	18	public device_video_interface
19	19	{

trunk/src/mame/video/dec8.c
r29404	r29405
298	298
299	299	UINT32 dec8_state::screen_update_ghostb(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
300	300	{
301
302
303	301	m_tilegen1->deco_bac06_pf_draw(bitmap,cliprect,TILEMAP_DRAW_OPAQUE, 0x00, 0x00, 0x00, 0x00);
304	302	m_spritegen_krn->draw_sprites(machine(), bitmap, cliprect, m_buffered_spriteram16, 0x400, 0);
305	303	m_fix_tilemap->draw(screen, bitmap, cliprect, 0, 0);

trunk/src/mame/video/combatsc.c
r29404	r29405
526	526	// if(m_vreg == 0x23 && (attributes & 0x02)) color += 1*16;
527	527	// if(m_vreg == 0x66 ) color += 2*16;
528	528
529		gfx->transpen(bitmap,cliprect,
	529	gfx->transpen(bitmap,cliprect,
530	530	number, color,
531	531	attributes & 0x10,0, /* flip */
532	532	x, y, 15 );

trunk/src/mame/video/battlex.c
r29404	r29405
81	81	flipy = !flipy;
82	82	}
83	83
84		gfx->transpen(bitmap,cliprect, tile, color, flipx, flipy, sx, sy, 0);
	84	gfx->transpen(bitmap,cliprect, tile, color, flipx, flipy, sx, sy, 0);
85	85	source += 4;
86	86	}
87	87

trunk/src/mame/video/m52.c
r29404	r29405
305	305	/* this may not be correct */
306	306	ypos = ypos + (22 - 8);
307	307
308
	308
309	309	m_gfxdecode->gfx(image)->transpen(bitmap,cliprect,
310	310	0, 0,
311	311	flip_screen(),
r29404	r29405
313	313	xpos,
314	314	ypos, 0);
315	315
316
	316
317	317	m_gfxdecode->gfx(image)->transpen(bitmap,cliprect,
318	318	0, 0,
319	319	flip_screen(),

trunk/src/mame/video/gottlieb.c
r29404	r29405
209	209	if (flip_screen_x()) sx = 233 - sx;
210	210	if (flip_screen_y()) sy = 228 - sy;
211	211
212
	212
213	213	m_gfxdecode->gfx(2)->transpen(bitmap,clip,
214	214	code, 0,
215	215	flip_screen_x(), flip_screen_y(),

trunk/src/mame/video/k001604.h
r29404	r29405
24	24	// static configuration
25	25	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
26	26	static void static_set_palette_tag(device_t &device, const char *tag);
27
	27
28	28	void draw_back_layer( bitmap_rgb32 &bitmap, const rectangle &cliprect );
29	29	void draw_front_layer( screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect );
30	30	DECLARE_WRITE32_MEMBER( tile_w );

trunk/src/mame/video/mugsmash.c
r29404	r29405
43	43	xpos -= 28;
44	44	ypos -= 16;
45	45
46
	46
47	47	gfx->transpen(
48	48	bitmap,
49	49	cliprect,

trunk/src/mame/video/mikie.c
r29404	r29405
156	156	flipy = !flipy;
157	157	}
158	158
159
	159
160	160	m_gfxdecode->gfx(gfxbank)->transpen(bitmap,cliprect,
161	161	code, color,
162	162	flipx,flipy,

trunk/src/mame/video/munchmo.c
r29404	r29405
63	63
64	64	for (sy = 0; sy < 256; sy += 8)
65	65	{
66
67	66	gfx->opaque(bitmap,cliprect,
68	67	*source++,
69	68	0, /* color */
r29404	r29405
94	93	{
95	94	for (col = 0; col < 4; col++)
96	95	{
97		gfx->opaque(*m_tmpbitmap,m_tmpbitmap->cliprect(),
	96	gfx->opaque(*m_tmpbitmap,m_tmpbitmap->cliprect(),
98	97	rom[col + tile_number * 4 + row * 0x400],
99	98	m_palette_bank,
100	99	0,0, /* flip */
r29404	r29405
135	134	{
136	135	sx = (sx >> 1) \| (tile_number & 0x80);
137	136	sx = 2 * ((- 32 - scroll - sx) & 0xff) + xadjust;
138		gfx->transpen(bitmap,cliprect,
	137	gfx->transpen(bitmap,cliprect,
139	138	0x7f - (tile_number & 0x7f),
140	139	color_base - (attributes & 0x03),
141	140	0,0, /* no flip */

trunk/src/mame/video/drgnmst.c
r29404	r29405
93	93	realy = ypos + incy * y;
94	94	realnumber = number + x + y * 16;
95	95
96		gfx->transpen(bitmap,cliprect, realnumber, colr, flipx, flipy, realx, realy, 15);
	96	gfx->transpen(bitmap,cliprect, realnumber, colr, flipx, flipy, realx, realy, 15);
97	97	}
98	98	}
99	99	source += 4;

trunk/src/mame/video/thepit.c
r29404	r29405
266	266	/* sprites 0-3 are drawn one pixel down */
267	267	if (offs < 16) y++;
268	268
269
	269
270	270	state->m_gfxdecode->gfx(2 * state->m_graphics_bank + 1)->transpen(bitmap,cliprect,
271	271	state->m_spriteram[offs + 1] & 0x3f,
272	272	state->m_spriteram[offs + 2],
273	273	flipx, flipy, x, y, 0);
274	274
275
	275
276	276	state->m_gfxdecode->gfx(2 * state->m_graphics_bank + 1)->transpen(bitmap,cliprect,
277	277	state->m_spriteram[offs + 1] & 0x3f,
278	278	state->m_spriteram[offs + 2],

trunk/src/mame/video/pooyan.c
r29404	r29405
167	167	int flipx = ~spriteram_2[offs] & 0x40;
168	168	int flipy = spriteram_2[offs] & 0x80;
169	169
170
	170
171	171	m_gfxdecode->gfx(1)->transmask(bitmap,cliprect,
172	172	code,
173	173	color,

trunk/src/mame/video/champbas.c
r29404	r29405
196	196	int sx = m_spriteram_2[offs + 1] - 16;
197	197	int sy = 255 - m_spriteram_2[offs];
198	198
199
	199
200	200	gfx->transmask(bitmap,cliprect,
201	201	code, color,
202	202	flipx, flipy,
r29404	r29405
204	204	m_palette->transpen_mask(*gfx, color, 0));
205	205
206	206	// wraparound
207
	207
208	208	gfx->transmask(bitmap,cliprect,
209	209	code, color,
210	210	flipx, flipy,
r29404	r29405
234	234	color = (obj1[offs + 1]) & 0x0f;
235	235	bank = ((obj1[offs + 1] >> 4) & 1);
236	236
237
	237
238	238	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
239	239	code + (bank << 6),
240	240	color,
r29404	r29405
257	257	flipy = (~obj1[offs]) & 0x02;
258	258	color = (obj1[offs + 1]) & 0x0f;
259	259
260
	260
261	261	m_gfxdecode->gfx(2)->transmask(bitmap,cliprect,
262	262	code,
263	263	color,

trunk/src/mame/video/baraduke.c
r29404	r29405
123	123	m_bg_tilemap[0]->set_scrolldx(-26, -227+26);
124	124	m_bg_tilemap[1]->set_scrolldx(-24, -227+24);
125	125	m_bg_tilemap[0]->set_scrolldy(-9, 9);
126		m_bg_tilemap[1]->set_scrolldy(-9, 9);
	126	m_bg_tilemap[1]->set_scrolldy(-9, 9);
127	127	m_tx_tilemap->set_scrolldy(16,16);
128	128	}
129	129

trunk/src/mame/video/tceptor.c
r29404	r29405
474	474	x -= 64;
475	475	y -= 78;
476	476
477
	477
478	478	m_gfxdecode->gfx(gfx)->zoom_transmask(bitmap,
479	479	cliprect,
480	480	code,

trunk/src/mame/video/gp9001.h
r29404	r29405
141	141
142	142	#define MCFG_GP9001_VDP_PALETTE(_palette_tag) \
143	143	gp9001vdp_device::static_set_palette_tag(*device, "^" _palette_tag);
144

trunk/src/mame/video/tagteam.c
r29404	r29405
163	163	flipy = !flipy;
164	164	}
165	165
166
	166
167	167	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
168	168	code, color,
169	169	flipx, flipy,
r29404	r29405
175	175	color = m_palettebank;
176	176	sy += (flip_screen() ? -256 : 256);
177	177
178
	178
179	179	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
180	180	code, color,
181	181	flipx, flipy,

trunk/src/mame/video/battlane.c
r29404	r29405
180	180	flipy = !flipy;
181	181	}
182	182
183
	183
184	184	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect,
185	185	code,
186	186	color,
r29404	r29405
191	191	{
192	192	dy = flipy ? 16 : -16;
193	193
194
	194
195	195	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect,
196	196	code + 1,
197	197	color,

trunk/src/mame/video/tecmo_spr.c
r29404	r29405
120	120	int x = sx + 8 * (flipx ? (size - 1 - col) : col);
121	121	int y = sy + 8 * (flipy ? (size - 1 - row) : row);
122	122
123		gfxdecode->gfx(2)->transpen_raw(bitmap,cliprect,
	123	gfxdecode->gfx(2)->transpen_raw(bitmap,cliprect,
124	124	code + layout[row][col],
125	125	gfxdecode->gfx(2)->colorbase() + color * gfxdecode->gfx(2)->granularity(),
126	126	flipx, flipy,

trunk/src/mame/video/tc0480scp.h
r29404	r29405
25	25	// static configuration
26	26	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
27	27	static void static_set_palette_tag(device_t &device, const char *tag);
28
	28
29	29	/* When writing a driver, pass zero for the text and flip offsets initially:
30	30	then tweak them once you have the 4 bg layer positions correct. Col_base
31	31	may be needed when tilemaps use a palette area from sprites. */

trunk/src/mame/video/ygv608.c
r29404	r29405
73	73
74	74	void ygv608_device::set_gfxbank(UINT8 gfxbank)
75	75	{
76		m_namcond1_gfxbank = gfxbank;
	76	m_namcond1_gfxbank = gfxbank;
77	77	}
78	78
79	79	/* interrupt generated every 1ms second */
r29404	r29405
95	95	{
96	96	m_ports.s.p6 \|= p6_fv;
97	97	if (m_regs.s.r14 & r14_iev)
98		device.execute().set_input_line(2, HOLD_LINE);
	98	device.execute().set_input_line(2, HOLD_LINE);
99	99	}
100	100
101	101	/* once every 60Hz, set the position detection flag (somewhere) */
r29404	r29405
103	103	{
104	104	m_ports.s.p6 \|= p6_fp;
105	105	if (m_regs.s.r14 & r14_iep)
106		device.execute().set_input_line(2, HOLD_LINE);
	106	device.execute().set_input_line(2, HOLD_LINE);
107	107	}
108	108	}
109	109

trunk/src/mame/video/crimfght.c
r29404	r29405
64	64	m_layer_colorbase[1] = 4;
65	65	m_layer_colorbase[2] = 8;
66	66	m_sprite_colorbase = 16;
67
	67
68	68	save_item(NAME(m_paletteram));
69	69	}
70	70

trunk/src/mame/video/wolfpack.c
r29404	r29405
139	139
140	140	int chop = (scaler[m_ship_size >> 2] * m_ship_h_precess) >> 16;
141	141
142
	142
143	143	m_gfxdecode->gfx(1)->zoom_transpen(bitmap,cliprect,
144	144	m_ship_pic,
145	145	0,
r29404	r29405
157	157	int x;
158	158	int y;
159	159
160
	160
161	161	m_gfxdecode->gfx(3)->transpen(bitmap,cliprect,
162	162	m_torpedo_pic,
163	163	0,
r29404	r29405
193	193	if (!(m_pt_pic & 0x10))
194	194	rect.max_x = 255;
195	195
196
	196
197	197	m_gfxdecode->gfx(2)->transpen(bitmap,rect,
198	198	m_pt_pic,
199	199	0,
r29404	r29405
201	201	2 * m_pt_horz,
202	202	m_pt_pos_select ? 0x70 : 0xA0, 0);
203	203
204
	204
205	205	m_gfxdecode->gfx(2)->transpen(bitmap,rect,
206	206	m_pt_pic,
207	207	0,
r29404	r29405
254	254	{
255	255	int code = m_alpha_num_ram[32 * i + j];
256	256
257
	257
258	258	m_gfxdecode->gfx(0)->opaque(bitmap,cliprect,
259	259	code,
260	260	m_video_invert,

trunk/src/mame/video/ygv608.h
r29404	r29405
289	289	// static configuration
290	290	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
291	291	static void static_set_palette_tag(device_t &device, const char *tag);
292
	292
293	293	DECLARE_WRITE16_MEMBER( write );
294	294	DECLARE_READ16_MEMBER( read );
295	295

trunk/src/mame/video/darkmist.c
r29404	r29405
172	172
173	173	palette+=32;
174	174
175
	175
176	176	m_gfxdecode->gfx(2)->transpen(
177	177	bitmap,cliprect,
178	178	tile,

trunk/src/mame/video/sonson.c
r29404	r29405
154	154	flipy = !flipy;
155	155	}
156	156
157
	157
158	158	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
159	159	code, color,
160	160	flipx, flipy,

trunk/src/mame/video/seibu_crtc.h
r29404	r29405
1	1	/***************************************************************************
2	2
3		Seibu CRTC device
	3	Seibu CRTC device
4	4
5	5	***************************************************************************/
6	6
r29404	r29405
16	16
17	17	#define MCFG_SEIBU_CRTC_LAYER_EN_CB(_devcb) \
18	18	devcb = &seibu_crtc_device::set_layer_en_callback(*device, DEVCB2_##_devcb);
19
	19
20	20	#define MCFG_SEIBU_CRTC_LAYER_SCROLL_CB(_devcb) \
21	21	devcb = &seibu_crtc_device::set_layer_scroll_callback(*device, DEVCB2_##_devcb);
22	22
r29404	r29405
37	37
38	38	template<class _Object> static devcb2_base &set_layer_en_callback(device_t &device, _Object object) { return downcast<seibu_crtc_device &>(device).m_layer_en_cb.set_callback(object); }
39	39	template<class _Object> static devcb2_base &set_layer_scroll_callback(device_t &device, _Object object) { return downcast<seibu_crtc_device &>(device).m_layer_scroll_cb.set_callback(object); }
40
	40
41	41	// I/O operations
42	42	DECLARE_WRITE16_MEMBER( write );
43	43	DECLARE_WRITE16_MEMBER( write_alt );
r29404	r29405
47	47	DECLARE_READ16_MEMBER( read_xor );
48	48	DECLARE_WRITE16_MEMBER(layer_en_w);
49	49	DECLARE_WRITE16_MEMBER(layer_scroll_w);
50
	50
51	51	protected:
52	52	// device-level overrides
53	53	virtual void device_validity_check(validity_checker &valid) const;

trunk/src/mame/video/kaneko_spr.c
r29404	r29405
314	314	{
315	315	if (pri[x] < priority)
316	316	{
317
318	317	if (!rgb) dest[x] = pen_base + c;
319	318	else dest[x] = pal[pen_base + c];
320	319

trunk/src/mame/video/mystston.c
r29404	r29405
197	197	flipy = !flipy;
198	198	}
199	199
200		gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 0);
	200	gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 0);
201	201	}
202	202	}
203	203	}

trunk/src/mame/video/kaneko_spr.h
r29404	r29405
85	85	template<class _BitmapClass>
86	86	void kaneko16_draw_sprites(running_machine &machine, _BitmapClass &bitmap, const rectangle &cliprect, bitmap_ind8 &priority_bitmap, UINT16* spriteram16, int spriteram16_bytes);
87	87
88
	88
89	89	template<class _BitmapClass>
90	90	void kaneko16_draw_sprites_custom(_BitmapClass &dest_bmp,const rectangle &clip,gfx_element *gfx,
91	91	UINT32 code,UINT32 color,int flipx,int flipy,int sx,int sy,

trunk/src/mame/video/twincobr.c
r29404	r29405
94	94	m_bg_tilemap->set_scrolldy(-30, -243 );
95	95	m_fg_tilemap->set_scrolldy(-30, -243 );
96	96	m_tx_tilemap->set_scrolldy(-30, -243 );
97
	97
98	98	m_fg_tilemap->set_transparent_pen(0);
99	99	m_tx_tilemap->set_transparent_pen(0);
100	100	}

trunk/src/mame/video/decbac06.h
r29404	r29405
108	108	TILEMAP_MAPPER_MEMBER(tile_shape2_8x8_scan);
109	109	TILE_GET_INFO_MEMBER(get_pf8x8_tile_info);
110	110	TILE_GET_INFO_MEMBER(get_pf16x16_tile_info);
111		required_device<gfxdecode_device> m_gfxdecode;
	111	required_device<gfxdecode_device> m_gfxdecode;
112	112	};
113	113
114	114	extern const device_type DECO_BAC06;

trunk/src/mame/video/gotya.c
r29404	r29405
125	125	else
126	126	sy = 31 - row;
127	127
128
	128
129	129	m_gfxdecode->gfx(0)->opaque(bitmap,cliprect,
130	130	m_videoram2[row * 32 + col],
131	131	m_videoram2[row * 32 + col + 0x10] & 0x0f,
r29404	r29405
149	149	if (flip_screen())
150	150	sy = 240 - sy;
151	151
152
	152
153	153	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
154	154	code, color,
155	155	flip_screen_x(), flip_screen_y(),

trunk/src/mame/video/ms32.c
r29404	r29405
97	97
98	98	// tp2m32 doesn't set the brightness registers so we need sensible defaults
99	99	m_brt[0] = m_brt[1] = 0xffff;
100
	100
101	101	save_item(NAME(m_irqreq));
102	102	save_item(NAME(m_temp_bitmap_tilemaps));
103	103	save_item(NAME(m_temp_bitmap_sprites));

trunk/src/mame/video/zaxxon.c
r29404	r29405
428	428	int sx = find_minimum_x(spriteram[offs + 3], flip);
429	429
430	430	/* draw with 256 pixel offsets to ensure we wrap properly */
431		gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, sx, sy, 0);
432		gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, sx, sy - 0x100, 0);
433		gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, sx - 0x100, sy, 0);
434		gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, sx - 0x100, sy - 0x100, 0);
	431	gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, sx, sy, 0);
	432	gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, sx, sy - 0x100, 0);
	433	gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, sx - 0x100, sy, 0);
	434	gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, sx - 0x100, sy - 0x100, 0);
435	435	}
436	436	}
437	437

trunk/src/mame/video/taito_h.c
r29404	r29405
144	144	flipy ^= 0x0080;
145	145	}
146	146
147
	147
148	148	m_gfxdecode->gfx(0)->zoom_transpen(bitmap,cliprect,
149	149	tile,
150	150	color,
r29404	r29405
256	256	flipy ^= 0x0080;
257	257	}
258	258
259
	259
260	260	m_gfxdecode->gfx(0)->zoom_transpen(bitmap,cliprect,
261	261	tile,
262	262	color,
r29404	r29405
358	358	flipy ^= 0x0080;
359	359	}
360	360
361
	361
362	362	m_gfxdecode->gfx(0)->zoom_transpen(bitmap,cliprect,
363	363	tile,
364	364	color,

trunk/src/mame/video/psikyo4.c
r29404	r29405
112	112	{
113	113	for (i = xstart; i != xend; i += xinc)
114	114	{
115		gfx->transpen(bitmap,cliprect, tnum + loopnum, colr, flipx, flipy, xpos + 16 * i, ypos + 16 * j, 0);
	115	gfx->transpen(bitmap,cliprect, tnum + loopnum, colr, flipx, flipy, xpos + 16 * i, ypos + 16 * j, 0);
116	116	loopnum++;
117	117	}
118	118	}

trunk/src/mame/video/taitosj.c
r29404	r29405
301	301
302	302	/* draw the sprites into separate bitmaps and check overlapping region */
303	303	m_sprite_layer_collbitmap1.fill(TRANSPARENT_PEN);
304		get_sprite_gfx_element(which1)->transpen(m_sprite_sprite_collbitmap1,m_sprite_sprite_collbitmap1.cliprect(),
	304	get_sprite_gfx_element(which1)->transpen(m_sprite_sprite_collbitmap1,m_sprite_sprite_collbitmap1.cliprect(),
305	305	m_spriteram[SPRITE_RAM_PAGE_OFFSET + offs1 + 3] & 0x3f,
306	306	0,
307	307	m_spriteram[SPRITE_RAM_PAGE_OFFSET + offs1 + 2] & 0x01,
r29404	r29405
309	309	sx1, sy1, 0);
310	310
311	311	m_sprite_sprite_collbitmap2.fill(TRANSPARENT_PEN);
312		get_sprite_gfx_element(which2)->transpen(m_sprite_sprite_collbitmap2,m_sprite_sprite_collbitmap2.cliprect(),
	312	get_sprite_gfx_element(which2)->transpen(m_sprite_sprite_collbitmap2,m_sprite_sprite_collbitmap2.cliprect(),
313	313	m_spriteram[SPRITE_RAM_PAGE_OFFSET + offs2 + 3] & 0x3f,
314	314	0,
315	315	m_spriteram[SPRITE_RAM_PAGE_OFFSET + offs2 + 2] & 0x01,

trunk/src/mame/video/chaknpop.c
r29404	r29405
198	198	flipy = !flipy;
199	199	}
200	200
201
	201
202	202	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect,
203	203	tile,
204	204	color,

trunk/src/mame/video/fitfight.c
r29404	r29405
34	34
35	35	if (end) break;
36	36	if (prio == layer)
37		gfx->transpen(bitmap,cliprect, number, colr, xflip, yflip, xpos, ypos, 0);
	37	gfx->transpen(bitmap,cliprect, number, colr, xflip, yflip, xpos, ypos, 0);
38	38
39	39	source += 4;
40	40	}

trunk/src/mame/video/cps1.c
r29404	r29405
1397	1397	{"sf2acca", CPS_B_21_DEF, mapper_S9263B, 0x36 },
1398	1398	{"sf2accp2", CPS_B_21_DEF, mapper_S9263B, 0x36 },
1399	1399	{"sf2amf", CPS_B_21_DEF, mapper_S9263B, 0x36, 0, 0, 1 }, // probably wrong but this set is not completely dumped anyway
1400		{"sf2amf2", CPS_B_21_DEF, mapper_S9263B, 0x36, 0, 0, 1 },
	1400	{"sf2amf2", CPS_B_21_DEF, mapper_S9263B, 0x36, 0, 0, 1 },
1401	1401	{"sf2dkot2", CPS_B_21_DEF, mapper_S9263B, 0x36 },
1402	1402	{"sf2m1", CPS_B_21_DEF, mapper_S9263B, 0x36 },
1403	1403	{"sf2m2", CPS_B_21_DEF, mapper_S9263B, 0x36, 0, 0, 1 },

trunk/src/mame/video/ddribble.c
r29404	r29405
218	218	ex = flipx ? (width - 1 - x) : x;
219	219	ey = flipy ? (height - 1 - y) : y;
220	220
221
	221
222	222	gfx->transpen(bitmap,cliprect,
223	223	(number)+x_offset[ex]+y_offset[ey],
224	224	color,

trunk/src/mame/video/shangkid.c
r29404	r29405
141	141	{
142	142	sx = xpos+(c^xflip)*width;
143	143	sy = ypos+(r^yflip)*height;
144
	144
145	145	gfx->zoom_transpen(
146	146	bitmap,
147	147	cliprect,
r29404	r29405
152	152	(width<<16)/16, (height<<16)/16,transparent_pen );
153	153
154	154	// wrap around y
155
	155
156	156	gfx->zoom_transpen(
157	157	bitmap,
158	158	cliprect,
r29404	r29405
264	264	if( pri==0 \|\| (attr>>7)==pri )
265	265	{
266	266	tile += ((attr>>5)&0x3)*256;
267
	267
268	268	m_gfxdecode->gfx(0)->transpen(
269	269	bitmap,
270	270	cliprect,
r29404	r29405
297	297	sx = videoram[0x1381+i]-64+8+16;
298	298	if( attr&1 ) sx += 0x100;
299	299
300
	300
301	301	m_gfxdecode->gfx(1)->transpen(
302	302	bitmap,
303	303	cliprect,

trunk/src/mame/video/trackfld.c
r29404	r29405
220	220	//}
221	221
222	222
223
	223
224	224	m_gfxdecode->gfx(0)->transmask(bitmap,cliprect,
225	225	code + m_sprite_bank1 + m_sprite_bank2, color,
226	226	flipx, flipy,
r29404	r29405
228	228	m_palette->transpen_mask(*m_gfxdecode->gfx(0), color, 0));
229	229
230	230	/* redraw with wraparound */
231
	231
232	232	m_gfxdecode->gfx(0)->transmask(bitmap,cliprect,
233	233	code + m_sprite_bank1 + m_sprite_bank2, color,
234	234	flipx, flipy,

trunk/src/mame/video/k001005.h
r29404	r29405
28	28	~k001005_device() {}
29	29
30	30	static void static_set_palette_tag(device_t &device, const char *tag);
31
	31
32	32	void draw(bitmap_rgb32 &bitmap, const rectangle &cliprect);
33	33	void swap_buffers();
34	34	void preprocess_texture_data(UINT8 *rom, int length, int gticlub);

trunk/src/mame/video/k007121.h
r29404	r29405
9	9	~k007121_device() {}
10	10
11	11	static void static_set_palette_tag(device_t &device, const char *tag);
12
	12
13	13	DECLARE_READ8_MEMBER( ctrlram_r );
14	14	DECLARE_WRITE8_MEMBER( ctrl_w );
15	15

trunk/src/mame/video/oneshot.c
r29404	r29405
122	122	{
123	123	for (blocky = 0; blocky < ysize; blocky++)
124	124	{
125
126	125	gfx->transpen(
127	126	bitmap,
128	127	cliprect,
r29404	r29405
131	130	0,0,
132	131	xpos + blockx * 8, ypos + blocky * 8, 0);
133	132
134
	133
135	134	gfx->transpen(
136	135	bitmap,
137	136	cliprect,

trunk/src/mame/video/cclimber.c
r29404	r29405
569	569	flipy = !flipy;
570	570	}
571	571
572		gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 0);
	572	gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 0);
573	573	}
574	574	}
575	575
r29404	r29405
606	606	flipy = !flipy;
607	607	}
608	608
609		gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 0);
	609	gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 0);
610	610	}
611	611	}
612	612
r29404	r29405
643	643	flipy = !flipy;
644	644	}
645	645
646		gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 0);
	646	gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 0);
647	647	}
648	648	}
649	649

trunk/src/mame/video/amspdwy.c
r29404	r29405
18	18
19	19	WRITE8_MEMBER(amspdwy_state::amspdwy_paletteram_w)
20	20	{
21		m_palette->write(space, offset, UINT8(~data));
	21	m_palette->write(space, offset, UINT8(~data));
22	22	}
23	23
24	24	WRITE8_MEMBER(amspdwy_state::amspdwy_flipscreen_w)

trunk/src/mame/video/namcona1.c
r29404	r29405
278	278	{
279	279	m_tilemap_palette_bank[i] = -1;
280	280	}
281
	281
282	282	m_bg_tilemap[0] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info0),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
283	283	m_bg_tilemap[1] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info1),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );
284	284	m_bg_tilemap[2] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info2),this), TILEMAP_SCAN_ROWS, 8,8,64,64 );

trunk/src/mame/video/kaneko16.c
r29404	r29405
180	180	WRITE16_MEMBER(kaneko16_berlwall_state::kaneko16_bg15_reg_w)
181	181	{
182	182	COMBINE_DATA(&m_bg15_reg[0]);
183		// printf("kaneko16_bg15_reg_w %04x\n", m_bg15_reg[0]);
	183	// printf("kaneko16_bg15_reg_w %04x\n", m_bg15_reg[0]);
184	184	double brt1 = data & 0xff;
185	185	brt1 = brt1 / 255.0;
186	186
r29404	r29405
198	198	int flip = select & 0x20;
199	199	int sx;//, sy;
200	200
201		// if (flip) select ^= 0x1f;
	201	// if (flip) select ^= 0x1f;
202	202
203	203	sx = (select & 0x1f) * 256;
204		// sy = 0;
	204	// sy = 0;
205	205
206	206	const pen_t *pal = m_bgpalette->pens();
207	207	UINT16* srcbitmap;

trunk/src/mame/video/stadhero.c
r29404	r29405
23	23	// machine().tilemap().set_flip_all(m_flipscreen ? (TILEMAP_FLIPY \| TILEMAP_FLIPX) : 0);
24	24
25	25	flip_screen_set(m_tilegen1->get_flip_state());
26
	26
27	27	m_tilegen1->set_bppmultmask(0x8, 0x7);
28	28	m_tilegen1->deco_bac06_pf_draw(bitmap,cliprect,TILEMAP_DRAW_OPAQUE, 0x00, 0x00, 0x00, 0x00);
29	29	m_spritegen->draw_sprites(machine(), bitmap, cliprect, m_spriteram, 0x00, 0x00, 0x0f);

trunk/src/mame/video/popeye.c
r29404	r29405
58	58
59	59	static const res_net_decode_info popeye_7051_decode_info =
60	60	{
61		1, /* one prom 5 lines */
62		0, /* start at 0 */
63		15, /* end at 15 (banked) */
	61	1, /* one prom 5 lines */
	62	0, /* start at 0 */
	63	15, /* end at 15 (banked) */
64	64	/* R, G, B, */
65		{ 0, 0, 0 }, /* offsets */
66		{ 0, 3, 6 }, /* shifts */
67		{0x07,0x07,0x03 } /* masks */
	65	{ 0, 0, 0 }, /* offsets */
	66	{ 0, 3, 6 }, /* shifts */
	67	{0x07,0x07,0x03 } /* masks */
68	68	};
69	69
70	70	static const res_net_decode_info popeye_7052_decode_info =
71	71	{
72		2, /* there may be two proms needed to construct color */
73		0, /* start at 0 */
74		255, /* end at 255 */
	72	2, /* there may be two proms needed to construct color */
	73	0, /* start at 0 */
	74	255, /* end at 255 */
75	75	/* R, G, B, R, G, B */
76		{ 0, 0, 0, 256, 256, 256}, /* offsets */
77		{ 0, 3, 0, 0, -1, 2}, /* shifts */
78		{0x07,0x01,0x00,0x00,0x06,0x03} /* masks */
	76	{ 0, 0, 0, 256, 256, 256}, /* offsets */
	77	{ 0, 3, 0, 0, -1, 2}, /* shifts */
	78	{0x07,0x01,0x00,0x00,0x06,0x03} /* masks */
79	79	};
80	80
81	81	static const res_net_info popeye_7051_txt_net_info =
r29404	r29405
122	122	#if USE_NEW_COLOR
123	123	for (i = 0; i < 16; i++)
124	124	{
125		int prom_offs = i \| ((i & 8) << 1); /* address bits 3 and 4 are tied together */
	125	int prom_offs = i \| ((i & 8) << 1); /* address bits 3 and 4 are tied together */
126	126	int r, g, b;
127	127	r = compute_res_net(((color_prom[prom_offs] ^ m_invertmask) >> 0) & 0x07, 0, popeye_7051_txt_net_info);
128	128	g = compute_res_net(((color_prom[prom_offs] ^ m_invertmask) >> 3) & 0x07, 1, popeye_7051_txt_net_info);
r29404	r29405
344	344	m_fg_tilemap->set_transparent_pen(0);
345	345
346	346	m_lastflip = 0;
347		m_field = 0;
	347	m_field = 0;
348	348
349		save_item(NAME(m_field));
350		save_item(NAME(m_lastflip));
	349	save_item(NAME(m_field));
	350	save_item(NAME(m_lastflip));
351	351	save_item(NAME(*m_tmpbitmap2));
352	352	save_pointer(NAME(m_bitmapram), popeye_bitmapram_size);
353	353	}
r29404	r29405
362	362	m_fg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(popeye_state::get_fg_tile_info),this), TILEMAP_SCAN_ROWS, 16, 16, 32, 32);
363	363	m_fg_tilemap->set_transparent_pen(0);
364	364
365		m_lastflip = 0;
366		m_field = 0;
	365	m_lastflip = 0;
	366	m_field = 0;
367	367
368		save_item(NAME(m_field));
	368	save_item(NAME(m_field));
369	369	save_item(NAME(m_lastflip));
370	370	save_item(NAME(*m_tmpbitmap2));
371	371	save_pointer(NAME(m_bitmapram), popeye_bitmapram_size);

trunk/src/mame/video/starcrus.c
r29404	r29405
164	164	org_y = m_s1_y;
165	165
166	166	/* Draw ship 1 */
167
	167
168	168	m_gfxdecode->gfx(8+((m_s1_sprite&0x04)>>2))->opaque(*m_ship1_vid,
169	169	clip,
170	170	(m_s1_sprite&0x03)^0x03,
r29404	r29405
173	173	m_s1_x-org_x, m_s1_y-org_y);
174	174
175	175	/* Draw ship 2 */
176
	176
177	177	m_gfxdecode->gfx(10+((m_s2_sprite&0x04)>>2))->opaque(*m_ship2_vid,
178	178	clip,
179	179	(m_s2_sprite&0x03)^0x03,
r29404	r29405
215	215	if (m_p1_sprite & 0x08) /* if p1 is a projectile */
216	216	{
217	217	/* Draw score/projectile 1 */
218
	218
219	219	m_gfxdecode->gfx((m_p1_sprite&0x0c)>>2)->opaque(*m_proj1_vid,
220	220	clip,
221	221	(m_p1_sprite&0x03)^0x03,
r29404	r29405
227	227	if (m_p2_sprite & 0x08) /* if p2 is a projectile */
228	228	{
229	229	/* Draw score/projectile 2 */
230
	230
231	231	m_gfxdecode->gfx(4+((m_p2_sprite&0x0c)>>2))->opaque(*m_proj2_vid,
232	232	clip,
233	233	(m_p2_sprite&0x03)^0x03,
r29404	r29405
269	269	org_y = m_s1_y;
270	270
271	271	/* Draw ship 1 */
272
	272
273	273	m_gfxdecode->gfx(8+((m_s1_sprite&0x04)>>2))->opaque(*m_ship1_vid,
274	274	clip,
275	275	(m_s1_sprite&0x03)^0x03,
r29404	r29405
280	280	if (m_p1_sprite & 0x08) /* if p1 is a projectile */
281	281	{
282	282	/* Draw projectile 1 */
283
	283
284	284	m_gfxdecode->gfx((m_p1_sprite&0x0c)>>2)->opaque(*m_proj1_vid,
285	285	clip,
286	286	(m_p1_sprite&0x03)^0x03,
r29404	r29405
292	292	if (m_p2_sprite & 0x08) /* if p2 is a projectile */
293	293	{
294	294	/* Draw projectile 2 */
295
	295
296	296	m_gfxdecode->gfx(4+((m_p2_sprite&0x0c)>>2))->opaque(*m_proj2_vid,
297	297	clip,
298	298	(m_p2_sprite&0x03)^0x03,
r29404	r29405
340	340	org_y = m_s2_y;
341	341
342	342	/* Draw ship 2 */
343
	343
344	344	m_gfxdecode->gfx(10+((m_s2_sprite&0x04)>>2))->opaque(*m_ship2_vid,
345	345	clip,
346	346	(m_s2_sprite&0x03)^0x03,
r29404	r29405
351	351	if (m_p1_sprite & 0x08) /* if p1 is a projectile */
352	352	{
353	353	/* Draw projectile 1 */
354
	354
355	355	m_gfxdecode->gfx((m_p1_sprite&0x0c)>>2)->opaque(*m_proj1_vid,
356	356	clip,
357	357	(m_p1_sprite&0x03)^0x03,
r29404	r29405
363	363	if (m_p2_sprite & 0x08) /* if p2 is a projectile */
364	364	{
365	365	/* Draw projectile 2 */
366
	366
367	367	m_gfxdecode->gfx(4+((m_p2_sprite&0x0c)>>2))->opaque(*m_proj2_vid,
368	368	clip,
369	369	(m_p2_sprite&0x03)^0x03,
r29404	r29405
393	393	bitmap.fill(0, cliprect);
394	394
395	395	/* Draw ship 1 */
396
	396
397	397	m_gfxdecode->gfx(8+((m_s1_sprite&0x04)>>2))->transpen(bitmap,
398	398	cliprect,
399	399	(m_s1_sprite&0x03)^0x03,
r29404	r29405
403	403	0);
404	404
405	405	/* Draw ship 2 */
406
	406
407	407	m_gfxdecode->gfx(10+((m_s2_sprite&0x04)>>2))->transpen(bitmap,
408	408	cliprect,
409	409	(m_s2_sprite&0x03)^0x03,
r29404	r29405
413	413	0);
414	414
415	415	/* Draw score/projectile 1 */
416
	416
417	417	m_gfxdecode->gfx((m_p1_sprite&0x0c)>>2)->transpen(bitmap,
418	418	cliprect,
419	419	(m_p1_sprite&0x03)^0x03,
r29404	r29405
423	423	0);
424	424
425	425	/* Draw score/projectile 2 */
426
	426
427	427	m_gfxdecode->gfx(4+((m_p2_sprite&0x0c)>>2))->transpen(bitmap,
428	428	cliprect,
429	429	(m_p2_sprite&0x03)^0x03,

trunk/src/mame/video/nova2001.c
r29404	r29405
283	283	flipy = !flipy;
284	284	}
285	285
286		gfx->transpen(bitmap,cliprect,
	286	gfx->transpen(bitmap,cliprect,
287	287	tile,
288	288	color,
289	289	flipx, flipy,
r29404	r29405
320	320	flipy = !flipy;
321	321	}
322	322
323		gfx->transpen(bitmap,cliprect,
	323	gfx->transpen(bitmap,cliprect,
324	324	tile,
325	325	color,
326	326	flipx, flipy,
327	327	sx, sy, 0);
328	328
329	329	// there's no X MSB, so draw with wraparound (fixes title screen)
330		gfx->transpen(bitmap,cliprect,
	330	gfx->transpen(bitmap,cliprect,
331	331	tile,
332	332	color,
333	333	flipx, flipy,

trunk/src/mame/video/galaxian.c
r29404	r29405
577	577	}
578	578
579	579	/* draw */
580
	580
581	581	m_gfxdecode->gfx(1)->transpen(bitmap,clip,
582	582	code, color,
583	583	flipx, flipy,

trunk/src/mame/video/firetrk.c
r29404	r29405
262	262	y = 104;
263	263	}
264	264
265		m_gfxdecode->gfx(gfx_bank)->transpen(bitmap,cliprect, code, color, flip_x, flip_y, x, y, 0);
	265	m_gfxdecode->gfx(gfx_bank)->transpen(bitmap,cliprect, code, color, flip_x, flip_y, x, y, 0);
266	266	}
267	267
268	268
r29404	r29405
274	274	int flip_x = *m_car_rot & 0x04;
275	275	int flip_y = *m_car_rot & 0x08;
276	276
277		m_gfxdecode->gfx(gfx_bank)->transpen(bitmap,cliprect, code, color, flip_x, flip_y, 144, 104, 0);
	277	m_gfxdecode->gfx(gfx_bank)->transpen(bitmap,cliprect, code, color, flip_x, flip_y, 144, 104, 0);
278	278	}
279	279
280	280
r29404	r29405
303	303	y = 104;
304	304	}
305	305
306		m_gfxdecode->gfx(gfx_bank)->transpen(bitmap,cliprect, code, color, flip_x, flip_y, x, y, 0);
	306	m_gfxdecode->gfx(gfx_bank)->transpen(bitmap,cliprect, code, color, flip_x, flip_y, x, y, 0);
307	307	}
308	308
309	309
r29404	r29405
313	313	int i;
314	314
315	315	for (i = 0; i < count; i++)
316		m_gfxdecode->gfx(0)->opaque(bitmap,cliprect, alpha_ram[i], 0, 0, 0, x, i * height);
	316	m_gfxdecode->gfx(0)->opaque(bitmap,cliprect, alpha_ram[i], 0, 0, 0, x, i * height);
317	317	}
318	318
319	319

trunk/src/mame/video/strnskil.c
r29404	r29405
107	107	if (sx > 248)
108	108	sx = sx - 256;
109	109
110
	110
111	111	m_gfxdecode->gfx(1)->transmask(bitmap,cliprect,
112	112	code, color,
113	113	flipx, flipy,

trunk/src/mame/video/k053244_k053245.h
r29404	r29405
70	70
71	71	required_device<gfxdecode_device> m_gfxdecode;
72	72	required_device<palette_device> m_palette;
73
	73
74	74	DECLARE_READ16_MEMBER( k053244_reg_word_r ); // OBJSET0 debug handler
75	75	};
76	76

trunk/src/mame/video/ppu2c0x.c
r29404	r29405
930	930	}
931	931
932	932	m_draw_phase = PPU_DRAW_OAM;
933
	933
934	934	/* if sprites are on, draw them, but we call always to process them */
935	935	draw_sprites(line_priority);
936	936
937	937	m_draw_phase = PPU_DRAW_BG;
938
	938
939	939	/* done updating, whew */
940	940	g_profiler.stop();
941	941	}

trunk/src/mame/video/segaic24.h
r29404	r29405
14	14
15	15	#define MCFG_S24TILE_DEVICE_GFXDECODE(_gfxtag) \
16	16	segas24_tile::static_set_gfxdecode_tag(*device, "^" _gfxtag);
17
	17
18	18	#define MCFG_S24TILE_DEVICE_PALETTE(_palette_tag) \
19	19	segas24_tile::static_set_palette_tag(*device, "^" _palette_tag);
20
	20
21	21	class segas24_tile : public device_t
22	22	{
23	23	friend class segas24_tile_config;

trunk/src/mame/video/ppu2c0x.h
r29404	r29405
180	180	int is_sprite_8x16() { return m_regs[PPU_CONTROL0] & PPU_CONTROL0_SPRITE_SIZE; };
181	181	int get_draw_phase() { return m_draw_phase; };
182	182	int get_tilenum() { return m_tilecount; };
183
	183
184	184	//27/12/2002 (HACK!)
185	185	void set_latch( ppu2c0x_latch_delegate cb ) { m_latch = cb; m_latch.bind_relative_to(*owner()); };
186	186
r29404	r29405
213	213	int m_scan_scale; /* scan scale */
214	214	int m_scanlines_per_frame; /* number of scanlines per frame */
215	215	int m_security_value; /* 2C05 protection */
216		int m_tilecount; /* MMC5 can change attributes to subsets of the 34 visibile tiles */
217		int m_draw_phase; /* MMC5 uses different regs for BG and OAM */
	216	int m_tilecount; /* MMC5 can change attributes to subsets of the 34 visibile tiles */
	217	int m_draw_phase; /* MMC5 uses different regs for BG and OAM */
218	218	ppu2c0x_latch_delegate m_latch;
219	219
220	220	// timers
r29404	r29405
223	223	emu_timer m_scanline_timer; / scanline timer */
224	224
225	225	const char *m_cpu_tag;
226
	226
227	227	private:
228	228	static const device_timer_id TIMER_HBLANK = 0;
229	229	static const device_timer_id TIMER_NMI = 1;
r29404	r29405
231	231
232	232	inline UINT8 readbyte(offs_t address);
233	233	inline void writebyte(offs_t address, UINT8 data);
234
	234
235	235	};
236	236
237	237	class ppu2c02_device : public ppu2c0x_device {

trunk/src/mame/video/mrflea.c
r29404	r29405
88	88	{
89	89	int tile_number = base + source[0] + source[0x400] * 0x100;
90	90	source++;
91
	91
92	92	gfx->opaque(bitmap,cliprect,
93	93	tile_number,
94	94	0, /* color */

trunk/src/mame/video/hyperspt.c
r29404	r29405
148	148
149	149	sy += 1;
150	150
151
	151
152	152	m_gfxdecode->gfx(0)->transmask(bitmap,cliprect,
153	153	code, color,
154	154	flipx, flipy,
r29404	r29405
157	157
158	158	/* redraw with wraparound */
159	159
160
	160
161	161	m_gfxdecode->gfx(0)->transmask(bitmap,cliprect,
162	162	code, color,
163	163	flipx, flipy,

trunk/src/mame/video/solomon.c
r29404	r29405
86	86	flipy = !flipy;
87	87	}
88	88
89
	89
90	90	m_gfxdecode->gfx(2)->transpen(bitmap,cliprect,
91	91	code, color,
92	92	flipx, flipy,

trunk/src/mame/video/goindol.c
r29404	r29405
99	99	tile += tile;
100	100	palette = sprite_ram[offs + 2] >> 3;
101	101
102
	102
103	103	m_gfxdecode->gfx(gfxbank)->transpen(bitmap,cliprect,
104	104	tile,
105	105	palette,
106	106	flip_screen(),flip_screen(),
107	107	sx,sy, 0);
108
	108
109	109	m_gfxdecode->gfx(gfxbank)->transpen(bitmap,cliprect,
110	110	tile+1,
111	111	palette,

trunk/src/mame/video/m10.c
r29404	r29405
130	130
131	131	for (i = 0; i < 4; i++)
132	132	if (m_flip)
133		m_back_gfx->opaque(bitmap,cliprect, i, color[i], 1, 1, 31 * 8 - xpos[i], 0);
	133	m_back_gfx->opaque(bitmap,cliprect, i, color[i], 1, 1, 31 * 8 - xpos[i], 0);
134	134	else
135		m_back_gfx->opaque(bitmap,cliprect, i, color[i], 0, 0, xpos[i], 0);
	135	m_back_gfx->opaque(bitmap,cliprect, i, color[i], 0, 0, xpos[i], 0);
136	136
137	137	if (m_bottomline)
138	138	{

trunk/src/mame/video/bwing.c
r29404	r29405
261	261
262	262	// single/double
263	263	if (!(attrib & 0x10))
264		gfx->transpen(bmp,clip, code, color, fx, fy, x, y, 0);
	264	gfx->transpen(bmp,clip, code, color, fx, fy, x, y, 0);
265	265	else
266		gfx->zoom_transpen(bmp,clip, code, color, fx, fy, x, y, 1<<16, 2<<16, 0);
	266	gfx->zoom_transpen(bmp,clip, code, color, fx, fy, x, y, 1<<16, 2<<16, 0);
267	267	}
268	268	}
269	269

trunk/src/mame/video/segaic16.h
r29404	r29405
98	98
99	99	// static configuration
100	100	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
101
	101
102	102	UINT8 segaic16_display_enable;
103	103	UINT16 *segaic16_tileram_0;
104	104	UINT16 *segaic16_textram_0;

trunk/src/mame/video/fcombat.c
r29404	r29405
174	174	else
175	175	code &= ~0x10, code2 \|= 0x10;
176	176
177		gfx->transpen(bitmap,cliprect, code2, color, xflip, yflip, x, y + gfx->height(), 0);
	177	gfx->transpen(bitmap,cliprect, code2, color, xflip, yflip, x, y + gfx->height(), 0);
178	178	}
179	179
180	180	if(flags&0x10)
181	181	{
182		gfx->transpen(bitmap,cliprect, code2 + 16, color, xflip, yflip, x, y + gfx->height(), 0);
183		gfx->transpen(bitmap,cliprect, code2 + 16 * 2, color, xflip, yflip, x, y + 2 * gfx->height(), 0);
184		gfx->transpen(bitmap,cliprect, code2 + 16 * 3, color, xflip, yflip, x, y + 3 * gfx->height(), 0);
	182	gfx->transpen(bitmap,cliprect, code2 + 16, color, xflip, yflip, x, y + gfx->height(), 0);
	183	gfx->transpen(bitmap,cliprect, code2 + 16 * 2, color, xflip, yflip, x, y + 2 * gfx->height(), 0);
	184	gfx->transpen(bitmap,cliprect, code2 + 16 * 3, color, xflip, yflip, x, y + 3 * gfx->height(), 0);
185	185
186	186	}
187	187
188		gfx->transpen(bitmap,cliprect, code, color, xflip, yflip, x, y, 0);
	188	gfx->transpen(bitmap,cliprect, code, color, xflip, yflip, x, y, 0);
189	189
190	190	if (doubled) i += 4;
191	191	}

trunk/src/mame/video/sbasketb.c
r29404	r29405
154	154	flipy = !flipy;
155	155	}
156	156
157
	157
158	158	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
159	159	code, color,
160	160	flipx, flipy,

trunk/src/mame/video/gaelco2.c
r29404	r29405
377	377
378	378	/* normal sprite, pen 0 transparent */
379	379	if (color_effect == 0){
380		gfx->transpen(bitmap,cliprect, number,
	380	gfx->transpen(bitmap,cliprect, number,
381	381	color, xflip, yflip,
382	382	((sx + ex*16) & 0x3ff) + spr_x_adjust,
383	383	((sy + ey*16) & 0x1ff), 0);

trunk/src/mame/video/ssozumo.c
r29404	r29405
160	160	flipy = !flipy;
161	161	}
162	162
163
	163
164	164	m_gfxdecode->gfx(2)->transpen(bitmap,cliprect,
165	165	code, color,
166	166	flipx, flipy,

trunk/src/mame/video/wecleman.c
r29404	r29405
74	74
75	75	void wecleman_state::get_sprite_info()
76	76	{
77
78	77	const pen_t *base_pal = m_palette->pens();
79	78	UINT8 *base_gfx = memregion("gfx1")->base();
80	79	int gfx_max = memregion("gfx1")->bytes();

trunk/src/mame/video/tc0080vco.h
r29404	r29405
84	84	#define MCFG_TC0080VCO_ADD(_tag, _interface) \
85	85	MCFG_DEVICE_ADD(_tag, TC0080VCO, 0) \
86	86	MCFG_DEVICE_CONFIG(_interface)
87
	87
88	88	#define MCFG_TC0080VCO_GFXDECODE(_gfxtag) \
89	89	tc0080vco_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
90	90

trunk/src/mame/video/lastduel.c
r29404	r29405
232	232	flipy = !flipy;
233	233	}
234	234
235
	235
236	236	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect,
237	237	code,
238	238	color,

trunk/src/mame/video/alpha68k.c
r29404	r29405
345	345	fy = data & 0x4000;
346	346	color = color_prom[tile << 1 \| data >> 15];
347	347
348		gfx->transpen(bitmap,cliprect, tile, color, 0, fy, mx, my, 0);
	348	gfx->transpen(bitmap,cliprect, tile, color, 0, fy, mx, my, 0);
349	349
350	350	my = (my + 8) & 0xff;
351	351	}

trunk/src/mame/video/k054338.c
r29404	r29405
309	309	}
310	310
311	311	void k054338_device::update_all_shadows( int rushingheroes_hack, palette_device *palette )
312		{
	312	{
313	313	int i, d;
314	314	int noclip = m_regs[K338_REG_CONTROL] & K338_CTL_CLIPSL;
315	315

trunk/src/mame/video/namcos22.c
r29404	r29405
1623	1623
1624	1624	int base = m_spriteram[0] & 0xffff; // alpinesa/alpinr2b
1625	1625	int num_sprites = ((m_spriteram[1] >> 16) - base) + 1;
1626
	1626
1627	1627	// airco22b doesn't use spriteset #1
1628	1628	if (m_gametype == NAMCOS22_AIR_COMBAT22)
1629	1629	num_sprites = 0;

trunk/src/mame/video/exerion.c
r29404	r29405
385	385	else
386	386	code &= ~0x10, code2 \|= 0x10;
387	387
388		gfx->transmask(bitmap,cliprect, code2, color, xflip, yflip, x, y + gfx->height(),
	388	gfx->transmask(bitmap,cliprect, code2, color, xflip, yflip, x, y + gfx->height(),
389	389	m_palette->transpen_mask(*gfx, color, 0x10));
390	390	}
391	391
392		gfx->transmask(bitmap,cliprect, code, color, xflip, yflip, x, y,
	392	gfx->transmask(bitmap,cliprect, code, color, xflip, yflip, x, y,
393	393	m_palette->transpen_mask(*gfx, color, 0x10));
394	394
395	395	if (doubled) i += 4;

trunk/src/mame/video/yiear.c
r29404	r29405
129	129	sy++; /* fix title screen & garbage at the bottom of the screen */
130	130	}
131	131
132
	132
133	133	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
134	134	code, color,
135	135	flipx, flipy,

trunk/src/mame/video/taitoair.c
r29404	r29405
163	163	flipy ^= 0x0080;
164	164	}
165	165
166
	166
167	167	m_gfxdecode->gfx(0)->zoom_transpen(bitmap,cliprect,
168	168	tile,
169	169	color,

trunk/src/mame/video/angelkds.c
r29404	r29405
161	161
162	162	if (enable & enable_n)
163	163	{
164
165	164	gfx->transpen(
166	165	bitmap,
167	166	cliprect,
r29404	r29405
172	171	);
173	172	/* wraparound */
174	173	if (xpos > 240)
175
	174
176	175	gfx->transpen(
177	176	bitmap,
178	177	cliprect,
r29404	r29405
184	183	/* wraparound */
185	184	if (ypos > 240)
186	185	{
187
188	186	gfx->transpen(
189	187	bitmap,
190	188	cliprect,
r29404	r29405
195	193	);
196	194	/* wraparound */
197	195	if (xpos > 240)
198
	196
199	197	gfx->transpen(
200	198	bitmap,
201	199	cliprect,

trunk/src/mame/video/tunhunt.c
r29404	r29405
333	333	{
334	334	for( sy=0; sy<256; sy+=16 )
335	335	{
336
337	336	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
338	337	picture_code,
339	338	0, /* color */
r29404	r29405
358	357	vstop = 0x00
359	358
360	359	*/
361
	360
362	361	m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
363	362	picture_code,
364	363	0, /* color */

trunk/src/mame/video/k007420.c
r29404	r29405
33	33	void k007420_device::device_start()
34	34	{
35	35	// bind the init function
36		m_callback.bind_relative_to(*owner());
37
	36	m_callback.bind_relative_to(*owner());
	37
38	38	m_ram = auto_alloc_array_clear(machine(), UINT8, 0x200);
39	39
40	40	save_pointer(NAME(m_ram), 0x200);

trunk/src/mame/video/k007420.h
r29404	r29405
11	11	~k007420_device() {}
12	12
13	13	static void static_set_palette_tag(device_t &device, const char *tag);
14		static void static_set_bank_limit(device_t &device, int limit) { downcast<k007420_device &>(device).m_banklimit = limit; }
	14	static void static_set_bank_limit(device_t &device, int limit) { downcast<k007420_device &>(device).m_banklimit = limit; }
15	15	static void static_set_callback(device_t &device, k007420_delegate callback) { downcast<k007420_device &>(device).m_callback = callback; }
16	16
17	17	DECLARE_READ8_MEMBER( read );
r29404	r29405
48	48	k007420_device::static_set_callback(device, k007420_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
49	49
50	50	// function definition for a callback
51		#define K007420_CALLBACK_MEMBER(_name) void _name(int code, int color)
	51	#define K007420_CALLBACK_MEMBER(_name) void _name(int code, int color)
52	52
53	53
54	54	#endif

trunk/src/mame/video/ninjakd2.c
r29404	r29405
384	384	{
385	385	int const tile = code ^ (x << big_xshift) ^ (y << big_yshift);
386	386
387		gfx->transpen(bitmap,bitmap.cliprect(),
	387	gfx->transpen(bitmap,bitmap.cliprect(),
388	388	tile,
389	389	color,
390	390	flipx,flipy,

trunk/src/mame/video/raiden.c
r29404	r29405
133	133	flipx = !flipx;
134	134	}
135	135
136		gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 15);
	136	gfx->transpen(bitmap,cliprect, code, color, flipx, flipy, x, y, 15);
137	137	}
138	138	}
139	139

trunk/src/mame/video/jalblend.c
r29404	r29405
110	110	x_index_base = flipx ? gfx->width()-1 : 0;
111	111	y_index = flipy ? gfx->height()-1 : 0;
112	112
113		// start coordinates
	113	// start coordinates
114	114	sx = offsx;
115	115	sy = offsy;
116	116

trunk/src/mame/video/bfm_adr2.c
r29404	r29405
228	228	m_palette->set_pen_color(12,rgb_t(0x80,0x00,0x00));
229	229	m_palette->set_pen_color(13,rgb_t(0x80,0x00,0x80));
230	230	m_palette->set_pen_color(14,rgb_t(0x80,0x80,0x00));
231		m_palette->set_pen_color(15,rgb_t(0x80,0x80,0x80));
	231	m_palette->set_pen_color(15,rgb_t(0x80,0x80,0x80));
232	232	}
233	233
234	234	// video update ///////////////////////////////////////////////////////////

trunk/src/mame/video/bfm_adr2.h
r29404	r29405
8	8	bfm_adder2_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
9	9
10	10	static void static_set_palette_tag(device_t &device, const char *tag);
11
	11
12	12	TILE_GET_INFO_MEMBER( get_tile0_info );
13	13	TILE_GET_INFO_MEMBER( get_tile1_info );
14	14	UINT32 update_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

trunk/src/mame/video/taito_o.c
r29404	r29405
118	118	flipy ^= 0x0080;
119	119	}
120	120
121
	121
122	122	m_gfxdecode->gfx(0)->zoom_transpen(bitmap,cliprect,
123	123	tile,
124	124	color,

trunk/src/mame/video/cheekyms.c
r29404	r29405
123	123	if (!flip)
124	124	code++;
125	125
126		gfx->transpen(bitmap,cliprect, code, color, 0, 0, x, y, 0);
	126	gfx->transpen(bitmap,cliprect, code, color, 0, 0, x, y, 0);
127	127	}
128	128	else
129	129	{
130	130	if (m_spriteram[offs + 0] & 0x02)
131	131	{
132		gfx->transpen(bitmap,cliprect, code \| 0x20, color, 0, 0, x, y, 0);
133		gfx->transpen(bitmap,cliprect, code \| 0x21, color, 0, 0, 0x10 + x, y, 0);
	132	gfx->transpen(bitmap,cliprect, code \| 0x20, color, 0, 0, x, y, 0);
	133	gfx->transpen(bitmap,cliprect, code \| 0x21, color, 0, 0, 0x10 + x, y, 0);
134	134	}
135	135	else
136	136	{
137		gfx->transpen(bitmap,cliprect, code \| 0x20, color, 0, 0, x, y, 0);
138		gfx->transpen(bitmap,cliprect, code \| 0x21, color, 0, 0, x, 0x10 + y, 0);
	137	gfx->transpen(bitmap,cliprect, code \| 0x20, color, 0, 0, x, y, 0);
	138	gfx->transpen(bitmap,cliprect, code \| 0x21, color, 0, 0, x, 0x10 + y, 0);
139	139	}
140	140	}
141	141	}

trunk/src/mame/video/argus.c
r29404	r29405
1002	1002	flipx = !flipx;
1003	1003	flipy = !flipy;
1004	1004	}
1005
	1005
1006	1006	fx = flipx;
1007	1007	fy = flipy;
1008	1008

trunk/src/mame/video/carpolo.c
r29404	r29405
205	205
206	206	x = 240 - x;
207	207	y = 240 - y;
208
	208
209	209	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect,
210	210	remapped_code, col,
211	211	0, flipy,

trunk/src/mame/video/deco16ic.h
r29404	r29405
39	39	public:
40	40	deco16ic_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
41	41	~deco16ic_device() {}
42
	42
43	43	// static configuration
44	44	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
45	45	static void static_set_palette_tag(device_t &device, const char *tag);
46
47	46
	47
48	48	DECLARE_WRITE16_MEMBER( pf1_data_w );
49	49	DECLARE_WRITE16_MEMBER( pf2_data_w );
50	50

trunk/src/tools/unidasm.c
r29404	r29405
231	231	{ "f8", _8bit, 0, CPU_DISASSEMBLE_NAME(f8) },
232	232	{ "g65816", _8bit, 0, CPU_DISASSEMBLE_NAME(g65816_generic) },
233	233	{ "h6280", _8bit, 0, CPU_DISASSEMBLE_NAME(h6280) },
234		// { "h8", _16be, 0, CPU_DISASSEMBLE_NAME(h8) },
235		// { "h8_24", _16be, 0, CPU_DISASSEMBLE_NAME(h8_24) },
236		// { "h8_32", _16be, 0, CPU_DISASSEMBLE_NAME(h8_32) },
	234	// { "h8", _16be, 0, CPU_DISASSEMBLE_NAME(h8) },
	235	// { "h8_24", _16be, 0, CPU_DISASSEMBLE_NAME(h8_24) },
	236	// { "h8_32", _16be, 0, CPU_DISASSEMBLE_NAME(h8_32) },
237	237	{ "hc11", _8bit, 0, CPU_DISASSEMBLE_NAME(mb88) },
238	238	{ "hcd62121", _16be, 0, CPU_DISASSEMBLE_NAME(hcd62121) },
239	239	{ "hd61700", _8bit, 0, CPU_DISASSEMBLE_NAME(hd61700) },

trunk/src/tools/nltool.c
r29404	r29405
59	59
60	60	void CLIB_DECL logerror(const char *format, ...)
61	61	{
62		va_list arg;
63		va_start(arg, format);
64		vprintf(format, arg);
65		va_end(arg);
	62	va_list arg;
	63	va_start(arg, format);
	64	vprintf(format, arg);
	65	va_end(arg);
66	66	}
67	67
68	68	struct options_entry oplist[] =
69	69	{
70	70	{ "time_to_run;t", "1.0", OPTION_FLOAT, "time to run the emulation (seconds)" },
71		{ "logs;l", "", OPTION_STRING, "colon separated list of terminals to log" },
	71	{ "logs;l", "", OPTION_STRING, "colon separated list of terminals to log" },
72	72	{ "f", "-", OPTION_STRING, "file to process (default is stdin)" },
73	73	{ "listdevices;ld", "", OPTION_BOOLEAN, "list all devices available for use" },
74	74	{ "help;h", "0", OPTION_BOOLEAN, "display help" },
r29404	r29405
123	123
124	124	void init()
125	125	{
126		m_setup = new netlist_setup_t(*this);
127		this->init_object(*this, "netlist");
128		m_setup->init();
	126	m_setup = new netlist_setup_t(*this);
	127	this->init_object(*this, "netlist");
	128	m_setup->init();
129	129	}
130	130
131		void read_netlist(const char *buffer)
132		{
133
	131	void read_netlist(const char *buffer)
	132	{
134	133	// read the netlist ...
135	134
136		netlist_sources_t sources;
	135	netlist_sources_t sources;
137	136
138		sources.add(netlist_source_t(buffer));
139		sources.parse(*m_setup,"");
	137	sources.add(netlist_source_t(buffer));
	138	sources.parse(*m_setup,"");
140	139	//m_setup->parse(buffer);
141	140	log_setup();
142	141
r29404	r29405
147	146	this->reset();
148	147	}
149	148
150		void log_setup()
151		{
152		NL_VERBOSE_OUT(("Creating dynamic logs ...\n"));
153		nl_util::pstring_list ll = nl_util::split(m_logs, ":");
154		for (int i=0; i < ll.count(); i++)
155		{
156		netlist_device_t nc = m_setup->factory().new_device_by_classname("nld_log", m_setup);
157		pstring name = "log_" + ll[i];
158		m_setup->register_dev(nc, name);
159		m_setup->register_link(name + ".I", ll[i]);
160		}
161		}
	149	void log_setup()
	150	{
	151	NL_VERBOSE_OUT(("Creating dynamic logs ...\n"));
	152	nl_util::pstring_list ll = nl_util::split(m_logs, ":");
	153	for (int i=0; i < ll.count(); i++)
	154	{
	155	netlist_device_t nc = m_setup->factory().new_device_by_classname("nld_log", m_setup);
	156	pstring name = "log_" + ll[i];
	157	m_setup->register_dev(nc, name);
	158	m_setup->register_link(name + ".I", ll[i]);
	159	}
	160	}
162	161
163		pstring m_logs;
	162	pstring m_logs;
164	163	protected:
165	164
166	165	void verror(const loglevel_e level, const char *format, va_list ap) const
167	166	{
168		switch (level)
169		{
170		case NL_LOG:
171		case NL_WARNING:
172		vprintf(format, ap);
173		printf("\n");
174		break;
175		case NL_ERROR:
176		vprintf(format, ap);
177		printf("\n");
178		throw;
179		break;
180		}
	167	switch (level)
	168	{
	169	case NL_LOG:
	170	case NL_WARNING:
	171	vprintf(format, ap);
	172	printf("\n");
	173	break;
	174	case NL_ERROR:
	175	vprintf(format, ap);
	176	printf("\n");
	177	throw;
	178	break;
	179	}
181	180	}
182	181
183	182	private:
r29404	r29405
200	199
201	200	static void run(core_options &opts)
202	201	{
203		netlist_tool_t nt;
204		osd_ticks_t t = osd_ticks();
	202	netlist_tool_t nt;
	203	osd_ticks_t t = osd_ticks();
205	204
206		nt.init();
207		nt.m_logs = opts.value("l");
208		nt.read_netlist(filetobuf(opts.value("f")));
209		double ttr = opts.float_value("t");
	205	nt.init();
	206	nt.m_logs = opts.value("l");
	207	nt.read_netlist(filetobuf(opts.value("f")));
	208	double ttr = opts.float_value("t");
210	209
211		printf("startup time ==> %5.3f\n", (double) (osd_ticks() - t) / (double) osd_ticks_per_second() );
212		printf("runnning ...\n");
213		t = osd_ticks();
	210	printf("startup time ==> %5.3f\n", (double) (osd_ticks() - t) / (double) osd_ticks_per_second() );
	211	printf("runnning ...\n");
	212	t = osd_ticks();
214	213
215		nt.process_queue(netlist_time::from_double(ttr));
	214	nt.process_queue(netlist_time::from_double(ttr));
216	215
217		double emutime = (double) (osd_ticks() - t) / (double) osd_ticks_per_second();
218		printf("%f seconds emulation took %f real time ==> %5.2f%%\n", ttr, emutime, ttr/emutime*100.0);
	216	double emutime = (double) (osd_ticks() - t) / (double) osd_ticks_per_second();
	217	printf("%f seconds emulation took %f real time ==> %5.2f%%\n", ttr, emutime, ttr/emutime*100.0);
219	218	}
220	219
221	220	static void listdevices()
222	221	{
223		netlist_tool_t nt;
224		nt.init();
225		const netlist_factory_t::list_t &list = nt.setup().factory().list();
	222	netlist_tool_t nt;
	223	nt.init();
	224	const netlist_factory_t::list_t &list = nt.setup().factory().list();
226	225
227		nt.setup().start_devices();
228		nt.setup().resolve_inputs();
	226	nt.setup().start_devices();
	227	nt.setup().resolve_inputs();
229	228
230		for (int i=0; i < list.count(); i++)
231		{
232		pstring out = pstring::sprintf("%-20s %s(<id>", list[i]->classname().cstr(),
233		list[i]->name().cstr() );
234		pstring terms("");
	229	for (int i=0; i < list.count(); i++)
	230	{
	231	pstring out = pstring::sprintf("%-20s %s(<id>", list[i]->classname().cstr(),
	232	list[i]->name().cstr() );
	233	pstring terms("");
235	234
236		net_device_t_base_factory *f = list[i];
237		netlist_device_t *d = f->Create();
238		d->init(nt, pstring::sprintf("dummy%d", i));
239		d->start_dev();
	235	net_device_t_base_factory *f = list[i];
	236	netlist_device_t *d = f->Create();
	237	d->init(nt, pstring::sprintf("dummy%d", i));
	238	d->start_dev();
240	239
241		// get the list of terminals ...
242		for (int j=0; j < d->m_terminals.count(); j++)
243		{
244		pstring inp = d->m_terminals[j];
245		if (inp.startsWith(d->name() + "."))
246		inp = inp.substr(d->name().len() + 1);
247		terms += "," + inp;
248		}
	240	// get the list of terminals ...
	241	for (int j=0; j < d->m_terminals.count(); j++)
	242	{
	243	pstring inp = d->m_terminals[j];
	244	if (inp.startsWith(d->name() + "."))
	245	inp = inp.substr(d->name().len() + 1);
	246	terms += "," + inp;
	247	}
249	248
250		if (list[i]->param_desc().startsWith("+"))
251		{
252		out += "," + list[i]->param_desc().substr(1);
253		terms = "";
254		}
255		else if (list[i]->param_desc() == "-")
256		{
257		/* no params at all */
258		}
259		else
260		{
261		out += "," + list[i]->param_desc();
262		}
263		out += ")";
264		printf("%s\n", out.cstr());
265		if (terms != "")
266		printf("Terminals: %s\n", terms.substr(1).cstr());
267		}
	249	if (list[i]->param_desc().startsWith("+"))
	250	{
	251	out += "," + list[i]->param_desc().substr(1);
	252	terms = "";
	253	}
	254	else if (list[i]->param_desc() == "-")
	255	{
	256	/* no params at all */
	257	}
	258	else
	259	{
	260	out += "," + list[i]->param_desc();
	261	}
	262	out += ")";
	263	printf("%s\n", out.cstr());
	264	if (terms != "")
	265	printf("Terminals: %s\n", terms.substr(1).cstr());
	266	}
268	267	}
269	268
270	269	/*-------------------------------------------------
r29404	r29405
291	290	return 1;
292	291	}
293	292
294		if (opts.bool_value("ld"))
295		{
296		listdevices();
297		}
298		else
299		{
300		run(opts);
301		}
	293	if (opts.bool_value("ld"))
	294	{
	295	listdevices();
	296	}
	297	else
	298	{
	299	run(opts);
	300	}
302	301
303	302	return 0;
304	303	}

trunk/src/tools/srcclean.c
r29404	r29405
33	33
34	34	static int le_convert(char *buffer, int size)
35	35	{
36		char *pos;
37		char *end = buffer + size;
	36	char *pos;
	37	char *end = buffer + size;
38	38
39		/* brute force */
40		*end = 0;
41		pos = strchr(buffer, 0x0d);
42		while (pos != NULL)
43		{
44		memmove(pos, pos+1,end - pos + 1);
45		size--;
46		buffer = pos + 1;
47		pos = strchr(buffer, 0x0d);
48		}
49		return size;
	39	/* brute force */
	40	*end = 0;
	41	pos = strchr(buffer, 0x0d);
	42	while (pos != NULL)
	43	{
	44	memmove(pos, pos+1,end - pos + 1);
	45	size--;
	46	buffer = pos + 1;
	47	pos = strchr(buffer, 0x0d);
	48	}
	49	return size;
50	50	}
51	51
52	52	/***************************************************************************
r29404	r29405
55	55
56	56	int main(int argc, char *argv[])
57	57	{
58		bool unix_le = false;
	58	bool unix_le = false;
59	59	int removed_tabs = 0;
60	60	int added_tabs = 0;
61	61	int removed_spaces = 0;
62	62	int removed_continuations = 0;
63		int fixed_dos_style = 0;
	63	int fixed_dos_style = 0;
64	64	int fixed_mac_style = 0;
65	65	int fixed_nix_style = 0;
66	66	int added_newline = 0;
r29404	r29405
85	85	bool dry_run = false;
86	86
87	87	while (arg_found && argc > 1) {
88		if (strcmp(argv[1], "-u") == 0)
89		{
90		unix_le = true;
91		argc--;
92		argv++;
93		}
94		else if (strcmp(argv[1], "-d") == 0)
95		{
96		dry_run = true;
97		argc--;
98		argv++;
99		}
100		else
101		arg_found = false;
	88	if (strcmp(argv[1], "-u") == 0)
	89	{
	90	unix_le = true;
	91	argc--;
	92	argv++;
	93	}
	94	else if (strcmp(argv[1], "-d") == 0)
	95	{
	96	dry_run = true;
	97	argc--;
	98	argv++;
	99	}
	100	else
	101	arg_found = false;
102	102
103	103	}
104	104
105		/* print usage info */
106		if (argc < 2)
107		{
108		printf("Usage:\nsrcclean [-u] [-d] <file>\n");
109		return 0;
110		}
	105	/* print usage info */
	106	if (argc < 2)
	107	{
	108	printf("Usage:\nsrcclean [-u] [-d] <file>\n");
	109	return 0;
	110	}
111	111
112	112	/* read the file */
113	113	file = fopen(argv[1], "rb");
r29404	r29405
121	121
122	122	/* check whether we have dos line endings and are in unix mode */
123	123	if (unix_le && (strchr((char *) original, 0x0d) != NULL))
124		fixed_dos_style = 1;
	124	fixed_dos_style = 1;
125	125
126	126	/* determine if we are a C file */
127	127	ext = strrchr(argv[1], '.');
r29404	r29405
245	245	}
246	246
247	247	/* insert a proper CR/LF */
248		modified[dst++] = 0x0d;
	248	modified[dst++] = 0x0d;
249	249	modified[dst++] = 0x0a;
250	250	col = 0;
251	251
252	252	/* skip over any LF in the source file */
253	253	if (ch == 0x0d && original[src] == 0x0a)
254		src++;
	254	src++;
255	255	else if (ch == 0x0a)
256	256	fixed_nix_style = 1;
257	257	else
r29404	r29405
367	367	}
368	368	}
369	369
370		/* convert to unix_le if requested */
	370	/* convert to unix_le if requested */
371	371
372		if (unix_le)
373		dst = le_convert((char *) modified, dst);
	372	if (unix_le)
	373	dst = le_convert((char *) modified, dst);
374	374
375	375	/* if the result == original, skip it */
376	376	if (dst != bytes \|\| memcmp(original, modified, bytes))
r29404	r29405
386	386	if (hichars) printf(" fixed %d high-ASCII char(s)", hichars);
387	387	if (fixed_nix_style && !unix_le) printf(" fixed *nix-style line-ends");
388	388	if (fixed_mac_style) printf(" fixed Mac-style line-ends");
389		if (fixed_dos_style) printf(" fixed Dos-style line-ends");
	389	if (fixed_dos_style) printf(" fixed Dos-style line-ends");
390	390	printf("\n");
391	391
392	392	if (!dry_run)
393	393	{
394		/* write the file */
395		file = fopen(argv[1], "wb");
396		fwrite(modified, 1, dst, file);
397		fclose(file);
	394	/* write the file */
	395	file = fopen(argv[1], "wb");
	396	fwrite(modified, 1, dst, file);
	397	fclose(file);
398	398	}
399	399	}
400	400

trunk/src/osd/osdcore.h
r29404	r29405
848	848
849	849	an allocated pointer to an osd_directory_entry representing
850	850	info on the path; even if the file does not exist.
851		free with osd_free()
	851	free with osd_free()
852	852
853	853	-----------------------------------------------------------------------------*/
854	854	osd_directory_entry osd_stat(const char path);

trunk/src/osd/osdcomm.h
r29404	r29405
113	113
114	114	/* pointer-sized values */
115	115	#ifdef PTR64
116		typedef UINT64 FPTR;
	116	typedef UINT64 FPTR;
117	117	#else
118		typedef UINT32 FPTR;
	118	typedef UINT32 FPTR;
119	119	#endif
120	120
121	121

trunk/src/osd/sdl/gl_shader_mgr.c
r29404	r29405
68	68	};
69	69
70	70	static GLhandleARB glsl_mamebm_vsh_shader[GLSL_VERTEX_SHADER_MAX_NUMBER+9] =
71		{
72		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	71	{
	72	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
73	73	}; /* general, custom0-9 */
74	74
75	75	static GLhandleARB glsl_mamebm_fsh_shader [GLSL_SHADER_FEAT_MAX_NUMBER+9] =
r29404	r29405
83	83	};
84	84
85	85	static GLhandleARB glsl_scrn_vsh_shader[10] =
86		{
87		0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	86	{
	87	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
88	88	}; /* custom0-9 */
89	89
90	90	static GLhandleARB glsl_scrn_fsh_shader [10] =
91		{
92		0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	91	{
	92	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
93	93	}; /* rgb32: custom0-9 */
94	94
95	95	const char * glsl_shader_get_filter_name_mamebm(int glslShaderFeature)

trunk/src/osd/sdl/drawogl.c
r29404	r29405
3091	3091	//FIXME: Handled in drawogl_window_draw as well
3092	3092	sdl->blittimer = 3;
3093	3093	}
3094

trunk/src/osd/sdl/blit13.h
r29404	r29405
54	54
55	55	#define OP_RGB32PAL_ARGB32(_src) \
56	56	(texsource->palette[0x200 + (((_src) >> 16) & 0xff) ] \| \
57		texsource->palette[0x100 + (((_src) >> 8) & 0xff) ] \| \
58		texsource->palette[((_src) & 0xff) ] \| 0xff000000)
	57	texsource->palette[0x100 + (((_src) >> 8) & 0xff) ] \| \
	58	texsource->palette[((_src) & 0xff) ] \| 0xff000000)
59	59
60	60	#define OP_PAL16_ARGB32(_src) (0xff000000 \| texsource->palette[_src])
61	61

trunk/src/osd/sdl/window.c
r29404	r29405
620	620	SDL_ShowCursor(SDL_ENABLE);
621	621	if (SDL_GetWindowGrab(window->sdl_window ))
622	622	SDL_SetWindowGrab(window->sdl_window, SDL_FALSE);
623		SDL_SetRelativeMouseMode(SDL_FALSE);
	623	SDL_SetRelativeMouseMode(SDL_FALSE);
624	624	}
625	625	else
626	626	{
627	627	SDL_ShowCursor(SDL_DISABLE);
628	628	if (!SDL_GetWindowGrab(window->sdl_window))
629	629	SDL_SetWindowGrab(window->sdl_window, SDL_TRUE);
630		SDL_SetRelativeMouseMode(SDL_TRUE);
	630	SDL_SetRelativeMouseMode(SDL_TRUE);
631	631	}
632	632	SDL_SetCursor(NULL); // Force an update in case the underlying driver has changed visibility
633	633	}

trunk/src/emu/rendlay.c
r29404	r29405
667	667	m_numsymbolsvisible = xml_get_attribute_int_with_subst(machine, compnode, "numsymbolsvisible", 3);
668	668	m_reelreversed = xml_get_attribute_int_with_subst(machine, compnode, "reelreversed", 0);
669	669	m_beltreel = xml_get_attribute_int_with_subst(machine, compnode, "beltreel", 0);
670
	670
671	671	}
672	672
673	673	// led7seg nodes
r29404	r29405
1004	1004	render_font *font = machine.render().font_alloc("default");
1005	1005	float aspect = 1.0f;
1006	1006	INT32 width;
1007
1008	1007
	1008
1009	1009	int curry = 0;
1010	1010	int num_shown = m_numsymbolsvisible;
1011	1011
r29404	r29405
1109	1109	int effx = curx + x + chbounds.min_x;
1110	1110	if (effx >= bounds.min_x && effx <= bounds.max_x)
1111	1111	{
1112		UINT32 spix = rgb_t(src[x]).a();
	1112	UINT32 spix = rgb_t(src[x]).a();
1113	1113	if (spix != 0)
1114	1114	{
1115	1115	rgb_t dpix = d[effx];
r29404	r29405
1259	1259	int effx = basex + curx + x;
1260	1260	if (effx >= bounds.min_x && effx <= bounds.max_x)
1261	1261	{
1262		UINT32 spix = rgb_t(src[x]).a();
	1262	UINT32 spix = rgb_t(src[x]).a();
1263	1263	if (spix != 0)
1264	1264	{
1265	1265	rgb_t dpix = d[effx];
r29404	r29405
2309	2309	//-------------------------------------------------
2310	2310
2311	2311
2312		render_container *layout_view::item::screen_container(running_machine &machine) const
2313		{
2314		return (m_screen != NULL) ? &m_screen->container() : NULL;
	2312	render_container *layout_view::item::screen_container(running_machine &machine) const
	2313	{
	2314	return (m_screen != NULL) ? &m_screen->container() : NULL;
2315	2315	}
2316	2316
2317	2317	//-------------------------------------------------

trunk/src/emu/diimage.c
r29404	r29405
891	891	m_software_info_ptr = &m_software_part_ptr->info();
892	892	m_software_list_name.cpy(m_software_info_ptr->list().list_name());
893	893	m_full_software_name.cpy(m_software_part_ptr->info().shortname());
894
	894
895	895	// if we had launched from softlist with a specified part, e.g. "shortname:part"
896	896	// we would have recorded the wrong name, so record it again based on software_info
897	897	if (m_software_info_ptr && m_full_software_name)
898	898	m_err = set_image_filename(m_full_software_name);
899	899
900		// check if image should be read-only
	900	// check if image should be read-only
901	901	const char *read_only = get_feature("read_only");
902	902	if (read_only && !strcmp(read_only, "true")) {
903	903	make_readonly();
r29404	r29405
1153	1153	}
1154	1154
1155	1155	//-------------------------------------------------
1156		// software_name_split - helper that splits a
1157		// software_list:software:part string into
1158		// separate software_list, software, and part
	1156	// software_name_split - helper that splits a
	1157	// software_list:software:part string into
	1158	// separate software_list, software, and part
1159	1159	// strings.
1160	1160	//
1161	1161	// str1:str2:str3 => swlist_name - str1, swname - str2, swpart - str3
r29404	r29405
1177	1177	swname.cpy(swlist_swname);
1178	1178	return;
1179	1179	}
1180
	1180
1181	1181	// if one colon, it is the swname and swpart alone
1182	1182	const char *split2 = strchr(split1 + 1, ':');
1183	1183	if (split2 == NULL)
r29404	r29405
1200	1200	// Note: old code would explicitly load swlist_name if it was specified, rather than
1201	1201	// searching the devices.
1202	1202	//
1203		// Also if not found, old code would attempt to open <drivername>.xml and even
	1203	// Also if not found, old code would attempt to open <drivername>.xml and even
1204	1204	// <swinfo_name>.xml. Hopefully removing this won't break anything.
1205	1205	//
1206	1206
r29404	r29405
1213	1213	const char *interface = NULL;
1214	1214	if (restrict_to_interface)
1215	1215	interface = image_interface();
1216
	1216
1217	1217	// find the software list if explicitly specified
1218	1218	software_list_device_iterator deviter(device().mconfig().root_device());
1219	1219	for (software_list_device *swlistdev = deviter.first(); swlistdev != NULL; swlistdev = deviter.next())
r29404	r29405
1227	1227	return part;
1228	1228	}
1229	1229	}
1230
	1230
1231	1231	// if explicitly specified and not found, just error here
1232	1232	return NULL;
1233	1233	}
r29404	r29405
1284	1284	{
1285	1285	const char *option = device().mconfig().options().value(req_image->brief_instance_name());
1286	1286	// mount only if not already mounted
1287		if (strlen(option) == 0 && !req_image->filename())
	1287	if (strlen(option) == 0 && !req_image->filename())
1288	1288	{
1289	1289	req_image->set_init_phase();
1290	1290	req_image->load(requirement);

trunk/src/emu/output.c
r29404	r29405
31	31	public:
32	32	output_notify(output_notifier_func callback, void *param)
33	33	: m_next(NULL),
34		m_notifier(callback),
35		m_param(param) { }
	34	m_notifier(callback),
	35	m_param(param) { }
36	36
37	37	output_notify *next() const { return m_next; }
38	38
39		output_notify * m_next; /* link to next item */
	39	output_notify * m_next; /* link to next item */
40	40	output_notifier_func m_notifier; /* callback to call */
41		void * m_param; /* parameter to pass the callback */
	41	void * m_param; /* parameter to pass the callback */
42	42	};
43	43
44	44

trunk/src/emu/rendlay.h
r29404	r29405
149	149	int m_stateoffset;
150	150	int m_reelreversed;
151	151	int m_numsymbolsvisible;
152		int m_beltreel;
	152	int m_beltreel;
153	153	};
154	154
155	155	// a texture encapsulates a texture for a given element in a given state

trunk/src/emu/diimage.h
r29404	r29405
74	74	public:
75	75	image_device_format(const char name, const char description, const char extensions, const char optspec)
76	76	: m_next(NULL),
77		m_name(name),
78		m_description(description),
79		m_extensions(extensions),
80		m_optspec(optspec) { }
	77	m_name(name),
	78	m_description(description),
	79	m_extensions(extensions),
	80	m_optspec(optspec) { }
81	81
82	82	image_device_format *next() const { return m_next; }
83	83	const char *name() const { return m_name; }

trunk/src/emu/emualloc.h
r29404	r29405
145	145	dynamic_array<resource_pool_item *> m_hash;
146	146	resource_pool_item * m_ordered_head;
147	147	resource_pool_item * m_ordered_tail;
148		static UINT64 s_id;
	148	static UINT64 s_id;
149	149	};
150	150
151	151

trunk/src/emu/sound/spu.c
r29404	r29405
138	138
139	139	output_buffer_size=65536/8/*,
140	140
141		sample_loop_cache_pool_size=64,
142		sample_loop_cache_extend_size=64,
143		sample_cache_pool_size=64,
144		sample_cache_extend_size=64,
	141	sample_loop_cache_pool_size=64,
	142	sample_loop_cache_extend_size=64,
	143	sample_cache_pool_size=64,
	144	sample_cache_extend_size=64,
145	145
146		stream_marker_pool_size=64,
147		stream_marker_extend_size=64*/;
	146	stream_marker_pool_size=64,
	147	stream_marker_extend_size=64*/;
148	148
149	149	//
150	150	//

trunk/src/emu/sound/votrax.h
r29404	r29405
38	38	votrax_sc01_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
39	39
40	40	template<class _Object> static devcb2_base &set_request_callback(device_t &device, _Object object) { return downcast<votrax_sc01_device &>(device).m_request_cb.set_callback(object); }
41
	41
42	42	// writers
43	43	DECLARE_WRITE8_MEMBER( write );
44	44	DECLARE_WRITE8_MEMBER( inflection_w );
r29404	r29405
73	73	UINT8 m_phoneme; // 6-bit phoneme value
74	74
75	75	// outputs
76		devcb2_write_line m_request_cb; // callback for request
	76	devcb2_write_line m_request_cb; // callback for request
77	77	UINT8 m_request_state; // request as seen to the outside world
78	78	UINT8 m_internal_request; // request managed by stream timing
79	79

trunk/src/emu/sound/tc8830f.c
r29404	r29405
111	111	m_delta -= 8;
112	112	if (m_delta <= 0)
113	113	m_delta = 1;
114
	114
115	115	// determine direction
116	116	if (bit)
117	117	m_output += m_delta;
118	118	else
119	119	m_output -= m_delta;
120
	120
121	121	if (m_output > 32767)
122	122	m_output = 32767;
123	123	else if (m_output < -32768)
124	124	m_output = -32768;
125
	125
126	126	m_prevbits = m_prevbits << 1 \| bit;
127	127	mix = m_output;
128	128	}
129
	129
130	130	outputs[0][i] = mix;
131	131	}
132	132	}

trunk/src/emu/sound/ay8910.c
r29404	r29405
422	422
423	423	INLINE void build_resisor_table(const ay_ym_param par, INT32 tab, int zero_is_off)
424	424	{
425		int j;
	425	int j;
426	426
427		for (j=0; j < par->res_count; j++)
428		{
429
430		if (zero_is_off && j == 0)
431		{
432		tab[j] = 1e6;
433		}
434		else
435		tab[j] = par->res[j];
436		}
	427	for (j=0; j < par->res_count; j++)
	428	{
	429	if (zero_is_off && j == 0)
	430	{
	431	tab[j] = 1e6;
	432	}
	433	else
	434	tab[j] = par->res[j];
	435	}
437	436	}
438	437
439	438
r29404	r29405
605	604	psg->count_noise++;
606	605	if (psg->count_noise >= NOISE_PERIOD(psg))
607	606	{
608		/* toggle the prescaler output. Noise is no different to
609		* channels.
610		*/
611		psg->count_noise = 0;
612		psg->prescale_noise ^= 1;
	607	/* toggle the prescaler output. Noise is no different to
	608	* channels.
	609	*/
	610	psg->count_noise = 0;
	611	psg->prescale_noise ^= 1;
613	612
614		if ( psg->prescale_noise)
615		{
616		/* The Random Number Generator of the 8910 is a 17-bit shift */
617		/* register. The input to the shift register is bit0 XOR bit3 */
618		/* (bit0 is the output). This was verified on AY-3-8910 and YM2149 chips. */
	613	if ( psg->prescale_noise)
	614	{
	615	/* The Random Number Generator of the 8910 is a 17-bit shift */
	616	/* register. The input to the shift register is bit0 XOR bit3 */
	617	/* (bit0 is the output). This was verified on AY-3-8910 and YM2149 chips. */
619	618
620		psg->rng ^= (((psg->rng & 1) ^ ((psg->rng >> 3) & 1)) << 17);
621		psg->rng >>= 1;
622		}
	619	psg->rng ^= (((psg->rng & 1) ^ ((psg->rng >> 3) & 1)) << 17);
	620	psg->rng >>= 1;
	621	}
623	622	}
624	623
625	624	for (chan = 0; chan < NUM_CHANNELS; chan++)
r29404	r29405
704	703	normalize = 1;
705	704	}
706	705
707		if ((psg->intf->flags & AY8910_RESISTOR_OUTPUT) != 0)
708		{
709		for (chan=0; chan < NUM_CHANNELS; chan++)
710		{
711		build_resisor_table(psg->par, psg->vol_table[chan], psg->zero_is_off);
712		build_resisor_table(psg->par_env, psg->env_table[chan], 0);
713		}
714		}
715		else
716		{
717		for (chan=0; chan < NUM_CHANNELS; chan++)
718		{
719		build_single_table(psg->intf->res_load[chan], psg->par, normalize, psg->vol_table[chan], psg->zero_is_off);
720		build_single_table(psg->intf->res_load[chan], psg->par_env, normalize, psg->env_table[chan], 0);
721		}
722		}
	706	if ((psg->intf->flags & AY8910_RESISTOR_OUTPUT) != 0)
	707	{
	708	for (chan=0; chan < NUM_CHANNELS; chan++)
	709	{
	710	build_resisor_table(psg->par, psg->vol_table[chan], psg->zero_is_off);
	711	build_resisor_table(psg->par_env, psg->env_table[chan], 0);
	712	}
	713	}
	714	else
	715	{
	716	for (chan=0; chan < NUM_CHANNELS; chan++)
	717	{
	718	build_single_table(psg->intf->res_load[chan], psg->par, normalize, psg->vol_table[chan], psg->zero_is_off);
	719	build_single_table(psg->intf->res_load[chan], psg->par_env, normalize, psg->env_table[chan], 0);
	720	}
	721	}
723	722	/*
724	723	* The previous implementation added all three channels up instead of averaging them.
725	724	* The factor of 3 will force the same levels if normalizing is used.

trunk/src/emu/sound/msm5205.h
r29404	r29405
35	35
36	36	#define MCFG_MSM6585_VCLK_CB(_devcb) \
37	37	devcb = &msm6585_device::set_vclk_callback(*device, DEVCB2_##_devcb);
38
39	38
	39
40	40	class msm5205_device : public device_t,
41	41	public device_sound_interface
42	42	{
r29404	r29405
44	44	msm5205_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
45	45	msm5205_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
46	46	~msm5205_device() {}
47
	47
48	48	static void set_prescaler_selector(device_t &device, int select) { downcast<msm5205_device &>(device).m_select = select; }
49	49	template<class _Object> static devcb2_base &set_vclk_callback(device_t &device, _Object object) { return downcast<msm5205_device &>(device).m_vclk_cb.set_callback(object); }
50	50

trunk/src/emu/sound/aica.c
r29404	r29405
1400	1400
1401	1401	// set up the IRQ callbacks
1402	1402	m_irq_cb.resolve_safe();
1403		m_main_irq_cb.resolve_safe();
	1403	m_main_irq_cb.resolve_safe();
1404	1404
1405	1405	m_stream = machine().sound().stream_alloc(*this, 0, 2, 44100);
1406
	1406
1407	1407	// save state
1408	1408	save_item(NAME(m_IrqTimA));
1409	1409	save_item(NAME(m_IrqTimBC));
r29404	r29405
1416	1416	save_item(NAME(m_LPANTABLE),0x20000);
1417	1417	save_item(NAME(m_RPANTABLE),0x20000);
1418	1418	save_item(NAME(m_TimPris),3);
1419		save_item(NAME(m_TimCnt),3);
	1419	save_item(NAME(m_TimCnt),3);
1420	1420	}
1421	1421
1422	1422	void aica_device::set_ram_base(void *base, int size)
r29404	r29405
1489	1489	m_bufferr(NULL),
1490	1490	m_length(0),
1491	1491	m_RBUFDST(NULL)
1492
	1492
1493	1493	{
1494		memset(&m_udata.data, 0, sizeof(m_udata.data));
1495		memset(m_EFSPAN, 0, sizeof(m_EFSPAN));
1496		memset(m_Slots, 0, sizeof(m_Slots));
1497		memset(m_RINGBUF, 0, sizeof(m_RINGBUF));
1498		memset(m_MidiStack, 0, sizeof(m_MidiStack));
	1494	memset(&m_udata.data, 0, sizeof(m_udata.data));
	1495	memset(m_EFSPAN, 0, sizeof(m_EFSPAN));
	1496	memset(m_Slots, 0, sizeof(m_Slots));
	1497	memset(m_RINGBUF, 0, sizeof(m_RINGBUF));
	1498	memset(m_MidiStack, 0, sizeof(m_MidiStack));
1499	1499
1500		memset(m_LPANTABLE, 0, sizeof(m_LPANTABLE));
1501		memset(m_RPANTABLE, 0, sizeof(m_RPANTABLE));
	1500	memset(m_LPANTABLE, 0, sizeof(m_LPANTABLE));
	1501	memset(m_RPANTABLE, 0, sizeof(m_RPANTABLE));
1502	1502
1503		memset(m_TimPris, 0, sizeof(m_TimPris));
1504		memset(m_TimCnt, 0, sizeof(m_TimCnt));
	1503	memset(m_TimPris, 0, sizeof(m_TimPris));
	1504	memset(m_TimCnt, 0, sizeof(m_TimCnt));
1505	1505
1506		memset(&m_dma, 0, sizeof(m_dma));
1507
1508		memset(m_ARTABLE, 0, sizeof(m_ARTABLE));
1509		memset(m_DRTABLE, 0, sizeof(m_DRTABLE));
	1506	memset(&m_dma, 0, sizeof(m_dma));
1510	1507
1511		memset(&m_DSP, 0, sizeof(m_DSP));
1512
1513		memset(m_EG_TABLE, 0, sizeof(m_EG_TABLE));
1514		memset(m_PLFO_TRI, 0, sizeof(m_PLFO_TRI));
1515		memset(m_PLFO_SQR, 0, sizeof(m_PLFO_SQR));
1516		memset(m_PLFO_SAW, 0, sizeof(m_PLFO_SAW));
1517		memset(m_PLFO_NOI, 0, sizeof(m_PLFO_NOI));
1518
1519		memset(m_ALFO_TRI, 0, sizeof(m_ALFO_TRI));
1520		memset(m_ALFO_SQR, 0, sizeof(m_ALFO_SQR));
1521		memset(m_ALFO_SAW, 0, sizeof(m_ALFO_SAW));
1522		memset(m_ALFO_NOI, 0, sizeof(m_ALFO_NOI));
1523
1524		memset(m_PSCALES, 0, sizeof(m_PSCALES));
1525		memset(m_ASCALES, 0, sizeof(m_ASCALES));
	1508	memset(m_ARTABLE, 0, sizeof(m_ARTABLE));
	1509	memset(m_DRTABLE, 0, sizeof(m_DRTABLE));
	1510
	1511	memset(&m_DSP, 0, sizeof(m_DSP));
	1512
	1513	memset(m_EG_TABLE, 0, sizeof(m_EG_TABLE));
	1514	memset(m_PLFO_TRI, 0, sizeof(m_PLFO_TRI));
	1515	memset(m_PLFO_SQR, 0, sizeof(m_PLFO_SQR));
	1516	memset(m_PLFO_SAW, 0, sizeof(m_PLFO_SAW));
	1517	memset(m_PLFO_NOI, 0, sizeof(m_PLFO_NOI));
	1518
	1519	memset(m_ALFO_TRI, 0, sizeof(m_ALFO_TRI));
	1520	memset(m_ALFO_SQR, 0, sizeof(m_ALFO_SQR));
	1521	memset(m_ALFO_SAW, 0, sizeof(m_ALFO_SAW));
	1522	memset(m_ALFO_NOI, 0, sizeof(m_ALFO_NOI));
	1523
	1524	memset(m_PSCALES, 0, sizeof(m_PSCALES));
	1525	memset(m_ASCALES, 0, sizeof(m_ASCALES));
1526	1526	}
1527	1527
1528	1528

trunk/src/emu/sound/aica.h
r29404	r29405
82	82	static void set_roffset(device_t &device, int roffset) { downcast<aica_device &>(device).m_roffset = roffset; }
83	83	template<class _Object> static devcb2_base &set_irq_callback(device_t &device, _Object object) { return downcast<aica_device &>(device).m_irq_cb.set_callback(object); }
84	84	template<class _Object> static devcb2_base &set_main_irq_callback(device_t &device, _Object object) { return downcast<aica_device &>(device).m_main_irq_cb.set_callback(object); }
85
	85
86	86	// AICA register access
87	87	DECLARE_READ16_MEMBER( read );
88	88	DECLARE_WRITE16_MEMBER( write );
r29404	r29405
90	90	// MIDI I/O access
91	91	DECLARE_WRITE16_MEMBER( midi_in );
92	92	DECLARE_READ16_MEMBER( midi_out_r );
93
	93
94	94	void set_ram_base(void *base, int size);
95	95
96	96	protected:
r29404	r29405
146	146	UINT16 data[0xc0/2];
147	147	UINT8 datab[0xc0];
148	148	} m_udata;
149
	149
150	150	UINT16 m_IRQL, m_IRQR;
151	151	UINT16 m_EFSPAN[0x48];
152	152	AICA_SLOT m_Slots[64];
r29404	r29405
193	193
194	194	stream_sample_t *m_bufferl;
195	195	stream_sample_t *m_bufferr;
196
	196
197	197	int m_length;
198
	198
199	199	signed short *m_RBUFDST; //this points to where the sample will be stored in the RingBuf
200	200	INT32 m_EG_TABLE[0x400];
201	201	int m_PLFO_TRI[256],m_PLFO_SQR[256],m_PLFO_SAW[256],m_PLFO_NOI[256];

trunk/src/emu/sound/dmadac.c
r29404	r29405
46	46
47	47	void dmadac_sound_device::device_start()
48	48	{
49
50	49	/* allocate a clear a buffer */
51	50	m_buffer = auto_alloc_array_clear(machine(), INT16, BUFFER_SIZE);
52	51
r29404	r29405
186	185
187	186	/* flush out as much data as we can */
188	187	for (i = 0; i < num_channels; i++)
189		{
	188	{
190	189	devlist[i]->set_volume(volume);
191	190	}
192	191	}

trunk/src/emu/sound/dmadac.h
r29404	r29405
24	24	void enable(UINT8 enable);
25	25	void set_frequency(double frequency);
26	26	void set_volume(UINT16 volume);
27
	27
28	28	protected:
29	29	// device-level overrides
30	30	virtual void device_start();

trunk/src/emu/sound/mos6560.h
r29404	r29405
138	138	public:
139	139	mos6560_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT32 variant, const char shortname, const char *source);
140	140	mos6560_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
141
	141
142	142	template<class _Object> static devcb2_base &set_potx_rd_callback(device_t &device, _Object object) { return downcast<mos6560_device &>(device).m_read_potx.set_callback(object); }
143	143	template<class _Object> static devcb2_base &set_poty_rd_callback(device_t &device, _Object object) { return downcast<mos6560_device &>(device).m_read_poty.set_callback(object); }
144	144

trunk/src/emu/sound/qs1000.c
r29404	r29405
239	239	m_out_p1_cb.resolve_safe();
240	240	m_out_p2_cb.resolve_safe();
241	241	m_out_p3_cb.resolve_safe();
242
	242
243	243	//m_serial_w_cb.resolve_safe();
244	244
245	245	m_cpu->i8051_set_serial_rx_callback(read8_delegate(FUNC(qs1000_device::data_to_i8052),this));

trunk/src/emu/sound/qs1000.h
r29404	r29405
38	38
39	39	#define MCFG_QS1000_OUT_P3_CB(_devcb) \
40	40	devcb = &qs1000_device::set_out_p3_callback(*device, DEVCB2_##_devcb);
41
	41
42	42	/*#define MCFG_QS1000_SERIAL_W_CB(_devcb) \
43		devcb = &qs1000_device::set_serial_w_callback(device, DEVCB2_##_devcb);/
	43	devcb = &qs1000_device::set_serial_w_callback(device, DEVCB2_##_devcb);/
44	44
45	45	//**************************************************************************
46	46	// TYPE DEFINITIONS
r29404	r29405
67	67	template<class _Object> static devcb2_base &set_out_p2_callback(device_t &device, _Object object) { return downcast<qs1000_device &>(device).m_out_p2_cb.set_callback(object); }
68	68	template<class _Object> static devcb2_base &set_out_p3_callback(device_t &device, _Object object) { return downcast<qs1000_device &>(device).m_out_p3_cb.set_callback(object); }
69	69	//template<class _Object> static devcb2_base &set_serial_w_callback(device_t &device, _Object object) { return downcast<qs1000_device &>(device).m_serial_w_cb.set_callback(object); }
70
	70
71	71	// external
72	72	void serial_in(UINT8 data);
73	73	void set_irq(int state);
r29404	r29405
113	113	void set_voice_regs(int ch);
114	114
115	115	bool m_external_rom;
116
	116
117	117	// Callbacks
118	118	devcb2_read8 m_in_p1_cb;
119	119	devcb2_read8 m_in_p2_cb;

trunk/src/emu/sound/scsp.c
r29404	r29405
173	173	memset(m_MidiStack, 0, sizeof(m_MidiStack));
174	174	memset(m_LPANTABLE, 0, sizeof(m_LPANTABLE));
175	175	memset(m_RPANTABLE, 0, sizeof(m_RPANTABLE));
176		memset(m_TimPris, 0, sizeof(m_TimPris));
	176	memset(m_TimPris, 0, sizeof(m_TimPris));
177	177	memset(m_ARTABLE, 0, sizeof(m_ARTABLE));
178	178	memset(m_DRTABLE, 0, sizeof(m_DRTABLE));
179	179	memset(m_EG_TABLE, 0, sizeof(m_EG_TABLE));
r29404	r29405
187	187	memset(m_ALFO_NOI, 0, sizeof(m_ALFO_NOI));
188	188	memset(m_PSCALES, 0, sizeof(m_PSCALES));
189	189	memset(m_ASCALES, 0, sizeof(m_ASCALES));
190		memset(&m_Slots, 0, sizeof(m_Slots));
191		memset(&m_udata.data, 0, sizeof(m_udata.data));
	190	memset(&m_Slots, 0, sizeof(m_Slots));
	191	memset(&m_udata.data, 0, sizeof(m_udata.data));
192	192	m_TimCnt[0] = 0;
193	193	m_TimCnt[1] = 0;
194	194	m_TimCnt[2] = 0;
r29404	r29405
205	205
206	206	// set up the IRQ callbacks
207	207	m_irq_cb.resolve_safe();
208		m_main_irq_cb.resolve_safe();
	208	m_main_irq_cb.resolve_safe();
209	209
210	210	m_stream = machine().sound().stream_alloc(*this, 0, 2, 44100, this);
211	211	}
r29404	r29405
219	219	m_bufferl = outputs[0];
220	220	m_bufferr = outputs[1];
221	221	m_length = samples;
222		DoMasterSamples(samples);
	222	DoMasterSamples(samples);
223	223	}
224	224
225	225	unsigned char scsp_device::DecodeSCI(unsigned char irq)
r29404	r29405
937	937	((unsigned short ) (m_DSP.COEF+(addr-0x700)/2))=val;
938	938	else if(addr<0x7c0)
939	939	((unsigned short ) (m_DSP.MADRS+(addr-0x780)/2))=val;
940		else if(addr<0x800) // MADRS is mirrored twice
	940	else if(addr<0x800) // MADRS is mirrored twice
941	941	((unsigned short ) (m_DSP.MADRS+(addr-0x7c0)/2))=val;
942	942	else if(addr<0xC00)
943	943	{

trunk/src/emu/sound/scsp.h
r29404	r29405
21	21
22	22	#define MCFG_SCSP_MAIN_IRQ_CB(_devcb) \
23	23	devcb = &scsp_device::set_main_irq_callback(*device, DEVCB2_##_devcb);
24
25	24
	25
26	26	enum SCSP_STATE {SCSP_ATTACK,SCSP_DECAY1,SCSP_DECAY2,SCSP_RELEASE};
27
	27
28	28	struct SCSP_EG_t
29	29	{
30	30	int volume; //
r29404	r29405
56	56	UINT16 data[0x10]; //only 0x1a bytes used
57	57	UINT8 datab[0x20];
58	58	} udata;
59
	59
60	60	UINT8 Backwards; //the wave is playing backwards
61	61	UINT8 active; //this slot is currently playing
62	62	UINT8 *base; //samples base address
r29404	r29405
76	76	{
77	77	public:
78	78	scsp_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
79
	79
80	80	static void set_roffset(device_t &device, int roffset) { downcast<scsp_device &>(device).m_roffset = roffset; }
81	81	template<class _Object> static devcb2_base &set_irq_callback(device_t &device, _Object object) { return downcast<scsp_device &>(device).m_irq_cb.set_callback(object); }
82	82	template<class _Object> static devcb2_base &set_main_irq_callback(device_t &device, _Object object) { return downcast<scsp_device &>(device).m_main_irq_cb.set_callback(object); }
r29404	r29405
88	88	// MIDI I/O access (used for comms on Model 2/3)
89	89	DECLARE_WRITE16_MEMBER( midi_in );
90	90	DECLARE_READ16_MEMBER( midi_out_r );
91
	91
92	92	void set_ram_base(void *base);
93	93
94	94	protected:
r29404	r29405
97	97
98	98	// sound stream update overrides
99	99	virtual void sound_stream_update(sound_stream &stream, stream_sample_t inputs, stream_sample_t outputs, int samples);
100
	100
101	101	private:
102	102	int m_roffset; /* offset in the region */
103		devcb2_write8 m_irq_cb; /* irq callback */
	103	devcb2_write8 m_irq_cb; /* irq callback */
104	104	devcb2_write_line m_main_irq_cb;
105
	105
106	106	union
107	107	{
108	108	UINT16 data[0x30/2];
109	109	UINT8 datab[0x30];
110	110	} m_udata;
111
	111
112	112	SCSP_SLOT m_Slots[32];
113	113	signed short m_RINGBUF[128];
114	114	unsigned char m_BUFPTR;
r29404	r29405
130	130	UINT8 m_MidiOutW, m_MidiOutR;
131	131	UINT8 m_MidiStack[32];
132	132	UINT8 m_MidiW, m_MidiR;
133
	133
134	134	INT32 m_EG_TABLE[0x400];
135	135
136	136	int m_LPANTABLE[0x10000];
r29404	r29405
158	158	int m_ARTABLE[64], m_DRTABLE[64];
159	159
160	160	SCSPDSP m_DSP;
161
	161
162	162	stream_sample_t *m_bufferl;
163	163	stream_sample_t *m_bufferr;
164	164
165	165	int m_length;
166	166
167	167	signed short *m_RBUFDST; //this points to where the sample will be stored in the RingBuf
168
	168
169	169	//LFO
170	170	int m_PLFO_TRI[256], m_PLFO_SQR[256], m_PLFO_SAW[256], m_PLFO_NOI[256];
171	171	int m_ALFO_TRI[256], m_ALFO_SQR[256], m_ALFO_SAW[256], m_ALFO_NOI[256];
172	172	int m_PSCALES[8][256];
173	173	int m_ASCALES[8][256];
174
	174
175	175	void exec_dma(address_space &space); /state DMA transfer function/
176	176	unsigned char DecodeSCI(unsigned char irq);
177	177	void CheckPendingIRQ();
r29404	r29405
198	198	unsigned short r16(address_space &space, unsigned int addr);
199	199	inline INT32 UpdateSlot(SCSP_SLOT *slot);
200	200	void DoMasterSamples(int nsamples);
201
	201
202	202	//LFO
203	203	void LFO_Init();
204	204	signed int PLFO_Step(SCSP_LFO_t *LFO);

trunk/src/emu/sound/msm5232.c
r29404	r29405
26	26	{
27	27	int rate = clock()/CLOCK_RATE_DIVIDER;
28	28	int voicenum;
29
	29
30	30	m_gate_handler_cb.resolve();
31	31
32	32	init(clock(), rate);

trunk/src/emu/sound/msm5232.h
r29404	r29405
6	6
7	7	#define MCFG_MSM5232_SET_CAPACITORS(_a, _b, _c, _d, _e, _f, _g, _h) \
8	8	msm5232_device::static_set_capacitors(*device, _a, _b, _c, _d, _e, _f, _g, _h);
9
	9
10	10	#define MCFG_MSM5232_GATE_HANDLER_CB(_devcb) \
11	11	devcb = &msm5232_device::set_gate_handler_callback(*device, DEVCB2_##_devcb);
12	12
r29404	r29405
45	45	public:
46	46	msm5232_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
47	47	~msm5232_device() {}
48
	48
49	49	static void static_set_capacitors(device_t &device, double cap1, double cap2, double cap3, double cap4, double cap5, double cap6, double cap7, double cap8);
50	50	template<class _Object> static devcb2_base &set_gate_handler_callback(device_t &device, _Object object) { return downcast<msm5232_device &>(device).m_gate_handler_cb.set_callback(object); }
51	51

trunk/src/emu/sound/zsg2.c
r29404	r29405
89	89	m_mem_base = *region();
90	90	m_mem_size = region()->bytes();
91	91	m_mem_blocks = m_mem_size / 4;
92
	92
93	93	m_mem_copy = auto_alloc_array_clear(machine(), UINT32, m_mem_blocks);
94	94	m_full_samples = auto_alloc_array_clear(machine(), INT16, m_mem_blocks * 4 + 4); // +4 is for empty block
95
	95
96	96	// register for savestates
97	97	save_pointer(NAME(m_mem_copy), m_mem_blocks / sizeof(UINT32));
98	98	save_pointer(NAME(m_full_samples), (m_mem_blocks * 4 + 4) / sizeof(INT16));
r29404	r29405
129	129	control_w(4, 0xffff);
130	130	control_w(5, 0xffff);
131	131	control_w(6, 0xffff);
132
	132
133	133	for (int ch = 0; ch < 48; ch++)
134	134	for (int reg = 0; reg < 0x10; reg++)
135	135	chan_w(ch, reg, 0);
r29404	r29405
155	155
156	156	if (block == 0)
157	157	return &m_full_samples[m_mem_blocks]; // overflow or 0
158
	158
159	159	if (block == m_mem_copy[offset])
160	160	return &m_full_samples[offset * 4]; // cached
161
	161
162	162	m_mem_copy[offset] = block;
163	163	offset *= 4;
164
	164
165	165	// decompress 32 byte block to 4 16-bit samples
166	166	// 42222222 51111111 60000000 ssss3333
167	167	m_full_samples[offset\|0] = block >> 8 & 0x7f;
168	168	m_full_samples[offset\|1] = block >> 16 & 0x7f;
169	169	m_full_samples[offset\|2] = block >> 24 & 0x7f;
170	170	m_full_samples[offset\|3] = (block >> (8+1) & 0x40) \| (block >> (16+2) & 0x20) \| (block >> (24+3) & 0x10) \| (block & 0xf);
171
	171
172	172	// sign-extend and shift
173	173	UINT8 shift = block >> 4 & 0xf;
174	174	for (int i = offset; i < (offset + 4); i++)
r29404	r29405
176	176	m_full_samples[i] <<= 9;
177	177	m_full_samples[i] >>= shift;
178	178	}
179
	179
180	180	return &m_full_samples[offset];
181	181	}
182	182
r29404	r29405
197	197	{
198	198	if (!m_chan[ch].is_playing)
199	199	continue;
200
	200
201	201	m_chan[ch].step_ptr += m_chan[ch].step;
202	202	if (m_chan[ch].step_ptr & 0x40000)
203	203	{
r29404	r29405
215	215	}
216	216	m_chan[ch].samples = prepare_samples(m_chan[ch].page \| m_chan[ch].cur_pos);
217	217	}
218
	218
219	219	INT32 sample = (m_chan[ch].samples[m_chan[ch].step_ptr >> 16 & 3] * m_chan[ch].vol) >> 16;
220
	220
221	221	mix_l += (sample * m_chan[ch].panl + sample * (0x1f - m_chan[ch].panr)) >> 5;
222	222	mix_r += (sample * m_chan[ch].panr + sample * (0x1f - m_chan[ch].panl)) >> 5;
223	223	}
r29404	r29405
246	246	m_chan[ch].start_pos = (m_chan[ch].start_pos & 0x00ff) \| (data << 8 & 0xff00);
247	247	m_chan[ch].page = data << 8 & 0xff0000;
248	248	break;
249
	249
250	250	case 0x2:
251	251	// no function? always 0
252	252	break;
253
	253
254	254	case 0x3:
255	255	// unknown, always 0x0400
256	256	break;
257
	257
258	258	case 0x4:
259	259	// frequency
260	260	m_chan[ch].step = data + 1;
r29404	r29405
266	266	m_chan[ch].loop_pos = (m_chan[ch].loop_pos & 0xff00) \| (data & 0xff);
267	267	m_chan[ch].panr = data >> 8 & 0x1f;
268	268	break;
269
	269
270	270	case 0x6:
271	271	// end address
272	272	m_chan[ch].end_pos = data;
r29404	r29405
278	278	m_chan[ch].loop_pos = (m_chan[ch].loop_pos & 0x00ff) \| (data << 8 & 0xff00);
279	279	m_chan[ch].panl = data >> 8 & 0x1f;
280	280	break;
281
	281
282	282	case 0x9:
283	283	// no function? always 0
284	284	break;
285
	285
286	286	case 0xb:
287	287	// always writes 0
288	288	// this register is read-only
289	289	break;
290
	290
291	291	case 0xe:
292	292	// volume
293	293	m_chan[ch].vol = data;
294	294	break;
295
	295
296	296	case 0xf:
297	297	// flags
298	298	m_chan[ch].flags = data;
299	299	break;
300
	300
301	301	default:
302	302	break;
303	303	}
r29404	r29405
316	316	default:
317	317	break;
318	318	}
319
	319
320	320	return m_chan[ch].v[reg];
321	321	}
322	322
r29404	r29405
397	397	default:
398	398	break;
399	399	}
400
	400
401	401	return 0;
402	402	}
403	403

trunk/src/emu/sound/ics2115.c
r29404	r29405
30	30	m_timer[0].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ics2115_device::timer_cb_0),this), this);
31	31	m_timer[1].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ics2115_device::timer_cb_1),this), this);
32	32	m_stream = machine().sound().stream_alloc(*this, 0, 2, 33075);
33
	33
34	34	m_irq_cb.resolve_safe();
35	35
36	36	//Exact formula as per patent 5809466

trunk/src/emu/sound/zsg2.h
r29404	r29405
74	74	INT16 *m_full_samples;
75	75
76	76	sound_stream *m_stream;
77
	77
78	78	devcb2_read32 m_ext_read_handler;
79	79
80	80	UINT32 read_memory(UINT32 offset);

trunk/src/emu/sound/ymf278b.c
r29404	r29405
267	267	if (slot->stepptr >= slot->endaddr)
268	268	{
269	269	slot->stepptr = slot->stepptr - slot->endaddr + slot->loopaddr;
270
	270
271	271	// NOTE: loop overflow is still possible here if (slot->stepptr >= slot->endaddr)
272	272	// This glitch may be (ab)used to your advantage to create pseudorandom noise.
273	273	}

trunk/src/emu/sound/qsound.c
r29404	r29405
11	11
12	12	Many thanks to CAB (the author of Amuse), without whom this probably would
13	13	never have been finished.
14
	14
15	15	TODO:
16	16	- hook up the DSP!
17	17	- is master volume really linear?
r29404	r29405
116	116	// create pan table
117	117	for (int i = 0; i < 33; i++)
118	118	m_pan_table[i] = (int)((256 / sqrt(32.0)) * sqrt((double)i));
119
	119
120	120	// init sound regs
121	121	memset(m_channel, 0, sizeof(m_channel));
122	122
r29404	r29405
165	165	m_channel[ch].address += (m_channel[ch].step_ptr >> 12);
166	166	m_channel[ch].step_ptr &= 0xfff;
167	167	m_channel[ch].step_ptr += m_channel[ch].freq;
168
	168
169	169	if (m_channel[ch].address >= m_channel[ch].end)
170	170	{
171	171	if (m_channel[ch].loop)
172	172	{
173	173	// Reached the end, restart the loop
174	174	m_channel[ch].address -= m_channel[ch].loop;
175
	175
176	176	// Make sure we don't overflow (what does the real chip do in this case?)
177	177	if (m_channel[ch].address >= m_channel[ch].end)
178	178	m_channel[ch].address = m_channel[ch].end - m_channel[ch].loop;
179
	179
180	180	m_channel[ch].address &= 0xffff;
181	181	}
182	182	else
r29404	r29405
186	186	break;
187	187	}
188	188	}
189
	189
190	190	INT8 sample = read_sample(m_channel[ch].bank \| m_channel[ch].address);
191	191	lmix++ += ((sample m_channel[ch].lvol * m_channel[ch].vol) >> 14);
192	192	rmix++ += ((sample m_channel[ch].rvol * m_channel[ch].vol) >> 14);
r29404	r29405
237	237	ch = address >> 3;
238	238	reg = address & 7;
239	239	}
240
	240
241	241	// >= 0x80 is probably for the dsp?
242	242	else if (address < 0x90)
243	243	{
r29404	r29405
312	312	pan = 0x20;
313	313	if (pan < 0)
314	314	pan = 0;
315
	315
316	316	m_channel[ch].rvol = m_pan_table[pan];
317	317	m_channel[ch].lvol = m_pan_table[0x20 - pan];
318	318	break;
319	319	}
320
	320
321	321	case 9:
322	322	// unknown
323	323	break;

trunk/src/emu/sound/k007232.h
r29404	r29405
12	12	#define MCFG_K007232_PORT_WRITE_HANDLER(_devcb) \
13	13	devcb = &k007232_device::set_port_write_handler(*device, DEVCB2_##_devcb);
14	14
15
	15
16	16	class k007232_device : public device_t,
17	17	public device_sound_interface
18	18	{
19	19	public:
20	20	k007232_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
21	21	~k007232_device() {}
22
	22
23	23	template<class _Object> static devcb2_base &set_port_write_handler(device_t &device, _Object object) { return downcast<k007232_device &>(device).m_port_write_handler.set_callback(object); }
24	24
25	25	DECLARE_WRITE8_MEMBER( write );

trunk/src/emu/sound/cdp1869.c
r29404	r29405
369	369
370	370	machine_config_constructor cdp1869_device::device_mconfig_additions() const
371	371	{
372		return MACHINE_CONFIG_NAME( cdp1869 );
	372	return MACHINE_CONFIG_NAME( cdp1869 );
373	373	}
374	374
375	375

trunk/src/emu/sound/cdp1869.h
r29404	r29405
202	202	static void static_set_char_ram_write(device_t &device, cdp1869_char_ram_write_delegate callback) { downcast<cdp1869_device &>(device).m_out_char_ram_func = callback; }
203	203	static void static_set_pcb_read(device_t &device, cdp1869_pcb_read_delegate callback) { downcast<cdp1869_device &>(device).m_in_pcb_func = callback; }
204	204	static void static_set_color_clock(device_t &device, int color_clock) { downcast<cdp1869_device &>(device).m_color_clock = color_clock; }
205
	205
206	206	DECLARE_PALETTE_INIT(cdp1869);
207	207
208	208	virtual DECLARE_ADDRESS_MAP(io_map, 8);
r29404	r29405
228	228
229	229	protected:
230	230	// device-level overrides
231		virtual machine_config_constructor device_mconfig_additions() const;
	231	virtual machine_config_constructor device_mconfig_additions() const;
232	232	virtual void device_start();
233	233	virtual void device_post_load();
234	234	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);

trunk/src/emu/sound/ymz280b.c
r29404	r29405
505	505	if (samples_left \|\| voice->ended)
506	506	{
507	507	voice->ended = false;
508
	508
509	509	/* if there are leftovers, ramp back to 0 */
510	510	int base = new_samples - samples_left;
511	511	int i, t = (base == 0) ? curr : m_scratch[base - 1];

trunk/src/emu/sound/upd7759.c
r29404	r29405
220	220	void upd7759_device::device_start()
221	221	{
222	222	m_drqcallback.resolve_safe();
223
	223
224	224	/* chip configuration */
225	225	m_sample_offset_shift = (type() == UPD7759) ? 1 : 0;
226	226
r29404	r29405
295	295	void upd7756_device::device_start()
296	296	{
297	297	m_drqcallback.resolve_safe();
298
	298
299	299	/* chip configuration */
300	300	m_sample_offset_shift = (type() == UPD7759) ? 1 : 0;
301	301

trunk/src/emu/sound/upd7759.h
r29404	r29405
22	22	~upd775x_device() {}
23	23
24	24	template<class _Object> static devcb2_base &set_drq_callback(device_t &device, _Object object) { return downcast<upd775x_device &>(device).m_drqcallback.set_callback(object); }
25
	25
26	26	void set_bank_base(offs_t base);
27	27
28	28	void reset_w(UINT8 data);
r29404	r29405
82	82	UINT32 m_rommask; /* maximum address offset */
83	83
84	84	devcb2_write_line m_drqcallback;
85
	85
86	86	void update_adpcm(int data);
87	87	void advance_state();
88	88	};

trunk/src/emu/sound/es5503.c
r29404	r29405
235	235
236	236	m_irq_func.resolve_safe();
237	237	m_adc_func.resolve_safe(0);
238
	238
239	239	rege0 = 0xff;
240	240
241	241	for (osc = 0; osc < 32; osc++)

trunk/src/emu/sound/es5503.h
r29404	r29405
13	13
14	14	#define MCFG_ES5503_IRQ_FUNC(_write) \
15	15	devcb = &es5503_device::static_set_irqf(*device, DEVCB2_##_write);
16
	16
17	17	#define MCFG_ES5503_ADC_FUNC(_read) \
18	18	devcb = &es5503_device::static_set_adcf(*device, DEVCB2_##_read);
19	19
r29404	r29405
31	31
32	32	template<class _Object> static devcb2_base &static_set_irqf(device_t &device, _Object object) { return downcast<es5503_device &>(device).m_irq_func.set_callback(object); }
33	33	template<class _Object> static devcb2_base &static_set_adcf(device_t &device, _Object object) { return downcast<es5503_device &>(device).m_adc_func.set_callback(object); }
34
	34
35	35	DECLARE_READ8_MEMBER(read);
36	36	DECLARE_WRITE8_MEMBER(write);
37	37
r29404	r29405
53	53
54	54	const address_space_config m_space_config;
55	55
56		devcb2_write_line m_irq_func;
57		devcb2_read8 m_adc_func;
	56	devcb2_write_line m_irq_func;
	57	devcb2_read8 m_adc_func;
58	58
59	59	emu_timer *m_sync_timer;
60	60

trunk/src/emu/sound/sp0256.h
r29404	r29405
74	74	public:
75	75	sp0256_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
76	76	~sp0256_device() { }
77
	77
78	78	template<class _Object> static devcb2_base &set_data_request_callback(device_t &device, _Object object) { return downcast<sp0256_device &>(device).m_drq_cb.set_callback(object); }
79	79	template<class _Object> static devcb2_base &set_standby_callback(device_t &device, _Object object) { return downcast<sp0256_device &>(device).m_sby_cb.set_callback(object); }
80
	80
81	81	DECLARE_WRITE8_MEMBER(ald_w);
82	82	DECLARE_READ_LINE_MEMBER(lrq_r);
83	83	DECLARE_READ_LINE_MEMBER(sby_r);
r29404	r29405
101	101	void micro();
102	102
103	103	sound_stream m_stream; / MAME core sound stream */
104		devcb2_write_line m_drq_cb; /* Data request callback */
105		devcb2_write_line m_sby_cb; /* Standby callback */
	104	devcb2_write_line m_drq_cb; /* Data request callback */
	105	devcb2_write_line m_sby_cb; /* Standby callback */
106	106
107	107	int m_sby_line; /* Standby line state */
108	108	int m_cur_len; /* Fullness of current sound buffer. */

trunk/src/emu/machine.h
r29404	r29405
284	284	void watchdog_fired(void *ptr = NULL, INT32 param = 0);
285	285	void watchdog_vblank(screen_device &screen, bool vblank_state);
286	286	const char image_parent_basename(device_t device);
287		astring &nvram_filename(astring &result, device_t &device);
	287	astring &nvram_filename(astring &result, device_t &device);
288	288	void nvram_load();
289	289	void nvram_save();
290	290

trunk/src/emu/ioport.c
r29404	r29405
706	706
707	707	//-------------------------------------------------
708	708	// restore_default_seq - restores the sequence
709		// from the default
	709	// from the default
710	710	//-------------------------------------------------
711	711
712	712	void input_type_entry::restore_default_seq()

trunk/src/emu/crsshair.c
r29404	r29405
38	38	UINT8 visible[MAX_PLAYERS]; /* visibility per player */
39	39	bitmap_argb32 * bitmap[MAX_PLAYERS]; /* bitmap per player */
40	40	render_texture * texture[MAX_PLAYERS]; /* texture per player */
41		screen_device * screen[MAX_PLAYERS]; /* the screen on which this player's crosshair is drawn */
	41	screen_device * screen[MAX_PLAYERS]; /* the screen on which this player's crosshair is drawn */
42	42	float x[MAX_PLAYERS]; /* current X position */
43	43	float y[MAX_PLAYERS]; /* current Y position */
44	44	float last_x[MAX_PLAYERS]; /* last X position */

trunk/src/emu/ioport.h
r29404	r29405
1361	1361	ioport_port *first_port() const { return m_portlist.first(); }
1362	1362	bool safe_to_read() const { return m_safe_to_read; }
1363	1363	natural_keyboard &natkeyboard() { return m_natkeyboard; }
1364
	1364
1365	1365	// has... getters
1366	1366	bool has_configs() const { return m_has_configs; }
1367	1367	bool has_analog() const { return m_has_analog; }
r29404	r29405
1448	1448	UINT32 m_playback_accumulated_frames; // accumulated frames during playback
1449	1449
1450	1450	// has...
1451		bool m_has_configs;
1452		bool m_has_analog;
1453		bool m_has_dips;
1454		bool m_has_bioses;
	1451	bool m_has_configs;
	1452	bool m_has_analog;
	1453	bool m_has_dips;
	1454	bool m_has_bioses;
1455	1455	};
1456	1456
1457	1457

trunk/src/emu/memarray.h
r29404	r29405
70	70	// entry-level readers and writers
71	71	UINT32 read(int index) { return (this->*m_read_entry)(index); }
72	72	void write(int index, UINT32 data) { (this->*m_write_entry)(index, data); }
73
	73
74	74	// byte/word/dword-level readers and writers
75	75	UINT8 read8(offs_t offset) { return reinterpret_cast<UINT8 *>(m_base)[offset]; }
76	76	UINT16 read16(offs_t offset) { return reinterpret_cast<UINT16 *>(m_base)[offset]; }

trunk/src/emu/bus/nubus/nubus_specpdq.h
r29404	r29405
51	51	int m_width, m_height, m_patofsx, m_patofsy;
52	52	UINT32 m_vram_addr, m_vram_src;
53	53	UINT8 m_fillbytes[256];
54		required_device<palette_device> m_palette;
	54	required_device<palette_device> m_palette;
55	55	};
56	56
57	57

trunk/src/emu/bus/nubus/nubus_specpdq.c
r29404	r29405
37	37	MCFG_SCREEN_RAW_PARAMS(25175000, 800, 0, 640, 525, 0, 480)
38	38	MCFG_SCREEN_SIZE(1280,1024)
39	39	MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 844-1)
40
	40
41	41	MCFG_PALETTE_ADD("palette", 256)
42	42	MACHINE_CONFIG_END
43	43

trunk/src/emu/bus/adam/exp.h
r29404	r29405
51	51	class device_adam_expansion_slot_card_interface;
52	52
53	53	class adam_expansion_slot_device : public device_t,
54		public device_slot_interface,
55		public device_image_interface
	54	public device_slot_interface,
	55	public device_image_interface
56	56	{
57	57	public:
58	58	// construction/destruction

trunk/src/emu/bus/megadrive/md_slot.c
r29404	r29405
466	466	bool is_smd, is_md;
467	467	UINT32 tmplen = length(), offset, len;
468	468	dynamic_buffer tmpROM(tmplen);
469
	469
470	470	// STEP 1: store a (possibly headered) copy of the file and determine its type (SMD? MD? BIN?)
471	471	fread(tmpROM, tmplen);
472	472	is_smd = genesis_is_SMD(&tmpROM[0x200], tmplen - 0x200);

trunk/src/emu/bus/megadrive/md_carts.c
r29404	r29405
1	1	/**********************************************************************
2	2
3		Megadrive carts
	3	Megadrive carts
4	4
5	5	**********************************************************************/
6	6

trunk/src/emu/bus/ieee488/c2031.h
r29404	r29405
29	29	// ======================> c2031_device
30	30
31	31	class c2031_device : public device_t,
32		public device_ieee488_interface
	32	public device_ieee488_interface
33	33	{
34	34	public:
35	35	// construction/destruction

trunk/src/emu/bus/ieee488/c2040.h
r29404	r29405
38	38	// ======================> c2040_device
39	39
40	40	class c2040_device : public device_t,
41		public device_ieee488_interface
	41	public device_ieee488_interface
42	42	{
43	43	public:
44	44	// construction/destruction

trunk/src/emu/bus/ieee488/c8050.c
r29404	r29405
13	13
14	14	TODO:
15	15
16		- Micropolis 8x50 stepper motor is same as 4040, except it takes 4 pulses to step a track instead of 1
	16	- Micropolis 8x50 stepper motor is same as 4040, except it takes 4 pulses to step a track instead of 1
17	17
18	18	- BASIC program to set 8250/SFD-1001 to 8050 mode:
19	19

trunk/src/emu/bus/ieee488/c2040fdc.c
r29404	r29405
11	11
12	12	/*
13	13
14		TODO:
	14	TODO:
15	15
16		- writing starts in the middle of a byte
17		- 8050 PLL
	16	- writing starts in the middle of a byte
	17	- 8050 PLL
18	18
19	19	*/
20	20
r29404	r29405
67	67	// c2040_fdc_t - constructor
68	68	//-------------------------------------------------
69	69
70		c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source) :
	70	c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source) :
71	71	device_t(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
72	72	m_write_sync(*this),
73	73	m_write_ready(*this),
r29404	r29405
92	92	cur_live.write_start_time = attotime::never;
93	93	}
94	94
95		c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	95	c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
96	96	device_t(mconfig, C2040_FDC, "C2040 FDC", tag, owner, clock, "c2040fdc", __FILE__),
97	97	m_write_sync(*this),
98	98	m_write_ready(*this),
r29404	r29405
117	117	cur_live.write_start_time = attotime::never;
118	118	}
119	119
120		c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	120	c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
121	121	c2040_fdc_t(mconfig, C2040_FDC, "C2040 FDC", tag, owner, clock, "c2040fdc", __FILE__) { }
122	122
123	123
r29404	r29405
242	242	{
243	243	if(cur_live.write_start_time.is_never() \|\| tm == cur_live.write_start_time \|\| !cur_live.write_position)
244	244	return;
245
	245
246	246	if (LOG) logerror("%s committing %u transitions since %s\n", tm.as_string(), cur_live.write_position, cur_live.write_start_time.as_string());
247	247
248	248	if(get_floppy())
r29404	r29405
336	336	cur_live.cell_counter++;
337	337	cur_live.cell_counter &= 0xf;
338	338	}
339
	339
340	340	if (!BIT(cell_counter, 1) && BIT(cur_live.cell_counter, 1)) {
341	341	// read bit
342	342	cur_live.shift_reg <<= 1;
343	343	cur_live.shift_reg \|= !(BIT(cur_live.cell_counter, 3) \|\| BIT(cur_live.cell_counter, 2));
344	344	cur_live.shift_reg &= 0x3ff;
345
346		if (LOG) logerror("%s read bit %u (%u) >> %03x, rw=%u mode=%u\n", cur_live.tm.as_string(), cur_live.bit_counter,
	345
	346	if (LOG) logerror("%s read bit %u (%u) >> %03x, rw=%u mode=%u\n", cur_live.tm.as_string(), cur_live.bit_counter,
347	347	!(BIT(cur_live.cell_counter, 3) \|\| BIT(cur_live.cell_counter, 2)), cur_live.shift_reg, cur_live.rw_sel, cur_live.mode_sel);
348	348
349	349	// write bit
r29404	r29405
375	375	cur_live.e = m_gcr_rom->base()[cur_live.i];
376	376
377	377	int ready = !(BIT(cell_counter, 1) && !BIT(cur_live.cell_counter, 1) && (cur_live.bit_counter == 9));
378
	378
379	379	if (!ready) {
380	380	// load write shift register
381	381	// E7 E6 I7 E5 E4 E3 E2 I2 E1 E0
r29404	r29405
383	383	offs_t i = cur_live.i;
384	384
385	385	cur_live.shift_reg_write = BIT(e,7)<<9 \| BIT(e,6)<<8 \| BIT(i,7)<<7 \| BIT(e,5)<<6 \| BIT(e,4)<<5 \| BIT(e,3)<<4 \| BIT(e,2)<<3 \| BIT(i,2)<<2 \| (e & 0x03);
386
	386
387	387	if (LOG) logerror("%s load write shift register %03x\n",cur_live.tm.as_string(),cur_live.shift_reg_write);
388	388	} else if (BIT(cell_counter, 1) && !BIT(cur_live.cell_counter, 1)) {
389	389	// clock write shift register
390	390	cur_live.shift_reg_write <<= 1;
391	391	cur_live.shift_reg_write &= 0x3ff;
392
	392
393	393	if (LOG) logerror("%s write shift << %03x\n",cur_live.tm.as_string(),cur_live.shift_reg_write);
394	394	}
395	395
r29404	r29405
463	463	offs_t i = checkpoint_live.i;
464	464
465	465	UINT8 data = (BIT(e, 6) << 7) \| (BIT(i, 7) << 6) \| (e & 0x33) \| (BIT(e, 2) << 3) \| (i & 0x04);
466
	466
467	467	if (LOG) logerror("%s VIA reads data %02x (%03x)\n", machine().time().as_string(), data, checkpoint_live.shift_reg);
468
	468
469	469	return data;
470	470	}
471	471

trunk/src/emu/bus/ieee488/softbox.c
r29404	r29405
30	30	#define I8255_1_TAG "ic16"
31	31	#define COM8116_TAG "ic14"
32	32	#define RS232_TAG "rs232"
33		#define CORVUS_HDC_TAG "corvus"
	33	#define CORVUS_HDC_TAG "corvus"
34	34
35	35
36	36

trunk/src/emu/bus/ieee488/hardbox.c
r29404	r29405
53	53	#define Z80_TAG "z80"
54	54	#define I8255_0_TAG "ic17"
55	55	#define I8255_1_TAG "ic16"
56		#define CORVUS_HDC_TAG "corvus"
	56	#define CORVUS_HDC_TAG "corvus"
57	57
58	58
59	59
r29404	r29405
88	88	The version numbers listed are the ROM version reported by the HardBox diagnostics program.
89	89	Disassembling the ROMs showed that v2.3 and v2.4 are for Corvus Systems drives but v3.1 is
90	90	for Sunol Systems drives. Both types use the Corvus flat cable interface but there may be
91		some programming differences, e.g. the v3.1 firmware for Sunol does not have the park heads
92		routine in the Corvus versions. MESS emulates a Corvus drive so we default to the last
93		known HardBox firmware for Corvus (v2.4). */
	91	some programming differences, e.g. the v3.1 firmware for Sunol does not have the park heads
	92	routine in the Corvus versions. MESS emulates a Corvus drive so we default to the last
	93	known HardBox firmware for Corvus (v2.4). */
94	94	ROM_END
95	95
96	96

trunk/src/emu/bus/ieee488/c2031.c
r29404	r29405
286	286	//-------------------------------------------------
287	287
288	288	static SLOT_INTERFACE_START( c2031_floppies )
289		SLOT_INTERFACE( "525ssqd", FLOPPY_525_SSQD )
	289	SLOT_INTERFACE( "525ssqd", FLOPPY_525_SSQD )
290	290	SLOT_INTERFACE_END
291	291
292	292

trunk/src/emu/bus/ieee488/c2040.c
r29404	r29405
36	36	#define M6504_TAG "uh3"
37	37	#define M6522_TAG "um3"
38	38	#define M6530_TAG "uk3"
39		#define FDC_TAG "fdc"
	39	#define FDC_TAG "fdc"
40	40
41	41
42	42
r29404	r29405
385	385
386	386	bit description
387	387
388		PB0
389		PB1
390		PB2
	388	PB0
	389	PB1
	390	PB2
391	391	PB3 WPS
392	392	PB4
393	393	PB5
394	394	PB6 SYNC
395		PB7
	395	PB7
396	396
397	397	*/
398	398
r29404	r29405
416	416	PB0 DRV SEL
417	417	PB1 DS0
418	418	PB2 DS1
419		PB3
	419	PB3
420	420	PB4
421	421	PB5
422		PB6
	422	PB6
423	423	PB7 M6504 IRQ
424	424
425	425	*/
r29404	r29405
452	452	//-------------------------------------------------
453	453
454	454	static SLOT_INTERFACE_START( c2040_floppies )
455		SLOT_INTERFACE( "525ssqd", FLOPPY_525_SSQD )
	455	SLOT_INTERFACE( "525ssqd", FLOPPY_525_SSQD )
456	456	SLOT_INTERFACE_END
457	457
458	458
r29404	r29405
461	461	//-------------------------------------------------
462	462
463	463	FLOPPY_FORMATS_MEMBER( c2040_device::floppy_formats )
464		FLOPPY_D64_FORMAT,
465		FLOPPY_G64_FORMAT,
466		FLOPPY_D67_FORMAT
	464	FLOPPY_D64_FORMAT,
	465	FLOPPY_G64_FORMAT,
	466	FLOPPY_D67_FORMAT
467	467	FLOPPY_FORMATS_END
468	468
469	469

trunk/src/emu/bus/a2bus/a2ultraterm.c
r29404	r29405
7	7	Notes:
8	8
9	9	C0nX: C0n0 is 6845 register address,
10		C0n1 is 6845 register data.
11		C0n2 is control 1: b7 = 0 to read RAM at cc00, 1 for ROM (writes always to RAM)
12		b6 = 0 for Apple II video, 1 for 6845
13		b5 = 0 for 17.430 MHz 6845 clock, 1 for 28.7595 MHz 6845 clock
14		b4 = 0 for 512 byte RAM block addressing (VideoTerm emulation), 1 for 256-byte RAM page addressing
15		b3-b0 = page select
16		C0n3 is control 2: b7 = 0 for attributes software controllable, 1 for DIP switches control attributes
17		b5 = 0 for normal video if bit 7 set, 1 for inverse if bit 7 set
18		b4 = 0 for lowlight if bit 7 set, 1 for highlight if bit 7 set
19		b2 = 0 for high-density character set, 1 for low-density character set
20		b1 = same as b5
21		b0 = same as b4
	10	C0n1 is 6845 register data.
	11	C0n2 is control 1: b7 = 0 to read RAM at cc00, 1 for ROM (writes always to RAM)
	12	b6 = 0 for Apple II video, 1 for 6845
	13	b5 = 0 for 17.430 MHz 6845 clock, 1 for 28.7595 MHz 6845 clock
	14	b4 = 0 for 512 byte RAM block addressing (VideoTerm emulation), 1 for 256-byte RAM page addressing
	15	b3-b0 = page select
	16	C0n3 is control 2: b7 = 0 for attributes software controllable, 1 for DIP switches control attributes
	17	b5 = 0 for normal video if bit 7 set, 1 for inverse if bit 7 set
	18	b4 = 0 for lowlight if bit 7 set, 1 for highlight if bit 7 set
	19	b2 = 0 for high-density character set, 1 for low-density character set
	20	b1 = same as b5
	21	b0 = same as b4
22	22
23	23	C800-CBFF: ROM page 1
24	24	CC00-CFEF: VRAM window or ROM page 2
r29404	r29405
46	46	#define ULTRATERM_MC6845_NAME "mc6845_uterm"
47	47
48	48	#define CLOCK_LOW 17430000
49		#define CLOCK_HIGH 28759500
	49	#define CLOCK_HIGH 28759500
50	50
51		#define CT1_MEMSEL (0x80) // 0 for read RAM at cc00, 1 for read ROM
52		#define CT1_VIDSEL (0x40) // 0 for Apple video passthrough, 1 for 6845 video
53		#define CT1_CLKSEL (0x20) // 0 for Videoterm clock, 1 for faster clock
54		#define CT1_VTEMU (0x10) // Videoterm emulation mode if 0
	51	#define CT1_MEMSEL (0x80) // 0 for read RAM at cc00, 1 for read ROM
	52	#define CT1_VIDSEL (0x40) // 0 for Apple video passthrough, 1 for 6845 video
	53	#define CT1_CLKSEL (0x20) // 0 for Videoterm clock, 1 for faster clock
	54	#define CT1_VTEMU (0x10) // Videoterm emulation mode if 0
55	55	#define CT1_PAGEMASK (0x0f)
56	56
57		#define CT2_USEDIPS (0x80) // 0 to use the rest of ctrl2's bits, 1 to use DIPs
	57	#define CT2_USEDIPS (0x80) // 0 to use the rest of ctrl2's bits, 1 to use DIPs
58	58	#define CT2_INVBIT7H (0x20)
59		#define CT2_HLBIT7H (0x10)
	59	#define CT2_HLBIT7H (0x10)
60	60	#define CT2_HIDENSITY (0x04)
61	61	#define CT2_INVBIT7L (0x02)
62		#define CT2_HLBIT7L (0x01)
	62	#define CT2_HLBIT7L (0x01)
63	63
64	64	static MC6845_UPDATE_ROW( ultraterm_update_row );
65	65
r29404	r29405
96	96
97	97	ROM_START( a2ultraterm )
98	98	ROM_REGION(0x1000, ULTRATERM_ROM_REGION, 0)
99		ROM_LOAD( "frm_b537.bin", 0x000000, 0x001000, CRC(1e85a93e) SHA1(b4acd1775c08ae43996ab4edf6d8e28f4736346b) )
	99	ROM_LOAD( "frm_b537.bin", 0x000000, 0x001000, CRC(1e85a93e) SHA1(b4acd1775c08ae43996ab4edf6d8e28f4736346b) )
100	100
101	101	ROM_REGION(0x1000, ULTRATERM_GFX_REGION, 0)
102		ROM_LOAD( "chs_7859.bin", 0x000000, 0x001000, CRC(ebe8f333) SHA1(3517fa9e7a39573f1cb159b3161d6939dec199ba) )
	102	ROM_LOAD( "chs_7859.bin", 0x000000, 0x001000, CRC(ebe8f333) SHA1(3517fa9e7a39573f1cb159b3161d6939dec199ba) )
103	103
104	104	ROM_REGION(0x400, "pal", 0)
105		ROM_LOAD( "ult_2a313.jed", 0x000000, 0x000305, CRC(dcd51dea) SHA1(0ad0c5e802e48495da27f7bd26ee3ab1c92d74dd) )
	105	ROM_LOAD( "ult_2a313.jed", 0x000000, 0x000305, CRC(dcd51dea) SHA1(0ad0c5e802e48495da27f7bd26ee3ab1c92d74dd) )
106	106	ROM_END
107	107
108	108	ROM_START( a2ultratermenh )
109	109	ROM_REGION(0x1000, ULTRATERM_ROM_REGION, 0)
110		ROM_LOAD( "frm_b5c9.bin", 0x000000, 0x001000, CRC(b71e05e0) SHA1(092e3eda4644d4f465809864a7f023ac7d1d1542) )
	110	ROM_LOAD( "frm_b5c9.bin", 0x000000, 0x001000, CRC(b71e05e0) SHA1(092e3eda4644d4f465809864a7f023ac7d1d1542) )
111	111
112	112	ROM_REGION(0x1000, ULTRATERM_GFX_REGION, 0)
113		ROM_LOAD( "chs_5604.bin", 0x000000, 0x001000, CRC(3fb4e90a) SHA1(94ff75199232a9b613585c22f88470f73fb7dd09) )
	113	ROM_LOAD( "chs_5604.bin", 0x000000, 0x001000, CRC(3fb4e90a) SHA1(94ff75199232a9b613585c22f88470f73fb7dd09) )
114	114
115	115	ROM_REGION(0x400, "pal", 0)
116		ROM_LOAD( "ult_251c.jed", 0x000000, 0x000305, CRC(12fabb0d) SHA1(d4a36837cb98bb65f7ddef7455eb5a7f8e648a82) )
	116	ROM_LOAD( "ult_251c.jed", 0x000000, 0x000305, CRC(12fabb0d) SHA1(d4a36837cb98bb65f7ddef7455eb5a7f8e648a82) )
117	117	ROM_END
118	118
119	119	/***************************************************************************
r29404	r29405
245	245
246	246	case 2:
247	247	m_ctrl1 = data;
248		// printf("%02x to ctrl1\n", data);
	248	// printf("%02x to ctrl1\n", data);
249	249
250	250	// if disabling Videoterm emulation, change RAM banking
251	251	if (data & CT1_VTEMU)
252	252	{
253	253	m_rambank = (data & CT1_PAGEMASK) * 256;
254	254	}
255		break;
	255	break;
256	256
257	257	case 3:
258	258	m_ctrl2 = data;
259		// printf("%02x to ctrl2\n", data);
	259	// printf("%02x to ctrl2\n", data);
260	260	break;
261	261	}
262	262
263	263	if (!(m_ctrl1 & CT1_VTEMU))
264	264	{
265		m_rambank = ((offset >> 2) & 3) * 512;
	265	m_rambank = ((offset >> 2) & 3) * 512;
266	266	}
267	267	}
268	268
r29404	r29405
298	298	}
299	299	else
300	300	{
301		if (m_ctrl1 & CT1_MEMSEL) // read ROM?
	301	if (m_ctrl1 & CT1_MEMSEL) // read ROM?
302	302	{
303	303	return m_rom[offset + 0x800];
304	304	}
305	305
306		return m_ram[(offset - 0x400) + m_rambank];
	306	return m_ram[(offset - 0x400) + m_rambank];
307	307	}
308	308	}
309	309

trunk/src/emu/bus/a2bus/a2corvus.c
r29404	r29405
4	4
5	5	Implementation of the Corvus flat-cable hard disk interface
6	6	for the Apple II.
7
	7
8	8	This same card was used in the Corvus Concept.
9
	9
10	10	C0n0 = drive read/write
11	11	C0n1 = read status (busy in bit 7, data direction in bit 6)
12
13		Reads and writes to C0n2+ happen; the contents of the reads are thrown away
	12
	13	Reads and writes to C0n2+ happen; the contents of the reads are thrown away
14	14	immediately by all the code I've examined, and sending the writes to the
15	15	drive's write port makes it not work so they're intended to be ignored too.
16
	16
17	17	5 MB: -chs 144,4,20 -ss 512
18	18	10 MB: -chs 358,3,20 -ss 512
19	19	20 MB: -chs 388,5,20 -ss 512
20
	20
21	21	To set up a disk from scratch on the Apple II:
22	22	1) Create a disk of your desired capacity using CHDMAN -c none and the parameters
23	23	listed above for each of the possible sizes.
24	24	2) Boot apple2p with the corvus in slot 2 and a diskii(ng) in slot 6 with the
25	25	"Corvus Hard Drive - Diagnostics.dsk" mounted.
26	26	3) Press F to format. Accept all the default options from now on;
27		there is no "format switch" to worry about with the current emulation.
	27	there is no "format switch" to worry about with the current emulation.
28	28	4) Quit MESS. Restart with the corvus in slot 6 and a diskii(ng) in slot 7
29	29	with the "Corvus Hard Drive - Utilities 1.dsk" mounted.
30	30	5) When you get the BASIC prompt, "LOAD BSYSGEN"
r29404	r29405
35	35	10) When the format completes, type "RUN APPLESOFT BOOT PREP" and press Enter.
36	36	11) Once it finishes, quit MESS. Remove the diskii(ng) from slot 7 and
37	37	the system should boot from the Corvus HD.
38
	38
39	39	*********************************************************************/
40	40
41	41	#include "a2corvus.h"
r29404	r29405
53	53	const device_type A2BUS_CORVUS = &device_creator<a2bus_corvus_device>;
54	54
55	55	#define CORVUS_ROM_REGION "corvus_rom"
56		#define CORVUS_HD_TAG "corvushd"
	56	#define CORVUS_HD_TAG "corvushd"
57	57
58	58	static MACHINE_CONFIG_FRAGMENT(corvus)
59	59	MCFG_DEVICE_ADD(CORVUS_HD_TAG, CORVUS_HDC, 0)
r29404	r29405
158	158	{
159	159	if (offset == 0)
160	160	{
161		m_corvushd->write(space, 0, data);
	161	m_corvushd->write(space, 0, data);
162	162	}
163	163	}
164	164
r29404	r29405
180	180	{
181	181	return m_rom[offset & 0x7ff];
182	182	}
183

trunk/src/emu/bus/a2bus/a2ssc.c
r29404	r29405
228	228	{
229	229	if (m_started)
230	230	{
231		if (!(m_dsw2->read() & 4))
	231	if (!(m_dsw2->read() & 4))
232	232	{
233	233	if (state)
234	234	{

trunk/src/emu/bus/a2bus/a2vulcan.c
r29404	r29405
77	77
78	78	ROM_START( vulcangold )
79	79	ROM_REGION(0x4000, VULCAN_ROM_REGION, 0)
80		ROM_LOAD( "ae vulcan gold rom v2.0.bin", 0x000000, 0x004000, CRC(19bc3958) SHA1(96a22c2540fa603648a4e638e176eee76523b4e1) )
	80	ROM_LOAD( "ae vulcan gold rom v2.0.bin", 0x000000, 0x004000, CRC(19bc3958) SHA1(96a22c2540fa603648a4e638e176eee76523b4e1) )
81	81	ROM_END
82	82
83	83	/***************************************************************************

trunk/src/emu/bus/a2bus/a2cffa.c
r29404	r29405
153	153	// Apple /// driver uses sta $c080,x when writing, which causes spurious reads of c088
154	154	if (!m_inwritecycle)
155	155	{
156		m_lastreaddata = m_ata->read_cs0(space, offset - 8, 0xffff);
	156	m_lastreaddata = m_ata->read_cs0(space, offset - 8, 0xffff);
157	157	}
158	158	return m_lastreaddata & 0xff;
159	159
r29404	r29405
184	184	case 0:
185	185	m_lastdata &= 0x00ff;
186	186	m_lastdata \|= data<<8;
187		// printf("%02x to 0, m_lastdata = %x\n", data, m_lastdata);
	187	// printf("%02x to 0, m_lastdata = %x\n", data, m_lastdata);
188	188	m_inwritecycle = true;
189	189	break;
190	190
r29404	r29405
199	199	case 8:
200	200	m_lastdata &= 0xff00;
201	201	m_lastdata \|= data;
202		// printf("%02x to 8, m_lastdata = %x\n", data, m_lastdata);
	202	// printf("%02x to 8, m_lastdata = %x\n", data, m_lastdata);
203	203	m_ata->write_cs0(space, offset-8, m_lastdata, 0xffff);
204	204	break;
205	205

trunk/src/emu/bus/a2bus/a2videoterm.c
r29404	r29405
125	125
126	126	ROM_START( a2aevm80 )
127	127	ROM_REGION(0x800, VIDEOTERM_ROM_REGION, 0)
128		ROM_LOAD( "ae viewmaster 80 rom.bin", 0x000000, 0x000800, CRC(62a4b111) SHA1(159bf7c4add1435be215fddb648c0743fbcc49b5) )
	128	ROM_LOAD( "ae viewmaster 80 rom.bin", 0x000000, 0x000800, CRC(62a4b111) SHA1(159bf7c4add1435be215fddb648c0743fbcc49b5) )
129	129
130	130	ROM_REGION(0x1000, VIDEOTERM_GFX_REGION, 0)
131		ROM_LOAD( "ae viewmaster 80 video rom.bin", 0x000000, 0x000800, CRC(4801ab90) SHA1(f90658ffee7740f3cb30ecef2e151f7dc6098833) )
	131	ROM_LOAD( "ae viewmaster 80 video rom.bin", 0x000000, 0x000800, CRC(4801ab90) SHA1(f90658ffee7740f3cb30ecef2e151f7dc6098833) )
132	132	ROM_END
133	133
134	134	/***************************************************************************

trunk/src/emu/bus/a2bus/a2videoterm.h
r29404	r29405
50	50
51	51	private:
52	52	int m_rambank;
53		public:
	53	public:
54	54	required_device<palette_device> m_palette;
55	55	};
56	56

trunk/src/emu/bus/a2bus/a2pic.c
r29404	r29405
32	32
33	33	ROM_START( pic )
34	34	ROM_REGION(0x000200, PIC_ROM_REGION, 0)
35		ROM_LOAD( "341-0057.bin", 0x000000, 0x000200, CRC(0d2d84ee) SHA1(bfc5b863d37e59875a6159528eb0f2b6082063b5) )
	35	ROM_LOAD( "341-0057.bin", 0x000000, 0x000200, CRC(0d2d84ee) SHA1(bfc5b863d37e59875a6159528eb0f2b6082063b5) )
36	36	ROM_END
37	37
38	38	static INPUT_PORTS_START( pic )
r29404	r29405
182	182	{
183	183	switch (offset)
184	184	{
185		case 3:
	185	case 3:
186	186	return m_ctx_data_in->read();
187	187
188	188	case 4:
189	189	return m_ack;
190	190
191		case 6: // does reading this really work?
	191	case 6: // does reading this really work?
192	192	m_irqenable = true;
193	193	break;
194	194
r29404	r29405
211	211	{
212	212	switch (offset)
213	213	{
214		case 0: // set data out and send a strobe
	214	case 0: // set data out and send a strobe
215	215	m_ctx_data_out->write(data);
216	216
217	217	if (m_autostrobe)
218	218	{
219	219	start_strobe();
220	220	}
221		break;
	221	break;
222	222
223		case 2: // send a strobe
	223	case 2: // send a strobe
224	224	start_strobe();
225	225	break;
226	226
r29404	r29405
236	236	}
237	237	}
238	238
239		WRITE_LINE_MEMBER( a2bus_pic_device::ack_w )
	239	WRITE_LINE_MEMBER( a2bus_pic_device::ack_w )
240	240	{
241	241	if (m_started)
242	242	{
243		UINT8 dsw1 = m_dsw1->read();
	243	UINT8 dsw1 = m_dsw1->read();
244	244
245		if (dsw1 & 0x10) // negative polarity
	245	if (dsw1 & 0x10) // negative polarity
246	246	{
247	247	m_ack = (state == ASSERT_LINE) ? 0x00 : 0x80;
248	248	}
r29404	r29405
251	251	m_ack = (state == ASSERT_LINE) ? 0x80 : 0x00;
252	252	}
253	253
254		m_ack \|= 0x40; // set ACK flip-flop
	254	m_ack \|= 0x40; // set ACK flip-flop
255	255
256	256	if ((dsw1 & 0x40) && (m_irqenable))
257	257	{
r29404	r29405
262	262
263	263	void a2bus_pic_device::start_strobe()
264	264	{
265		int usec = ((m_dsw1->read() & 7) * 2) + 1; // strobe length in microseconds
	265	int usec = ((m_dsw1->read() & 7) * 2) + 1; // strobe length in microseconds
266	266
267		if (m_dsw1->read() & 0x8) // negative polarity
	267	if (m_dsw1->read() & 0x8) // negative polarity
268	268	{
269	269	m_ctx->write_strobe(CLEAR_LINE);
270	270	}
r29404	r29405
278	278
279	279	void a2bus_pic_device::clear_strobe()
280	280	{
281		if (m_dsw1->read() & 0x8) // negative polarity
	281	if (m_dsw1->read() & 0x8) // negative polarity
282	282	{
283	283	m_ctx->write_strobe(ASSERT_LINE);
284	284	}

trunk/src/emu/bus/econet/e01.c
r29404	r29405
197	197	update_interrupts();
198	198	}
199	199
200		WRITE_LINE_MEMBER( e01_device::fdc_drq_w )
	200	WRITE_LINE_MEMBER( e01_device::fdc_drq_w )
201	201	{
202	202	m_fdc_drq = state;
203	203

trunk/src/emu/bus/econet/econet.c
r29404	r29405
196	196	// econet_device - constructor
197	197	//-------------------------------------------------
198	198
199		econet_device::econet_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	199	econet_device::econet_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
200	200	device_t(mconfig, ECONET, "Econet", tag, owner, clock, "econet", __FILE__),
201	201	m_write_clk(*this),
202	202	m_write_data(*this)

trunk/src/emu/bus/econet/econet.h
r29404	r29405
31	31	//**************************************************************************
32	32
33	33	#define MCFG_ECONET_ADD() \
34		MCFG_DEVICE_ADD(ECONET_TAG, ECONET, 0) \
	34	MCFG_DEVICE_ADD(ECONET_TAG, ECONET, 0)
35	35
36
37	36	#define MCFG_ECONET_SLOT_ADD(_tag, _num, _slot_intf, _def_slot) \
38	37	MCFG_DEVICE_ADD(_tag, ECONET_SLOT, 0) \
39	38	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \

trunk/src/emu/bus/ep64/exp.h
r29404	r29405
69	69
70	70	#define MCFG_EP64_EXPANSION_BUS_SLOT_ADD(_tag, _def_slot) \
71	71	MCFG_DEVICE_ADD(_tag, EP64_EXPANSION_BUS_SLOT, 0) \
72		MCFG_DEVICE_SLOT_INTERFACE(ep64_expansion_bus_cards, _def_slot, false) \
	72	MCFG_DEVICE_SLOT_INTERFACE(ep64_expansion_bus_cards, _def_slot, false)
73	73
74
75	74	#define MCFG_EP64_EXPANSION_BUS_SLOT_DAVE(_tag) \
76	75	ep64_expansion_bus_slot_device::static_set_dave_tag(*device, "^"_tag);
77	76
r29404	r29405
95	94	class device_ep64_expansion_bus_card_interface;
96	95
97	96	class ep64_expansion_bus_slot_device : public device_t,
98		public device_slot_interface
	97	public device_slot_interface
99	98	{
100	99	friend class device_ep64_expansion_bus_card_interface;
101	100

trunk/src/emu/bus/sms_exp/smsexp.h
r29404	r29405
51	51	DECLARE_WRITE8_MEMBER(write_mapper);
52	52	DECLARE_READ8_MEMBER(read_ram);
53	53	DECLARE_WRITE8_MEMBER(write_ram);
54
	54
55	55	int get_lphaser_xoffs();
56	56
57	57	device_sms_expansion_slot_interface *m_device;

trunk/src/emu/bus/wangpc/tig.c
r29404	r29405
122	122
123	123	MCFG_PALETTE_ADD_MONOCHROME_GREEN_HIGHLIGHT("palette")
124	124
125		MCFG_DEVICE_ADD(UPD7720_0_TAG, UPD7220, XTAL_52_832MHz/28)
	125	MCFG_DEVICE_ADD(UPD7720_0_TAG, UPD7220, XTAL_52_832MHz/28)
126	126	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_0_map)
127		MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(wangpc_tig_device, hgdc_draw_text)
	127	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(wangpc_tig_device, hgdc_draw_text)
128	128	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
129	129
130	130	MCFG_DEVICE_ADD(UPD7720_1_TAG, UPD7220, XTAL_52_832MHz/28)
131	131	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
132		MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(wangpc_tig_device, hgdc_display_pixels)
	132	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(wangpc_tig_device, hgdc_display_pixels)
133	133	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
134	134	MACHINE_CONFIG_END
135	135

trunk/src/emu/bus/wangpc/wangpc.h
r29404	r29405
82	82	class wangpcbus_device;
83	83
84	84	class wangpcbus_slot_device : public device_t,
85		public device_slot_interface
	85	public device_slot_interface
86	86	{
87	87	public:
88	88	// construction/destruction

trunk/src/emu/bus/wangpc/tig.h
r29404	r29405
61	61	UINT8 m_option;
62	62	UINT8 m_attr[16];
63	63	UINT8 m_underline;
64		required_device<palette_device> m_palette;
	64	required_device<palette_device> m_palette;
65	65	};
66	66
67	67

trunk/src/emu/bus/compucolor/floppy.c
r29404	r29405
111	111
112	112
113	113	//-------------------------------------------------
114		// device_config_complete -
	114	// device_config_complete -
115	115	//-------------------------------------------------
116	116
117	117	void compucolor_floppy_port_device::device_config_complete()

trunk/src/emu/bus/gameboy/gb_slot.c
r29404	r29405
36	36
37	37	device_gb_cart_interface::device_gb_cart_interface(const machine_config &mconfig, device_t &device)
38	38	: device_slot_card_interface(mconfig, device),
39		has_rumble(false),
40		has_timer(false),
	39	has_rumble(false),
	40	has_timer(false),
41	41	has_battery(false)
42	42	{
43	43	}

trunk/src/emu/bus/cbm2/hrg.h
r29404	r29405
26	26	// ======================> cbm2_graphic_cartridge_device
27	27
28	28	class cbm2_graphic_cartridge_device : public device_t,
29		public device_cbm2_expansion_card_interface
	29	public device_cbm2_expansion_card_interface
30	30	{
31	31	public:
32	32	// construction/destruction

trunk/src/emu/bus/cbm2/hrg.c
r29404	r29405
13	13
14	14	TODO:
15	15
16		http://www.wfking.de/hires.htm
	16	http://www.wfking.de/hires.htm
17	17
18	18	- version A (EF9365, 512x512 interlaced, 1 page)
19	19	- version B (EF9366, 512x256 non-interlaced, 2 pages)

trunk/src/emu/bus/cbm2/user.h
r29404	r29405
104	104	// ======================> cbm2_user_port_device
105	105
106	106	class cbm2_user_port_device : public device_t,
107		public device_slot_interface
	107	public device_slot_interface
108	108	{
109	109	public:
110	110	// construction/destruction

trunk/src/emu/bus/coco/coco_fdc.c
r29404	r29405
80	80
81	81	#define LOG_FDC 0
82	82	#define WD_TAG "wd17xx"
83		#define WD2797_TAG "wd2797"
	83	#define WD2797_TAG "wd2797"
84	84	#define DISTO_TAG "disto"
85	85	#define CLOUD9_TAG "cloud9"
86	86
r29404	r29405
437	437	// dragon_fdc_device - constructor
438	438	//-------------------------------------------------
439	439	dragon_fdc_device::dragon_fdc_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source)
440		: coco_fdc_device(mconfig, type, name, tag, owner, clock, shortname, source)
	440	: coco_fdc_device(mconfig, type, name, tag, owner, clock, shortname, source)
441	441	{
442	442	}
443	443	dragon_fdc_device::dragon_fdc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)

trunk/src/emu/bus/coco/coco_fdc.h
r29404	r29405
46	46
47	47	void set_intrq(UINT8 val) { m_intrq = val; }
48	48	void set_drq(UINT8 val) { m_drq = val; }
49
	49
50	50	DECLARE_WRITE_LINE_MEMBER(fdc_intrq_w);
51	51	DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
52	52	protected:
r29404	r29405
65	65	UINT8 m_intrq : 1;
66	66
67	67	optional_device<wd1773_device> m_wd17xx; /* WD17xx */
68		optional_device<wd2797_device> m_wd2797; /* WD2797 */
	68	optional_device<wd2797_device> m_wd2797; /* WD2797 */
69	69	optional_device<ds1315_device> m_ds1315; /* DS1315 */
70	70
71	71	/* Disto RTC */
72	72	optional_device<msm6242_device> m_disto_msm6242; /* 6242 RTC on Disto interface */
73
	73
74	74	offs_t m_msm6242_rtc_address;
75	75	};
76	76

trunk/src/emu/bus/imi7000/imi5000h.h
r29404	r29405
32	32	// ======================> imi5000h_device
33	33
34	34	class imi5000h_device : public device_t,
35		public device_imi7000_interface
	35	public device_imi7000_interface
36	36	{
37	37	public:
38	38	// construction/destruction

trunk/src/emu/bus/c64/magic_formel.c
r29404	r29405
11	11
12	12	/*
13	13
14		TODO:
	14	TODO:
15	15
16		- pia6821 port A DDR needs to reset to 0xff or this won't boot
	16	- pia6821 port A DDR needs to reset to 0xff or this won't boot
17	17
18	18	*/
19	19
r29404	r29405
69	69	PB2 RAM A9
70	70	PB3 RAM A8
71	71	PB4 RAM A12
72		PB5 U9A clr
	72	PB5 U9A clr
73	73	PB6
74	74	PB7 ROMH enable
75	75

trunk/src/emu/bus/bml3/bml3mp1805.h
r29404	r29405
33	33
34	34	DECLARE_READ8_MEMBER(bml3_mp1805_r);
35	35	DECLARE_WRITE8_MEMBER(bml3_mp1805_w);
36
	36
37	37	DECLARE_WRITE_LINE_MEMBER( bml3_mc6843_intrq_w );
38	38
39	39	protected:

trunk/src/emu/bus/vidbrain/exp.h
r29404	r29405
108	108	// ======================> videobrain_expansion_slot_device
109	109
110	110	class videobrain_expansion_slot_device : public device_t,
111		public device_slot_interface,
112		public device_image_interface
	111	public device_slot_interface,
	112	public device_image_interface
113	113	{
114	114	public:
115	115	// construction/destruction

trunk/src/emu/bus/ecbbus/ecbbus.h
r29404	r29405
69	69	//**************************************************************************
70	70
71	71	#define MCFG_ECBBUS_ADD() \
72		MCFG_DEVICE_ADD(ECBBUS_TAG, ECBBUS, 0) \
73
	72	MCFG_DEVICE_ADD(ECBBUS_TAG, ECBBUS, 0)
74	73	#define MCFG_ECBBUS_SLOT_ADD(_num, _tag, _slot_intf, _def_slot) \
75	74	MCFG_DEVICE_ADD(_tag, ECBBUS_SLOT, 0) \
76	75	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
r29404	r29405
94	93	class ecbbus_device;
95	94
96	95	class ecbbus_slot_device : public device_t,
97		public device_slot_interface
	96	public device_slot_interface
98	97	{
99	98	public:
100	99	// construction/destruction

trunk/src/emu/bus/ecbbus/grip.c
r29404	r29405
305	305	static MC6845_INTERFACE( grip5_crtc_intf )
306	306	{
307	307	false,
308		0,0,0,0,
	308	0,0,0,0,
309	309	8,
310	310	NULL,
311	311	grip5_update_row,
312	312	NULL,
313		DEVCB_DEVICE_LINE_MEMBER(Z80STI_TAG, z80sti_device, i1_w),
314		DEVCB_DEVICE_LINE_MEMBER(Z80STI_TAG, z80sti_device, i2_w),
	313	DEVCB_DEVICE_LINE_MEMBER(Z80STI_TAG, z80sti_device, i1_w),
	314	DEVCB_DEVICE_LINE_MEMBER(Z80STI_TAG, z80sti_device, i2_w),
315	315	DEVCB_NULL,
316	316	DEVCB_NULL,
317	317	grip5_update_addr_changed

trunk/src/emu/bus/coleco/sac.h
r29404	r29405
26	26	// ======================> coleco_super_action_controller_t
27	27
28	28	class coleco_super_action_controller_t : public device_t,
29		public device_colecovision_control_port_interface
	29	public device_colecovision_control_port_interface
30	30	{
31	31	public:
32	32	// construction/destruction

trunk/src/emu/bus/coleco/hand.h
r29404	r29405
26	26	// ======================> coleco_hand_controller_t
27	27
28	28	class coleco_hand_controller_t : public device_t,
29		public device_colecovision_control_port_interface
	29	public device_colecovision_control_port_interface
30	30	{
31	31	public:
32	32	// construction/destruction

trunk/src/emu/bus/coleco/std.h
r29404	r29405
25	25	// ======================> colecovision_standard_cartridge_device
26	26
27	27	class colecovision_standard_cartridge_device : public device_t,
28		public device_colecovision_cartridge_interface
	28	public device_colecovision_cartridge_interface
29	29	{
30	30	public:
31	31	// construction/destruction

trunk/src/emu/bus/coleco/exp.h
r29404	r29405
64	64	class device_colecovision_cartridge_interface;
65	65
66	66	class colecovision_cartridge_slot_device : public device_t,
67		public device_slot_interface,
68		public device_image_interface
	67	public device_slot_interface,
	68	public device_image_interface
69	69	{
70	70	public:
71	71	// construction/destruction

trunk/src/emu/bus/plus4/c1551.h
r29404	r29405
30	30	// ======================> c1551_device
31	31
32	32	class c1551_device : public device_t,
33		public device_plus4_expansion_card_interface
	33	public device_plus4_expansion_card_interface
34	34	{
35	35	public:
36	36	// construction/destruction

trunk/src/emu/bus/plus4/c1551.c
r29404	r29405
355	355	//-------------------------------------------------
356	356
357	357	static SLOT_INTERFACE_START( c1551_floppies )
358		SLOT_INTERFACE( "525ssqd", FLOPPY_525_SSQD )
	358	SLOT_INTERFACE( "525ssqd", FLOPPY_525_SSQD )
359	359	SLOT_INTERFACE_END
360	360
361	361

trunk/src/emu/bus/adamnet/spi.c
r29404	r29405
18	18	//**************************************************************************
19	19
20	20	#define M6801_TAG "m6801"
21		#define MC2661_TAG "mc2661"
22		#define RS232_TAG "rs232"
23		#define CENTRONICS_TAG "centronics"
	21	#define MC2661_TAG "mc2661"
	22	#define RS232_TAG "rs232"
	23	#define CENTRONICS_TAG "centronics"
24	24
25	25
26	26

trunk/src/emu/bus/adamnet/spi.h
r29404	r29405
30	30	// ======================> adam_spi_device
31	31
32	32	class adam_spi_device : public device_t,
33		public device_adamnet_card_interface
	33	public device_adamnet_card_interface
34	34	{
35	35	public:
36	36	// construction/destruction

trunk/src/emu/bus/adamnet/fdc.h
r29404	r29405
29	29	// ======================> adam_fdc_device
30	30
31	31	class adam_fdc_device : public device_t,
32		public device_adamnet_card_interface
	32	public device_adamnet_card_interface
33	33	{
34	34	public:
35	35	// construction/destruction

trunk/src/emu/bus/isa/3c505.c
r29404	r29405
3	3	*
4	4	* Created on: August 27, 2010
5	5	* Author: Hans Ostermeyer
6		* ISA conversion by R. Belmont
7		*
	6	* ISA conversion by R. Belmont
	7	*
8	8	* Released for general non-commercial use under the MAME license
9	9	* Visit http://mamedev.org for licensing and usage restrictions.
10	10	*
r29404	r29405
566	566	case 5: m_isa->irq5_w(state); break;
567	567	case 6: m_isa->irq6_w(state); break;
568	568	case 7: m_isa->irq7_w(state); break;
569		case 9: m_isa->irq2_w(state); break; // IRQ 9 on ISA16 goes to IRQ 2
	569	case 9: m_isa->irq2_w(state); break; // IRQ 9 on ISA16 goes to IRQ 2
570	570	case 10: m_isa->irq10_w(state); break;
571	571	case 11: m_isa->irq11_w(state); break;
572	572	case 12: m_isa->irq12_w(state); break;
r29404	r29405
1579	1579	LOG2(("reading 3C505 Register at offset %02x = %02x", offset, data));
1580	1580	return data;
1581	1581	}
1582

trunk/src/emu/bus/isa/adlib.h
r29404	r29405
23	23
24	24	// optional information overrides
25	25	virtual machine_config_constructor device_mconfig_additions() const;
26
	26
27	27	DECLARE_READ8_MEMBER(ym3812_16_r);
28	28	DECLARE_WRITE8_MEMBER(ym3812_16_w);
29	29	protected:

trunk/src/emu/bus/isa/mufdc.c
r29404	r29405
1	1	/***************************************************************************
2	2
3		Multi Unique FDC
	3	Multi Unique FDC
4	4
5	5	license: MAME, GPL-2.0+
6	6	copyright-holders: Dirk Best

trunk/src/emu/bus/isa/mda.c
r29404	r29405
99	99	MACHINE_CONFIG_FRAGMENT( pcvideo_mda )
100	100	MCFG_SCREEN_ADD( MDA_SCREEN_NAME, RASTER)
101	101	MCFG_SCREEN_RAW_PARAMS(MDA_CLOCK, 882, 0, 720, 370, 0, 350 )
102		MCFG_SCREEN_UPDATE_DEVICE( MDA_MC6845_NAME, mc6845_device, screen_update )
	102	MCFG_SCREEN_UPDATE_DEVICE( MDA_MC6845_NAME, mc6845_device, screen_update )
103	103
104	104	MCFG_PALETTE_ADD( "palette", 4 )
105	105

trunk/src/emu/bus/isa/mufdc.h
r29404	r29405
1	1	/***************************************************************************
2	2
3		Multi Unique FDC
	3	Multi Unique FDC
4	4
5	5	license: MAME, GPL-2.0+
6	6	copyright-holders: Dirk Best
r29404	r29405
33	33	// ======================> mufdc_device
34	34
35	35	class mufdc_device : public device_t,
36		public device_isa8_card_interface
	36	public device_isa8_card_interface
37	37	{
38	38	public:
39	39	// construction/destruction

trunk/src/emu/bus/isa/mda.h
r29404	r29405
39	39	protected:
40	40	// device-level overrides
41	41	virtual void device_start();
42		virtual void device_reset();
	42	virtual void device_reset();
43	43	public:
44	44	int m_framecnt;
45	45

trunk/src/emu/bus/isa/sc499.c
r29404	r29405
1	1	/*
2	2	* sc499.c - ARCHIVE SC-499 cartridge tape controller (for Apollo DN3x00)
3	3	* Created on: April 17, 2011
4		* Author: Hans Ostermeyer
5		* ISA conversion by R. Belmont
	4	* Author: Hans Ostermeyer
	5	* ISA conversion by R. Belmont
6	6	*
7	7	* Released for general non-commercial use under the MAME license
8	8	* Visit http://mamedev.org for licensing and usage restrictions.
r29404	r29405
636	636	{
637	637	if (state != irq_state)
638	638	{
639		LOG2(("set_interrupt(%d)",state));
	639	LOG2(("set_interrupt(%d)",state));
640	640	switch (m_irq)
641	641	{
642	642	case 2: m_isa->irq2_w(state); break;
r29404	r29405
659	659	{
660	660	if (state != dma_drq_state)
661	661	{
662		LOG2(("set_dma_drq(%d)",state));
	662	LOG2(("set_dma_drq(%d)",state));
663	663
664	664	switch (m_drq)
665	665	{
r29404	r29405
668	668	case 3: m_isa->drq3_w(state); break;
669	669	default: logerror("sc499: invalid DRQ %d\n", m_drq); break;
670	670	}
671
	671
672	672	dma_drq_state = state;
673	673	}
674	674	}
r29404	r29405
1115	1115	return data;
1116	1116	}
1117	1117
1118		void sc499_device::dack_w(int line, UINT8 data)
	1118	void sc499_device::dack_w(int line, UINT8 data)
1119	1119	{
1120	1120	LOG3(("dack_write: data=%x", data));
1121	1121
r29404	r29405
1311	1311	{
1312	1312	update_names(SC499_CTAPE, "ctape", "ct");
1313	1313	};
1314

trunk/src/emu/bus/isa/pds.c
r29404	r29405
47	47
48	48	void isa8_pds_device::device_reset()
49	49	{
50
51	50	}
52	51
53	52	void isa8_pds_device::device_stop()
54	53	{
55
56	54	}
57	55
58	56	I8255_INTERFACE(pds_ppi_intf)
r29404	r29405
73	71	{
74	72	return MACHINE_CONFIG_NAME( pds_config );
75	73	}
76

trunk/src/emu/bus/isa/aga.c
r29404	r29405
92	92	m_isa->install_memory(0xb0000, 0xbffff, 0, 0, read8_delegate(FUNC(isa8_aga_device::pc_aga_videoram_r),this), write8_delegate(FUNC(isa8_aga_device::pc_aga_videoram_w),this));
93	93	m_isa->install_device(0x3b0, 0x3bf, 0, 0, read8_delegate( FUNC(isa8_aga_device::pc_aga_mda_r), this ), write8_delegate( FUNC(isa8_aga_device::pc_aga_mda_w), this ) );
94	94	m_isa->install_device(0x3d0, 0x3df, 0, 0, read8_delegate( FUNC(isa8_aga_device::pc_aga_cga_r), this ), write8_delegate( FUNC(isa8_aga_device::pc_aga_cga_w), this ) );
95
	95
96	96	/* Initialise the cga palette */
97	97	int i;
98	98
r29404	r29405
113	113	}
114	114	}
115	115	}
116
117		UINT8 *gfx = &memregion("gfx1")->base()[0x8000];
	116
	117	UINT8 *gfx = &memregion("gfx1")->base()[0x8000];
118	118	/* just a plain bit pattern for graphics data generation */
119	119	for (i = 0; i < 256; i++)
120	120	gfx[i] = i;
r29404	r29405
179	179	m_isa->install_memory(0xb0000, 0xbffff, 0, 0, read8_delegate(FUNC(isa8_aga_pc200_device::pc200_videoram_r),this), write8_delegate(FUNC(isa8_aga_pc200_device::pc200_videoram_w),this));
180	180	m_isa->install_device(0x3b0, 0x3bf, 0, 0, read8_delegate( FUNC(isa8_aga_device::pc_aga_mda_r), this ), write8_delegate( FUNC(isa8_aga_device::pc_aga_mda_w), this ) );
181	181	m_isa->install_device(0x3d0, 0x3df, 0, 0, read8_delegate( FUNC(isa8_aga_pc200_device::pc200_cga_r), this ), write8_delegate( FUNC(isa8_aga_pc200_device::pc200_cga_w), this ) );
182
	182
183	183	/* Initialise the cga palette */
184	184	int i;
185	185
r29404	r29405
200	200	}
201	201	}
202	202	}
203
204		UINT8 *gfx = &memregion("gfx1")->base()[0x8000];
	203
	204	UINT8 *gfx = &memregion("gfx1")->base()[0x8000];
205	205	/* just a plain bit pattern for graphics data generation */
206	206	for (i = 0; i < 256; i++)
207	207	gfx[i] = i;
r29404	r29405
765	765	WRITE8_MEMBER (isa8_aga_device:: pc_aga_cga_w )
766	766	{
767	767	if ( m_mode == AGA_COLOR ) {
768
769	768	switch(offset) {
770	769	case 0: case 2: case 4: case 6:
771	770	m_mc6845->address_w( space, offset, data );
r29404	r29405
867	866	}
868	867
869	868	READ8_MEMBER( isa8_aga_device::pc_aga_videoram_r )
870		{
	869	{
871	870	switch (m_mode) {
872	871	case AGA_COLOR:
873	872	if (offset>=0x8000) return m_videoram[offset-0x8000];

trunk/src/emu/bus/isa/omti8621.c
r29404	r29405
3	3	*
4	4	* Created on: August 30, 2010
5	5	* Author: Hans Ostermeyer
6		*
	6	*
7	7	* Converted to ISA device by R. Belmont
8		*
	8	*
9	9	* Released for general non-commercial use under the MAME license
10	10	* Visit http://mamedev.org for licensing and usage restrictions.
11	11	*
r29404	r29405
72	72	virtual void device_config_complete();
73	73	virtual void device_start();
74	74	virtual void device_reset();
75
	75
76	76	void omti_disk_config(UINT16 disk_type);
77	77	public:
78	78	UINT16 m_type;
r29404	r29405
288	288	sector_buffer.resize(OMTI_DISK_SECTOR_SIZE*OMTI_MAX_BLOCK_COUNT);
289	289
290	290	m_timer = timer_alloc(0, NULL);
291
	291
292	292	our_disks[0] = subdevice<omti_disk_image_device>(OMTI_DISK0_TAG);
293	293	our_disks[1] = subdevice<omti_disk_image_device>(OMTI_DISK1_TAG);
294	294	}
r29404	r29405
388	388	set_interrupt - update the IRQ state
389	389	-------------------------------------------------*/
390	390
391		void omti8621_device::set_interrupt(enum line_state line_state)
	391	void omti8621_device::set_interrupt(enum line_state line_state)
392	392	{
393	393	LOG2(("set_interrupt: status_port=%x, line_state %d", status_port, line_state));
394	394	m_isa->irq14_w(line_state);
r29404	r29405
396	396
397	397	void omti8621_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
398	398	{
399		set_interrupt(ASSERT_LINE);
	399	set_interrupt(ASSERT_LINE);
400	400	}
401	401
402	402	/***************************************************************************
r29404	r29405
525	525	set_data_transfer - setup for data transfer from/to data
526	526	***************************************************************************/
527	527
528		void omti8621_device::set_data_transfer(UINT8 *data, UINT16 length)
	528	void omti8621_device::set_data_transfer(UINT8 *data, UINT16 length)
529	529	{
530	530	// set controller for read data transfer
531	531	omti_state = OMTI_STATE_DATA;
r29404	r29405
541	541	read_sectors_from_disk - read sectors starting at diskaddr into sector_buffer
542	542	***************************************************************************/
543	543
544		void omti8621_device::read_sectors_from_disk(INT32 diskaddr, UINT8 count, UINT8 lun)
	544	void omti8621_device::read_sectors_from_disk(INT32 diskaddr, UINT8 count, UINT8 lun)
545	545	{
546	546	UINT8 *data_buffer = sector_buffer;
547	547	device_image_interface *image = our_disks[lun]->m_image;
r29404	r29405
561	561	write_sectors_to_disk - write sectors starting at diskaddr from sector_buffer
562	562	***************************************************************************/
563	563
564		void omti8621_device::write_sectors_to_disk(INT32 diskaddr, UINT8 count, UINT8 lun)
	564	void omti8621_device::write_sectors_to_disk(INT32 diskaddr, UINT8 count, UINT8 lun)
565	565	{
566	566	UINT8 *data_buffer = sector_buffer;
567	567	device_image_interface *image = our_disks[lun]->m_image;
r29404	r29405
586	586	copy_sectors - copy sectors
587	587	***************************************************************************/
588	588
589		void omti8621_device::copy_sectors(INT32 dst_addr, INT32 src_addr, UINT8 count, UINT8 lun)
	589	void omti8621_device::copy_sectors(INT32 dst_addr, INT32 src_addr, UINT8 count, UINT8 lun)
590	590	{
591	591	device_image_interface *image = our_disks[lun]->m_image;
592	592
r29404	r29405
613	613	format track - format a track
614	614	***************************************************************************/
615	615
616		void omti8621_device::format_track(const UINT8 * cdb)
	616	void omti8621_device::format_track(const UINT8 * cdb)
617	617	{
618	618	UINT8 lun = get_lun(cdb);
619	619	UINT32 disk_addr = get_disk_address(cdb);
r29404	r29405
668	668	log_command - log command from a command descriptor block
669	669	***************************************************************************/
670	670
671		void omti8621_device::log_command(const UINT8 cdb[], const UINT16 cdb_length)
	671	void omti8621_device::log_command(const UINT8 cdb[], const UINT16 cdb_length)
672	672	{
673	673	if (verbose > 0) {
674	674	int i;
r29404	r29405
767	767	log_data - log data in the common data buffer
768	768	***************************************************************************/
769	769
770		void omti8621_device::log_data()
	770	void omti8621_device::log_data()
771	771	{
772	772	if (verbose > 0) {
773	773	int i;
r29404	r29405
788	788	do_command
789	789	***************************************************************************/
790	790
791		void omti8621_device::do_command(const UINT8 cdb[], const UINT16 cdb_length)
	791	void omti8621_device::do_command(const UINT8 cdb[], const UINT16 cdb_length)
792	792	{
793	793	UINT8 lun = get_lun(cdb);
794	794	omti_disk_image_device *disk = our_disks[lun];
r29404	r29405
943	943	// LOG(("do_command: UNEXPECTED omti_state %02x",omti_state));
944	944	// }
945	945	status_port \|= OMTI_STATUS_IREQ;
946		if (command_duration == 0)
	946	if (command_duration == 0)
947	947	{
948	948	set_interrupt(ASSERT_LINE);
949		}
950		else
	949	}
	950	else
951	951	{
952	952	// FIXME: should delay omti_state and status_port as well
953	953	m_timer->adjust(attotime::from_msec(command_duration), 0);
r29404	r29405
959	959	get_command_length
960	960	***************************************************************************/
961	961
962		UINT8 omti8621_device::get_command_length(UINT8 command_byte)
	962	UINT8 omti8621_device::get_command_length(UINT8 command_byte)
963	963	{
964	964	return command_byte == OMTI_CMD_COPY ? 10 : 6;
965	965	}
r29404	r29405
968	968	get_data
969	969	***************************************************************************/
970	970
971		UINT16 omti8621_device::get_data()
	971	UINT16 omti8621_device::get_data()
972	972	{
973	973	UINT16 data = 0xff;
974	974	if (data_index < data_length) {
r29404	r29405
989	989	set_data
990	990	***************************************************************************/
991	991
992		void omti8621_device::set_data(UINT16 data)
	992	void omti8621_device::set_data(UINT16 data)
993	993	{
994	994	if (data_index < data_length) {
995	995	data_buffer[data_index++] = data >> 8;
r29404	r29405
1008	1008
1009	1009	WRITE16_MEMBER(omti8621_device::write)
1010	1010	{
1011		switch (mem_mask)
	1011	switch (mem_mask)
1012	1012	{
1013	1013	case 0x00ff:
1014	1014	write8(space, offset*2+1, data, mem_mask);
r29404	r29405
1026	1026
1027	1027	WRITE8_MEMBER(omti8621_device::write8)
1028	1028	{
1029		switch (offset)
	1029	switch (offset)
1030	1030	{
1031	1031	case OMTI_PORT_DATA_OUT: // 0x00
1032	1032	switch (omti_state) {
r29404	r29405
1120	1120
1121	1121	READ16_MEMBER(omti8621_device::read)
1122	1122	{
1123		switch (mem_mask)
	1123	switch (mem_mask)
1124	1124	{
1125	1125	case 0x00ff:
1126	1126	return read8(space, offset*2+1, mem_mask);
r29404	r29405
1138	1138
1139	1139	switch (offset) {
1140	1140	case OMTI_PORT_DATA_IN: // 0x00
1141		if (status_port & OMTI_STATUS_CD)
	1141	if (status_port & OMTI_STATUS_CD)
1142	1142	{
1143	1143	data = command_status;
1144		switch (omti_state)
	1144	switch (omti_state)
1145	1145	{
1146	1146	case OMTI_STATE_COMMAND:
1147	1147	LOG2(("reading OMTI 8621 Data Status Register 1 at offset %02x = %02x (omti state = %02x)", offset, data, omti_state));
r29404	r29405
1155	1155	LOG(("UNEXPECTED reading OMTI 8621 Data Status Register 3 at offset %02x = %02x (omti state = %02x)", offset, data, omti_state));
1156	1156	break;
1157	1157	}
1158		}
1159		else
	1158	}
	1159	else
1160	1160	{
1161	1161	LOG(("UNEXPECTED reading OMTI 8621 Data Register 4 at offset %02x = %02x (status bit C/D = 0)", offset, data));
1162	1162	}
r29404	r29405
1165	1165	case OMTI_PORT_STATUS: // 0x01
1166	1166	data = status_port;
1167	1167	// omit excessive logging
1168		if (data != last_data)
	1168	if (data != last_data)
1169	1169	{
1170	1170	LOG2(("reading OMTI 8621 Status Register 5 at offset %02x = %02x", offset, data));
1171	1171	// last_data = data;
r29404	r29405
1342	1342	-------------------------------------------------*/
1343	1343
1344	1344	void omti_disk_image_device::device_reset()
1345		{
	1345	{
1346	1346	LOG1(("device_reset_omti_disk"));
1347	1347
1348	1348	if (exists() && fseek(0, SEEK_END) == 0)
r29404	r29405
1379	1379	}
1380	1380	return IMAGE_INIT_PASS;
1381	1381	}
1382

trunk/src/emu/bus/isa/cga.c
r29404	r29405
285	285	m_vram.resize(m_vram_size);
286	286	m_update_row = NULL;
287	287	m_isa->install_device(0x3d0, 0x3df, 0, 0, read8_delegate( FUNC(isa8_cga_device::io_read), this ), write8_delegate( FUNC(isa8_cga_device::io_write), this ) );
288		m_isa->install_bank(0xb8000, 0xb8000 + MIN(0x8000,m_vram_size) - 1, 0, m_vram_size & 0x4000, "bank_cga", m_vram);
	288	m_isa->install_bank(0xb8000, 0xb8000 + MIN(0x8000,m_vram_size) - 1, 0, m_vram_size & 0x4000, "bank_cga", m_vram);
289	289
290	290	/* Initialise the cga palette */
291	291	int i;
r29404	r29405
1799	1799	ROM_START( mc1502 )
1800	1800	ROM_REGION(0x2000,"gfx1", 0)
1801	1801	// taken from mc1502
1802		ROM_LOAD( "symgen.rom", 0x0000, 0x2000, CRC(b2747a52) SHA1(6766d275467672436e91ac2997ac6b77700eba1e))
	1802	ROM_LOAD( "symgen.rom", 0x0000, 0x2000, CRC(b2747a52) SHA1(6766d275467672436e91ac2997ac6b77700eba1e))
1803	1803	ROM_END
1804	1804
1805	1805	const rom_entry *isa8_cga_mc1502_device::device_rom_region() const

trunk/src/emu/bus/isa/aga.h
r29404	r29405
38	38	isa8_aga_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
39	39	isa8_aga_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
40	40	// device-level overrides
41		virtual void device_start();
	41	virtual void device_start();
42	42	// optional information overrides
43	43	virtual machine_config_constructor device_mconfig_additions() const;
44	44	virtual const rom_entry *device_rom_region() const;
r29404	r29405
46	46
47	47	DECLARE_WRITE_LINE_MEMBER( hsync_changed );
48	48	DECLARE_WRITE_LINE_MEMBER( vsync_changed );
49
	49
50	50	DECLARE_READ8_MEMBER( pc_aga_mda_r );
51	51	DECLARE_WRITE8_MEMBER( pc_aga_mda_w );
52	52	DECLARE_READ8_MEMBER( pc_aga_cga_r );
r29404	r29405
56	56	DECLARE_WRITE8_MEMBER( pc_aga_videoram_w );
57	57	DECLARE_READ8_MEMBER( pc_aga_videoram_r );
58	58
59		required_device<palette_device> m_palette;
60		required_device<mc6845_device> m_mc6845;
61
	59	required_device<palette_device> m_palette;
	60	required_device<mc6845_device> m_mc6845;
	61
62	62	required_ioport m_cga_config;
63	63
64	64	mc6845_update_row_func m_update_row;
r29404	r29405
75	75	int m_framecnt;
76	76	UINT8 m_vsync;
77	77	UINT8 m_hsync;
78
79	78
	79
80	80	UINT8 m_cga_palette_lut_2bpp[4];
81	81
82		UINT8 *m_videoram;
	82	UINT8 *m_videoram;
83	83	};
84	84
85	85	// device type definition
r29404	r29405
94	94	// construction/destruction
95	95	isa8_aga_pc200_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
96	96	// device-level overrides
97		virtual void device_start();
	97	virtual void device_start();
98	98	// optional information overrides
99	99	virtual const rom_entry *device_rom_region() const;
100
	100
101	101	UINT8 m_port8;
102	102	UINT8 m_portd;
103	103	UINT8 m_porte;
104
	104
105	105	DECLARE_READ8_MEMBER( pc200_videoram_r );
106	106	DECLARE_WRITE8_MEMBER( pc200_videoram_w );
107	107	DECLARE_WRITE8_MEMBER( pc200_cga_w );

trunk/src/emu/bus/isa/omti8621.h
r29404	r29405
2	2	* omti8621.h - SMS OMTI 8621 disk controller
3	3	*
4	4	* Created on: August 30, 2010
5		* Author: Hans Ostermeyer
6		*
	5	* Author: Hans Ostermeyer
	6	*
7	7	* Converted to ISA device March 3, 2014 by R. Belmont
8	8	*
9	9	* Released for general non-commercial use under the MAME license
r29404	r29405
28	28	***************************************************************************/
29	29
30	30	class omti_disk_image_device;
31
	31
32	32	/* ----- device interface ----- */
33	33
34	34	class omti8621_device : public device_t, public device_isa16_card_interface

trunk/src/emu/bus/isa/cga.h
r29404	r29405
68	68	bool m_superimpose;
69	69	UINT8 m_plantronics; /* This should be moved into the appropriate subclass */
70	70	offs_t m_start_offset;
71		required_device<palette_device> m_palette;
	71	required_device<palette_device> m_palette;
72	72	};
73	73
74	74	// device type definition

trunk/src/emu/bus/isa/ega.h
r29404	r29405
96	96	UINT8 m_vsync;
97	97	UINT8 m_vblank;
98	98	UINT8 m_display_enable;
99		required_device<palette_device> m_palette;
	99	required_device<palette_device> m_palette;
100	100	};
101	101
102	102

trunk/src/emu/bus/isa/gblaster.h
r29404	r29405
23	23
24	24	// optional information overrides
25	25	virtual machine_config_constructor device_mconfig_additions() const;
26
	26
27	27	DECLARE_READ8_MEMBER(saa1099_16_r);
28	28	DECLARE_WRITE8_MEMBER(saa1099_1_16_w);
29	29	DECLARE_WRITE8_MEMBER(saa1099_2_16_w);

trunk/src/emu/bus/isa/isa.c
r29404	r29405
243	243	m_iowidth = m_iospace->data_width();
244	244	m_prgwidth = m_prgspace->data_width();
245	245	}
246		else // use host CPU's program and I/O spaces directly
	246	else // use host CPU's program and I/O spaces directly
247	247	{
248		m_iospace = &m_maincpu->space(AS_IO);
249		m_iowidth = m_maincpu->space_config(AS_IO)->m_databus_width;
	248	m_iospace = &m_maincpu->space(AS_IO);
	249	m_iowidth = m_maincpu->space_config(AS_IO)->m_databus_width;
250	250	m_prgspace = &m_maincpu->space(AS_PROGRAM);
251		m_prgwidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
	251	m_prgwidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
252	252	}
253	253	}
254	254
r29404	r29405
679	679	void device_isa16_card_interface::dack16_w(int line,UINT16 data)
680	680	{
681	681	}
682
683

trunk/src/emu/bus/isa/sblaster.c
r29404	r29405
1190	1190	set_isa_device();
1191	1191	// 1.0 always has the SAA1099s for CMS back-compatibility
1192	1192	m_isa->install_device(0x0220, 0x0221, 0, 0, read8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_16_r), this ), write8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_1_16_w), this ) );
1193		m_isa->install_device(0x0222, 0x0223, 0, 0, read8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_16_r), this ), write8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_2_16_w), this ) );
	1193	m_isa->install_device(0x0222, 0x0223, 0, 0, read8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_16_r), this ), write8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_2_16_w), this ) );
1194	1194	m_isa->set_dma_channel(1, this, FALSE);
1195	1195	m_dsp.version = 0x0105;
1196	1196	sb8_device::device_start();

trunk/src/emu/bus/isa/isa.h
r29404	r29405
156	156	template<class _iochck> void set_iochck_callback(_iochck iochck) { m_write_iochck.set_callback(iochck); }
157	157
158	158	// for ISA8, put the 8-bit configs in the primary slots and the 16-bit configs in the secondary
159		virtual const address_space_config *memory_space_config(address_spacenum spacenum) const
160		{
	159	virtual const address_space_config *memory_space_config(address_spacenum spacenum) const
	160	{
161	161	switch (spacenum)
162	162	{
163	163	case AS_PROGRAM: return &m_program_config;
164		case AS_IO: return &m_io_config;
165		case AS_DATA: return &m_program16_config;
166		case AS_3: return &m_io16_config;
167		default: fatalerror("isa: invalid memory space!\n");
	164	case AS_IO: return &m_io_config;
	165	case AS_DATA: return &m_program16_config;
	166	case AS_3: return &m_io16_config;
	167	default: fatalerror("isa: invalid memory space!\n");
168	168	}
169	169	}
170	170
171	171	void install_device(offs_t start, offs_t end, offs_t mask, offs_t mirror, read8_delegate rhandler, write8_delegate whandler);
172		template<typename T> void install_device(offs_t addrstart, offs_t addrend, T &device, void (T::*map)(class address_map &map, device_t &device), int bits = 8, UINT64 unitmask = U64(0xffffffffffffffff))
	172	template<typename T> void install_device(offs_t addrstart, offs_t addrend, T &device, void (T::*map)(class address_map &map, device_t &device), int bits = 8, UINT64 unitmask = U64(0xffffffffffffffff))
173	173	{
174		m_iospace->install_device(addrstart, addrend, device, map, bits, unitmask);
	174	m_iospace->install_device(addrstart, addrend, device, map, bits, unitmask);
175	175	}
176	176	void install_bank(offs_t start, offs_t end, offs_t mask, offs_t mirror, const char tag, UINT8 data);
177	177	void install_rom(device_t dev, offs_t start, offs_t end, offs_t mask, offs_t mirror, const char tag, const char *region);
r29404	r29405
331	331	void install16_device(offs_t start, offs_t end, offs_t mask, offs_t mirror, read16_delegate rhandler, write16_delegate whandler);
332	332
333	333	// for ISA16, put the 16-bit configs in the primary slots and the 8-bit configs in the secondary
334		virtual const address_space_config *memory_space_config(address_spacenum spacenum) const
335		{
	334	virtual const address_space_config *memory_space_config(address_spacenum spacenum) const
	335	{
336	336	switch (spacenum)
337	337	{
338	338	case AS_PROGRAM: return &m_program16_config;
339		case AS_IO: return &m_io16_config;
340		case AS_DATA: return &m_program_config;
341		case AS_3: return &m_io_config;
342		default: fatalerror("isa: invalid memory space!\n");
	339	case AS_IO: return &m_io16_config;
	340	case AS_DATA: return &m_program_config;
	341	case AS_3: return &m_io_config;
	342	default: fatalerror("isa: invalid memory space!\n");
343	343	}
344	344	}
345	345

trunk/src/emu/bus/isa/side116.h
r29404	r29405
26	26	// ======================> side116_device
27	27
28	28	class side116_device : public device_t,
29		public device_isa8_card_interface
	29	public device_isa8_card_interface
30	30	{
31	31	public:
32	32	// construction/destruction

trunk/src/emu/bus/isa/sblaster.h
r29404	r29405
157	157	public:
158	158	// construction/destruction
159	159	sb8_device(const machine_config &mconfig, device_type type, const char tag, device_t owner, UINT32 clock, const char name, const char shortname, const char *source);
160
	160
161	161	DECLARE_READ8_MEMBER(ym3812_16_r);
162		DECLARE_WRITE8_MEMBER(ym3812_16_w);
	162	DECLARE_WRITE8_MEMBER(ym3812_16_w);
163	163	protected:
164	164	virtual void device_start();
165	165	virtual void drq_w(int state) { m_isa->drq1_w(state); }
166	166	virtual void irq_w(int state, int source) { m_isa->irq5_w(state); }
167	167	virtual UINT8 dack_r(int line) { return sb_device::dack_r(line); }
168	168	virtual void dack_w(int line, UINT8 data) { sb_device::dack_w(line, data); }
169		private:
170		required_device<ym3812_device> m_ym3812;
	169	private:
	170	required_device<ym3812_device> m_ym3812;
171	171	};
172	172
173	173	class isa8_sblaster1_0_device : public sb8_device
r29404	r29405
189	189	// internal state
190	190	required_device<saa1099_device> m_saa1099_1;
191	191	required_device<saa1099_device> m_saa1099_2;
192
	192
193	193	};
194	194
195	195	class isa8_sblaster1_5_device : public sb8_device

trunk/src/emu/bus/isa/dectalk.c
r29404	r29405
143	143	ROM_LOAD16_BYTE("pc_boot_hxl.am27c64.d6.e26", 0x0000, 0x2000, CRC(7492f1e3) SHA1(fe6946a227f01c94f2b99220320a616445c96ee0)) // Some cards have a different label on the chip which lists the sum16: 31AC (matches contents)
144	144	ROM_LOAD16_BYTE("pc_boot_hxh.am27c64.d8.e27", 0x0001, 0x2000, CRC(1fe7fe40) SHA1(6e89c237f01aa22e0d21ff4d6fdf8137c6ace374)) // Some cards have a different label on the chip which lists the sum16: 1A25 (matches contents)
145	145	ROM_REGION( 0x2000, "dectalk_dsp", 0 )
146		ROM_LOAD("spc_034c__2-1-92.tms320p15nl.d3.bin", 0x0000, 0x2000, CRC(d8b1201e) SHA1(4b873a5e882205fcac79a27562054b5c4d1a117c))
	146	ROM_LOAD("spc_034c__2-1-92.tms320p15nl.d3.bin", 0x0000, 0x2000, CRC(d8b1201e) SHA1(4b873a5e882205fcac79a27562054b5c4d1a117c))
147	147	ROM_END
148	148
149	149	const rom_entry* dectalk_isa_device::device_rom_region() const

trunk/src/emu/bus/comx35/printer.c
r29404	r29405
73	73	MCFG_CENTRONICS_BUSY_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit1))
74	74	MCFG_CENTRONICS_PERROR_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit2))
75	75	MCFG_CENTRONICS_SELECT_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit3))
76		MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics")
	76	MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics")
77	77
78	78	MCFG_DEVICE_ADD("cent_status_in", INPUT_BUFFER, 0)
79	79	MACHINE_CONFIG_END

trunk/src/emu/bus/comx35/exp.h
r29404	r29405
74	74	class device_comx_expansion_card_interface;
75	75
76	76	class comx_expansion_slot_device : public device_t,
77		public device_slot_interface
	77	public device_slot_interface
78	78	{
79	79	public:
80	80	// construction/destruction

trunk/src/emu/bus/cbmiec/c1541.c
r29404	r29405
706	706	//-------------------------------------------------
707	707
708	708	static SLOT_INTERFACE_START( c1540_floppies )
709		SLOT_INTERFACE( "525ssqd", ALPS_3255190x )
	709	SLOT_INTERFACE( "525ssqd", ALPS_3255190x )
710	710	SLOT_INTERFACE_END
711	711
712	712
r29404	r29405
715	715	//-------------------------------------------------
716	716
717	717	FLOPPY_FORMATS_MEMBER( base_c1541_device::floppy_formats )
718		FLOPPY_D64_FORMAT,
719		FLOPPY_G64_FORMAT
	718	FLOPPY_D64_FORMAT,
	719	FLOPPY_G64_FORMAT
720	720	FLOPPY_FORMATS_END
721	721
722	722
r29404	r29405
889	889
890	890	MCFG_CENTRONICS_ADD(CENTRONICS_TAG, centronics_printers, "image")
891	891	MCFG_CENTRONICS_ACK_HANDLER(DEVWRITELINE(MC6821_TAG, pia6821_device, ca1_w))
892		MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics")
	892	MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics")
893	893	MACHINE_CONFIG_END
894	894
895	895

trunk/src/emu/bus/cbmiec/c1571.c
r29404	r29405
13	13
14	14	TODO:
15	15
16		- WD1770 set_floppy
	16	- WD1770 set_floppy
17	17	- 1571CR
18	18	- MOS5710
19	19	- ICT Mini Chief MC-20
r29404	r29405
698	698	MCFG_MOS6526_PB_INPUT_CALLBACK(READ8(c1571_device, cia_pb_r))
699	699	MCFG_MOS6526_PB_OUTPUT_CALLBACK(WRITE8(c1571_device, cia_pb_w))
700	700	MCFG_MOS6526_PC_CALLBACK(WRITELINE(c1571_device, cia_pc_w))
701
	701
702	702	MCFG_WD1770x_ADD(WD1770_TAG, XTAL_16MHz/2)
703	703	MCFG_DEVICE_ADD(C64H156_TAG, C64H156, XTAL_16MHz)
704	704	MCFG_64H156_BYTE_CALLBACK(WRITELINE(c1571_device, byte_w))

trunk/src/emu/bus/cbmiec/c1541.h
r29404	r29405
40	40	// ======================> base_c1541_device
41	41
42	42	class base_c1541_device : public device_t,
43		public device_cbm_iec_interface,
44		public device_c64_floppy_parallel_interface
	43	public device_cbm_iec_interface,
	44	public device_c64_floppy_parallel_interface
45	45	{
46	46	public:
47	47	// construction/destruction

trunk/src/emu/bus/cbmiec/c1571.h
r29404	r29405
42	42	// ======================> c1571_device
43	43
44	44	class c1571_device : public device_t,
45		public device_cbm_iec_interface,
46		public device_c64_floppy_parallel_interface
	45	public device_cbm_iec_interface,
	46	public device_c64_floppy_parallel_interface
47	47	{
48	48	public:
49	49	// construction/destruction

trunk/src/emu/bus/nes/act53.c
r29404	r29405
7	7	Visit http://mamedev.org for licensing and usage restrictions.
8	8
9	9
10		Here we emulate the Multi-Discrete PCB designed by Tepples for
	10	Here we emulate the Multi-Discrete PCB designed by Tepples for
11	11	this homebew multicart [mapper 28]
12	12
13	13	***********************************************************************************************************/
r29404	r29405
67	67
68	68	Board ACTION 53
69	69
70		In MESS: VERY preliminary support.
71
	70	In MESS: VERY preliminary support.
	71
72	72	This board uses 4 registers (reg is selected by writes to 0x5xxx)
73	73	Info from nesdev wiki
74
	74
75	75	R:$00: [...M ..CC]
76	76	C = CHR Reg
77	77	M = Mirroring
78	78	This bit overwrites bit 0 of R:$80, but only if bit 1 of
79	79	R:$80 is clear
80
	80
81	81	R:$01: [...M PPPP]
82	82	P = PRG Reg
83	83	M = Mirroring
84	84	This bit overwrites bit 0 of R:$80, but only if bit 1 of
85	85	R:$80 is clear
86
	86
87	87	R:$80: [..GG PSMM]
88	88	G = Game Size (0=32K, 1=64K, 2=128K, 3=256K)
89	89	P = PRG Size (0=32k mode, 1=16k mode)
r29404	r29405
106	106	void nes_action53_device::update_prg()
107	107	{
108	108	UINT8 prg_lo = 0, prg_hi = 0, helper = 0;
109		UINT8 out = (m_reg[3] & 0x3f) << 1; // Outer PRG reg
110		UINT8 size = (m_reg[2] & 0x30) >> 4; // Game size
111		UINT8 mask = (1 << (size + 1)) - 1; // Bits to be taken from PRG reg
	109	UINT8 out = (m_reg[3] & 0x3f) << 1; // Outer PRG reg
	110	UINT8 size = (m_reg[2] & 0x30) >> 4; // Game size
	111	UINT8 mask = (1 << (size + 1)) - 1; // Bits to be taken from PRG reg
112	112
113	113	if (!BIT(m_reg[2], 3))
114	114	{
r29404	r29405
134	134	}
135	135	}
136	136
137		// printf("banks : 0x%2X - 0x%2X\n", prg_lo, prg_hi);
	137	// printf("banks : 0x%2X - 0x%2X\n", prg_lo, prg_hi);
138	138	prg16_89ab(prg_lo);
139	139	prg16_cdef(prg_hi);
140	140	}

trunk/src/emu/bus/nes/nes_ines.inc
r29404	r29405
56	56	{ 24, KONAMI_VRC6 },
57	57	{ 25, KONAMI_VRC4 },
58	58	{ 26, KONAMI_VRC6 },
59		{ 27, UNL_WORLDHERO }, // 27 World Hero board - Unsupported
60		{ 28, BTL_ACTION53 }, // 28 - Multi-discrete PCB designed by Tepples for Action 53
	59	{ 27, UNL_WORLDHERO }, // 27 World Hero board - Unsupported
	60	{ 28, BTL_ACTION53 }, // 28 - Multi-discrete PCB designed by Tepples for Action 53
61	61	// 29 Unused
62	62	// 30 Unused
63	63	// 31 Unused
r29404	r29405
132	132	// 100 images hacked to work with nesticle?
133	133	// 101 Unused (Urusei Yatsura had been assigned to this mapper, but it's Mapper 87)
134	134	// 102 Unused
135		{ 103, UNL_2708 }, // 103 Bootleg cart 2708 (Doki Doki Panic - FDS Conversion) - Unsupported
	135	{ 103, UNL_2708 }, // 103 Bootleg cart 2708 (Doki Doki Panic - FDS Conversion) - Unsupported
136	136	{ 104, CAMERICA_GOLDENFIVE },
137	137	{ 105, STD_EVENT },
138	138	{ 106, BTL_SMB3 },
r29404	r29405
191	191	{ 159, BANDAI_LZ93EX1 }, // with 24c01
192	192	{ 160, SACHEN_SA009 },
193	193	// 161 Unused
194		{ 162, WAIXING_FS304}, // not confirmed, but a lot of chinese releases use it like this...
	194	{ 162, WAIXING_FS304}, // not confirmed, but a lot of chinese releases use it like this...
195	195	{ 163, NANJING_BOARD},
196	196	{ 164, WAIXING_FFV },
197	197	{ 165, WAIXING_SH2 },
r29404	r29405
264	264	{ 232, CAMERICA_BF9096 },
265	265	{ 233, BMC_SUPER22 },
266	266	{ 234, AVE_MAXI15 },
267		{ 235, BMC_GOLD150 }, // 235 Golden Game x-in-1 - Unsupported
	267	{ 235, BMC_GOLD150 }, // 235 Golden Game x-in-1 - Unsupported
268	268	// 236 Game 800-in-1 - Unsupported
269	269	// 237 Unused
270	270	{ 238, UNL_603_5052 },
r29404	r29405
525	525	switch (m_pcb_id)
526	526	{
527	527	case STD_NROM:
528		if (prg_size == 3 * 0x4000) // NROM368 are padded with 2k empty data at start to accomplish with iNES standard
	528	if (prg_size == 3 * 0x4000) // NROM368 are padded with 2k empty data at start to accomplish with iNES standard
529	529	{
530	530	m_pcb_id = STD_NROM368;
531	531	fseek(0x810, SEEK_SET);
r29404	r29405
834	834	}
835	835
836	836	// use info from nes.hsi if available!
837		// if (hashfile_extrainfo(*this, mapinfo))
	837	// if (hashfile_extrainfo(*this, mapinfo))
838	838	if (0)
839	839	{
840	840	if (4 == sscanf(mapinfo,"%d %d %d %d", &mapint1, &mapint2, &mapint3, &mapint4))

trunk/src/emu/bus/nes/camerica.c
r29404	r29405
13	13	* Camerica BF9096 Boards [mapper 232]
14	14	* Camerica Golden Five [mapper 104]
15	15
16		Aladdin Deck Enhancer pass-thru cart and the corresponding minicarts
	16	Aladdin Deck Enhancer pass-thru cart and the corresponding minicarts
17	17	(ALGNV11 & ALGQV11 PCBs) are emulated in a separate source file.
18	18
19
	19
20	20	TODO:
21	21	- check what causes flickering from PPU in Fire Hawk, Poogie and Big Nose (same PPU issue as Back to
22	22	Future 2&3?)
r29404	r29405
189	189	{
190	190	m_latch = data & 3;
191	191	prg16_89ab(m_bank_base \| m_latch);
192		}
	192	}
193	193	}
194	194
195	195	/*-------------------------------------------------

trunk/src/emu/bus/nes/mmc5.c
r29404	r29405
117	117	m_split_chr = 0;
118	118	m_ex1_bank = 0;
119	119	m_vcount = 0;
120
	120
121	121	memset(m_vrom_bank, 0x3ff, ARRAY_LENGTH(m_vrom_bank));
122	122	m_prg_regs[0] = 0xfc;
123	123	m_prg_regs[1] = 0xfd;
r29404	r29405
241	241	void nes_exrom_device::hblank_irq(int scanline, int vblank, int blanked )
242	242	{
243	243	m_vcount = scanline;
244
	244
245	245	if (scanline == m_irq_count)
246	246	{
247	247	if (m_irq_enable)
r29404	r29405
284	284	{
285	285	ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
286	286	int tile = ppu->get_tilenum();
287
	287
288	288	if (tile < 34)
289	289	{
290	290	if (!m_split_rev && tile < m_split_ctrl)
r29404	r29405
303	303	{
304	304	case MMC5FILL:
305	305	if ((offset & 0x3ff) >= 0x3c0)
306		return m_floodattr;
	306	return m_floodattr;
307	307	return m_floodtile;
308	308
309	309	case EXRAM:
r29404	r29405
315	315
316	316	case CIRAM:
317	317	default:
318		// Uchuu Keibitai SDF uses extensively split screen for its intro,
	318	// Uchuu Keibitai SDF uses extensively split screen for its intro,
319	319	// but it does not work yet
320	320	if (m_split_scr && !(m_exram_control & 0x02) && in_split())
321	321	{
r29404	r29405
338	338	{
339	339	if ((offset & 0x3ff) >= 0x3c0)
340	340	return m_mmc5_attrib[(m_exram[offset & 0x3ff] >> 6) & 0x03];
341		else // in this case, we write Ex1 CHR bank, but then access NT normally!
	341	else // in this case, we write Ex1 CHR bank, but then access NT normally!
342	342	{
343	343	m_ex1_chr = 1;
344	344	m_ex1_bank = (m_exram[offset & 0x3ff] & 0x3f) \| (m_high_chr << 6);
r29404	r29405
350	350
351	351	WRITE8_MEMBER(nes_exrom_device::nt_w)
352	352	{
353		int page = ((offset & 0xc00) >> 10);
354
	353	int page = ((offset & 0xc00) >> 10);
	354
355	355	if (!m_nt_writable[page])
356	356	return;
357
	357
358	358	switch (m_nt_src[page])
359	359	{
360	360	case EXRAM:
361	361	m_exram[offset & 0x3ff] = data;
362	362	break;
363
	363
364	364	case CIRAM:
365	365	default:
366	366	m_nt_access[page][offset & 0x3ff] = data;
r29404	r29405
415	415	// However, if a game enables Ex1 but does not write a new m_ex1_bank, I'm not sure here we get the correct behavior
416	416	if (m_exram_control == 1 && ppu->get_draw_phase() == PPU_DRAW_BG && m_ex1_chr)
417	417	return bg_ex1_chr_r(offset & 0xfff);
418
	418
419	419	if (m_split_scr && !(m_exram_control & 0x02) && in_split() && ppu->get_draw_phase() == PPU_DRAW_BG && m_split_chr)
420	420	return split_chr_r(offset & 0xfff);
421
	421
422	422	if (ppu->is_sprite_8x16())
423	423	{
424	424	if (ppu->get_draw_phase() == PPU_DRAW_OAM)
r29404	r29405
444	444	if ((offset >= 0x1c00) && (offset <= 0x1fff))
445	445	{
446	446	// EXRAM
447		if (BIT(m_exram_control, 1)) // Modes 2,3 = read
	447	if (BIT(m_exram_control, 1)) // Modes 2,3 = read
448	448	return m_exram[offset - 0x1c00];
449		else
	449	else
450	450	return m_open_bus; // Modes 0,1 = open bus
451	451	}
452	452
r29404	r29405
486	486	if ((offset >= 0x1c00) && (offset <= 0x1fff))
487	487	{
488	488	// EXRAM
489		if (m_exram_control == 0x02) // Mode 2 = write data
	489	if (m_exram_control == 0x02) // Mode 2 = write data
490	490	m_exram[offset - 0x1c00] = data;
491		else if (m_exram_control != 0x03) // Modes 0,1 = write data in frame / write 0 otherwise
	491	else if (m_exram_control != 0x03) // Modes 0,1 = write data in frame / write 0 otherwise
492	492	{
493	493	if (m_irq_status & 0x40)
494	494	m_exram[offset - 0x1c00] = data;
r29404	r29405
554	554	case 0x1116:
555	555	case 0x1117:
556	556	m_prg_regs[offset & 3] = data & 0x7f;
557		m_prg_ram_mapped[offset & 3] = !BIT(data, 7); // m_prg_ram_mapped[3] is not used, in fact!
	557	m_prg_ram_mapped[offset & 3] = !BIT(data, 7); // m_prg_ram_mapped[3] is not used, in fact!
558	558	update_prg();
559	559	break;
560	560

trunk/src/emu/bus/nes/nxrom.c
r29404	r29405
283	283	-------------------------------------------------*/
284	284
285	285	/*-------------------------------------------------
286
	286
287	287	NROM-368 board emulation
288
	288
289	289	iNES: mapper 0 with 3xPRG banks
290	290	This is an homebrew extension to map linearly 46KB
291	291	or PRG in boards with no PRG bankswitch logic
292
	292
293	293	In MESS: Supported
294
	294
295	295	-------------------------------------------------*/
296	296
297	297	READ8_MEMBER(nes_nrom368_device::read_l)
r29404	r29405
425	425	// For most boards, chr_open_bus remains always zero.
426	426	if (m_chr_open_bus)
427	427	return m_open_bus;
428
	428
429	429	return m_chr_access[bank][offset & 0x3ff];
430	430	}
431	431
r29404	r29405
549	549	}
550	550
551	551	/*-------------------------------------------------
552
	552
553	553	NoCash NOCHR board emulation
554
	554
555	555	This is an homebrew PCB design on a single chip
556	556	(+possibly CIC) which uses the NTRAM as CHRRAM!
557
	557
558	558	iNES: mapper 218
559
	559
560	560	In MESS: Supported.
561
	561
562	562	-------------------------------------------------*/
563	563
564	564	WRITE8_MEMBER(nes_nochr_device::chr_w)
r29404	r29405
569	569	else if (mirr == PPU_MIRROR_LOW)
570	570	m_ciram[(offset & 0x3ff) + 0x400] = data;
571	571	else
572		m_ciram[offset & 0x7ff] = data; // not sure here, since there is no software to test...
	572	m_ciram[offset & 0x7ff] = data; // not sure here, since there is no software to test...
573	573	}
574	574
575	575	READ8_MEMBER(nes_nochr_device::chr_r)
r29404	r29405
580	580	else if (mirr == PPU_MIRROR_LOW)
581	581	return m_ciram[(offset & 0x3ff) + 0x400];
582	582	else
583		return m_ciram[offset & 0x7ff]; // not sure here, since there is no software to test...
	583	return m_ciram[offset & 0x7ff]; // not sure here, since there is no software to test...
584	584	}

trunk/src/emu/bus/nes/karastudio.c
r29404	r29405
8	8
9	9
10	10	Here we emulate the following PCBs Bandai Karaoke Studio [mapper 188]
11
	11
12	12	The Karaoke Studio cart consist of a large connector which fits the FC cart slot, with a microphone
13		connected. The game data is in the connector itself. The microphone has two buttons on it, and the
14		game uses these only to navigate through the menus (the two buttons are not read through the controller
15		port, which is not accessible from the cart, but from $6000-$7fff). Part of the connector body can be
	13	connected. The game data is in the connector itself. The microphone has two buttons on it, and the
	14	game uses these only to navigate through the menus (the two buttons are not read through the controller
	15	port, which is not accessible from the cart, but from $6000-$7fff). Part of the connector body can be
16	16	removed to be replaced by an expansion cart containing new songs (we emulate this by adding a -cart2 slot).
17	17
18
	18
19	19	TODO:
20	20	- verify expansion slot emulation for the Senyou Cassettes:
21	21	not much documentation exists about the expansion carts (except for few paragraphs
22	22	at Enri's FC webpage), so I implemented it based on "common sense"
23	23	* expansion carts do not contain the required game data => main PRG must be in the main cart
24		so to remain connected even when an expansion is inserted (differently from Datach, where
	24	so to remain connected even when an expansion is inserted (differently from Datach, where
25	25	the base unit contains no PRG)
26		* bankswicth writes with bit3=0 (to access expansion) when no expansion is present should do
	26	* bankswicth writes with bit3=0 (to access expansion) when no expansion is present should do
27	27	nothing
28	28
29	29	***********************************************************************************************************/
r29404	r29405
43	43
44	44	//-----------------------------------------
45	45	//
46		// Karaoke Studio Cartslot implementation
	46	// Karaoke Studio Cartslot implementation
47	47	//
48	48	//-----------------------------------------
49	49
r29404	r29405
93	93	{
94	94	if (m_cart)
95	95	return m_cart->read(space, offset, mem_mask);
96
	96
97	97	return 0xff;
98	98	}
99	99
r29404	r29405
102	102	if (m_cart)
103	103	{
104	104	UINT8 *ROM = m_cart->get_cart_base();
105
	105
106	106	if (!ROM)
107	107	return IMAGE_INIT_FAIL;
108
	108
109	109	// Existing exapnsion carts are all 128K, so we only load files of this size
110	110	if (software_entry() == NULL)
111	111	{
112	112	if (length() != 0x20000)
113	113	return IMAGE_INIT_FAIL;
114
115		fread(&ROM, 0x20000);
	114
	115	fread(&ROM, 0x20000);
116	116	}
117	117	else
118	118	{
119	119	if (get_software_region_length("rom") != 0x20000)
120	120	return IMAGE_INIT_FAIL;
121
	121
122	122	memcpy(ROM, get_software_region("rom"), 0x20000);
123	123	}
124	124	}
125
	125
126	126	return IMAGE_INIT_PASS;
127	127	}
128	128
r29404	r29405
141	141
142	142	//-----------------------------------------------
143	143	//
144		// Karaoke Studio Expansion cart implementation
	144	// Karaoke Studio Expansion cart implementation
145	145	//
146	146	//-----------------------------------------------
147	147
r29404	r29405
181	181
182	182	//------------------------------------------
183	183	//
184		// Karaoke Studio Base Cart implementation
	184	// Karaoke Studio Base Cart implementation
185	185	//
186	186	//------------------------------------------
187	187
r29404	r29405
220	220
221	221	Bandai Karaoke Studio board emulation
222	222
223		Games: Karaoke Studio + expansion carts with
	223	Games: Karaoke Studio + expansion carts with
224	224	additional songs
225	225
226	226	Note: we currently do not emulate properly the
r29404	r29405
260	260	// cart (when expansion is present, code keeps switching both from the expansion rom and from
261	261	// the main ROM)
262	262	// my guess is that writes with bit3=0 and no expansion just do nothing, but it shall be verified
263
	263
264	264	if (offset >= 04000)
265	265	{
266	266	if (BIT(data, 3))
r29404	r29405
268	268	m_exp_active = 0;
269	269	prg16_89ab(data & 7);
270	270	}
271		else // expansion cart
	271	else // expansion cart
272	272	{
273	273	m_exp_active = 1;
274	274	m_subslot->write_prg_bank(data & 7);
r29404	r29405
308	308	{
309	309	return MACHINE_CONFIG_NAME( karaoke_studio );
310	310	}
311

trunk/src/emu/bus/nes/mmc5.h
r29404	r29405
66	66	UINT8 m_prg_ram_mapped[4];
67	67
68	68	UINT8 m_ex1_bank;
69
	69
70	70	UINT8 m_high_chr; // $5130
71	71
72	72	UINT8 m_split_scr; // $5200

trunk/src/emu/bus/nes/karastudio.h
r29404	r29405
6	6
7	7	//-----------------------------------------
8	8	//
9		// Karaoke Studio Cartslot implementation
	9	// Karaoke Studio Cartslot implementation
10	10	//
11	11	//-----------------------------------------
12	12
r29404	r29405
18	18	// construction/destruction
19	19	kstudio_cart_interface(const machine_config &mconfig, device_t &device);
20	20	virtual ~kstudio_cart_interface();
21
	21
22	22	// reading and writing
23	23	virtual DECLARE_READ8_MEMBER(read);
24
	24
25	25	UINT8 *get_cart_base() { return m_rom; }
26	26	void write_prg_bank(UINT8 bank) { m_bank = bank; }
27
	27
28	28	protected:
29	29	// internal state
30	30	UINT8 *m_rom;
r29404	r29405
42	42	// construction/destruction
43	43	nes_kstudio_slot_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
44	44	virtual ~nes_kstudio_slot_device();
45
	45
46	46	// device-level overrides
47	47	virtual void device_start();
48	48	virtual void device_config_complete() { update_names(); }
49
	49
50	50	// image-level overrides
51	51	virtual bool call_load();
52	52	virtual bool call_softlist_load(software_list_device &swlist, const char swname, const rom_entry start_entry);
53
	53
54	54	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
55	55	virtual bool is_readable() const { return 1; }
56	56	virtual bool is_writeable() const { return 0; }
r29404	r29405
60	60	virtual const char *image_interface() const { return "ks_cart"; }
61	61	virtual const char *file_extensions() const { return "bin"; }
62	62	virtual const option_guide *create_option_guide() const { return NULL; }
63
	63
64	64	// slot interface overrides
65	65	virtual void get_default_card_software(astring &result);
66
	66
67	67	virtual DECLARE_READ8_MEMBER(read);
68	68	void write_prg_bank(UINT8 bank) { if (m_cart) m_cart->write_prg_bank(bank); }
69
	69
70	70	kstudio_cart_interface* m_cart;
71	71	};
72	72
r29404	r29405
81	81
82	82	//-----------------------------------------------
83	83	//
84		// Karaoke Studio Expansion cart implementation
	84	// Karaoke Studio Expansion cart implementation
85	85	//
86	86	//-----------------------------------------------
87	87
r29404	r29405
93	93	public:
94	94	// construction/destruction
95	95	nes_kstudio_rom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
96
	96
97	97	// optional information overrides
98	98	virtual const rom_entry *device_rom_region() const;
99	99	virtual UINT8* get_cart_base();
100
	100
101	101	protected:
102	102	// device-level overrides
103	103	virtual void device_start();
r29404	r29405
110	110
111	111	//-------------------------------------------
112	112	//
113		// Karaoke Studio Base Cart implementation
	113	// Karaoke Studio Base Cart implementation
114	114	//
115	115	//-------------------------------------------
116	116

trunk/src/emu/bus/nes/bandai.c
r29404	r29405
19	19	* Bandai Datach Joint ROM System [mapper 157] is emulated in a separate source file
20	20	to implement also the subslot, but the PCB is basically a Bandai LZ93D50 + 24C02 EEPROM
21	21	pcb with added barcode reader and subslot
22
	22
23	23	* Bandai Karaoke Studio [mapper 188] is emulated in a separate source file
24	24	to implement also the subslot and the mic inputs
25
26
	25
	26
27	27	TODO:
28	28	- investigate why EEPROM does not work
29	29	- add support to the PPU for the code necessary to Oeka Kids games (also needed by UNL-DANCE2000 PCB)

trunk/src/emu/bus/nes/nes_carts.c
r29404	r29405
127	127	SLOT_INTERFACE_INTERNAL("bf9093", NES_BF9093)
128	128	SLOT_INTERFACE_INTERNAL("bf9096", NES_BF9096)
129	129	SLOT_INTERFACE_INTERNAL("goldenfive", NES_GOLDEN5)
130		SLOT_INTERFACE_INTERNAL("ade", NES_ALADDIN)
	130	SLOT_INTERFACE_INTERNAL("ade", NES_ALADDIN)
131	131	SLOT_INTERFACE_INTERNAL("cne_decathl", NES_CNE_DECATHL)
132	132	SLOT_INTERFACE_INTERNAL("cne_fsb", NES_CNE_FSB)
133	133	SLOT_INTERFACE_INTERNAL("cne_shlz", NES_CNE_SHLZ)
r29404	r29405
354	354	//
355	355	SLOT_INTERFACE_INTERNAL("unknown", NES_NROM) // a few pirate dumps uses the wrong mapper...
356	356	SLOT_INTERFACE_END
357

trunk/src/emu/bus/nes/bandai.h
r29404	r29405
38	38	// construction/destruction
39	39	nes_fcg_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
40	40	nes_fcg_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
41
	41
42	42	// device-level overrides
43	43	virtual void device_start();
44	44	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
r29404	r29405
46	46	virtual DECLARE_WRITE8_MEMBER(write_m);
47	47
48	48	virtual void pcb_reset();
49
	49
50	50	protected:
51	51	UINT16 m_irq_count;
52	52	int m_irq_enable;
53
	53
54	54	static const device_timer_id TIMER_IRQ = 0;
55	55	emu_timer *irq_timer;
56	56	};

trunk/src/emu/bus/nes/datach.c
r29404	r29405
35	35
36	36	//--------------------------------
37	37	//
38		// Datach Cartslot implementation
	38	// Datach Cartslot implementation
39	39	//
40	40	//--------------------------------
41	41
r29404	r29405
55	55	}
56	56
57	57	READ8_MEMBER(datach_cart_interface::read)
58		{
	58	{
59	59	if (offset < 0x4000)
60	60	return m_rom[(m_bank * 0x4000) + (offset & 0x3fff)];
61	61	else
r29404	r29405
113	113	fread(&temp, length());
114	114	memcpy(ROM, temp + shift, 0x40000);
115	115
116		// double check that iNES files are really mapper 157
	116	// double check that iNES files are really mapper 157
117	117	// (or 16, since some older .nes files marked Datach as mapper 16)
118	118	if (length() == 0x40010)
119	119	{
r29404	r29405
153	153
154	154	//--------------------------------
155	155	//
156		// Datach Minicart implementation
	156	// Datach Minicart implementation
157	157	//
158	158	// Two kinds of PCB exist
159	159	// * ROM only, used by most games
r29404	r29405
221	221
222	222	//---------------------------------
223	223	//
224		// Datach Base Unit implementation
	224	// Datach Base Unit implementation
225	225	//
226	226	//---------------------------------
227	227
r29404	r29405
244	244	serial_timer = timer_alloc(TIMER_SERIAL);
245	245	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
246	246	serial_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1000));
247
	247
248	248	save_item(NAME(m_irq_enable));
249	249	save_item(NAME(m_irq_count));
250	250	save_item(NAME(m_datach_latch));
r29404	r29405
256	256	prg16_89ab(0);
257	257	prg16_cdef(m_prg_chunks - 1);
258	258	chr8(0, m_chr_source);
259
	259
260	260	m_irq_enable = 0;
261	261	m_irq_count = 0;
262	262	m_datach_latch = 0;
r29404	r29405
269	269	-------------------------------------------------*/
270	270
271	271	/*-------------------------------------------------
272
	272
273	273	Bandai LZ93D50 + Datach barcode reader emulation
274
	274
275	275	Games: Datach Games
276
	276
277	277	iNES: mappers 157
278
	278
279	279	In MESS: Supported
280
	280
281	281	TODO: Datach carts should actually be handled
282	282	separately! Original carts were minicarts to be
283	283	inserted in a smaller slot of the Barcode reader
284	284	FC cart. The Barcode reader acts as a passthrough
285	285	but it has no internal ROM (it does not work if
286	286	you don't have any minicart inserted)
287
288		TODO2: This class should be derived from the
	287
	288	TODO2: This class should be derived from the
289	289	LZ93D50 + X24C02 class, since the main board
290		has this EEPROM. Moreover, Datach - Battle Rush
	290	has this EEPROM. Moreover, Datach - Battle Rush
291	291	has a second X24C01 EEPROM that we don't emulate yet...
292
	292
293	293	-------------------------------------------------*/
294	294
295	295
r29404	r29405
318	318
319	319	if (m_subslot->m_cart)
320	320	return m_subslot->m_cart->read(space, offset, mem_mask);
321		else // this is "fake" in the sense that we fill CPU space with 0xff if no Datach cart is loaded
	321	else // this is "fake" in the sense that we fill CPU space with 0xff if no Datach cart is loaded
322	322	return hi_access_rom(offset);
323	323	}
324	324
325	325	WRITE8_MEMBER(nes_datach_device::write_h)
326	326	{
327	327	LOG_MMC(("Datach write_h, offset: %04x, data: %02x\n", offset, data));
328
	328
329	329	switch (offset & 0x0f)
330	330	{
331	331	case 0: case 1: case 2: case 3:
r29404	r29405
406	406	m_irq_count = 0xffff;
407	407	else
408	408	m_irq_count--;
409
	409
410	410	if (!m_irq_count)
411	411	{
412	412	machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, ASSERT_LINE);

trunk/src/emu/bus/nes/datach.h
r29404	r29405
7	7
8	8	//--------------------------------
9	9	//
10		// Datach Cartslot implementation
	10	// Datach Cartslot implementation
11	11	//
12	12	//--------------------------------
13	13
r29404	r29405
84	84
85	85	//--------------------------------
86	86	//
87		// Datach Minicart implementation
	87	// Datach Minicart implementation
88	88	//
89	89	//--------------------------------
90	90
r29404	r29405
127	127
128	128	//---------------------------------
129	129	//
130		// Datach Base Unit implementation
	130	// Datach Base Unit implementation
131	131	//
132	132	//---------------------------------
133	133
r29404	r29405
138	138	public:
139	139	// construction/destruction
140	140	nes_datach_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
141
	141
142	142	// device-level overrides
143	143	virtual void device_start();
144	144	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
r29404	r29405
146	146	virtual DECLARE_READ8_MEMBER(read_m);
147	147	virtual DECLARE_READ8_MEMBER(read_h);
148	148	virtual DECLARE_WRITE8_MEMBER(write_h);
149
	149
150	150	virtual void pcb_reset();
151
	151
152	152	protected:
153	153	UINT8 m_datach_latch;
154	154	required_device<i2cmem_device> m_i2cmem;
155		required_device<barcode_reader_device> m_reader;
	155	required_device<barcode_reader_device> m_reader;
156	156	required_device<nes_datach_slot_device> m_subslot;
157	157	UINT8 m_i2c_dir;
158	158	UINT8 m_i2c_in_use;
159
	159
160	160	static const device_timer_id TIMER_SERIAL = 1;
161	161	emu_timer *serial_timer;
162	162	};

trunk/src/emu/bus/nes/sunsoft_dcs.c
r29404	r29405
27	27
28	28	//-----------------------------------------------
29	29	//
30		// Nantettate!! Baseball Cartslot implementation
	30	// Nantettate!! Baseball Cartslot implementation
31	31	//
32	32	//-----------------------------------------------
33	33
r29404	r29405
119	119
120	120	//-----------------------------------------------
121	121	//
122		// Nantettate!! Baseball Minicart implementation
	122	// Nantettate!! Baseball Minicart implementation
123	123	//
124	124	//-----------------------------------------------
125	125
r29404	r29405
154	154
155	155	//------------------------------------------------
156	156	//
157		// Nantettate!! Baseball base cart implementation
158		// a.k.a. Sunsoft Dual Cassette System
	157	// Nantettate!! Baseball base cart implementation
	158	// a.k.a. Sunsoft Dual Cassette System
159	159	// (variant of Sunsoft-4 PCB)
160	160	//
161	161	//------------------------------------------------

trunk/src/emu/bus/nes/nes_slot.h
r29404	r29405
119	119	WAIXING_DQ8, WAIXING_FFV, WAIXING_WXZS2, SUPERGAME_LIONKING, SUPERGAME_BOOGERMAN,
120	120	KAY_BOARD, HOSENKAN_BOARD, NITRA_TDA, GOUDER_37017, NANJING_BOARD,
121	121	WHIRLWIND_2706,
122		NOCASH_NOCHR, // homebrew PCB design which uses NTRAM for CHRRAM
123		BTL_ACTION53, // homebrew PCB for homebrew multicarts
	122	NOCASH_NOCHR, // homebrew PCB design which uses NTRAM for CHRRAM
	123	BTL_ACTION53, // homebrew PCB for homebrew multicarts
124	124	/* FFE boards, for mappers 6, 8, 17 */
125	125	FFE3_BOARD, FFE4_BOARD, FFE8_BOARD, TEST_BOARD,
126	126	/* Unsupported (for place-holder boards, with no working emulation) & no-board (at init) */

trunk/src/emu/bus/nes/aladdin.c
r29404	r29405
31	31
32	32	//----------------------------------
33	33	//
34		// Aladdin Cartslot implementation
	34	// Aladdin Cartslot implementation
35	35	//
36	36	//----------------------------------
37	37
r29404	r29405
52	52	}
53	53
54	54	READ8_MEMBER(aladdin_cart_interface::read)
55		{
	55	{
56	56	if (offset < 0x4000)
57	57	return m_rom[(m_lobank * 0x4000) + (offset & 0x3fff)];
58	58	else
r29404	r29405
86	86	{
87	87	if (m_cart)
88	88	return m_cart->read(space, offset, mem_mask);
89
	89
90	90	return 0xff;
91	91	}
92	92
r29404	r29405
100	100
101	101	if (!ROM)
102	102	return IMAGE_INIT_FAIL;
103
	103
104	104	if (software_entry() == NULL)
105	105	{
106	106	if (length() != 0x20010 && length() != 0x40010)
107	107	return IMAGE_INIT_FAIL;
108
	108
109	109	UINT8 temp[0x40010];
110	110	size = length() - 0x10;
111	111	fread(&temp, length());
112	112	memcpy(ROM, temp + 0x10, size);
113
114		// double check that iNES files are really mapper 71 or 232
	113
	114	// double check that iNES files are really mapper 71 or 232
115	115	{
116	116	UINT8 mapper = (temp[6] & 0xf0) >> 4;
117	117	mapper \|= temp[7] & 0xf0;
r29404	r29405
123	123	{
124	124	if (get_software_region_length("rom") != 0x20000 && get_software_region_length("rom") != 0x40000)
125	125	return IMAGE_INIT_FAIL;
126
	126
127	127	size = get_software_region_length("rom");
128	128	memcpy(ROM, get_software_region("rom"), size);
129	129	}
130	130
131	131	m_cart->set_cart_size(size);
132	132	}
133
	133
134	134	return IMAGE_INIT_PASS;
135	135	}
136	136
r29404	r29405
149	149	UINT32 len = core_fsize(m_file);
150	150	dynamic_buffer rom(len);
151	151	UINT8 mapper;
152
	152
153	153	core_fread(m_file, rom, len);
154	154
155	155	mapper = (rom[6] & 0xf0) >> 4;
156	156	mapper \|= rom[7] & 0xf0;
157	157
158		// if (mapper == 71)
159		// slot_string = "algn";
	158	// if (mapper == 71)
	159	// slot_string = "algn";
160	160	if (mapper == 232)
161	161	slot_string = "algq";
162	162
163	163	clear();
164
	164
165	165	result.cpy(slot_string);
166	166	}
167	167	else
r29404	r29405
171	171
172	172	//----------------------------------
173	173	//
174		// Aladdin Minicart implementation
	174	// Aladdin Minicart implementation
175	175	//
176	176	//----------------------------------
177	177
r29404	r29405
262	262
263	263	//-----------------------------------------------
264	264	//
265		// Camerica/Codemasters Aladdin passthru
	265	// Camerica/Codemasters Aladdin passthru
266	266	// implementation
267	267	//
268	268	//-----------------------------------------------
r29404	r29405
295	295	/*-------------------------------------------------
296	296
297	297	Camerica/Codemasters Aladdin Deck Enhancer
298
	298
299	299	iNES: mapper 71 & 232
300	300
301	301	In MESS: Supported (but timing issues in some games)
r29404	r29405
307	307	LOG_MMC(("aladdin read_h, offset: %04x\n", offset));
308	308	// this shall be the proper code, but it's a bit slower, so we access directly the subcart below
309	309	//return m_subslot->read(space, offset, mem_mask);
310
	310
311	311	if (m_subslot->m_cart)
312	312	return m_subslot->m_cart->read(space, offset, mem_mask);
313		else // this is "fake" in the sense that we fill CPU space with 0xff if no Aladdin cart is loaded
	313	else // this is "fake" in the sense that we fill CPU space with 0xff if no Aladdin cart is loaded
314	314	return hi_access_rom(offset);
315	315	}
316	316

trunk/src/emu/bus/nes/sunsoft_dcs.h
r29404	r29405
6	6
7	7	//-----------------------------------------------
8	8	//
9		// Nantettate!! Baseball Cartslot implementation
	9	// Nantettate!! Baseball Cartslot implementation
10	10	//
11	11	//-----------------------------------------------
12	12
r29404	r29405
77	77
78	78	//-----------------------------------------------
79	79	//
80		// Nantettate!! Baseball Minicart implementation
	80	// Nantettate!! Baseball Minicart implementation
81	81	//
82	82	//-----------------------------------------------
83	83
r29404	r29405
106	106
107	107	//------------------------------------------------
108	108	//
109		// Nantettate!! Baseball base cart implementation
110		// a.k.a. Sunsoft Dual Cassette System
	109	// Nantettate!! Baseball base cart implementation
	110	// a.k.a. Sunsoft Dual Cassette System
111	111	// (variant of Sunsoft-4 PCB)
112	112	//
113	113	//------------------------------------------------

trunk/src/emu/bus/nes/aladdin.h
r29404	r29405
6	6
7	7	//----------------------------------
8	8	//
9		// Aladdin Cartslot implementation
	9	// Aladdin Cartslot implementation
10	10	//
11	11	//----------------------------------
12	12
r29404	r29405
18	18	// construction/destruction
19	19	aladdin_cart_interface(const machine_config &mconfig, device_t &device);
20	20	virtual ~aladdin_cart_interface();
21
	21
22	22	// reading and writing
23	23	virtual DECLARE_READ8_MEMBER(read);
24
	24
25	25	UINT8 *get_cart_base() { return m_rom; }
26	26	void set_cart_size(UINT32 size) { m_rom_size = size; m_rom_mask = (size / 0x4000) - 1; }
27	27	virtual void write_prg(UINT32 offset, UINT8 data) { }
28
	28
29	29	protected:
30	30	// internal state
31	31	UINT8 *m_rom;
r29404	r29405
43	43	// construction/destruction
44	44	nes_aladdin_slot_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
45	45	virtual ~nes_aladdin_slot_device();
46
	46
47	47	// device-level overrides
48	48	virtual void device_start();
49	49	virtual void device_config_complete() { update_names(); }
50
	50
51	51	// image-level overrides
52	52	virtual bool call_load();
53	53	virtual bool call_softlist_load(software_list_device &swlist, const char swname, const rom_entry start_entry);
54
	54
55	55	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
56	56	virtual bool is_readable() const { return 1; }
57	57	virtual bool is_writeable() const { return 0; }
r29404	r29405
61	61	virtual const char *image_interface() const { return "ade_cart"; }
62	62	virtual const char *file_extensions() const { return "nes,bin"; }
63	63	virtual const option_guide *create_option_guide() const { return NULL; }
64
	64
65	65	// slot interface overrides
66	66	virtual void get_default_card_software(astring &result);
67
	67
68	68	virtual DECLARE_READ8_MEMBER(read);
69	69	void write_prg(UINT32 offset, UINT8 data) { if (m_cart) m_cart->write_prg(offset, data); }
70
	70
71	71	aladdin_cart_interface* m_cart;
72	72	};
73	73
r29404	r29405
82	82
83	83	//----------------------------------
84	84	//
85		// Aladdin Minicart implementation
	85	// Aladdin Minicart implementation
86	86	//
87	87	//----------------------------------
88	88
r29404	r29405
95	95	// construction/destruction
96	96	nes_algn_rom_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
97	97	nes_algn_rom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
98
	98
99	99	// optional information overrides
100	100	virtual const rom_entry *device_rom_region() const;
101	101	virtual UINT8* get_cart_base();
102	102	virtual void write_prg(UINT32 offset, UINT8 data);
103
	103
104	104	protected:
105	105	// device-level overrides
106	106	virtual void device_start();
r29404	r29405
115	115	public:
116	116	// construction/destruction
117	117	nes_algq_rom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
118
	118
119	119	// optional information overrides
120	120	virtual void write_prg(UINT32 offset, UINT8 data);
121	121
r29404	r29405
134	134
135	135	//-----------------------------------------------
136	136	//
137		// Codemasters Aladdin passthru implementation
	137	// Codemasters Aladdin passthru implementation
138	138	//
139	139	//-----------------------------------------------
140	140

trunk/src/emu/bus/nes/jy.c
r29404	r29405
310	310	prg32((last & 0x0f) \| (exPrg >> 2));
311	311	m_bank_6000 = (((m_mmc_prg_bank[3] * 4) + 3) & 0x3f) \| (exPrg >> 2);
312	312	break;
313
	313
314	314	case 1: // 16KB
315	315	prg16_89ab((m_mmc_prg_bank[1] & 0x1f) \| (exPrg >> 1));
316	316	prg16_cdef((last & 0x1f) \| (exPrg >> 1));
317	317	m_bank_6000 = (((m_mmc_prg_bank[3] * 2) + 1) & 0x1f) \| (exPrg >> 1);
318	318	break;
319
	319
320	320	case 2: // 8KB
321	321	prg8_89(m_mmc_prg_bank[0] \| exPrg);
322	322	prg8_ab(m_mmc_prg_bank[1] \| exPrg);
r29404	r29405
324	324	prg8_ef(last \| exPrg);
325	325	m_bank_6000 = m_mmc_prg_bank[3] \| exPrg;
326	326	break;
327
	327
328	328	case 3: // 8KB Alt
329	329	prg8_89((unscramble(m_mmc_prg_bank[0]) & 0x3f) \| exPrg);
330	330	prg8_ab((unscramble(m_mmc_prg_bank[1]) & 0x3f) \| exPrg);
r29404	r29405
347	347	// Block mode enabled: in this case lower bits select a 256KB page inside CHRROM
348	348	// and the low bytes of m_mmc_vrom_bank select the banks inside such a page
349	349
350		// docs suggest m_reg[3] & 0x1f for chr_page below,
	350	// docs suggest m_reg[3] & 0x1f for chr_page below,
351	351	// but 45 in 1 (JY-120A) menu requires to use this (from NEStopia)
352		UINT8 chr_page = (m_reg[3] & 1) \| ((m_reg[3] & 0x18) >> 2);
	352	UINT8 chr_page = (m_reg[3] & 1) \| ((m_reg[3] & 0x18) >> 2);
353	353	UINT32 extra_chr_base = BIT(m_reg[3], 5) ? 0 : (chr_page * 0x100);
354	354	UINT32 extra_chr_mask = BIT(m_reg[3], 5) ? 0xffffff : 0xff;
355
	355
356	356	switch (m_reg[0] & 0x18)
357	357	{
358	358	case 0x00: // 8KB
r29404	r29405
360	360	extra_chr_mask >>= 3;
361	361	chr8(extra_chr_base \| (m_mmc_vrom_bank[0] & extra_chr_mask), m_chr_source);
362	362	break;
363
	363
364	364	case 0x08: // 4KB
365	365	extra_chr_base >>= 2;
366	366	extra_chr_mask >>= 2;
r29404	r29405
369	369	chr4_0(extra_chr_base \| (m_mmc_vrom_bank[m_chr_latch[0]] & extra_chr_mask), m_chr_source);
370	370	chr4_4(extra_chr_base \| (m_mmc_vrom_bank[m_chr_latch[1]] & extra_chr_mask), m_chr_source);
371	371	break;
372
	372
373	373	case 0x10: // 2KB
374	374	extra_chr_base >>= 1;
375	375	extra_chr_mask >>= 1;
r29404	r29405
378	378	chr2_4(extra_chr_base \| (m_mmc_vrom_bank[4] & extra_chr_mask), m_chr_source);
379	379	chr2_6(extra_chr_base \| (m_mmc_vrom_bank[6] & extra_chr_mask), m_chr_source);
380	380	break;
381
	381
382	382	case 0x18: // 1KB
383	383	chr1_0(extra_chr_base \| (m_mmc_vrom_bank[0] & extra_chr_mask), m_chr_source);
384	384	chr1_1(extra_chr_base \| (m_mmc_vrom_bank[1] & extra_chr_mask), m_chr_source);
r29404	r29405
573	573	READ8_MEMBER(nes_jy_typec_device::chr_r)
574	574	{
575	575	int bank = offset >> 10;
576
	576
577	577	irq_clock(0, 2);
578	578	switch (offset & 0xff0)
579	579	{

trunk/src/emu/bus/nes/jy.h
r29404	r29405
20	20	virtual DECLARE_READ8_MEMBER(read_m);
21	21	virtual DECLARE_WRITE8_MEMBER(write_l);
22	22	virtual DECLARE_WRITE8_MEMBER(write_h);
23
	23
24	24	virtual DECLARE_READ8_MEMBER(chr_r);
25	25	virtual DECLARE_READ8_MEMBER(nt_r);
26	26
r29404	r29405
39	39	UINT8 m_mul[2];
40	40	UINT8 m_latch;
41	41	UINT8 m_reg[4];
42		UINT8 m_chr_latch[2]; // type C uses a more complex CHR 4K mode, and these vars are only changed for those games
	42	UINT8 m_chr_latch[2]; // type C uses a more complex CHR 4K mode, and these vars are only changed for those games
43	43	UINT8 m_mmc_prg_bank[4];
44	44	UINT16 m_mmc_nt_bank[4];
45	45	UINT16 m_mmc_vrom_bank[8];

trunk/src/emu/render.c
r29404	r29405
1212	1212
1213	1213	// get visible area
1214	1214	rectangle visarea = (screen->screen_type() == SCREEN_TYPE_VECTOR)
1215		? rectangle(0, 639, 0, 479) // use a hard-coded default visible area for vector screens
	1215	? rectangle(0, 639, 0, 479) // use a hard-coded default visible area for vector screens
1216	1216	: screen->visible_area();
1217	1217
1218	1218	// is our visible area too small? if so, we need to bump up the size

trunk/src/emu/emupal.c
r29404	r29405
87	87
88	88
89	89	//**************************************************************************
90		// INDIRECTION (AKA COLORTABLES)
	90	// INDIRECTION (AKA COLORTABLES)
91	91	//**************************************************************************
92	92
93	93	//-------------------------------------------------
r29404	r29405
132	132
133	133	//-------------------------------------------------
134	134	// transpen_mask - return a mask of pens that
135		// whose indirect values match the given
	135	// whose indirect values match the given
136	136	// transcolor
137	137	//-------------------------------------------------
138	138
r29404	r29405
160	160
161	161	//-------------------------------------------------
162	162	// configure_tilemap_groups - configure groups
163		// within a tilemap to match the indirect masks
	163	// within a tilemap to match the indirect masks
164	164	//-------------------------------------------------
165	165
166	166	void palette_device::configure_tilemap_groups(tilemap_t &tmap, gfx_element &gfx, int transcolor)
r29404	r29405
227	227	//-------------------------------------------------
228	228
229	229	//-------------------------------------------------
230		// set_shadow_dRGB32 - configure delta RGB values
	230	// set_shadow_dRGB32 - configure delta RGB values
231	231	// for 1 of 4 shadow tables
232	232	//-------------------------------------------------
233	233
r29404	r29405
269	269	g = rgb_t::clamp(g);
270	270	b = rgb_t::clamp(b);
271	271	}
272		rgb_t final = rgb_t(r, g, b);
	272	rgb_t final = rgb_t(r, g, b);
273	273
274	274	// store either 16 or 32 bit
275	275	if (m_format == BITMAP_FORMAT_RGB32)
r29404	r29405
282	282
283	283
284	284	//**************************************************************************
285		// GENERIC WRITE HANDLERS
	285	// GENERIC WRITE HANDLERS
286	286	//**************************************************************************
287	287
288	288	//-------------------------------------------------
289	289	// update_for_write - given a write of a given
290		// length to a given byte offset, update all
291		// potentially modified palette entries
	290	// length to a given byte offset, update all
	291	// potentially modified palette entries
292	292	//-------------------------------------------------
293	293
294	294	inline void palette_device::update_for_write(offs_t byte_offset, int bytes_modified)
r29404	r29405
319	319	m_paletteram.write8(offset, data);
320	320	update_for_write(offset, 1);
321	321	}
322
	322
323	323	WRITE16_MEMBER(palette_device::write)
324	324	{
325	325	m_paletteram.write16(offset, data, mem_mask);
r29404	r29405
349	349
350	350
351	351	//-------------------------------------------------
352		// write_ext - write a byte to the extended
	352	// write_ext - write a byte to the extended
353	353	// paletteram
354	354	//-------------------------------------------------
355	355
r29404	r29405
369	369
370	370
371	371	//**************************************************************************
372		// DEVICE MANAGEMENT
	372	// DEVICE MANAGEMENT
373	373	//**************************************************************************
374	374
375	375	//-------------------------------------------------
r29404	r29405
379	379	void palette_device::device_start()
380	380	{
381	381	// bind the init function
382		m_init.bind_relative_to(*owner());
	382	m_init.bind_relative_to(*owner());
383	383
384	384	// find the memory, if present
385	385	const memory_share *share = memshare(tag());
r29404	r29405
401	401	m_paletteram.set(*share, bytes_per_entry / 2);
402	402	m_paletteram_ext.set(*share_ext, bytes_per_entry / 2);
403	403	}
404
	404
405	405	// override endianness if provided
406	406	if (m_endianness_supplied)
407	407	{
r29404	r29405
421	421	allocate_palette();
422	422	allocate_color_tables();
423	423	allocate_shadow_tables();
424
	424
425	425	// allocate indirection tables
426	426	if (m_indirect_entries > 0)
427	427	{
r29404	r29405
447	447	m_save_contrast.resize(m_palette->num_colors());
448	448	save_item(NAME(m_save_pen));
449	449	save_item(NAME(m_save_contrast));
450
	450
451	451	// save indirection tables if we have them
452	452	if (m_indirect_entries > 0)
453	453	{
r29404	r29405
510	510
511	511	//-------------------------------------------------
512	512	// device_validity_check - validate device
513		// configuration
	513	// configuration
514	514	//-------------------------------------------------
515	515
516	516	void palette_device::device_validity_check(validity_checker &valid) const

trunk/src/emu/validity.c
r29404	r29405
966	966	void validity_checker::validate_devices()
967	967	{
968	968	int_map device_map;
969
	969
970	970	device_iterator iter_find(m_current_config->root_device());
971	971	for (const device_t *device = iter_find.first(); device != NULL; device = iter_find.next())
972	972	{

trunk/src/emu/clifront.h
r29404	r29405
114	114	cli_options & m_options;
115	115	osd_interface & m_osd;
116	116	int m_result;
117		UINT64 m_start_memory;
	117	UINT64 m_start_memory;
118	118	};
119	119
120	120

trunk/src/emu/emupal.h
r29404	r29405
159	159
160	160	#define MCFG_PALETTE_ADD(_tag, _entries) \
161	161	MCFG_DEVICE_ADD(_tag, PALETTE, 0) \
162		MCFG_PALETTE_ENTRIES(_entries) \
163
	162	MCFG_PALETTE_ENTRIES(_entries)
164	163	#define MCFG_PALETTE_ADD_INIT_BLACK(_tag, _entries) \
165	164	MCFG_PALETTE_ADD(_tag, _entries) \
166	165	palette_device::static_set_init(device, palette_init_delegate(FUNC(palette_device::palette_init_all_black), downcast<palette_device >(device)));
r29404	r29405
262	261	// constructor
263	262	raw_to_rgb_converter(int bytes_per_entry = 0, raw_to_rgb_func func = NULL)
264	263	: m_bytes_per_entry(bytes_per_entry),
265		m_func(func) { }
266
	264	m_func(func) { }
	265
267	266	// getters
268	267	int bytes_per_entry() const { return m_bytes_per_entry; }
269
	268
270	269	// helpers
271	270	rgb_t operator()(UINT32 raw) const { return (*m_func)(raw); }
272	271
r29404	r29405
297	296	UINT8 b = pal4bit(((raw >> 4) & 0x0c) \| i);
298	297	return rgb_t(r, g, b);
299	298	}
300
	299
301	300	// other standard decoders
302		static rgb_t RRRRGGGGBBBBRGBx_decoder(UINT32 raw); // bits 3/2/1 are LSb
303		static rgb_t xRGBRRRRGGGGBBBB_decoder(UINT32 raw); // bits 14/13/12 are LSb
	301	static rgb_t RRRRGGGGBBBBRGBx_decoder(UINT32 raw); // bits 3/2/1 are LSb
	302	static rgb_t xRGBRRRRGGGGBBBB_decoder(UINT32 raw); // bits 14/13/12 are LSb
304	303
305	304	private:
306	305	// internal data
307		int m_bytes_per_entry;
308		raw_to_rgb_func m_func;
	306	int m_bytes_per_entry;
	307	raw_to_rgb_func m_func;
309	308	};
310	309
311	310
r29404	r29405
314	313	// device type definition
315	314	extern const device_type PALETTE;
316	315
317		class palette_device : public device_t
	316	class palette_device : public device_t
318	317	{
319	318	static const int MAX_SHADOW_PRESETS = 4;
320	319
r29404	r29405
330	329	static void static_set_indirect_entries(device_t &device, int entries);
331	330	static void static_enable_shadows(device_t &device);
332	331	static void static_enable_hilights(device_t &device);
333
	332
334	333	// getters
335	334	int entries() const { return m_entries; }
336	335	int indirect_entries() const { return m_indirect_entries; }
r29404	r29405
339	338	const pen_t *pens() const { return m_pens; }
340	339	pen_t *shadow_table() const { return m_shadow_table; }
341	340	rgb_t pen_color(pen_t pen) { return m_palette->entry_color(pen); }
342		double pen_contrast(pen_t pen) { return m_palette->entry_contrast(pen); }
	341	double pen_contrast(pen_t pen) { return m_palette->entry_contrast(pen); }
343	342	pen_t black_pen() const { return m_black_pen; }
344	343	pen_t white_pen() const { return m_white_pen; }
345	344	memory_array &basemem() { return m_paletteram; }
r29404	r29405
365	364	void set_shadow_factor(double factor) { assert(m_shadow_group != 0); m_palette->group_set_contrast(m_shadow_group, factor); }
366	365	void set_highlight_factor(double factor) { assert(m_hilight_group != 0); m_palette->group_set_contrast(m_hilight_group, factor); }
367	366	void set_shadow_mode(int mode) { assert(mode >= 0 && mode < MAX_SHADOW_PRESETS); m_shadow_table = m_shadow_tables[mode].base; }
368
	367
369	368	// generic read/write handlers
370	369	DECLARE_READ8_MEMBER(read);
371	370	DECLARE_WRITE8_MEMBER(write);
r29404	r29405
388	387	void palette_init_RRRRRGGGGGBBBBB(palette_device &palette);
389	388	void palette_init_BBBBBGGGGGRRRRR(palette_device &palette);
390	389	void palette_init_RRRRRGGGGGGBBBBB(palette_device &palette);
391
	390
392	391	// helper to update palette when data changed
393	392	void update() { if (!m_init.isnull()) m_init(*this); }
394	393	protected:
r29404	r29405
402	401	void allocate_palette();
403	402	void allocate_color_tables();
404	403	void allocate_shadow_tables();
405
	404
406	405	void update_for_write(offs_t byte_offset, int bytes_modified);
407		public: // needed by konamigx
	406	public: // needed by konamigx
408	407	void set_shadow_dRGB32(int mode, int dr, int dg, int db, bool noclip);
409	408	protected:
410	409	void configure_rgb_shadows(int mode, float factor);
411
	410
412	411	private:
413	412	// configuration state
414		int m_entries; // number of entries in the palette
415		int m_indirect_entries; // number of indirect colors in the palette
416		bool m_enable_shadows; // are shadows enabled?
417		bool m_enable_hilights; // are hilights enabled?
418		endianness_t m_endianness; // endianness of palette RAM
419		bool m_endianness_supplied; // endianness supplied in static config
	413	int m_entries; // number of entries in the palette
	414	int m_indirect_entries; // number of indirect colors in the palette
	415	bool m_enable_shadows; // are shadows enabled?
	416	bool m_enable_hilights; // are hilights enabled?
	417	endianness_t m_endianness; // endianness of palette RAM
	418	bool m_endianness_supplied; // endianness supplied in static config
420	419
421	420	// palette RAM
422		raw_to_rgb_converter m_raw_to_rgb; // format of palette RAM
423		memory_array m_paletteram; // base memory
424		memory_array m_paletteram_ext; // extended memory
	421	raw_to_rgb_converter m_raw_to_rgb; // format of palette RAM
	422	memory_array m_paletteram; // base memory
	423	memory_array m_paletteram_ext; // extended memory
425	424
426	425	// internal state
427		palette_t * m_palette; // the palette itself
428		const pen_t * m_pens; // remapped palette pen numbers
429		bitmap_format m_format; // format assumed for palette data
430		pen_t * m_shadow_table; // table for looking up a shadowed pen
431		UINT32 m_shadow_group; // index of the shadow group, or 0 if none
432		UINT32 m_hilight_group; // index of the hilight group, or 0 if none
433		pen_t m_white_pen; // precomputed white pen value
434		pen_t m_black_pen; // precomputed black pen value
435
	426	palette_t * m_palette; // the palette itself
	427	const pen_t * m_pens; // remapped palette pen numbers
	428	bitmap_format m_format; // format assumed for palette data
	429	pen_t * m_shadow_table; // table for looking up a shadowed pen
	430	UINT32 m_shadow_group; // index of the shadow group, or 0 if none
	431	UINT32 m_hilight_group; // index of the hilight group, or 0 if none
	432	pen_t m_white_pen; // precomputed white pen value
	433	pen_t m_black_pen; // precomputed black pen value
	434
436	435	// indirection state
437		dynamic_array<rgb_t> m_indirect_colors; // actual colors set for indirection
438		dynamic_array<UINT16> m_indirect_pens; // indirection values
	436	dynamic_array<rgb_t> m_indirect_colors; // actual colors set for indirection
	437	dynamic_array<UINT16> m_indirect_pens; // indirection values
439	438
440	439	struct shadow_table_data
441	440	{
r29404	r29405
449	448
450	449	dynamic_array<pen_t> m_save_pen; // pens for save/restore
451	450	dynamic_array<float> m_save_contrast; // brightness for save/restore
452
	451
453	452	dynamic_array<pen_t> m_pen_array;
454	453	dynamic_array<pen_t> m_shadow_array;
455	454	dynamic_array<pen_t> m_hilight_array;

trunk/src/emu/validity.h
r29404	r29405
47	47	// helpers for devices
48	48	void validate_tag(const char *tag);
49	49	int region_length(const char *tag) { return m_region_map.find(tag); }
50
	50
51	51	// generic registry of already-checked stuff
52	52	bool already_checked(const char *string) { return (m_already_checked.add(string, 1, false) == TMERR_DUPLICATE); }
53
	53
54	54	private:
55	55	// internal helpers
56	56	const char *ioport_string_from_index(UINT32 index);
r29404	r29405
99	99	const device_t * m_current_device;
100	100	const char * m_current_ioport;
101	101	int_map m_region_map;
102		tagmap_t<UINT8> m_already_checked;
	102	tagmap_t<UINT8> m_already_checked;
103	103
104	104	// callbacks
105	105	output_delegate m_saved_error_output;

trunk/src/emu/ui/menu.h
r29404	r29405
21	21	CONSTANTS
22	22	***************************************************************************/
23	23
24		// flags for menu items
	24	// flags for menu items
25	25	#define MENU_FLAG_LEFT_ARROW (1 << 0)
26	26	#define MENU_FLAG_RIGHT_ARROW (1 << 1)
27	27	#define MENU_FLAG_INVERT (1 << 2)
r29404	r29405
29	29	#define MENU_FLAG_REDTEXT (1 << 4)
30	30	#define MENU_FLAG_DISABLE (1 << 5)
31	31
32		// special menu item for separators
	32	// special menu item for separators
33	33	#define MENU_SEPARATOR_ITEM "---"
34	34
35		// flags to pass to ui_menu_process
	35	// flags to pass to ui_menu_process
36	36	#define UI_MENU_PROCESS_NOKEYS 1
37	37	#define UI_MENU_PROCESS_LR_REPEAT 2
38	38	#define UI_MENU_PROCESS_CUSTOM_ONLY 4
39	39
40		// options for ui_menu_reset
	40	// options for ui_menu_reset
41	41	enum ui_menu_reset_options
42	42	{
43	43	UI_MENU_RESET_SELECT_FIRST,
r29404	r29405
51	51	TYPE DEFINITIONS
52	52	***************************************************************************/
53	53
54		// menu-related events
	54	// menu-related events
55	55	struct ui_menu_event
56	56	{
57		void * itemref; // reference for the selected item
58		int iptkey; // one of the IPT_* values from inptport.h
59		unicode_char unichar; // unicode character if iptkey == IPT_SPECIAL
	57	void * itemref; // reference for the selected item
	58	int iptkey; // one of the IPT_* values from inptport.h
	59	unicode_char unichar; // unicode character if iptkey == IPT_SPECIAL
60	60	};
61	61
62	62	struct ui_menu_pool
63	63	{
64		ui_menu_pool * next; // chain to next one
65		UINT8 * top; // top of the pool
66		UINT8 * end; // end of the pool
	64	ui_menu_pool * next; // chain to next one
	65	UINT8 * top; // top of the pool
	66	UINT8 * end; // end of the pool
67	67	};
68	68
69	69
r29404	r29405
86	86
87	87	running_machine &machine() const { return m_machine; }
88	88
89		render_container * container; // render_container we render to
90		ui_menu_event menu_event; // the UI menu_event that occurred
91		ui_menu * parent; // pointer to parent menu
92		int resetpos; // reset position
93		void * resetref; // reset reference
94		int selected; // which item is selected
95		int hover; // which item is being hovered over
96		int visitems; // number of visible items
97		int numitems; // number of items in the menu
98		int allocitems; // allocated size of array
99		ui_menu_item * item; // pointer to array of items
100		float customtop; // amount of extra height to add at the top
101		float custombottom; // amount of extra height to add at the bottom
102		ui_menu_pool * pool; // list of memory pools
	89	render_container * container; // render_container we render to
	90	ui_menu_event menu_event; // the UI menu_event that occurred
	91	ui_menu * parent; // pointer to parent menu
	92	int resetpos; // reset position
	93	void * resetref; // reset reference
	94	int selected; // which item is selected
	95	int hover; // which item is being hovered over
	96	int visitems; // number of visible items
	97	int numitems; // number of items in the menu
	98	int allocitems; // allocated size of array
	99	ui_menu_item * item; // pointer to array of items
	100	float customtop; // amount of extra height to add at the top
	101	float custombottom; // amount of extra height to add at the bottom
	102	ui_menu_pool * pool; // list of memory pools
103	103
104		// free all items in the menu, and all memory allocated from the memory pool
	104	// free all items in the menu, and all memory allocated from the memory pool
105	105	void reset(ui_menu_reset_options options);
106	106
107		// returns true if the menu has any non-default items in it
	107	// returns true if the menu has any non-default items in it
108	108	bool populated();
109	109
110		// append a new item to the end of the menu
	110	// append a new item to the end of the menu
111	111	void item_append(const char text, const char subtext, UINT32 flags, void *ref);
112	112
113		// process a menu, drawing it and returning any interesting events
	113	// process a menu, drawing it and returning any interesting events
114	114	const ui_menu_event *process(UINT32 flags);
115	115
116		// configure the menu for custom rendering
	116	// configure the menu for custom rendering
117	117	virtual void custom_render(void *selectedref, float top, float bottom, float x, float y, float x2, float y2);
118	118
119		// allocate temporary memory from the menu's memory pool
	119	// allocate temporary memory from the menu's memory pool
120	120	void *m_pool_alloc(size_t size);
121	121
122		// make a temporary string copy in the menu's memory pool
	122	// make a temporary string copy in the menu's memory pool
123	123	const char pool_strdup(const char string);
124	124
125		// retrieves the index of the currently selected menu item
	125	// retrieves the index of the currently selected menu item
126	126	void *get_selection();
127	127
128		// changes the index of the currently selected menu item
	128	// changes the index of the currently selected menu item
129	129	void set_selection(void *selected_itemref);
130	130
131		// request the specific handling of the game selection main menu
	131	// request the specific handling of the game selection main menu
132	132	bool is_special_main_menu() const;
133	133	void set_special_main_menu(bool disable);
134	134
135		// Global initialization
	135	// Global initialization
136	136	static void init(running_machine &machine);
137	137	static void exit(running_machine &machine);
138	138
139		// reset the menus, clearing everything
	139	// reset the menus, clearing everything
140	140	static void stack_reset(running_machine &machine);
141	141
142		// push a new menu onto the stack
	142	// push a new menu onto the stack
143	143	static void stack_push(ui_menu *menu);
144	144
145		// pop a menu from the stack
	145	// pop a menu from the stack
146	146	static void stack_pop(running_machine &machine);
147	147
148		// test if one of the menus in the stack requires hide disable
	148	// test if one of the menus in the stack requires hide disable
149	149	static bool stack_has_special_main_menu();
150	150
151		// highlight
	151	// highlight
152	152	static void highlight(render_container *container, float x0, float y0, float x1, float y1, rgb_t bgcolor);
153	153
154		// draw arrow
	154	// draw arrow
155	155	static void draw_arrow(render_container *container, float x0, float y0, float x1, float y1, rgb_t fgcolor, UINT32 orientation);
156	156
157		// master handler
	157	// master handler
158	158	static UINT32 ui_handler(running_machine &machine, render_container *container, UINT32 state);
159	159
160		// Used by sliders
	160	// Used by sliders
161	161	void validate_selection(int scandir);
162	162	static ui_menu *menu_stack;
163	163
164	164	void do_handle();
165	165
166		// To be reimplemented in the menu subclass
	166	// To be reimplemented in the menu subclass
167	167	virtual void populate() = 0;
168	168
169		// To be reimplemented in the menu subclass
	169	// To be reimplemented in the menu subclass
170	170	virtual void handle() = 0;
171	171
172	172	private:
r29404	r29405
188	188	static void render_triangle(bitmap_argb32 &dest, bitmap_argb32 &source, const rectangle &sbounds, void *param);
189	189	};
190	190
191		#endif // __UI_MENU_H__
	191	#endif // __UI_MENU_H__

trunk/src/emu/ui/mainmenu.c
r29404	r29405
246	246	case BIOS_SELECTION:
247	247	ui_menu::stack_push(auto_alloc_clear(machine(), ui_menu_bios_selection(machine(), container)));
248	248	break;
249
	249
250	250	case BARCODE_READ:
251	251	ui_menu::stack_push(auto_alloc_clear(machine(), ui_menu_barcode_reader(machine(), container)));
252	252	break;
253
	253
254	254	default:
255	255	fatalerror("ui_menu_main::handle - unknown reference\n");
256	256	}

trunk/src/emu/ui/ui.c
r29404	r29405
40	40	LOCAL VARIABLES
41	41	***************************************************************************/
42	42
43		// list of natural keyboard keys that are not associated with UI_EVENT_CHARs
	43	// list of natural keyboard keys that are not associated with UI_EVENT_CHARs
44	44	static const input_item_id non_char_keys[] =
45	45	{
46	46	ITEM_ID_ESC,
r29404	r29405
88	88	GLOBAL VARIABLES
89	89	***************************************************************************/
90	90
91		// messagebox buffer
	91	// messagebox buffer
92	92	static astring messagebox_text;
93	93	static rgb_t messagebox_backcolor;
94	94
95		// slider info
	95	// slider info
96	96	static slider_state *slider_list;
97	97	static slider_state *slider_current;
98	98
r29404	r29405
101	101	FUNCTION PROTOTYPES
102	102	***************************************************************************/
103	103
104		// slider controls
	104	// slider controls
105	105	static slider_state slider_alloc(running_machine &machine, const char title, INT32 minval, INT32 defval, INT32 maxval, INT32 incval, slider_update update, void *arg);
106	106	static slider_state *slider_init(running_machine &machine);
107	107	static INT32 slider_volume(running_machine &machine, void arg, astring string, INT32 newval);
r29404	r29405
221	221	ui_manager::ui_manager(running_machine &machine)
222	222	: m_machine(machine)
223	223	{
224		// initialize the other UI bits
	224	// initialize the other UI bits
225	225	ui_menu::init(machine);
226	226	ui_gfx_init(machine);
227	227
228		// reset instance variables
	228	// reset instance variables
229	229	m_font = NULL;
230	230	m_handler_callback = NULL;
231	231	m_handler_param = 0;
r29404	r29405
245	245	// request a callback upon exiting
246	246	machine.add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(ui_manager::exit), this));
247	247
248		// retrieve options
	248	// retrieve options
249	249	m_use_natural_keyboard = machine.options().natural_keyboard();
250	250	bitmap_argb32 *ui_mouse_bitmap = auto_alloc(machine, bitmap_argb32(32, 32));
251	251	UINT32 *dst = &ui_mouse_bitmap->pix32(0);
r29404	r29405
265	265	machine().render().texture_free(m_mouse_arrow_texture);
266	266	m_mouse_arrow_texture = NULL;
267	267
268		// free the font
	268	// free the font
269	269	if (m_font != NULL)
270	270	{
271	271	machine().render().font_free(m_font);
r29404	r29405
280	280
281	281	void ui_manager::initialize(running_machine &machine)
282	282	{
283		// initialize the on-screen display system
	283	// initialize the on-screen display system
284	284	slider_list = slider_current = slider_init(machine);
285	285	}
286	286
r29404	r29405
712	712	if (curwidth > maxwidth)
713	713	maxwidth = curwidth;
714	714
715		// if opaque, add a black box
	715	// if opaque, add a black box
716	716	if (draw == DRAW_OPAQUE)
717	717	container->add_rect(curx, cury, curx + curwidth, cury + lineheight, bgcolor, PRIMFLAG_BLENDMODE(BLENDMODE_ALPHA));
718	718
r29404	r29405
1131	1131	// get cpu specific clock that takes internal multiplier/dividers into account
1132	1132	int clock = exec->device().clock();
1133	1133
1134		// count how many identical CPUs we have
	1134	// count how many identical CPUs we have
1135	1135	int count = 1;
1136	1136	const char *name = exec->device().name();
1137	1137	execute_interface_iterator execinneriter(machine().root_device());
r29404	r29405
1142	1142	count++;
1143	1143	}
1144	1144
1145		// if more than one, prepend a #x in front of the CPU name
	1145	// if more than one, prepend a #x in front of the CPU name
1146	1146	if (count > 1)
1147	1147	string.catprintf("%d" UTF8_MULTIPLY, count);
1148	1148	string.cat(name);
1149	1149
1150		// display clock in kHz or MHz
	1150	// display clock in kHz or MHz
1151	1151	if (clock >= 1000000)
1152	1152	string.catprintf(" %d.%06d" UTF8_NBSP "MHz\n", clock / 1000000, clock % 1000000);
1153	1153	else
1154	1154	string.catprintf(" %d.%03d" UTF8_NBSP "kHz\n", clock / 1000, clock % 1000);
1155	1155	}
1156	1156
1157		// loop over all sound chips
	1157	// loop over all sound chips
1158	1158	sound_interface_iterator snditer(machine().root_device());
1159	1159	tagmap_t<UINT8> soundtags;
1160	1160	bool found_sound = false;
r29404	r29405
1163	1163	if (soundtags.add(sound->device().tag(), 1, FALSE) == TMERR_DUPLICATE)
1164	1164	continue;
1165	1165
1166		// append the Sound: string
	1166	// append the Sound: string
1167	1167	if (!found_sound)
1168	1168	string.cat("\nSound:\n");
1169	1169	found_sound = true;
1170	1170
1171		// count how many identical sound chips we have
	1171	// count how many identical sound chips we have
1172	1172	int count = 1;
1173	1173	sound_interface_iterator sndinneriter(machine().root_device());
1174	1174	for (device_sound_interface *scan = sndinneriter.first(); scan != NULL; scan = sndinneriter.next())
r29404	r29405
1177	1177	if (soundtags.add(scan->device().tag(), 1, FALSE) != TMERR_DUPLICATE)
1178	1178	count++;
1179	1179	}
1180		// if more than one, prepend a #x in front of the CPU name
	1180	// if more than one, prepend a #x in front of the CPU name
1181	1181	if (count > 1)
1182	1182	string.catprintf("%d" UTF8_MULTIPLY, count);
1183	1183	string.cat(sound->device().name());
1184	1184
1185		// display clock in kHz or MHz
	1185	// display clock in kHz or MHz
1186	1186	int clock = sound->device().clock();
1187	1187	if (clock >= 1000000)
1188	1188	string.catprintf(" %d.%06d" UTF8_NBSP "MHz\n", clock / 1000000, clock % 1000000);
r29404	r29405
1192	1192	string.cat("\n");
1193	1193	}
1194	1194
1195		// display screen information
	1195	// display screen information
1196	1196	string.cat("\nVideo:\n");
1197	1197	screen_device_iterator scriter(machine().root_device());
1198	1198	int scrcount = scriter.count();
r29404	r29405
1250	1250
1251	1251	UINT32 ui_manager::handler_messagebox_ok(running_machine &machine, render_container *container, UINT32 state)
1252	1252	{
1253		// draw a standard message window
	1253	// draw a standard message window
1254	1254	machine.ui().draw_text_box(container, messagebox_text, JUSTIFY_LEFT, 0.5f, 0.5f, messagebox_backcolor);
1255	1255
1256		// an 'O' or left joystick kicks us to the next state
	1256	// an 'O' or left joystick kicks us to the next state
1257	1257	if (state == 0 && (machine.input().code_pressed_once(KEYCODE_O) \|\| ui_input_pressed(machine, IPT_UI_LEFT)))
1258	1258	state++;
1259	1259
1260		// a 'K' or right joystick exits the state
	1260	// a 'K' or right joystick exits the state
1261	1261	else if (state == 1 && (machine.input().code_pressed_once(KEYCODE_K) \|\| ui_input_pressed(machine, IPT_UI_RIGHT)))
1262	1262	state = UI_HANDLER_CANCEL;
1263	1263
1264		// if the user cancels, exit out completely
	1264	// if the user cancels, exit out completely
1265	1265	else if (ui_input_pressed(machine, IPT_UI_CANCEL))
1266	1266	{
1267	1267	machine.schedule_exit();
r29404	r29405
1280	1280
1281	1281	UINT32 ui_manager::handler_messagebox_anykey(running_machine &machine, render_container *container, UINT32 state)
1282	1282	{
1283		// draw a standard message window
	1283	// draw a standard message window
1284	1284	machine.ui().draw_text_box(container, messagebox_text, JUSTIFY_LEFT, 0.5f, 0.5f, messagebox_backcolor);
1285	1285
1286		// if the user cancels, exit out completely
	1286	// if the user cancels, exit out completely
1287	1287	if (ui_input_pressed(machine, IPT_UI_CANCEL))
1288	1288	{
1289	1289	machine.schedule_exit();
1290	1290	state = UI_HANDLER_CANCEL;
1291	1291	}
1292	1292
1293		// if any key is pressed, just exit
	1293	// if any key is pressed, just exit
1294	1294	else if (machine.input().poll_switches() != INPUT_CODE_INVALID)
1295	1295	state = UI_HANDLER_CANCEL;
1296	1296
r29404	r29405
1312	1312	UINT8 *key_down_ptr;
1313	1313	UINT8 key_down_mask;
1314	1314
1315		// loop while we have interesting events
	1315	// loop while we have interesting events
1316	1316	while (ui_input_pop_event(machine(), &event))
1317	1317	{
1318		// if this was a UI_EVENT_CHAR event, post it
	1318	// if this was a UI_EVENT_CHAR event, post it
1319	1319	if (event.event_type == UI_EVENT_CHAR)
1320	1320	machine().ioport().natkeyboard().post(event.ch);
1321	1321	}
1322	1322
1323		// process natural keyboard keys that don't get UI_EVENT_CHARs
	1323	// process natural keyboard keys that don't get UI_EVENT_CHARs
1324	1324	for (i = 0; i < ARRAY_LENGTH(non_char_keys); i++)
1325	1325	{
1326		// identify this keycode
	1326	// identify this keycode
1327	1327	itemid = non_char_keys[i];
1328	1328	code = machine().input().code_from_itemid(itemid);
1329	1329
1330		// ...and determine if it is pressed
	1330	// ...and determine if it is pressed
1331	1331	pressed = machine().input().code_pressed(code);
1332	1332
1333		// figure out whey we are in the key_down map
	1333	// figure out whey we are in the key_down map
1334	1334	key_down_ptr = &m_non_char_keys_down[i / 8];
1335	1335	key_down_mask = 1 << (i % 8);
1336	1336
1337	1337	if (pressed && !(*key_down_ptr & key_down_mask))
1338	1338	{
1339		// this key is now down
	1339	// this key is now down
1340	1340	*key_down_ptr \|= key_down_mask;
1341	1341
1342		// post the key
	1342	// post the key
1343	1343	machine().ioport().natkeyboard().post(UCHAR_MAMEKEY_BEGIN + code.item_id());
1344	1344	}
1345	1345	else if (!pressed && (*key_down_ptr & key_down_mask))
1346	1346	{
1347		// this key is now up
	1347	// this key is now up
1348	1348	*key_down_ptr &= ~key_down_mask;
1349	1349	}
1350	1350	}
r29404	r29405
1357	1357
1358	1358	void ui_manager::increase_frameskip()
1359	1359	{
1360		// get the current value and increment it
	1360	// get the current value and increment it
1361	1361	int newframeskip = machine().video().frameskip() + 1;
1362	1362	if (newframeskip > MAX_FRAMESKIP)
1363	1363	newframeskip = -1;
1364	1364	machine().video().set_frameskip(newframeskip);
1365	1365
1366		// display the FPS counter for 2 seconds
	1366	// display the FPS counter for 2 seconds
1367	1367	machine().ui().show_fps_temp(2.0);
1368	1368	}
1369	1369
r29404	r29405
1374	1374
1375	1375	void ui_manager::decrease_frameskip()
1376	1376	{
1377		// get the current value and decrement it
	1377	// get the current value and decrement it
1378	1378	int newframeskip = machine().video().frameskip() - 1;
1379	1379	if (newframeskip < -1)
1380	1380	newframeskip = MAX_FRAMESKIP;
1381	1381	machine().video().set_frameskip(newframeskip);
1382	1382
1383		// display the FPS counter for 2 seconds
	1383	// display the FPS counter for 2 seconds
1384	1384	machine().ui().show_fps_temp(2.0);
1385	1385	}
1386	1386
r29404	r29405
1391	1391
1392	1392	bool ui_manager::can_paste()
1393	1393	{
1394		// retrieve the clipboard text
	1394	// retrieve the clipboard text
1395	1395	char *text = osd_get_clipboard_text();
1396	1396
1397	1397	// free the string if allocated
r29404	r29405
1409	1409
1410	1410	void ui_manager::paste()
1411	1411	{
1412		// retrieve the clipboard text
	1412	// retrieve the clipboard text
1413	1413	char *text = osd_get_clipboard_text();
1414	1414
1415		// was a result returned?
	1415	// was a result returned?
1416	1416	if (text != NULL)
1417	1417	{
1418		// post the text
	1418	// post the text
1419	1419	machine().ioport().natkeyboard().post_utf8(text);
1420	1420
1421		// free the string
	1421	// free the string
1422	1422	osd_free(text);
1423	1423	}
1424	1424	}
r29404	r29405
1431	1431
1432	1432	void ui_manager::image_handler_ingame()
1433	1433	{
1434		// run display routine for devices
	1434	// run display routine for devices
1435	1435	if (machine().phase() == MACHINE_PHASE_RUNNING)
1436	1436	{
1437	1437	image_interface_iterator iter(machine().root_device());
r29404	r29405
1450	1450	{
1451	1451	bool is_paused = machine.paused();
1452	1452
1453		// first draw the FPS counter
	1453	// first draw the FPS counter
1454	1454	if (machine.ui().show_fps_counter())
1455	1455	{
1456	1456	astring tempstring;
r29404	r29405
1458	1458	JUSTIFY_RIGHT, WRAP_WORD, DRAW_OPAQUE, ARGB_WHITE, ARGB_BLACK, NULL, NULL);
1459	1459	}
1460	1460
1461		// draw the profiler if visible
	1461	// draw the profiler if visible
1462	1462	if (machine.ui().show_profiler())
1463	1463	{
1464	1464	const char *text = g_profiler.text(machine);
1465	1465	machine.ui().draw_text_full(container, text, 0.0f, 0.0f, 1.0f, JUSTIFY_LEFT, WRAP_WORD, DRAW_OPAQUE, ARGB_WHITE, ARGB_BLACK, NULL, NULL);
1466	1466	}
1467	1467
1468		// if we're single-stepping, pause now
	1468	// if we're single-stepping, pause now
1469	1469	if (machine.ui().single_step())
1470	1470	{
1471	1471	machine.pause();
1472	1472	machine.ui().set_single_step(false);
1473	1473	}
1474	1474
1475		// determine if we should disable the rest of the UI
	1475	// determine if we should disable the rest of the UI
1476	1476	bool ui_disabled = (machine.ioport().has_keyboard() && !machine.ui_active());
1477	1477
1478		// is ScrLk UI toggling applicable here?
	1478	// is ScrLk UI toggling applicable here?
1479	1479	if (machine.ioport().has_keyboard())
1480	1480	{
1481		// are we toggling the UI with ScrLk?
	1481	// are we toggling the UI with ScrLk?
1482	1482	if (ui_input_pressed(machine, IPT_UI_TOGGLE_UI))
1483	1483	{
1484		// toggle the UI
	1484	// toggle the UI
1485	1485	machine.set_ui_active(!machine.ui_active());
1486	1486
1487		// display a popup indicating the new status
	1487	// display a popup indicating the new status
1488	1488	if (machine.ui_active())
1489	1489	{
1490	1490	machine.ui().popup_time(2, "%s\n%s\n%s\n%s\n%s\n%s\n",
r29404	r29405
1508	1508	}
1509	1509	}
1510	1510
1511		// is the natural keyboard enabled?
	1511	// is the natural keyboard enabled?
1512	1512	if (machine.ui().use_natural_keyboard() && (machine.phase() == MACHINE_PHASE_RUNNING))
1513	1513	machine.ui().process_natural_keyboard();
1514	1514
1515	1515	if (!ui_disabled)
1516	1516	{
1517		// paste command
	1517	// paste command
1518	1518	if (ui_input_pressed(machine, IPT_UI_PASTE))
1519	1519	machine.ui().paste();
1520	1520	}
r29404	r29405
1529	1529	return 0;
1530	1530	}
1531	1531
1532		// turn on menus if requested
	1532	// turn on menus if requested
1533	1533	if (ui_input_pressed(machine, IPT_UI_CONFIGURE))
1534	1534	return machine.ui().set_handler(ui_menu::ui_handler, 0);
1535	1535
1536		// if the on-screen display isn't up and the user has toggled it, turn it on
	1536	// if the on-screen display isn't up and the user has toggled it, turn it on
1537	1537	if ((machine.debug_flags & DEBUG_FLAG_ENABLED) == 0 && ui_input_pressed(machine, IPT_UI_ON_SCREEN_DISPLAY))
1538	1538	return machine.ui().set_handler(ui_menu_sliders::ui_handler, 1);
1539	1539
1540		// handle a reset request
	1540	// handle a reset request
1541	1541	if (ui_input_pressed(machine, IPT_UI_RESET_MACHINE))
1542	1542	machine.schedule_hard_reset();
1543	1543	if (ui_input_pressed(machine, IPT_UI_SOFT_RESET))
1544	1544	machine.schedule_soft_reset();
1545	1545
1546		// handle a request to display graphics/palette
	1546	// handle a request to display graphics/palette
1547	1547	if (ui_input_pressed(machine, IPT_UI_SHOW_GFX))
1548	1548	{
1549	1549	if (!is_paused)
r29404	r29405
1551	1551	return machine.ui().set_handler(ui_gfx_ui_handler, is_paused);
1552	1552	}
1553	1553
1554		// handle a save state request
	1554	// handle a save state request
1555	1555	if (ui_input_pressed(machine, IPT_UI_SAVE_STATE))
1556	1556	{
1557	1557	machine.pause();
1558	1558	return machine.ui().set_handler(handler_load_save, LOADSAVE_SAVE);
1559	1559	}
1560	1560
1561		// handle a load state request
	1561	// handle a load state request
1562	1562	if (ui_input_pressed(machine, IPT_UI_LOAD_STATE))
1563	1563	{
1564	1564	machine.pause();
1565	1565	return machine.ui().set_handler(handler_load_save, LOADSAVE_LOAD);
1566	1566	}
1567	1567
1568		// handle a save snapshot request
	1568	// handle a save snapshot request
1569	1569	if (ui_input_pressed(machine, IPT_UI_SNAPSHOT))
1570	1570	machine.video().save_active_screen_snapshots();
1571	1571
1572		// toggle pause
	1572	// toggle pause
1573	1573	if (ui_input_pressed(machine, IPT_UI_PAUSE))
1574	1574	{
1575		// with a shift key, it is single step
	1575	// with a shift key, it is single step
1576	1576	if (is_paused && (machine.input().code_pressed(KEYCODE_LSHIFT) \|\| machine.input().code_pressed(KEYCODE_RSHIFT)))
1577	1577	{
1578	1578	machine.ui().set_single_step(true);
r29404	r29405
1582	1582	machine.toggle_pause();
1583	1583	}
1584	1584
1585		// handle a toggle cheats request
	1585	// handle a toggle cheats request
1586	1586	if (ui_input_pressed(machine, IPT_UI_TOGGLE_CHEAT))
1587	1587	machine.cheat().set_enable(!machine.cheat().enabled());
1588	1588
1589		// toggle movie recording
	1589	// toggle movie recording
1590	1590	if (ui_input_pressed(machine, IPT_UI_RECORD_MOVIE))
1591	1591	machine.video().toggle_record_movie();
1592	1592
1593		// toggle profiler display
	1593	// toggle profiler display
1594	1594	if (ui_input_pressed(machine, IPT_UI_SHOW_PROFILER))
1595	1595	machine.ui().set_show_profiler(!machine.ui().show_profiler());
1596	1596
1597		// toggle FPS display
	1597	// toggle FPS display
1598	1598	if (ui_input_pressed(machine, IPT_UI_SHOW_FPS))
1599	1599	machine.ui().set_show_fps(!machine.ui().show_fps());
1600	1600
1601		// increment frameskip?
	1601	// increment frameskip?
1602	1602	if (ui_input_pressed(machine, IPT_UI_FRAMESKIP_INC))
1603	1603	machine.ui().increase_frameskip();
1604	1604
1605		// decrement frameskip?
	1605	// decrement frameskip?
1606	1606	if (ui_input_pressed(machine, IPT_UI_FRAMESKIP_DEC))
1607	1607	machine.ui().decrease_frameskip();
1608	1608
1609		// toggle throttle?
	1609	// toggle throttle?
1610	1610	if (ui_input_pressed(machine, IPT_UI_THROTTLE))
1611	1611	machine.video().toggle_throttle();
1612	1612
1613		// check for fast forward
	1613	// check for fast forward
1614	1614	if (machine.ioport().type_pressed(IPT_UI_FAST_FORWARD))
1615	1615	{
1616	1616	machine.video().set_fastforward(true);
r29404	r29405
1634	1634	input_code code;
1635	1635	char file = 0;
1636	1636
1637		// if we're not in the middle of anything, skip
	1637	// if we're not in the middle of anything, skip
1638	1638	if (state == LOADSAVE_NONE)
1639	1639	return 0;
1640	1640
1641		// okay, we're waiting for a key to select a slot; display a message
	1641	// okay, we're waiting for a key to select a slot; display a message
1642	1642	if (state == LOADSAVE_SAVE)
1643	1643	machine.ui().draw_message_window(container, "Select position to save to");
1644	1644	else
1645	1645	machine.ui().draw_message_window(container, "Select position to load from");
1646	1646
1647		// check for cancel key
	1647	// check for cancel key
1648	1648	if (ui_input_pressed(machine, IPT_UI_CANCEL))
1649	1649	{
1650		// display a popup indicating things were cancelled
	1650	// display a popup indicating things were cancelled
1651	1651	if (state == LOADSAVE_SAVE)
1652	1652	popmessage("Save cancelled");
1653	1653	else
1654	1654	popmessage("Load cancelled");
1655	1655
1656		// reset the state
	1656	// reset the state
1657	1657	machine.resume();
1658	1658	return UI_HANDLER_CANCEL;
1659	1659	}
1660	1660
1661		// check for A-Z or 0-9
	1661	// check for A-Z or 0-9
1662	1662	for (input_item_id id = ITEM_ID_A; id <= ITEM_ID_Z; id++)
1663	1663	if (machine.input().code_pressed_once(input_code(DEVICE_CLASS_KEYBOARD, 0, ITEM_CLASS_SWITCH, ITEM_MODIFIER_NONE, id)))
1664	1664	file = id - ITEM_ID_A + 'a';
r29404	r29405
1673	1673	if (file == 0)
1674	1674	return state;
1675	1675
1676		// display a popup indicating that the save will proceed
	1676	// display a popup indicating that the save will proceed
1677	1677	sprintf(filename, "%c", file);
1678	1678	if (state == LOADSAVE_SAVE)
1679	1679	{
r29404	r29405
1686	1686	machine.schedule_load(filename);
1687	1687	}
1688	1688
1689		// remove the pause and reset the state
	1689	// remove the pause and reset the state
1690	1690	machine.resume();
1691	1691	return UI_HANDLER_CANCEL;
1692	1692	}
r29404	r29405
1719	1719	machine.ui().draw_text_box(container, quit_message, JUSTIFY_CENTER, 0.5f, 0.5f, UI_RED_COLOR);
1720	1720	machine.pause();
1721	1721
1722		// if the user press ENTER, quit the game
	1722	// if the user press ENTER, quit the game
1723	1723	if (ui_input_pressed(machine, IPT_UI_SELECT))
1724	1724	machine.schedule_exit();
1725	1725
1726		// if the user press ESC, just continue
	1726	// if the user press ESC, just continue
1727	1727	else if (ui_input_pressed(machine, IPT_UI_CANCEL))
1728	1728	{
1729	1729	machine.resume();
r29404	r29405
1783	1783	astring string;
1784	1784	int item;
1785	1785
1786		// add overall volume
	1786	// add overall volume
1787	1787	*tailptr = slider_alloc(machine, "Master Volume", -32, 0, 0, 1, slider_volume, NULL);
1788	1788	tailptr = &(*tailptr)->next;
1789	1789
1790		// add per-channel volume
	1790	// add per-channel volume
1791	1791	mixer_input info;
1792	1792	for (item = 0; machine.sound().indexed_mixer_input(item, info); item++)
1793	1793	{
r29404	r29405
1800	1800	tailptr = &(*tailptr)->next;
1801	1801	}
1802	1802
1803		// add analog adjusters
	1803	// add analog adjusters
1804	1804	for (port = machine.ioport().first_port(); port != NULL; port = port->next())
1805	1805	for (field = port->first_field(); field != NULL; field = field->next())
1806	1806	if (field->type() == IPT_ADJUSTER)
r29404	r29405
1810	1810	tailptr = &(*tailptr)->next;
1811	1811	}
1812	1812
1813		// add CPU overclocking (cheat only)
	1813	// add CPU overclocking (cheat only)
1814	1814	if (machine.options().cheat())
1815	1815	{
1816	1816	execute_interface_iterator iter(machine.root_device());
r29404	r29405
1823	1823	}
1824	1824	}
1825	1825
1826		// add screen parameters
	1826	// add screen parameters
1827	1827	screen_device_iterator scriter(machine.root_device());
1828	1828	for (screen_device *screen = scriter.first(); screen != NULL; screen = scriter.next())
1829	1829	{
r29404	r29405
1833	1833	int defyoffset = floor(screen->yoffset() * 1000.0f + 0.5f);
1834	1834	void param = (void )screen;
1835	1835
1836		// add refresh rate tweaker
	1836	// add refresh rate tweaker
1837	1837	if (machine.options().cheat())
1838	1838	{
1839	1839	string.printf("%s Refresh Rate", slider_get_screen_desc(*screen));
r29404	r29405
1841	1841	tailptr = &(*tailptr)->next;
1842	1842	}
1843	1843
1844		// add standard brightness/contrast/gamma controls per-screen
	1844	// add standard brightness/contrast/gamma controls per-screen
1845	1845	string.printf("%s Brightness", slider_get_screen_desc(*screen));
1846	1846	*tailptr = slider_alloc(machine, string, 100, 1000, 2000, 10, slider_brightness, param);
1847	1847	tailptr = &(*tailptr)->next;
r29404	r29405
1852	1852	*tailptr = slider_alloc(machine, string, 100, 1000, 3000, 50, slider_gamma, param);
1853	1853	tailptr = &(*tailptr)->next;
1854	1854
1855		// add scale and offset controls per-screen
	1855	// add scale and offset controls per-screen
1856	1856	string.printf("%s Horiz Stretch", slider_get_screen_desc(*screen));
1857	1857	*tailptr = slider_alloc(machine, string, 500, defxscale, 1500, 2, slider_xscale, param);
1858	1858	tailptr = &(*tailptr)->next;
r29404	r29405
1879	1879	int defyoffset = floor(config.m_overposy * 1000.0f + 0.5f);
1880	1880	void param = (void )laserdisc;
1881	1881
1882		// add scale and offset controls per-overlay
	1882	// add scale and offset controls per-overlay
1883	1883	string.printf("Laserdisc '%s' Horiz Stretch", laserdisc->tag());
1884	1884	*tailptr = slider_alloc(machine, string, 500, (defxscale == 0) ? 1000 : defxscale, 1500, 2, slider_overxscale, param);
1885	1885	tailptr = &(*tailptr)->next;
r29404	r29405
1897	1897	for (screen_device *screen = scriter.first(); screen != NULL; screen = scriter.next())
1898	1898	if (screen->screen_type() == SCREEN_TYPE_VECTOR)
1899	1899	{
1900		// add flicker control
	1900	// add flicker control
1901	1901	*tailptr = slider_alloc(machine, "Vector Flicker", 0, 0, 1000, 10, slider_flicker, NULL);
1902	1902	tailptr = &(*tailptr)->next;
1903	1903	*tailptr = slider_alloc(machine, "Beam Width", 10, 100, 1000, 10, slider_beam, NULL);
r29404	r29405
1906	1906	}
1907	1907
1908	1908	#ifdef MAME_DEBUG
1909		// add crosshair adjusters
	1909	// add crosshair adjusters
1910	1910	for (port = machine.ioport().first_port(); port != NULL; port = port->next())
1911	1911	for (field = port->first_field(); field != NULL; field = field->next())
1912	1912	if (field->crosshair_axis() != CROSSHAIR_AXIS_NONE && field->player() == 0)

trunk/src/emu/ui/selgame.c
r29404	r29405
47	47
48	48
49	49	//-------------------------------------------------
50		// build_driver_list - build a list of available
51		// drivers
	50	// build_driver_list - build a list of available
	51	// drivers
52	52	//-------------------------------------------------
53	53
54	54	void ui_menu_select_game::build_driver_list()
r29404	r29405
108	108	m_error = false;
109	109
110	110	// handle selections
111		else
	111	else
112	112	{
113	113	switch(menu_event->iptkey)
114	114	{

trunk/src/emu/ui/imgcntrl.c
r29404	r29405
119	119	need_confirm = false;
120	120	break;
121	121	}
122
	122
123	123	if (entry != NULL)
124	124	osd_free(entry);
125	125	}

trunk/src/emu/ui/viewgfx.c
r29404	r29405
41	41	// information about a single gfx device
42	42	struct ui_gfx_info
43	43	{
44		device_gfx_interface *interface; // pointer to device's gfx interface
45		UINT8 setcount; // how many gfx sets device has
46		UINT8 rotate[MAX_GFX_ELEMENTS]; // current rotation (orientation) value
47		UINT8 columns[MAX_GFX_ELEMENTS]; // number of items per row
48		int offset[MAX_GFX_ELEMENTS]; // current offset of top,left item
49		int color[MAX_GFX_ELEMENTS]; // current color selected
	44	device_gfx_interface *interface; // pointer to device's gfx interface
	45	UINT8 setcount; // how many gfx sets device has
	46	UINT8 rotate[MAX_GFX_ELEMENTS]; // current rotation (orientation) value
	47	UINT8 columns[MAX_GFX_ELEMENTS]; // number of items per row
	48	int offset[MAX_GFX_ELEMENTS]; // current offset of top,left item
	49	int color[MAX_GFX_ELEMENTS]; // current color selected
50	50	};
51	51
52	52	struct ui_gfx_state
53	53	{
54		bool started; // have we called ui_gfx_count_devices() yet?
55		UINT8 mode; // which mode are we in?
	54	bool started; // have we called ui_gfx_count_devices() yet?
	55	UINT8 mode; // which mode are we in?
56	56
57	57	// intermediate bitmaps
58		bool bitmap_dirty; // is the bitmap dirty?
59		bitmap_rgb32 * bitmap; // bitmap for drawing gfx and tilemaps
60		render_texture *texture; // texture for rendering the above bitmap
	58	bool bitmap_dirty; // is the bitmap dirty?
	59	bitmap_rgb32 * bitmap; // bitmap for drawing gfx and tilemaps
	60	render_texture *texture; // texture for rendering the above bitmap
61	61
62	62	// palette-specific data
63	63	struct
64	64	{
65		palette_device *device; // pointer to current device
66		int devcount; // how many palette devices exist
67		int devindex; // which palette device is visible
68		UINT8 which; // which subset (pens or indirect colors)?
69		UINT8 columns; // number of items per row
70		int offset; // current offset of top left item
	65	palette_device *device; // pointer to current device
	66	int devcount; // how many palette devices exist
	67	int devindex; // which palette device is visible
	68	UINT8 which; // which subset (pens or indirect colors)?
	69	UINT8 columns; // number of items per row
	70	int offset; // current offset of top left item
71	71	} palette;
72	72
73	73	// graphics-specific data
74	74	struct
75	75	{
76		UINT8 devcount; // how many gfx devices exist
77		UINT8 devindex; // which device is visible
78		UINT8 set; // which set is visible
	76	UINT8 devcount; // how many gfx devices exist
	77	UINT8 devindex; // which device is visible
	78	UINT8 set; // which set is visible
79	79	} gfxset;
80
	80
81	81	// information about each gfx device
82	82	ui_gfx_info gfxdev[MAX_GFX_DECODERS];
83	83
84	84	// tilemap-specific data
85	85	struct
86	86	{
87		int which; // which tilemap are we viewing?
88		int xoffs; // current X offset
89		int yoffs; // current Y offset
90		int zoom; // zoom factor
91		UINT8 rotate; // current rotation (orientation) value
	87	int which; // which tilemap are we viewing?
	88	int xoffs; // current X offset
	89	int yoffs; // current Y offset
	90	int zoom; // zoom factor
	91	UINT8 rotate; // current rotation (orientation) value
92	92	} tilemap;
93	93	};
94	94
r29404	r29405
254	254	UINT32 ui_gfx_ui_handler(running_machine &machine, render_container *container, UINT32 uistate)
255	255	{
256	256	ui_gfx_state &state = ui_gfx;
257
	257
258	258	// if we have nothing, implicitly cancel
259	259	if (!ui_gfx_is_relevant(machine))
260	260	goto cancel;

trunk/src/emu/ui/selgame.h
r29404	r29405
31	31	private:
32	32	// internal state
33	33	enum { VISIBLE_GAMES_IN_LIST = 15 };
34		UINT8 m_error;
35		UINT8 m_rerandomize;
36		char m_search[40];
37		int m_matchlist[VISIBLE_GAMES_IN_LIST];
	34	UINT8 m_error;
	35	UINT8 m_rerandomize;
	36	char m_search[40];
	37	int m_matchlist[VISIBLE_GAMES_IN_LIST];
38	38	dynamic_array<const game_driver *> m_driverlist;
39	39	auto_pointer<driver_enumerator> m_drivlist;
40	40

trunk/src/emu/ui/ui.h
r29404	r29405
170	170
171	171	private:
172	172	// instance variables
173		running_machine & m_machine;
174		render_font * m_font;
175		ui_callback m_handler_callback;
176		UINT32 m_handler_param;
177		bool m_single_step;
178		bool m_showfps;
179		osd_ticks_t m_showfps_end;
180		bool m_show_profiler;
181		osd_ticks_t m_popup_text_end;
182		bool m_use_natural_keyboard;
183		UINT8 * m_non_char_keys_down;
184		render_texture * m_mouse_arrow_texture;
185		bool m_mouse_show;
	173	running_machine & m_machine;
	174	render_font * m_font;
	175	ui_callback m_handler_callback;
	176	UINT32 m_handler_param;
	177	bool m_single_step;
	178	bool m_showfps;
	179	osd_ticks_t m_showfps_end;
	180	bool m_show_profiler;
	181	osd_ticks_t m_popup_text_end;
	182	bool m_use_natural_keyboard;
	183	UINT8 * m_non_char_keys_down;
	184	render_texture * m_mouse_arrow_texture;
	185	bool m_mouse_show;
186	186
187		// text generators
	187	// text generators
188	188	astring &disclaimer_string(astring &buffer);
189	189	astring &warnings_string(astring &buffer);
190	190
191		// UI handlers
	191	// UI handlers
192	192	static UINT32 handler_messagebox(running_machine &machine, render_container *container, UINT32 state);
193	193	static UINT32 handler_messagebox_ok(running_machine &machine, render_container *container, UINT32 state);
194	194	static UINT32 handler_messagebox_anykey(running_machine &machine, render_container *container, UINT32 state);

trunk/src/emu/ui/filesel.c
r29404	r29405
203	203	// this should really be in the OSD layer
204	204	static const char valid_filename_char[] =
205	205	{
206		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 00-0f
207		0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 10-1f
208		1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, // !"#$%&'()*+,-./
209		1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, // 0123456789:;<=>?
210		1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // @ABCDEFGHIJKLMNO
211		1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, // PQRSTUVWXYZ[\]^_
212		0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // `abcdefghijklmno
213		1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, // pqrstuvwxyz{\|}~
	206	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 00-0f
	207	0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 10-1f
	208	1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, // !"#$%&'()*+,-./
	209	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, // 0123456789:;<=>?
	210	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // @ABCDEFGHIJKLMNO
	211	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, // PQRSTUVWXYZ[\]^_
	212	0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // `abcdefghijklmno
	213	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, // pqrstuvwxyz{\|}~
214	214	};
215	215	return (unichar < ARRAY_LENGTH(valid_filename_char)) && valid_filename_char[unichar];
216	216	}
r29404	r29405
222	222
223	223	ui_menu_file_create::ui_menu_file_create(running_machine &machine, render_container container, device_image_interface image, astring &current_directory, astring &current_file)
224	224	: ui_menu(machine, container),
225		m_current_directory(current_directory),
226		m_current_file(current_file)
	225	m_current_directory(current_directory),
	226	m_current_file(current_file)
227	227	{
228	228	m_image = image;
229	229	}
r29404	r29405
344	344
345	345	ui_menu_file_selector::ui_menu_file_selector(running_machine &machine, render_container container, device_image_interface image, astring &current_directory, astring &current_file, bool has_empty, bool has_softlist, bool has_create, int *result)
346	346	: ui_menu(machine, container),
347		m_current_directory(current_directory),
348		m_current_file(current_file)
	347	m_current_directory(current_directory),
	348	m_current_file(current_file)
349	349	{
350	350	m_image = image;
351	351	m_has_empty = has_empty;

trunk/src/emu/ui/swlist.c
r29404	r29405
360	360
361	361	/***************************************************************************
362	362	SOFTWARE MENU - list of available software lists - i.e. cartridges,
363		floppies
	363	floppies
364	364	***************************************************************************/
365	365
366	366	//-------------------------------------------------

trunk/src/emu/ui/imginfo.c
r29404	r29405
186	186	}
187	187	}
188	188	}
189
190

trunk/src/emu/ui/filesel.h
r29404	r29405
41	41	virtual void custom_render(void *selectedref, float top, float bottom, float x, float y, float x2, float y2);
42	42
43	43	private:
44		device_image_interface * m_image;
45		astring & m_current_directory;
46		astring & m_current_file;
47		const image_device_format * m_current_format;
48		char m_filename_buffer[1024];
	44	device_image_interface * m_image;
	45	astring & m_current_directory;
	46	astring & m_current_file;
	47	const image_device_format * m_current_format;
	48	char m_filename_buffer[1024];
49	49	};
50	50
51	51
r29404	r29405
82	82	};
83	83
84	84	// internal state
85		device_image_interface * m_image;
86		astring & m_current_directory;
87		astring & m_current_file;
88		bool m_has_empty;
89		bool m_has_softlist;
90		bool m_has_create;
91		int * m_result;
92		file_selector_entry * m_entrylist;
93		char m_filename_buffer[1024];
	85	device_image_interface * m_image;
	86	astring & m_current_directory;
	87	astring & m_current_file;
	88	bool m_has_empty;
	89	bool m_has_softlist;
	90	bool m_has_create;
	91	int * m_result;
	92	file_selector_entry * m_entrylist;
	93	char m_filename_buffer[1024];
94	94
95	95	// methods
96	96	int compare_entries(const file_selector_entry e1, const file_selector_entry e2);
r29404	r29405
113	113
114	114	private:
115	115	// internal state
116		floppy_image_format_t ** m_formats;
117		int m_ext_match;
118		int m_total_usable;
119		int * m_result;
	116	floppy_image_format_t ** m_formats;
	117	int m_ext_match;
	118	int m_total_usable;
	119	int * m_result;
120	120	};
121	121
122	122
r29404	r29405
134	134
135	135	private:
136	136	// internal state
137		bool m_can_in_place;
138		int * m_result;
	137	bool m_can_in_place;
	138	int * m_result;
139	139	};
140	140
141	141	// helper

trunk/src/emu/ui/swlist.h
r29404	r29405
29	29	};
30	30
31	31	// variables
32		const software_info * m_info;
33		const char * m_interface;
34		const software_part ** m_selected_part;
35		bool m_opt_fmgr;
36		int * m_result;
	32	const software_info * m_info;
	33	const char * m_interface;
	34	const software_part ** m_selected_part;
	35	bool m_opt_fmgr;
	36	int * m_result;
37	37	};
38	38
39	39
r29404	r29405
55	55	};
56	56
57	57	// variables
58		software_list_device * m_swlist; // currently selected list
59		const char * m_interface;
60		astring & m_result;
61		entry_info * m_entrylist;
62		char m_filename_buffer[1024];
63		bool m_ordered_by_shortname;
	58	software_list_device * m_swlist; // currently selected list
	59	const char * m_interface;
	60	astring & m_result;
	61	entry_info * m_entrylist;
	62	char m_filename_buffer[1024];
	63	bool m_ordered_by_shortname;
64	64
65	65	// functions
66	66	int compare_entries(const entry_info e1, const entry_info e2, bool shortname);
r29404	r29405
78	78	virtual void handle();
79	79
80	80	private:
81		const char * m_interface;
82		software_list_device ** m_result;
	81	const char * m_interface;
	82	software_list_device ** m_result;
83	83	};
84	84
85	85	#endif /* __UI_SWLIST_H__ */

trunk/src/emu/ui/barcode.c
r29404	r29405
1	1	/***************************************************************************
2	2
3		ui/barcode.c
4
5		MESS's "barcode reader" control
6
	3	ui/barcode.c
	4
	5	MESS's "barcode reader" control
	6
7	7	Copyright Nicola Salmoria and the MAME Team.
8	8	Visit http://mamedev.org for licensing and usage restrictions.
9	9
r29404	r29405
21	21
22	22
23	23	/**************************************************
24
	24
25	25	BARCODE INPUT MENU
26
	26
27	27	**************************************************/
28	28
29	29
r29404	r29405
67	67	}
68	68
69	69	item_append("New Barcode:", new_barcode, 0, ITEMREF_NEW_BARCODE);
70
	70
71	71	// finish up the menu
72	72	item_append(MENU_SEPARATOR_ITEM, NULL, 0, NULL);
73	73	item_append("Enter Code", NULL, 0, ITEMREF_ENTER);
r29404	r29405
108	108	}
109	109	}
110	110	break;
111
	111
112	112	case IPT_SPECIAL:
113	113	if (get_selection() == ITEMREF_NEW_BARCODE)
114	114	{
115	115	int buflen = strlen(m_barcode_buffer);
116
	116
117	117	// if it's a backspace and we can handle it, do so
118	118	if ((event->unichar == 8 \|\| event->unichar == 0x7f) && buflen > 0)
119	119	(char )utf8_previous_char(&m_barcode_buffer[buflen]) = 0;
r29404	r29405
140	140	/**************************************************
141	141
142	142	READER MENU
143
	143
144	144	**************************************************/
145	145
146	146	//-------------------------------------------------
r29404	r29405
168	168	void ui_menu_barcode_reader::populate()
169	169	{
170	170	astring buffer;
171
	171
172	172	barcode_reader_device_iterator iter(machine().config().root_device());
173	173	for (const barcode_reader_device *bcreader = iter.first(); bcreader != NULL; bcreader = iter.next())
174	174	{
175	175	char label[0x400];
176	176	sprintf(label,"[%s (%s)]",bcreader->name(),bcreader->basetag());
177	177	item_append(label, NULL, 0, (void *)bcreader);
178		}
	178	}
179	179	}
180	180
181	181
r29404	r29405
187	187	{
188	188	// process the menu
189	189	const ui_menu_event *event = process(0);
190
	190
191	191	// process the event
192	192	if (event != NULL && event->iptkey == IPT_UI_SELECT)
193	193	{
r29404	r29405
195	195	{
196	196	ui_menu::stack_push(auto_alloc_clear(machine(), ui_menu_barcode_code(machine(), container, (barcode_reader_device *)event->itemref)));
197	197	}
198
	198
199	199	}
200	200	}

trunk/src/emu/ui/filemngr.c
r29404	r29405
134	134	}
135	135	}
136	136	}
137
138

trunk/src/emu/ui/barcode.h
r29404	r29405
22	22	virtual ~ui_menu_barcode_code();
23	23	virtual void populate();
24	24	virtual void handle();
25
	25
26	26	private:
27	27	barcode_reader_device *m_reader;
28	28	char m_barcode_buffer[20];

trunk/src/emu/ui/menu.c
r29404	r29405
83	83	{
84	84	int x;
85	85
86		// initialize the menu stack
	86	// initialize the menu stack
87	87	ui_menu::stack_reset(machine);
88	88
89		// create a texture for hilighting items
	89	// create a texture for hilighting items
90	90	hilight_bitmap = auto_bitmap_rgb32_alloc(machine, 256, 1);
91	91	for (x = 0; x < 256; x++)
92	92	{
r29404	r29405
98	98	hilight_texture = machine.render().texture_alloc();
99	99	hilight_texture->set_bitmap(*hilight_bitmap, hilight_bitmap->cliprect(), TEXFORMAT_ARGB32);
100	100
101		// create a texture for arrow icons
	101	// create a texture for arrow icons
102	102	arrow_texture = machine.render().texture_alloc(render_triangle);
103	103
104		// add an exit callback to free memory
	104	// add an exit callback to free memory
105	105	machine.add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(ui_menu::exit), &machine));
106	106	}
107	107
r29404	r29405
112	112
113	113	void ui_menu::exit(running_machine &machine)
114	114	{
115		// free menus
	115	// free menus
116	116	ui_menu::stack_reset(machine);
117	117	ui_menu::clear_free_list(machine);
118	118
119		// free textures
	119	// free textures
120	120	machine.render().texture_free(hilight_texture);
121	121	machine.render().texture_free(arrow_texture);
122	122	}
r29404	r29405
146	146
147	147	ui_menu::~ui_menu()
148	148	{
149		// free the pools
	149	// free the pools
150	150	while (pool)
151	151	{
152	152	ui_menu_pool *ppool = pool;
r29404	r29405
154	154	auto_free(machine(), ppool);
155	155	}
156	156
157		// free the item array
	157	// free the item array
158	158	if (item)
159	159	auto_free(machine(), item);
160	160	}
r29404	r29405
167	167
168	168	void ui_menu::reset(ui_menu_reset_options options)
169	169	{
170		// based on the reset option, set the reset info
	170	// based on the reset option, set the reset info
171	171	resetpos = 0;
172	172	resetref = NULL;
173	173	if (options == UI_MENU_RESET_REMEMBER_POSITION)
r29404	r29405
175	175	else if (options == UI_MENU_RESET_REMEMBER_REF)
176	176	resetref = item[selected].ref;
177	177
178		// reset all the pools and the numitems back to 0
	178	// reset all the pools and the numitems back to 0
179	179	for (ui_menu_pool *ppool = pool; ppool != NULL; ppool = ppool->next)
180	180	ppool->top = (UINT8 *)(ppool + 1);
181	181	numitems = 0;
r29404	r29405
184	184	astring backtext;
185	185	backtext.printf("Return to %s",emulator_info::get_capstartgamenoun());
186	186
187		// add an item to return
	187	// add an item to return
188	188	if (parent == NULL)
189	189	item_append(backtext.cstr(), NULL, 0, NULL);
190	190	else if (parent->is_special_main_menu())
r29404	r29405
237	237	ui_menu_item *pitem;
238	238	int index;
239	239
240		// only allow multiline as the first item
	240	// only allow multiline as the first item
241	241	if ((flags & MENU_FLAG_MULTILINE) != 0)
242	242	assert(numitems == 1);
243	243
244		// only allow a single multi-line item
	244	// only allow a single multi-line item
245	245	else if (numitems >= 2)
246	246	assert((item[0].flags & MENU_FLAG_MULTILINE) == 0);
247	247
248		// realloc the item array if necessary
	248	// realloc the item array if necessary
249	249	if (numitems >= allocitems)
250	250	{
251	251	int olditems = allocitems;
r29404	r29405
258	258	}
259	259	index = numitems++;
260	260
261		// copy the previous last item to the next one
	261	// copy the previous last item to the next one
262	262	if (index != 0)
263	263	{
264	264	index--;
265	265	item[index + 1] = item[index];
266	266	}
267	267
268		// allocate a new item and populate it
	268	// allocate a new item and populate it
269	269	pitem = &item[index];
270	270	pitem->text = (text != NULL) ? pool_strdup(text) : NULL;
271	271	pitem->subtext = (subtext != NULL) ? pool_strdup(subtext) : NULL;
272	272	pitem->flags = flags;
273	273	pitem->ref = ref;
274	274
275		// update the selection if we need to
	275	// update the selection if we need to
276	276	if (resetpos == index \|\| (resetref != NULL && resetref == ref))
277	277	selected = index;
278	278	if (resetpos == numitems - 1)
r29404	r29405
287	287
288	288	const ui_menu_event *ui_menu::process(UINT32 flags)
289	289	{
290		// reset the menu_event
	290	// reset the menu_event
291	291	menu_event.iptkey = IPT_INVALID;
292	292
293		// first make sure our selection is valid
	293	// first make sure our selection is valid
294	294	validate_selection(1);
295	295
296		// draw the menu
	296	// draw the menu
297	297	if (numitems > 1 && (item[0].flags & MENU_FLAG_MULTILINE) != 0)
298	298	draw_text_box();
299	299	else
300	300	draw(flags & UI_MENU_PROCESS_CUSTOM_ONLY);
301	301
302		// process input
	302	// process input
303	303	if (!(flags & UI_MENU_PROCESS_NOKEYS))
304	304	{
305		// read events
	305	// read events
306	306	handle_events();
307	307
308		// handle the keys if we don't already have an menu_event
	308	// handle the keys if we don't already have an menu_event
309	309	if (menu_event.iptkey == IPT_INVALID)
310	310	handle_keys(flags);
311	311	}
312	312
313		// update the selected item in the menu_event
	313	// update the selected item in the menu_event
314	314	if (menu_event.iptkey != IPT_INVALID && selected >= 0 && selected < numitems)
315	315	{
316	316	menu_event.itemref = item[selected].ref;
r29404	r29405
331	331
332	332	assert(size < UI_MENU_POOL_SIZE);
333	333
334		// find a pool with enough room
	334	// find a pool with enough room
335	335	for (ppool = pool; ppool != NULL; ppool = ppool->next)
336	336	if (ppool->end - ppool->top >= size)
337	337	{
r29404	r29405
340	340	return result;
341	341	}
342	342
343		// allocate a new pool
	343	// allocate a new pool
344	344	ppool = (ui_menu_pool )auto_alloc_array_clear(machine(), UINT8, sizeof(ppool) + UI_MENU_POOL_SIZE);
345	345
346		// wire it up
	346	// wire it up
347	347	ppool->next = pool;
348	348	pool = ppool;
349	349	ppool->top = (UINT8 *)(ppool + 1);
r29404	r29405
423	423	INT32 mouse_target_x, mouse_target_y;
424	424	float mouse_x = -1, mouse_y = -1;
425	425
426		// compute the width and height of the full menu
	426	// compute the width and height of the full menu
427	427	visible_width = 0;
428	428	visible_main_menu_height = 0;
429	429	for (itemnum = 0; itemnum < numitems; itemnum++)
r29404	r29405
431	431	const ui_menu_item &pitem = item[itemnum];
432	432	float total_width;
433	433
434		// compute width of left hand side
	434	// compute width of left hand side
435	435	total_width = gutter_width + machine().ui().get_string_width(pitem.text) + gutter_width;
436	436
437		// add in width of right hand side
	437	// add in width of right hand side
438	438	if (pitem.subtext)
439	439	total_width += 2.0f * gutter_width + machine().ui().get_string_width(pitem.subtext);
440	440
441		// track the maximum
	441	// track the maximum
442	442	if (total_width > visible_width)
443	443	visible_width = total_width;
444	444
445		// track the height as well
	445	// track the height as well
446	446	visible_main_menu_height += line_height;
447	447	}
448	448
449		// account for extra space at the top and bottom
	449	// account for extra space at the top and bottom
450	450	visible_extra_menu_height = customtop + custombottom;
451	451
452		// add a little bit of slop for rounding
	452	// add a little bit of slop for rounding
453	453	visible_width += 0.01f;
454	454	visible_main_menu_height += 0.01f;
455	455
456		// if we are too wide or too tall, clamp it down
	456	// if we are too wide or too tall, clamp it down
457	457	if (visible_width + 2.0f * UI_BOX_LR_BORDER > 1.0f)
458	458	visible_width = 1.0f - 2.0f * UI_BOX_LR_BORDER;
459	459
460		// if the menu and extra menu won't fit, take away part of the regular menu, it will scroll
	460	// if the menu and extra menu won't fit, take away part of the regular menu, it will scroll
461	461	if (visible_main_menu_height + visible_extra_menu_height + 2.0f * UI_BOX_TB_BORDER > 1.0f)
462	462	visible_main_menu_height = 1.0f - 2.0f * UI_BOX_TB_BORDER - visible_extra_menu_height;
463	463
464	464	visible_lines = floor(visible_main_menu_height / line_height);
465	465	visible_main_menu_height = (float)visible_lines * line_height;
466	466
467		// compute top/left of inner menu area by centering
	467	// compute top/left of inner menu area by centering
468	468	visible_left = (1.0f - visible_width) * 0.5f;
469	469	visible_top = (1.0f - (visible_main_menu_height + visible_extra_menu_height)) * 0.5f;
470	470
471		// if the menu is at the bottom of the extra, adjust
	471	// if the menu is at the bottom of the extra, adjust
472	472	visible_top += customtop;
473	473
474		// first add us a box
	474	// first add us a box
475	475	x1 = visible_left - UI_BOX_LR_BORDER;
476	476	y1 = visible_top - UI_BOX_TB_BORDER;
477	477	x2 = visible_left + visible_width + UI_BOX_LR_BORDER;
r29404	r29405
479	479	if (!customonly)
480	480	machine().ui().draw_outlined_box(container, x1, y1, x2, y2, UI_BACKGROUND_COLOR);
481	481
482		// determine the first visible line based on the current selection
	482	// determine the first visible line based on the current selection
483	483	top_line = selected - visible_lines / 2;
484	484	if (top_line < 0)
485	485	top_line = 0;
486	486	if (top_line + visible_lines >= numitems)
487	487	top_line = numitems - visible_lines;
488	488
489		// determine effective positions taking into account the hilighting arrows
	489	// determine effective positions taking into account the hilighting arrows
490	490	effective_width = visible_width - 2.0f * gutter_width;
491	491	effective_left = visible_left + gutter_width;
492	492
493		// locate mouse
	493	// locate mouse
494	494	mouse_hit = false;
495	495	mouse_button = false;
496	496	if (!customonly)
r29404	r29405
501	501	mouse_hit = true;
502	502	}
503	503
504		// loop over visible lines
	504	// loop over visible lines
505	505	hover = numitems + 1;
506	506	if (!customonly)
507	507	for (linenum = 0; linenum < visible_lines; linenum++)
r29404	r29405
519	519	float line_x1 = x2 - 0.5f * UI_LINE_WIDTH;
520	520	float line_y1 = line_y + line_height;
521	521
522		// set the hover if this is our item
	522	// set the hover if this is our item
523	523	if (mouse_hit && line_x0 <= mouse_x && line_x1 > mouse_x && line_y0 <= mouse_y && line_y1 > mouse_y && pitem.is_selectable())
524	524	hover = itemnum;
525	525
526		// if we're selected, draw with a different background
	526	// if we're selected, draw with a different background
527	527	if (itemnum == selected)
528	528	{
529	529	fgcolor = UI_SELECTED_COLOR;
r29404	r29405
532	532	fgcolor3 = UI_SELECTED_COLOR;
533	533	}
534	534
535		// else if the mouse is over this item, draw with a different background
	535	// else if the mouse is over this item, draw with a different background
536	536	else if (itemnum == hover)
537	537	{
538	538	fgcolor = UI_MOUSEOVER_COLOR;
r29404	r29405
541	541	fgcolor3 = UI_MOUSEOVER_COLOR;
542	542	}
543	543
544		// if we have some background hilighting to do, add a quad behind everything else
	544	// if we have some background hilighting to do, add a quad behind everything else
545	545	if (bgcolor != UI_TEXT_BG_COLOR)
546	546	highlight(container, line_x0, line_y0, line_x1, line_y1, bgcolor);
547	547
548		// if we're on the top line, display the up arrow
	548	// if we're on the top line, display the up arrow
549	549	if (linenum == 0 && top_line != 0)
550	550	{
551	551	draw_arrow(
r29404	r29405
560	560	hover = -2;
561	561	}
562	562
563		// if we're on the bottom line, display the down arrow
	563	// if we're on the bottom line, display the down arrow
564	564	else if (linenum == visible_lines - 1 && itemnum != numitems - 1)
565	565	{
566	566	draw_arrow(
r29404	r29405
575	575	hover = -1;
576	576	}
577	577
578		// if we're just a divider, draw a line
	578	// if we're just a divider, draw a line
579	579	else if (strcmp(itemtext, MENU_SEPARATOR_ITEM) == 0)
580	580	container->add_line(visible_left, line_y + 0.5f * line_height, visible_left + visible_width, line_y + 0.5f * line_height, UI_LINE_WIDTH, UI_BORDER_COLOR, PRIMFLAG_BLENDMODE(BLENDMODE_ALPHA));
581	581
582		// if we don't have a subitem, just draw the string centered
	582	// if we don't have a subitem, just draw the string centered
583	583	else if (pitem.subtext == NULL)
584	584	machine().ui().draw_text_full(container, itemtext, effective_left, line_y, effective_width,
585	585	JUSTIFY_CENTER, WRAP_TRUNCATE, DRAW_NORMAL, fgcolor, bgcolor, NULL, NULL);
586	586
587		// otherwise, draw the item on the left and the subitem text on the right
	587	// otherwise, draw the item on the left and the subitem text on the right
588	588	else
589	589	{
590	590	int subitem_invert = pitem.flags & MENU_FLAG_INVERT;
591	591	const char *subitem_text = pitem.subtext;
592	592	float item_width, subitem_width;
593	593
594		// draw the left-side text
	594	// draw the left-side text
595	595	machine().ui().draw_text_full(container, itemtext, effective_left, line_y, effective_width,
596	596	JUSTIFY_LEFT, WRAP_TRUNCATE, DRAW_NORMAL, fgcolor, bgcolor, &item_width, NULL);
597	597
598		// give 2 spaces worth of padding
	598	// give 2 spaces worth of padding
599	599	item_width += 2.0f * gutter_width;
600	600
601		// if the subitem doesn't fit here, display dots
	601	// if the subitem doesn't fit here, display dots
602	602	if (machine().ui().get_string_width(subitem_text) > effective_width - item_width)
603	603	{
604	604	subitem_text = "...";
r29404	r29405
606	606	selected_subitem_too_big = TRUE;
607	607	}
608	608
609		// draw the subitem right-justified
	609	// draw the subitem right-justified
610	610	machine().ui().draw_text_full(container, subitem_text, effective_left + item_width, line_y, effective_width - item_width,
611	611	JUSTIFY_RIGHT, WRAP_TRUNCATE, DRAW_NORMAL, subitem_invert ? fgcolor3 : fgcolor2, bgcolor, &subitem_width, NULL);
612	612
613		// apply arrows
	613	// apply arrows
614	614	if (itemnum == selected && (pitem.flags & MENU_FLAG_LEFT_ARROW))
615	615	{
616	616	draw_arrow(
r29404	r29405
636	636	}
637	637	}
638	638
639		// if the selected subitem is too big, display it in a separate offset box
	639	// if the selected subitem is too big, display it in a separate offset box
640	640	if (selected_subitem_too_big)
641	641	{
642	642	const ui_menu_item &pitem = item[selected];
r29404	r29405
646	646	float target_width, target_height;
647	647	float target_x, target_y;
648	648
649		// compute the multi-line target width/height
	649	// compute the multi-line target width/height
650	650	machine().ui().draw_text_full(container, pitem.subtext, 0, 0, visible_width * 0.75f,
651	651	JUSTIFY_RIGHT, WRAP_WORD, DRAW_NONE, ARGB_WHITE, ARGB_BLACK, &target_width, &target_height);
652	652
653		// determine the target location
	653	// determine the target location
654	654	target_x = visible_left + visible_width - target_width - UI_BOX_LR_BORDER;
655	655	target_y = line_y + line_height + UI_BOX_TB_BORDER;
656	656	if (target_y + target_height + UI_BOX_TB_BORDER > visible_main_menu_height)
657	657	target_y = line_y - target_height - UI_BOX_TB_BORDER;
658	658
659		// add a box around that
	659	// add a box around that
660	660	machine().ui().draw_outlined_box(container, target_x - UI_BOX_LR_BORDER,
661	661	target_y - UI_BOX_TB_BORDER,
662	662	target_x + target_width + UI_BOX_LR_BORDER,
r29404	r29405
665	665	JUSTIFY_RIGHT, WRAP_WORD, DRAW_NORMAL, UI_SELECTED_COLOR, UI_SELECTED_BG_COLOR, NULL, NULL);
666	666	}
667	667
668		// if there is something special to add, do it by calling the virtual method
	668	// if there is something special to add, do it by calling the virtual method
669	669	custom_render((selected >= 0 && selected < numitems) ? item[selected].ref : NULL, customtop, custombottom, x1, y1, x2, y2);
670	670
671		// return the number of visible lines, minus 1 for top arrow and 1 for bottom arrow
	671	// return the number of visible lines, minus 1 for top arrow and 1 for bottom arrow
672	672	visitems = visible_lines - (top_line != 0) - (top_line + visible_lines != numitems);
673	673	}
674	674
r29404	r29405
692	692	float target_width, target_height, prior_width;
693	693	float target_x, target_y;
694	694
695		// compute the multi-line target width/height
	695	// compute the multi-line target width/height
696	696	machine().ui().draw_text_full(container, text, 0, 0, 1.0f - 2.0f * UI_BOX_LR_BORDER - 2.0f * gutter_width,
697	697	JUSTIFY_LEFT, WRAP_WORD, DRAW_NONE, ARGB_WHITE, ARGB_BLACK, &target_width, &target_height);
698	698	target_height += 2.0f * line_height;
699	699	if (target_height > 1.0f - 2.0f * UI_BOX_TB_BORDER)
700	700	target_height = floor((1.0f - 2.0f * UI_BOX_TB_BORDER) / line_height) * line_height;
701	701
702		// maximum against "return to prior menu" text
	702	// maximum against "return to prior menu" text
703	703	prior_width = machine().ui().get_string_width(backtext) + 2.0f * gutter_width;
704	704	target_width = MAX(target_width, prior_width);
705	705
706		// determine the target location
	706	// determine the target location
707	707	target_x = 0.5f - 0.5f * target_width;
708	708	target_y = 0.5f - 0.5f * target_height;
709	709
710		// make sure we stay on-screen
	710	// make sure we stay on-screen
711	711	if (target_x < UI_BOX_LR_BORDER + gutter_width)
712	712	target_x = UI_BOX_LR_BORDER + gutter_width;
713	713	if (target_x + target_width + gutter_width + UI_BOX_LR_BORDER > 1.0f)
r29404	r29405
717	717	if (target_y + target_height + UI_BOX_TB_BORDER > 1.0f)
718	718	target_y = 1.0f - UI_BOX_TB_BORDER - target_height;
719	719
720		// add a box around that
	720	// add a box around that
721	721	machine().ui().draw_outlined_box(container, target_x - UI_BOX_LR_BORDER - gutter_width,
722	722	target_y - UI_BOX_TB_BORDER,
723	723	target_x + target_width + gutter_width + UI_BOX_LR_BORDER,
r29404	r29405
725	725	machine().ui().draw_text_full(container, text, target_x, target_y, target_width,
726	726	JUSTIFY_LEFT, WRAP_WORD, DRAW_NORMAL, UI_TEXT_COLOR, UI_TEXT_BG_COLOR, NULL, NULL);
727	727
728		// draw the "return to prior menu" text with a hilight behind it
	728	// draw the "return to prior menu" text with a hilight behind it
729	729	highlight(
730	730	container,
731	731	target_x + 0.5f * UI_LINE_WIDTH,
r29404	r29405
736	736	machine().ui().draw_text_full(container, backtext, target_x, target_y + target_height - line_height, target_width,
737	737	JUSTIFY_CENTER, WRAP_TRUNCATE, DRAW_NORMAL, UI_SELECTED_COLOR, UI_SELECTED_BG_COLOR, NULL, NULL);
738	738
739		// artificially set the hover to the last item so a double-click exits
	739	// artificially set the hover to the last item so a double-click exits
740	740	hover = numitems - 1;
741	741	}
742	742
r29404	r29405
751	751	int stop = FALSE;
752	752	ui_event local_menu_event;
753	753
754		// loop while we have interesting events
	754	// loop while we have interesting events
755	755	while (!stop && ui_input_pop_event(machine(), &local_menu_event))
756	756	{
757	757	switch (local_menu_event.event_type)
758	758	{
759		// if we are hovering over a valid item, select it with a single click
	759	// if we are hovering over a valid item, select it with a single click
760	760	case UI_EVENT_MOUSE_DOWN:
761	761	if (hover >= 0 && hover < numitems)
762	762	selected = hover;
r29404	r29405
772	772	}
773	773	break;
774	774
775		// if we are hovering over a valid item, fake a UI_SELECT with a double-click
	775	// if we are hovering over a valid item, fake a UI_SELECT with a double-click
776	776	case UI_EVENT_MOUSE_DOUBLE_CLICK:
777	777	if (hover >= 0 && hover < numitems)
778	778	{
r29404	r29405
790	790	}
791	791	break;
792	792
793		// translate CHAR events into specials
	793	// translate CHAR events into specials
794	794	case UI_EVENT_CHAR:
795	795	menu_event.iptkey = IPT_SPECIAL;
796	796	menu_event.unichar = local_menu_event.ch;
797	797	stop = TRUE;
798	798	break;
799	799
800		// ignore everything else
	800	// ignore everything else
801	801	default:
802	802	break;
803	803	}
r29404	r29405
817	817	int ignoreleft = FALSE;
818	818	int code;
819	819
820		// bail if no items
	820	// bail if no items
821	821	if (numitems == 0)
822	822	return;
823	823
824		// if we hit select, return TRUE or pop the stack, depending on the item
	824	// if we hit select, return TRUE or pop the stack, depending on the item
825	825	if (exclusive_input_pressed(IPT_UI_SELECT, 0))
826	826	{
827	827	if (selected == numitems - 1)
r29404	r29405
832	832	return;
833	833	}
834	834
835		// hitting cancel also pops the stack
	835	// hitting cancel also pops the stack
836	836	if (exclusive_input_pressed(IPT_UI_CANCEL, 0))
837	837	{
838	838	ui_menu::stack_pop(machine());
839	839	return;
840	840	}
841	841
842		// validate the current selection
	842	// validate the current selection
843	843	validate_selection(1);
844	844
845		// swallow left/right keys if they are not appropriate
	845	// swallow left/right keys if they are not appropriate
846	846	ignoreleft = ((item[selected].flags & MENU_FLAG_LEFT_ARROW) == 0);
847	847	ignoreright = ((item[selected].flags & MENU_FLAG_RIGHT_ARROW) == 0);
848	848
849		// accept left/right keys as-is with repeat
	849	// accept left/right keys as-is with repeat
850	850	if (!ignoreleft && exclusive_input_pressed(IPT_UI_LEFT, (flags & UI_MENU_PROCESS_LR_REPEAT) ? 6 : 0))
851	851	return;
852	852	if (!ignoreright && exclusive_input_pressed(IPT_UI_RIGHT, (flags & UI_MENU_PROCESS_LR_REPEAT) ? 6 : 0))
853	853	return;
854	854
855		// up backs up by one item
	855	// up backs up by one item
856	856	if (exclusive_input_pressed(IPT_UI_UP, 6))
857	857	{
858	858	selected = (selected + numitems - 1) % numitems;
859	859	validate_selection(-1);
860	860	}
861	861
862		// down advances by one item
	862	// down advances by one item
863	863	if (exclusive_input_pressed(IPT_UI_DOWN, 6))
864	864	{
865	865	selected = (selected + 1) % numitems;
866	866	validate_selection(1);
867	867	}
868	868
869		// page up backs up by visitems
	869	// page up backs up by visitems
870	870	if (exclusive_input_pressed(IPT_UI_PAGE_UP, 6))
871	871	{
872	872	selected -= visitems - 1;
873	873	validate_selection(1);
874	874	}
875	875
876		// page down advances by visitems
	876	// page down advances by visitems
877	877	if (exclusive_input_pressed(IPT_UI_PAGE_DOWN, 6))
878	878	{
879	879	selected += visitems - 1;
880	880	validate_selection(-1);
881	881	}
882	882
883		// home goes to the start
	883	// home goes to the start
884	884	if (exclusive_input_pressed(IPT_UI_HOME, 0))
885	885	{
886	886	selected = 0;
887	887	validate_selection(1);
888	888	}
889	889
890		// end goes to the last
	890	// end goes to the last
891	891	if (exclusive_input_pressed(IPT_UI_END, 0))
892	892	{
893	893	selected = numitems - 1;
894	894	validate_selection(-1);
895	895	}
896	896
897		// pause enables/disables pause
	897	// pause enables/disables pause
898	898	if (!ignorepause && exclusive_input_pressed(IPT_UI_PAUSE, 0))
899	899	{
900	900	if (machine().paused())
r29404	r29405
903	903	machine().pause();
904	904	}
905	905
906		// handle a toggle cheats request
	906	// handle a toggle cheats request
907	907	if (ui_input_pressed_repeat(machine(), IPT_UI_TOGGLE_CHEAT, 0))
908	908	machine().cheat().set_enable(!machine().cheat().enabled());
909	909
910		// see if any other UI keys are pressed
	910	// see if any other UI keys are pressed
911	911	if (menu_event.iptkey == IPT_INVALID)
912	912	for (code = IPT_UI_FIRST + 1; code < IPT_UI_LAST; code++)
913	913	{
r29404	r29405
927	927
928	928	void ui_menu::validate_selection(int scandir)
929	929	{
930		// clamp to be in range
	930	// clamp to be in range
931	931	if (selected < 0)
932	932	selected = 0;
933	933	else if (selected >= numitems)
934	934	selected = numitems - 1;
935	935
936		// skip past unselectable items
	936	// skip past unselectable items
937	937	while (!item[selected].is_selectable())
938	938	selected = (selected + numitems + scandir) % numitems;
939	939	}
r29404	r29405
1038	1038
1039	1039	UINT32 ui_menu::ui_handler(running_machine &machine, render_container *container, UINT32 state)
1040	1040	{
1041		// if we have no menus stacked up, start with the main menu
	1041	// if we have no menus stacked up, start with the main menu
1042	1042	if (menu_stack == NULL)
1043	1043	stack_push(auto_alloc_clear(machine, ui_menu_main(machine, container)));
1044	1044
1045		// update the menu state
	1045	// update the menu state
1046	1046	if (menu_stack != NULL)
1047	1047	menu_stack->do_handle();
1048	1048
1049		// clear up anything pending to be released
	1049	// clear up anything pending to be released
1050	1050	clear_free_list(machine);
1051	1051
1052		// if the menus are to be hidden, return a cancel here
	1052	// if the menus are to be hidden, return a cancel here
1053	1053	if (machine.ui().is_menu_active() && ((ui_input_pressed(machine, IPT_UI_CONFIGURE) && !stack_has_special_main_menu()) \|\| menu_stack == NULL))
1054	1054	return UI_HANDLER_CANCEL;
1055	1055
r29404	r29405
1072	1072	int height = dest.height();
1073	1073	int x, y;
1074	1074
1075		// start with all-transparent
	1075	// start with all-transparent
1076	1076	dest.fill(rgb_t(0x00,0x00,0x00,0x00));
1077	1077
1078		// render from the tip to the bottom
	1078	// render from the tip to the bottom
1079	1079	for (y = 0; y < height; y++)
1080	1080	{
1081	1081	int linewidth = (y * (halfwidth - 1) + (height / 2)) * 255 * 2 / height;
1082	1082	UINT32 *target = &dest.pix32(y, halfwidth);
1083	1083
1084		// don't antialias if height < 12
	1084	// don't antialias if height < 12
1085	1085	if (dest.height() < 12)
1086	1086	{
1087	1087	int pixels = (linewidth + 254) / 255;
r29404	r29405
1089	1089	linewidth = pixels * 255;
1090	1090	}
1091	1091
1092		// loop while we still have data to generate
	1092	// loop while we still have data to generate
1093	1093	for (x = 0; linewidth > 0; x++)
1094	1094	{
1095	1095	int dalpha;
1096	1096
1097		// first column we only consume one pixel
	1097	// first column we only consume one pixel
1098	1098	if (x == 0)
1099	1099	{
1100	1100	dalpha = MIN(0xff, linewidth);
1101	1101	target[x] = rgb_t(dalpha,0xff,0xff,0xff);
1102	1102	}
1103	1103
1104		// remaining columns consume two pixels, one on each side
	1104	// remaining columns consume two pixels, one on each side
1105	1105	else
1106	1106	{
1107	1107	dalpha = MIN(0x1fe, linewidth);

trunk/src/emu/ui/devctrl.h
r29404	r29405
23	23	protected:
24	24	_DeviceType *current_device() { return m_device; }
25	25	int count() { return m_count; }
26
	26
27	27	int current_index();
28	28	void previous();
29	29	void next();
r29404	r29405
32	32	// device iterator
33	33	typedef device_type_iterator<&device_creator<_DeviceType>, _DeviceType> iterator;
34	34
35		_DeviceType * m_device;
36		int m_count;
	35	_DeviceType * m_device;
	36	int m_count;
37	37	};
38	38
39	39

trunk/src/emu/drivers/xtal.h
r29404	r29405
138	138	XTAL_17_36MHz = 17360000, /* OMTI Series 10 SCSI controller */
139	139	XTAL_17_73447MHz = 17734470, /* (~4x PAL subcarrier) */
140	140	XTAL_17_734472MHz = 17734472, /* actually ~4x PAL subcarrier */
141		XTAL_17_9712MHz = 17971200,
	141	XTAL_17_9712MHz = 17971200,
142	142	XTAL_18MHz = 18000000, /* S.A.R, Ikari Warriors 3 */
143	143	XTAL_18_432MHz = 18432000, /* Extremely common, used on 100's of PCBs (48000 * 384) */
144	144	XTAL_18_720MHz = 18720000, /* Nokia MikroMikko 1 */

trunk/src/emu/imagedev/harddriv.h
r29404	r29405
36	36
37	37	void set_device_load(device_image_load_delegate _load) { m_device_image_load = _load; }
38	38	void set_device_unload(device_image_func_delegate _unload) { m_device_image_unload = _unload; }
39
	39
40	40	// image-level overrides
41	41	virtual bool call_load();
42	42	virtual bool call_create(int create_format, option_resolution *create_args);
r29404	r29405
71	71	chd_file m_origchd; /* handle to the original CHD */
72	72	chd_file m_diffchd; /* handle to the diff CHD */
73	73	hard_disk_file *m_hard_disk_handle;
74
	74
75	75	device_image_load_delegate m_device_image_load;
76		device_image_func_delegate m_device_image_unload;
	76	device_image_func_delegate m_device_image_unload;
77	77	};
78	78
79	79	// device type definition
r29404	r29405
88	88	#define MCFG_HARDDISK_CONFIG_ADD(_tag,_config) \
89	89	MCFG_DEVICE_ADD(_tag, HARDDISK, 0) \
90	90	MCFG_DEVICE_CONFIG(_config)
91
	91
92	92	#define MCFG_HARDDISK_LOAD(_class,_load) \
93	93	static_cast<harddisk_image_device *>(device)->set_device_load( DEVICE_IMAGE_LOAD_DELEGATE(_class,_load));
94	94
95	95	#define MCFG_HARDDISK_UNLOAD(_class,_unload) \
96	96	static_cast<harddisk_image_device *>(device)->set_device_unload( DEVICE_IMAGE_UNLOAD_DELEGATE(_class,_unload));
97
	97
98	98	#endif /* HARDDRIV_H */

trunk/src/emu/imagedev/flopdrv.c
r29404	r29405
206	206	a fixed set of circumstances */
207	207	/* use this to set ready state of drive */
208	208	void legacy_floppy_image_device::floppy_drive_set_ready_state(int state, int flag)
209		{
	209	{
210	210	if (flag)
211	211	{
212	212	/* set ready only if drive is present, disk is in the drive,
r29404	r29405
252	252
253	253
254	254	void legacy_floppy_image_device::floppy_drive_seek(signed int signed_tracks)
255		{
	255	{
256	256	LOG(("seek from: %d delta: %d\n",m_current_track, signed_tracks));
257	257
258	258	/* update position */
r29404	r29405
432	432	const char *extension;
433	433
434	434	device_image_interface *image = NULL;
435		interface(image); /* figure out the floppy options */
	435	interface(image); /* figure out the floppy options */
436	436	floppy_options = ((floppy_interface*)static_config())->formats;
437	437
438	438	if (has_been_created())
r29404	r29405
621	621	/* step */
622	622	WRITE_LINE_MEMBER( legacy_floppy_image_device::floppy_stp_w )
623	623	{
624
625	624	/* move head one track when going from high to low and write gate is high */
626	625	if (m_active && m_stp && state == CLEAR_LINE && m_wtg)
627	626	{

trunk/src/emu/softlist.c
r29404	r29405
40	40	POS_PART,
41	41	POS_DATA
42	42	};
43
	43
44	44	// internal parsing helpers
45	45	const char *filename() const { return m_list.filename(); }
46	46	const char *infoname() const { return (m_current_info != NULL) ? m_current_info->shortname() : "???"; }
r29404	r29405
74	74	void parse_soft_end(const char *name);
75	75
76	76	// internal parsing state
77		software_list_device & m_list;
78		astring & m_errors;
79		XML_Parser m_parser;
80		bool m_done;
81		bool m_data_accum_expected;
82		astring m_data_accum;
83		software_info * m_current_info;
84		software_part * m_current_part;
85		parse_position m_pos;
	77	software_list_device & m_list;
	78	astring & m_errors;
	79	XML_Parser m_parser;
	80	bool m_done;
	81	bool m_data_accum_expected;
	82	astring m_data_accum;
	83	software_info * m_current_info;
	84	software_part * m_current_part;
	85	parse_position m_pos;
86	86	};
87	87
88	88
r29404	r29405
106	106
107	107	software_part::software_part(software_info &info, const char name, const char interface)
108	108	: m_next(NULL),
109		m_info(info),
110		m_name(name),
111		m_interface(interface)
	109	m_info(info),
	110	m_name(name),
	111	m_interface(interface)
112	112	{
113	113	// ensure strings we are passed are in the string pool
114	114	assert(info.list().string_pool_contains(name));
r29404	r29405
117	117
118	118
119	119	//-------------------------------------------------
120		// feature - return the value of the given
121		// feature, if specified
	120	// feature - return the value of the given
	121	// feature, if specified
122	122	//-------------------------------------------------
123	123
124	124	const char software_part::feature(const char feature_name) const
r29404	r29405
136	136
137	137	//-------------------------------------------------
138	138	// is_compatible - determine if we are compatible
139		// with the given software_list_device
	139	// with the given software_list_device
140	140	//-------------------------------------------------
141	141
142	142	bool software_part::is_compatible(const software_list_device &swlistdev) const
r29404	r29405
150	150	// copy the comma-delimited strings and ensure they end with a final comma
151	151	astring comp(compatibility, ",");
152	152	astring filt(filter, ",");
153
	153
154	154	// iterate over filter items and see if they exist in the compatibility list; if so, return true
155	155	for (int start = 0, end = filt.chr(start, ','); end != -1; start = end + 1, end = filt.chr(start, ','))
156	156	{
r29404	r29405
164	164
165	165	//-------------------------------------------------
166	166	// matches_interface - determine if we match
167		// an interface in the provided list
	167	// an interface in the provided list
168	168	//-------------------------------------------------
169	169
170	170	bool software_part::matches_interface(const char *interface_list) const
r29404	r29405
175	175
176	176	// copy the comma-delimited interface list and ensure it ends with a final comma
177	177	astring interfaces(interface_list, ",");
178
	178
179	179	// then add a comma to the end of our interface and return true if we find it in the list string
180	180	astring our_interface(m_interface, ",");
181	181	return (interfaces.find(0, our_interface) != -1);
r29404	r29405
193	193
194	194	software_info::software_info(software_list_device &list, const char name, const char parent, const char *supported)
195	195	: m_next(NULL),
196		m_list(list),
197		m_supported(SOFTWARE_SUPPORTED_YES),
198		m_shortname(name),
199		m_parentname(parent)
	196	m_list(list),
	197	m_supported(SOFTWARE_SUPPORTED_YES),
	198	m_shortname(name),
	199	m_parentname(parent)
200	200	{
201	201	// ensure strings we are passed are in the string pool
202	202	assert(list.string_pool_contains(name));
r29404	r29405
215	215
216	216	//-------------------------------------------------
217	217	// find_part - find a part by name with an
218		// optional interface match
	218	// optional interface match
219	219	//-------------------------------------------------
220	220
221	221	software_part software_info::find_part(const char partname, const char *interface)
r29404	r29405
225	225
226	226	if (partname == NULL && interface == NULL)
227	227	return m_partdata.first();
228
	228
229	229	// look for the part by name and match against the interface if provided
230	230	for (software_part *part = m_partdata.first(); part != NULL; part = part->next())
231	231	if (partname != NULL && strcmp(partname, part->name()) == 0)
232	232	{
233	233	if (interface == NULL \|\| part->matches_interface(interface))
234	234	return part;
235		}
	235	}
236	236	else if (partname == NULL && part->matches_interface(interface))
237	237	return part;
238	238	return NULL;
r29404	r29405
241	241
242	242	//-------------------------------------------------
243	243	// has_multiple_parts - return true if we have
244		// more than one part matching the given
245		// interface
	244	// more than one part matching the given
	245	// interface
246	246	//-------------------------------------------------
247	247
248	248	bool software_info::has_multiple_parts(const char *interface) const
249	249	{
250	250	int count = 0;
251
	251
252	252	// increment the count for each match and stop if we hit more than 1
253	253	for (software_part *part = first_part(); part != NULL; part = part->next())
254	254	if (part->matches_interface(interface))
255	255	if (++count > 1)
256	256	return true;
257
	257
258	258	return false;
259	259	}
260	260
r29404	r29405
290	290	if (result != NULL)
291	291	return result;
292	292	}
293
	293
294	294	// no space anywhere, create a new pool and prepend it (so it gets used first)
295	295	const char result = m_chunklist.prepend(global_alloc(pool_chunk)).add(string);
296	296	assert(result != NULL);
r29404	r29405
299	299
300	300
301	301	//-------------------------------------------------
302		// contains - determine if the given string
	302	// contains - determine if the given string
303	303	// pointer lives in the pool
304	304	//-------------------------------------------------
305	305
r29404	r29405
313	313	for (pool_chunk *chunk = m_chunklist.first(); chunk != NULL; chunk = chunk->next())
314	314	if (chunk->contains(string))
315	315	return true;
316
	316
317	317	return false;
318	318	}
319	319
r29404	r29405
323	323	//-------------------------------------------------
324	324
325	325	const_string_pool::pool_chunk::pool_chunk()
326		: m_next(NULL),
327		m_used(0)
	326	: m_next(NULL),
	327	m_used(0)
328	328	{
329	329	}
330	330
r29404	r29405
338	338	// get the length of the string (no string can be longer than a full pool)
339	339	int bytes = strlen(string) + 1;
340	340	assert(bytes < POOL_SIZE);
341
	341
342	342	// if too big, return NULL
343	343	if (m_used + bytes > POOL_SIZE)
344	344	return NULL;
r29404	r29405
405	405
406	406	//-------------------------------------------------
407	407	// find_approx_matches - search ourselves for
408		// a list of possible matches of the given name
409		// and optional interface
	408	// a list of possible matches of the given name
	409	// and optional interface
410	410	//-------------------------------------------------
411	411
412	412	void software_list_device::find_approx_matches(const char name, int matches, software_info list, const char interface)
r29404	r29405
456	456
457	457
458	458	//-------------------------------------------------
459		// release - reset to a pre-parsed state
	459	// release - reset to a pre-parsed state
460	460	//-------------------------------------------------
461	461
462	462	void software_list_device::release()
r29404	r29405
471	471
472	472
473	473	//-------------------------------------------------
474		// find_by_name - find a software list by name
475		// across all software list devices
	474	// find_by_name - find a software list by name
	475	// across all software list devices
476	476	//-------------------------------------------------
477	477
478	478	software_list_device software_list_device::find_by_name(const machine_config &config, const char name)
r29404	r29405
488	488
489	489	//-------------------------------------------------
490	490	// software_display_matches - display a list of
491		// possible matches in the system to the given
492		// name, across all software list devices
	491	// possible matches in the system to the given
	492	// name, across all software list devices
493	493	//-------------------------------------------------
494	494
495	495	void software_list_device::display_matches(const machine_config &config, const char interface, const char name)
r29404	r29405
528	528
529	529
530	530	//-------------------------------------------------
531		// find - find an item by name in the software
	531	// find - find an item by name in the software
532	532	// list, using wildcards and optionally starting
533		// from an intermediate point
	533	// from an intermediate point
534	534	//-------------------------------------------------
535	535
536	536	software_info software_list_device::find(const char look_for, software_info *prev)
r29404	r29405
566	566	if (filerr == FILERR_NONE)
567	567	{
568	568	// parse if no error
569		softlist_parser parser(*this, m_errors);
	569	softlist_parser parser(*this, m_errors);
570	570	m_file.close();
571	571	}
572	572	else
573	573	m_errors.printf("Error opening file: %s\n", filename());
574
	574
575	575	// indicate that we've been parsed
576	576	m_parsed = true;
577	577	}
r29404	r29405
579	579
580	580	//-------------------------------------------------
581	581	// device_validity_check - validate the device
582		// configuration
	582	// configuration
583	583	//-------------------------------------------------
584	584
585	585	void software_list_device::device_validity_check(validity_checker &valid) const
r29404	r29405
592	592	// do device validation only in case of validate command
593	593	if (strcmp(mconfig().options().command(), CLICOMMAND_VALIDATE) != 0)
594	594	return;
595
	595
596	596	// actually do the validate
597	597	const_cast<software_list_device *>(this)->internal_validity_check(valid);
598	598	}
r29404	r29405
600	600
601	601	//-------------------------------------------------
602	602	// internal_validity_check - internal helper to
603		// check the list
	603	// check the list
604	604	//-------------------------------------------------
605	605
606	606	void software_list_device::internal_validity_check(validity_checker &valid)
r29404	r29405
734	734
735	735	softlist_parser::softlist_parser(software_list_device &list, astring &errors)
736	736	: m_list(list),
737		m_errors(errors),
738		m_done(false),
739		m_data_accum_expected(false),
740		m_current_info(NULL),
741		m_current_part(NULL),
742		m_pos(POS_ROOT)
	737	m_errors(errors),
	738	m_done(false),
	739	m_data_accum_expected(false),
	740	m_current_info(NULL),
	741	m_current_part(NULL),
	742	m_pos(POS_ROOT)
743	743	{
744	744	mame_printf_verbose("Parsing %s\n", m_list.m_file.filename());
745	745
r29404	r29405
805	805
806	806	//-------------------------------------------------
807	807	// parse_error - append a parsing error with
808		// filename, line and column information
	808	// filename, line and column information
809	809	//-------------------------------------------------
810	810
811	811	void ATTR_PRINTF(2,3) softlist_parser::parse_error(const char *fmt, ...)
812	812	{
813		// always start with filename(line.column):
	813	// always start with filename(line.column):
814	814	m_errors.catprintf("%s(%d.%d): ", filename(), line(), column());
815
	815
816	816	// append the remainder of the string
817	817	va_list va;
818	818	va_start(va, fmt);
819	819	m_errors.catvprintf(fmt, va);
820	820	va_end(va);
821
	821
822	822	// append a newline at the end
823	823	m_errors.cat("\n");
824	824	}
r29404	r29405
826	826
827	827	//-------------------------------------------------
828	828	// parse_attributes - helper to parse a set of
829		// attributes into a list of strings
	829	// attributes into a list of strings
830	830	//-------------------------------------------------
831	831
832	832	void softlist_parser::parse_attributes(const char *attributes, int numattrs, const char attrlist[], const char *outlist[])
r29404	r29405
835	835	for( ; attributes[0]; attributes += 2)
836	836	{
837	837	int index;
838
	838
839	839	// look for a match among the attributes provided
840	840	for (index = 0; index < numattrs; index++)
841	841	if (strcmp(attributes[0], attrlist[index]) == 0)
r29404	r29405
844	844	outlist[index] = attributes[1];
845	845	break;
846	846	}
847
	847
848	848	// if not found, report an unknown attribute
849	849	if (index == numattrs)
850	850	unknown_attribute(attributes[0]);
r29404	r29405
854	854
855	855	//-------------------------------------------------
856	856	// add_rom_entry - append a new ROM entry to the
857		// current part's list
	857	// current part's list
858	858	//-------------------------------------------------
859	859
860	860	void softlist_parser::add_rom_entry(const char name, const char hashdata, UINT32 offset, UINT32 length, UINT32 flags)
r29404	r29405
903	903	case POS_SOFT:
904	904	state->parse_soft_start(tagname, attributes);
905	905	break;
906
	906
907	907	case POS_PART:
908	908	state->parse_part_start(tagname, attributes);
909	909	break;
910
	910
911	911	case POS_DATA:
912	912	state->parse_data_start(tagname, attributes);
913	913	break;
914	914	}
915
	915
916	916	// increment the state since this is a tag start
917	917	state->m_pos = parse_position(state->m_pos + 1);
918	918	}
r29404	r29405
949	949	case POS_DATA:
950	950	break;
951	951	}
952
	952
953	953	// stop accumulating
954	954	state->m_data_accum_expected = false;
955	955	state->m_data_accum.reset();
r29404	r29405
991	991	static const char *attrnames[] = { "name", "description" };
992	992	const char *attrvalues[ARRAY_LENGTH(attrnames)] = { 0 };
993	993	parse_attributes(attributes, ARRAY_LENGTH(attrnames), attrnames, attrvalues);
994
	994
995	995	if (attrvalues[1] != NULL)
996	996	m_list.m_description = m_list.add_string(attrvalues[1]);
997	997	}
r29404	r29405
1002	1002
1003	1003	//-------------------------------------------------
1004	1004	// parse_main_start - handle tag start within
1005		// a softwarelist tag
	1005	// a softwarelist tag
1006	1006	//-------------------------------------------------
1007	1007
1008	1008	void softlist_parser::parse_main_start(const char tagname, const char *attributes)
r29404	r29405
1026	1026
1027	1027	//-------------------------------------------------
1028	1028	// parse_main_start - handle tag start within
1029		// a software tag
	1029	// a software tag
1030	1030	//-------------------------------------------------
1031	1031
1032	1032	void softlist_parser::parse_soft_start(const char tagname, const char *attributes)
r29404	r29405
1062	1062	else
1063	1063	parse_error("Incomplete other_info definition");
1064	1064	}
1065
	1065
1066	1066	// <sharedfeat name='' value=''>
1067	1067	else if (strcmp(tagname, "sharedfeat") == 0)
1068	1068	{
1069	1069	static const char *attrnames[] = { "name", "value" };
1070	1070	const char *attrvalues[ARRAY_LENGTH(attrnames)] = { 0 };
1071	1071	parse_attributes(attributes, ARRAY_LENGTH(attrnames), attrnames, attrvalues);
1072
	1072
1073	1073	if (attrvalues[0] != NULL && attrvalues[1] != NULL)
1074	1074	m_current_info->m_shared_info.append(*global_alloc(feature_list_item(m_list.add_string(attrvalues[0]), m_list.add_string(attrvalues[1]))));
1075	1075	else
1076	1076	parse_error("Incomplete sharedfeat definition");
1077	1077	}
1078
	1078
1079	1079	// <part name='' interface=''>
1080	1080	else if (strcmp(tagname, "part" ) == 0)
1081	1081	{
r29404	r29405
1095	1095
1096	1096	//-------------------------------------------------
1097	1097	// parse_part_start - handle tag start within
1098		// a part tag
	1098	// a part tag
1099	1099	//-------------------------------------------------
1100	1100
1101	1101	void softlist_parser::parse_part_start(const char tagname, const char *attributes)
r29404	r29405
1113	1113	static const char *attrnames[] = { "name", "size" };
1114	1114	const char *attrvalues[ARRAY_LENGTH(attrnames)] = { 0 };
1115	1115	parse_attributes(attributes, ARRAY_LENGTH(attrnames), attrnames, attrvalues);
1116
	1116
1117	1117	if (attrvalues[0] != NULL && attrvalues[1] != NULL && strcmp(attrvalues[0], "") != 0 && strcmp(attrvalues[1], "") != 0)
1118	1118	add_rom_entry(attrvalues[0], NULL, 0, strtol(attrvalues[1], NULL, 0), ROMENTRYTYPE_REGION);
1119	1119	else
1120	1120	parse_error("Incomplete dataarea definition");
1121	1121	}
1122
	1122
1123	1123	// <diskarea name=''>
1124	1124	else if (strcmp(tagname, "diskarea") == 0)
1125	1125	{
r29404	r29405
1132	1132	else
1133	1133	parse_error("Incomplete diskarea definition");
1134	1134	}
1135
	1135
1136	1136	// <feature name='' value=''>
1137	1137	else if (strcmp(tagname, "feature") == 0)
1138	1138	{
1139	1139	static const char *attrnames[] = { "name", "value" };
1140	1140	const char *attrvalues[ARRAY_LENGTH(attrnames)] = { 0 };
1141	1141	parse_attributes(attributes, ARRAY_LENGTH(attrnames), attrnames, attrvalues);
1142
	1142
1143	1143	if (attrvalues[0] != NULL)
1144	1144	m_current_part->m_featurelist.append(*global_alloc(feature_list_item(m_list.add_string(attrvalues[0]), m_list.add_string(attrvalues[1]))));
1145	1145	else
1146	1146	parse_error("Incomplete feature definition");
1147	1147	}
1148
	1148
1149	1149	// <dipswitch>
1150	1150	else if (strcmp(tagname, "dipswitch") == 0)
1151	1151	;
r29404	r29405
1156	1156
1157	1157	//-------------------------------------------------
1158	1158	// parse_data_start - handle tag start within a
1159		// dataarea or diskarea tag
	1159	// dataarea or diskarea tag
1160	1160	//-------------------------------------------------
1161	1161
1162	1162	void softlist_parser::parse_data_start(const char tagname, const char *attributes)
r29404	r29405
1174	1174	static const char *attrnames[] = { "name", "size", "crc", "sha1", "offset", "value", "status", "loadflag" };
1175	1175	const char *attrvalues[ARRAY_LENGTH(attrnames)] = { 0 };
1176	1176	parse_attributes(attributes, ARRAY_LENGTH(attrnames), attrnames, attrvalues);
1177
	1177
1178	1178	const char *name = attrvalues[0];
1179	1179	const char *sizestr = attrvalues[1];
1180	1180	const char *crc = attrvalues[2];
r29404	r29405
1237	1237	else
1238	1238	parse_error("Incomplete rom definition");
1239	1239	}
1240
	1240
1241	1241	// <rom name='' sha1='' status='' writeable=''>
1242	1242	else if (strcmp(tagname, "disk") == 0)
1243	1243	{
r29404	r29405
1262	1262	else if (status == NULL \|\| !strcmp(status, "nodump")) // a no_dump chd is not an incomplete entry
1263	1263	parse_error("Incomplete disk definition");
1264	1264	}
1265
	1265
1266	1266	// <dipvalue>
1267	1267	else if (strcmp(tagname, "dipvalue") == 0)
1268	1268	;
r29404	r29405
1273	1273
1274	1274	//-------------------------------------------------
1275	1275	// parse_soft_end - handle end-of-tag post-
1276		// processing within the <software> tag
	1276	// processing within the <software> tag
1277	1277	//-------------------------------------------------
1278	1278
1279	1279	void softlist_parser::parse_soft_end(const char *tagname)
r29404	r29405
1299	1299	assert(m_current_part != NULL);
1300	1300	if (m_current_part == NULL)
1301	1301	return;
1302
	1302
1303	1303	// was any dataarea/rom information encountered? if so, add a terminator
1304	1304	if (m_current_part->romdata() != NULL)
1305	1305	add_rom_entry(NULL, NULL, 0, 0, ROMENTRYTYPE_END);
1306
	1306
1307	1307	// get the info; if present, copy shared data (we assume name/value strings live
1308	1308	// in the string pool and don't need to be reallocated)
1309	1309	if (m_current_info != NULL)

trunk/src/emu/softlist.h
r29404	r29405
78	78	// construction/destruction
79	79	feature_list_item(const char name = NULL, const char value = NULL)
80	80	: m_next(NULL),
81		m_name(name),
82		m_value(value) { }
	81	m_name(name),
	82	m_value(value) { }
83	83
84	84	// getters
85	85	feature_list_item *next() const { return m_next; }
r29404	r29405
87	87	const char *value() const { return m_value; }
88	88
89	89	private:
90		// internal state
	90	// internal state
91	91	feature_list_item * m_next;
92		const char * m_name;
93		const char * m_value;
	92	const char * m_name;
	93	const char * m_value;
94	94	};
95	95
96	96
r29404	r29405
101	101	{
102	102	friend class softlist_parser;
103	103	friend class simple_list<software_part>;
104
	104
105	105	public:
106	106	// construction/destruction
107	107	software_part(software_info &info, const char name = NULL, const char interface = NULL);
r29404	r29405
121	121
122	122	private:
123	123	// internal state
124		software_part * m_next;
125		software_info & m_info;
126		const char * m_name;
127		const char * m_interface;
	124	software_part * m_next;
	125	software_info & m_info;
	126	const char * m_name;
	127	const char * m_interface;
128	128	simple_list<feature_list_item> m_featurelist;
129	129	dynamic_array<rom_entry> m_romdata;
130	130	};
r29404	r29405
137	137	{
138	138	friend class softlist_parser;
139	139	friend class simple_list<software_info>;
140
	140
141	141	public:
142	142	// construction/destruction
143	143	software_info(software_list_device &list, const char name, const char parent, const char *supported);
144
	144
145	145	// getters
146	146	software_info *next() const { return m_next; }
147	147	software_list_device &list() const { return m_list; }
r29404	r29405
156	156	int num_parts() const { return m_partdata.count(); }
157	157	software_part *first_part() const { return m_partdata.first(); }
158	158	software_part *last_part() const { return m_partdata.last(); }
159
	159
160	160	// additional operations
161	161	software_part find_part(const char partname, const char *interface = NULL);
162	162	bool has_multiple_parts(const char *interface) const;
163	163
164	164	private:
165	165	// internal state
166		software_info * m_next;
167		software_list_device & m_list;
168		UINT32 m_supported;
169		const char * m_shortname;
170		const char * m_longname;
171		const char * m_parentname;
172		const char * m_year; // Copyright year on title screen, actual release dates can be tracked in external resources
173		const char * m_publisher;
	166	software_info * m_next;
	167	software_list_device & m_list;
	168	UINT32 m_supported;
	169	const char * m_shortname;
	170	const char * m_longname;
	171	const char * m_parentname;
	172	const char * m_year; // Copyright year on title screen, actual release dates can be tracked in external resources
	173	const char * m_publisher;
174	174	simple_list<feature_list_item> m_other_info; // Here we store info like developer, serial #, etc. which belong to the software entry as a whole
175	175	simple_list<feature_list_item> m_shared_info; // Here we store info like TV standard compatibility, or add-on requirements, etc. which get inherited
176		// by each part of this software entry (after loading these are stored in partdata->featurelist)
	176	// by each part of this software entry (after loading these are stored in partdata->featurelist)
177	177	simple_list<software_part> m_partdata;
178	178	};
179	179
r29404	r29405
228	228	virtual void device_validity_check(validity_checker &valid) const ATTR_COLD;
229	229
230	230	// configuration state
231		astring m_list_name;
	231	astring m_list_name;
232	232	softlist_type m_list_type;
233	233	const char * m_filter;
234	234
235	235	// internal state
236		bool m_parsed;
237		emu_file m_file;
238		const char * m_description;
239		astring m_errors;
240		simple_list<software_info> m_infolist;
241		const_string_pool m_stringpool;
	236	bool m_parsed;
	237	emu_file m_file;
	238	const char * m_description;
	239	astring m_errors;
	240	simple_list<software_info> m_infolist;
	241	const_string_pool m_stringpool;
242	242	};
243	243
244	244

trunk/src/emu/dioutput.c
r29404	r29405
40	40	if (m_output_name)
41	41	output_set_value(m_output_name, value);
42	42	else
43		fatalerror("Output name not set!");
	43	fatalerror("Output name not set!");
44	44	}
45	45
46	46	void device_output_interface::set_led_value(int value)

trunk/src/emu/devfind.c
r29404	r29405
73	73	mame_printf_error("Tag not defined for required device\n");
74	74	return false;
75	75	}
76
	76
77	77	// just pass through in the found case
78	78	if (found)
79	79	return true;

trunk/src/emu/diserial.h
r29404	r29405
156	156	UINT8 m_rcv_bit_count;
157	157	/* the byte of data received */
158	158	UINT8 m_rcv_byte_received;
159
	159
160	160	bool m_rcv_framing_error;
161	161	bool m_rcv_parity_error;
162	162

trunk/src/emu/mame.c
r29404	r29405
170	170	astring errors;
171	171	options.parse_standard_inis(errors);
172	172	}
173
	173
174	174	// otherwise, perform validity checks before anything else
175	175	if (system != NULL)
176	176	{
r29404	r29405
189	189
190	190	web.set_machine(machine);
191	191	web.push_message("update_machine");
192
	192
193	193	// run the machine
194	194	error = machine.run(firstrun);
195	195	firstrun = false;

trunk/src/emu/rendfont.c
r29404	r29405
392	392	// if that worked, we're done
393	393	if (result)
394	394	{
395		// don't do that - glyphs data point into this array ...
396		// m_rawdata.reset();
	395	// don't do that - glyphs data point into this array ...
	396	// m_rawdata.reset();
397	397	return true;
398	398	}
399	399	}

trunk/src/emu/machine/mc68681.c
r29404	r29405
167	167	{
168	168	LOG(( "68681: Interrupt line not active (IMR & ISR = %02X)\n", ISR & IMR));
169	169	write_irq(CLEAR_LINE);
170		m_read_vector = false; // clear IACK too
	170	m_read_vector = false; // clear IACK too
171	171	}
172	172	};
173	173
r29404	r29405
235	235	// timer output to bit 3?
236	236	if ((OPCR & 0xc) == 0x4)
237	237	{
238		OPR ^= 0x8;
	238	OPR ^= 0x8;
239	239	write_outport(OPR ^ 0xff);
240	240	}
241	241
r29404	r29405
280	280
281	281	// reading this clears all the input change bits
282	282	IPCR &= 0x0f;
283		ISR &= ~INT_INPUT_PORT_CHANGE;
	283	ISR &= ~INT_INPUT_PORT_CHANGE;
284	284	update_interrupts();
285	285	}
286	286	break;
r29404	r29405
304	304	break;
305	305
306	306	case 0x0a: /* 1X/16X Test */
307		r = 0x61; // the old 68681 returned this and it makes Apollo happy
	307	r = 0x61; // the old 68681 returned this and it makes Apollo happy
308	308	break;
309	309
310	310	case 0x0d: /* IP */
311	311	if (!read_inport.isnull())
312	312	{
313		r = read_inport(); // TODO: go away
	313	r = read_inport(); // TODO: go away
314	314	}
315	315	else
316	316	{
317	317	r = IP_last_state;
318	318	}
319	319
320		r \|= 0x80; // bit 7 is always set
	320	r \|= 0x80; // bit 7 is always set
321	321
322	322	// bit 6 is /IACK (note the active-low)
323	323	if (m_read_vector)
r29404	r29405
328	328	{
329	329	r \|= 0x40;
330	330	}
331		break;
	331	break;
332	332
333	333	case 0x0e: /* Start counter command */
334	334	{
r29404	r29405
402	402	// check for pending input port delta interrupts
403	403	if ((((IPCR>>4) & data) & 0x0f) != 0)
404	404	{
405		ISR \|= INT_INPUT_PORT_CHANGE;
	405	ISR \|= INT_INPUT_PORT_CHANGE;
406	406	}
407	407
408	408	m_chanA->ACR_updated();
r29404	r29405
466	466
467	467	if (ACR & 1)
468	468	{
469		ISR \|= INT_INPUT_PORT_CHANGE;
	469	ISR \|= INT_INPUT_PORT_CHANGE;
470	470	update_interrupts();
471	471	}
472	472	}
r29404	r29405
486	486
487	487	if (ACR & 2)
488	488	{
489		ISR \|= INT_INPUT_PORT_CHANGE;
	489	ISR \|= INT_INPUT_PORT_CHANGE;
490	490	update_interrupts();
491	491	}
492	492	}
r29404	r29405
506	506
507	507	if (ACR & 4)
508	508	{
509		ISR \|= INT_INPUT_PORT_CHANGE;
	509	ISR \|= INT_INPUT_PORT_CHANGE;
510	510	update_interrupts();
511	511	}
512	512	}
r29404	r29405
526	526
527	527	if (ACR & 8)
528	528	{
529		ISR \|= INT_INPUT_PORT_CHANGE;
	529	ISR \|= INT_INPUT_PORT_CHANGE;
530	530	update_interrupts();
531	531	}
532	532	}
r29404	r29405
671	671	{
672	672	receive_register_extract();
673	673
674		// printf("%s ch %d rcv complete\n", tag(), m_ch);
	674	// printf("%s ch %d rcv complete\n", tag(), m_ch);
675	675
676	676	if ( rx_enabled )
677	677	{
r29404	r29405
693	693
694	694	void mc68681_channel::tra_complete()
695	695	{
696		// printf("%s ch %d Tx complete\n", tag(), m_ch);
	696	// printf("%s ch %d Tx complete\n", tag(), m_ch);
697	697	tx_ready = 1;
698	698	SR \|= STATUS_TRANSMITTER_READY;
699	699
r29404	r29405
730	730	if ((MR2&0xC0) != 0x80)
731	731	{
732	732	int bit = transmit_register_get_data_bit();
733		// printf("%s ch %d transmit %d\n", tag(), m_ch, bit);
	733	// printf("%s ch %d transmit %d\n", tag(), m_ch, bit);
734	734	if (m_ch == 0)
735	735	{
736	736	m_uart->write_a_tx(bit);
r29404	r29405
740	740	m_uart->write_b_tx(bit);
741	741	}
742	742	}
743		else // must call this to advance the transmitter
	743	else // must call this to advance the transmitter
744	744	{
745	745	transmit_register_get_data_bit();
746	746	}
r29404	r29405
750	750	{
751	751	if (rx_enabled)
752	752	{
753		if (rx_fifo_num > 0)
	753	if (rx_fifo_num > 0)
754	754	{
755	755	SR \|= STATUS_RECEIVER_READY;
756	756	}
r29404	r29405
867	867	rx_fifo_num--;
868	868	update_interrupts();
869	869
870		// printf("Rx read %02x\n", rv);
	870	// printf("Rx read %02x\n", rv);
871	871
872	872	return rv;
873	873	};
r29404	r29405
917	917	CSR = data;
918	918	tx_baud_rate = m_uart->calc_baud(m_ch, data & 0xf);
919	919	rx_baud_rate = m_uart->calc_baud(m_ch, (data>>4) & 0xf);
920		// printf("%s ch %d CSR %02x Tx baud %d Rx baud %d\n", tag(), m_ch, data, tx_baud_rate, rx_baud_rate);
	920	// printf("%s ch %d CSR %02x Tx baud %d Rx baud %d\n", tag(), m_ch, data, tx_baud_rate, rx_baud_rate);
921	921	set_rcv_rate(rx_baud_rate);
922	922	set_tra_rate(tx_baud_rate);
923	923	break;
r29404	r29405
1000	1000	break;
1001	1001	}
1002	1002
1003		// printf("%s ch %d MR1 %02x MR2 %02x => %d bits / char, %d stop bits, parity %d\n", tag(), m_ch, MR1, MR2, (MR1 & 3)+5, stopbits, parity);
	1003	// printf("%s ch %d MR1 %02x MR2 %02x => %d bits / char, %d stop bits, parity %d\n", tag(), m_ch, MR1, MR2, (MR1 & 3)+5, stopbits, parity);
1004	1004
1005	1005	set_data_frame(1, (MR1 & 3)+5, parity, stopbits);
1006	1006	}
r29404	r29405
1092	1092	printf("Write %02x to TX when TX not ready!\n", data);
1093	1093	}*/
1094	1094
1095		// printf("%s ch %d Tx %02x\n", tag(), m_ch, data);
	1095	// printf("%s ch %d Tx %02x\n", tag(), m_ch, data);
1096	1096
1097	1097	tx_ready = 0;
1098	1098	SR &= ~STATUS_TRANSMITTER_READY;

trunk/src/emu/machine/mc68328.h
r29404	r29405
633	633	template<class _Object> static devcb2_base &set_out_spim_callback(device_t &device, _Object object) { return downcast<mc68328_device &>(device).m_out_spim_cb.set_callback(object); }
634	634	template<class _Object> static devcb2_base &set_in_spim_callback(device_t &device, _Object object) { return downcast<mc68328_device &>(device).m_in_spim_cb.set_callback(object); }
635	635	template<class _Object> static devcb2_base &set_spim_xch_trigger_callback(device_t &device, _Object object) { return downcast<mc68328_device &>(device).m_spim_xch_trigger_cb.set_callback(object); }
636
637
	636
	637
638	638	DECLARE_WRITE16_MEMBER(write);
639	639	DECLARE_READ16_MEMBER(read);
640	640	DECLARE_WRITE_LINE_MEMBER(set_penirq_line);
r29404	r29405
699	699
700	700	required_device<cpu_device> m_cpu;
701	701	};
702
703	702
	703
704	704	extern const device_type MC68328;
705	705
706	706	#define MCFG_MC68328_CPU(_tag) \
707	707	mc68328_device::static_set_cpu_tag(*device, "^"_tag);
708
	708
709	709	#define MCFG_MC68328_OUT_PORT_A_CB(_devcb) \
710	710	devcb = &mc68328_device::set_out_port_a_callback(*device, DEVCB2_##_devcb);
711
	711
712	712	#define MCFG_MC68328_OUT_PORT_B_CB(_devcb) \
713	713	devcb = &mc68328_device::set_out_port_b_callback(*device, DEVCB2_##_devcb);
714
	714
715	715	#define MCFG_MC68328_OUT_PORT_C_CB(_devcb) \
716	716	devcb = &mc68328_device::set_out_port_c_callback(*device, DEVCB2_##_devcb);
717
	717
718	718	#define MCFG_MC68328_OUT_PORT_D_CB(_devcb) \
719	719	devcb = &mc68328_device::set_out_port_d_callback(*device, DEVCB2_##_devcb);
720
	720
721	721	#define MCFG_MC68328_OUT_PORT_E_CB(_devcb) \
722	722	devcb = &mc68328_device::set_out_port_e_callback(*device, DEVCB2_##_devcb);
723
	723
724	724	#define MCFG_MC68328_OUT_PORT_F_CB(_devcb) \
725	725	devcb = &mc68328_device::set_out_port_f_callback(*device, DEVCB2_##_devcb);
726
	726
727	727	#define MCFG_MC68328_OUT_PORT_G_CB(_devcb) \
728	728	devcb = &mc68328_device::set_out_port_g_callback(*device, DEVCB2_##_devcb);
729
	729
730	730	#define MCFG_MC68328_OUT_PORT_J_CB(_devcb) \
731	731	devcb = &mc68328_device::set_out_port_j_callback(*device, DEVCB2_##_devcb);
732
	732
733	733	#define MCFG_MC68328_OUT_PORT_K_CB(_devcb) \
734	734	devcb = &mc68328_device::set_out_port_k_callback(*device, DEVCB2_##_devcb);
735
	735
736	736	#define MCFG_MC68328_OUT_PORT_M_CB(_devcb) \
737	737	devcb = &mc68328_device::set_out_port_m_callback(*device, DEVCB2_##_devcb);
738
	738
739	739	#define MCFG_MC68328_IN_PORT_A_CB(_devcb) \
740	740	devcb = &mc68328_device::set_in_port_a_callback(*device, DEVCB2_##_devcb);
741
	741
742	742	#define MCFG_MC68328_IN_PORT_B_CB(_devcb) \
743	743	devcb = &mc68328_device::set_in_port_b_callback(*device, DEVCB2_##_devcb);
744
	744
745	745	#define MCFG_MC68328_IN_PORT_C_CB(_devcb) \
746	746	devcb = &mc68328_device::set_in_port_c_callback(*device, DEVCB2_##_devcb);
747
	747
748	748	#define MCFG_MC68328_IN_PORT_D_CB(_devcb) \
749	749	devcb = &mc68328_device::set_in_port_d_callback(*device, DEVCB2_##_devcb);
750
	750
751	751	#define MCFG_MC68328_IN_PORT_E_CB(_devcb) \
752	752	devcb = &mc68328_device::set_in_port_e_callback(*device, DEVCB2_##_devcb);
753
	753
754	754	#define MCFG_MC68328_IN_PORT_F_CB(_devcb) \
755	755	devcb = &mc68328_device::set_in_port_f_callback(*device, DEVCB2_##_devcb);
756
	756
757	757	#define MCFG_MC68328_IN_PORT_G_CB(_devcb) \
758	758	devcb = &mc68328_device::set_in_port_g_callback(*device, DEVCB2_##_devcb);
759
	759
760	760	#define MCFG_MC68328_IN_PORT_J_CB(_devcb) \
761	761	devcb = &mc68328_device::set_in_port_j_callback(*device, DEVCB2_##_devcb);
762
	762
763	763	#define MCFG_MC68328_IN_PORT_K_CB(_devcb) \
764	764	devcb = &mc68328_device::set_in_port_k_callback(*device, DEVCB2_##_devcb);
765
	765
766	766	#define MCFG_MC68328_IN_PORT_M_CB(_devcb) \
767	767	devcb = &mc68328_device::set_in_port_m_callback(*device, DEVCB2_##_devcb);
768
	768
769	769	#define MCFG_MC68328_OUT_PWM_CB(_devcb) \
770	770	devcb = &mc68328_device::set_out_pwm_callback(*device, DEVCB2_##_devcb);
771
	771
772	772	#define MCFG_MC68328_OUT_SPIM_CB(_devcb) \
773	773	devcb = &mc68328_device::set_out_spim_callback(*device, DEVCB2_##_devcb);
774
	774
775	775	#define MCFG_MC68328_IN_SPIM_CB(_devcb) \
776	776	devcb = &mc68328_device::set_in_spim_callback(*device, DEVCB2_##_devcb);
777
	777
778	778	#define MCFG_MC68328_SPIM_XCH_TRIGGER_CB(_devcb) \
779	779	devcb = &mc68328_device::set_spim_xch_trigger_callback(*device, DEVCB2_##_devcb);
780	780

trunk/src/emu/machine/mc68681.h
r29404	r29405
149	149	PAIR CTR; /* Counter/Timer Preset Value */
150	150	UINT8 IPCR; /* Input Port Control Register */
151	151
152		bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
	152	bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
153	153
154	154	/* state */
155	155	UINT8 IP_last_state; /* last state of IP bits */

trunk/src/emu/machine/lh5810.h
r29404	r29405
43	43
44	44	#define MCFG_LH5810_PORTA_W_CB(_devcb) \
45	45	devcb = &lh5810_device::set_porta_w_callback(*device, DEVCB2_##_devcb);
46
	46
47	47	#define MCFG_LH5810_PORTB_R_CB(_devcb) \
48	48	devcb = &lh5810_device::set_portb_r_callback(*device, DEVCB2_##_devcb);
49
	49
50	50	#define MCFG_LH5810_PORTB_W_CB(_devcb) \
51	51	devcb = &lh5810_device::set_portb_w_callback(*device, DEVCB2_##_devcb);
52
	52
53	53	#define MCFG_LH5810_PORTC_W_CB(_devcb) \
54	54	devcb = &lh5810_device::set_portc_w_callback(*device, DEVCB2_##_devcb);
55
	55
56	56	#define MCFG_LH5810_OUT_INT_CB(_devcb) \
57	57	devcb = &lh5810_device::set_out_int_callback(*device, DEVCB2_##_devcb); //currently unused
58	58
r29404	r29405
76	76	template<class _Object> static devcb2_base &set_portb_w_callback(device_t &device, _Object object) { return downcast<lh5810_device &>(device).m_portb_w_cb.set_callback(object); }
77	77	template<class _Object> static devcb2_base &set_portc_w_callback(device_t &device, _Object object) { return downcast<lh5810_device &>(device).m_portc_w_cb.set_callback(object); }
78	78	template<class _Object> static devcb2_base &set_out_int_callback(device_t &device, _Object object) { return downcast<lh5810_device &>(device).m_out_int_cb.set_callback(object); }
79
	79
80	80	DECLARE_READ8_MEMBER( data_r );
81	81	DECLARE_WRITE8_MEMBER( data_w );
82	82

trunk/src/emu/machine/74145.h
r29404	r29405
23	23
24	24	#define MCFG_TTL74145_OUTPUT_LINE_2_CB(_devcb) \
25	25	devcb = &ttl74145_device::set_output_line_2_callback(*device, DEVCB2_##_devcb);
26
	26
27	27	#define MCFG_TTL74145_OUTPUT_LINE_3_CB(_devcb) \
28	28	devcb = &ttl74145_device::set_output_line_3_callback(*device, DEVCB2_##_devcb);
29
	29
30	30	#define MCFG_TTL74145_OUTPUT_LINE_4_CB(_devcb) \
31	31	devcb = &ttl74145_device::set_output_line_4_callback(*device, DEVCB2_##_devcb);
32
	32
33	33	#define MCFG_TTL74145_OUTPUT_LINE_5_CB(_devcb) \
34	34	devcb = &ttl74145_device::set_output_line_5_callback(*device, DEVCB2_##_devcb);
35
	35
36	36	#define MCFG_TTL74145_OUTPUT_LINE_6_CB(_devcb) \
37	37	devcb = &ttl74145_device::set_output_line_6_callback(*device, DEVCB2_##_devcb);
38
	38
39	39	#define MCFG_TTL74145_OUTPUT_LINE_7_CB(_devcb) \
40	40	devcb = &ttl74145_device::set_output_line_7_callback(*device, DEVCB2_##_devcb);
41
	41
42	42	#define MCFG_TTL74145_OUTPUT_LINE_8_CB(_devcb) \
43	43	devcb = &ttl74145_device::set_output_line_8_callback(*device, DEVCB2_##_devcb);
44
	44
45	45	#define MCFG_TTL74145_OUTPUT_LINE_9_CB(_devcb) \
46	46	devcb = &ttl74145_device::set_output_line_9_callback(*device, DEVCB2_##_devcb);
47	47
r29404	r29405
56	56	public:
57	57	// construction/destruction
58	58	ttl74145_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
59
	59
60	60	template<class _Object> static devcb2_base &set_output_line_0_callback(device_t &device, _Object object) { return downcast<ttl74145_device &>(device).m_output_line_0_cb.set_callback(object); }
61	61	template<class _Object> static devcb2_base &set_output_line_1_callback(device_t &device, _Object object) { return downcast<ttl74145_device &>(device).m_output_line_1_cb.set_callback(object); }
62	62	template<class _Object> static devcb2_base &set_output_line_2_callback(device_t &device, _Object object) { return downcast<ttl74145_device &>(device).m_output_line_2_cb.set_callback(object); }
r29404	r29405
67	67	template<class _Object> static devcb2_base &set_output_line_7_callback(device_t &device, _Object object) { return downcast<ttl74145_device &>(device).m_output_line_7_cb.set_callback(object); }
68	68	template<class _Object> static devcb2_base &set_output_line_8_callback(device_t &device, _Object object) { return downcast<ttl74145_device &>(device).m_output_line_8_cb.set_callback(object); }
69	69	template<class _Object> static devcb2_base &set_output_line_9_callback(device_t &device, _Object object) { return downcast<ttl74145_device &>(device).m_output_line_9_cb.set_callback(object); }
70
	70
71	71	UINT16 read();
72	72	void write(UINT8 data);
73	73	protected:

trunk/src/emu/machine/kr2376.c
r29404	r29405
346	346	ioport_constructor kr2376_device::device_input_ports() const
347	347	{
348	348	return INPUT_PORTS_NAME( kr2376 );
349		}
		No newline at end of file
	349	}

trunk/src/emu/machine/s3c2410.c
r29404	r29405
101	101	void s3c2410_device::device_start()
102	102	{
103	103	s3c24xx_device_start();
104
105		address_space &space = m_cpu->memory().space( AS_PROGRAM);
	104
	105	address_space &space = m_cpu->memory().space( AS_PROGRAM);
106	106	space.install_readwrite_handler( 0x48000000, 0x4800003b, read32_delegate(FUNC(s3c2410_device::s3c24xx_memcon_r), this), write32_delegate(FUNC(s3c2410_device::s3c24xx_memcon_w), this));
107	107	space.install_readwrite_handler( 0x49000000, 0x4900005b, read32_delegate(FUNC(s3c2410_device::s3c24xx_usb_host_r), this), write32_delegate(FUNC(s3c2410_device::s3c24xx_usb_host_w), this));
108	108	space.install_readwrite_handler( 0x4a000000, 0x4a00001f, read32_delegate(FUNC(s3c2410_device::s3c24xx_irq_r), this), write32_delegate(FUNC(s3c2410_device::s3c24xx_irq_w), this));

trunk/src/emu/machine/com8116.h
r29404	r29405
90	90	int m_fx4;
91	91	int m_fr;
92	92	int m_ft;
93
	93
94	94	const int *m_fr_divisors;
95	95	const int *m_ft_divisors;
96	96

trunk/src/emu/machine/kr2376.h
r29404	r29405
59	59	~kr2376_device() {}
60	60
61	61	template<class _Object> static devcb2_base &set_strobe_wr_callback(device_t &device, _Object object) { return downcast<kr2376_device &>(device).m_write_strobe.set_callback(object); }
62
	62
63	63	/* keyboard data */
64	64	DECLARE_READ8_MEMBER( data_r );
65	65
r29404	r29405
74	74	virtual void device_start();
75	75	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
76	76	virtual ioport_constructor device_input_ports() const;
77
	77
78	78	private:
79	79	// internal state
80	80	int m_pins[41];
r29404	r29405
91	91	/* timers */
92	92	emu_timer m_scan_timer; / keyboard scan timer */
93	93	devcb2_write_line m_write_strobe;
94
	94
95	95	enum
96	96	{
97	97	TIMER_SCAN_TICK
98	98	};
99
	99
100	100	void change_output_lines();
101	101	void clock_scan_counters();
102	102	void detect_keypress();

trunk/src/emu/machine/s3c2410.h
r29404	r29405
16	16
17	17	#define MCFG_S3C2410_ADD(_tag, _clock, _config, _palette_tag) \
18	18	MCFG_DEVICE_ADD(_tag, S3C2410, _clock) \
19		MCFG_DEVICE_CONFIG(_config) \
	19	MCFG_DEVICE_CONFIG(_config) \
20	20	s3c2410_device::static_set_palette_tag(*device, "^" _palette_tag);
21	21
22	22	#define S3C2410_INTERFACE(name) \
r29404	r29405
454	454	#define S3C24XX_DMA_COUNT 4
455	455	#define S3C24XX_SPI_COUNT 2
456	456
457		class s3c2410_device : public device_t,
	457	class s3c2410_device : public device_t,
458	458	public s3c2410_interface
459	459	{
460	460	public:
r29404	r29405
465	465	static void static_set_palette_tag(device_t &device, const char *tag);
466	466
467	467	DECLARE_WRITE_LINE_MEMBER( frnb_w );
468
	468
469	469	// device-level overrides
470	470	virtual void device_config_complete();
471	471	virtual void device_start();
r29404	r29405
475	475	required_device<palette_device> m_palette;
476	476	public:
477	477	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
478
	478
479	479	void s3c24xx_reset();
480	480	inline int iface_core_pin_r(int pin);
481	481	void s3c24xx_lcd_reset();
r29404	r29405
633	633	void s3c24xx_spi_w(UINT32 ch, UINT32 offset, UINT32 data, UINT32 mem_mask);
634	634	READ32_MEMBER( s3c24xx_spi_0_r );
635	635	READ32_MEMBER( s3c24xx_spi_1_r );
636		WRITE32_MEMBER( s3c24xx_spi_0_w );
	636	WRITE32_MEMBER( s3c24xx_spi_0_w );
637	637	WRITE32_MEMBER( s3c24xx_spi_1_w );
638	638	void s3c24xx_sdi_reset();
639	639	READ32_MEMBER( s3c24xx_sdi_r );
r29404	r29405
661	661	void s3c2410_touch_screen( int state);
662	662	void s3c2410_request_eint( UINT32 number);
663	663	void s3c2410_nand_calculate_mecc( UINT8 data, UINT32 size, UINT8 mecc);
664
	664
665	665	/*******************************************************************************
666		TYPE DEFINITIONS
	666	TYPE DEFINITIONS
667	667	*******************************************************************************/
668	668
669	669	struct s3c24xx_memcon_regs_t
r29404	r29405
1070	1070	devcb_resolved_write8 m_command_w;
1071	1071	devcb_resolved_write8 m_address_w;
1072	1072	devcb_resolved_read8 m_nand_data_r;
1073		devcb_resolved_write8 m_nand_data_w;
	1073	devcb_resolved_write8 m_nand_data_w;
1074	1074	};
1075	1075
1076	1076	extern const device_type S3C2410;

trunk/src/emu/machine/s3c24xx.inc
r29404	r29405
86	86	/* ... */
87	87
88	88	void S3C24_CLASS_NAME::s3c24xx_reset()
89		{
	89	{
90	90	verboselog( machine(), 1, "reset\n");
91	91	m_cpu->reset();
92	92	this->reset();
r29404	r29405
3472	3472
3473	3473	void S3C24_CLASS_NAME::s3c24xx_device_start()
3474	3474	{
3475
3476	3475	verboselog( machine(), 1, "s3c24xx device start\n");
3477	3476	m_pin_r.resolve(m_iface_core.pin_r, *this);
3478	3477	m_pin_w.resolve(m_iface_core.pin_w, *this);

trunk/src/emu/machine/bcreader.c
r29404	r29405
4	4
5	5	Generic barcode reader emulation.
6	6
7		This device only provides the storage of the actual barcode, entered
8		by the user via Internal UI, both as a raw strip of pixels (up to 95,
9		for an EAN-13 barcode) and as an array of 0-9 digits.
10
11		It is up to the driver to handle the serial transfer of the data to
12		the emulated machine, depending on the used protocol
13
14		E.g. Bandai Datach games directly read the raw pixel sequence of
15		black/white bars;
16		OTOH Barcode Battle (used by Barcode World for NES and a few SNES
17		titles) sends the digits as sequences of 20 bytes (13 for the code,
18		suitably padded for shorted codes, followed by a signature) and the
19		actual serial transmission to the console is up to the slot device
20		connected to the NES/SNES controller port (yet to be emulated, in this
21		case)
	7	This device only provides the storage of the actual barcode, entered
	8	by the user via Internal UI, both as a raw strip of pixels (up to 95,
	9	for an EAN-13 barcode) and as an array of 0-9 digits.
22	10
	11	It is up to the driver to handle the serial transfer of the data to
	12	the emulated machine, depending on the used protocol
	13
	14	E.g. Bandai Datach games directly read the raw pixel sequence of
	15	black/white bars;
	16	OTOH Barcode Battle (used by Barcode World for NES and a few SNES
	17	titles) sends the digits as sequences of 20 bytes (13 for the code,
	18	suitably padded for shorted codes, followed by a signature) and the
	19	actual serial transmission to the console is up to the slot device
	20	connected to the NES/SNES controller port (yet to be emulated, in this
	21	case)
	22
23	23	Note: we currently support the following barcode formats
24	24	* UPC-A: 12 digits
25	25	* EAN-13: 13 digits (extension of the former)
26		* EAN-8: 8 digits (same encoding as UPC-A, but 4-digits blocks instead
27		of 6-digits blocks)
	26	* EAN-8: 8 digits (same encoding as UPC-A, but 4-digits blocks instead
	27	of 6-digits blocks)
28	28	Notice that since EAN-13 is an extension of UPC-A, we just treat UPC-A
29		as an EAN-13 code with leading '0'. If any barcode reader shall be found
30		which supports the older format only, this shall be changed
	29	as an EAN-13 code with leading '0'. If any barcode reader shall be found
	30	which supports the older format only, this shall be changed
31	31
32
33		TODO: add support for UPC-E barcodes? these are 8 digits barcodes with 17
34		black stripes (they are compressed UPC-A codes). Datach reader does not
35		support these, so it is low priority
36	32
37
38		TODO 2: verify barcode checksum in is_valid() and not only length, so
39		that we can then use the actual last digit in the decode function below,
40		rather than replacing it with the checksum value
41
42
43		TODO 3: possibly the white spaces before the actual barcode (see the
44		61 white pixels sent by read_pixel() before and after the code), shall
45		be moved to the specific implementations to emulate different "sensitivity"
46		of the readers? Bandai Datach seems to need at least 32 pixels...
	33	TODO: add support for UPC-E barcodes? these are 8 digits barcodes with 17
	34	black stripes (they are compressed UPC-A codes). Datach reader does not
	35	support these, so it is low priority
47	36
	37
	38	TODO 2: verify barcode checksum in is_valid() and not only length, so
	39	that we can then use the actual last digit in the decode function below,
	40	rather than replacing it with the checksum value
	41
	42
	43	TODO 3: possibly the white spaces before the actual barcode (see the
	44	61 white pixels sent by read_pixel() before and after the code), shall
	45	be moved to the specific implementations to emulate different "sensitivity"
	46	of the readers? Bandai Datach seems to need at least 32 pixels...
	47
48	48	***************************************************************************/
49	49
50	50	#include "emu.h"
r29404	r29405
85	85
86	86	//-------------------------------------------------
87	87	// Barcode Decoding - convert the entered sequence
88		// of digits into a sequence of B/W pixels (the
	88	// of digits into a sequence of B/W pixels (the
89	89	// actual bars) - each digit corresponds to 7 pixels
90	90	// 0 is black, 1 is white
91	91	//-------------------------------------------------
r29404	r29405
140	140	if (len == 13)
141	141	{
142	142	// UPC-A and EAN-13
143
	143
144	144	m_pixel_data[output++] = 0;
145	145	m_pixel_data[output++] = 1;
146	146	m_pixel_data[output++] = 0;
147
	147
148	148	for (int i = 1; i < 7; i++)
149	149	{
150	150	if (bcread_parity_type[m_byte_data[0]][i - 1])
r29404	r29405
158	158	m_pixel_data[output++] = bcread_data_LE[m_byte_data[i]][j];
159	159	}
160	160	}
161
	161
162	162	m_pixel_data[output++] = 1;
163	163	m_pixel_data[output++] = 0;
164	164	m_pixel_data[output++] = 1;
165	165	m_pixel_data[output++] = 0;
166	166	m_pixel_data[output++] = 1;
167
	167
168	168	for (int i = 7; i < 12; i++)
169	169	{
170	170	for (int j = 0; j < 7; j++)
r29404	r29405
178	178	else if (len == 8)
179	179	{
180	180	// EAN-8 (same encoding as UPC-A, but only 4+4 digits, instead of 6+6)
181
	181
182	182	m_pixel_data[output++] = 0;
183	183	m_pixel_data[output++] = 1;
184	184	m_pixel_data[output++] = 0;
185
	185
186	186	for (int i = 0; i < 4; i++)
187	187	{
188	188	for (int j = 0; j < 7; j++)
189	189	m_pixel_data[output++] = bcread_data_LO[m_byte_data[i]][j];
190	190	}
191
	191
192	192	m_pixel_data[output++] = 1;
193	193	m_pixel_data[output++] = 0;
194	194	m_pixel_data[output++] = 1;
195	195	m_pixel_data[output++] = 0;
196	196	m_pixel_data[output++] = 1;
197
	197
198	198	for (int i = 4; i < 7; i++)
199	199	{
200	200	for (int j = 0; j < 7; j++)
201	201	m_pixel_data[output++] = bcread_data_RE[m_byte_data[i]][j];
202	202	}
203
	203
204	204	// ignore the last digit and compute it as checksum of the first 12
205	205	for (int i = 0; i < 7; i++)
206	206	sum += (i & 1) ? (m_byte_data[i] * 1) : (m_byte_data[i] * 3);
207	207	}
208
	208
209	209	if (m_pixel_data)
210	210	{
211	211	sum = (10 - (sum % 10)) % 10;
212	212	if (sum != m_byte_data[len - 1])
213		logerror("WARNING: wrong checksum detected in the barcode! chksum %d last digit %d\n",
	213	logerror("WARNING: wrong checksum detected in the barcode! chksum %d last digit %d\n",
214	214	sum, m_byte_data[len - 1]);
215
	215
216	216	for (int i = 0; i < 7; i++)
217	217	m_pixel_data[output++] = bcread_data_RE[sum][i];
218
	218
219	219	m_pixel_data[output++] = 0;
220	220	m_pixel_data[output++] = 1;
221	221	m_pixel_data[output++] = 0;
222	222	}
223
	223
224	224	m_byte_length = len;
225	225	m_pixel_length = output;
226	226
227		// printf("byte len %d - pixel len\n", m_byte_length, m_pixel_length);
	227	// printf("byte len %d - pixel len\n", m_byte_length, m_pixel_length);
228	228	}
229	229
230	230
231	231	//-------------------------------------------------
232	232	// write_code - invoked by UI, stores the barcode
233		// both as an array of digits and as a sequence
	233	// both as an array of digits and as a sequence
234	234	// of B/W pixels (the actual bars)
235	235	//-------------------------------------------------
236	236
r29404	r29405
322	322	return 0;
323	323	}
324	324	}
325
	325
326	326	// no pending transfer = black pixel = 0
327	327	return 0;
328	328	}

trunk/src/emu/machine/i8251.c
r29404	r29405
686	686	WRITE_LINE_MEMBER(i8251_device::write_rxd)
687	687	{
688	688	m_rxd = state;
689		// device_serial_interface::rx_w(state);
	689	// device_serial_interface::rx_w(state);
690	690	}
691	691
692	692	WRITE_LINE_MEMBER(i8251_device::write_cts)

trunk/src/emu/machine/bcreader.h
r29404	r29405
31	31	// TODO: add checksum validation!
32	32	bool is_valid(int len) { return (len != 12 && len != 13 && len != 8) ? FALSE : TRUE; }
33	33	void decode(int len);
34
	34
35	35	protected:
36	36	// device-level overrides
37	37	virtual void device_start();
38
	38
39	39	UINT8 m_byte_data[13];
40	40	UINT8 m_pixel_data[100];
41	41	int m_byte_length;

trunk/src/emu/machine/upd765.c
r29404	r29405
133	133	intrq_cb.resolve_safe();
134	134	drq_cb.resolve_safe();
135	135	hdl_cb.resolve_safe();
136
	136
137	137	for(int i=0; i != 4; i++) {
138	138	char name[2];
139	139	flopi[i].tm = timer_alloc(i);

trunk/src/emu/machine/tmp68301.h
r29404	r29405
28	28
29	29	template<class _Object> static devcb2_base &set_in_parallel_callback(device_t &device, _Object object) { return downcast<tmp68301_device &>(device).m_in_parallel_cb.set_callback(object); }
30	30	template<class _Object> static devcb2_base &set_out_parallel_callback(device_t &device, _Object object) { return downcast<tmp68301_device &>(device).m_out_parallel_cb.set_callback(object); }
31
	31
32	32	// Hardware Registers
33	33	DECLARE_READ16_MEMBER( regs_r );
34	34	DECLARE_WRITE16_MEMBER( regs_w );
r29404	r29405
58	58	private:
59	59	devcb2_read16 m_in_parallel_cb;
60	60	devcb2_write16 m_out_parallel_cb;
61
	61
62	62	// internal state
63	63	UINT16 m_regs[0x400];
64	64

trunk/src/emu/machine/mm58167.c
r29404	r29405
1	1	/**********************************************************************
2	2
3	3	mm58167.c - National Semiconductor MM58167 real-time clock emulation
4
	4
5	5	TODO: alarms and IRQs not used by the Apple /// and aren't implemented.
6
	6
7	7	**********************************************************************/
8	8
9	9	#include "mm58167.h"
r29404	r29405
18	18	// registers (0-7 are the live data, 8-f are the setting for the compare IRQ)
19	19	typedef enum
20	20	{
21		R_CNT_MILLISECONDS = 0, // 0 = milliseconds
22		R_CNT_HUNDTENTHS, // 1 = hundreds and tenths of seconds
23		R_CNT_SECONDS, // 2 = seconds
24		R_CNT_MINUTES, // 3 = minutes
25		R_CNT_HOURS, // 4 = hours
26		R_CNT_DAYOFWEEK, // 5 = day of the week
27		R_CNT_DAYOFMONTH, // 6 = day of the month
28		R_CNT_MONTH, // 7 = month
29		R_RAM_MILLISECONDS, // 8 = milliseconds
30		R_RAM_HUNDTENTHS, // 9 = hundreds and tenths of seconds
31		R_RAM_SECONDS, // a = seconds
32		R_RAM_MINUTES, // b = minutes
33		R_RAM_HOURS, // c = hours
34		R_RAM_DAYOFWEEK, // d = day of the week
35		R_RAM_DAYOFMONTH, // e = day of the month
36		R_RAM_MONTH, // f = month
37		R_CTL_IRQSTATUS, // 10 = IRQ status (b7 = compare, b6 = 10th sec, b5 = sec, b4 = min, b3 = hour, b2 = day, b1 = week, b0 = month)
38		R_CTL_IRQCONTROL, // 11 = IRQ control (same bit layout as status, but write here to enable/disable/clear)
39		R_CTL_RESETCOUNTERS, // 12 = reset counters
40		R_CTL_RESETRAM, // 13 = reset RAM
41		R_CTL_STATUS, // 14 = status bit
42		R_CTL_GOCMD, // 15 = GO Command
43		R_CTL_STANDBYIRQ, // 16 = standby IRQ
44		R_CTL_TESTMODE // 17 = test mode
	21	R_CNT_MILLISECONDS = 0, // 0 = milliseconds
	22	R_CNT_HUNDTENTHS, // 1 = hundreds and tenths of seconds
	23	R_CNT_SECONDS, // 2 = seconds
	24	R_CNT_MINUTES, // 3 = minutes
	25	R_CNT_HOURS, // 4 = hours
	26	R_CNT_DAYOFWEEK, // 5 = day of the week
	27	R_CNT_DAYOFMONTH, // 6 = day of the month
	28	R_CNT_MONTH, // 7 = month
	29	R_RAM_MILLISECONDS, // 8 = milliseconds
	30	R_RAM_HUNDTENTHS, // 9 = hundreds and tenths of seconds
	31	R_RAM_SECONDS, // a = seconds
	32	R_RAM_MINUTES, // b = minutes
	33	R_RAM_HOURS, // c = hours
	34	R_RAM_DAYOFWEEK, // d = day of the week
	35	R_RAM_DAYOFMONTH, // e = day of the month
	36	R_RAM_MONTH, // f = month
	37	R_CTL_IRQSTATUS, // 10 = IRQ status (b7 = compare, b6 = 10th sec, b5 = sec, b4 = min, b3 = hour, b2 = day, b1 = week, b0 = month)
	38	R_CTL_IRQCONTROL, // 11 = IRQ control (same bit layout as status, but write here to enable/disable/clear)
	39	R_CTL_RESETCOUNTERS, // 12 = reset counters
	40	R_CTL_RESETRAM, // 13 = reset RAM
	41	R_CTL_STATUS, // 14 = status bit
	42	R_CTL_GOCMD, // 15 = GO Command
	43	R_CTL_STANDBYIRQ, // 16 = standby IRQ
	44	R_CTL_TESTMODE // 17 = test mode
45	45	} mm58167_regs_t;
46	46
47	47	//-------------------------------------------------
r29404	r29405
81	81	{
82	82	set_current_time(machine());
83	83
84		m_regs[R_CTL_STATUS] = 0; // not busy
	84	m_regs[R_CTL_STATUS] = 0; // not busy
85	85	m_milliseconds = 0;
86	86	}
87	87
r29404	r29405
116	116
117	117	void mm58167_device::rtc_clock_updated(int year, int month, int day, int day_of_week, int hour, int minute, int second)
118	118	{
119		m_regs[R_CNT_SECONDS] = make_bcd(second); // seconds (BCD)
120		m_regs[R_CNT_MINUTES] = make_bcd(minute); // minutes (BCD)
121		m_regs[R_CNT_HOURS] = make_bcd(hour); // hour (BCD)
122		m_regs[R_CNT_DAYOFWEEK] = make_bcd(day_of_week); // day of the week (BCD)
123		m_regs[R_CNT_DAYOFMONTH] = make_bcd(day); // day of the month (BCD)
124		m_regs[R_CNT_MONTH] = make_bcd(month); // month (BCD)
	119	m_regs[R_CNT_SECONDS] = make_bcd(second); // seconds (BCD)
	120	m_regs[R_CNT_MINUTES] = make_bcd(minute); // minutes (BCD)
	121	m_regs[R_CNT_HOURS] = make_bcd(hour); // hour (BCD)
	122	m_regs[R_CNT_DAYOFWEEK] = make_bcd(day_of_week); // day of the week (BCD)
	123	m_regs[R_CNT_DAYOFMONTH] = make_bcd(day); // day of the month (BCD)
	124	m_regs[R_CNT_MONTH] = make_bcd(month); // month (BCD)
125	125	}
126	126
127	127	READ8_MEMBER(mm58167_device::read)
128	128	{
129		// printf("read reg %x = %02x\n", offset, m_regs[offset]);
	129	// printf("read reg %x = %02x\n", offset, m_regs[offset]);
130	130	return m_regs[offset];
131	131	}
132	132
133	133	WRITE8_MEMBER(mm58167_device::write)
134	134	{
135		// printf("%02x to reg %x\n", data, offset);
	135	// printf("%02x to reg %x\n", data, offset);
136	136
137	137	if ((offset >= R_RAM_MILLISECONDS) && (offset != R_CTL_IRQSTATUS))
138	138	{
r29404	r29405
149	149	case R_CTL_RESETRAM:
150	150	if (data == 0xff)
151	151	{
152		for (int i = R_RAM_MILLISECONDS; i < R_CTL_IRQSTATUS; i++)
	152	for (int i = R_RAM_MILLISECONDS; i < R_CTL_IRQSTATUS; i++)
153	153	{
154	154	m_regs[i] = 0;
155	155	}
r29404	r29405
159	159	case R_CTL_IRQCONTROL:
160	160	if (data != 0)
161	161	{
162		logerror("MM58167: IRQs not implemented\n");
	162	logerror("MM58167: IRQs not implemented\n");
163	163	}
164	164	break;
165	165	}
166	166	}
167

trunk/src/emu/machine/rp5c15.h
r29404	r29405
52	52	public:
53	53	// construction/destruction
54	54	rp5c15_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
55
	55
56	56	template<class _Object> static devcb2_base &set_out_alarm_callback(device_t &device, _Object object) { return downcast<rp5c15_device &>(device).m_out_alarm_cb.set_callback(object); }
57	57	template<class _Object> static devcb2_base &set_out_clkout_callback(device_t &device, _Object object) { return downcast<rp5c15_device &>(device).m_out_clkout_cb.set_callback(object); }
58	58

trunk/src/emu/machine/mm58167.h
r29404	r29405
1	1	/**********************************************************************
2	2
3	3	mm58167.h - National Semiconductor MM58167 real-time clock emulation
4
5		license: MAME, BSD-3-Clause, LGPL v2
6		copyright-holders: R. Belmont
7	4
	5	license: MAME, BSD-3-Clause, LGPL v2
	6	copyright-holders: R. Belmont
	7
8	8	**********************************************************************/
9	9
10	10	#pragma once

trunk/src/emu/machine/hd63450.c
r29404	r29405
61	61	// get the CPU device
62	62	m_cpu = machine().device<cpu_device>(m_cpu_tag);
63	63	assert(m_cpu != NULL);
64
	64
65	65	// resolve callbacks
66	66	m_dma_end.resolve();
67	67	m_dma_error.resolve_safe();
r29404	r29405
73	73	m_dma_write_1.resolve();
74	74	m_dma_write_2.resolve();
75	75	m_dma_write_3.resolve();
76
	76
77	77	// Initialise timers and registers
78	78	for (int x = 0; x < 4 ; x++)
79	79	{
r29404	r29405
86	86	READ16_MEMBER(hd63450_device::read)
87	87	{
88	88	int channel,reg;
89
	89
90	90	channel = (offset & 0x60) >> 5;
91	91	reg = offset & 0x1f;
92	92
r29404	r29405
321	321	address_space &space = m_cpu->space(AS_PROGRAM);
322	322	int data;
323	323	int datasize = 1;
324
	324
325	325	if(m_in_progress[x] != 0) // DMA in progress in channel x
326	326	{
327	327	if(m_reg[x].ocr & 0x80) // direction: 1 = device -> memory

trunk/src/emu/machine/hd63450.h
r29404	r29405
16	16
17	17	#define MCFG_HD63450_DMA_READ_1_CB(_devcb) \
18	18	devcb = &hd63450_device::set_dma_read_1_callback(*device, DEVCB2_##_devcb);
19
	19
20	20	#define MCFG_HD63450_DMA_READ_2_CB(_devcb) \
21	21	devcb = &hd63450_device::set_dma_read_2_callback(*device, DEVCB2_##_devcb);
22	22
23	23	#define MCFG_HD63450_DMA_READ_3_CB(_devcb) \
24	24	devcb = &hd63450_device::set_dma_read_3_callback(*device, DEVCB2_##_devcb);
25
	25
26	26	#define MCFG_HD63450_DMA_WRITE_0_CB(_devcb) \
27	27	devcb = &hd63450_device::set_dma_write_0_callback(*device, DEVCB2_##_devcb);
28	28
29	29	#define MCFG_HD63450_DMA_WRITE_1_CB(_devcb) \
30	30	devcb = &hd63450_device::set_dma_write_1_callback(*device, DEVCB2_##_devcb);
31
	31
32	32	#define MCFG_HD63450_DMA_WRITE_2_CB(_devcb) \
33	33	devcb = &hd63450_device::set_dma_write_2_callback(*device, DEVCB2_##_devcb);
34
	34
35	35	#define MCFG_HD63450_DMA_WRITE_3_CB(_devcb) \
36	36	devcb = &hd63450_device::set_dma_write_3_callback(*device, DEVCB2_##_devcb);
37
38	37
	38
39	39	struct hd63450_regs
40	40	{ // offsets in bytes
41	41	unsigned char csr; // [00] Channel status register (R/W)
r29404	r29405
81	81	template<class _Object> static devcb2_base &set_dma_write_0_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_write_0.set_callback(object); }
82	82	template<class _Object> static devcb2_base &set_dma_write_1_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_write_1.set_callback(object); }
83	83	template<class _Object> static devcb2_base &set_dma_write_2_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_write_2.set_callback(object); }
84		template<class _Object> static devcb2_base &set_dma_write_3_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_write_3.set_callback(object); }
	84	template<class _Object> static devcb2_base &set_dma_write_3_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_write_3.set_callback(object); }
85	85
86	86	DECLARE_READ16_MEMBER( read );
87	87	DECLARE_WRITE16_MEMBER( write );
88
	88
89	89	void single_transfer(int x);
90	90	void set_timer(int channel, attotime tm);
91	91	int get_vector(int channel);
92	92	int get_error_vector(int channel);
93
	93
94	94	protected:
95	95	// device-level overrides
96	96	virtual void device_config_complete();
r29404	r29405
107	107	devcb2_write8 m_dma_write_1;
108	108	devcb2_write8 m_dma_write_2;
109	109	devcb2_write8 m_dma_write_3;
110
	110
111	111	// internal state
112	112	hd63450_regs m_reg[4];
113	113	emu_timer* m_timer[4]; // for timing data reading/writing each channel

trunk/src/emu/machine/z80dma.c
r29404	r29405
897	897	WRITE_LINE_MEMBER(z80dma_device::bai_w)
898	898	{
899	899	}
900

trunk/src/emu/machine/smc92x4.c
r29404	r29405
189	189
190	190	smc92x4_device::smc92x4_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
191	191	: device_t(mconfig, SMC92X4, "SMC 9224/9234 Hard/Floppy Disk Controller", tag, owner, clock, "smc92x4", __FILE__),
192		m_out_intrq(*this),
193		m_out_dip(*this),
194		m_out_auxbus(*this),
195		m_in_auxbus(*this),
196		m_in_dma(*this),
197		m_out_dma(*this)
	192	m_out_intrq(*this),
	193	m_out_dip(*this),
	194	m_out_auxbus(*this),
	195	m_in_auxbus(*this),
	196	m_in_dma(*this),
	197	m_out_dma(*this)
198	198	{
199	199	}
200	200

trunk/src/emu/machine/mb87078.c
r29404	r29405
119	119	void mb87078_device::device_start()
120	120	{
121	121	m_gain_changed_cb.resolve_safe();
122
	122
123	123	save_item(NAME(m_channel_latch));
124	124	save_item(NAME(m_reset_comp));
125	125	save_item(NAME(m_latch[0]));

trunk/src/emu/machine/tms5501.c
r29404	r29405
443	443	}
444	444	}
445	445
446		m_xi7 = state;
	446	m_xi7 = state;
447	447	}
448	448
449	449
r29404	r29405
458	458	set_interrupt(IRQ_SENS);
459	459	}
460	460
461		m_sens = state;
	461	m_sens = state;
462	462	}
463	463
464	464
r29404	r29405
501	501	}
502	502	else
503	503	{
504		m_write_irq(CLEAR_LINE);
	504	m_write_irq(CLEAR_LINE);
505	505	}
506	506	}
507	507
r29404	r29405
522	522	m_irq &= ~(1 << i);
523	523
524	524	check_interrupt();
525
	525
526	526	if (LOG) logerror("%s: TMS5501 '%s' Interrupt Acknowledge %02x\n", machine().describe_context(), tag(), rst);
527	527	break;
528	528	}

trunk/src/emu/machine/smc92x4.h
r29404	r29405
223	223	// We expect the embedding board to replace the drive according to the
224	224	// select lines.
225	225	legacy_floppy_image_device *m_drive;
226		mfm_harddisk_device *m_harddisk;
	226	mfm_harddisk_device *m_harddisk;
227	227	};
228	228
229	229	#define MCFG_SMC92X4_ADD(_tag, _intrf) \

trunk/src/emu/machine/k053252.h
r29404	r29405
19	19	devcb = &k053252_device::set_int2_ack_callback(*device, DEVCB2_##_devcb);
20	20
21	21	/*#define MCFG_K053252_INT_TIME_CB(_devcb) \
22		devcb = &k053252_device::set_int_time_callback(device, DEVCB2_##_devcb); /
	22	devcb = &k053252_device::set_int_time_callback(device, DEVCB2_##_devcb); /
23	23
24	24	#define MCFG_K053252_OFFSETS(_offsx, _offsy) \
25	25	k053252_device::set_offsets(*device, _offsx, _offsy);
r29404	r29405
38	38	template<class _Object> static devcb2_base &set_int2_ack_callback(device_t &device, _Object object) { return downcast<k053252_device &>(device).m_int2_ack_cb.set_callback(object); }
39	39	//template<class _Object> static devcb2_base &set_int_time_callback(device_t &device, _Object object) { return downcast<k053252_device &>(device).m_int_time_cb.set_callback(object); }
40	40	static void set_offsets(device_t &device, int offsx, int offsy) { downcast<k053252_device &>(device).m_offsx = offsx; downcast<k053252_device &>(device).m_offsy = offsy;}
41
	41
42	42	DECLARE_READ8_MEMBER( read ); // CCU registers
43	43	DECLARE_WRITE8_MEMBER( write );
44	44

trunk/src/emu/machine/6850acia.c
r29404	r29405
329	329	{
330	330	m_status &= ~SR_DCD;
331	331	}
332
	332
333	333	m_rx_counter++;
334	334
335	335	switch (m_rx_state)
r29404	r29405
430	430	m_rx_counter = 0;
431	431
432	432	if (LOG) logerror("MC6850 '%s': RX STOP BIT\n", tag());
433
	433
434	434	if (!m_rxd)
435	435	{
436	436	m_status \|= SR_FE;
r29404	r29405
536	536	if (m_tx_counter == m_divide)
537	537	{
538	538	m_tx_counter = 0;
539
	539
540	540	m_tx_bits++;
541	541
542	542	if (LOG) logerror("MC6850 '%s': TX STOP BIT %d\n", tag(), m_tx_bits);

trunk/src/emu/machine/mb87078.h
r29404	r29405
25	25	public:
26	26	mb87078_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
27	27	~mb87078_device() {}
28
	28
29	29	template<class _Object> static devcb2_base &set_gain_changed_callback(device_t &device, _Object object) { return downcast<mb87078_device &>(device).m_gain_changed_cb.set_callback(object); }
30	30
31	31	void data_w(int data, int dsel);
r29404	r29405
57	57	int m_channel_latch; /* current channel */
58	58	UINT8 m_latch[2][4]; /* 6bit+3bit 4 data latches */
59	59	UINT8 m_reset_comp;
60
	60
61	61	devcb2_write8 m_gain_changed_cb;
62	62	};
63	63

trunk/src/emu/machine/mc2661.h
r29404	r29405
78	78	// ======================> mc2661_device
79	79
80	80	class mc2661_device : public device_t,
81		public device_serial_interface
	81	public device_serial_interface
82	82	{
83	83	public:
84	84	// construction/destruction

trunk/src/emu/machine/mc6846.h
r29404	r29405
18	18
19	19	#define MCFG_MC6846_OUT_CP2_CB(_devcb) \
20	20	devcb = &mc6846_device::set_out_cp2_callback(*device, DEVCB2_##_devcb);
21
	21
22	22	#define MCFG_MC6846_IN_PORT_CB(_devcb) \
23	23	devcb = &mc6846_device::set_in_port_callback(*device, DEVCB2_##_devcb);
24	24
r29404	r29405
41	41	template<class _Object> static devcb2_base &set_in_port_callback(device_t &device, _Object object) { return downcast<mc6846_device &>(device).m_in_port_cb.set_callback(object); }
42	42	template<class _Object> static devcb2_base &set_out_cto_callback(device_t &device, _Object object) { return downcast<mc6846_device &>(device).m_out_cto_cb.set_callback(object); }
43	43	template<class _Object> static devcb2_base &set_irq_callback(device_t &device, _Object object) { return downcast<mc6846_device &>(device).m_irq_cb.set_callback(object); }
44
	44
45	45	/* interface to CPU via address/data bus*/
46	46	DECLARE_READ8_MEMBER(read);
47	47	DECLARE_WRITE8_MEMBER(write);

trunk/src/emu/machine/laserdsc.c
r29404	r29405
314	314	// if we have a palette and it's not started, wait for it
315	315	if (m_overlay_palette != NULL && !m_overlay_palette->started())
316	316	throw device_missing_dependencies();
317
	317
318	318	// initialize the various pieces
319	319	init_disc();
320	320	init_video();
r29404	r29405
373	373	{
374	374	texture_format texformat = !m_overupdate_ind16.isnull() ? TEXFORMAT_PALETTE16 : TEXFORMAT_RGB32;
375	375	if (m_overlay_palette == NULL && texformat == TEXFORMAT_PALETTE16)
376		mame_printf_error("Overlay screen does not have palette defined\n");
	376	mame_printf_error("Overlay screen does not have palette defined\n");
377	377	}
378	378
379	379	//-------------------------------------------------

trunk/src/emu/machine/hd64610.h
r29404	r29405
36	36
37	37	#define MCFG_HD64610_OUT_IRQ_CB(_devcb) \
38	38	devcb = &hd64610_device::set_out_irq_callback(*device, DEVCB2_##_devcb);
39
	39
40	40	#define MCFG_HD64610_OUT_1HZ_CB(_devcb) \
41	41	devcb = &hd64610_device::set_out_1hz_callback(*device, DEVCB2_##_devcb);
42
43	42
	43
44	44	//**************************************************************************
45	45	// TYPE DEFINITIONS
46	46	//**************************************************************************
r29404	r29405
54	54	public:
55	55	// construction/destruction
56	56	hd64610_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
57
	57
58	58	template<class _Object> static devcb2_base &set_out_irq_callback(device_t &device, _Object object) { return downcast<hd64610_device &>(device).m_out_irq_cb.set_callback(object); }
59	59	template<class _Object> static devcb2_base &set_out_1hz_callback(device_t &device, _Object object) { return downcast<hd64610_device &>(device).m_out_1hz_cb.set_callback(object); }
60	60

trunk/src/emu/machine/mc68901.c
r29404	r29405
530	530	receive_register_extract();
531	531	m_receive_buffer = get_received_char();
532	532	//if (m_receive_pending) TODO: error?
533
	533
534	534	m_receive_pending = 1;
535	535	rx_buffer_full();
536	536	}

trunk/src/emu/machine/mc68901.h
r29404	r29405
74	74
75	75	#define MCFG_MC68901_OUT_TDO_CB(_devcb) \
76	76	devcb = &mc68901_device::set_out_tdo_callback(*device, DEVCB2_##_devcb);
77
	77
78	78	#define MCFG_MC68901_OUT_SO_CB(_devcb) \
79	79	devcb = &mc68901_device::set_out_so_callback(*device, DEVCB2_##_devcb);
80	80
81	81	/*#define MCFG_MC68901_OUT_RR_CB(_devcb) \
82		devcb = &mc68901_device::set_out_rr_callback(*device, DEVCB2_##_devcb);
	82	devcb = &mc68901_device::set_out_rr_callback(*device, DEVCB2_##_devcb);
83	83
84	84	#define MCFG_MC68901_OUT_TR_CB(_devcb) \
85		devcb = &mc68901_device::set_out_tr_callback(device, DEVCB2_##_devcb);/
86
	85	devcb = &mc68901_device::set_out_tr_callback(device, DEVCB2_##_devcb);/
87	86
	87
88	88	//**************************************************************************
89	89	// TYPE DEFINITIONS
90	90	//**************************************************************************
r29404	r29405
98	98	public:
99	99	// construction/destruction
100	100	mc68901_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
101
	101
102	102	static void set_timer_clock(device_t &device, int timer_clock) { downcast<mc68901_device &>(device).m_timer_clock = timer_clock; }
103	103	static void set_rx_clock(device_t &device, int rx_clock) { downcast<mc68901_device &>(device).m_rx_clock = rx_clock; }
104	104	static void set_tx_clock(device_t &device, int tx_clock) { downcast<mc68901_device &>(device).m_tx_clock = tx_clock; }

trunk/src/emu/machine/6522via.c
r29404	r29405
470	470	void via6522_device::output_pb()
471	471	{
472	472	UINT8 pb = (m_out_b & m_ddr_b) \| ~m_ddr_b;
473
	473
474	474	if (T1_SET_PB7(m_acr))
475	475	pb = (pb & 0x7f) \| (m_t1_pb7 << 7);
476	476

trunk/src/emu/machine/ncr5380.h
r29404	r29405
40	40	public:
41	41	// construction/destruction
42	42	ncr5380_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
43
	43
44	44	template<class _Object> static devcb2_base &set_irq_callback(device_t &device, _Object object) { return downcast<ncr5380_device &>(device).m_irq_cb.set_callback(object); }
45	45
46	46	// our API

trunk/src/emu/machine/mos6530.h
r29404	r29405
70	70
71	71	DECLARE_READ8_MEMBER( read );
72	72	DECLARE_WRITE8_MEMBER( write );
73
	73
74	74	UINT8 porta_in_get();
75	75	UINT8 portb_in_get();
76	76
77	77	UINT8 porta_out_get();
78	78	UINT8 portb_out_get();
79
	79
80	80	protected:
81	81	// device-level overrides
82	82	virtual void device_config_complete();
83	83	virtual void device_start();
84	84	virtual void device_reset();
85	85	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
86
	86
87	87	private:
88	88	// internal state
89	89
r29404	r29405
99	99	emu_timer * m_timer;
100	100
101	101	UINT32 m_clock;
102
103		void update_irqstate();
	102
	103	void update_irqstate();
104	104	UINT8 get_timer();
105
	105
106	106	void porta_in_set(UINT8 data, UINT8 mask);
107	107	void portb_in_set(UINT8 data, UINT8 mask);
108
	108
109	109	enum
110	110	{
111	111	TIMER_END_CALLBACK

trunk/src/emu/machine/ins8154.h
r29404	r29405
46	46
47	47	#define MCFG_INS8154_IN_A_CB(_devcb) \
48	48	devcb = &ins8154_device::set_in_a_callback(*device, DEVCB2_##_devcb);
49
	49
50	50	#define MCFG_INS8154_OUT_A_CB(_devcb) \
51	51	devcb = &ins8154_device::set_out_a_callback(*device, DEVCB2_##_devcb);
52
	52
53	53	#define MCFG_INS8154_IN_B_CB(_devcb) \
54	54	devcb = &ins8154_device::set_in_b_callback(*device, DEVCB2_##_devcb);
55
	55
56	56	#define MCFG_INS8154_OUT_B_CB(_devcb) \
57	57	devcb = &ins8154_device::set_out_b_callback(*device, DEVCB2_##_devcb);
58	58
r29404	r29405
76	76	template<class _Object> static devcb2_base &set_in_b_callback(device_t &device, _Object object) { return downcast<ins8154_device &>(device).m_in_b_cb.set_callback(object); }
77	77	template<class _Object> static devcb2_base &set_out_b_callback(device_t &device, _Object object) { return downcast<ins8154_device &>(device).m_out_b_cb.set_callback(object); }
78	78	template<class _Object> static devcb2_base &set_out_irq_callback(device_t &device, _Object object) { return downcast<ins8154_device &>(device).m_out_irq_cb.set_callback(object); }
79
	79
80	80	DECLARE_READ8_MEMBER( ins8154_r );
81	81	DECLARE_WRITE8_MEMBER( ins8154_w );
82	82

trunk/src/emu/machine/8530scc.c
r29404	r29405
23	23	IMPLEMENTATION
24	24	***************************************************************************/
25	25
26		scc8530_t::scc8530_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	26	scc8530_t::scc8530_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
27	27	device_t(mconfig, SCC8530, "Zilog 8530 SCC", tag, owner, clock, "scc8530", __FILE__),
28	28	intrq_cb(*this)
29	29	{

trunk/src/emu/machine/wd17xx.c
r29404	r29405
376	376
377	377	/* set intrq after delay */
378	378	TIMER_CALLBACK_MEMBER( wd1770_device::wd17xx_command_callback )
379		{
	379	{
380	380	if (m_last_command_data != FDC_FORCE_INT)
381	381	{
382	382	wd17xx_set_intrq();

trunk/src/emu/machine/wd17xx.h
r29404	r29405
68	68	WRITE_LINE_MEMBER( wprt_w );
69	69	WRITE_LINE_MEMBER( dden_w );
70	70	READ_LINE_MEMBER( drq_r );
71		READ_LINE_MEMBER( intrq_r );
	71	READ_LINE_MEMBER( intrq_r );
72	72	protected:
73	73	// device-level overrides
74	74	virtual void device_config_complete();
r29404	r29405
179	179	UINT8 m_was_busy;
180	180
181	181	/* Pointer to interface */
182		const wd17xx_interface *m_intf;
	182	const wd17xx_interface *m_intf;
183	183	};
184	184
185	185	extern ATTR_DEPRECATED const device_type WD1770;

trunk/src/emu/machine/i8271.c
r29404	r29405
133	133	{
134	134	m_CommandParameters[i] = 0;
135	135	}
136
	136
137	137	for (int i = 0; i < 2; i++ )
138	138	{
139	139	m_CurrentTrack[i] = 0;
140	140	}
141
	141
142	142	for (int i = 0; i < 4; i++ )
143	143	{
144	144	m_BadTracks[i] = 0;
r29404	r29405
313	313	/* stop it */
314	314	m_data_timer->reset();
315	315	break;
316
	316
317	317	case TIMER_TIMED_COMMAND_COMPLETE:
318	318	command_complete(1,1);
319	319
320	320	/* stop it, but don't allow it to be free'd */
321	321	m_command_complete_timer->reset();
322	322	break;
323
	323
324	324	default:
325	325	break;
326	326	}
327	327	}
328
	328
329	329	/* setup a timed data request - data request will be triggered in a few usecs time */
330	330	void i8271_device::timed_data_request()
331	331	{
r29404	r29405
345	345	void i8271_device::timed_command_complete()
346	346	{
347	347	int usecs;
348
	348
349	349	/* 64 for single density - 2 crc bytes later*/
350	350	usecs = 64*2;
351	351
r29404	r29405
669	669	void i8271_device::do_read_id()
670	670	{
671	671	chrn_id id;
672
	672
673	673	/* get next id from disc */
674	674	current_image()->floppy_drive_get_next_id(m_side,&id);
675	675

trunk/src/emu/machine/rp5c01.h
r29404	r29405
51	51	public:
52	52	// construction/destruction
53	53	rp5c01_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
54
	54
55	55	template<class _Object> static devcb2_base &set_out_alarm_callback(device_t &device, _Object object) { return downcast<rp5c01_device &>(device).m_out_alarm_cb.set_callback(object); }
56	56
57	57	DECLARE_READ8_MEMBER( read );

trunk/src/emu/machine/i8271.h
r29404	r29405
46	46
47	47	DECLARE_READ8_MEMBER(data_r);
48	48	DECLARE_WRITE8_MEMBER(data_w);
49
	49
50	50	protected:
51	51	// device-level overrides
52	52	virtual void device_config_complete();
53	53	virtual void device_start();
54	54	virtual void device_reset();
55	55	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
56
	56
57	57	private:
58	58	// internal state
59	59	enum
r29404	r29405
64	64
65	65	devcb2_write_line m_write_irq;
66	66	devcb2_write_line m_write_drq;
67
	67
68	68	int m_flags;
69	69	int m_state;
70	70	unsigned char m_Command;
r29404	r29405
127	127
128	128	emu_timer *m_data_timer;
129	129	emu_timer *m_command_complete_timer;
130
	130
131	131	legacy_floppy_image_device *current_image();
132	132	void seek_to_track(int track);
133	133	void load_bad_tracks(int surface);

trunk/src/emu/machine/latch8.c
r29404	r29405
54	54	{
55	55	int i;
56	56	for (i=0; i<8; i++)
57		{
	57	{
58	58	if (i==0 && !m_read_0.isnull()) { res &= ~( 1 << i); res \|= ((m_read_0(space, 0, 0xff) >> m_offset[i]) & 0x01) << i; }
59	59	if (i==1 && !m_read_1.isnull()) { res &= ~( 1 << i); res \|= ((m_read_1(space, 0, 0xff) >> m_offset[i]) & 0x01) << i; }
60	60	if (i==2 && !m_read_2.isnull()) { res &= ~( 1 << i); res \|= ((m_read_2(space, 0, 0xff) >> m_offset[i]) & 0x01) << i; }
r29404	r29405
62	62	if (i==4 && !m_read_4.isnull()) { res &= ~( 1 << i); res \|= ((m_read_4(space, 0, 0xff) >> m_offset[i]) & 0x01) << i; }
63	63	if (i==5 && !m_read_5.isnull()) { res &= ~( 1 << i); res \|= ((m_read_5(space, 0, 0xff) >> m_offset[i]) & 0x01) << i; }
64	64	if (i==6 && !m_read_6.isnull()) { res &= ~( 1 << i); res \|= ((m_read_6(space, 0, 0xff) >> m_offset[i]) & 0x01) << i; }
65		if (i==7 && !m_read_7.isnull()) { res &= ~( 1 << i); res \|= ((m_read_7(space, 0, 0xff) >> m_offset[i]) & 0x01) << i;}
	65	if (i==7 && !m_read_7.isnull()) { res &= ~( 1 << i); res \|= ((m_read_7(space, 0, 0xff) >> m_offset[i]) & 0x01) << i;}
66	66	}
67	67	}
68	68	return (res & ~m_maskout) ^ m_xorvalue;
r29404	r29405
150	150	m_has_read(0),
151	151	m_maskout(0),
152	152	m_xorvalue(0),
153		m_nosync(0),
	153	m_nosync(0),
154	154	m_write_0(*this),
155	155	m_write_1(*this),
156	156	m_write_2(*this),
r29404	r29405
168	168	m_read_6(*this),
169	169	m_read_7(*this)
170	170	{
171		memset(m_offset, 0, sizeof(m_offset));
	171	memset(m_offset, 0, sizeof(m_offset));
172	172	}
173	173
174	174
175	175	//-------------------------------------------------
176	176	// device_validity_check - validate device
177		// configuration
	177	// configuration
178	178	//-------------------------------------------------
179	179
180	180	void latch8_device::device_validity_check(validity_checker &valid) const
r29404	r29405
202	202	m_write_5.resolve();
203	203	m_write_6.resolve();
204	204	m_write_7.resolve();
205
	205
206	206	m_read_0.resolve();
207	207	m_read_1.resolve();
208	208	m_read_2.resolve();
r29404	r29405
211	211	m_read_5.resolve();
212	212	m_read_6.resolve();
213	213	m_read_7.resolve();
214
	214
215	215	/* setup nodemap */
216	216	if (!m_write_0.isnull()) m_has_write = 1;
217	217	if (!m_write_1.isnull()) m_has_write = 1;
r29404	r29405
221	221	if (!m_write_5.isnull()) m_has_write = 1;
222	222	if (!m_write_6.isnull()) m_has_write = 1;
223	223	if (!m_write_7.isnull()) m_has_write = 1;
224
	224
225	225	/* setup device read handlers */
226	226	if (!m_read_0.isnull()) m_has_read = 1;
227	227	if (!m_read_1.isnull()) m_has_read = 1;

trunk/src/emu/machine/latch8.h
r29404	r29405
26	26	{
27	27	public:
28	28	latch8_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
29
30
	29
	30
31	31	/* write & read full byte */
32	32
33	33	DECLARE_READ8_MEMBER( read );
r29404	r29405
76	76	static void set_maskout(device_t &device, UINT32 maskout) { downcast<latch8_device &>(device).m_maskout = maskout; }
77	77	static void set_xorvalue(device_t &device, UINT32 xorvalue) { downcast<latch8_device &>(device).m_xorvalue = xorvalue; }
78	78	static void set_nosync(device_t &device, UINT32 nosync) { downcast<latch8_device &>(device).m_nosync = nosync; }
79
	79
80	80	template<class _Object> static devcb2_base &set_write_0(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[0] = offset; return downcast<latch8_device &>(device).m_write_0.set_callback(object); }
81	81	template<class _Object> static devcb2_base &set_write_1(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[1] = offset; return downcast<latch8_device &>(device).m_write_1.set_callback(object); }
82	82	template<class _Object> static devcb2_base &set_write_2(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[2] = offset; return downcast<latch8_device &>(device).m_write_2.set_callback(object); }
r29404	r29405
85	85	template<class _Object> static devcb2_base &set_write_5(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[5] = offset; return downcast<latch8_device &>(device).m_write_5.set_callback(object); }
86	86	template<class _Object> static devcb2_base &set_write_6(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[6] = offset; return downcast<latch8_device &>(device).m_write_6.set_callback(object); }
87	87	template<class _Object> static devcb2_base &set_write_7(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[7] = offset; return downcast<latch8_device &>(device).m_write_7.set_callback(object); }
88
	88
89	89	template<class _Object> static devcb2_base &set_read_0(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[0] = offset; return downcast<latch8_device &>(device).m_read_0.set_callback(object); }
90	90	template<class _Object> static devcb2_base &set_read_1(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[1] = offset; return downcast<latch8_device &>(device).m_read_1.set_callback(object); }
91	91	template<class _Object> static devcb2_base &set_read_2(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[2] = offset; return downcast<latch8_device &>(device).m_read_2.set_callback(object); }
r29404	r29405
94	94	template<class _Object> static devcb2_base &set_read_5(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[5] = offset; return downcast<latch8_device &>(device).m_read_5.set_callback(object); }
95	95	template<class _Object> static devcb2_base &set_read_6(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[6] = offset; return downcast<latch8_device &>(device).m_read_6.set_callback(object); }
96	96	template<class _Object> static devcb2_base &set_read_7(device_t &device, _Object object, UINT32 offset) { downcast<latch8_device &>(device).m_offset[7] = offset; return downcast<latch8_device &>(device).m_read_7.set_callback(object); }
97
	97
98	98	protected:
99	99	// device-level overrides
100	100	virtual void device_start();
101	101	virtual void device_reset();
102	102	virtual void device_validity_check(validity_checker &valid) const;
103
	103
104	104	TIMER_CALLBACK_MEMBER( timerproc );
105	105	void update(UINT8 new_val, UINT8 mask);
106	106	inline UINT8 bitx_r( offs_t offset, int bit);
r29404	r29405
110	110	UINT8 m_value;
111	111	UINT8 m_has_write;
112	112	UINT8 m_has_read;
113
	113
114	114	/* only for byte reads, does not affect bit reads and node_map */
115	115	UINT32 m_maskout;
116	116	UINT32 m_xorvalue; /* after mask */
117	117	UINT32 m_nosync;
118
	118
119	119	devcb2_write8 m_write_0;
120	120	devcb2_write8 m_write_1;
121	121	devcb2_write8 m_write_2;
r29404	r29405
133	133	devcb2_read8 m_read_5;
134	134	devcb2_read8 m_read_6;
135	135	devcb2_read8 m_read_7;
136
	136
137	137	UINT32 m_offset[8];
138	138	};
139	139
r29404	r29405
186	186	/* Upon read, replace bits by reading from another device handler */
187	187	#define MCFG_LATCH8_READ_0(_devcb, _from_bit) \
188	188	devcb = &latch8_device::set_read_0(*device, DEVCB2_##_devcb, _from_bit);
189
	189
190	190	#define MCFG_LATCH8_READ_1(_devcb, _from_bit) \
191	191	devcb = &latch8_device::set_read_1(*device, DEVCB2_##_devcb, _from_bit);
192	192

trunk/src/emu/machine/64h156.c
r29404	r29405
19	19	- cycle exact VIA
20	20
21	21	- get these running and we're golden
22		- Bounty Bob Strikes Back (aligned halftracks)
	22	- Bounty Bob Strikes Back (aligned halftracks)
23	23	- Quiwi (speed change within track)
24	24	- Defender of the Crown (V-MAX! v2, density checks)
25	25	- Test Drive / Cabal (HLS, sub-cycle jitter)
r29404	r29405
201	201	{
202	202	if(cur_live.write_start_time.is_never() \|\| tm == cur_live.write_start_time \|\| !cur_live.write_position)
203	203	return;
204
	204
205	205	if (LOG) logerror("%s committing %u transitions since %s\n", tm.as_string(), cur_live.write_position, cur_live.write_start_time.as_string());
206	206
207	207	m_floppy->write_flux(cur_live.write_start_time, tm, cur_live.write_position, cur_live.write_buffer);
r29404	r29405
293	293	cur_live.cell_counter++;
294	294	cur_live.cell_counter &= 0xf;
295	295	}
296
	296
297	297	if (!BIT(cell_counter, 1) && BIT(cur_live.cell_counter, 1)) {
298	298	// read bit
299	299	cur_live.shift_reg <<= 1;
300	300	cur_live.shift_reg \|= !(BIT(cur_live.cell_counter, 3) \|\| BIT(cur_live.cell_counter, 2));
301	301	cur_live.shift_reg &= 0x3ff;
302
303		if (LOG) logerror("%s read bit %u (%u) >> %03x, oe=%u soe=%u sync=%u byte=%u\n", cur_live.tm.as_string(), cur_live.bit_counter,
	302
	303	if (LOG) logerror("%s read bit %u (%u) >> %03x, oe=%u soe=%u sync=%u byte=%u\n", cur_live.tm.as_string(), cur_live.bit_counter,
304	304	!(BIT(cur_live.cell_counter, 3) \|\| BIT(cur_live.cell_counter, 2)), cur_live.shift_reg, cur_live.oe, cur_live.soe, cur_live.sync, cur_live.byte);
305	305
306	306	syncpoint = true;
r29404	r29405
392	392	if (bit) {
393	393	cur_live.zero_counter = 0;
394	394	cur_live.cycles_until_random_flux = (rand() % 31) + 289;
395
	395
396	396	get_next_edge(next);
397	397	}
398	398

trunk/src/emu/machine/z8536.h
r29404	r29405
76	76	// ======================> z8536_device
77	77
78	78	class z8536_device : public device_t,
79		public device_z80daisy_interface
	79	public device_z80daisy_interface
80	80	{
81	81	public:
82	82	// construction/destruction

trunk/src/emu/machine/nsc810.c
r29404	r29405
308	308	}
309	309	}
310	310	}
311

trunk/src/emu/machine/msm6242.h
r29404	r29405
27	27	public:
28	28	// construction/destruction
29	29	msm6242_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
30
31
	30
	31
32	32	template<class _Object> static devcb2_base &set_out_int_handler(device_t &device, _Object object) { return downcast<msm6242_device &>(device).m_out_int_handler.set_callback(object); }
33	33
34	34	// I/O operations

trunk/src/emu/machine/ds75161a.h
r29404	r29405
37	37
38	38	#define MCFG_DS75161A_IN_REN_CB(_devcb) \
39	39	devcb = &ds75161a_device::set_in_ren_callback(*device, DEVCB2_##_devcb);
40
	40
41	41	#define MCFG_DS75161A_IN_IFC_CB(_devcb) \
42	42	devcb = &ds75161a_device::set_in_ifc_callback(*device, DEVCB2_##_devcb);
43
	43
44	44	#define MCFG_DS75161A_IN_NDAC_CB(_devcb) \
45	45	devcb = &ds75161a_device::set_in_ndac_callback(*device, DEVCB2_##_devcb);
46
	46
47	47	#define MCFG_DS75161A_IN_NRFD_CB(_devcb) \
48	48	devcb = &ds75161a_device::set_in_nrfd_callback(*device, DEVCB2_##_devcb);
49
	49
50	50	#define MCFG_DS75161A_IN_DAV_CB(_devcb) \
51	51	devcb = &ds75161a_device::set_in_dav_callback(*device, DEVCB2_##_devcb);
52
	52
53	53	#define MCFG_DS75161A_IN_EOI_CB(_devcb) \
54	54	devcb = &ds75161a_device::set_in_eoi_callback(*device, DEVCB2_##_devcb);
55
	55
56	56	#define MCFG_DS75161A_IN_ATN_CB(_devcb) \
57	57	devcb = &ds75161a_device::set_in_atn_callback(*device, DEVCB2_##_devcb);
58	58
r29404	r29405
61	61
62	62	#define MCFG_DS75161A_OUT_REN_CB(_devcb) \
63	63	devcb = &ds75161a_device::set_out_ren_callback(*device, DEVCB2_##_devcb);
64
	64
65	65	#define MCFG_DS75161A_OUT_IFC_CB(_devcb) \
66	66	devcb = &ds75161a_device::set_out_ifc_callback(*device, DEVCB2_##_devcb);
67
	67
68	68	#define MCFG_DS75161A_OUT_NDAC_CB(_devcb) \
69	69	devcb = &ds75161a_device::set_out_ndac_callback(*device, DEVCB2_##_devcb);
70
	70
71	71	#define MCFG_DS75161A_OUT_NRFD_CB(_devcb) \
72	72	devcb = &ds75161a_device::set_out_nrfd_callback(*device, DEVCB2_##_devcb);
73
	73
74	74	#define MCFG_DS75161A_OUT_DAV_CB(_devcb) \
75	75	devcb = &ds75161a_device::set_out_dav_callback(*device, DEVCB2_##_devcb);
76
	76
77	77	#define MCFG_DS75161A_OUT_EOI_CB(_devcb) \
78	78	devcb = &ds75161a_device::set_out_eoi_callback(*device, DEVCB2_##_devcb);
79
	79
80	80	#define MCFG_DS75161A_OUT_ATN_CB(_devcb) \
81	81	devcb = &ds75161a_device::set_out_atn_callback(*device, DEVCB2_##_devcb);
82	82
r29404	r29405
94	94	public:
95	95	// construction/destruction
96	96	ds75161a_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
97
	97
98	98	template<class _Object> static devcb2_base &set_in_ren_callback(device_t &device, _Object object) { return downcast<ds75161a_device &>(device).m_in_ren_cb.set_callback(object); }
99	99	template<class _Object> static devcb2_base &set_in_ifc_callback(device_t &device, _Object object) { return downcast<ds75161a_device &>(device).m_in_ifc_cb.set_callback(object); }
100	100	template<class _Object> static devcb2_base &set_in_ndac_callback(device_t &device, _Object object) { return downcast<ds75161a_device &>(device).m_in_ndac_cb.set_callback(object); }

trunk/src/emu/machine/wd33c93.h
r29404	r29405
53	53	public:
54	54	// construction/destruction
55	55	wd33c93_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
56
	56
57	57	template<class _Object> static devcb2_base &set_irq_callback(device_t &device, _Object object) { return downcast<wd33c93_device &>(device).m_irq_cb.set_callback(object); }
58	58
59	59	DECLARE_READ8_MEMBER(read);

trunk/src/emu/machine/smc91c9x.h
r29404	r29405
25	25	~smc91c9x_device() {}
26	26
27	27	template<class _Object> static devcb2_base &set_irq_callback(device_t &device, _Object object) { return downcast<smc91c9x_device &>(device).m_irq_handler.set_callback(object); }
28
	28
29	29	DECLARE_READ16_MEMBER( read );
30	30	DECLARE_WRITE16_MEMBER( write );
31	31
r29404	r29405
86	86
87	87	#define MCFG_SMC91C94_ADD(_tag) \
88	88	MCFG_DEVICE_ADD(_tag, SMC91C94, 0)
89
	89
90	90	#define MCFG_SMC91C94_IRQ_CALLBACK(_write) \
91	91	devcb = &smc91c94_device::set_irq_callback(*device, DEVCB2_##_write);
92	92

trunk/src/emu/machine/s3c2440.c
r29404	r29405
104	104	void s3c2440_device::device_start()
105	105	{
106	106	address_space &space = m_cpu->memory().space( AS_PROGRAM);
107		space.install_readwrite_handler(0x48000000, 0x4800003b, read32_delegate(FUNC(s3c2440_device::s3c24xx_memcon_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_memcon_w), this));
108		space.install_readwrite_handler(0x49000000, 0x4900005b, read32_delegate(FUNC(s3c2440_device::s3c24xx_usb_host_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_usb_host_w), this));
109		space.install_readwrite_handler(0x4a000000, 0x4a00001f, read32_delegate(FUNC(s3c2440_device::s3c24xx_irq_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_irq_w), this));
110		space.install_readwrite_handler(0x4b000000, 0x4b000023, read32_delegate(FUNC(s3c2440_device::s3c24xx_dma_0_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_dma_0_w), this));
111		space.install_readwrite_handler(0x4b000040, 0x4b000063, read32_delegate(FUNC(s3c2440_device::s3c24xx_dma_1_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_dma_1_w), this));
112		space.install_readwrite_handler(0x4b000080, 0x4b0000a3, read32_delegate(FUNC(s3c2440_device::s3c24xx_dma_2_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_dma_2_w), this));
113		space.install_readwrite_handler(0x4b0000c0, 0x4b0000e3, read32_delegate(FUNC(s3c2440_device::s3c24xx_dma_3_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_dma_3_w), this));
114		space.install_readwrite_handler(0x4c000000, 0x4c00001b, read32_delegate(FUNC(s3c2440_device::s3c24xx_clkpow_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_clkpow_w), this));
115		space.install_readwrite_handler(0x4d000000, 0x4d000063, read32_delegate(FUNC(s3c2440_device::s3c24xx_lcd_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_lcd_w), this));
116		space.install_readwrite_handler(0x4d000400, 0x4d0007ff, read32_delegate(FUNC(s3c2440_device::s3c24xx_lcd_palette_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_lcd_palette_w), this));
117		space.install_readwrite_handler(0x4e000000, 0x4e00003f, read32_delegate(FUNC(s3c2440_device::s3c24xx_nand_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_nand_w), this));
118		space.install_readwrite_handler(0x4f000000, 0x4f0000a3, read32_delegate(FUNC(s3c2440_device::s3c24xx_cam_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_cam_w), this));
119		space.install_readwrite_handler(0x50000000, 0x5000002b, read32_delegate(FUNC(s3c2440_device::s3c24xx_uart_0_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_uart_0_w), this));
120		space.install_readwrite_handler(0x50004000, 0x5000402b, read32_delegate(FUNC(s3c2440_device::s3c24xx_uart_1_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_uart_1_w), this));
121		space.install_readwrite_handler(0x50008000, 0x5000802b, read32_delegate(FUNC(s3c2440_device::s3c24xx_uart_2_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_uart_2_w), this));
122		space.install_readwrite_handler(0x51000000, 0x51000043, read32_delegate(FUNC(s3c2440_device::s3c24xx_pwm_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_pwm_w), this));
123		space.install_readwrite_handler(0x52000140, 0x5200026f, read32_delegate(FUNC(s3c2440_device::s3c24xx_usb_device_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_usb_device_w), this));
124		space.install_readwrite_handler(0x53000000, 0x5300000b, read32_delegate(FUNC(s3c2440_device::s3c24xx_wdt_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_wdt_w), this));
125		space.install_readwrite_handler(0x54000000, 0x54000013, read32_delegate(FUNC(s3c2440_device::s3c24xx_iic_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_iic_w), this));
126		space.install_readwrite_handler(0x55000000, 0x55000013, read32_delegate(FUNC(s3c2440_device::s3c24xx_iis_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_iis_w), this));
127		space.install_readwrite_handler(0x56000000, 0x560000df, read32_delegate(FUNC(s3c2440_device::s3c24xx_gpio_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_gpio_w), this));
128		space.install_readwrite_handler(0x57000040, 0x5700008b, read32_delegate(FUNC(s3c2440_device::s3c24xx_rtc_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_rtc_w), this));
129		space.install_readwrite_handler(0x58000000, 0x58000017, read32_delegate(FUNC(s3c2440_device::s3c24xx_adc_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_adc_w), this));
130		space.install_readwrite_handler(0x59000000, 0x59000017, read32_delegate(FUNC(s3c2440_device::s3c24xx_spi_0_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_spi_0_w), this));
131		space.install_readwrite_handler(0x59000020, 0x59000037, read32_delegate(FUNC(s3c2440_device::s3c24xx_spi_1_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_spi_1_w), this));
132		space.install_readwrite_handler(0x5a000000, 0x5a000043, read32_delegate(FUNC(s3c2440_device::s3c24xx_sdi_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_sdi_w), this));
133		space.install_readwrite_handler(0x5b000000, 0x5b00001f, read32_delegate(FUNC(s3c2440_device::s3c24xx_ac97_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_ac97_w), this));
	107	space.install_readwrite_handler(0x48000000, 0x4800003b, read32_delegate(FUNC(s3c2440_device::s3c24xx_memcon_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_memcon_w), this));
	108	space.install_readwrite_handler(0x49000000, 0x4900005b, read32_delegate(FUNC(s3c2440_device::s3c24xx_usb_host_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_usb_host_w), this));
	109	space.install_readwrite_handler(0x4a000000, 0x4a00001f, read32_delegate(FUNC(s3c2440_device::s3c24xx_irq_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_irq_w), this));
	110	space.install_readwrite_handler(0x4b000000, 0x4b000023, read32_delegate(FUNC(s3c2440_device::s3c24xx_dma_0_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_dma_0_w), this));
	111	space.install_readwrite_handler(0x4b000040, 0x4b000063, read32_delegate(FUNC(s3c2440_device::s3c24xx_dma_1_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_dma_1_w), this));
	112	space.install_readwrite_handler(0x4b000080, 0x4b0000a3, read32_delegate(FUNC(s3c2440_device::s3c24xx_dma_2_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_dma_2_w), this));
	113	space.install_readwrite_handler(0x4b0000c0, 0x4b0000e3, read32_delegate(FUNC(s3c2440_device::s3c24xx_dma_3_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_dma_3_w), this));
	114	space.install_readwrite_handler(0x4c000000, 0x4c00001b, read32_delegate(FUNC(s3c2440_device::s3c24xx_clkpow_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_clkpow_w), this));
	115	space.install_readwrite_handler(0x4d000000, 0x4d000063, read32_delegate(FUNC(s3c2440_device::s3c24xx_lcd_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_lcd_w), this));
	116	space.install_readwrite_handler(0x4d000400, 0x4d0007ff, read32_delegate(FUNC(s3c2440_device::s3c24xx_lcd_palette_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_lcd_palette_w), this));
	117	space.install_readwrite_handler(0x4e000000, 0x4e00003f, read32_delegate(FUNC(s3c2440_device::s3c24xx_nand_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_nand_w), this));
	118	space.install_readwrite_handler(0x4f000000, 0x4f0000a3, read32_delegate(FUNC(s3c2440_device::s3c24xx_cam_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_cam_w), this));
	119	space.install_readwrite_handler(0x50000000, 0x5000002b, read32_delegate(FUNC(s3c2440_device::s3c24xx_uart_0_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_uart_0_w), this));
	120	space.install_readwrite_handler(0x50004000, 0x5000402b, read32_delegate(FUNC(s3c2440_device::s3c24xx_uart_1_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_uart_1_w), this));
	121	space.install_readwrite_handler(0x50008000, 0x5000802b, read32_delegate(FUNC(s3c2440_device::s3c24xx_uart_2_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_uart_2_w), this));
	122	space.install_readwrite_handler(0x51000000, 0x51000043, read32_delegate(FUNC(s3c2440_device::s3c24xx_pwm_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_pwm_w), this));
	123	space.install_readwrite_handler(0x52000140, 0x5200026f, read32_delegate(FUNC(s3c2440_device::s3c24xx_usb_device_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_usb_device_w), this));
	124	space.install_readwrite_handler(0x53000000, 0x5300000b, read32_delegate(FUNC(s3c2440_device::s3c24xx_wdt_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_wdt_w), this));
	125	space.install_readwrite_handler(0x54000000, 0x54000013, read32_delegate(FUNC(s3c2440_device::s3c24xx_iic_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_iic_w), this));
	126	space.install_readwrite_handler(0x55000000, 0x55000013, read32_delegate(FUNC(s3c2440_device::s3c24xx_iis_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_iis_w), this));
	127	space.install_readwrite_handler(0x56000000, 0x560000df, read32_delegate(FUNC(s3c2440_device::s3c24xx_gpio_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_gpio_w), this));
	128	space.install_readwrite_handler(0x57000040, 0x5700008b, read32_delegate(FUNC(s3c2440_device::s3c24xx_rtc_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_rtc_w), this));
	129	space.install_readwrite_handler(0x58000000, 0x58000017, read32_delegate(FUNC(s3c2440_device::s3c24xx_adc_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_adc_w), this));
	130	space.install_readwrite_handler(0x59000000, 0x59000017, read32_delegate(FUNC(s3c2440_device::s3c24xx_spi_0_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_spi_0_w), this));
	131	space.install_readwrite_handler(0x59000020, 0x59000037, read32_delegate(FUNC(s3c2440_device::s3c24xx_spi_1_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_spi_1_w), this));
	132	space.install_readwrite_handler(0x5a000000, 0x5a000043, read32_delegate(FUNC(s3c2440_device::s3c24xx_sdi_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_sdi_w), this));
	133	space.install_readwrite_handler(0x5b000000, 0x5b00001f, read32_delegate(FUNC(s3c2440_device::s3c24xx_ac97_r), this), write32_delegate(FUNC(s3c2440_device::s3c24xx_ac97_w), this));
134	134
135	135	s3c24xx_device_start();
136
	136
137	137	s3c24xx_video_start();
138	138	}
139	139

trunk/src/emu/machine/pckeybrd.c
r29404	r29405
336	336	ioport_queue_chars_delegate(FUNC(pc_keyboard_device::queue_chars), this),
337	337	ioport_accept_char_delegate(FUNC(pc_keyboard_device::accept_char), this),
338	338	ioport_charqueue_empty_delegate(FUNC(pc_keyboard_device::charqueue_empty), this));
339
	339
340	340	m_out_keypress_func.resolve_safe();
341	341	m_keyboard_timer = timer_alloc();
342	342	}

trunk/src/emu/machine/s3c2440.h
r29404	r29405
15	15
16	16	#define MCFG_S3C2440_ADD(_tag, _clock, _config, _palette_tag) \
17	17	MCFG_DEVICE_ADD(_tag, S3C2440, _clock) \
18		MCFG_DEVICE_CONFIG(_config) \
	18	MCFG_DEVICE_CONFIG(_config) \
19	19	s3c2440_device::static_set_palette_tag(*device, "^" _palette_tag);
20	20
21	21	#define S3C2440_INTERFACE(name) \
r29404	r29405
486	486	#define S3C24XX_DMA_COUNT 4
487	487	#define S3C24XX_SPI_COUNT 2
488	488
489		class s3c2440_device : public device_t,
	489	class s3c2440_device : public device_t,
490	490	public s3c2440_interface
491	491	{
492	492	public:
r29404	r29405
508	508	required_device<palette_device> m_palette;
509	509	public:
510	510	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
511
	511
512	512	void s3c24xx_reset();
513	513	inline int iface_core_pin_r(int pin);
514	514	void s3c24xx_lcd_reset();
r29404	r29405
696	696	void s3c24xx_nand_auto_boot();
697	697	void s3c24xx_device_reset();
698	698	void s3c24xx_device_start();
699
700	699
	700
701	701	void s3c2440_uart_fifo_w( int uart, UINT8 data);
702	702	void s3c2440_touch_screen( int state);
703	703	void s3c2440_request_irq( UINT32 int_type);
r29404	r29405
705	705
706	706
707	707	/*******************************************************************************
708		TYPE DEFINITIONS
	708	TYPE DEFINITIONS
709	709	*******************************************************************************/
710	710
711	711	struct s3c24xx_memcon_regs_t
r29404	r29405
1119	1119	s3c24xx_ac97_regs_t regs;
1120	1120	};
1121	1121
1122
	1122
1123	1123	UINT8 m_steppingstone[4*1024];
1124	1124	s3c24xx_memcon_t m_memcon;
1125	1125	s3c24xx_usbhost_t m_usbhost;
r29404	r29405
1156	1156	devcb_resolved_write8 m_address_w;
1157	1157	devcb_resolved_read8 m_nand_data_r;
1158	1158	devcb_resolved_write8 m_nand_data_w;
1159
	1159
1160	1160	};
1161	1161
1162	1162	extern const device_type S3C2440;

trunk/src/emu/machine/pckeybrd.h
r29404	r29405
73	73	optional_ioport m_ioport_5;
74	74	optional_ioport m_ioport_6;
75	75	optional_ioport m_ioport_7;
76
	76
77	77	devcb2_write_line m_out_keypress_func;
78	78	emu_timer *m_keyboard_timer;
79	79	};
r29404	r29405
85	85
86	86	DECLARE_WRITE8_MEMBER( write );
87	87
88		static void static_set_type(device_t &device, KEYBOARD_TYPE type, int default_set)
	88	static void static_set_type(device_t &device, KEYBOARD_TYPE type, int default_set)
89	89	{ downcast<at_keyboard_device &>(device).m_scan_code_set = default_set; downcast<at_keyboard_device &>(device).m_type = type; }
90
	90
91	91	protected:
92	92	virtual void device_reset();
93	93	virtual void device_start();

trunk/src/emu/machine/netlist.c
r29404	r29405
73	73
74	74	void netlist_mame_sub_interface::static_set_mult_offset(device_t &device, const double mult, const double offset)
75	75	{
76		netlist_mame_sub_interface &netlist = dynamic_cast<netlist_mame_sub_interface &>(device);
77		netlist.m_mult = mult;
78		netlist.m_offset = offset;
	76	netlist_mame_sub_interface &netlist = dynamic_cast<netlist_mame_sub_interface &>(device);
	77	netlist.m_mult = mult;
	78	netlist.m_offset = offset;
79	79	}
80	80
81	81
r29404	r29405
105	105	}
106	106	if (m_mult != 1.0 \|\| m_offset != 0.0)
107	107	{
108		// disable automatic scaling for ioports
109		m_auto_port = false;
	108	// disable automatic scaling for ioports
	109	m_auto_port = false;
110	110	}
111	111
112	112	}
r29404	r29405
116	116	// ----------------------------------------------------------------------------------------
117	117
118	118	netlist_mame_analog_output_t::netlist_mame_analog_output_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
119		: device_t(mconfig, NETLIST_ANALOG_INPUT, "netlist analog output", tag, owner, clock, "netlist_analog_output", __FILE__),
120		netlist_mame_sub_interface(*owner),
121		m_in("")
	119	: device_t(mconfig, NETLIST_ANALOG_INPUT, "netlist analog output", tag, owner, clock, "netlist_analog_output", __FILE__),
	120	netlist_mame_sub_interface(*owner),
	121	m_in("")
122	122	{
123	123	}
124	124
125	125	void netlist_mame_analog_output_t::static_set_params(device_t &device, const char *in_name, netlist_analog_output_delegate adelegate)
126	126	{
127		netlist_mame_analog_output_t &netlist = downcast<netlist_mame_analog_output_t &>(device);
128		netlist.m_in = in_name;
129		netlist.m_delegate = adelegate;
	127	netlist_mame_analog_output_t &netlist = downcast<netlist_mame_analog_output_t &>(device);
	128	netlist.m_in = in_name;
	129	netlist.m_delegate = adelegate;
130	130	}
131	131
132	132	void netlist_mame_analog_output_t::custom_netlist_additions(netlist_setup_t &setup)
133	133	{
134		pstring dname = "OUT_" + m_in;
135		m_delegate.bind_relative_to(owner()->machine().root_device());
136		NETLIB_NAME(analog_callback) dev = downcast<NETLIB_NAME(analog_callback) >(
137		setup.factory().new_device_by_classname("nld_analog_callback", setup));
	134	pstring dname = "OUT_" + m_in;
	135	m_delegate.bind_relative_to(owner()->machine().root_device());
	136	NETLIB_NAME(analog_callback) dev = downcast<NETLIB_NAME(analog_callback) >(
	137	setup.factory().new_device_by_classname("nld_analog_callback", setup));
138	138
139		setup.register_dev(dev, dname);
140		dev->register_callback(m_delegate);
141		setup.register_link(dname + ".IN", m_in);
	139	setup.register_dev(dev, dname);
	140	dev->register_callback(m_delegate);
	141	setup.register_link(dname + ".IN", m_in);
142	142	}
143	143
144	144	void netlist_mame_analog_output_t::device_start()
145	145	{
146		LOG_DEV_CALLS(("start %s\n", tag()));
	146	LOG_DEV_CALLS(("start %s\n", tag()));
147	147	}
148	148
149	149
r29404	r29405
185	185	// ----------------------------------------------------------------------------------------
186	186
187	187	netlist_mame_stream_input_t::netlist_mame_stream_input_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
188		: device_t(mconfig, NETLIST_ANALOG_INPUT, "netlist analog input", tag, owner, clock, "netlist_analog_input", __FILE__),
189		netlist_mame_sub_interface(*owner),
190		m_channel(0),
191		m_param_name("")
	188	: device_t(mconfig, NETLIST_ANALOG_INPUT, "netlist analog input", tag, owner, clock, "netlist_analog_input", __FILE__),
	189	netlist_mame_sub_interface(*owner),
	190	m_channel(0),
	191	m_param_name("")
192	192	{
193	193	}
194	194
195	195	void netlist_mame_stream_input_t::static_set_params(device_t &device, int channel, const char *param_name)
196	196	{
197		netlist_mame_stream_input_t &netlist = downcast<netlist_mame_stream_input_t &>(device);
198		netlist.m_param_name = param_name;
199		netlist.m_channel = channel;
	197	netlist_mame_stream_input_t &netlist = downcast<netlist_mame_stream_input_t &>(device);
	198	netlist.m_param_name = param_name;
	199	netlist.m_channel = channel;
200	200	}
201	201
202	202	void netlist_mame_stream_input_t::device_start()
203	203	{
204		LOG_DEV_CALLS(("start %s\n", tag()));
	204	LOG_DEV_CALLS(("start %s\n", tag()));
205	205	}
206	206
207	207	void netlist_mame_stream_input_t::custom_netlist_additions(netlist_setup_t &setup)
208	208	{
209		NETLIB_NAME(sound_in) *snd_in = setup.netlist().get_first_device<NETLIB_NAME(sound_in)>();
210		if (snd_in == NULL)
211		{
212		snd_in = dynamic_cast<NETLIB_NAME(sound_in) *>(setup.factory().new_device_by_classname("nld_sound_in", setup));
213		setup.register_dev(snd_in, "STREAM_INPUT");
214		}
	209	NETLIB_NAME(sound_in) *snd_in = setup.netlist().get_first_device<NETLIB_NAME(sound_in)>();
	210	if (snd_in == NULL)
	211	{
	212	snd_in = dynamic_cast<NETLIB_NAME(sound_in) *>(setup.factory().new_device_by_classname("nld_sound_in", setup));
	213	setup.register_dev(snd_in, "STREAM_INPUT");
	214	}
215	215
216		pstring sparam = pstring::sprintf("STREAM_INPUT.CHAN%d", m_channel);
217		setup.register_param(sparam, m_param_name);
218		sparam = pstring::sprintf("STREAM_INPUT.MULT%d", m_channel);
219		setup.register_param(sparam, m_mult);
220		sparam = pstring::sprintf("STREAM_INPUT.OFFSET%d", m_channel);
221		setup.register_param(sparam, m_offset);
	216	pstring sparam = pstring::sprintf("STREAM_INPUT.CHAN%d", m_channel);
	217	setup.register_param(sparam, m_param_name);
	218	sparam = pstring::sprintf("STREAM_INPUT.MULT%d", m_channel);
	219	setup.register_param(sparam, m_mult);
	220	sparam = pstring::sprintf("STREAM_INPUT.OFFSET%d", m_channel);
	221	setup.register_param(sparam, m_offset);
222	222	}
223	223
224	224	// ----------------------------------------------------------------------------------------
r29404	r29405
226	226	// ----------------------------------------------------------------------------------------
227	227
228	228	netlist_mame_stream_output_t::netlist_mame_stream_output_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
229		: device_t(mconfig, NETLIST_ANALOG_INPUT, "netlist analog input", tag, owner, clock, "netlist_analog_input", __FILE__),
230		netlist_mame_sub_interface(*owner),
231		m_channel(0),
232		m_out_name("")
	229	: device_t(mconfig, NETLIST_ANALOG_INPUT, "netlist analog input", tag, owner, clock, "netlist_analog_input", __FILE__),
	230	netlist_mame_sub_interface(*owner),
	231	m_channel(0),
	232	m_out_name("")
233	233	{
234	234	}
235	235
236	236	void netlist_mame_stream_output_t::static_set_params(device_t &device, int channel, const char *out_name)
237	237	{
238		netlist_mame_stream_output_t &netlist = downcast<netlist_mame_stream_output_t &>(device);
239		netlist.m_out_name = out_name;
240		netlist.m_channel = channel;
	238	netlist_mame_stream_output_t &netlist = downcast<netlist_mame_stream_output_t &>(device);
	239	netlist.m_out_name = out_name;
	240	netlist.m_channel = channel;
241	241	}
242	242
243	243	void netlist_mame_stream_output_t::device_start()
244	244	{
245		LOG_DEV_CALLS(("start %s\n", tag()));
	245	LOG_DEV_CALLS(("start %s\n", tag()));
246	246	}
247	247
248	248	void netlist_mame_stream_output_t::custom_netlist_additions(netlist_setup_t &setup)
249	249	{
250		NETLIB_NAME(sound_out) *snd_out;
251		pstring sname = pstring::sprintf("STREAM_OUT_%d", m_channel);
	250	NETLIB_NAME(sound_out) *snd_out;
	251	pstring sname = pstring::sprintf("STREAM_OUT_%d", m_channel);
252	252
253		snd_out = dynamic_cast<NETLIB_NAME(sound_out) *>(setup.factory().new_device_by_classname("nld_sound_out", setup));
254		setup.register_dev(snd_out, sname);
	253	snd_out = dynamic_cast<NETLIB_NAME(sound_out) *>(setup.factory().new_device_by_classname("nld_sound_out", setup));
	254	setup.register_dev(snd_out, sname);
255	255
256		setup.register_param(sname + ".CHAN" , m_channel);
257		setup.register_param(sname + ".MULT", m_mult);
258		setup.register_param(sname + ".OFFSET", m_offset);
259		setup.register_link(sname + ".IN", m_out_name);
	256	setup.register_param(sname + ".CHAN" , m_channel);
	257	setup.register_param(sname + ".MULT", m_mult);
	258	setup.register_param(sname + ".OFFSET", m_offset);
	259	setup.register_link(sname + ".IN", m_out_name);
260	260	}
261	261
262	262
r29404	r29405
266	266
267	267	void netlist_mame_t::verror(const loglevel_e level, const char *format, va_list ap) const
268	268	{
269		pstring errstr = pstring(format).vprintf(ap);
	269	pstring errstr = pstring(format).vprintf(ap);
270	270
271		switch (level)
272		{
273		case NL_WARNING:
274		logerror("netlist WARNING: %s\n", errstr.cstr());
275		break;
276		case NL_LOG:
277		logerror("netlist LOG: %s\n", errstr.cstr());
278		break;
279		case NL_ERROR:
280		emu_fatalerror error("netlist ERROR: %s\n", errstr.cstr());
281		throw error;
282		break;
283		}
	271	switch (level)
	272	{
	273	case NL_WARNING:
	274	logerror("netlist WARNING: %s\n", errstr.cstr());
	275	break;
	276	case NL_LOG:
	277	logerror("netlist LOG: %s\n", errstr.cstr());
	278	break;
	279	case NL_ERROR:
	280	emu_fatalerror error("netlist ERROR: %s\n", errstr.cstr());
	281	throw error;
	282	break;
	283	}
284	284	}
285	285
286	286	// ----------------------------------------------------------------------------------------
r29404	r29405
293	293
294	294	netlist_mame_device_t::netlist_mame_device_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
295	295	: device_t(mconfig, NETLIST_CORE, "Netlist core device", tag, owner, clock, "netlist_core", __FILE__),
296		m_icount(0),
297		m_div(0),
298		m_rem(0),
299		m_old(netlist_time::zero),
300		m_netlist(NULL),
301		m_setup(NULL),
302		m_setup_func(NULL)
	296	m_icount(0),
	297	m_div(0),
	298	m_rem(0),
	299	m_old(netlist_time::zero),
	300	m_netlist(NULL),
	301	m_setup(NULL),
	302	m_setup_func(NULL)
303	303	{
304	304	}
305	305
306	306	netlist_mame_device_t::netlist_mame_device_t(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *file)
307		: device_t(mconfig, type, name, tag, owner, clock, shortname, file),
308		m_icount(0),
309		m_div(0),
310		m_rem(0),
311		m_old(netlist_time::zero),
312		m_netlist(NULL),
313		m_setup(NULL),
314		m_setup_func(NULL)
	307	: device_t(mconfig, type, name, tag, owner, clock, shortname, file),
	308	m_icount(0),
	309	m_div(0),
	310	m_rem(0),
	311	m_old(netlist_time::zero),
	312	m_netlist(NULL),
	313	m_setup(NULL),
	314	m_setup_func(NULL)
315	315	{
316	316	}
317	317
r29404	r29405
358	358	m_setup->start_devices();
359	359	m_setup->resolve_inputs();
360	360
361		netlist().save(NAME(m_rem));
362		netlist().save(NAME(m_div));
363		netlist().save(NAME(m_old));
	361	netlist().save(NAME(m_rem));
	362	netlist().save(NAME(m_div));
	363	netlist().save(NAME(m_old));
364	364
365	365	save_state();
366	366
367		m_old = netlist_time::zero;
368		m_rem = 0;
	367	m_old = netlist_time::zero;
	368	m_rem = 0;
369	369
370	370	}
371	371
372	372	void netlist_mame_device_t::device_clock_changed()
373	373	{
374		//printf("device_clock_changed\n");
375		m_div = netlist_time::from_hz(clock()).as_raw();
376		//m_rem = 0;
377		NL_VERBOSE_OUT(("Setting clock %" I64FMT "d and divisor %d\n", clockfreq, m_div));
378		//printf("Setting clock %d and divisor %d\n", clock(), m_div);
	374	//printf("device_clock_changed\n");
	375	m_div = netlist_time::from_hz(clock()).as_raw();
	376	//m_rem = 0;
	377	NL_VERBOSE_OUT(("Setting clock %" I64FMT "d and divisor %d\n", clockfreq, m_div));
	378	//printf("Setting clock %d and divisor %d\n", clock(), m_div);
379	379	}
380	380
381	381
382	382	void netlist_mame_device_t::device_reset()
383	383	{
384	384	LOG_DEV_CALLS(("device_reset\n"));
385		m_old = netlist_time::zero;
386		m_rem = 0;
	385	m_old = netlist_time::zero;
	386	m_rem = 0;
387	387	netlist().do_reset();
388	388	}
389	389
r29404	r29405
419	419
420	420	ATTR_HOT ATTR_ALIGN void netlist_mame_device_t::update_time_x()
421	421	{
422		const netlist_time delta = netlist().time() - m_old + netlist_time::from_raw(m_rem);
423		m_old = netlist().time();
424		m_icount -= divu_64x32_rem(delta.as_raw(), m_div, &m_rem);
	422	const netlist_time delta = netlist().time() - m_old + netlist_time::from_raw(m_rem);
	423	m_old = netlist().time();
	424	m_icount -= divu_64x32_rem(delta.as_raw(), m_div, &m_rem);
425	425	}
426	426
427	427	ATTR_HOT ATTR_ALIGN void netlist_mame_device_t::check_mame_abort_slice()
428	428	{
429		if (m_icount <= 0)
430		netlist().abort_current_queue_slice();
	429	if (m_icount <= 0)
	430	netlist().abort_current_queue_slice();
431	431	}
432	432
433	433	ATTR_COLD void netlist_mame_device_t::save_state()
r29404	r29405
444	444	case DT_INT64:
445	445	save_pointer((INT64 *) s->m_ptr, s->m_name, s->m_count);
446	446	break;
447		case DT_INT16:
448		save_pointer((INT16 *) s->m_ptr, s->m_name, s->m_count);
449		break;
	447	case DT_INT16:
	448	save_pointer((INT16 *) s->m_ptr, s->m_name, s->m_count);
	449	break;
450	450	case DT_INT8:
451	451	save_pointer((INT8 *) s->m_ptr, s->m_name, s->m_count);
452	452	break;
r29404	r29405
457	457	save_pointer((bool *) s->m_ptr, s->m_name, s->m_count);
458	458	break;
459	459	case DT_CUSTOM:
460		break;
	460	break;
461	461	case NOT_SUPPORTED:
462	462	default:
463	463	netlist().error("found unsupported save element %s\n", s->m_name.cstr());
r29404	r29405
472	472	// ----------------------------------------------------------------------------------------
473	473
474	474	netlist_mame_cpu_device_t::netlist_mame_cpu_device_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
475		: netlist_mame_device_t(mconfig, NETLIST_CPU, "Netlist cpu device", tag, owner, clock, "netlist_cpu", __FILE__),
476		device_execute_interface(mconfig, *this),
477		device_state_interface(mconfig, *this),
478		device_disasm_interface(mconfig, *this),
479		device_memory_interface(mconfig, *this),
480		m_program_config("program", ENDIANNESS_LITTLE, 8, 12, 0, ADDRESS_MAP_NAME(program_dummy))
	475	: netlist_mame_device_t(mconfig, NETLIST_CPU, "Netlist cpu device", tag, owner, clock, "netlist_cpu", __FILE__),
	476	device_execute_interface(mconfig, *this),
	477	device_state_interface(mconfig, *this),
	478	device_disasm_interface(mconfig, *this),
	479	device_memory_interface(mconfig, *this),
	480	m_program_config("program", ENDIANNESS_LITTLE, 8, 12, 0, ADDRESS_MAP_NAME(program_dummy))
481	481	{
482	482	}
483	483
484	484
485	485	void netlist_mame_cpu_device_t::device_start()
486	486	{
487		netlist_mame_device_t::device_start();
	487	netlist_mame_device_t::device_start();
488	488
489		LOG_DEV_CALLS(("device_start %s\n", tag()));
	489	LOG_DEV_CALLS(("device_start %s\n", tag()));
490	490
491		// State support
	491	// State support
492	492
493		state_add(STATE_GENPC, "curpc", m_genPC).noshow();
	493	state_add(STATE_GENPC, "curpc", m_genPC).noshow();
494	494
495		for (int i=0; i < netlist().m_nets.count(); i++)
496		{
497		netlist_net_t *n = netlist().m_nets[i];
498		if (n->isFamily(netlist_object_t::LOGIC))
499		{
500		state_add(i*2, n->name(), n->Q_state_ptr());
501		}
502		else
503		{
504		state_add(i*2+1, n->name(), n->Q_Analog_state_ptr()).formatstr("%20s");
505		}
506		}
	495	for (int i=0; i < netlist().m_nets.count(); i++)
	496	{
	497	netlist_net_t *n = netlist().m_nets[i];
	498	if (n->isFamily(netlist_object_t::LOGIC))
	499	{
	500	state_add(i*2, n->name(), n->Q_state_ptr());
	501	}
	502	else
	503	{
	504	state_add(i*2+1, n->name(), n->Q_Analog_state_ptr()).formatstr("%20s");
	505	}
	506	}
507	507
508		// set our instruction counter
509		m_icountptr = &m_icount;
	508	// set our instruction counter
	509	m_icountptr = &m_icount;
510	510	}
511	511
512	512
513	513	void netlist_mame_cpu_device_t::nl_register_devices()
514	514	{
515		setup().factory().register_device<nld_analog_callback>( "NETDEV_CALLBACK", "nld_analog_callback", "-");
	515	setup().factory().register_device<nld_analog_callback>( "NETDEV_CALLBACK", "nld_analog_callback", "-");
516	516	}
517	517
518	518	ATTR_COLD UINT64 netlist_mame_cpu_device_t::execute_clocks_to_cycles(UINT64 clocks) const
r29404	r29405
559	559	m_genPC &= 255;
560	560	debugger_instruction_hook(this, m_genPC);
561	561	netlist().process_queue(netlist_time::from_raw(m_div));
562		update_time_x();
	562	update_time_x();
563	563	}
564	564	}
565	565	else
566	566	{
567		netlist().process_queue(netlist_time::from_raw(m_div) * m_icount);
568		update_time_x();
	567	netlist().process_queue(netlist_time::from_raw(m_div) * m_icount);
	568	update_time_x();
569	569	}
570	570	}
571	571
r29404	r29405
574	574	// ----------------------------------------------------------------------------------------
575	575
576	576	netlist_mame_sound_device_t::netlist_mame_sound_device_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
577		: netlist_mame_device_t(mconfig, NETLIST_CPU, "Netlist sound device", tag, owner, clock, "netlist_sound", __FILE__),
578		device_sound_interface(mconfig, *this)
	577	: netlist_mame_device_t(mconfig, NETLIST_CPU, "Netlist sound device", tag, owner, clock, "netlist_sound", __FILE__),
	578	device_sound_interface(mconfig, *this)
579	579	{
580	580	}
581	581
582	582
583	583	void netlist_mame_sound_device_t::device_start()
584	584	{
585		netlist_mame_device_t::device_start();
	585	netlist_mame_device_t::device_start();
586	586
587		LOG_DEV_CALLS(("device_start %s\n", tag()));
	587	LOG_DEV_CALLS(("device_start %s\n", tag()));
588	588
589		// Configure outputs
	589	// Configure outputs
590	590
591		netlist_list_t<nld_sound_out *> outdevs = netlist().get_device_list<nld_sound_out>();
592		if (outdevs.count() == 0)
593		fatalerror("No output devices");
	591	netlist_list_t<nld_sound_out *> outdevs = netlist().get_device_list<nld_sound_out>();
	592	if (outdevs.count() == 0)
	593	fatalerror("No output devices");
594	594
595		m_num_outputs = outdevs.count();
	595	m_num_outputs = outdevs.count();
596	596
597		/* resort channels */
598		for (int i=0; i < MAX_OUT; i++) m_out[i] = NULL;
599		for (int i=0; i < m_num_outputs; i++)
600		{
601		int chan = outdevs[i]->m_channel.Value();
	597	/* resort channels */
	598	for (int i=0; i < MAX_OUT; i++) m_out[i] = NULL;
	599	for (int i=0; i < m_num_outputs; i++)
	600	{
	601	int chan = outdevs[i]->m_channel.Value();
602	602
603		netlist().log("Output %d on channel %d", i, chan);
	603	netlist().log("Output %d on channel %d", i, chan);
604	604
605		if (chan < 0 \|\| chan >= MAX_OUT \|\| chan >= outdevs.count())
606		fatalerror("illegal channel number");
607		m_out[chan] = outdevs[i];
608		m_out[chan]->m_sample = netlist_time::from_hz(clock());
609		m_out[chan]->m_buffer = NULL;
610		}
	605	if (chan < 0 \|\| chan >= MAX_OUT \|\| chan >= outdevs.count())
	606	fatalerror("illegal channel number");
	607	m_out[chan] = outdevs[i];
	608	m_out[chan]->m_sample = netlist_time::from_hz(clock());
	609	m_out[chan]->m_buffer = NULL;
	610	}
611	611
612		// Configure inputs
	612	// Configure inputs
613	613
614		m_num_inputs = 0;
615		m_in = NULL;
	614	m_num_inputs = 0;
	615	m_in = NULL;
616	616
617		netlist_list_t<nld_sound_in *> indevs = netlist().get_device_list<nld_sound_in>();
618		if (indevs.count() > 1)
619		fatalerror("A maximum of one input device is allowed!");
620		if (indevs.count() == 1)
621		{
622		m_in = indevs[0];
623		m_num_inputs = m_in->resolve();
624		m_in->m_inc = netlist_time::from_hz(clock());
625		}
	617	netlist_list_t<nld_sound_in *> indevs = netlist().get_device_list<nld_sound_in>();
	618	if (indevs.count() > 1)
	619	fatalerror("A maximum of one input device is allowed!");
	620	if (indevs.count() == 1)
	621	{
	622	m_in = indevs[0];
	623	m_num_inputs = m_in->resolve();
	624	m_in->m_inc = netlist_time::from_hz(clock());
	625	}
626	626
627		/* initialize the stream(s) */
628		m_stream = machine().sound().stream_alloc(*this, m_num_inputs, m_num_outputs, clock());
	627	/* initialize the stream(s) */
	628	m_stream = machine().sound().stream_alloc(*this, m_num_inputs, m_num_outputs, clock());
629	629
630	630	}
631	631
632	632	void netlist_mame_sound_device_t::nl_register_devices()
633	633	{
634		setup().factory().register_device<nld_sound_out>("NETDEV_SOUND_OUT", "nld_sound_out", "+CHAN");
635		setup().factory().register_device<nld_sound_in>("NETDEV_SOUND_IN", "nld_sound_in", "-");
	634	setup().factory().register_device<nld_sound_out>("NETDEV_SOUND_OUT", "nld_sound_out", "+CHAN");
	635	setup().factory().register_device<nld_sound_in>("NETDEV_SOUND_IN", "nld_sound_in", "-");
636	636	}
637	637
638	638
639	639	void netlist_mame_sound_device_t::sound_stream_update(sound_stream &stream, stream_sample_t inputs, stream_sample_t outputs, int samples)
640	640	{
641		for (int i=0; i < m_num_outputs; i++)
642		{
643		m_out[i]->m_buffer = outputs[i];
644		}
	641	for (int i=0; i < m_num_outputs; i++)
	642	{
	643	m_out[i]->m_buffer = outputs[i];
	644	}
645	645
646		if (m_num_inputs)
647		m_in->buffer_reset();
	646	if (m_num_inputs)
	647	m_in->buffer_reset();
648	648
649		for (int i=0; i < m_num_inputs; i++)
650		{
651		m_in->m_buffer[i] = inputs[i];
652		}
	649	for (int i=0; i < m_num_inputs; i++)
	650	{
	651	m_in->m_buffer[i] = inputs[i];
	652	}
653	653
654		netlist_time cur = netlist().time();
	654	netlist_time cur = netlist().time();
655	655
656		netlist().process_queue(netlist_time::from_raw(m_div) * samples);
	656	netlist().process_queue(netlist_time::from_raw(m_div) * samples);
657	657
658		cur += (netlist_time::from_raw(m_div) * samples);
	658	cur += (netlist_time::from_raw(m_div) * samples);
659	659
660		for (int i=0; i < m_num_outputs; i++)
661		{
662		m_out[i]->sound_update(cur);
663		m_out[i]->buffer_reset(cur);
664		}
	660	for (int i=0; i < m_num_outputs; i++)
	661	{
	662	m_out[i]->sound_update(cur);
	663	m_out[i]->buffer_reset(cur);
	664	}
665	665	}
666

trunk/src/emu/machine/netlist.h
r29404	r29405
68	68	netlist_mame_analog_input_t::static_set_mult_offset(*device, _mult, _offset);
69	69
70	70	#define MCFG_NETLIST_ANALOG_OUTPUT(_basetag, _tag, _IN, _class, _member, _class_tag) \
71		MCFG_DEVICE_ADD(_basetag ":" _tag, NETLIST_ANALOG_OUTPUT, 0) \
72		netlist_mame_analog_output_t::static_set_params(*device, _IN, \
73		netlist_analog_output_delegate(& _class :: _member, \
74		# _class "::" # _member, _class_tag, (_class *) 0) );
	71	MCFG_DEVICE_ADD(_basetag ":" _tag, NETLIST_ANALOG_OUTPUT, 0) \
	72	netlist_mame_analog_output_t::static_set_params(*device, _IN, \
	73	netlist_analog_output_delegate(& _class :: _member, \
	74	# _class "::" # _member, _class_tag, (_class *) 0) );
75	75
76	76	#define MCFG_NETLIST_LOGIC_INPUT(_basetag, _tag, _name, _shift, _mask) \
77	77	MCFG_DEVICE_ADD(_basetag ":" _tag, NETLIST_LOGIC_INPUT, 0) \
78	78	netlist_mame_logic_input_t::static_set_params(*device, _name, _mask, _shift);
79	79
80	80	#define MCFG_NETLIST_STREAM_INPUT(_basetag, _chan, _name) \
81		MCFG_DEVICE_ADD(_basetag ":cin" # _chan, NETLIST_STREAM_INPUT, 0) \
82		netlist_mame_stream_input_t::static_set_params(*device, _chan, _name);
	81	MCFG_DEVICE_ADD(_basetag ":cin" # _chan, NETLIST_STREAM_INPUT, 0) \
	82	netlist_mame_stream_input_t::static_set_params(*device, _chan, _name);
83	83
84	84	#define MCFG_NETLIST_STREAM_OUTPUT(_basetag, _chan, _name) \
85		MCFG_DEVICE_ADD(_basetag ":cout" # _chan, NETLIST_STREAM_OUTPUT, 0) \
86		netlist_mame_stream_output_t::static_set_params(*device, _chan, _name);
	85	MCFG_DEVICE_ADD(_basetag ":cout" # _chan, NETLIST_STREAM_OUTPUT, 0) \
	86	netlist_mame_stream_output_t::static_set_params(*device, _chan, _name);
87	87
88	88
89	89	#define NETLIST_LOGIC_PORT_CHANGED(_base, _tag) \
90	90	PORT_CHANGED_MEMBER(_base ":" _tag, netlist_mame_logic_input_t, input_changed, 0)
91	91
92	92	#define NETLIST_ANALOG_PORT_CHANGED(_base, _tag) \
93		PORT_CHANGED_MEMBER(_base ":" _tag, netlist_mame_analog_input_t, input_changed, 0)
	93	PORT_CHANGED_MEMBER(_base ":" _tag, netlist_mame_analog_input_t, input_changed, 0)
94	94
95	95
96	96	// ----------------------------------------------------------------------------------------
r29404	r29405
101	101	setup.parse((char *)downcast<netlist_mame_t &>(setup.netlist()).machine().root_device().memregion(_name)->base());
102	102
103	103	#define NETDEV_ANALOG_CALLBACK_MEMBER(_name) \
104		void _name(const double data, const attotime &time)
	104	void _name(const double data, const attotime &time)
105	105
106	106
107	107	#if 0
r29404	r29405
116	116
117	117	#if 0
118	118	#define NETDEV_SOUND_OUT(_name, _v, _m) \
119		NET_REGISTER_DEV(sound_out, _name) \
120		PARAM(_name.CHAN, _v) \
121		PARAM(_name.MULT, _m)
	119	NET_REGISTER_DEV(sound_out, _name) \
	120	PARAM(_name.CHAN, _v) \
	121	PARAM(_name.MULT, _m)
122	122
123	123	#define NETDEV_SOUND_IN(_name) \
124		NET_REGISTER_DEV(sound_in, _name)
	124	NET_REGISTER_DEV(sound_in, _name)
125	125	#endif
126	126
127	127	class netlist_mame_device_t;
r29404	r29405
166	166	ATTR_HOT inline netlist_setup_t &setup() { return *m_setup; }
167	167	ATTR_HOT inline netlist_mame_t &netlist() { return *m_netlist; }
168	168
169		ATTR_HOT inline netlist_time last_time_update() { return m_old; }
	169	ATTR_HOT inline netlist_time last_time_update() { return m_old; }
170	170	ATTR_HOT void update_time_x();
171	171	ATTR_HOT void check_mame_abort_slice();
172	172
173		int m_icount;
	173	int m_icount;
174	174
175	175	protected:
176		// Custom to netlist ...
	176	// Custom to netlist ...
177	177
178		virtual void nl_register_devices() { };
	178	virtual void nl_register_devices() { };
179	179
180		// device_t overrides
	180	// device_t overrides
181	181	virtual void device_config_complete();
182	182	virtual void device_start();
183	183	virtual void device_stop();
r29404	r29405
185	185	virtual void device_post_load();
186	186	virtual void device_pre_save();
187	187	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
188		//virtual void device_debug_setup();
189		virtual void device_clock_changed();
	188	//virtual void device_debug_setup();
	189	virtual void device_clock_changed();
190	190
191		UINT32 m_div;
	191	UINT32 m_div;
192	192
193	193	private:
194		void save_state();
	194	void save_state();
195	195
196		/* timing support here - so sound can hijack it ... */
197		UINT32 m_rem;
198		netlist_time m_old;
	196	/* timing support here - so sound can hijack it ... */
	197	UINT32 m_rem;
	198	netlist_time m_old;
199	199
200	200	netlist_mame_t * m_netlist;
201		netlist_setup_t * m_setup;
	201	netlist_setup_t * m_setup;
202	202
203	203	void (*m_setup_func)(netlist_setup_t &);
204	204	};
r29404	r29405
213	213	// ----------------------------------------------------------------------------------------
214	214
215	215	class netlist_mame_cpu_device_t : public netlist_mame_device_t,
216		public device_execute_interface,
217		public device_state_interface,
218		public device_disasm_interface,
219		public device_memory_interface
	216	public device_execute_interface,
	217	public device_state_interface,
	218	public device_disasm_interface,
	219	public device_memory_interface
220	220	{
221	221	public:
222	222
223		// construction/destruction
224		netlist_mame_cpu_device_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
225		virtual ~netlist_mame_cpu_device_t() {}
	223	// construction/destruction
	224	netlist_mame_cpu_device_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	225	virtual ~netlist_mame_cpu_device_t() {}
226	226
227		static void static_set_constructor(device_t &device, void (*setup_func)(netlist_setup_t &));
	227	static void static_set_constructor(device_t &device, void (*setup_func)(netlist_setup_t &));
228	228
229	229	protected:
230		// netlist_mame_device_t
231		virtual void nl_register_devices();
	230	// netlist_mame_device_t
	231	virtual void nl_register_devices();
232	232
233		// device_t overrides
	233	// device_t overrides
234	234
235		//virtual void device_config_complete();
236		virtual void device_start();
237		//virtual void device_stop();
238		//virtual void device_reset();
239		//virtual void device_post_load();
240		//virtual void device_pre_save();
241		//virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	235	//virtual void device_config_complete();
	236	virtual void device_start();
	237	//virtual void device_stop();
	238	//virtual void device_reset();
	239	//virtual void device_post_load();
	240	//virtual void device_pre_save();
	241	//virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
242	242
243		// device_execute_interface overrides
	243	// device_execute_interface overrides
244	244
245		virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const;
246		virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const;
	245	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const;
	246	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const;
247	247
248		ATTR_HOT virtual void execute_run();
	248	ATTR_HOT virtual void execute_run();
249	249
250		// device_disasm_interface overrides
251		ATTR_COLD virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
252		ATTR_COLD virtual UINT32 disasm_max_opcode_bytes() const { return 1; }
253		ATTR_COLD virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	250	// device_disasm_interface overrides
	251	ATTR_COLD virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
	252	ATTR_COLD virtual UINT32 disasm_max_opcode_bytes() const { return 1; }
	253	ATTR_COLD virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
254	254
255		// device_memory_interface overrides
	255	// device_memory_interface overrides
256	256
257		address_space_config m_program_config;
	257	address_space_config m_program_config;
258	258
259		virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
260		{
261		switch (spacenum)
262		{
263		case AS_PROGRAM: return &m_program_config;
264		case AS_IO: return NULL;
265		default: return NULL;
266		}
267		}
	259	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
	260	{
	261	switch (spacenum)
	262	{
	263	case AS_PROGRAM: return &m_program_config;
	264	case AS_IO: return NULL;
	265	default: return NULL;
	266	}
	267	}
268	268
269		// device_state_interface overrides
	269	// device_state_interface overrides
270	270
271		virtual void state_string_export(const device_state_entry &entry, astring &string)
272		{
273		if (entry.index() >= 0)
274		{
275		if (entry.index() & 1)
276		string.format("%10.6f", ((double ) entry.dataptr()));
277		else
278		string.format("%d", ((netlist_sig_t ) entry.dataptr()));
279		}
280		}
	271	virtual void state_string_export(const device_state_entry &entry, astring &string)
	272	{
	273	if (entry.index() >= 0)
	274	{
	275	if (entry.index() & 1)
	276	string.format("%10.6f", ((double ) entry.dataptr()));
	277	else
	278	string.format("%d", ((netlist_sig_t ) entry.dataptr()));
	279	}
	280	}
281	281
282	282	private:
283	283
284		int m_genPC;
	284	int m_genPC;
285	285
286	286	};
287	287
r29404	r29405
293	293	// ----------------------------------------------------------------------------------------
294	294
295	295	class netlist_mame_sound_device_t : public netlist_mame_device_t,
296		public device_sound_interface
	296	public device_sound_interface
297	297	{
298	298	public:
299	299
300		// construction/destruction
301		netlist_mame_sound_device_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
302		virtual ~netlist_mame_sound_device_t() {}
	300	// construction/destruction
	301	netlist_mame_sound_device_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	302	virtual ~netlist_mame_sound_device_t() {}
303	303
304		static void static_set_constructor(device_t &device, void (*setup_func)(netlist_setup_t &));
	304	static void static_set_constructor(device_t &device, void (*setup_func)(netlist_setup_t &));
305	305
306		inline sound_stream *get_stream() { return m_stream; }
	306	inline sound_stream *get_stream() { return m_stream; }
307	307
308	308
309		// device_sound_interface overrides
	309	// device_sound_interface overrides
310	310
311		virtual void sound_stream_update(sound_stream &stream, stream_sample_t inputs, stream_sample_t outputs, int samples);
	311	virtual void sound_stream_update(sound_stream &stream, stream_sample_t inputs, stream_sample_t outputs, int samples);
312	312
313	313	protected:
314		// netlist_mame_device_t
315		virtual void nl_register_devices();
	314	// netlist_mame_device_t
	315	virtual void nl_register_devices();
316	316
317		// device_t overrides
	317	// device_t overrides
318	318
319		//virtual void device_config_complete();
320		virtual void device_start();
321		//virtual void device_stop();
322		//virtual void device_reset();
323		//virtual void device_post_load();
324		//virtual void device_pre_save();
325		//virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	319	//virtual void device_config_complete();
	320	virtual void device_start();
	321	//virtual void device_stop();
	322	//virtual void device_reset();
	323	//virtual void device_post_load();
	324	//virtual void device_pre_save();
	325	//virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
326	326
327	327	private:
328	328
329		static const int MAX_OUT = 10;
330		nld_sound_out *m_out[MAX_OUT];
331		nld_sound_in *m_in;
332		sound_stream *m_stream;
333		int m_num_inputs;
334		int m_num_outputs;
	329	static const int MAX_OUT = 10;
	330	nld_sound_out *m_out[MAX_OUT];
	331	nld_sound_in *m_in;
	332	sound_stream *m_stream;
	333	int m_num_inputs;
	334	int m_num_outputs;
335	335
336	336	};
337	337
r29404	r29405
344	344	public:
345	345	// construction/destruction
346	346	netlist_mame_sub_interface(device_t &aowner)
347		: m_offset(0.0), m_mult(1.0)
348		{
349		m_owner = dynamic_cast<netlist_mame_device_t *>(&aowner);
350		m_sound = dynamic_cast<netlist_mame_sound_device_t *>(&aowner);
351		}
	347	: m_offset(0.0), m_mult(1.0)
	348	{
	349	m_owner = dynamic_cast<netlist_mame_device_t *>(&aowner);
	350	m_sound = dynamic_cast<netlist_mame_sound_device_t *>(&aowner);
	351	}
352	352	virtual ~netlist_mame_sub_interface() { }
353	353
354	354	virtual void custom_netlist_additions(netlist_setup_t &setup) { }
r29404	r29405
359	359
360	360	inline void update_to_current_time()
361	361	{
362		m_sound->get_stream()->update();
	362	m_sound->get_stream()->update();
363	363	}
364	364
365		static void static_set_mult_offset(device_t &device, const double mult, const double offset);
	365	static void static_set_mult_offset(device_t &device, const double mult, const double offset);
366	366
367	367	protected:
368		double m_offset;
369		double m_mult;
	368	double m_offset;
	369	double m_mult;
370	370
371	371	private:
372	372	netlist_mame_device_t *m_owner;
r29404	r29405
390	390
391	391	inline void write(const double val)
392	392	{
393		if (is_sound_device())
394		{
395		update_to_current_time();
396		m_param->setTo(val * m_mult + m_offset);
397		}
398		else
399		{
400		// FIXME: use device timer ....
401		m_param->setTo(val * m_mult + m_offset);
402		}
	393	if (is_sound_device())
	394	{
	395	update_to_current_time();
	396	m_param->setTo(val * m_mult + m_offset);
	397	}
	398	else
	399	{
	400	// FIXME: use device timer ....
	401	m_param->setTo(val * m_mult + m_offset);
	402	}
403	403	}
404	404
405	405	inline DECLARE_INPUT_CHANGED_MEMBER(input_changed)
r29404	r29405
432	432	typedef device_delegate<void (const double, const attotime &)> netlist_analog_output_delegate;
433	433
434	434	class netlist_mame_analog_output_t : public device_t,
435		public netlist_mame_sub_interface
	435	public netlist_mame_sub_interface
436	436	{
437	437	public:
438	438
439		// construction/destruction
440		netlist_mame_analog_output_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
441		virtual ~netlist_mame_analog_output_t() { }
	439	// construction/destruction
	440	netlist_mame_analog_output_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	441	virtual ~netlist_mame_analog_output_t() { }
442	442
443		static void static_set_params(device_t &device, const char *in_name, netlist_analog_output_delegate adelegate);
	443	static void static_set_params(device_t &device, const char *in_name, netlist_analog_output_delegate adelegate);
444	444
445	445	protected:
446		// device-level overrides
447		virtual void device_start();
448		virtual void custom_netlist_additions(netlist_setup_t &setup);
	446	// device-level overrides
	447	virtual void device_start();
	448	virtual void custom_netlist_additions(netlist_setup_t &setup);
449	449
450	450	private:
451		pstring m_in;
452		netlist_analog_output_delegate m_delegate;
	451	pstring m_in;
	452	netlist_analog_output_delegate m_delegate;
453	453	};
454	454
455	455
r29404	r29405
470	470
471	471	inline void write(const UINT32 val)
472	472	{
473		if (is_sound_device())
474		{
475		update_to_current_time();
476		m_param->setTo((val >> m_shift) & m_mask);
477		}
478		else
479		{
480		// FIXME: use device timer ....
481		m_param->setTo((val >> m_shift) & m_mask);
482		}
	473	if (is_sound_device())
	474	{
	475	update_to_current_time();
	476	m_param->setTo((val >> m_shift) & m_mask);
	477	}
	478	else
	479	{
	480	// FIXME: use device timer ....
	481	m_param->setTo((val >> m_shift) & m_mask);
	482	}
483	483	}
484	484
485	485	inline DECLARE_INPUT_CHANGED_MEMBER(input_changed) { write(newval); }
r29404	r29405
505	505	// ----------------------------------------------------------------------------------------
506	506
507	507	class netlist_mame_stream_input_t : public device_t,
508		public netlist_mame_sub_interface
	508	public netlist_mame_sub_interface
509	509	{
510	510	public:
511	511
512		// construction/destruction
513		netlist_mame_stream_input_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
514		virtual ~netlist_mame_stream_input_t() { }
	512	// construction/destruction
	513	netlist_mame_stream_input_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	514	virtual ~netlist_mame_stream_input_t() { }
515	515
516		static void static_set_params(device_t &device, int channel, const char *param_name);
	516	static void static_set_params(device_t &device, int channel, const char *param_name);
517	517
518	518	protected:
519		// device-level overrides
520		virtual void device_start();
521		virtual void custom_netlist_additions(netlist_setup_t &setup);
	519	// device-level overrides
	520	virtual void device_start();
	521	virtual void custom_netlist_additions(netlist_setup_t &setup);
522	522	private:
523		UINT32 m_channel;
524		pstring m_param_name;
	523	UINT32 m_channel;
	524	pstring m_param_name;
525	525	};
526	526
527	527	// ----------------------------------------------------------------------------------------
r29404	r29405
529	529	// ----------------------------------------------------------------------------------------
530	530
531	531	class netlist_mame_stream_output_t : public device_t,
532		public netlist_mame_sub_interface
	532	public netlist_mame_sub_interface
533	533	{
534	534	public:
535	535
536		// construction/destruction
537		netlist_mame_stream_output_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
538		virtual ~netlist_mame_stream_output_t() { }
	536	// construction/destruction
	537	netlist_mame_stream_output_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	538	virtual ~netlist_mame_stream_output_t() { }
539	539
540		static void static_set_params(device_t &device, int channel, const char *out_name);
	540	static void static_set_params(device_t &device, int channel, const char *out_name);
541	541
542	542	protected:
543		// device-level overrides
544		virtual void device_start();
545		virtual void custom_netlist_additions(netlist_setup_t &setup);
	543	// device-level overrides
	544	virtual void device_start();
	545	virtual void custom_netlist_additions(netlist_setup_t &setup);
546	546	private:
547		UINT32 m_channel;
548		pstring m_out_name;
	547	UINT32 m_channel;
	548	pstring m_out_name;
549	549	};
550	550	// ----------------------------------------------------------------------------------------
551	551	// netdev_callback
r29404	r29405
563	563	m_cpu_device = downcast<netlist_mame_cpu_device_t *>(&downcast<netlist_mame_t &>(netlist()).parent());
564	564	}
565	565
566		ATTR_COLD void reset()
567		{
568		}
	566	ATTR_COLD void reset()
	567	{
	568	}
569	569
570	570	ATTR_COLD void register_callback(netlist_analog_output_delegate callback)
571	571	{
r29404	r29405
574	574
575	575	ATTR_HOT void update()
576	576	{
577		m_cpu_device->update_time_x();
578		m_callback(INPANALOG(m_in), m_cpu_device->local_time());
579		m_cpu_device->check_mame_abort_slice();
	577	m_cpu_device->update_time_x();
	578	m_callback(INPANALOG(m_in), m_cpu_device->local_time());
	579	m_cpu_device->check_mame_abort_slice();
580	580	}
581	581
582	582	private:
r29404	r29405
601	601	{
602	602	register_input("IN", m_in);
603	603	register_param("CHAN", m_channel, 0);
604		register_param("MULT", m_mult, 1000.0);
605		register_param("OFFSET", m_offset, 0.0);
606		m_sample = netlist_time::from_hz(1); //sufficiently big enough
607		save(NAME(m_last_buffer));
	604	register_param("MULT", m_mult, 1000.0);
	605	register_param("OFFSET", m_offset, 0.0);
	606	m_sample = netlist_time::from_hz(1); //sufficiently big enough
	607	save(NAME(m_last_buffer));
608	608	}
609	609
610		ATTR_COLD void reset()
611		{
612		m_cur = 0;
613		m_last_pos = 0;
614		m_last_buffer = netlist_time::zero;
615		}
	610	ATTR_COLD void reset()
	611	{
	612	m_cur = 0;
	613	m_last_pos = 0;
	614	m_last_buffer = netlist_time::zero;
	615	}
616	616
617	617	ATTR_HOT void sound_update(const netlist_time upto)
618	618	{
r29404	r29405
634	634
635	635	ATTR_HOT void buffer_reset(netlist_time upto)
636	636	{
637		m_last_pos = 0;
638		m_last_buffer = upto;
	637	m_last_pos = 0;
	638	m_last_buffer = upto;
639	639	}
640	640
641	641	netlist_param_int_t m_channel;
642		netlist_param_double_t m_mult;
643		netlist_param_double_t m_offset;
644		stream_sample_t *m_buffer;
645		netlist_time m_sample;
	642	netlist_param_double_t m_mult;
	643	netlist_param_double_t m_offset;
	644	stream_sample_t *m_buffer;
	645	netlist_time m_sample;
646	646
647	647	private:
648	648	netlist_analog_input_t m_in;
r29404	r29405
658	658	class NETLIB_NAME(sound_in) : public netlist_device_t
659	659	{
660	660	public:
661		NETLIB_NAME(sound_in)()
662		: netlist_device_t() { }
	661	NETLIB_NAME(sound_in)()
	662	: netlist_device_t() { }
663	663
664		static const int MAX_INPUT_CHANNELS = 10;
	664	static const int MAX_INPUT_CHANNELS = 10;
665	665
666		ATTR_COLD void start()
667		{
668		// clock part
669		register_output("Q", m_Q);
670		register_input("FB", m_feedback);
	666	ATTR_COLD void start()
	667	{
	668	// clock part
	669	register_output("Q", m_Q);
	670	register_input("FB", m_feedback);
671	671
672		connect(m_feedback, m_Q);
673		m_inc = netlist_time::from_nsec(1);
	672	connect(m_feedback, m_Q);
	673	m_inc = netlist_time::from_nsec(1);
674	674
675	675
676		for (int i = 0; i < MAX_INPUT_CHANNELS; i++)
677		{
678		register_param(pstring::sprintf("CHAN%d", i), m_param_name[i], "");
679		register_param(pstring::sprintf("MULT%d", i), m_param_mult[i], 1.0);
680		register_param(pstring::sprintf("OFFSET%d", i), m_param_offset[i], 0.0);
681		}
682		m_num_channel = 0;
683		}
	676	for (int i = 0; i < MAX_INPUT_CHANNELS; i++)
	677	{
	678	register_param(pstring::sprintf("CHAN%d", i), m_param_name[i], "");
	679	register_param(pstring::sprintf("MULT%d", i), m_param_mult[i], 1.0);
	680	register_param(pstring::sprintf("OFFSET%d", i), m_param_offset[i], 0.0);
	681	}
	682	m_num_channel = 0;
	683	}
684	684
685		ATTR_COLD void reset()
686		{
687		m_pos = 0;
688		for (int i = 0; i < MAX_INPUT_CHANNELS; i++)
689		m_buffer[i] = NULL;
690		}
	685	ATTR_COLD void reset()
	686	{
	687	m_pos = 0;
	688	for (int i = 0; i < MAX_INPUT_CHANNELS; i++)
	689	m_buffer[i] = NULL;
	690	}
691	691
692		ATTR_COLD int resolve()
693		{
694		m_pos = 0;
695		for (int i = 0; i < MAX_INPUT_CHANNELS; i++)
696		{
697		if (m_param_name[i].Value() != "")
698		{
699		if (i != m_num_channel)
700		netlist().error("sound input numbering has to be sequential!");
701		m_num_channel++;
702		m_param[i] = dynamic_cast<netlist_param_double_t *>(setup().find_param(m_param_name[i].Value(), true));
703		}
704		}
705		return m_num_channel;
706		}
	692	ATTR_COLD int resolve()
	693	{
	694	m_pos = 0;
	695	for (int i = 0; i < MAX_INPUT_CHANNELS; i++)
	696	{
	697	if (m_param_name[i].Value() != "")
	698	{
	699	if (i != m_num_channel)
	700	netlist().error("sound input numbering has to be sequential!");
	701	m_num_channel++;
	702	m_param[i] = dynamic_cast<netlist_param_double_t *>(setup().find_param(m_param_name[i].Value(), true));
	703	}
	704	}
	705	return m_num_channel;
	706	}
707	707
708		ATTR_HOT void update()
709		{
710		for (int i=0; i<m_num_channel; i++)
711		{
712		if (m_buffer[i] == NULL)
713		break; // stop, called outside of stream_update
714		double v = m_buffer[i][m_pos];
715		m_param[i]->setTo(v * m_param_mult[i].Value() + m_param_offset[i].Value());
716		}
717		m_pos++;
718		OUTLOGIC(m_Q, !m_Q.net().new_Q(), m_inc );
719		}
	708	ATTR_HOT void update()
	709	{
	710	for (int i=0; i<m_num_channel; i++)
	711	{
	712	if (m_buffer[i] == NULL)
	713	break; // stop, called outside of stream_update
	714	double v = m_buffer[i][m_pos];
	715	m_param[i]->setTo(v * m_param_mult[i].Value() + m_param_offset[i].Value());
	716	}
	717	m_pos++;
	718	OUTLOGIC(m_Q, !m_Q.net().new_Q(), m_inc );
	719	}
720	720
721		ATTR_HOT void buffer_reset()
722		{
723		m_pos = 0;
724		}
	721	ATTR_HOT void buffer_reset()
	722	{
	723	m_pos = 0;
	724	}
725	725
726		netlist_param_str_t m_param_name[MAX_INPUT_CHANNELS];
727		netlist_param_double_t *m_param[MAX_INPUT_CHANNELS];
728		stream_sample_t *m_buffer[MAX_INPUT_CHANNELS];
729		netlist_param_double_t m_param_mult[MAX_INPUT_CHANNELS];
730		netlist_param_double_t m_param_offset[MAX_INPUT_CHANNELS];
731		netlist_time m_inc;
	726	netlist_param_str_t m_param_name[MAX_INPUT_CHANNELS];
	727	netlist_param_double_t *m_param[MAX_INPUT_CHANNELS];
	728	stream_sample_t *m_buffer[MAX_INPUT_CHANNELS];
	729	netlist_param_double_t m_param_mult[MAX_INPUT_CHANNELS];
	730	netlist_param_double_t m_param_offset[MAX_INPUT_CHANNELS];
	731	netlist_time m_inc;
732	732
733	733	private:
734		netlist_ttl_input_t m_feedback;
735		netlist_ttl_output_t m_Q;
	734	netlist_ttl_input_t m_feedback;
	735	netlist_ttl_output_t m_Q;
736	736
737		int m_pos;
738		int m_num_channel;
	737	int m_pos;
	738	int m_num_channel;
739	739	};
740	740
741	741	// device type definition

trunk/src/emu/machine/terminal.c
r29404	r29405
418	418	}
419	419
420	420	const device_type GENERIC_TERMINAL = &device_creator<generic_terminal_device>;
421

trunk/src/emu/machine/pc_lpt.c
r29404	r29405
167	167	m_cent_status_in->write_bit6(state);
168	168	update_irq();
169	169	}
170

trunk/src/emu/machine/6526cia.h
r29404	r29405
1	1	/**********************************************************************
2
3		WARNING: DO NOT USE! WILL BE REMOVED IN FAVOR OF machine/mos6526.h
4	2
	3	WARNING: DO NOT USE! WILL BE REMOVED IN FAVOR OF machine/mos6526.h
	4
5	5	**********************************************************************
6	6
7	7	MOS 6526/8520 Complex Interface Adapter emulation

trunk/src/emu/machine/saturn.c
r29404	r29405
762	762
763	763	if (offset != 0)
764	764	{
765		if (data == ASSERT_LINE) m_scsp_last_line = offset;
	765	if (data == ASSERT_LINE) m_scsp_last_line = offset;
766	766	m_audiocpu->set_input_line(offset, data);
767		}
	767	}
768	768	else
769	769	{
770	770	m_audiocpu->set_input_line(m_scsp_last_line, data);

trunk/src/emu/machine/seibu_cop.h
r29404	r29405
1	1	/***************************************************************************
2	2
3		Seibu COP device
	3	Seibu COP device
4	4
5	5	***************************************************************************/
6	6
r29404	r29405
20	20
21	21	#define MCFG_SEIBU_COP_IN_WORD_CB(_devcb) \
22	22	devcb = &seibu_cop_device::set_in_word_callback(*device, DEVCB2_##_devcb);
23
	23
24	24	#define MCFG_SEIBU_COP_IN_DWORD_CB(_devcb) \
25	25	devcb = &seibu_cop_device::set_in_dword_callback(*device, DEVCB2_##_devcb);
26	26
r29404	r29405
32	32
33	33	#define MCFG_SEIBU_COP_OUT_DWORD_CB(_devcb) \
34	34	devcb = &seibu_cop_device::set_out_dword_callback(*device, DEVCB2_##_devcb);
35
36	35
37	36
	37
38	38	//**************************************************************************
39	39	// TYPE DEFINITIONS
40	40	//**************************************************************************
r29404	r29405
47	47	public:
48	48	// construction/destruction
49	49	seibu_cop_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
50
	50
51	51	template<class _Object> static devcb2_base &set_in_byte_callback(device_t &device, _Object object) { return downcast<seibu_cop_device &>(device).m_in_byte_cb.set_callback(object); }
52	52	template<class _Object> static devcb2_base &set_in_word_callback(device_t &device, _Object object) { return downcast<seibu_cop_device &>(device).m_in_word_cb.set_callback(object); }
53	53	template<class _Object> static devcb2_base &set_in_dword_callback(device_t &device, _Object object) { return downcast<seibu_cop_device &>(device).m_in_dword_cb.set_callback(object); }

trunk/src/emu/machine/mos6551.c
r29404	r29405
577	577	m_rx_counter = 0;
578	578
579	579	if (LOG) logerror("MOS6551 '%s': RX STOP BIT\n", tag());
580
	580
581	581	if (!(m_status & SR_RDRF))
582	582	{
583	583	if (!m_rxd)

trunk/src/emu/machine/i8355.h
r29404	r29405
57	57
58	58	#define MCFG_I8355_OUT_PA_CB(_devcb) \
59	59	devcb = &i8355_device::set_out_pa_callback(*device, DEVCB2_##_devcb);
60
	60
61	61	#define MCFG_I8355_IN_PB_CB(_devcb) \
62	62	devcb = &i8355_device::set_in_pb_callback(*device, DEVCB2_##_devcb);
63
	63
64	64	#define MCFG_I8355_OUT_PB_CB(_devcb) \
65	65	devcb = &i8355_device::set_out_pb_callback(*device, DEVCB2_##_devcb);
66
67	66
	67
68	68	///*************************************************************************
69	69	// TYPE DEFINITIONS
70	70	///*************************************************************************
r29404	r29405
82	82	template<class _Object> static devcb2_base &set_out_pa_callback(device_t &device, _Object object) { return downcast<i8355_device &>(device).m_out_pa_cb.set_callback(object); }
83	83	template<class _Object> static devcb2_base &set_in_pb_callback(device_t &device, _Object object) { return downcast<i8355_device &>(device).m_in_pb_cb.set_callback(object); }
84	84	template<class _Object> static devcb2_base &set_out_pb_callback(device_t &device, _Object object) { return downcast<i8355_device &>(device).m_out_pb_cb.set_callback(object); }
85
	85
86	86	DECLARE_READ8_MEMBER( io_r );
87	87	DECLARE_WRITE8_MEMBER( io_w );
88	88

trunk/src/emu/machine/mc6843.c
r29404	r29405
144	144	img->floppy_drive_set_ready_state(FLOPPY_DRIVE_READY, 0 );
145	145	img->floppy_drive_set_rpm( 300. );
146	146	}
147
	147
148	148	/* reset registers */
149	149	m_CMR &= 0xf0; /* zero only command */
150	150	m_ISR = 0;
r29404	r29405
464	464	}
465	465	}
466	466	break;
467
	467
468	468	default:
469	469	break;
470	470	}

trunk/src/emu/machine/8042kbdc.h
r29404	r29405
101	101	int m_offset1;
102	102
103	103	int m_poll_delay;
104
	104
105	105	required_device<at_keyboard_device> m_keyboard_dev;
106	106
107	107	devcb_resolved_write_line m_system_reset_func;

trunk/src/emu/machine/mc6843.h
r29404	r29405
19	19	public:
20	20	mc6843_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
21	21	~mc6843_device() {}
22
	22
23	23	template<class _Object> static devcb2_base &set_irq_wr_callback(device_t &device, _Object object) { return downcast<mc6843_device &>(device).m_write_irq.set_callback(object); }
24	24
25	25	DECLARE_READ8_MEMBER(read);
r29404	r29405
34	34	virtual void device_start();
35	35	virtual void device_reset();
36	36	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
37
	37
38	38	private:
39	39	enum
40	40	{
41	41	TIMER_CONT
42	42	};
43
	43
44	44	devcb2_write_line m_write_irq;
45	45
46	46	/* registers */
r29404	r29405
66	66
67	67	/* trigger delayed actions (bottom halves) */
68	68	emu_timer* m_timer_cont;
69
	69
70	70	legacy_floppy_image_device* floppy_image(UINT8 drive);
71	71	legacy_floppy_image_device* floppy_image();
72	72	void status_update();
r29404	r29405
78	78	void finish_RCR();
79	79	void cont_SR();
80	80	void cont_SW();
81
	81
82	82	};
83	83
84	84	extern const device_type MC6843;

trunk/src/emu/machine/68561mpcc.c
r29404	r29405
160	160	void mpcc68561_t::device_start()
161	161	{
162	162	intrq_cb.resolve_safe();
163
	163
164	164	memset(channel, 0, sizeof(channel));
165	165
166	166	mode = 0;

trunk/src/emu/machine/s3c2400.c
r29404	r29405
67	67	s3c2400_device::~s3c2400_device()
68	68	{
69	69	}
70
	70
71	71	//-------------------------------------------------
72	72	// static_set_palette_tag: Set the tag of the
73	73	// palette device
r29404	r29405
99	99	void s3c2400_device::device_start()
100	100	{
101	101	s3c24xx_device_start();
102
103		address_space &space = m_cpu->memory().space( AS_PROGRAM);
	102
	103	address_space &space = m_cpu->memory().space( AS_PROGRAM);
104	104	space.install_readwrite_handler(0x14000000, 0x1400003b, read32_delegate(FUNC(s3c2400_device::s3c24xx_memcon_r), this), write32_delegate(FUNC(s3c2400_device::s3c24xx_memcon_w), this));
105	105	space.install_readwrite_handler(0x14200000, 0x1420005b, read32_delegate(FUNC(s3c2400_device::s3c24xx_usb_host_r), this), write32_delegate(FUNC(s3c2400_device::s3c24xx_usb_host_w), this));
106	106	space.install_readwrite_handler(0x14400000, 0x14400017, read32_delegate(FUNC(s3c2400_device::s3c24xx_irq_r), this), write32_delegate(FUNC(s3c2400_device::s3c24xx_irq_w), this));

trunk/src/emu/machine/upd7002.c
r29404	r29405
17	17	const device_type UPD7002 = &device_creator<upd7002_device>;
18	18
19	19	upd7002_device::upd7002_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
20		: device_t(mconfig, UPD7002, "uPD7002", tag, owner, clock, "upd7002", __FILE__)
	20	: device_t(mconfig, UPD7002, "uPD7002", tag, owner, clock, "upd7002", __FILE__)
21	21	{
22	22	}
23	23

trunk/src/emu/machine/s3c2400.h
r29404	r29405
16	16
17	17	#define MCFG_S3C2400_ADD(_tag, _clock, _config, _palette_tag) \
18	18	MCFG_DEVICE_ADD(_tag, S3C2400, _clock) \
19		MCFG_DEVICE_CONFIG(_config) \
	19	MCFG_DEVICE_CONFIG(_config) \
20	20	s3c2400_device::static_set_palette_tag(*device, "^" _palette_tag);
21	21
22	22	#define S3C2400_INTERFACE(name) \
r29404	r29405
369	369	#define S3C24XX_DMA_COUNT 4
370	370	#define S3C24XX_SPI_COUNT 1
371	371
372		class s3c2400_device : public device_t,
	372	class s3c2400_device : public device_t,
373	373	public s3c2400_interface
374	374	{
375	375	public:
r29404	r29405
536	536	void s3c24xx_spi_reset();
537	537	UINT32 s3c24xx_spi_r(UINT32 ch, UINT32 offset);
538	538	void s3c24xx_spi_w(UINT32 ch, UINT32 offset, UINT32 data, UINT32 mem_mask);
539		READ32_MEMBER( s3c24xx_spi_0_r );
	539	READ32_MEMBER( s3c24xx_spi_0_r );
540	540	WRITE32_MEMBER( s3c24xx_spi_0_w );
541	541	void s3c24xx_mmc_reset();
542	542	READ32_MEMBER( s3c24xx_mmc_r );
543	543	WRITE32_MEMBER( s3c24xx_mmc_w );
544	544	void s3c24xx_device_reset();
545	545	void s3c24xx_device_start();
546
547	546
	547
548	548	void s3c2400_uart_fifo_w(int uart, UINT8 data);
549	549
550	550	/*******************************************************************************
551		TYPE DEFINITIONS
	551	TYPE DEFINITIONS
552	552	*******************************************************************************/
553	553
554	554	struct s3c24xx_memcon_regs_t
r29404	r29405
901	901	devcb_resolved_write8 m_address_w;
902	902	devcb_resolved_read8 m_nand_data_r;
903	903	devcb_resolved_write8 m_nand_data_w;
904
	904
905	905	};
906	906
907	907	extern const device_type S3C2400;

trunk/src/emu/machine/upd7002.h
r29404	r29405
33	33	***************************************************************************/
34	34
35	35	class upd7002_device : public device_t,
36		public upd7002_interface
	36	public upd7002_interface
37	37	{
38	38	public:
39	39	upd7002_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
r29404	r29405
42	42	DECLARE_READ8_MEMBER ( eoc_r );
43	43	DECLARE_READ8_MEMBER ( read );
44	44	DECLARE_WRITE8_MEMBER ( write );
45
	45
46	46	protected:
47	47	// device-level overrides
48	48	virtual void device_config_complete();
49	49	virtual void device_start();
50	50	virtual void device_reset();
51	51	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
52
	52
53	53	private:
54	54	// internal state
55
	55
56	56	/* Status Register
57	57	D0 and D1 define the currently selected input channel
58	58	D2 flag output
r29404	r29405
83	83	the counter at the end of the first conversion will not match and not be processed
84	84	only then at the end of the second conversion will the conversion complete function run */
85	85	int m_conversion_counter;
86
	86
87	87	enum
88	88	{
89	89	TIMER_CONVERSION_COMPLETE

trunk/src/emu/machine/generic.c
r29404	r29405
433	433	const char tag = (const char )param;
434	434	return ioport(tag)->read();
435	435	}
436

trunk/src/emu/machine/mm74c922.h
r29404	r29405
106	106	void clock_scan_counters();
107	107	void detect_keypress();
108	108
109		devcb2_write_line m_write_da;
110		devcb2_read8 m_read_x1;
111		devcb2_read8 m_read_x2;
112		devcb2_read8 m_read_x3;
113		devcb2_read8 m_read_x4;
114		devcb2_read8 m_read_x5;
	109	devcb2_write_line m_write_da;
	110	devcb2_read8 m_read_x1;
	111	devcb2_read8 m_read_x2;
	112	devcb2_read8 m_read_x3;
	113	devcb2_read8 m_read_x4;
	114	devcb2_read8 m_read_x5;
115	115
116	116	double m_cap_osc;
117	117	double m_cap_debounce;

trunk/src/emu/machine/tc009xlvc.h
r29404	r29405
20	20	// static configuration
21	21	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
22	22	static void static_set_palette_tag(device_t &device, const char *tag);
23
	23
24	24	DECLARE_READ8_MEMBER( vregs_r );
25	25	DECLARE_WRITE8_MEMBER( vregs_w );
26	26

trunk/src/emu/machine/rtc65271.h
r29404	r29405
31	31	public:
32	32
33	33	template<class _Object> static devcb2_base &set_interrupt_callback(device_t &device, _Object object) { return downcast<rtc65271_device &>(device).m_interrupt_cb.set_callback(object); }
34
	34
35	35	DECLARE_READ8_MEMBER( rtc_r );
36	36	DECLARE_READ8_MEMBER( xram_r );
37	37	DECLARE_WRITE8_MEMBER( rtc_w );

trunk/src/emu/machine/rtc4543.c
r29404	r29405
29	29
30	30	rtc4543_device::rtc4543_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
31	31	: device_t(mconfig, RTC4543, "Epson R4543", tag, owner, clock, "rtc4543", __FILE__),
32		device_rtc_interface(mconfig, *this),
33		data_cb(*this)
	32	device_rtc_interface(mconfig, *this),
	33	data_cb(*this)
34	34	{
35	35	}
36	36

trunk/src/emu/machine/pci.c
r29404	r29405
287	287	m_devicenum = -1;
288	288	m_address = 0;
289	289	}
290

trunk/src/emu/machine/upd1990a.c
r29404	r29405
171	171	int max_shift = is_serial_mode() ? 6 : 5;
172	172	m_data_out = (m_time_counter[max_shift - 1] == 0);
173	173	m_write_data(get_data_out());
174
	174
175	175	for (int i = 0; i < max_shift; i++)
176	176	{
177	177	m_time_counter[i]++;
r29404	r29405
219	219	{
220	220	m_c = m_c_unlatched;
221	221	if (m_c == 7)
222		m_c = MODE_TEST;
	222	m_c = MODE_TEST;
223	223	}
224
	224
225	225	if (LOG) logerror("uPD1990A '%s' Command %x\n", tag(), m_c);
226
	226
227	227	// common functions
228	228	if (m_c == MODE_REGISTER_HOLD \|\| (m_c >= MODE_TP_64HZ && m_c < MODE_TEST))
229	229	{
r29404	r29405
234	234	m_testmode = false;
235	235	m_timer_test_mode->enable(0);
236	236	}
237
	237
238	238	switch (m_c)
239	239	{
240	240	case MODE_REGISTER_HOLD:
r29404	r29405
285	285	bcd_to_integer(m_time_counter[1]),
286	286	bcd_to_integer(m_time_counter[0])
287	287	);
288
	288
289	289	// reset stage 10-15 of clock divider
290	290	m_timer_clock->adjust(attotime::from_ticks(m_timer_clock->remaining().as_ticks(clock()) % (clock() / 512), clock()), 0, attotime::from_hz(clock() / 32768.0));
291
	291
292	292	// disable(low) time pulse in testmode
293	293	if (m_testmode)
294	294	{
r29404	r29405
336	336	// set timer pulse
337	337	const float div[4] = { 512.0, 128.0, 16.0, 8.0 };
338	338	m_timer_tp->adjust(attotime::zero, 0, attotime::from_hz((clock() / div[m_c - MODE_TP_64HZ]) * 2.0));
339
	339
340	340	break;
341	341	}
342	342
r29404	r29405
349	349	attotime one_second = attotime::from_hz(clock() / 32768.0);
350	350	const float mul[4] = { 1.0, 10.0, 30.0, 60.0 };
351	351	m_timer_tp->adjust(attotime::zero, 0, one_second * mul[m_c - MODE_TP_1S_INT] / 2.0);
352
	352
353	353	break;
354	354	}
355	355
r29404	r29405
374	374	m_timer_test_mode->adjust(attotime::zero, 0, attotime::from_hz(clock() / div));
375	375	break;
376	376	}
377
	377
378	378	default:
379	379	break;
380	380	}
r29404	r29405
399	399	if (!m_clk && state)
400	400	{
401	401	int in = m_data_in;
402
	402
403	403	if (is_serial_mode())
404	404	{
405	405	// always clock serial command register
r29404	r29405
407	407	m_shift_reg[6] >>= 1;
408	408	m_shift_reg[6] \|= (m_data_in << 3);
409	409	}
410
	410
411	411	if (m_c == MODE_SHIFT)
412	412	{
413	413	// clock shift register
r29404	r29405
420	420	else
421	421	m_shift_reg[i] \|= (m_shift_reg[i + 1] << 7 & 0x80);
422	422	}
423
	423
424	424	// data out LSB of shift register
425	425	m_data_out = m_shift_reg[0] & 1;
426	426	m_write_data(get_data_out());
r29404	r29405
449	449
450	450	int prev_oe = m_oe;
451	451	m_oe = state;
452
	452
453	453	if (m_oe != prev_oe && m_c != MODE_TEST)
454	454	m_write_data(get_data_out());
455	455	}

trunk/src/emu/machine/upd1990a.h
r29404	r29405
134	134	bool m_testmode; // testmode active
135	135
136	136	int m_variant;
137
	137
138	138	// timers
139	139	emu_timer *m_timer_clock;
140	140	emu_timer *m_timer_tp;

trunk/src/emu/machine/im6402.h
r29404	r29405
78	78	// ======================> im6402_device
79	79
80	80	class im6402_device : public device_t,
81		public device_serial_interface
	81	public device_serial_interface
82	82	{
83	83	public:
84	84	// construction/destruction

trunk/src/emu/machine/kb3600.c
r29404	r29405
160	160
161	161	if (!found)
162	162	{
163		ako = 1;
	163	ako = 1;
164	164
165	165	if (m_b != b)
166	166	{
r29404	r29405
181	181	}
182	182	}
183	183	}
184		else // key released, unmark it from the keys_down table
	184	else // key released, unmark it from the keys_down table
185	185	{
186	186	for (int k = 0; k < MAX_KEYS_DOWN; k++)
187	187	{

trunk/src/emu/machine/kb3600.h
r29404	r29405
65	65	// INTERFACE CONFIGURATION MACROS
66	66	//**************************************************************************
67	67
68		#define MCFG_AY3600_MATRIX_X0(_cb) \
	68	#define MCFG_AY3600_MATRIX_X0(_cb) \
69	69	devcb = &ay3600_device::set_x0_cb(*device, DEVCB2_##_cb);
70		#define MCFG_AY3600_MATRIX_X1(_cb) \
	70	#define MCFG_AY3600_MATRIX_X1(_cb) \
71	71	devcb = &ay3600_device::set_x1_cb(*device, DEVCB2_##_cb);
72		#define MCFG_AY3600_MATRIX_X2(_cb) \
	72	#define MCFG_AY3600_MATRIX_X2(_cb) \
73	73	devcb = &ay3600_device::set_x2_cb(*device, DEVCB2_##_cb);
74		#define MCFG_AY3600_MATRIX_X3(_cb) \
	74	#define MCFG_AY3600_MATRIX_X3(_cb) \
75	75	devcb = &ay3600_device::set_x3_cb(*device, DEVCB2_##_cb);
76		#define MCFG_AY3600_MATRIX_X4(_cb) \
	76	#define MCFG_AY3600_MATRIX_X4(_cb) \
77	77	devcb = &ay3600_device::set_x4_cb(*device, DEVCB2_##_cb);
78		#define MCFG_AY3600_MATRIX_X5(_cb) \
	78	#define MCFG_AY3600_MATRIX_X5(_cb) \
79	79	devcb = &ay3600_device::set_x5_cb(*device, DEVCB2_##_cb);
80		#define MCFG_AY3600_MATRIX_X6(_cb) \
	80	#define MCFG_AY3600_MATRIX_X6(_cb) \
81	81	devcb = &ay3600_device::set_x6_cb(*device, DEVCB2_##_cb);
82		#define MCFG_AY3600_MATRIX_X7(_cb) \
	82	#define MCFG_AY3600_MATRIX_X7(_cb) \
83	83	devcb = &ay3600_device::set_x7_cb(*device, DEVCB2_##_cb);
84		#define MCFG_AY3600_MATRIX_X8(_cb) \
	84	#define MCFG_AY3600_MATRIX_X8(_cb) \
85	85	devcb = &ay3600_device::set_x8_cb(*device, DEVCB2_##_cb);
86		#define MCFG_AY3600_SHIFT_CB(_cb) \
	86	#define MCFG_AY3600_SHIFT_CB(_cb) \
87	87	devcb = &ay3600_device::set_shift_cb(*device, DEVCB2_##_cb);
88		#define MCFG_AY3600_CONTROL_CB(_cb) \
	88	#define MCFG_AY3600_CONTROL_CB(_cb) \
89	89	devcb = &ay3600_device::set_control_cb(*device, DEVCB2_##_cb);
90		#define MCFG_AY3600_DATA_READY_CB(_cb) \
	90	#define MCFG_AY3600_DATA_READY_CB(_cb) \
91	91	devcb = &ay3600_device::set_data_ready_cb(*device, DEVCB2_##_cb);
92		#define MCFG_AY3600_AKO_CB(_cb) \
	92	#define MCFG_AY3600_AKO_CB(_cb) \
93	93	devcb = &ay3600_device::set_ako_cb(*device, DEVCB2_##_cb);
94	94
95	95	//**************************************************************************

trunk/src/emu/rendfont.h
r29404	r29405
52	52	public:
53	53	glyph()
54	54	: width(0),
55		xoffs(0), yoffs(0),
56		bmwidth(0), bmheight(0),
57		rawdata(NULL),
58		texture(NULL) { }
59
	55	xoffs(0), yoffs(0),
	56	bmwidth(0), bmheight(0),
	57	rawdata(NULL),
	58	texture(NULL) { }
	59
60	60	INT32 width; // width from this character to the next
61	61	INT32 xoffs, yoffs; // X and Y offset from baseline to top,left of bitmap
62	62	INT32 bmwidth, bmheight; // width and height of bitmap

trunk/src/emu/netlist/nl_parser.c
r29404	r29405
16	16
17	17	pstring ptokenizer::currentline_str()
18	18	{
19		char buf[300];
20		int bufp = 0;
21		const char *p = m_line_ptr;
22		while (p && p != 10)
23		buf[bufp++] = *p++;
24		buf[bufp] = 0;
25		return pstring(buf);
	19	char buf[300];
	20	int bufp = 0;
	21	const char *p = m_line_ptr;
	22	while (p && p != 10)
	23	buf[bufp++] = *p++;
	24	buf[bufp] = 0;
	25	return pstring(buf);
26	26	}
27	27
28	28
29	29	void ptokenizer::skipeol()
30	30	{
31		char c = getc();
32		while (c)
33		{
34		if (c == 10)
35		{
36		c = getc();
37		if (c != 13)
38		ungetc();
39		return;
40		}
41		c = getc();
42		}
	31	char c = getc();
	32	while (c)
	33	{
	34	if (c == 10)
	35	{
	36	c = getc();
	37	if (c != 13)
	38	ungetc();
	39	return;
	40	}
	41	c = getc();
	42	}
43	43	}
44	44
45	45
46	46	unsigned char ptokenizer::getc()
47	47	{
48		if (*m_px == 10)
49		{
50		m_line++;
51		m_line_ptr = m_px + 1;
52		}
53		if (*m_px)
54		return *(m_px++);
55		else
56		return *m_px;
	48	if (*m_px == 10)
	49	{
	50	m_line++;
	51	m_line_ptr = m_px + 1;
	52	}
	53	if (*m_px)
	54	return *(m_px++);
	55	else
	56	return *m_px;
57	57	}
58	58
59	59	void ptokenizer::ungetc()
60	60	{
61		m_px--;
	61	m_px--;
62	62	}
63	63
64	64	void ptokenizer::require_token(const token_id_t &token_num)
65	65	{
66		require_token(get_token(), token_num);
	66	require_token(get_token(), token_num);
67	67	}
68	68
69	69	void ptokenizer::require_token(const token_t tok, const token_id_t &token_num)
70	70	{
71		if (!tok.is(token_num))
72		{
73		error("Error: expected token <%s> got <%s>\n", m_tokens[token_num.id()].cstr(), tok.str().cstr());
74		}
	71	if (!tok.is(token_num))
	72	{
	73	error("Error: expected token <%s> got <%s>\n", m_tokens[token_num.id()].cstr(), tok.str().cstr());
	74	}
75	75	}
76	76
77	77	pstring ptokenizer::get_string()
78	78	{
79		token_t tok = get_token();
80		if (!tok.is_type(STRING))
81		{
82		error("Error: expected a string, got <%s>\n", tok.str().cstr());
83		}
84		return tok.str();
	79	token_t tok = get_token();
	80	if (!tok.is_type(STRING))
	81	{
	82	error("Error: expected a string, got <%s>\n", tok.str().cstr());
	83	}
	84	return tok.str();
85	85	}
86	86
87	87	pstring ptokenizer::get_identifier()
88	88	{
89		token_t tok = get_token();
90		if (!tok.is_type(IDENTIFIER))
91		{
92		error("Error: expected an identifier, got <%s>\n", tok.str().cstr());
93		}
94		return tok.str();
	89	token_t tok = get_token();
	90	if (!tok.is_type(IDENTIFIER))
	91	{
	92	error("Error: expected an identifier, got <%s>\n", tok.str().cstr());
	93	}
	94	return tok.str();
95	95	}
96	96
97	97	ptokenizer::token_t ptokenizer::get_token()
98	98	{
99		while (true)
100		{
101		token_t ret = get_token_internal();
102		if (ret.is_type(ENDOFFILE))
103		return ret;
	99	while (true)
	100	{
	101	token_t ret = get_token_internal();
	102	if (ret.is_type(ENDOFFILE))
	103	return ret;
104	104
105		if (ret.is(m_tok_comment_start))
106		{
107		do {
108		ret = get_token_internal();
109		} while (ret.is_not(m_tok_comment_end));
110		}
111		else if (ret.is(m_tok_line_comment))
112		{
113		skipeol();
114		}
115		else if (ret.str() == "#")
116		{
117		skipeol();
118		}
119		else
120		return ret;
121		}
	105	if (ret.is(m_tok_comment_start))
	106	{
	107	do {
	108	ret = get_token_internal();
	109	} while (ret.is_not(m_tok_comment_end));
	110	}
	111	else if (ret.is(m_tok_line_comment))
	112	{
	113	skipeol();
	114	}
	115	else if (ret.str() == "#")
	116	{
	117	skipeol();
	118	}
	119	else
	120	return ret;
	121	}
122	122	}
123	123
124	124	ptokenizer::token_t ptokenizer::get_token_internal()
125	125	{
126		/* skip ws */
127		char c = getc();
128		while (m_whitespace.find(c)>=0)
129		{
130		c = getc();
131		if (eof())
132		{
133		return token_t(ENDOFFILE);
134		}
135		}
136		if (m_identifier_chars.find(c)>=0)
137		{
138		/* read identifier till non identifier char */
139		pstring tokstr = "";
140		while (m_identifier_chars.find(c)>=0) {
141		tokstr += c;
142		c = getc();
143		}
144		ungetc();
145		token_id_t id = token_id_t(m_tokens.indexof(tokstr));
146		if (id.id() >= 0)
147		return token_t(id, tokstr);
148		else
149		{
150		return token_t(IDENTIFIER, tokstr);
151		}
152		}
153		else if (c == m_string)
154		{
155		pstring tokstr = "";
156		c = getc();
157		while (c != m_string)
158		{
159		tokstr += c;
160		c = getc();
161		}
162		return token_t(STRING, tokstr);
163		}
164		else
165		{
166		/* read identifier till first identifier char or ws */
167		pstring tokstr = "";
168		while ((m_identifier_chars.find(c)) < 0 && (m_whitespace.find(c) < 0)) {
169		tokstr += c;
170		/* expensive, check for single char tokens */
171		if (tokstr.len() == 1)
172		{
173		token_id_t id = token_id_t(m_tokens.indexof(tokstr));
174		if (id.id() >= 0)
175		return token_t(id, tokstr);
176		}
177		c = getc();
178		}
179		ungetc();
180		token_id_t id = token_id_t(m_tokens.indexof(tokstr));
181		if (id.id() >= 0)
182		return token_t(id, tokstr);
183		else
184		{
185		return token_t(UNKNOWN, tokstr);
186		}
187		}
	126	/* skip ws */
	127	char c = getc();
	128	while (m_whitespace.find(c)>=0)
	129	{
	130	c = getc();
	131	if (eof())
	132	{
	133	return token_t(ENDOFFILE);
	134	}
	135	}
	136	if (m_identifier_chars.find(c)>=0)
	137	{
	138	/* read identifier till non identifier char */
	139	pstring tokstr = "";
	140	while (m_identifier_chars.find(c)>=0) {
	141	tokstr += c;
	142	c = getc();
	143	}
	144	ungetc();
	145	token_id_t id = token_id_t(m_tokens.indexof(tokstr));
	146	if (id.id() >= 0)
	147	return token_t(id, tokstr);
	148	else
	149	{
	150	return token_t(IDENTIFIER, tokstr);
	151	}
	152	}
	153	else if (c == m_string)
	154	{
	155	pstring tokstr = "";
	156	c = getc();
	157	while (c != m_string)
	158	{
	159	tokstr += c;
	160	c = getc();
	161	}
	162	return token_t(STRING, tokstr);
	163	}
	164	else
	165	{
	166	/* read identifier till first identifier char or ws */
	167	pstring tokstr = "";
	168	while ((m_identifier_chars.find(c)) < 0 && (m_whitespace.find(c) < 0)) {
	169	tokstr += c;
	170	/* expensive, check for single char tokens */
	171	if (tokstr.len() == 1)
	172	{
	173	token_id_t id = token_id_t(m_tokens.indexof(tokstr));
	174	if (id.id() >= 0)
	175	return token_t(id, tokstr);
	176	}
	177	c = getc();
	178	}
	179	ungetc();
	180	token_id_t id = token_id_t(m_tokens.indexof(tokstr));
	181	if (id.id() >= 0)
	182	return token_t(id, tokstr);
	183	else
	184	{
	185	return token_t(UNKNOWN, tokstr);
	186	}
	187	}
188	188
189	189	}
190	190
191	191	ATTR_COLD void ptokenizer::error(const char *format, ...)
192	192	{
193		va_list ap;
194		va_start(ap, format);
	193	va_list ap;
	194	va_start(ap, format);
195	195
196		pstring errmsg1 =pstring(format).vprintf(ap);
197		va_end(ap);
	196	pstring errmsg1 =pstring(format).vprintf(ap);
	197	va_end(ap);
198	198
199		verror(errmsg1, currentline_no(), currentline_str());
	199	verror(errmsg1, currentline_no(), currentline_str());
200	200
201		//throw error;
	201	//throw error;
202	202	}
203	203
204	204	// ----------------------------------------------------------------------------------------
r29404	r29405
207	207
208	208	ATTR_COLD void netlist_parser::verror(pstring msg, int line_num, pstring line)
209	209	{
210		m_setup.netlist().error("line %d: error: %s\n\t\t%s\n", line_num,
211		msg.cstr(), line.cstr());
	210	m_setup.netlist().error("line %d: error: %s\n\t\t%s\n", line_num,
	211	msg.cstr(), line.cstr());
212	212
213		//throw error;
	213	//throw error;
214	214	}
215	215
216	216
217	217	bool netlist_parser::parse(const char *buf, const pstring nlname)
218	218	{
219		m_buf = buf;
	219	m_buf = buf;
220	220
221		reset(buf);
222		set_identifier_chars("abcdefghijklmnopqrstuvwvxyzABCDEFGHIJKLMNOPQRSTUVWXYZ01234567890_.-");
223		set_number_chars("01234567890eE-."); //FIXME: processing of numbers
224		char ws[5];
225		ws[0] = ' ';
226		ws[1] = 9;
227		ws[2] = 10;
228		ws[3] = 13;
229		ws[4] = 0;
230		set_whitespace(ws);
231		set_comment("/", "/", "//");
232		m_tok_param_left = register_token("(");
233		m_tok_param_right = register_token(")");
234		m_tok_comma = register_token(",");
	221	reset(buf);
	222	set_identifier_chars("abcdefghijklmnopqrstuvwvxyzABCDEFGHIJKLMNOPQRSTUVWXYZ01234567890_.-");
	223	set_number_chars("01234567890eE-."); //FIXME: processing of numbers
	224	char ws[5];
	225	ws[0] = ' ';
	226	ws[1] = 9;
	227	ws[2] = 10;
	228	ws[3] = 13;
	229	ws[4] = 0;
	230	set_whitespace(ws);
	231	set_comment("/", "/", "//");
	232	m_tok_param_left = register_token("(");
	233	m_tok_param_right = register_token(")");
	234	m_tok_comma = register_token(",");
235	235
236		m_tok_ALIAS = register_token("ALIAS");
237		m_tok_NET_C = register_token("NET_C");
238		m_tok_PARAM = register_token("PARAM");
239		m_tok_NET_MODEL = register_token("NET_MODEL");
240		m_tok_INCLUDE = register_token("INCLUDE");
241		m_tok_SUBMODEL = register_token("SUBMODEL");
242		m_tok_NETLIST_START = register_token("NETLIST_START");
243		m_tok_NETLIST_END = register_token("NETLIST_END");
	236	m_tok_ALIAS = register_token("ALIAS");
	237	m_tok_NET_C = register_token("NET_C");
	238	m_tok_PARAM = register_token("PARAM");
	239	m_tok_NET_MODEL = register_token("NET_MODEL");
	240	m_tok_INCLUDE = register_token("INCLUDE");
	241	m_tok_SUBMODEL = register_token("SUBMODEL");
	242	m_tok_NETLIST_START = register_token("NETLIST_START");
	243	m_tok_NETLIST_END = register_token("NETLIST_END");
244	244
245		bool in_nl = false;
	245	bool in_nl = false;
246	246
247		while (true)
	247	while (true)
248	248	{
249		token_t token = get_token();
	249	token_t token = get_token();
250	250
251		if (token.is_type(ENDOFFILE))
252		{
253		return false;
254		//error("EOF while searching for <%s>", nlname.cstr());
255		}
	251	if (token.is_type(ENDOFFILE))
	252	{
	253	return false;
	254	//error("EOF while searching for <%s>", nlname.cstr());
	255	}
256	256
257		if (token.is(m_tok_NETLIST_END))
258		{
259		require_token(m_tok_param_left);
260		if (!in_nl)
261		error("Unexpected NETLIST_END");
262		else
263		{
264		in_nl = false;
265		}
266		require_token(m_tok_param_right);
267		}
268		else if (token.is(m_tok_NETLIST_START))
269		{
270		if (in_nl)
271		error("Unexpected NETLIST_START");
272		require_token(m_tok_param_left);
273		token_t name = get_token();
274		require_token(m_tok_param_right);
275		if (name.str() == nlname \|\| nlname == "")
276		{
277		parse_netlist(name.str());
278		return true;
279		} else
280		in_nl = true;
281		}
	257	if (token.is(m_tok_NETLIST_END))
	258	{
	259	require_token(m_tok_param_left);
	260	if (!in_nl)
	261	error("Unexpected NETLIST_END");
	262	else
	263	{
	264	in_nl = false;
	265	}
	266	require_token(m_tok_param_right);
	267	}
	268	else if (token.is(m_tok_NETLIST_START))
	269	{
	270	if (in_nl)
	271	error("Unexpected NETLIST_START");
	272	require_token(m_tok_param_left);
	273	token_t name = get_token();
	274	require_token(m_tok_param_right);
	275	if (name.str() == nlname \|\| nlname == "")
	276	{
	277	parse_netlist(name.str());
	278	return true;
	279	} else
	280	in_nl = true;
	281	}
282	282	}
283	283	}
284	284
285	285	void netlist_parser::parse_netlist(const pstring &nlname)
286	286	{
	287	while (true)
	288	{
	289	token_t token = get_token();
287	290
288		while (true)
289		{
290		token_t token = get_token();
	291	if (token.is_type(ENDOFFILE))
	292	return;
291	293
292		if (token.is_type(ENDOFFILE))
293		return;
	294	require_token(m_tok_param_left);
	295	NL_VERBOSE_OUT(("Parser: Device: %s\n", token.str().cstr()));
294	296
295		require_token(m_tok_param_left);
296		NL_VERBOSE_OUT(("Parser: Device: %s\n", token.str().cstr()));
297
298		if (token.is(m_tok_ALIAS))
299		net_alias();
300		else if (token.is(m_tok_NET_C))
301		net_c();
302		else if (token.is(m_tok_PARAM))
303		netdev_param();
304		else if (token.is(m_tok_NET_MODEL))
305		net_model();
306		else if (token.is(m_tok_SUBMODEL))
307		net_submodel();
308		else if (token.is(m_tok_INCLUDE))
309		net_include();
310		else if (token.is(m_tok_NETLIST_END))
311		{
312		netdev_netlist_end();
313		return;
314		}
315		else
316		device(token.str());
317		}
	297	if (token.is(m_tok_ALIAS))
	298	net_alias();
	299	else if (token.is(m_tok_NET_C))
	300	net_c();
	301	else if (token.is(m_tok_PARAM))
	302	netdev_param();
	303	else if (token.is(m_tok_NET_MODEL))
	304	net_model();
	305	else if (token.is(m_tok_SUBMODEL))
	306	net_submodel();
	307	else if (token.is(m_tok_INCLUDE))
	308	net_include();
	309	else if (token.is(m_tok_NETLIST_END))
	310	{
	311	netdev_netlist_end();
	312	return;
	313	}
	314	else
	315	device(token.str());
	316	}
318	317	}
319	318
320	319
321	320	void netlist_parser::netdev_netlist_start()
322	321	{
323		// don't do much
324		token_t name = get_token();
325		require_token(m_tok_param_right);
	322	// don't do much
	323	token_t name = get_token();
	324	require_token(m_tok_param_right);
326	325	}
327	326
328	327	void netlist_parser::netdev_netlist_end()
329	328	{
330		// don't do much
331		require_token(m_tok_param_right);
	329	// don't do much
	330	require_token(m_tok_param_right);
332	331	}
333	332
334	333	void netlist_parser::net_model()
335	334	{
336		// don't do much
337		pstring model = get_string();
338		m_setup.register_model(model);
339		require_token(m_tok_param_right);
	335	// don't do much
	336	pstring model = get_string();
	337	m_setup.register_model(model);
	338	require_token(m_tok_param_right);
340	339	}
341	340
342	341	void netlist_parser::net_submodel()
343	342	{
344		// don't do much
345		pstring name = get_identifier();
346		require_token(m_tok_comma);
347		pstring model = get_identifier();
348		require_token(m_tok_param_right);
	343	// don't do much
	344	pstring name = get_identifier();
	345	require_token(m_tok_comma);
	346	pstring model = get_identifier();
	347	require_token(m_tok_param_right);
349	348
350		m_setup.namespace_push(name);
351		netlist_parser subparser(m_setup);
352		subparser.parse(m_buf, model);
353		m_setup.namespace_pop();
	349	m_setup.namespace_push(name);
	350	netlist_parser subparser(m_setup);
	351	subparser.parse(m_buf, model);
	352	m_setup.namespace_pop();
354	353	}
355	354
356	355	void netlist_parser::net_include()
357	356	{
358		// don't do much
359		pstring name = get_identifier();
360		require_token(m_tok_param_right);
	357	// don't do much
	358	pstring name = get_identifier();
	359	require_token(m_tok_param_right);
361	360
362		netlist_parser subparser(m_setup);
363		subparser.parse(m_buf, name);
	361	netlist_parser subparser(m_setup);
	362	subparser.parse(m_buf, name);
364	363	}
365	364
366	365	void netlist_parser::net_alias()
r29404	r29405
380	379	void netlist_parser::net_c()
381	380	{
382	381	pstring last = get_identifier();
383		require_token(m_tok_comma);
	382	require_token(m_tok_comma);
384	383
385	384	while (true)
386	385	{
387		pstring t1 = get_identifier();
388		m_setup.register_link(last , t1);
389		token_t n = get_token();
390		if (n.is(m_tok_param_right))
391		break;
392		if (!n.is(m_tok_comma))
393		error("expected a comma, found <%s>", n.str().cstr());
394		last = t1;
	386	pstring t1 = get_identifier();
	387	m_setup.register_link(last , t1);
	388	token_t n = get_token();
	389	if (n.is(m_tok_param_right))
	390	break;
	391	if (!n.is(m_tok_comma))
	392	error("expected a comma, found <%s>", n.str().cstr());
	393	last = t1;
395	394	}
396	395
397	396	NL_VERBOSE_OUT(("Parser: Connect: %s %s\n", t1.cstr(), t2.cstr()));
r29404	r29405
406	405	val = eval_param(get_token());
407	406	NL_VERBOSE_OUT(("Parser: Param: %s %f\n", param.cstr(), val));
408	407	m_setup.register_param(param, val);
409		require_token(m_tok_param_right);
	408	require_token(m_tok_param_right);
410	409	}
411	410
412	411	void netlist_parser::device(const pstring &dev_type)
r29404	r29405
427	426
428	427	NL_VERBOSE_OUT(("Parser: IC: %s\n", devname.cstr()));
429	428
430		cnt = 0;
431		while (cnt < def_params.count())
432		{
433		pstring paramfq = devname + "." + def_params[cnt];
	429	cnt = 0;
	430	while (cnt < def_params.count())
	431	{
	432	pstring paramfq = devname + "." + def_params[cnt];
434	433
435		NL_VERBOSE_OUT(("Defparam: %s\n", paramfq.cstr()));
436		require_token(m_tok_comma);
437		tok = get_token();
438		if (tok.is_type(STRING))
439		{
440		m_setup.register_param(paramfq, tok.str());
441		}
442		else
443		{
444		double val = eval_param(tok);
445		m_setup.register_param(paramfq, val);
446		}
447		cnt++;
448		}
	434	NL_VERBOSE_OUT(("Defparam: %s\n", paramfq.cstr()));
	435	require_token(m_tok_comma);
	436	tok = get_token();
	437	if (tok.is_type(STRING))
	438	{
	439	m_setup.register_param(paramfq, tok.str());
	440	}
	441	else
	442	{
	443	double val = eval_param(tok);
	444	m_setup.register_param(paramfq, val);
	445	}
	446	cnt++;
	447	}
449	448
450	449	tok = get_token();
451	450	cnt = 0;
r29404	r29405
456	455	m_setup.register_link(devname + "." + termlist[cnt], output_name);
457	456
458	457	cnt++;
459		tok = get_token();
	458	tok = get_token();
460	459	}
461		if (cnt != termlist.count())
462		fatalerror("netlist: input count mismatch for %s - expected %d found %d\n", devname.cstr(), termlist.count(), cnt);
463		require_token(tok, m_tok_param_right);
	460	if (cnt != termlist.count())
	461	fatalerror("netlist: input count mismatch for %s - expected %d found %d\n", devname.cstr(), termlist.count(), cnt);
	462	require_token(tok, m_tok_param_right);
464	463	}
465	464
466	465
r29404	r29405
483	482	for (i=1; i<6;i++)
484	483	if (tok.str().equals(macs[i]))
485	484	f = i;
486		if (f>0)
487		{
488		require_token(m_tok_param_left);
489		val = get_identifier();
490		}
491		else
492		val = tok.str();
	485	if (f>0)
	486	{
	487	require_token(m_tok_param_left);
	488	val = get_identifier();
	489	}
	490	else
	491	val = tok.str();
493	492
494		ret = val.as_double(&e);
	493	ret = val.as_double(&e);
495	494
496		if (e)
	495	if (e)
497	496	error("Error with parameter ...\n");
498	497	if (f>0)
499		require_token(m_tok_param_right);
	498	require_token(m_tok_param_right);
500	499	return ret * facs[f];
501	500	}
502

trunk/src/emu/netlist/nl_setup.c
r29404	r29405
19	19	TTL_INPUT(ttllow, 0)
20	20	NET_REGISTER_DEV(gnd, GND)
21	21
22		INCLUDE(diode_models);
23		INCLUDE(bjt_models);
	22	INCLUDE(diode_models);
	23	INCLUDE(bjt_models);
24	24
25	25	NETLIST_END()
26	26
r29404	r29405
58	58
59	59	ATTR_COLD pstring netlist_setup_t::build_fqn(const pstring &obj_name) const
60	60	{
61		if (m_stack.empty())
62		return netlist().name() + "." + obj_name;
63		else
64		return m_stack.peek() + "." + obj_name;
	61	if (m_stack.empty())
	62	return netlist().name() + "." + obj_name;
	63	else
	64	return m_stack.peek() + "." + obj_name;
65	65	}
66	66
67	67	void netlist_setup_t::namespace_push(const pstring &aname)
68	68	{
69		if (m_stack.empty())
70		m_stack.push(netlist().name() + "." + aname);
71		else
72		m_stack.push(m_stack.peek() + "." + aname);
	69	if (m_stack.empty())
	70	m_stack.push(netlist().name() + "." + aname);
	71	else
	72	m_stack.push(m_stack.peek() + "." + aname);
73	73	}
74	74
75	75	void netlist_setup_t::namespace_pop()
76	76	{
77		m_stack.pop();
	77	m_stack.pop();
78	78	}
79	79
80	80
81	81	netlist_device_t netlist_setup_t::register_dev(netlist_device_t dev, const pstring &name)
82	82	{
83		pstring fqn = build_fqn(name);
	83	pstring fqn = build_fqn(name);
84	84
85		dev->init(netlist(), fqn);
	85	dev->init(netlist(), fqn);
86	86
87	87	if (!(netlist().m_devices.add(fqn, dev, false)==TMERR_NONE))
88	88	netlist().error("Error adding %s to device list\n", name.cstr());
r29404	r29405
120	120	const link_t *p = m_links.first();
121	121	while (p != NULL)
122	122	{
123		const link_t *n = m_links.next(p);
	123	const link_t *n = m_links.next(p);
124	124	if (temp.equals(p->e1.substr(0,temp.len())) \|\| temp.equals(p->e2.substr(0,temp.len())))
125	125	m_links.remove(*p);
126	126	p = n;
r29404	r29405
135	135
136	136	void netlist_setup_t::register_alias_nofqn(const pstring &alias, const pstring &out)
137	137	{
138		if (!(m_alias.add(alias, out, false)==TMERR_NONE))
139		netlist().error("Error adding alias %s to alias list\n", alias.cstr());
	138	if (!(m_alias.add(alias, out, false)==TMERR_NONE))
	139	netlist().error("Error adding alias %s to alias list\n", alias.cstr());
140	140	}
141	141
142	142	void netlist_setup_t::register_alias(const pstring &alias, const pstring &out)
143	143	{
144		pstring alias_fqn = build_fqn(alias);
145		pstring out_fqn = build_fqn(out);
146		register_alias_nofqn(alias_fqn, out_fqn);
	144	pstring alias_fqn = build_fqn(alias);
	145	pstring out_fqn = build_fqn(out);
	146	register_alias_nofqn(alias_fqn, out_fqn);
147	147	}
148	148
149	149	pstring netlist_setup_t::objtype_as_astr(netlist_object_t &in) const
r29404	r29405
241	241	//int pl=m_models[i].find("(");
242	242	//int pr=m_models[i].find(")");
243	243	//dynamic_cast<netlist_param_model_t &>(param).initial(m_models[i].substr(pl+1,pr-pl-1));
244		dynamic_cast<netlist_param_model_t &>(param).initial(m_models[i]);
	244	dynamic_cast<netlist_param_model_t &>(param).initial(m_models[i]);
245	245	found = true;
246	246	break;
247	247	}
r29404	r29405
269	269
270	270	void netlist_setup_t::register_link_arr(const pstring &terms)
271	271	{
272		nl_util::pstring_list list = nl_util::split(terms,", ");
273		if (list.count() < 2)
274		netlist().error("You must pass at least 2 terminals to NET_C");
275		pstring last = list[0];
276		for (int i = 1; i < list.count(); i++)
277		{
278		register_link(last, list[i]);
279		last = list[i];
280		}
	272	nl_util::pstring_list list = nl_util::split(terms,", ");
	273	if (list.count() < 2)
	274	netlist().error("You must pass at least 2 terminals to NET_C");
	275	pstring last = list[0];
	276	for (int i = 1; i < list.count(); i++)
	277	{
	278	register_link(last, list[i]);
	279	last = list[i];
	280	}
281	281	}
282	282
283	283
r29404	r29405
298	298
299	299	void netlist_setup_t::register_param(const pstring &param, const pstring &value)
300	300	{
301		pstring fqn = build_fqn(param);
	301	pstring fqn = build_fqn(param);
302	302
303	303	if (!(m_params_temp.add(fqn, value, false)==TMERR_NONE))
304	304	netlist().error("Error adding parameter %s to parameter list\n", param.cstr());
r29404	r29405
368	368
369	369	netlist_param_t *netlist_setup_t::find_param(const pstring &param_in, bool required)
370	370	{
371		const pstring param_in_fqn = build_fqn(param_in);
	371	const pstring param_in_fqn = build_fqn(param_in);
372	372
373	373	const pstring &outname = resolve_alias(param_in_fqn);
374	374	netlist_param_t *ret;
r29404	r29405
383	383
384	384	nld_base_d_to_a_proxy *netlist_setup_t::get_d_a_proxy(netlist_output_t &out)
385	385	{
386		assert(out.isFamily(netlist_terminal_t::LOGIC));
	386	assert(out.isFamily(netlist_terminal_t::LOGIC));
387	387
388		//printf("proxy for %s\n", out.name().cstr());;
389		netlist_logic_output_t &out_cast = dynamic_cast<netlist_logic_output_t &>(out);
390		nld_base_d_to_a_proxy *proxy = out_cast.get_proxy();
	388	//printf("proxy for %s\n", out.name().cstr());;
	389	netlist_logic_output_t &out_cast = dynamic_cast<netlist_logic_output_t &>(out);
	390	nld_base_d_to_a_proxy *proxy = out_cast.get_proxy();
391	391
392		if (proxy == NULL)
393		{
394		// create a new one ...
395		proxy = new nld_d_to_a_proxy(out);
396		pstring x = pstring::sprintf("proxy_da_%d", m_proxy_cnt);
397		m_proxy_cnt++;
	392	if (proxy == NULL)
	393	{
	394	// create a new one ...
	395	proxy = new nld_d_to_a_proxy(out);
	396	pstring x = pstring::sprintf("proxy_da_%d", m_proxy_cnt);
	397	m_proxy_cnt++;
398	398
399		register_dev(proxy, x);
400		proxy->start_dev();
	399	register_dev(proxy, x);
	400	proxy->start_dev();
401	401
402	402	#if 1
403		/* connect all existing terminals to new net */
	403	/* connect all existing terminals to new net */
404	404
405		netlist_core_terminal_t *p = out.net().m_list.first();
406		while (p != NULL)
407		{
408		netlist_core_terminal_t *np = out.net().m_list.next(p);
409		p->clear_net(); // de-link from all nets ...
410		connect(proxy->out(), *p);
411		p = np;
412		}
413		out.net().m_list.clear(); // clear the list
414		out.net().m_num_cons = 0;
	405	netlist_core_terminal_t *p = out.net().m_list.first();
	406	while (p != NULL)
	407	{
	408	netlist_core_terminal_t *np = out.net().m_list.next(p);
	409	p->clear_net(); // de-link from all nets ...
	410	connect(proxy->out(), *p);
	411	p = np;
	412	}
	413	out.net().m_list.clear(); // clear the list
	414	out.net().m_num_cons = 0;
415	415	#endif
416		out.net().register_con(proxy->m_I);
417		out_cast.set_proxy(proxy);
	416	out.net().register_con(proxy->m_I);
	417	out_cast.set_proxy(proxy);
418	418
419		}
420		return proxy;
	419	}
	420	return proxy;
421	421	}
422	422
423	423	void netlist_setup_t::connect_input_output(netlist_input_t &in, netlist_output_t &out)
r29404	r29405
429	429	m_proxy_cnt++;
430	430
431	431	register_dev(proxy, x);
432		proxy->start_dev();
	432	proxy->start_dev();
433	433
434	434	proxy->m_Q.net().register_con(in);
435	435	out.net().register_con(proxy->m_I);
r29404	r29405
437	437	}
438	438	else if (out.isFamily(netlist_terminal_t::LOGIC) && in.isFamily(netlist_terminal_t::ANALOG))
439	439	{
440		nld_base_d_to_a_proxy *proxy = get_d_a_proxy(out);
	440	nld_base_d_to_a_proxy *proxy = get_d_a_proxy(out);
441	441
442		connect_terminals(proxy->out(), in);
443		//proxy->out().net().register_con(in);
	442	connect_terminals(proxy->out(), in);
	443	//proxy->out().net().register_con(in);
444	444	}
445	445	else
446	446	{
r29404	r29405
462	462	m_proxy_cnt++;
463	463
464	464	register_dev(proxy, x);
465		proxy->start_dev();
	465	proxy->start_dev();
466	466
467	467	connect_terminals(term, proxy->m_I);
468	468
r29404	r29405
536	536
537	537	static netlist_core_terminal_t &resolve_proxy(netlist_core_terminal_t &term)
538	538	{
539		if (term.isType(netlist_core_terminal_t::OUTPUT) && term.isFamily(netlist_core_terminal_t::LOGIC))
540		{
541		netlist_logic_output_t &out = dynamic_cast<netlist_logic_output_t &>(term);
542		if (out.has_proxy())
543		return out.get_proxy()->out();
544		}
545		return term;
	539	if (term.isType(netlist_core_terminal_t::OUTPUT) && term.isFamily(netlist_core_terminal_t::LOGIC))
	540	{
	541	netlist_logic_output_t &out = dynamic_cast<netlist_logic_output_t &>(term);
	542	if (out.has_proxy())
	543	return out.get_proxy()->out();
	544	}
	545	return term;
546	546	}
547	547
548	548	void netlist_setup_t::connect(netlist_core_terminal_t &t1_in, netlist_core_terminal_t &t2_in)
r29404	r29405
560	560	else if (t1.isType(netlist_core_terminal_t::INPUT) && t2.isType(netlist_core_terminal_t::OUTPUT))
561	561	{
562	562	if (t1.has_net() && t1.net().isRailNet())
563		netlist().error("Input %s already connected\n", t1.name().cstr());
	563	netlist().error("Input %s already connected\n", t1.name().cstr());
564	564	connect_input_output(dynamic_cast<netlist_input_t &>(t1), dynamic_cast<netlist_output_t &>(t2));
565	565	}
566	566	else if (t1.isType(netlist_core_terminal_t::OUTPUT) && t2.isType(netlist_core_terminal_t::TERMINAL))
r29404	r29405
589	589
590	590	void netlist_setup_t::resolve_inputs()
591	591	{
592		bool has_twoterms = false;
	592	bool has_twoterms = false;
593	593
594		netlist().log("Resolving inputs ...");
	594	netlist().log("Resolving inputs ...");
595	595
596	596	for (const link_t *entry = m_links.first(); entry != NULL; entry = m_links.next(entry))
597	597	{
r29404	r29405
612	612	//VERBOSE_OUT(("%s %d\n", out->netdev()->name(), *out->Q_ptr()));
613	613	}
614	614
615		netlist().log("deleting empty nets ...");
	615	netlist().log("deleting empty nets ...");
616	616
617	617	// delete empty nets ... and save m_list ...
618	618
619		netlist_net_t::list_t todelete;
	619	netlist_net_t::list_t todelete;
620	620
621	621	for (netlist_net_t const pn = netlist().m_nets.first(); pn != NULL; pn = netlist().m_nets.next(pn))
622	622	{
623	623	if ((*pn)->m_list.is_empty())
624	624	{
625		todelete.add(*pn);
	625	todelete.add(*pn);
626	626	}
627	627	else
628	628	{
629		for (netlist_core_terminal_t p = (pn)->m_list.first(); p != NULL; p = (*pn)->m_list.next(p))
630		(*pn)->m_registered.add(p);
	629	for (netlist_core_terminal_t p = (pn)->m_list.first(); p != NULL; p = (*pn)->m_list.next(p))
	630	(*pn)->m_registered.add(p);
631	631	}
632	632	}
633	633
634		for (int i=0; i < todelete.count(); i++)
635		{
636		netlist().log("Deleting net %s ...", todelete[i]->name().cstr());
637		netlist().m_nets.remove(todelete[i]);
638		if (!todelete[i]->isRailNet())
639		delete todelete[i];
640		}
	634	for (int i=0; i < todelete.count(); i++)
	635	{
	636	netlist().log("Deleting net %s ...", todelete[i]->name().cstr());
	637	netlist().m_nets.remove(todelete[i]);
	638	if (!todelete[i]->isRailNet())
	639	delete todelete[i];
	640	}
641	641
642		pstring errstr("");
	642	pstring errstr("");
643	643
644		netlist().log("looking for terminals not connected ...");
645		for (tagmap_terminal_t::entry_t *entry = m_terminals.first(); entry != NULL; entry = m_terminals.next(entry))
646		{
647		if (!entry->object()->has_net())
648		errstr += pstring::sprintf("Found terminal %s without a net\n",
649		entry->object()->name().cstr());
650		else if (entry->object()->net().num_cons() == 0)
651		netlist().warning("Found terminal %s without connections",
652		entry->object()->name().cstr());
653		}
654		if (errstr != "")
655		netlist().error("%s", errstr.cstr());
	644	netlist().log("looking for terminals not connected ...");
	645	for (tagmap_terminal_t::entry_t *entry = m_terminals.first(); entry != NULL; entry = m_terminals.next(entry))
	646	{
	647	if (!entry->object()->has_net())
	648	errstr += pstring::sprintf("Found terminal %s without a net\n",
	649	entry->object()->name().cstr());
	650	else if (entry->object()->net().num_cons() == 0)
	651	netlist().warning("Found terminal %s without connections",
	652	entry->object()->name().cstr());
	653	}
	654	if (errstr != "")
	655	netlist().error("%s", errstr.cstr());
656	656
657	657
658		netlist().log("looking for two terms connected to rail nets ...\n");
659		for (tagmap_devices_t::entry_t *entry = netlist().m_devices.first(); entry != NULL; entry = netlist().m_devices.next(entry))
660		{
661		NETLIB_NAME(twoterm) t = dynamic_cast<NETLIB_NAME(twoterm) >(entry->object());
662		if (t != NULL)
663		{
664		has_twoterms = true;
665		if (t->m_N.net().isRailNet() && t->m_P.net().isRailNet())
666		netlist().error("Found device %s connected only to railterminals %s/%s\n",
667		t->name().cstr(), t->m_N.net().name().cstr(), t->m_P.net().name().cstr());
668		}
669		}
	658	netlist().log("looking for two terms connected to rail nets ...\n");
	659	for (tagmap_devices_t::entry_t *entry = netlist().m_devices.first(); entry != NULL; entry = netlist().m_devices.next(entry))
	660	{
	661	NETLIB_NAME(twoterm) t = dynamic_cast<NETLIB_NAME(twoterm) >(entry->object());
	662	if (t != NULL)
	663	{
	664	has_twoterms = true;
	665	if (t->m_N.net().isRailNet() && t->m_P.net().isRailNet())
	666	netlist().error("Found device %s connected only to railterminals %s/%s\n",
	667	t->name().cstr(), t->m_N.net().name().cstr(), t->m_P.net().name().cstr());
	668	}
	669	}
670	670
671		netlist().log("initialize solver ...\n");
	671	netlist().log("initialize solver ...\n");
672	672
673	673	if (m_netlist.solver() == NULL)
674	674	{
675		if (has_twoterms)
676		netlist().error("No solver found for this net although analog elements are present\n");
	675	if (has_twoterms)
	676	netlist().error("No solver found for this net although analog elements are present\n");
677	677	}
678	678	else
679	679	m_netlist.solver()->post_start();

trunk/src/emu/netlist/nl_parser.h
r29404	r29405
12	12
13	13	class ptokenizer
14	14	{
15		NETLIST_PREVENT_COPYING(ptokenizer)
	15	NETLIST_PREVENT_COPYING(ptokenizer)
16	16	public:
17		virtual ~ptokenizer() {}
	17	virtual ~ptokenizer() {}
18	18
19		ptokenizer()
20		: m_line(1), m_line_ptr(NULL), m_px(NULL)
21		{}
	19	ptokenizer()
	20	: m_line(1), m_line_ptr(NULL), m_px(NULL)
	21	{}
22	22
23		enum token_type
24		{
25		IDENTIFIER,
26		NUMBER,
27		TOKEN,
28		STRING,
29		COMMENT,
30		UNKNOWN,
31		ENDOFFILE,
32		};
	23	enum token_type
	24	{
	25	IDENTIFIER,
	26	NUMBER,
	27	TOKEN,
	28	STRING,
	29	COMMENT,
	30	UNKNOWN,
	31	ENDOFFILE,
	32	};
33	33
34		struct token_id_t
35		{
36		public:
37		token_id_t() : m_id(-2) {}
38		token_id_t(const int id) : m_id(id) {}
39		const int id() const { return m_id; }
40		private:
41		int m_id;
42		};
	34	struct token_id_t
	35	{
	36	public:
	37	token_id_t() : m_id(-2) {}
	38	token_id_t(const int id) : m_id(id) {}
	39	const int id() const { return m_id; }
	40	private:
	41	int m_id;
	42	};
43	43
44		struct token_t
45		{
46		token_t() {};
47		token_t(token_type type)
48		{
49		m_type = type;
50		m_id = token_id_t(-1);
51		m_token ="";
52		}
53		token_t(token_type type, const pstring str)
54		{
55		m_type = type;
56		m_id = token_id_t(-1);
57		m_token = str;
58		}
59		token_t(const token_id_t id, const pstring str)
60		{
61		m_type = TOKEN;
62		m_id = id;
63		m_token = str;
64		}
	44	struct token_t
	45	{
	46	token_t() {};
	47	token_t(token_type type)
	48	{
	49	m_type = type;
	50	m_id = token_id_t(-1);
	51	m_token ="";
	52	}
	53	token_t(token_type type, const pstring str)
	54	{
	55	m_type = type;
	56	m_id = token_id_t(-1);
	57	m_token = str;
	58	}
	59	token_t(const token_id_t id, const pstring str)
	60	{
	61	m_type = TOKEN;
	62	m_id = id;
	63	m_token = str;
	64	}
65	65
66		bool is(const token_id_t &tok_id) const { return m_id.id() == tok_id.id(); }
67		bool is_not(const token_id_t &tok_id) const { return !is(tok_id); }
	66	bool is(const token_id_t &tok_id) const { return m_id.id() == tok_id.id(); }
	67	bool is_not(const token_id_t &tok_id) const { return !is(tok_id); }
68	68
69		bool is_type(const token_type type) const { return m_type == type; }
	69	bool is_type(const token_type type) const { return m_type == type; }
70	70
71		pstring str() const { return m_token; }
	71	pstring str() const { return m_token; }
72	72
73		private:
74		token_type m_type;
75		token_id_t m_id;
76		pstring m_token;
77		};
	73	private:
	74	token_type m_type;
	75	token_id_t m_id;
	76	pstring m_token;
	77	};
78	78
79	79
80		int currentline_no() { return m_line; }
81		pstring currentline_str();
	80	int currentline_no() { return m_line; }
	81	pstring currentline_str();
82	82
83		/* tokenizer stuff follows ... */
	83	/* tokenizer stuff follows ... */
84	84
85		token_t get_token();
86		pstring get_string();
87		pstring get_identifier();
	85	token_t get_token();
	86	pstring get_string();
	87	pstring get_identifier();
88	88
89		void require_token(const token_id_t &token_num);
90		void require_token(const token_t tok, const token_id_t &token_num);
	89	void require_token(const token_id_t &token_num);
	90	void require_token(const token_t tok, const token_id_t &token_num);
91	91
92		token_id_t register_token(pstring token)
93		{
94		m_tokens.add(token);
95		return token_id_t(m_tokens.count() - 1);
96		}
	92	token_id_t register_token(pstring token)
	93	{
	94	m_tokens.add(token);
	95	return token_id_t(m_tokens.count() - 1);
	96	}
97	97
98		void set_identifier_chars(pstring s) { m_identifier_chars = s; }
99		void set_number_chars(pstring s) { m_number_chars = s; }
100		void set_whitespace(pstring s) { m_whitespace = s; }
101		void set_comment(pstring start, pstring end, pstring line)
102		{
103		m_tok_comment_start = register_token(start);
104		m_tok_comment_end = register_token(end);
105		m_tok_line_comment = register_token(line);
106		m_string = '"';
107		}
	98	void set_identifier_chars(pstring s) { m_identifier_chars = s; }
	99	void set_number_chars(pstring s) { m_number_chars = s; }
	100	void set_whitespace(pstring s) { m_whitespace = s; }
	101	void set_comment(pstring start, pstring end, pstring line)
	102	{
	103	m_tok_comment_start = register_token(start);
	104	m_tok_comment_end = register_token(end);
	105	m_tok_line_comment = register_token(line);
	106	m_string = '"';
	107	}
108	108
109		token_t get_token_internal();
110		void error(const char *format, ...) ATTR_PRINTF(2,3);
	109	token_t get_token_internal();
	110	void error(const char *format, ...) ATTR_PRINTF(2,3);
111	111
112	112	protected:
113		void reset(const char *p) { m_px = p; m_line = 1; m_line_ptr = p; }
114		virtual void verror(pstring msg, int line_num, pstring line) = 0;
	113	void reset(const char *p) { m_px = p; m_line = 1; m_line_ptr = p; }
	114	virtual void verror(pstring msg, int line_num, pstring line) = 0;
115	115
116	116	private:
117		void skipeol();
	117	void skipeol();
118	118
119		unsigned char getc();
120		void ungetc();
121		bool eof() { return *m_px == 0; }
	119	unsigned char getc();
	120	void ungetc();
	121	bool eof() { return *m_px == 0; }
122	122
123		int m_line;
124		const char * m_line_ptr;
125		const char * m_px;
	123	int m_line;
	124	const char * m_line_ptr;
	125	const char * m_px;
126	126
127		/* tokenizer stuff follows ... */
	127	/* tokenizer stuff follows ... */
128	128
129		pstring m_identifier_chars;
130		pstring m_number_chars;
131		netlist_list_t<pstring> m_tokens;
132		pstring m_whitespace;
133		char m_string;
	129	pstring m_identifier_chars;
	130	pstring m_number_chars;
	131	netlist_list_t<pstring> m_tokens;
	132	pstring m_whitespace;
	133	char m_string;
134	134
135		token_id_t m_tok_comment_start;
136		token_id_t m_tok_comment_end;
137		token_id_t m_tok_line_comment;
	135	token_id_t m_tok_comment_start;
	136	token_id_t m_tok_comment_end;
	137	token_id_t m_tok_line_comment;
138	138	};
139	139
140	140	class netlist_parser : public ptokenizer
r29404	r29405
146	146
147	147	bool parse(const char *buf, const pstring nlname = "");
148	148
149		void parse_netlist(const pstring &nlname);
	149	void parse_netlist(const pstring &nlname);
150	150	void net_alias();
151	151	void netdev_param();
152	152	void net_c();
153	153	void device(const pstring &dev_type);
154		void netdev_netlist_start();
155		void netdev_netlist_end();
156		void net_model();
157		void net_submodel();
158		void net_include();
	154	void netdev_netlist_start();
	155	void netdev_netlist_end();
	156	void net_model();
	157	void net_submodel();
	158	void net_include();
159	159
160	160	protected:
161		virtual void verror(pstring msg, int line_num, pstring line);
	161	virtual void verror(pstring msg, int line_num, pstring line);
162	162	private:
163	163
164		double eval_param(const token_t tok);
	164	double eval_param(const token_t tok);
165	165
166		token_id_t m_tok_param_left;
167		token_id_t m_tok_param_right;
168		token_id_t m_tok_comma;
169		token_id_t m_tok_ALIAS;
170		token_id_t m_tok_NET_C;
171		token_id_t m_tok_PARAM;
172		token_id_t m_tok_NET_MODEL;
173		token_id_t m_tok_NETLIST_START;
174		token_id_t m_tok_NETLIST_END;
175		token_id_t m_tok_SUBMODEL;
176		token_id_t m_tok_INCLUDE;
	166	token_id_t m_tok_param_left;
	167	token_id_t m_tok_param_right;
	168	token_id_t m_tok_comma;
	169	token_id_t m_tok_ALIAS;
	170	token_id_t m_tok_NET_C;
	171	token_id_t m_tok_PARAM;
	172	token_id_t m_tok_NET_MODEL;
	173	token_id_t m_tok_NETLIST_START;
	174	token_id_t m_tok_NETLIST_END;
	175	token_id_t m_tok_SUBMODEL;
	176	token_id_t m_tok_INCLUDE;
177	177
178		netlist_setup_t &m_setup;
	178	netlist_setup_t &m_setup;
179	179
180		const char *m_buf;
	180	const char *m_buf;
181	181	};
182	182
183	183	class netlist_source_t
184	184	{
185	185	public:
186		typedef netlist_list_t<netlist_source_t> list_t;
	186	typedef netlist_list_t<netlist_source_t> list_t;
187	187
188		enum source_e
189		{
190		EMPTY,
191		STRING,
192		PROC,
193		MEMORY
194		};
	188	enum source_e
	189	{
	190	EMPTY,
	191	STRING,
	192	PROC,
	193	MEMORY
	194	};
195	195
196		netlist_source_t()
197		: m_type(EMPTY),
198		m_setup_func(NULL),
199		m_setup_func_name(""),
200		m_mem(NULL)
201		{
202		}
	196	netlist_source_t()
	197	: m_type(EMPTY),
	198	m_setup_func(NULL),
	199	m_setup_func_name(""),
	200	m_mem(NULL)
	201	{
	202	}
203	203
204		netlist_source_t(pstring name, void (*setup_func)(netlist_setup_t &))
205		: m_type(PROC),
206		m_setup_func(setup_func),
207		m_setup_func_name(name),
208		m_mem(NULL)
209		{
210		}
	204	netlist_source_t(pstring name, void (*setup_func)(netlist_setup_t &))
	205	: m_type(PROC),
	206	m_setup_func(setup_func),
	207	m_setup_func_name(name),
	208	m_mem(NULL)
	209	{
	210	}
211	211
212		netlist_source_t(const char *mem)
213		: m_type(MEMORY),
214		m_setup_func(NULL),
215		m_setup_func_name(""),
216		m_mem(mem)
217		{
218		}
	212	netlist_source_t(const char *mem)
	213	: m_type(MEMORY),
	214	m_setup_func(NULL),
	215	m_setup_func_name(""),
	216	m_mem(mem)
	217	{
	218	}
219	219
220		~netlist_source_t() { }
	220	~netlist_source_t() { }
221	221
222		bool parse(netlist_setup_t &setup, const pstring name)
223		{
224		switch (m_type)
225		{
226		case PROC:
227		if (name == m_setup_func_name)
228		{
229		m_setup_func(setup);
230		return true;
231		}
232		break;
233		case MEMORY:
234		{
235		netlist_parser p(setup);
236		return p.parse(m_mem, name);
237		}
238		break;
239		case STRING:
240		case EMPTY:
241		break;
242		}
243		return false;
244		}
	222	bool parse(netlist_setup_t &setup, const pstring name)
	223	{
	224	switch (m_type)
	225	{
	226	case PROC:
	227	if (name == m_setup_func_name)
	228	{
	229	m_setup_func(setup);
	230	return true;
	231	}
	232	break;
	233	case MEMORY:
	234	{
	235	netlist_parser p(setup);
	236	return p.parse(m_mem, name);
	237	}
	238	break;
	239	case STRING:
	240	case EMPTY:
	241	break;
	242	}
	243	return false;
	244	}
245	245	private:
246		source_e m_type;
	246	source_e m_type;
247	247
248		void (*m_setup_func)(netlist_setup_t &);
249		pstring m_setup_func_name;
250		const char *m_mem;
	248	void (*m_setup_func)(netlist_setup_t &);
	249	pstring m_setup_func_name;
	250	const char *m_mem;
251	251
252	252	};
253	253
254	254	class netlist_sources_t
255	255	{
256	256	public:
257		void add(netlist_source_t src)
258		{
259		m_list.add(src);
260		}
	257	void add(netlist_source_t src)
	258	{
	259	m_list.add(src);
	260	}
261	261
262		void parse(netlist_setup_t &setup, const pstring name)
263		{
264		for (int i=0; i < m_list.count(); i++)
265		{
266		if (m_list[i].parse(setup, name))
267		return;
268		}
269		setup.netlist().error("unable to find %s in source collection", name.cstr());
270		}
	262	void parse(netlist_setup_t &setup, const pstring name)
	263	{
	264	for (int i=0; i < m_list.count(); i++)
	265	{
	266	if (m_list[i].parse(setup, name))
	267	return;
	268	}
	269	setup.netlist().error("unable to find %s in source collection", name.cstr());
	270	}
271	271
272	272	private:
273		netlist_source_t::list_t m_list;
	273	netlist_source_t::list_t m_list;
274	274	};
275	275
276	276	#endif /* NL_PARSER_H_ */

trunk/src/emu/netlist/pstring.h
r29404	r29405
97	97	inline const char *cstr() const { return m_ptr->str(); }
98	98
99	99	// concatenation operators
100		pstring& operator+=(const char c) { char buf[2] = { c, 0 }; pcat(buf); return *this; }
	100	pstring& operator+=(const char c) { char buf[2] = { c, 0 }; pcat(buf); return *this; }
101	101	pstring& operator+=(const pstring &string) { pcat(string.cstr()); return *this; }
102	102	friend pstring operator+(const pstring &lhs, const pstring &rhs) { return pstring(lhs) += rhs; }
103	103	friend pstring operator+(const pstring &lhs, const char *rhs) { return pstring(lhs) += rhs; }
r29404	r29405
133	133	return (result != NULL) ? (result - cstr()) : -1;
134	134	}
135	135
136		inline int find(const char search, int start = 0) const
137		{
138		int alen = len();
139		const char *result = strchr(cstr() + MIN(start, alen), search);
140		return (result != NULL) ? (result - cstr()) : -1;
141		}
	136	inline int find(const char search, int start = 0) const
	137	{
	138	int alen = len();
	139	const char *result = strchr(cstr() + MIN(start, alen), search);
	140	return (result != NULL) ? (result - cstr()) : -1;
	141	}
142	142
143	143	// various
144	144
r29404	r29405
174	174
175	175	struct str_t
176	176	{
177		str_t() : m_ref_count(1), m_len(0) { m_str[0] = 0; }
	177	str_t() : m_ref_count(1), m_len(0) { m_str[0] = 0; }
178	178	str_t(int alen) : m_ref_count(1), m_len(alen) { m_str[0] = 0; }
179	179
180	180	char *str() { return &m_str[0]; }

trunk/src/emu/netlist/nl_lists.h
r29404	r29405
22	22	{
23	23	public:
24	24
25		ATTR_COLD netlist_list_t(int numElements = _NumElem)
26		{
27		m_num_elements = numElements;
28		m_list = new _ListClass[m_num_elements];
29		m_count = 0;
30		}
	25	ATTR_COLD netlist_list_t(int numElements = _NumElem)
	26	{
	27	m_num_elements = numElements;
	28	m_list = new _ListClass[m_num_elements];
	29	m_count = 0;
	30	}
31	31
32		ATTR_COLD netlist_list_t(const netlist_list_t &rhs)
33		{
34		m_num_elements = rhs.capacity();
35		m_list = new _ListClass[m_num_elements];
36		m_count = 0;
37		for (int i=0; i<rhs.count(); i++)
38		{
39		this->add(rhs[i]);
40		}
41		}
	32	ATTR_COLD netlist_list_t(const netlist_list_t &rhs)
	33	{
	34	m_num_elements = rhs.capacity();
	35	m_list = new _ListClass[m_num_elements];
	36	m_count = 0;
	37	for (int i=0; i<rhs.count(); i++)
	38	{
	39	this->add(rhs[i]);
	40	}
	41	}
42	42
43		ATTR_COLD netlist_list_t &operator=(const netlist_list_t &rhs)
44		{
45		this->reset();
46		for (int i=0; i<rhs.count(); i++)
47		{
48		this->add(rhs[i]);
49		}
50		return *this;
51		}
	43	ATTR_COLD netlist_list_t &operator=(const netlist_list_t &rhs)
	44	{
	45	this->reset();
	46	for (int i=0; i<rhs.count(); i++)
	47	{
	48	this->add(rhs[i]);
	49	}
	50	return *this;
	51	}
52	52
53	53
54		ATTR_COLD ~netlist_list_t()
55		{
56		delete[] m_list;
57		}
	54	ATTR_COLD ~netlist_list_t()
	55	{
	56	delete[] m_list;
	57	}
58	58
59		ATTR_HOT inline void add(const _ListClass &elem)
60		{
61		if (m_count >= m_num_elements)
62		resize(m_num_elements * 2);
	59	ATTR_HOT inline void add(const _ListClass &elem)
	60	{
	61	if (m_count >= m_num_elements)
	62	resize(m_num_elements * 2);
63	63
64		m_list[m_count++] = elem;
65		}
	64	m_list[m_count++] = elem;
	65	}
66	66
67		ATTR_HOT inline void resize(const int new_size)
68		{
69		int cnt = count();
70		_ListClass *m_new = new _ListClass[new_size];
71		_ListClass *pd = m_new;
	67	ATTR_HOT inline void resize(const int new_size)
	68	{
	69	int cnt = count();
	70	_ListClass *m_new = new _ListClass[new_size];
	71	_ListClass *pd = m_new;
72	72
73		for (_ListClass *ps = m_list; ps < m_list + cnt; ps++, pd++)
74		pd = ps;
75		delete[] m_list;
76		m_list = m_new;
77		m_count = cnt;
78		m_num_elements = new_size;
79		}
	73	for (_ListClass *ps = m_list; ps < m_list + cnt; ps++, pd++)
	74	pd = ps;
	75	delete[] m_list;
	76	m_list = m_new;
	77	m_count = cnt;
	78	m_num_elements = new_size;
	79	}
80	80
81		ATTR_HOT inline void remove(const _ListClass &elem)
82		{
83		for (int i = 0; i < m_count; i++)
84		{
85		if (m_list[i] == elem)
86		{
87		m_count --;
88		while (i < m_count)
89		{
90		m_list[i] = m_list[i+1];
91		i++;
92		}
93		return;
94		}
95		}
96		}
	81	ATTR_HOT inline void remove(const _ListClass &elem)
	82	{
	83	for (int i = 0; i < m_count; i++)
	84	{
	85	if (m_list[i] == elem)
	86	{
	87	m_count --;
	88	while (i < m_count)
	89	{
	90	m_list[i] = m_list[i+1];
	91	i++;
	92	}
	93	return;
	94	}
	95	}
	96	}
97	97
98		ATTR_HOT inline void remove_at(const int pos)
99		{
100		assert((pos>=0) && (pos<m_count));
101		m_count--;
102		for (int i = pos; i < m_count; i++)
103		{
104		m_list[i] = m_list[i+1];
105		}
106		}
	98	ATTR_HOT inline void remove_at(const int pos)
	99	{
	100	assert((pos>=0) && (pos<m_count));
	101	m_count--;
	102	for (int i = pos; i < m_count; i++)
	103	{
	104	m_list[i] = m_list[i+1];
	105	}
	106	}
107	107
108		ATTR_HOT inline bool contains(const _ListClass &elem) const
109		{
110		for (_ListClass *i = m_list; i < m_list + m_count; i++)
111		{
112		if (*i == elem)
113		return true;
114		}
115		return false;
116		}
	108	ATTR_HOT inline bool contains(const _ListClass &elem) const
	109	{
	110	for (_ListClass *i = m_list; i < m_list + m_count; i++)
	111	{
	112	if (*i == elem)
	113	return true;
	114	}
	115	return false;
	116	}
117	117
118		ATTR_HOT inline int indexof(const _ListClass &elem) const
119		{
120		for (int i = 0; i < m_count; i++)
121		{
122		if (m_list[i] == elem)
123		return i;
124		}
125		return -1;
126		}
	118	ATTR_HOT inline int indexof(const _ListClass &elem) const
	119	{
	120	for (int i = 0; i < m_count; i++)
	121	{
	122	if (m_list[i] == elem)
	123	return i;
	124	}
	125	return -1;
	126	}
127	127
128		ATTR_HOT inline const _ListClass *first() const { return ((m_count > 0) ? &m_list[0] : NULL ); }
129		ATTR_HOT inline const _ListClass next(const _ListClass lc) const { return ((lc < last()) ? lc + 1 : NULL ); }
130		ATTR_HOT inline const _ListClass *last() const { return &m_list[m_count -1]; }
131		ATTR_HOT inline int count() const { return m_count; }
132		ATTR_HOT inline bool empty() const { return (m_count == 0); }
133		ATTR_HOT inline void clear() { m_count = 0; }
134		ATTR_HOT inline int capacity() const { return m_num_elements; }
	128	ATTR_HOT inline const _ListClass *first() const { return ((m_count > 0) ? &m_list[0] : NULL ); }
	129	ATTR_HOT inline const _ListClass next(const _ListClass lc) const { return ((lc < last()) ? lc + 1 : NULL ); }
	130	ATTR_HOT inline const _ListClass *last() const { return &m_list[m_count -1]; }
	131	ATTR_HOT inline int count() const { return m_count; }
	132	ATTR_HOT inline bool empty() const { return (m_count == 0); }
	133	ATTR_HOT inline void clear() { m_count = 0; }
	134	ATTR_HOT inline int capacity() const { return m_num_elements; }
135	135
136		ATTR_COLD void clear_and_free()
137		{
138		for (_ListClass *i = m_list; i < m_list + m_count; i++)
139		{
140		delete *i;
141		}
142		clear();
143		}
	136	ATTR_COLD void clear_and_free()
	137	{
	138	for (_ListClass *i = m_list; i < m_list + m_count; i++)
	139	{
	140	delete *i;
	141	}
	142	clear();
	143	}
144	144
145		ATTR_HOT inline _ListClass& operator[](const int & index) { return m_list[index]; }
146		ATTR_HOT inline const _ListClass& operator[](const int & index) const { return m_list[index]; }
	145	ATTR_HOT inline _ListClass& operator[](const int & index) { return m_list[index]; }
	146	ATTR_HOT inline const _ListClass& operator[](const int & index) const { return m_list[index]; }
147	147
148	148	private:
149		int m_count;
150		_ListClass * m_list;
151		int m_num_elements;
	149	int m_count;
	150	_ListClass * m_list;
	151	int m_num_elements;
152	152	};
153	153
154	154	// ----------------------------------------------------------------------------------------
r29404	r29405
158	158	template <class _Element, class _Time, int _Size>
159	159	class netlist_timed_queue
160	160	{
161		NETLIST_PREVENT_COPYING(netlist_timed_queue)
	161	NETLIST_PREVENT_COPYING(netlist_timed_queue)
162	162	public:
163	163
164		class entry_t
165		{
166		public:
167		ATTR_HOT inline entry_t()
168		: m_exec_time(), m_object() {}
169		ATTR_HOT inline entry_t(const _Time atime, const _Element elem) : m_exec_time(atime), m_object(elem) {}
170		ATTR_HOT inline const _Time exec_time() const { return m_exec_time; }
171		ATTR_HOT inline const _Element object() const { return m_object; }
	164	class entry_t
	165	{
	166	public:
	167	ATTR_HOT inline entry_t()
	168	: m_exec_time(), m_object() {}
	169	ATTR_HOT inline entry_t(const _Time atime, const _Element elem) : m_exec_time(atime), m_object(elem) {}
	170	ATTR_HOT inline const _Time exec_time() const { return m_exec_time; }
	171	ATTR_HOT inline const _Element object() const { return m_object; }
172	172
173		private:
174		_Time m_exec_time;
175		_Element m_object;
176		};
	173	private:
	174	_Time m_exec_time;
	175	_Element m_object;
	176	};
177	177
178		netlist_timed_queue()
179		{
180		//m_list = global_alloc_array(entry_t, SIZE);
181		clear();
182		}
	178	netlist_timed_queue()
	179	{
	180	//m_list = global_alloc_array(entry_t, SIZE);
	181	clear();
	182	}
183	183
184		ATTR_HOT inline int capacity() const { return _Size; }
185		ATTR_HOT inline bool is_empty() const { return (m_end == &m_list[0]); }
186		ATTR_HOT inline bool is_not_empty() const { return (m_end > &m_list[0]); }
	184	ATTR_HOT inline int capacity() const { return _Size; }
	185	ATTR_HOT inline bool is_empty() const { return (m_end == &m_list[0]); }
	186	ATTR_HOT inline bool is_not_empty() const { return (m_end > &m_list[0]); }
187	187
188		ATTR_HOT ATTR_ALIGN void push(const entry_t &e)
189		{
190		entry_t * i = m_end++;
191		const _Time e_time = e.exec_time();
192		while ((i > &m_list[0]) && (e_time > (i - 1)->exec_time()) )
193		{
194		(i) = (i-1);
195		i--;
196		inc_stat(m_prof_sortmove);
197		}
198		*i = e;
199		inc_stat(m_prof_sort);
200		assert(m_end - m_list < _Size);
201		}
	188	ATTR_HOT ATTR_ALIGN void push(const entry_t &e)
	189	{
	190	entry_t * i = m_end++;
	191	const _Time e_time = e.exec_time();
	192	while ((i > &m_list[0]) && (e_time > (i - 1)->exec_time()) )
	193	{
	194	(i) = (i-1);
	195	i--;
	196	inc_stat(m_prof_sortmove);
	197	}
	198	*i = e;
	199	inc_stat(m_prof_sort);
	200	assert(m_end - m_list < _Size);
	201	}
202	202
203		ATTR_HOT inline const entry_t *pop()
204		{
205		return --m_end;
206		}
	203	ATTR_HOT inline const entry_t *pop()
	204	{
	205	return --m_end;
	206	}
207	207
208		ATTR_HOT inline const entry_t *peek() const
209		{
210		return (m_end-1);
211		}
	208	ATTR_HOT inline const entry_t *peek() const
	209	{
	210	return (m_end-1);
	211	}
212	212
213		ATTR_COLD void clear()
214		{
215		m_end = &m_list[0];
216		}
	213	ATTR_COLD void clear()
	214	{
	215	m_end = &m_list[0];
	216	}
217	217
218		// save state support & mame disasm
	218	// save state support & mame disasm
219	219
220		ATTR_COLD inline const entry_t *listptr() const { return &m_list[0]; }
221		ATTR_HOT inline int count() const { return m_end - m_list; }
222		ATTR_HOT inline const entry_t & operator[](const int & index) const { return m_list[index]; }
	220	ATTR_COLD inline const entry_t *listptr() const { return &m_list[0]; }
	221	ATTR_HOT inline int count() const { return m_end - m_list; }
	222	ATTR_HOT inline const entry_t & operator[](const int & index) const { return m_list[index]; }
223	223
224	224	#if (NL_KEEP_STATISTICS)
225		// profiling
226		INT32 m_prof_start;
227		INT32 m_prof_end;
228		INT32 m_prof_sortmove;
229		INT32 m_prof_sort;
	225	// profiling
	226	INT32 m_prof_start;
	227	INT32 m_prof_end;
	228	INT32 m_prof_sortmove;
	229	INT32 m_prof_sort;
230	230	#endif
231	231
232	232	private:
233	233
234		entry_t * m_end;
235		entry_t m_list[_Size];
	234	entry_t * m_end;
	235	entry_t m_list[_Size];
236	236
237	237	};
238	238
r29404	r29405
246	246	{
247	247	public:
248	248
249		ATTR_COLD netlist_stack_t(int numElements = _NumElem)
250		: m_list(numElements)
251		{
252		}
	249	ATTR_COLD netlist_stack_t(int numElements = _NumElem)
	250	: m_list(numElements)
	251	{
	252	}
253	253
254		ATTR_COLD netlist_stack_t(const netlist_stack_t &rhs)
255		: m_list(rhs.m_list)
256		{
257		}
	254	ATTR_COLD netlist_stack_t(const netlist_stack_t &rhs)
	255	: m_list(rhs.m_list)
	256	{
	257	}
258	258
259		ATTR_COLD netlist_stack_t &operator=(const netlist_stack_t &rhs)
260		{
261		m_list = rhs.m_list;
262		return *this;
263		}
	259	ATTR_COLD netlist_stack_t &operator=(const netlist_stack_t &rhs)
	260	{
	261	m_list = rhs.m_list;
	262	return *this;
	263	}
264	264
265	265
266		ATTR_COLD ~netlist_stack_t()
267		{
268		}
	266	ATTR_COLD ~netlist_stack_t()
	267	{
	268	}
269	269
270		ATTR_HOT inline void push(const _StackClass &elem)
271		{
272		m_list.add(elem);
273		}
	270	ATTR_HOT inline void push(const _StackClass &elem)
	271	{
	272	m_list.add(elem);
	273	}
274	274
275		ATTR_HOT inline _StackClass peek() const
276		{
277		return m_list[m_list.count() - 1];
278		}
	275	ATTR_HOT inline _StackClass peek() const
	276	{
	277	return m_list[m_list.count() - 1];
	278	}
279	279
280		ATTR_HOT inline _StackClass pop()
281		{
282		_StackClass ret = peek();
283		m_list.remove_at(m_list.count() - 1);
284		return ret;
285		}
	280	ATTR_HOT inline _StackClass pop()
	281	{
	282	_StackClass ret = peek();
	283	m_list.remove_at(m_list.count() - 1);
	284	return ret;
	285	}
286	286
287		ATTR_HOT inline int count() const { return m_list.count(); }
288		ATTR_HOT inline bool empty() const { return (m_list.count() == 0); }
289		ATTR_HOT inline void reset() { m_list.reset(); }
290		ATTR_HOT inline int capacity() const { return m_list.capacity(); }
	287	ATTR_HOT inline int count() const { return m_list.count(); }
	288	ATTR_HOT inline bool empty() const { return (m_list.count() == 0); }
	289	ATTR_HOT inline void reset() { m_list.reset(); }
	290	ATTR_HOT inline int capacity() const { return m_list.capacity(); }
291	291
292	292	private:
293		netlist_list_t<_StackClass, _NumElem> m_list;
	293	netlist_list_t<_StackClass, _NumElem> m_list;
294	294	};
295	295
296	296	template <class _ListClass>
297	297	struct plinked_list_element
298	298	{
299		plinked_list_element() : m_next(NULL) {}
300		_ListClass * m_next;
	299	plinked_list_element() : m_next(NULL) {}
	300	_ListClass * m_next;
301	301
302	302	};
303	303
r29404	r29405
306	306	{
307	307	public:
308	308
309		plinked_list() : m_head(NULL) {}
	309	plinked_list() : m_head(NULL) {}
310	310
311		ATTR_HOT inline void insert(const _ListClass &before, _ListClass &elem)
312		{
313		if (m_head == &before)
314		{
315		elem.m_next = m_head;
316		m_head = elem;
317		}
318		else
319		{
320		_ListClass *p = m_head;
321		while (p != NULL)
322		{
323		if (p->m_next == &before)
324		{
325		elem->m_next = &before;
326		p->m_next = &elem;
327		return;
328		}
329		p = p->m_next;
330		}
331		assert_always(false, "element not found");
332		}
333		}
	311	ATTR_HOT inline void insert(const _ListClass &before, _ListClass &elem)
	312	{
	313	if (m_head == &before)
	314	{
	315	elem.m_next = m_head;
	316	m_head = elem;
	317	}
	318	else
	319	{
	320	_ListClass *p = m_head;
	321	while (p != NULL)
	322	{
	323	if (p->m_next == &before)
	324	{
	325	elem->m_next = &before;
	326	p->m_next = &elem;
	327	return;
	328	}
	329	p = p->m_next;
	330	}
	331	assert_always(false, "element not found");
	332	}
	333	}
334	334
335		ATTR_HOT inline void insert(_ListClass &elem)
336		{
337		elem.m_next = m_head;
338		m_head = &elem;
339		}
	335	ATTR_HOT inline void insert(_ListClass &elem)
	336	{
	337	elem.m_next = m_head;
	338	m_head = &elem;
	339	}
340	340
341		ATTR_HOT inline void add(_ListClass &elem)
342		{
343		_ListClass **p = &m_head;
344		while (*p != NULL)
345		{
346		p = &((*p)->m_next);
347		}
348		*p = &elem;
349		elem.m_next = NULL;
350		}
	341	ATTR_HOT inline void add(_ListClass &elem)
	342	{
	343	_ListClass **p = &m_head;
	344	while (*p != NULL)
	345	{
	346	p = &((*p)->m_next);
	347	}
	348	*p = &elem;
	349	elem.m_next = NULL;
	350	}
351	351
352		ATTR_HOT inline void remove(const _ListClass &elem)
353		{
354		_ListClass **p = &m_head;
355		while (*p != &elem)
356		{
357		assert(*p != NULL);
358		p = &((*p)->m_next);
359		}
360		(*p) = elem.m_next;
361		}
	352	ATTR_HOT inline void remove(const _ListClass &elem)
	353	{
	354	_ListClass **p = &m_head;
	355	while (*p != &elem)
	356	{
	357	assert(*p != NULL);
	358	p = &((*p)->m_next);
	359	}
	360	(*p) = elem.m_next;
	361	}
362	362
363	363
364		ATTR_HOT static inline _ListClass *next(const _ListClass &elem) { return elem.m_next; }
365		ATTR_HOT static inline _ListClass next(const _ListClass elem) { return elem->m_next; }
366		ATTR_HOT inline _ListClass *first() const { return m_head; }
367		ATTR_HOT inline void clear() { m_head = NULL; }
368		ATTR_HOT inline bool is_empty() const { return (m_head == NULL); }
	364	ATTR_HOT static inline _ListClass *next(const _ListClass &elem) { return elem.m_next; }
	365	ATTR_HOT static inline _ListClass next(const _ListClass elem) { return elem->m_next; }
	366	ATTR_HOT inline _ListClass *first() const { return m_head; }
	367	ATTR_HOT inline void clear() { m_head = NULL; }
	368	ATTR_HOT inline bool is_empty() const { return (m_head == NULL); }
369	369
370	370	private:
371		_ListClass *m_head;
	371	_ListClass *m_head;
372	372	};
373	373
374	374	#endif /* NLLISTS_H_ */

trunk/src/emu/netlist/nl_setup.h
r29404	r29405
39	39	setup.register_link(# _name "." # _input, # _output);
40	40
41	41	#define NET_C(_term1, ...) \
42		setup.register_link_arr( #_term1 ", " # __VA_ARGS__);
	42	setup.register_link_arr( #_term1 ", " # __VA_ARGS__);
43	43
44	44	#define PARAM(_name, _val) \
45	45	setup.register_param(# _name, _val);
r29404	r29405
55	55	#define NETLIST_START(_name) \
56	56	ATTR_COLD void NETLIST_NAME(_name)(netlist_setup_t &setup) \
57	57	{
58
59
60	58	#define NETLIST_END() }
61	59
62	60	#define INCLUDE(_name) \
63	61	NETLIST_NAME(_name)(setup);
64	62
65	63	#define SUBMODEL(_name, _model) \
66		setup.namespace_push(# _name); \
67		NETLIST_NAME(_model)(setup); \
68		setup.namespace_pop();
	64	setup.namespace_push(# _name); \
	65	NETLIST_NAME(_model)(setup); \
	66	setup.namespace_pop();
69	67
70	68	// ----------------------------------------------------------------------------------------
71	69	// FIXME: Clean this up
r29404	r29405
117	115	netlist_base_t &netlist() { return m_netlist; }
118	116	const netlist_base_t &netlist() const { return m_netlist; }
119	117	netlist_factory_t &factory() { return m_factory; }
120		const netlist_factory_t &factory() const { return m_factory; }
	118	const netlist_factory_t &factory() const { return m_factory; }
121	119
122		pstring build_fqn(const pstring &obj_name) const;
	120	pstring build_fqn(const pstring &obj_name) const;
123	121
124	122	netlist_device_t register_dev(netlist_device_t dev, const pstring &name);
125	123	void remove_dev(const pstring &name);
r29404	r29405
127	125	void register_model(const pstring &model);
128	126	void register_alias(const pstring &alias, const pstring &out);
129	127	void register_alias_nofqn(const pstring &alias, const pstring &out);
130		void register_link_arr(const pstring &terms);
	128	void register_link_arr(const pstring &terms);
131	129	void register_link(const pstring &sin, const pstring &sout);
132	130	void register_param(const pstring &param, const pstring &value);
133	131	void register_param(const pstring &param, const double value);
r29404	r29405
148	146	/* handle namespace */
149	147
150	148	void namespace_push(const pstring &aname);
151		void namespace_pop();
	149	void namespace_pop();
152	150
153	151	/* not ideal, but needed for save_state */
154	152	tagmap_terminal_t m_terminals;
r29404	r29405
172	170
173	171	int m_proxy_cnt;
174	172
175		netlist_stack_t<pstring> m_stack;
	173	netlist_stack_t<pstring> m_stack;
176	174
177	175
178	176	void connect_terminals(netlist_core_terminal_t &in, netlist_core_terminal_t &out);

trunk/src/emu/netlist/pstate.c
r29404	r29405
17	17	pstring fullname = stname;
18	18	ATTR_UNUSED pstring ts[] = {
19	19	"NOT_SUPPORTED",
20		"DT_CUSTOM",
	20	"DT_CUSTOM",
21	21	"DT_DOUBLE",
22	22	"DT_INT64",
23		"DT_INT16",
	23	"DT_INT16",
24	24	"DT_INT8",
25	25	"DT_INT",
26	26	"DT_BOOLEAN"
r29404	r29405
33	33
34	34	ATTR_COLD void pstate_manager_t::remove_save_items(const void *owner)
35	35	{
36		pstate_entry_t::list_t todelete;
	36	pstate_entry_t::list_t todelete;
37	37
38		for (int i=0; i < m_save.count(); i++)
39		{
40		if (m_save[i]->m_owner == owner)
41		todelete.add(m_save[i]);
42		}
43		for (int i=0; i < todelete.count(); i++)
44		{
45		m_save.remove(todelete[i]);
46		}
47		todelete.clear_and_free();
	38	for (int i=0; i < m_save.count(); i++)
	39	{
	40	if (m_save[i]->m_owner == owner)
	41	todelete.add(m_save[i]);
	42	}
	43	for (int i=0; i < todelete.count(); i++)
	44	{
	45	m_save.remove(todelete[i]);
	46	}
	47	todelete.clear_and_free();
48	48	}
49	49
50	50	ATTR_COLD void pstate_manager_t::pre_save()
51	51	{
52	52	for (int i=0; i < m_save.count(); i++)
53		if (m_save[i]->m_dt == DT_CUSTOM)
54		m_save[i]->m_callback->on_pre_save();
	53	if (m_save[i]->m_dt == DT_CUSTOM)
	54	m_save[i]->m_callback->on_pre_save();
55	55	}
56	56
57	57	ATTR_COLD void pstate_manager_t::post_load()
58	58	{
59		for (int i=0; i < m_save.count(); i++)
60		if (m_save[i]->m_dt == DT_CUSTOM)
61		m_save[i]->m_callback->on_post_load();
	59	for (int i=0; i < m_save.count(); i++)
	60	if (m_save[i]->m_dt == DT_CUSTOM)
	61	m_save[i]->m_callback->on_post_load();
62	62	}

trunk/src/emu/netlist/devices/nld_74107.c
r29404	r29405
18	18
19	19	NETLIB_RESET(74107Asub)
20	20	{
21		m_clk.set_state(netlist_input_t::STATE_INP_HL);
22		m_Q.initial(0);
23		m_QQ.initial(1);
	21	m_clk.set_state(netlist_input_t::STATE_INP_HL);
	22	m_Q.initial(0);
	23	m_QQ.initial(1);
24	24
25		m_Q1 = 0;
26		m_Q2 = 0;
27		m_F = 0;
	25	m_Q1 = 0;
	26	m_Q2 = 0;
	27	m_F = 0;
28	28	}
29	29
30	30	NETLIB_START(74107A)
r29404	r29405
42	42
43	43	NETLIB_RESET(74107A)
44	44	{
45		sub.reset();
	45	sub.reset();
46	46	}
47	47
48	48	ATTR_HOT inline void NETLIB_NAME(74107Asub)::newstate(const netlist_sig_t state)
r29404	r29405
103	103
104	104	NETLIB_START(74107_dip)
105	105	{
106		register_sub(m_1, "1");
107		register_sub(m_2, "2");
	106	register_sub(m_1, "1");
	107	register_sub(m_2, "2");
108	108
109		register_subalias("1", m_1.m_J);
110		register_subalias("2", m_1.sub.m_QQ);
111		register_subalias("3", m_1.sub.m_Q);
	109	register_subalias("1", m_1.m_J);
	110	register_subalias("2", m_1.sub.m_QQ);
	111	register_subalias("3", m_1.sub.m_Q);
112	112
113		register_subalias("4", m_1.m_K);
114		register_subalias("5", m_2.sub.m_Q);
115		register_subalias("6", m_2.sub.m_QQ);
	113	register_subalias("4", m_1.m_K);
	114	register_subalias("5", m_2.sub.m_Q);
	115	register_subalias("6", m_2.sub.m_QQ);
116	116
117		// register_subalias("7", ); ==> GND
	117	// register_subalias("7", ); ==> GND
118	118
119		register_subalias("8", m_2.m_J);
120		register_subalias("9", m_2.sub.m_clk);
121		register_subalias("10", m_2.m_clrQ);
	119	register_subalias("8", m_2.m_J);
	120	register_subalias("9", m_2.sub.m_clk);
	121	register_subalias("10", m_2.m_clrQ);
122	122
123		register_subalias("11", m_2.m_K);
124		register_subalias("12", m_1.sub.m_clk);
125		register_subalias("13", m_1.m_clrQ);
	123	register_subalias("11", m_2.m_K);
	124	register_subalias("12", m_1.sub.m_clk);
	125	register_subalias("13", m_1.m_clrQ);
126	126
127		// register_subalias("14", ); ==> VCC
	127	// register_subalias("14", ); ==> VCC
128	128	}
129	129
130	130	NETLIB_RESET(74107_dip)
131	131	{
132		m_1.do_reset();
133		m_2.do_reset();
	132	m_1.do_reset();
	133	m_2.do_reset();
134	134	}
135	135
136	136	NETLIB_UPDATE(74107_dip)
137	137	{
138		/* only called during startup */
139		m_1.update_dev();
140		m_2.update_dev();
	138	/* only called during startup */
	139	m_1.update_dev();
	140	m_2.update_dev();
141	141	}

trunk/src/emu/netlist/devices/nld_signal.h
r29404	r29405
47	47
48	48	ATTR_COLD void reset()
49	49	{
50		m_Q.initial(1);
51		m_active = 1;
	50	m_Q.initial(1);
	51	m_active = 1;
52	52	}
53	53
54	54	#if (USE_DEACTIVE_DEVICE)
r29404	r29405
98	98	save(NAME(m_active));
99	99	}
100	100
101		ATTR_COLD void reset()
102		{
103		m_Q.initial(1);
104		m_active = 1;
105		}
	101	ATTR_COLD void reset()
	102	{
	103	m_Q.initial(1);
	104	m_active = 1;
	105	}
106	106
107	107	#if (USE_DEACTIVE_DEVICE)
108		ATTR_HOT void inc_active()
109		{
110		if (++m_active == 1)
111		{
112		update();
113		}
114		}
	108	ATTR_HOT void inc_active()
	109	{
	110	if (++m_active == 1)
	111	{
	112	update();
	113	}
	114	}
115	115
116		ATTR_HOT void dec_active()
117		{
118		if (--m_active == 0)
119		{
120		for (int i = 0; i< _numdev; i++)
121		m_i[i].inactivate();
122		}
123		}
	116	ATTR_HOT void dec_active()
	117	{
	118	if (--m_active == 0)
	119	{
	120	for (int i = 0; i< _numdev; i++)
	121	m_i[i].inactivate();
	122	}
	123	}
124	124	#endif
125	125
126		virtual void update()
127		{
128		const netlist_time times[2] = { NLTIME_FROM_NS(22), NLTIME_FROM_NS(15) };
	126	virtual void update()
	127	{
	128	const netlist_time times[2] = { NLTIME_FROM_NS(22), NLTIME_FROM_NS(15) };
129	129
130		// FIXME: this check is needed because update is called during startup as well
131		if (UNEXPECTED(USE_DEACTIVE_DEVICE && m_active == 0))
132		return;
	130	// FIXME: this check is needed because update is called during startup as well
	131	if (UNEXPECTED(USE_DEACTIVE_DEVICE && m_active == 0))
	132	return;
133	133
134		for (int i = 0; i< _numdev; i++)
135		{
136		this->m_i[i].activate();
137		if (INPLOGIC(this->m_i[i]) == _check)
138		{
139		for (int j = 0; j < i; j++)
140		this->m_i[j].inactivate();
141		for (int j = i + 1; j < _numdev; j++)
142		this->m_i[j].inactivate();
	134	for (int i = 0; i< _numdev; i++)
	135	{
	136	this->m_i[i].activate();
	137	if (INPLOGIC(this->m_i[i]) == _check)
	138	{
	139	for (int j = 0; j < i; j++)
	140	this->m_i[j].inactivate();
	141	for (int j = i + 1; j < _numdev; j++)
	142	this->m_i[j].inactivate();
143	143
144		OUTLOGIC(this->m_Q, _check ^ (1 ^ _invert), times[_check]);// ? 15000 : 22000);
145		return;
146		}
147		}
148		OUTLOGIC(this->m_Q,_check ^ (_invert), times[1-_check]);// ? 22000 : 15000);
149		}
	144	OUTLOGIC(this->m_Q, _check ^ (1 ^ _invert), times[_check]);// ? 15000 : 22000);
	145	return;
	146	}
	147	}
	148	OUTLOGIC(this->m_Q,_check ^ (_invert), times[1-_check]);// ? 22000 : 15000);
	149	}
150	150
151	151	public:
152	152	netlist_ttl_input_t m_i[_numdev];
r29404	r29405
166	166	ATTR_COLD void start()
167	167	{
168	168	register_output("Q", m_Q);
169		register_input("A", m_i[0]);
170		register_input("B", m_i[1]);
	169	register_input("A", m_i[0]);
	170	register_input("B", m_i[1]);
171	171
172		save(NAME(m_active));
	172	save(NAME(m_active));
173	173	}
174	174
175		ATTR_COLD void reset()
176		{
177		m_Q.initial(1);
178		m_active = 1;
179		}
	175	ATTR_COLD void reset()
	176	{
	177	m_Q.initial(1);
	178	m_active = 1;
	179	}
180	180
181	181	#if (USE_DEACTIVE_DEVICE)
182		ATTR_HOT virtual void inc_active()
183		{
184		if (++m_active == 1)
185		{
186		update();
187		}
188		}
	182	ATTR_HOT virtual void inc_active()
	183	{
	184	if (++m_active == 1)
	185	{
	186	update();
	187	}
	188	}
189	189
190		ATTR_HOT virtual void dec_active()
191		{
192		if (--m_active == 0)
193		{
194		m_i[0].inactivate();
195		m_i[1].inactivate();
196		}
197		}
	190	ATTR_HOT virtual void dec_active()
	191	{
	192	if (--m_active == 0)
	193	{
	194	m_i[0].inactivate();
	195	m_i[1].inactivate();
	196	}
	197	}
198	198	#endif
199	199
200	200	ATTR_HOT ATTR_ALIGN void update()
r29404	r29405
202	202	const netlist_time times[2] = { NLTIME_FROM_NS(15), NLTIME_FROM_NS(22)};
203	203
204	204	// FIXME: this check is needed because update is called during startup as well
205		if (UNEXPECTED(USE_DEACTIVE_DEVICE && m_active == 0))
206		return;
	205	if (UNEXPECTED(USE_DEACTIVE_DEVICE && m_active == 0))
	206	return;
207	207
208	208	m_i[0].activate();
209	209	m_i[1].activate();
210	210	#if 0
211		UINT8 res = _invert ^ 1 ^_check;
	211	UINT8 res = _invert ^ 1 ^_check;
212	212	if (INPLOGIC(m_i[0]) ^ _check)
213	213	{
214	214	if (INPLOGIC(m_i[1]) ^ _check)
r29404	r29405
221	221	if (INPLOGIC(m_i[1]) ^ _check)
222	222	m_i[1].inactivate();
223	223	}
224		OUTLOGIC(m_Q, res, times[res & 1]);// ? 22000 : 15000);
	224	OUTLOGIC(m_Q, res, times[res & 1]);// ? 22000 : 15000);
225	225	#else
226	226	const UINT8 val = (INPLOGIC(m_i[0]) ^ _check) \| ((INPLOGIC(m_i[1]) ^ _check) << 1);
227		UINT8 res = _invert ^ 1 ^_check;
	227	UINT8 res = _invert ^ 1 ^_check;
228	228	switch (val)
229	229	{
230		case 1:
231		m_i[0].inactivate();
232		break;
233		case 2:
234		m_i[1].inactivate();
235		break;
236		case 3:
237		res = _invert ^ _check;
238		break;
	230	case 1:
	231	m_i[0].inactivate();
	232	break;
	233	case 2:
	234	m_i[1].inactivate();
	235	break;
	236	case 3:
	237	res = _invert ^ _check;
	238	break;
239	239	}
240		OUTLOGIC(m_Q, res, times[res]);// ? 22000 : 15000);
	240	OUTLOGIC(m_Q, res, times[res]);// ? 22000 : 15000);
241	241	#endif
242	242	}
243	243

trunk/src/emu/netlist/devices/nld_74107.h
r29404	r29405
72	72	TTL_74107A(_name, _CLK, _J, _K, _CLRQ)
73	73
74	74	#define TTL_74107_DIP(_name) \
75		NET_REGISTER_DEV(74107_dip, _name)
	75	NET_REGISTER_DEV(74107_dip, _name)
76	76
77	77	NETLIB_SUBDEVICE(74107Asub,
78	78	netlist_ttl_input_t m_clk;
r29404	r29405
108	108
109	109	NETLIB_DEVICE(74107_dip,
110	110
111		NETLIB_NAME(74107) m_1;
112		NETLIB_NAME(74107) m_2;
	111	NETLIB_NAME(74107) m_1;
	112	NETLIB_NAME(74107) m_2;
113	113	);
114	114
115	115	#endif /* NLD_74107_H_ */

trunk/src/emu/netlist/devices/nld_7400.c
r29404	r29405
7	7
8	8	NETLIB_START(7400_dip)
9	9	{
10		register_sub(m_1, "1");
11		register_sub(m_2, "2");
12		register_sub(m_3, "3");
13		register_sub(m_4, "4");
	10	register_sub(m_1, "1");
	11	register_sub(m_2, "2");
	12	register_sub(m_3, "3");
	13	register_sub(m_4, "4");
14	14
15		register_subalias("1", m_1.m_i[0]);
16		register_subalias("2", m_1.m_i[1]);
17		register_subalias("3", m_1.m_Q);
	15	register_subalias("1", m_1.m_i[0]);
	16	register_subalias("2", m_1.m_i[1]);
	17	register_subalias("3", m_1.m_Q);
18	18
19		register_subalias("4", m_2.m_i[0]);
20		register_subalias("5", m_2.m_i[1]);
21		register_subalias("6", m_2.m_Q);
	19	register_subalias("4", m_2.m_i[0]);
	20	register_subalias("5", m_2.m_i[1]);
	21	register_subalias("6", m_2.m_Q);
22	22
23		register_subalias("9", m_3.m_i[0]);
24		register_subalias("10", m_3.m_i[1]);
25		register_subalias("8", m_3.m_Q);
	23	register_subalias("9", m_3.m_i[0]);
	24	register_subalias("10", m_3.m_i[1]);
	25	register_subalias("8", m_3.m_Q);
26	26
27		register_subalias("12", m_4.m_i[0]);
28		register_subalias("13", m_4.m_i[1]);
29		register_subalias("11", m_4.m_Q);
	27	register_subalias("12", m_4.m_i[0]);
	28	register_subalias("13", m_4.m_i[1]);
	29	register_subalias("11", m_4.m_Q);
30	30	}
31	31
32	32	NETLIB_UPDATE(7400_dip)
33	33	{
34		/* only called during startup */
35		m_1.update_dev();
36		m_2.update_dev();
37		m_3.update_dev();
38		m_4.update_dev();
	34	/* only called during startup */
	35	m_1.update_dev();
	36	m_2.update_dev();
	37	m_3.update_dev();
	38	m_4.update_dev();
39	39	}
40	40
41	41	NETLIB_RESET(7400_dip)
42	42	{
43		m_1.do_reset();
44		m_2.do_reset();
45		m_3.do_reset();
46		m_4.do_reset();
	43	m_1.do_reset();
	44	m_2.do_reset();
	45	m_3.do_reset();
	46	m_4.do_reset();
47	47	}
48

trunk/src/emu/netlist/devices/nld_74ls629.c
r29404	r29405
50	50	reset();
51	51
52	52	save(NAME(m_enableq));
53		save(NAME(m_inc));
	53	save(NAME(m_inc));
54	54	}
55	55
56	56	NETLIB_RESET(SN74LS629clk)
57	57	{
58		m_enableq = 1;
59		m_inc = netlist_time::zero;
	58	m_enableq = 1;
	59	m_inc = netlist_time::zero;
60	60	}
61	61
62	62	NETLIB_UPDATE(SN74LS629clk)
63	63	{
64		if (!m_enableq)
65		{
66		OUTLOGIC(m_Y, !m_Y.net().new_Q(), m_inc);
67		}
68		else
69		{
70		OUTLOGIC(m_Y, 1, m_inc);
71		}
	64	if (!m_enableq)
	65	{
	66	OUTLOGIC(m_Y, !m_Y.net().new_Q(), m_inc);
	67	}
	68	else
	69	{
	70	OUTLOGIC(m_Y, 1, m_inc);
	71	}
72	72	}
73	73
74	74	NETLIB_START(SN74LS629)
75	75	{
76		register_sub(m_clock, "OSC");
77		register_sub(m_R_FC, "R_FC");
78		register_sub(m_R_RNG, "R_RNG");
	76	register_sub(m_clock, "OSC");
	77	register_sub(m_R_FC, "R_FC");
	78	register_sub(m_R_RNG, "R_RNG");
79	79
80		register_input("ENQ", m_ENQ);
81		register_input("RNG", m_RNG);
82		register_input("FC", m_FC);
83		register_subalias("GND", m_R_FC.m_N);
	80	register_input("ENQ", m_ENQ);
	81	register_input("RNG", m_RNG);
	82	register_input("FC", m_FC);
	83	register_subalias("GND", m_R_FC.m_N);
84	84
85		connect(m_FC, m_R_FC.m_P);
86		connect(m_RNG, m_R_RNG.m_P);
87		connect(m_R_FC.m_N, m_R_RNG.m_N);
	85	connect(m_FC, m_R_FC.m_P);
	86	connect(m_RNG, m_R_RNG.m_P);
	87	connect(m_R_FC.m_N, m_R_RNG.m_N);
88	88
89		register_subalias("Y", m_clock.m_Y);
90		register_param("CAP", m_CAP, 1e-6);
	89	register_subalias("Y", m_clock.m_Y);
	90	register_param("CAP", m_CAP, 1e-6);
91	91	}
92	92
93	93	NETLIB_RESET(SN74LS629)
94	94	{
95		m_R_FC.set_R(90000.0);
96		m_R_RNG.set_R(90000.0);
97		m_clock.reset();
	95	m_R_FC.set_R(90000.0);
	96	m_R_RNG.set_R(90000.0);
	97	m_clock.reset();
98	98	}
99	99
100	100	NETLIB_UPDATE(SN74LS629)
101	101	{
102		{
103		// recompute
104		double freq;
105		double v_freq_2, v_freq_3, v_freq_4;
106		double v_freq = INPANALOG(m_FC);
107		double v_rng = INPANALOG(m_RNG);
	102	{
	103	// recompute
	104	double freq;
	105	double v_freq_2, v_freq_3, v_freq_4;
	106	double v_freq = INPANALOG(m_FC);
	107	double v_rng = INPANALOG(m_RNG);
108	108
109		/* coefficients */
110		const double k1 = 1.9904769024796283E+03;
111		const double k2 = 1.2070059213983407E+03;
112		const double k3 = 1.3266985579561108E+03;
113		const double k4 = -1.5500979825922698E+02;
114		const double k5 = 2.8184536266938172E+00;
115		const double k6 = -2.3503421582744556E+02;
116		const double k7 = -3.3836786704527788E+02;
117		const double k8 = -1.3569136703258670E+02;
118		const double k9 = 2.9914575453819188E+00;
119		const double k10 = 1.6855569086173170E+00;
	109	/* coefficients */
	110	const double k1 = 1.9904769024796283E+03;
	111	const double k2 = 1.2070059213983407E+03;
	112	const double k3 = 1.3266985579561108E+03;
	113	const double k4 = -1.5500979825922698E+02;
	114	const double k5 = 2.8184536266938172E+00;
	115	const double k6 = -2.3503421582744556E+02;
	116	const double k7 = -3.3836786704527788E+02;
	117	const double k8 = -1.3569136703258670E+02;
	118	const double k9 = 2.9914575453819188E+00;
	119	const double k10 = 1.6855569086173170E+00;
120	120
121		/* scale due to input resistance */
	121	/* scale due to input resistance */
122	122
123		/* Polyfunctional3D_model created by zunzun.com using sum of squared absolute error */
124		v_freq_2 = v_freq * v_freq;
125		v_freq_3 = v_freq_2 * v_freq;
126		v_freq_4 = v_freq_3 * v_freq;
127		freq = k1;
128		freq += k2 * v_freq;
129		freq += k3 * v_freq_2;
130		freq += k4 * v_freq_3;
131		freq += k5 * v_freq_4;
132		freq += k6 * v_rng;
133		freq += k7 * v_rng * v_freq;
134		freq += k8 * v_rng * v_freq_2;
135		freq += k9 * v_rng * v_freq_3;
136		freq += k10 * v_rng * v_freq_4;
	123	/* Polyfunctional3D_model created by zunzun.com using sum of squared absolute error */
	124	v_freq_2 = v_freq * v_freq;
	125	v_freq_3 = v_freq_2 * v_freq;
	126	v_freq_4 = v_freq_3 * v_freq;
	127	freq = k1;
	128	freq += k2 * v_freq;
	129	freq += k3 * v_freq_2;
	130	freq += k4 * v_freq_3;
	131	freq += k5 * v_freq_4;
	132	freq += k6 * v_rng;
	133	freq += k7 * v_rng * v_freq;
	134	freq += k8 * v_rng * v_freq_2;
	135	freq += k9 * v_rng * v_freq_3;
	136	freq += k10 * v_rng * v_freq_4;
137	137
138		freq *= 0.1e-6 / m_CAP.Value();
	138	freq *= 0.1e-6 / m_CAP.Value();
139	139
140		// FIXME: we need a possibility to remove entries from queue ...
141		// or an exact model ...
142		m_clock.m_inc = netlist_time::from_double(0.5 / freq);
143		//m_clock.update();
144		}
	140	// FIXME: we need a possibility to remove entries from queue ...
	141	// or an exact model ...
	142	m_clock.m_inc = netlist_time::from_double(0.5 / freq);
	143	//m_clock.update();
	144	}
145	145
146		if (!m_clock.m_enableq && INPLOGIC(m_ENQ))
147		{
148		m_clock.m_enableq = 1;
149		OUTLOGIC(m_clock.m_Y, !m_clock.m_Y.net().last_Q(), netlist_time::from_nsec(1));
150		}
151		else if (m_clock.m_enableq && !INPLOGIC(m_ENQ))
152		{
153		m_clock.m_enableq = 0;
154		OUTLOGIC(m_clock.m_Y, !m_clock.m_Y.net().last_Q(), netlist_time::from_nsec(1));
155		}
	146	if (!m_clock.m_enableq && INPLOGIC(m_ENQ))
	147	{
	148	m_clock.m_enableq = 1;
	149	OUTLOGIC(m_clock.m_Y, !m_clock.m_Y.net().last_Q(), netlist_time::from_nsec(1));
	150	}
	151	else if (m_clock.m_enableq && !INPLOGIC(m_ENQ))
	152	{
	153	m_clock.m_enableq = 0;
	154	OUTLOGIC(m_clock.m_Y, !m_clock.m_Y.net().last_Q(), netlist_time::from_nsec(1));
	155	}
156	156	}
157	157
158	158	NETLIB_UPDATE_PARAM(SN74LS629)
159	159	{
160		//printf("updating %s to %f\n", name().cstr(), m_R.Value());
161		update_dev();
	160	//printf("updating %s to %f\n", name().cstr(), m_R.Value());
	161	update_dev();
162	162	}
163	163
164	164
165	165
166	166	NETLIB_START(SN74LS629_dip)
167	167	{
168		register_sub(m_1, "1");
169		register_sub(m_2, "2");
	168	register_sub(m_1, "1");
	169	register_sub(m_2, "2");
170	170
171		register_subalias("1", m_2.m_FC);
172		register_subalias("2", m_1.m_FC);
173		register_subalias("3", m_1.m_RNG);
	171	register_subalias("1", m_2.m_FC);
	172	register_subalias("2", m_1.m_FC);
	173	register_subalias("3", m_1.m_RNG);
174	174
175		register_subalias("6", m_1.m_ENQ);
176		register_subalias("7", m_1.m_clock.m_Y);
	175	register_subalias("6", m_1.m_ENQ);
	176	register_subalias("7", m_1.m_clock.m_Y);
177	177
178		register_subalias("8", m_1.m_R_FC.m_N);
179		register_subalias("9", m_1.m_R_FC.m_N);
180		connect(m_1.m_R_FC.m_N, m_2.m_R_FC.m_N);
	178	register_subalias("8", m_1.m_R_FC.m_N);
	179	register_subalias("9", m_1.m_R_FC.m_N);
	180	connect(m_1.m_R_FC.m_N, m_2.m_R_FC.m_N);
181	181
182		register_subalias("10", m_2.m_clock.m_Y);
	182	register_subalias("10", m_2.m_clock.m_Y);
183	183
184		register_subalias("11", m_2.m_ENQ);
185		register_subalias("14", m_2.m_RNG);
	184	register_subalias("11", m_2.m_ENQ);
	185	register_subalias("14", m_2.m_RNG);
186	186
187	187	}
188	188
r29404	r29405
192	192
193	193	NETLIB_RESET(SN74LS629_dip)
194	194	{
195		m_1.do_reset();
196		m_2.do_reset();
	195	m_1.do_reset();
	196	m_2.do_reset();
197	197	}

trunk/src/emu/netlist/devices/nld_7420.c
r29404	r29405
7	7
8	8	NETLIB_START(7420_dip)
9	9	{
10		register_sub(m_1, "1");
11		register_sub(m_2, "2");
	10	register_sub(m_1, "1");
	11	register_sub(m_2, "2");
12	12
13		register_subalias("1", m_1.m_i[0]);
14		register_subalias("2", m_1.m_i[1]);
	13	register_subalias("1", m_1.m_i[0]);
	14	register_subalias("2", m_1.m_i[1]);
15	15
16		register_subalias("4", m_1.m_i[2]);
17		register_subalias("5", m_1.m_i[3]);
18		register_subalias("6", m_1.m_Q);
	16	register_subalias("4", m_1.m_i[2]);
	17	register_subalias("5", m_1.m_i[3]);
	18	register_subalias("6", m_1.m_Q);
19	19
20		register_subalias("8", m_2.m_Q);
21		register_subalias("9", m_2.m_i[0]);
22		register_subalias("10", m_2.m_i[1]);
	20	register_subalias("8", m_2.m_Q);
	21	register_subalias("9", m_2.m_i[0]);
	22	register_subalias("10", m_2.m_i[1]);
23	23
24		register_subalias("12", m_2.m_i[2]);
25		register_subalias("13", m_2.m_i[3]);
	24	register_subalias("12", m_2.m_i[2]);
	25	register_subalias("13", m_2.m_i[3]);
26	26
27	27	}
28	28
29	29	NETLIB_UPDATE(7420_dip)
30	30	{
31		/* only called during startup */
32		m_1.update_dev();
33		m_2.update_dev();
	31	/* only called during startup */
	32	m_1.update_dev();
	33	m_2.update_dev();
34	34	}
35	35
36	36	NETLIB_RESET(7420_dip)
37	37	{
38		m_1.do_reset();
39		m_2.do_reset();
	38	m_1.do_reset();
	39	m_2.do_reset();
40	40	}
41

trunk/src/emu/netlist/devices/nld_7402.c
r29404	r29405
7	7
8	8	NETLIB_START(7402_dip)
9	9	{
10		register_sub(m_1, "1");
11		register_sub(m_2, "2");
12		register_sub(m_3, "3");
13		register_sub(m_4, "4");
	10	register_sub(m_1, "1");
	11	register_sub(m_2, "2");
	12	register_sub(m_3, "3");
	13	register_sub(m_4, "4");
14	14
15		register_subalias("1", m_1.m_Q);
16		register_subalias("2", m_1.m_i[0]);
17		register_subalias("3", m_1.m_i[1]);
	15	register_subalias("1", m_1.m_Q);
	16	register_subalias("2", m_1.m_i[0]);
	17	register_subalias("3", m_1.m_i[1]);
18	18
19		register_subalias("4", m_2.m_Q);
20		register_subalias("5", m_2.m_i[0]);
21		register_subalias("6", m_2.m_i[1]);
	19	register_subalias("4", m_2.m_Q);
	20	register_subalias("5", m_2.m_i[0]);
	21	register_subalias("6", m_2.m_i[1]);
22	22
23		register_subalias("8", m_3.m_i[0]);
24		register_subalias("9", m_3.m_i[1]);
25		register_subalias("10", m_3.m_Q);
	23	register_subalias("8", m_3.m_i[0]);
	24	register_subalias("9", m_3.m_i[1]);
	25	register_subalias("10", m_3.m_Q);
26	26
27		register_subalias("11", m_4.m_i[0]);
28		register_subalias("12", m_4.m_i[1]);
29		register_subalias("13", m_4.m_Q);
	27	register_subalias("11", m_4.m_i[0]);
	28	register_subalias("12", m_4.m_i[1]);
	29	register_subalias("13", m_4.m_Q);
30	30	}
31	31
32	32	NETLIB_UPDATE(7402_dip)
33	33	{
34		/* only called during startup */
35		m_1.update_dev();
36		m_2.update_dev();
37		m_3.update_dev();
38		m_4.update_dev();
	34	/* only called during startup */
	35	m_1.update_dev();
	36	m_2.update_dev();
	37	m_3.update_dev();
	38	m_4.update_dev();
39	39	}
40	40
41	41	NETLIB_RESET(7402_dip)
42	42	{
43		m_1.do_reset();
44		m_2.do_reset();
45		m_3.do_reset();
46		m_4.do_reset();
	43	m_1.do_reset();
	44	m_2.do_reset();
	45	m_3.do_reset();
	46	m_4.do_reset();
47	47	}
48

trunk/src/emu/netlist/devices/nld_7404.c
r29404	r29405
24	24
25	25	NETLIB_START(7404_dip)
26	26	{
27		register_sub(m_1, "1");
28		register_sub(m_2, "2");
29		register_sub(m_3, "3");
30		register_sub(m_4, "4");
31		register_sub(m_5, "5");
32		register_sub(m_6, "6");
	27	register_sub(m_1, "1");
	28	register_sub(m_2, "2");
	29	register_sub(m_3, "3");
	30	register_sub(m_4, "4");
	31	register_sub(m_5, "5");
	32	register_sub(m_6, "6");
33	33
34		register_subalias("1", m_1.m_I);
35		register_subalias("2", m_1.m_Q);
	34	register_subalias("1", m_1.m_I);
	35	register_subalias("2", m_1.m_Q);
36	36
37		register_subalias("3", m_2.m_I);
38		register_subalias("4", m_2.m_Q);
	37	register_subalias("3", m_2.m_I);
	38	register_subalias("4", m_2.m_Q);
39	39
40		register_subalias("5", m_3.m_I);
41		register_subalias("6", m_3.m_Q);
	40	register_subalias("5", m_3.m_I);
	41	register_subalias("6", m_3.m_Q);
42	42
43		register_subalias("8", m_4.m_Q);
44		register_subalias("9", m_4.m_I);
	43	register_subalias("8", m_4.m_Q);
	44	register_subalias("9", m_4.m_I);
45	45
46		register_subalias("10", m_5.m_Q);
47		register_subalias("11", m_5.m_I);
	46	register_subalias("10", m_5.m_Q);
	47	register_subalias("11", m_5.m_I);
48	48
49		register_subalias("12", m_6.m_Q);
50		register_subalias("13", m_6.m_I);
	49	register_subalias("12", m_6.m_Q);
	50	register_subalias("13", m_6.m_I);
51	51	}
52	52
53	53	NETLIB_UPDATE(7404_dip)
54	54	{
55		/* only called during startup */
	55	/* only called during startup */
56	56
57		m_1.update_dev();
58		m_2.update_dev();
59		m_3.update_dev();
60		m_4.update_dev();
61		m_5.update_dev();
62		m_6.update_dev();
	57	m_1.update_dev();
	58	m_2.update_dev();
	59	m_3.update_dev();
	60	m_4.update_dev();
	61	m_5.update_dev();
	62	m_6.update_dev();
63	63	}
64	64
65	65	NETLIB_RESET(7404_dip)
66	66	{
67		m_1.do_reset();
68		m_2.do_reset();
69		m_3.do_reset();
70		m_4.do_reset();
71		m_5.do_reset();
72		m_6.do_reset();
	67	m_1.do_reset();
	68	m_2.do_reset();
	69	m_3.do_reset();
	70	m_4.do_reset();
	71	m_5.do_reset();
	72	m_6.do_reset();
73	73	}

trunk/src/emu/netlist/devices/nld_7400.h
r29404	r29405
42	42	NETLIB_SIGNAL(7400, 2, 0, 0);
43	43
44	44	#define TTL_7400_DIP(_name) \
45		NET_REGISTER_DEV(7400_dip, _name)
	45	NET_REGISTER_DEV(7400_dip, _name)
46	46
47	47	NETLIB_DEVICE(7400_dip,
48	48

trunk/src/emu/netlist/devices/nld_74ls629.h
r29404	r29405
33	33
34	34	#define SN74LS629(_name, _cap) \
35	35	NET_REGISTER_DEV(SN74LS629, _name) \
36		NETDEV_PARAMI(_name, CAP, _cap)
	36	NETDEV_PARAMI(_name, CAP, _cap)
37	37
38	38	NETLIB_SUBDEVICE(SN74LS629clk,
39		netlist_logic_input_t m_FB;
40		netlist_logic_output_t m_Y;
	39	netlist_logic_input_t m_FB;
	40	netlist_logic_output_t m_Y;
41	41
42		netlist_time m_inc;
43		netlist_sig_t m_enableq;
	42	netlist_time m_inc;
	43	netlist_sig_t m_enableq;
44	44	);
45	45
46	46	NETLIB_DEVICE_WITH_PARAMS(SN74LS629,
47	47	public:
48	48	NETLIB_NAME(SN74LS629clk) m_clock;
49		NETLIB_NAME(R_base) m_R_FC;
50		NETLIB_NAME(R_base) m_R_RNG;
	49	NETLIB_NAME(R_base) m_R_FC;
	50	NETLIB_NAME(R_base) m_R_RNG;
51	51
52		netlist_logic_input_t m_ENQ;
	52	netlist_logic_input_t m_ENQ;
53	53	netlist_analog_input_t m_RNG;
54	54	netlist_analog_input_t m_FC;
55	55
r29404	r29405
57	57	);
58	58
59	59	#define SN74LS629_DIP(_name, _cap1, _cap2) \
60		NET_REGISTER_DEV(SN74LS629_dip, _name) \
61		NETDEV_PARAMI(_name, 1.CAP, _cap1) \
62		NETDEV_PARAMI(_name, 2.CAP, _cap2)
	60	NET_REGISTER_DEV(SN74LS629_dip, _name) \
	61	NETDEV_PARAMI(_name, 1.CAP, _cap1) \
	62	NETDEV_PARAMI(_name, 2.CAP, _cap2)
63	63
64	64	NETLIB_DEVICE(SN74LS629_dip,
65		NETLIB_NAME(SN74LS629) m_1;
66		NETLIB_NAME(SN74LS629) m_2;
	65	NETLIB_NAME(SN74LS629) m_1;
	66	NETLIB_NAME(SN74LS629) m_2;
67	67	);
68	68
69	69

trunk/src/emu/netlist/devices/nld_7425.c
r29404	r29405
7	7
8	8	NETLIB_START(7425_dip)
9	9	{
10		register_sub(m_1, "1");
11		register_sub(m_2, "2");
	10	register_sub(m_1, "1");
	11	register_sub(m_2, "2");
12	12
13		register_subalias("1", m_1.m_i[0]);
14		register_subalias("2", m_1.m_i[1]);
	13	register_subalias("1", m_1.m_i[0]);
	14	register_subalias("2", m_1.m_i[1]);
15	15
16		//register_subalias("3", ); X1 ==> NC
	16	//register_subalias("3", ); X1 ==> NC
17	17
18		register_subalias("4", m_1.m_i[2]);
19		register_subalias("5", m_1.m_i[3]);
20		register_subalias("6", m_1.m_Q);
	18	register_subalias("4", m_1.m_i[2]);
	19	register_subalias("5", m_1.m_i[3]);
	20	register_subalias("6", m_1.m_Q);
21	21
22		register_subalias("8", m_2.m_Q);
23		register_subalias("9", m_2.m_i[0]);
24		register_subalias("10", m_2.m_i[1]);
	22	register_subalias("8", m_2.m_Q);
	23	register_subalias("9", m_2.m_i[0]);
	24	register_subalias("10", m_2.m_i[1]);
25	25
26		//register_subalias("11", ); X2 ==> NC
	26	//register_subalias("11", ); X2 ==> NC
27	27
28		register_subalias("12", m_2.m_i[2]);
29		register_subalias("13", m_2.m_i[3]);
	28	register_subalias("12", m_2.m_i[2]);
	29	register_subalias("13", m_2.m_i[3]);
30	30
31	31	}
32	32
33	33	NETLIB_UPDATE(7425_dip)
34	34	{
35		/* only called during startup */
36		m_1.update_dev();
37		m_2.update_dev();
	35	/* only called during startup */
	36	m_1.update_dev();
	37	m_2.update_dev();
38	38	}
39	39
40	40	NETLIB_RESET(7425_dip)
41	41	{
42		m_1.do_reset();
43		m_2.do_reset();
	42	m_1.do_reset();
	43	m_2.do_reset();
44	44	}
45

trunk/src/emu/netlist/devices/nld_7420.h
r29404	r29405
46	46	NETLIB_SIGNAL(7420, 4, 0, 0);
47	47
48	48	#define TTL_7420_DIP(_name) \
49		NET_REGISTER_DEV(7420_dip, _name)
	49	NET_REGISTER_DEV(7420_dip, _name)
50	50
51	51	NETLIB_DEVICE(7420_dip,
52	52
53		NETLIB_NAME(7420) m_1;
54		NETLIB_NAME(7420) m_2;
	53	NETLIB_NAME(7420) m_1;
	54	NETLIB_NAME(7420) m_2;
55	55	);
56	56
57	57	#endif /* NLD_7420_H_ */

trunk/src/emu/netlist/devices/nld_7402.h
r29404	r29405
40	40	NET_CONNECT(_name, B, _I2)
41	41
42	42	#define TTL_7402_DIP(_name) \
43		NET_REGISTER_DEV(7402_dip, _name)
	43	NET_REGISTER_DEV(7402_dip, _name)
44	44
45	45
46	46	NETLIB_SIGNAL(7402, 2, 1, 0);
47	47
48	48	NETLIB_DEVICE(7402_dip,
49	49
50		NETLIB_NAME(7402) m_1;
51		NETLIB_NAME(7402) m_2;
52		NETLIB_NAME(7402) m_3;
53		NETLIB_NAME(7402) m_4;
	50	NETLIB_NAME(7402) m_1;
	51	NETLIB_NAME(7402) m_2;
	52	NETLIB_NAME(7402) m_3;
	53	NETLIB_NAME(7402) m_4;
54	54	);
55	55
56	56	#endif /* NLD_7402_H_ */

trunk/src/emu/netlist/devices/nld_7427.c
r29404	r29405
7	7
8	8	NETLIB_START(7427_dip)
9	9	{
10		register_sub(m_1, "1");
11		register_sub(m_2, "2");
12		register_sub(m_3, "3");
	10	register_sub(m_1, "1");
	11	register_sub(m_2, "2");
	12	register_sub(m_3, "3");
13	13
14		register_subalias("1", m_1.m_i[0]);
15		register_subalias("2", m_1.m_i[1]);
16		register_subalias("3", m_2.m_i[0]);
17		register_subalias("4", m_2.m_i[1]);
18		register_subalias("5", m_2.m_i[2]);
19		register_subalias("6", m_2.m_Q);
	14	register_subalias("1", m_1.m_i[0]);
	15	register_subalias("2", m_1.m_i[1]);
	16	register_subalias("3", m_2.m_i[0]);
	17	register_subalias("4", m_2.m_i[1]);
	18	register_subalias("5", m_2.m_i[2]);
	19	register_subalias("6", m_2.m_Q);
20	20
21		register_subalias("8", m_3.m_Q);
22		register_subalias("9", m_3.m_i[0]);
23		register_subalias("10", m_3.m_i[1]);
24		register_subalias("11", m_3.m_i[2]);
	21	register_subalias("8", m_3.m_Q);
	22	register_subalias("9", m_3.m_i[0]);
	23	register_subalias("10", m_3.m_i[1]);
	24	register_subalias("11", m_3.m_i[2]);
25	25
26		register_subalias("12", m_1.m_Q);
27		register_subalias("13", m_1.m_i[2]);
	26	register_subalias("12", m_1.m_Q);
	27	register_subalias("13", m_1.m_i[2]);
28	28	}
29	29
30	30	NETLIB_UPDATE(7427_dip)
31	31	{
32		/* only called during startup */
33		m_1.update_dev();
34		m_2.update_dev();
35		m_3.update_dev();
	32	/* only called during startup */
	33	m_1.update_dev();
	34	m_2.update_dev();
	35	m_3.update_dev();
36	36	}
37	37
38	38	NETLIB_RESET(7427_dip)
39	39	{
40		m_1.do_reset();
41		m_2.do_reset();
42		m_3.do_reset();
	40	m_1.do_reset();
	41	m_2.do_reset();
	42	m_3.do_reset();
43	43	}
44

trunk/src/emu/netlist/devices/nld_7404.h
r29404	r29405
43	43	NET_CONNECT(_name, A, _A)
44	44
45	45	#define TTL_7404_DIP(_name) \
46		NET_REGISTER_DEV(7402_dip, _name)
	46	NET_REGISTER_DEV(7402_dip, _name)
47	47
48	48	NETLIB_DEVICE(7404_dip,
49	49
50		NETLIB_NAME(7404) m_1;
51		NETLIB_NAME(7404) m_2;
52		NETLIB_NAME(7404) m_3;
53		NETLIB_NAME(7404) m_4;
54		NETLIB_NAME(7404) m_5;
55		NETLIB_NAME(7404) m_6;
	50	NETLIB_NAME(7404) m_1;
	51	NETLIB_NAME(7404) m_2;
	52	NETLIB_NAME(7404) m_3;
	53	NETLIB_NAME(7404) m_4;
	54	NETLIB_NAME(7404) m_5;
	55	NETLIB_NAME(7404) m_6;
56	56	);
57	57	#endif /* NLD_7404_H_ */

trunk/src/emu/netlist/devices/nld_legacy.c
r29404	r29405
16	16
17	17	NETLIB_RESET(nicRSFF)
18	18	{
19		m_Q.initial(0);
20		m_QQ.initial(1);
	19	m_Q.initial(0);
	20	m_QQ.initial(1);
21	21	}
22	22
23	23	NETLIB_UPDATE(nicRSFF)

trunk/src/emu/netlist/devices/nld_7483.c
r29404	r29405
28	28
29	29	NETLIB_RESET(7483)
30	30	{
31		m_lastr = 0;
	31	m_lastr = 0;
32	32	}
33	33
34	34	NETLIB_UPDATE(7483)
r29404	r29405
51	51
52	52	NETLIB_START(7483_dip)
53	53	{
54		NETLIB_NAME(7483)::start();
55		register_subalias("1", m_A4);
56		register_subalias("2", m_S3);
57		register_subalias("3", m_A3);
58		register_subalias("4", m_B3);
59		// register_subalias("5", ); --> VCC
60		register_subalias("6", m_S2);
61		register_subalias("7", m_B2);
62		register_subalias("8", m_A2);
	54	NETLIB_NAME(7483)::start();
	55	register_subalias("1", m_A4);
	56	register_subalias("2", m_S3);
	57	register_subalias("3", m_A3);
	58	register_subalias("4", m_B3);
	59	// register_subalias("5", ); --> VCC
	60	register_subalias("6", m_S2);
	61	register_subalias("7", m_B2);
	62	register_subalias("8", m_A2);
63	63
64		register_subalias("9", m_S1);
65		register_subalias("10", m_A1);
66		register_subalias("11", m_B1);
67		// register_subalias("12", ); --> GND
68		register_subalias("13", m_C0);
69		register_subalias("14", m_C4);
70		register_subalias("15", m_S4);
71		register_subalias("16", m_B4);
	64	register_subalias("9", m_S1);
	65	register_subalias("10", m_A1);
	66	register_subalias("11", m_B1);
	67	// register_subalias("12", ); --> GND
	68	register_subalias("13", m_C0);
	69	register_subalias("14", m_C4);
	70	register_subalias("15", m_S4);
	71	register_subalias("16", m_B4);
72	72
73	73	}
74	74
75	75	NETLIB_UPDATE(7483_dip)
76	76	{
77		NETLIB_NAME(7483)::update();
	77	NETLIB_NAME(7483)::update();
78	78	}
79	79
80	80	NETLIB_RESET(7483_dip)
81	81	{
82		NETLIB_NAME(7483)::reset();
	82	NETLIB_NAME(7483)::reset();
83	83	}

trunk/src/emu/netlist/devices/nld_7425.h
r29404	r29405
49	49	NETLIB_SIGNAL(7425, 4, 1, 0);
50	50
51	51	#define TTL_7425_DIP(_name) \
52		NET_REGISTER_DEV(7425_dip, _name)
	52	NET_REGISTER_DEV(7425_dip, _name)
53	53
54	54	NETLIB_DEVICE(7425_dip,
55	55
56		NETLIB_NAME(7425) m_1;
57		NETLIB_NAME(7425) m_2;
	56	NETLIB_NAME(7425) m_1;
	57	NETLIB_NAME(7425) m_2;
58	58	);
59	59	#endif /* NLD_7425_H_ */

trunk/src/emu/netlist/devices/nld_7448.c
r29404	r29405
9	9
10	10	NETLIB_START(7448)
11	11	{
12		register_sub(sub, "sub");
	12	register_sub(sub, "sub");
13	13
14		register_subalias("A", sub.m_A);
15		register_subalias("B", sub.m_B);
16		register_subalias("C", sub.m_C);
17		register_subalias("D", sub.m_D);
18		register_input("LTQ", m_LTQ);
19		register_input("BIQ", m_BIQ);
20		register_subalias("RBIQ",sub.m_RBIQ);
	14	register_subalias("A", sub.m_A);
	15	register_subalias("B", sub.m_B);
	16	register_subalias("C", sub.m_C);
	17	register_subalias("D", sub.m_D);
	18	register_input("LTQ", m_LTQ);
	19	register_input("BIQ", m_BIQ);
	20	register_subalias("RBIQ",sub.m_RBIQ);
21	21
22		register_subalias("a", sub.m_a);
23		register_subalias("b", sub.m_b);
24		register_subalias("c", sub.m_c);
25		register_subalias("d", sub.m_d);
26		register_subalias("e", sub.m_e);
27		register_subalias("f", sub.m_f);
28		register_subalias("g", sub.m_g);
	22	register_subalias("a", sub.m_a);
	23	register_subalias("b", sub.m_b);
	24	register_subalias("c", sub.m_c);
	25	register_subalias("d", sub.m_d);
	26	register_subalias("e", sub.m_e);
	27	register_subalias("f", sub.m_f);
	28	register_subalias("g", sub.m_g);
29	29	}
30	30
31	31	NETLIB_RESET(7448)
32	32	{
33		sub.do_reset();
	33	sub.do_reset();
34	34	}
35	35
36	36	NETLIB_UPDATE(7448)
37	37	{
38		if (INPLOGIC(m_BIQ) && !INPLOGIC(m_LTQ))
39		{
40		sub.update_outputs(8);
41		}
42		else if (!INPLOGIC(m_BIQ))
43		{
44		sub.update_outputs(15);
45		}
	38	if (INPLOGIC(m_BIQ) && !INPLOGIC(m_LTQ))
	39	{
	40	sub.update_outputs(8);
	41	}
	42	else if (!INPLOGIC(m_BIQ))
	43	{
	44	sub.update_outputs(15);
	45	}
46	46
47		if (!INPLOGIC(m_BIQ) \|\| (INPLOGIC(m_BIQ) && !INPLOGIC(m_LTQ)))
48		{
49		sub.m_A.inactivate();
50		sub.m_B.inactivate();
51		sub.m_C.inactivate();
52		sub.m_D.inactivate();
53		sub.m_RBIQ.inactivate();
54		} else {
55		sub.m_RBIQ.activate();
56		sub.m_D.activate();
57		sub.m_C.activate();
58		sub.m_B.activate();
59		sub.m_A.activate();
60		sub.update();
61		}
	47	if (!INPLOGIC(m_BIQ) \|\| (INPLOGIC(m_BIQ) && !INPLOGIC(m_LTQ)))
	48	{
	49	sub.m_A.inactivate();
	50	sub.m_B.inactivate();
	51	sub.m_C.inactivate();
	52	sub.m_D.inactivate();
	53	sub.m_RBIQ.inactivate();
	54	} else {
	55	sub.m_RBIQ.activate();
	56	sub.m_D.activate();
	57	sub.m_C.activate();
	58	sub.m_B.activate();
	59	sub.m_A.activate();
	60	sub.update();
	61	}
62	62
63	63	}
64	64
65	65	NETLIB_START(7448_sub)
66	66	{
67		register_input("A0", m_A);
68		register_input("A1", m_B);
69		register_input("A2", m_C);
70		register_input("A3", m_D);
71		register_input("RBIQ", m_RBIQ);
	67	register_input("A0", m_A);
	68	register_input("A1", m_B);
	69	register_input("A2", m_C);
	70	register_input("A3", m_D);
	71	register_input("RBIQ", m_RBIQ);
72	72
73		register_output("a", m_a);
74		register_output("b", m_b);
75		register_output("c", m_c);
76		register_output("d", m_d);
77		register_output("e", m_e);
78		register_output("f", m_f);
79		register_output("g", m_g);
	73	register_output("a", m_a);
	74	register_output("b", m_b);
	75	register_output("c", m_c);
	76	register_output("d", m_d);
	77	register_output("e", m_e);
	78	register_output("f", m_f);
	79	register_output("g", m_g);
80	80
81		save(NAME(m_state));
	81	save(NAME(m_state));
82	82	}
83	83
84	84	NETLIB_RESET(7448_sub)
85	85	{
86		m_state = 0;
	86	m_state = 0;
87	87	}
88	88
89	89	NETLIB_UPDATE(7448_sub)
90	90	{
91		UINT8 v;
	91	UINT8 v;
92	92
93		v = (INPLOGIC(m_A) << 0) \| (INPLOGIC(m_B) << 1) \| (INPLOGIC(m_C) << 2) \| (INPLOGIC(m_D) << 3);
94		if ((!INPLOGIC(m_RBIQ) && (v==0)))
95		v = 15;
96		update_outputs(v);
	93	v = (INPLOGIC(m_A) << 0) \| (INPLOGIC(m_B) << 1) \| (INPLOGIC(m_C) << 2) \| (INPLOGIC(m_D) << 3);
	94	if ((!INPLOGIC(m_RBIQ) && (v==0)))
	95	v = 15;
	96	update_outputs(v);
97	97	}
98	98
99	99	NETLIB_FUNC_VOID(7448_sub, update_outputs, (UINT8 v))
100	100	{
101		assert(v<16);
102		if (v != m_state)
103		{
104		// max transfer time is 100 NS */
	101	assert(v<16);
	102	if (v != m_state)
	103	{
	104	// max transfer time is 100 NS */
105	105
106		OUTLOGIC(m_a, tab7448[v][0], NLTIME_FROM_NS(100));
107		OUTLOGIC(m_b, tab7448[v][1], NLTIME_FROM_NS(100));
108		OUTLOGIC(m_c, tab7448[v][2], NLTIME_FROM_NS(100));
109		OUTLOGIC(m_d, tab7448[v][3], NLTIME_FROM_NS(100));
110		OUTLOGIC(m_e, tab7448[v][4], NLTIME_FROM_NS(100));
111		OUTLOGIC(m_f, tab7448[v][5], NLTIME_FROM_NS(100));
112		OUTLOGIC(m_g, tab7448[v][6], NLTIME_FROM_NS(100));
113		m_state = v;
114		}
	106	OUTLOGIC(m_a, tab7448[v][0], NLTIME_FROM_NS(100));
	107	OUTLOGIC(m_b, tab7448[v][1], NLTIME_FROM_NS(100));
	108	OUTLOGIC(m_c, tab7448[v][2], NLTIME_FROM_NS(100));
	109	OUTLOGIC(m_d, tab7448[v][3], NLTIME_FROM_NS(100));
	110	OUTLOGIC(m_e, tab7448[v][4], NLTIME_FROM_NS(100));
	111	OUTLOGIC(m_f, tab7448[v][5], NLTIME_FROM_NS(100));
	112	OUTLOGIC(m_g, tab7448[v][6], NLTIME_FROM_NS(100));
	113	m_state = v;
	114	}
115	115	}
116	116
117	117	const UINT8 NETLIB_NAME(7448_sub)::tab7448[16][7] =
118	118	{
119		{ 1, 1, 1, 1, 1, 1, 0 }, /* 00 - not blanked ! */
120		{ 0, 1, 1, 0, 0, 0, 0 }, /* 01 */
121		{ 1, 1, 0, 1, 1, 0, 1 }, /* 02 */
122		{ 1, 1, 1, 1, 0, 0, 1 }, /* 03 */
123		{ 0, 1, 1, 0, 0, 1, 1 }, /* 04 */
124		{ 1, 0, 1, 1, 0, 1, 1 }, /* 05 */
125		{ 0, 0, 1, 1, 1, 1, 1 }, /* 06 */
126		{ 1, 1, 1, 0, 0, 0, 0 }, /* 07 */
127		{ 1, 1, 1, 1, 1, 1, 1 }, /* 08 */
128		{ 1, 1, 1, 0, 0, 1, 1 }, /* 09 */
129		{ 0, 0, 0, 1, 1, 0, 1 }, /* 10 */
130		{ 0, 0, 1, 1, 0, 0, 1 }, /* 11 */
131		{ 0, 1, 0, 0, 0, 1, 1 }, /* 12 */
132		{ 1, 0, 0, 1, 0, 1, 1 }, /* 13 */
133		{ 0, 0, 0, 1, 1, 1, 1 }, /* 14 */
134		{ 0, 0, 0, 0, 0, 0, 0 }, /* 15 */
	119	{ 1, 1, 1, 1, 1, 1, 0 }, /* 00 - not blanked ! */
	120	{ 0, 1, 1, 0, 0, 0, 0 }, /* 01 */
	121	{ 1, 1, 0, 1, 1, 0, 1 }, /* 02 */
	122	{ 1, 1, 1, 1, 0, 0, 1 }, /* 03 */
	123	{ 0, 1, 1, 0, 0, 1, 1 }, /* 04 */
	124	{ 1, 0, 1, 1, 0, 1, 1 }, /* 05 */
	125	{ 0, 0, 1, 1, 1, 1, 1 }, /* 06 */
	126	{ 1, 1, 1, 0, 0, 0, 0 }, /* 07 */
	127	{ 1, 1, 1, 1, 1, 1, 1 }, /* 08 */
	128	{ 1, 1, 1, 0, 0, 1, 1 }, /* 09 */
	129	{ 0, 0, 0, 1, 1, 0, 1 }, /* 10 */
	130	{ 0, 0, 1, 1, 0, 0, 1 }, /* 11 */
	131	{ 0, 1, 0, 0, 0, 1, 1 }, /* 12 */
	132	{ 1, 0, 0, 1, 0, 1, 1 }, /* 13 */
	133	{ 0, 0, 0, 1, 1, 1, 1 }, /* 14 */
	134	{ 0, 0, 0, 0, 0, 0, 0 }, /* 15 */
135	135	};
136	136
137	137
138	138	NETLIB_START(7448_dip)
139	139	{
140		NETLIB_NAME(7448)::start();
	140	NETLIB_NAME(7448)::start();
141	141
142		register_subalias("1", sub.m_B);
143		register_subalias("2", sub.m_C);
144		register_subalias("3", m_LTQ);
145		register_subalias("4", m_BIQ);
146		register_subalias("5",sub.m_RBIQ);
147		register_subalias("6", sub.m_D);
148		register_subalias("7", sub.m_A);
	142	register_subalias("1", sub.m_B);
	143	register_subalias("2", sub.m_C);
	144	register_subalias("3", m_LTQ);
	145	register_subalias("4", m_BIQ);
	146	register_subalias("5",sub.m_RBIQ);
	147	register_subalias("6", sub.m_D);
	148	register_subalias("7", sub.m_A);
149	149
150		register_subalias("9", sub.m_e);
151		register_subalias("10", sub.m_d);
152		register_subalias("11", sub.m_c);
153		register_subalias("12", sub.m_b);
154		register_subalias("13", sub.m_a);
155		register_subalias("14", sub.m_g);
156		register_subalias("15", sub.m_f);
	150	register_subalias("9", sub.m_e);
	151	register_subalias("10", sub.m_d);
	152	register_subalias("11", sub.m_c);
	153	register_subalias("12", sub.m_b);
	154	register_subalias("13", sub.m_a);
	155	register_subalias("14", sub.m_g);
	156	register_subalias("15", sub.m_f);
157	157	}
158	158
159	159	NETLIB_UPDATE(7448_dip)
160	160	{
161		NETLIB_NAME(7448)::update();
	161	NETLIB_NAME(7448)::update();
162	162	}
163	163
164	164	NETLIB_RESET(7448_dip)
165	165	{
166		NETLIB_NAME(7448)::reset();
	166	NETLIB_NAME(7448)::reset();
167	167	}
168

trunk/src/emu/netlist/devices/nld_7486.c
r29404	r29405
25	25
26	26	NETLIB_START(7486_dip)
27	27	{
28		register_sub(m_1, "1");
29		register_sub(m_2, "2");
30		register_sub(m_3, "3");
31		register_sub(m_4, "4");
	28	register_sub(m_1, "1");
	29	register_sub(m_2, "2");
	30	register_sub(m_3, "3");
	31	register_sub(m_4, "4");
32	32
33		register_subalias("1", m_1.m_A);
34		register_subalias("2", m_1.m_B);
35		register_subalias("3", m_1.m_Q);
	33	register_subalias("1", m_1.m_A);
	34	register_subalias("2", m_1.m_B);
	35	register_subalias("3", m_1.m_Q);
36	36
37		register_subalias("4", m_2.m_A);
38		register_subalias("5", m_2.m_B);
39		register_subalias("6", m_2.m_Q);
	37	register_subalias("4", m_2.m_A);
	38	register_subalias("5", m_2.m_B);
	39	register_subalias("6", m_2.m_Q);
40	40
41		register_subalias("9", m_3.m_A);
42		register_subalias("10", m_3.m_B);
43		register_subalias("8", m_3.m_Q);
	41	register_subalias("9", m_3.m_A);
	42	register_subalias("10", m_3.m_B);
	43	register_subalias("8", m_3.m_Q);
44	44
45		register_subalias("12", m_4.m_A);
46		register_subalias("13", m_4.m_B);
47		register_subalias("11", m_4.m_Q);
	45	register_subalias("12", m_4.m_A);
	46	register_subalias("13", m_4.m_B);
	47	register_subalias("11", m_4.m_Q);
48	48	}
49	49
50	50	NETLIB_UPDATE(7486_dip)
51	51	{
52		/* only called during startup */
53		m_1.update_dev();
54		m_2.update_dev();
55		m_3.update_dev();
56		m_4.update_dev();
	52	/* only called during startup */
	53	m_1.update_dev();
	54	m_2.update_dev();
	55	m_3.update_dev();
	56	m_4.update_dev();
57	57	}
58	58
59	59	NETLIB_RESET(7486_dip)
60	60	{
61		m_1.do_reset();
62		m_2.do_reset();
63		m_3.do_reset();
64		m_4.do_reset();
	61	m_1.do_reset();
	62	m_2.do_reset();
	63	m_3.do_reset();
	64	m_4.do_reset();
65	65	}
66

trunk/src/emu/netlist/devices/nld_7427.h
r29404	r29405
43	43	NETLIB_SIGNAL(7427, 3, 1, 0);
44	44
45	45	#define TTL_7427_DIP(_name) \
46		NET_REGISTER_DEV(7427_dip, _name)
	46	NET_REGISTER_DEV(7427_dip, _name)
47	47
48	48	NETLIB_DEVICE(7427_dip,
49	49
50		NETLIB_NAME(7427) m_1;
51		NETLIB_NAME(7427) m_2;
52		NETLIB_NAME(7427) m_3;
	50	NETLIB_NAME(7427) m_1;
	51	NETLIB_NAME(7427) m_2;
	52	NETLIB_NAME(7427) m_3;
53	53	);
54	54	#endif /* NLD_7427_H_ */

trunk/src/emu/netlist/devices/nld_7483.h
r29404	r29405
42	42	NET_CONNECT(_name, C0, _CI)
43	43
44	44	#define TTL_7483_DIP(_name) \
45		NET_REGISTER_DEV(7483_dip, _name)
	45	NET_REGISTER_DEV(7483_dip, _name)
46	46
47	47	NETLIB_DEVICE(7483,
48	48	netlist_ttl_input_t m_C0;

trunk/src/emu/netlist/devices/nld_7448.h
r29404	r29405
27	27	#include "../nl_base.h"
28	28
29	29	#define TTL_7448(_name, _A0, _A1, _A2, _A3, _LTQ, _BIQ, _RBIQ) \
30		NET_REGISTER_DEV(7448, _name) \
31		NET_CONNECT(_name, A, _A0) \
32		NET_CONNECT(_name, B, _A1) \
33		NET_CONNECT(_name, C, _A2) \
34		NET_CONNECT(_name, D, _A3) \
35		NET_CONNECT(_name, LTQ, _LTQ) \
36		NET_CONNECT(_name, BIQ, _BIQ) \
37		NET_CONNECT(_name, RBIQ, _RBIQ)
	30	NET_REGISTER_DEV(7448, _name) \
	31	NET_CONNECT(_name, A, _A0) \
	32	NET_CONNECT(_name, B, _A1) \
	33	NET_CONNECT(_name, C, _A2) \
	34	NET_CONNECT(_name, D, _A3) \
	35	NET_CONNECT(_name, LTQ, _LTQ) \
	36	NET_CONNECT(_name, BIQ, _BIQ) \
	37	NET_CONNECT(_name, RBIQ, _RBIQ)
38	38
39	39	#define TTL_7448_DIP(_name) \
40		NET_REGISTER_DEV(7448_dip, _name)
	40	NET_REGISTER_DEV(7448_dip, _name)
41	41
42	42	NETLIB_SUBDEVICE(7448_sub,
43		ATTR_HOT void update_outputs(UINT8 v);
44		static const UINT8 tab7448[16][7];
	43	ATTR_HOT void update_outputs(UINT8 v);
	44	static const UINT8 tab7448[16][7];
45	45
46		netlist_ttl_input_t m_A;
47		netlist_ttl_input_t m_B;
48		netlist_ttl_input_t m_C;
49		netlist_ttl_input_t m_D;
50		netlist_ttl_input_t m_RBIQ;
	46	netlist_ttl_input_t m_A;
	47	netlist_ttl_input_t m_B;
	48	netlist_ttl_input_t m_C;
	49	netlist_ttl_input_t m_D;
	50	netlist_ttl_input_t m_RBIQ;
51	51
52		UINT8 m_state;
	52	UINT8 m_state;
53	53
54		netlist_ttl_output_t m_a;
55		netlist_ttl_output_t m_b;
56		netlist_ttl_output_t m_c;
57		netlist_ttl_output_t m_d;
58		netlist_ttl_output_t m_e;
59		netlist_ttl_output_t m_f;
60		netlist_ttl_output_t m_g;
	54	netlist_ttl_output_t m_a;
	55	netlist_ttl_output_t m_b;
	56	netlist_ttl_output_t m_c;
	57	netlist_ttl_output_t m_d;
	58	netlist_ttl_output_t m_e;
	59	netlist_ttl_output_t m_f;
	60	netlist_ttl_output_t m_g;
61	61	);
62	62
63	63	NETLIB_DEVICE(7448,
64	64	public:
65		NETLIB_NAME(7448_sub) sub;
	65	NETLIB_NAME(7448_sub) sub;
66	66
67		netlist_ttl_input_t m_LTQ;
68		netlist_ttl_input_t m_BIQ;
	67	netlist_ttl_input_t m_LTQ;
	68	netlist_ttl_input_t m_BIQ;
69	69	);
70	70
71	71	NETLIB_DEVICE_DERIVED(7448_dip, 7448,

trunk/src/emu/netlist/devices/nld_7486.h
r29404	r29405
47	47	);
48	48
49	49	#define TTL_7486_DIP(_name) \
50		NET_REGISTER_DEV(7486_dip, _name)
	50	NET_REGISTER_DEV(7486_dip, _name)
51	51
52	52	NETLIB_DEVICE(7486_dip,
53	53
54		NETLIB_NAME(7486) m_1;
55		NETLIB_NAME(7486) m_2;
56		NETLIB_NAME(7486) m_3;
57		NETLIB_NAME(7486) m_4;
	54	NETLIB_NAME(7486) m_1;
	55	NETLIB_NAME(7486) m_2;
	56	NETLIB_NAME(7486) m_3;
	57	NETLIB_NAME(7486) m_4;
58	58	);
59	59
60	60	#endif /* NLD_7486_H_ */

trunk/src/emu/netlist/devices/nld_74153.c
r29404	r29405
12	12
13	13	NETLIB_START(74153sub)
14	14	{
15		register_input("C0", m_C[0]);
16		register_input("C1", m_C[1]);
17		register_input("C2", m_C[2]);
18		register_input("C3", m_C[3]);
19		register_input("G", m_G);
	15	register_input("C0", m_C[0]);
	16	register_input("C1", m_C[1]);
	17	register_input("C2", m_C[2]);
	18	register_input("C3", m_C[3]);
	19	register_input("G", m_G);
20	20
21		register_output("AY", m_Y); //FIXME: Change netlists
	21	register_output("AY", m_Y); //FIXME: Change netlists
22	22
23		m_chan = 0;
	23	m_chan = 0;
24	24
25		save(NAME(m_chan));
	25	save(NAME(m_chan));
26	26	}
27	27
28	28	NETLIB_RESET(74153sub)
29	29	{
30		m_chan = 0;
	30	m_chan = 0;
31	31	}
32	32
33	33	NETLIB_UPDATE(74153sub)
34	34	{
35		const netlist_time delay[2] = { NLTIME_FROM_NS(23), NLTIME_FROM_NS(18) };
36		if (!INPLOGIC(m_G))
37		{
38		UINT8 t = INPLOGIC(m_C[m_chan]);
39		OUTLOGIC(m_Y, t, delay[t] );
40		}
41		else
42		{
43		OUTLOGIC(m_Y, 0, delay[0]);
44		}
	35	const netlist_time delay[2] = { NLTIME_FROM_NS(23), NLTIME_FROM_NS(18) };
	36	if (!INPLOGIC(m_G))
	37	{
	38	UINT8 t = INPLOGIC(m_C[m_chan]);
	39	OUTLOGIC(m_Y, t, delay[t] );
	40	}
	41	else
	42	{
	43	OUTLOGIC(m_Y, 0, delay[0]);
	44	}
45	45	}
46	46
47	47
48	48	NETLIB_START(74153)
49	49	{
50		register_sub(m_sub, "SUB");
	50	register_sub(m_sub, "SUB");
51	51
52	52	register_subalias("C0", m_sub.m_C[0]);
53	53	register_subalias("C1", m_sub.m_C[1]);
r29404	r29405
68	68
69	69	NETLIB_UPDATE(74153)
70	70	{
71		m_sub.m_chan = (INPLOGIC(m_A) \| (INPLOGIC(m_B)<<1));
72		m_sub.update();
	71	m_sub.m_chan = (INPLOGIC(m_A) \| (INPLOGIC(m_B)<<1));
	72	m_sub.update();
73	73	}
74	74
75	75
76	76	NETLIB_START(74153_dip)
77	77	{
78		register_sub(m_1, "1");
79		register_sub(m_2, "2");
	78	register_sub(m_1, "1");
	79	register_sub(m_2, "2");
80	80
81		register_subalias("1", m_1.m_G);
82		register_input("2", m_B); // m_2.m_B
83		register_subalias("3", m_1.m_C[3]);
84		register_subalias("4", m_1.m_C[2]);
85		register_subalias("5", m_1.m_C[1]);
86		register_subalias("6", m_1.m_C[0]);
87		register_subalias("7", m_1.m_Y);
	81	register_subalias("1", m_1.m_G);
	82	register_input("2", m_B); // m_2.m_B
	83	register_subalias("3", m_1.m_C[3]);
	84	register_subalias("4", m_1.m_C[2]);
	85	register_subalias("5", m_1.m_C[1]);
	86	register_subalias("6", m_1.m_C[0]);
	87	register_subalias("7", m_1.m_Y);
88	88
89		register_subalias("9", m_2.m_Y);
90		register_subalias("10", m_2.m_C[0]);
91		register_subalias("11", m_2.m_C[1]);
92		register_subalias("12", m_2.m_C[2]);
93		register_subalias("13", m_2.m_C[3]);
	89	register_subalias("9", m_2.m_Y);
	90	register_subalias("10", m_2.m_C[0]);
	91	register_subalias("11", m_2.m_C[1]);
	92	register_subalias("12", m_2.m_C[2]);
	93	register_subalias("13", m_2.m_C[3]);
94	94
95		register_input("14", m_A); // m_2.m_B
96		register_subalias("15", m_2.m_G);
	95	register_input("14", m_A); // m_2.m_B
	96	register_subalias("15", m_2.m_G);
97	97	}
98	98
99	99	NETLIB_UPDATE(74153_dip)
100	100	{
101		m_2.m_chan = m_1.m_chan = (INPLOGIC(m_A) \| (INPLOGIC(m_B)<<1));
102		m_1.update();
103		m_2.update();
	101	m_2.m_chan = m_1.m_chan = (INPLOGIC(m_A) \| (INPLOGIC(m_B)<<1));
	102	m_1.update();
	103	m_2.update();
104	104	}
105	105
106	106	NETLIB_RESET(74153_dip)
107	107	{
108		m_1.do_reset();
109		m_2.do_reset();
	108	m_1.do_reset();
	109	m_2.do_reset();
110	110	}
111

trunk/src/emu/netlist/devices/nld_system.c
r29404	r29405
51	51
52	52	NETLIB_UPDATE(ttl_input)
53	53	{
54		OUTLOGIC(m_Q, m_IN.Value() & 1, netlist_time::from_nsec(1));
	54	OUTLOGIC(m_Q, m_IN.Value() & 1, netlist_time::from_nsec(1));
55	55	}
56	56
57	57	NETLIB_UPDATE_PARAM(ttl_input)
58	58	{
59		update();
	59	update();
60	60	}
61	61
62	62	// ----------------------------------------------------------------------------------------
r29404	r29405
66	66	NETLIB_START(analog_input)
67	67	{
68	68	register_output("Q", m_Q);
69		register_param("IN", m_IN, 0.0);
	69	register_param("IN", m_IN, 0.0);
70	70	}
71	71
72	72	NETLIB_RESET(analog_input)
r29404	r29405
75	75
76	76	NETLIB_UPDATE(analog_input)
77	77	{
78		OUTANALOG(m_Q, m_IN.Value(), NLTIME_IMMEDIATE);
	78	OUTANALOG(m_Q, m_IN.Value(), NLTIME_IMMEDIATE);
79	79	}
80	80
81	81	NETLIB_UPDATE_PARAM(analog_input)
82	82	{
83		update();
	83	update();
84	84	}

trunk/src/emu/netlist/devices/nld_74153.h
r29404	r29405
58	58	NET_CONNECT(_name, G, _G)
59	59
60	60	#define TTL_74153_DIP(_name) \
61		NET_REGISTER_DEV(74153_dip, _name)
	61	NET_REGISTER_DEV(74153_dip, _name)
62	62
63	63	NETLIB_SUBDEVICE(74153sub,
64		netlist_ttl_input_t m_C[4];
65		netlist_ttl_input_t m_G;
	64	netlist_ttl_input_t m_C[4];
	65	netlist_ttl_input_t m_G;
66	66
67		netlist_ttl_output_t m_Y;
	67	netlist_ttl_output_t m_Y;
68	68
69		int m_chan;
	69	int m_chan;
70	70	);
71	71
72	72	NETLIB_DEVICE(74153,
73	73	public:
74		NETLIB_NAME(74153sub) m_sub;
	74	NETLIB_NAME(74153sub) m_sub;
75	75	netlist_ttl_input_t m_A;
76	76	netlist_ttl_input_t m_B;
77	77	);
78	78
79	79	NETLIB_DEVICE(74153_dip,
80	80
81		NETLIB_NAME(74153sub) m_1;
82		NETLIB_NAME(74153sub) m_2;
83		netlist_ttl_input_t m_A;
84		netlist_ttl_input_t m_B;
	81	NETLIB_NAME(74153sub) m_1;
	82	NETLIB_NAME(74153sub) m_2;
	83	netlist_ttl_input_t m_A;
	84	netlist_ttl_input_t m_B;
85	85	);
86	86
87	87	#endif /* NLD_74153_H_ */

trunk/src/emu/netlist/devices/nld_system.h
r29404	r29405
27	27
28	28	#define MAINCLOCK(_name, _freq) \
29	29	NET_REGISTER_DEV(mainclock, _name) \
30		PARAM(_name.FREQ, _freq)
	30	PARAM(_name.FREQ, _freq)
31	31
32	32	#define CLOCK(_name, _freq) \
33	33	NET_REGISTER_DEV(clock, _name) \
34		PARAM(_name.FREQ, _freq)
	34	PARAM(_name.FREQ, _freq)
35	35
36	36	#define GNDA() \
37		NET_REGISTER_DEV(gnd, GND)
	37	NET_REGISTER_DEV(gnd, GND)
38	38
39	39	// ----------------------------------------------------------------------------------------
40	40	// mainclock
r29404	r29405
47	47	netlist_param_double_t m_freq;
48	48	netlist_time m_inc;
49	49
50		ATTR_HOT inline static void mc_update(netlist_net_t &net);
	50	ATTR_HOT inline static void mc_update(netlist_net_t &net);
51	51	);
52	52
53	53	// ----------------------------------------------------------------------------------------
r29404	r29405
76	76	NETLIB_DEVICE_WITH_PARAMS(analog_input,
77	77	netlist_analog_output_t m_Q;
78	78
79		netlist_param_double_t m_IN;
	79	netlist_param_double_t m_IN;
80	80	);
81	81
82	82	// ----------------------------------------------------------------------------------------
r29404	r29405
86	86	class nld_gnd : public netlist_device_t
87	87	{
88	88	public:
89		ATTR_COLD nld_gnd()
90		: netlist_device_t(GND) { }
	89	ATTR_COLD nld_gnd()
	90	: netlist_device_t(GND) { }
91	91
92		ATTR_COLD virtual ~nld_gnd() {}
	92	ATTR_COLD virtual ~nld_gnd() {}
93	93
94	94	protected:
95	95
96		ATTR_COLD void start()
97		{
98		register_output("Q", m_Q);
99		}
	96	ATTR_COLD void start()
	97	{
	98	register_output("Q", m_Q);
	99	}
100	100
101		ATTR_COLD void reset()
102		{
103		}
	101	ATTR_COLD void reset()
	102	{
	103	}
104	104
105		ATTR_HOT ATTR_ALIGN void update()
106		{
107		OUTANALOG(m_Q, 0.0, NLTIME_IMMEDIATE);
108		}
	105	ATTR_HOT ATTR_ALIGN void update()
	106	{
	107	OUTANALOG(m_Q, 0.0, NLTIME_IMMEDIATE);
	108	}
109	109
110	110	private:
111		netlist_analog_output_t m_Q;
	111	netlist_analog_output_t m_Q;
112	112
113	113	};
114	114
r29404	r29405
120	120	class nld_a_to_d_proxy : public netlist_device_t
121	121	{
122	122	public:
123		ATTR_COLD nld_a_to_d_proxy(netlist_input_t &in_proxied)
124		: netlist_device_t()
125		{
126		assert(in_proxied.family() == LOGIC);
127		m_I.m_family_desc = in_proxied.m_family_desc;
128		}
	123	ATTR_COLD nld_a_to_d_proxy(netlist_input_t &in_proxied)
	124	: netlist_device_t()
	125	{
	126	assert(in_proxied.family() == LOGIC);
	127	m_I.m_family_desc = in_proxied.m_family_desc;
	128	}
129	129
130		ATTR_COLD virtual ~nld_a_to_d_proxy() {}
	130	ATTR_COLD virtual ~nld_a_to_d_proxy() {}
131	131
132		netlist_analog_input_t m_I;
133		netlist_ttl_output_t m_Q;
	132	netlist_analog_input_t m_I;
	133	netlist_ttl_output_t m_Q;
134	134
135	135	protected:
136		ATTR_COLD void start()
137		{
138		register_input("I", m_I);
139		register_output("Q", m_Q);
140		}
	136	ATTR_COLD void start()
	137	{
	138	register_input("I", m_I);
	139	register_output("Q", m_Q);
	140	}
141	141
142		ATTR_COLD void reset()
143		{
144		}
	142	ATTR_COLD void reset()
	143	{
	144	}
145	145
146		ATTR_HOT ATTR_ALIGN void update()
147		{
148		if (m_I.Q_Analog() > m_I.m_family_desc->m_high_thresh_V)
149		OUTLOGIC(m_Q, 1, NLTIME_FROM_NS(1));
150		else if (m_I.Q_Analog() < m_I.m_family_desc->m_low_thresh_V)
151		OUTLOGIC(m_Q, 0, NLTIME_FROM_NS(1));
152		//else
153		// OUTLOGIC(m_Q, m_Q.net().last_Q(), NLTIME_FROM_NS(1));
154		}
	146	ATTR_HOT ATTR_ALIGN void update()
	147	{
	148	if (m_I.Q_Analog() > m_I.m_family_desc->m_high_thresh_V)
	149	OUTLOGIC(m_Q, 1, NLTIME_FROM_NS(1));
	150	else if (m_I.Q_Analog() < m_I.m_family_desc->m_low_thresh_V)
	151	OUTLOGIC(m_Q, 0, NLTIME_FROM_NS(1));
	152	//else
	153	// OUTLOGIC(m_Q, m_Q.net().last_Q(), NLTIME_FROM_NS(1));
	154	}
155	155
156	156	};
157	157
r29404	r29405
162	162	class nld_base_d_to_a_proxy : public netlist_device_t
163	163	{
164	164	public:
165		ATTR_COLD nld_base_d_to_a_proxy(netlist_output_t &out_proxied)
166		: netlist_device_t()
167		{
168		assert(out_proxied.family() == LOGIC);
169		m_family_desc = out_proxied.m_family_desc;
170		}
	165	ATTR_COLD nld_base_d_to_a_proxy(netlist_output_t &out_proxied)
	166	: netlist_device_t()
	167	{
	168	assert(out_proxied.family() == LOGIC);
	169	m_family_desc = out_proxied.m_family_desc;
	170	}
171	171
172		ATTR_COLD virtual ~nld_base_d_to_a_proxy() {}
	172	ATTR_COLD virtual ~nld_base_d_to_a_proxy() {}
173	173
174		ATTR_COLD virtual netlist_core_terminal_t &out() = 0;
	174	ATTR_COLD virtual netlist_core_terminal_t &out() = 0;
175	175
176		netlist_ttl_input_t m_I;
	176	netlist_ttl_input_t m_I;
177	177
178	178	protected:
179		ATTR_COLD void start()
180		{
181		register_input("I", m_I);
182		}
	179	ATTR_COLD void start()
	180	{
	181	register_input("I", m_I);
	182	}
183	183
184	184	private:
185	185	};
r29404	r29405
188	188	class nld_d_to_a_proxy : public nld_base_d_to_a_proxy
189	189	{
190	190	public:
191		ATTR_COLD nld_d_to_a_proxy(netlist_output_t &out_proxied)
192		: nld_base_d_to_a_proxy(out_proxied)
193		{
194		}
	191	ATTR_COLD nld_d_to_a_proxy(netlist_output_t &out_proxied)
	192	: nld_base_d_to_a_proxy(out_proxied)
	193	{
	194	}
195	195
196		ATTR_COLD virtual ~nld_d_to_a_proxy() {}
	196	ATTR_COLD virtual ~nld_d_to_a_proxy() {}
197	197
198	198	protected:
199		ATTR_COLD void start()
200		{
201		nld_base_d_to_a_proxy::start();
202		register_output("Q", m_Q);
203		}
	199	ATTR_COLD void start()
	200	{
	201	nld_base_d_to_a_proxy::start();
	202	register_output("Q", m_Q);
	203	}
204	204
205		ATTR_COLD void reset()
206		{
207		//m_Q.initial(0);
208		}
	205	ATTR_COLD void reset()
	206	{
	207	//m_Q.initial(0);
	208	}
209	209
210		ATTR_COLD virtual netlist_core_terminal_t &out()
211		{
212		return m_Q;
213		}
	210	ATTR_COLD virtual netlist_core_terminal_t &out()
	211	{
	212	return m_Q;
	213	}
214	214
215		ATTR_HOT ATTR_ALIGN void update()
216		{
217		OUTANALOG(m_Q, INPLOGIC(m_I) ? m_family_desc->m_high_V : m_family_desc->m_low_V, NLTIME_FROM_NS(1));
218		}
	215	ATTR_HOT ATTR_ALIGN void update()
	216	{
	217	OUTANALOG(m_Q, INPLOGIC(m_I) ? m_family_desc->m_high_V : m_family_desc->m_low_V, NLTIME_FROM_NS(1));
	218	}
219	219
220	220	private:
221		netlist_analog_output_t m_Q;
	221	netlist_analog_output_t m_Q;
222	222	};
223	223	#else
224	224	class nld_d_to_a_proxy : public nld_base_d_to_a_proxy
225	225	{
226	226	public:
227		ATTR_COLD nld_d_to_a_proxy(netlist_output_t &out_proxied)
228		: nld_base_d_to_a_proxy(out_proxied)
229		{
230		}
	227	ATTR_COLD nld_d_to_a_proxy(netlist_output_t &out_proxied)
	228	: nld_base_d_to_a_proxy(out_proxied)
	229	{
	230	}
231	231
232		ATTR_COLD virtual ~nld_d_to_a_proxy() {}
	232	ATTR_COLD virtual ~nld_d_to_a_proxy() {}
233	233
234	234	protected:
235		ATTR_COLD void start()
236		{
237		nld_base_d_to_a_proxy::start();
	235	ATTR_COLD void start()
	236	{
	237	nld_base_d_to_a_proxy::start();
238	238
239		register_sub(m_R, "R");
240		register_output("_Q", m_Q);
241		register_subalias("Q", m_R.m_N);
	239	register_sub(m_R, "R");
	240	register_output("_Q", m_Q);
	241	register_subalias("Q", m_R.m_N);
242	242
243		connect(m_R.m_P, m_Q);
	243	connect(m_R.m_P, m_Q);
244	244
245		//m_Q.initial(m_family_desc->m_low_V);
246		//m_R.set_R(m_family_desc->m_R_low);
247		}
	245	//m_Q.initial(m_family_desc->m_low_V);
	246	//m_R.set_R(m_family_desc->m_R_low);
	247	}
248	248
249		ATTR_COLD void reset()
250		{
251		//m_Q.initial(m_family_desc->m_low_V);
252		//m_R.set_R(m_family_desc->m_R_low);
253		m_R.do_reset();
254		}
	249	ATTR_COLD void reset()
	250	{
	251	//m_Q.initial(m_family_desc->m_low_V);
	252	//m_R.set_R(m_family_desc->m_R_low);
	253	m_R.do_reset();
	254	}
255	255
256		ATTR_COLD virtual netlist_core_terminal_t &out()
257		{
258		return m_R.m_N;
259		}
	256	ATTR_COLD virtual netlist_core_terminal_t &out()
	257	{
	258	return m_R.m_N;
	259	}
260	260
261		ATTR_HOT ATTR_ALIGN void update()
262		{
263		double R = INPLOGIC(m_I) ? m_family_desc->m_R_high : m_family_desc->m_R_low;
264		double V = INPLOGIC(m_I) ? m_family_desc->m_high_V : m_family_desc->m_low_V;
265		//printf("%f %f\n", R, V);
266		m_R.set_R(R);
267		OUTANALOG(m_Q, V, NLTIME_FROM_NS(0));
268		}
	261	ATTR_HOT ATTR_ALIGN void update()
	262	{
	263	double R = INPLOGIC(m_I) ? m_family_desc->m_R_high : m_family_desc->m_R_low;
	264	double V = INPLOGIC(m_I) ? m_family_desc->m_high_V : m_family_desc->m_low_V;
	265	//printf("%f %f\n", R, V);
	266	m_R.set_R(R);
	267	OUTANALOG(m_Q, V, NLTIME_FROM_NS(0));
	268	}
269	269
270	270	private:
271		netlist_analog_output_t m_Q;
272		nld_R_base m_R;
	271	netlist_analog_output_t m_Q;
	272	nld_R_base m_R;
273	273	};
274	274	#endif
275	275

trunk/src/emu/netlist/devices/nld_7410.c
r29404	r29405
7	7
8	8	NETLIB_START(7410_dip)
9	9	{
10		register_sub(m_1, "1");
11		register_sub(m_2, "2");
12		register_sub(m_3, "3");
	10	register_sub(m_1, "1");
	11	register_sub(m_2, "2");
	12	register_sub(m_3, "3");
13	13
14		register_subalias("1", m_1.m_i[0]);
15		register_subalias("2", m_1.m_i[1]);
16		register_subalias("3", m_2.m_i[0]);
17		register_subalias("4", m_2.m_i[1]);
18		register_subalias("5", m_2.m_i[2]);
19		register_subalias("6", m_2.m_Q);
	14	register_subalias("1", m_1.m_i[0]);
	15	register_subalias("2", m_1.m_i[1]);
	16	register_subalias("3", m_2.m_i[0]);
	17	register_subalias("4", m_2.m_i[1]);
	18	register_subalias("5", m_2.m_i[2]);
	19	register_subalias("6", m_2.m_Q);
20	20
21		register_subalias("8", m_3.m_Q);
22		register_subalias("9", m_3.m_i[0]);
23		register_subalias("10", m_3.m_i[1]);
24		register_subalias("11", m_3.m_i[2]);
	21	register_subalias("8", m_3.m_Q);
	22	register_subalias("9", m_3.m_i[0]);
	23	register_subalias("10", m_3.m_i[1]);
	24	register_subalias("11", m_3.m_i[2]);
25	25
26		register_subalias("12", m_1.m_Q);
27		register_subalias("13", m_1.m_i[2]);
	26	register_subalias("12", m_1.m_Q);
	27	register_subalias("13", m_1.m_i[2]);
28	28	}
29	29
30	30	NETLIB_UPDATE(7410_dip)
31	31	{
32		/* only called during startup */
33		m_1.update_dev();
34		m_2.update_dev();
35		m_3.update_dev();
	32	/* only called during startup */
	33	m_1.update_dev();
	34	m_2.update_dev();
	35	m_3.update_dev();
36	36	}
37	37
38	38	NETLIB_RESET(7410_dip)
39	39	{
40		m_1.do_reset();
41		m_2.do_reset();
42		m_3.do_reset();
	40	m_1.do_reset();
	41	m_2.do_reset();
	42	m_3.do_reset();
43	43	}
44

trunk/src/emu/netlist/devices/nld_7430.c
r29404	r29405
7	7
8	8	NETLIB_START(7430_dip)
9	9	{
10		register_sub(m_1, "1");
	10	register_sub(m_1, "1");
11	11
12		register_subalias("1", m_1.m_i[0]);
13		register_subalias("2", m_1.m_i[1]);
14		register_subalias("3", m_1.m_i[2]);
15		register_subalias("4", m_1.m_i[3]);
16		register_subalias("5", m_1.m_i[4]);
17		register_subalias("6", m_1.m_i[5]);
	12	register_subalias("1", m_1.m_i[0]);
	13	register_subalias("2", m_1.m_i[1]);
	14	register_subalias("3", m_1.m_i[2]);
	15	register_subalias("4", m_1.m_i[3]);
	16	register_subalias("5", m_1.m_i[4]);
	17	register_subalias("6", m_1.m_i[5]);
18	18
19		register_subalias("8", m_1.m_Q);
	19	register_subalias("8", m_1.m_Q);
20	20
21		register_subalias("11", m_1.m_i[6]);
22		register_subalias("12", m_1.m_i[7]);
	21	register_subalias("11", m_1.m_i[6]);
	22	register_subalias("12", m_1.m_i[7]);
23	23	}
24	24
25	25	NETLIB_UPDATE(7430_dip)
26	26	{
27		/* only called during startup */
28		m_1.update_dev();
	27	/* only called during startup */
	28	m_1.update_dev();
29	29	}
30	30
31	31	NETLIB_RESET(7430_dip)
32	32	{
33		m_1.do_reset();
	33	m_1.do_reset();
34	34	}
35

trunk/src/emu/netlist/devices/nld_7450.c
r29404	r29405
7	7
8	8	NETLIB_START(7450)
9	9	{
10		register_input("A", m_A);
11		register_input("B", m_B);
12		register_input("C", m_C);
13		register_input("D", m_D);
14		register_output("Q", m_Q);
	10	register_input("A", m_A);
	11	register_input("B", m_B);
	12	register_input("C", m_C);
	13	register_input("D", m_D);
	14	register_output("Q", m_Q);
15	15	}
16	16
17	17	NETLIB_RESET(7450)
r29404	r29405
20	20
21	21	NETLIB_UPDATE(7450)
22	22	{
23		m_A.activate();
24		m_B.activate();
25		m_C.activate();
26		m_D.activate();
27		UINT8 t1 = INPLOGIC(m_A) & INPLOGIC(m_B);
28		UINT8 t2 = INPLOGIC(m_C) & INPLOGIC(m_D);
	23	m_A.activate();
	24	m_B.activate();
	25	m_C.activate();
	26	m_D.activate();
	27	UINT8 t1 = INPLOGIC(m_A) & INPLOGIC(m_B);
	28	UINT8 t2 = INPLOGIC(m_C) & INPLOGIC(m_D);
29	29
30		const netlist_time times[2] = { NLTIME_FROM_NS(22), NLTIME_FROM_NS(15) };
	30	const netlist_time times[2] = { NLTIME_FROM_NS(22), NLTIME_FROM_NS(15) };
31	31
32		UINT8 res = 0;
33		if (t1 ^ 1)
34		{
35		if (t2 ^ 1)
36		{
37		res = 1;
38		}
39		else
40		{
41		m_A.inactivate();
42		m_B.inactivate();
43		}
44		} else {
45		if (t2 ^ 1)
46		{
47		m_C.inactivate();
48		m_D.inactivate();
49		}
50		}
51		OUTLOGIC(m_Q, res, times[1 - res]);// ? 22000 : 15000);
	32	UINT8 res = 0;
	33	if (t1 ^ 1)
	34	{
	35	if (t2 ^ 1)
	36	{
	37	res = 1;
	38	}
	39	else
	40	{
	41	m_A.inactivate();
	42	m_B.inactivate();
	43	}
	44	} else {
	45	if (t2 ^ 1)
	46	{
	47	m_C.inactivate();
	48	m_D.inactivate();
	49	}
	50	}
	51	OUTLOGIC(m_Q, res, times[1 - res]);// ? 22000 : 15000);
52	52	}
53	53
54	54
55	55	NETLIB_START(7450_dip)
56	56	{
57		register_sub(m_1, "1");
58		register_sub(m_2, "2");
	57	register_sub(m_1, "1");
	58	register_sub(m_2, "2");
59	59
60		register_subalias("1", m_1.m_A);
61		register_subalias("2", m_2.m_A);
62		register_subalias("3", m_2.m_B);
63		register_subalias("4", m_2.m_C);
64		register_subalias("5", m_2.m_D);
65		register_subalias("6", m_2.m_Q);
66		//register_subalias("7",); GND
	60	register_subalias("1", m_1.m_A);
	61	register_subalias("2", m_2.m_A);
	62	register_subalias("3", m_2.m_B);
	63	register_subalias("4", m_2.m_C);
	64	register_subalias("5", m_2.m_D);
	65	register_subalias("6", m_2.m_Q);
	66	//register_subalias("7",); GND
67	67
68		register_subalias("8", m_1.m_Q);
69		register_subalias("9", m_1.m_C);
70		register_subalias("10", m_1.m_D);
71		//register_subalias("11", m_1.m_X1);
72		//register_subalias("12", m_1.m_X1Q);
73		register_subalias("13", m_1.m_B);
74		//register_subalias("14",); VCC
	68	register_subalias("8", m_1.m_Q);
	69	register_subalias("9", m_1.m_C);
	70	register_subalias("10", m_1.m_D);
	71	//register_subalias("11", m_1.m_X1);
	72	//register_subalias("12", m_1.m_X1Q);
	73	register_subalias("13", m_1.m_B);
	74	//register_subalias("14",); VCC
75	75	}
76	76
77	77	NETLIB_UPDATE(7450_dip)
78	78	{
79		/* only called during startup */
80		m_1.update_dev();
81		m_2.update_dev();
	79	/* only called during startup */
	80	m_1.update_dev();
	81	m_2.update_dev();
82	82	}
83	83
84	84	NETLIB_RESET(7450_dip)
85	85	{
86		m_1.do_reset();
87		m_2.do_reset();
	86	m_1.do_reset();
	87	m_2.do_reset();
88	88	}
89

trunk/src/emu/netlist/devices/nld_4066.c
r29404	r29405
25	25
26	26	NETLIB_RESET(4066)
27	27	{
28		m_R.do_reset();
	28	m_R.do_reset();
29	29	}
30	30
31	31	NETLIB_UPDATE(4066)
32	32	{
33		double sup = (m_supply->vdd() - m_supply->vss());
34		double low = 0.45 * sup;
35		double high = 0.55 * sup;
36		double in = INPANALOG(m_control) - m_supply->vss();
37		double rON = 270.0 * 5.0 / sup;
	33	double sup = (m_supply->vdd() - m_supply->vss());
	34	double low = 0.45 * sup;
	35	double high = 0.55 * sup;
	36	double in = INPANALOG(m_control) - m_supply->vss();
	37	double rON = 270.0 * 5.0 / sup;
38	38
39		if (in < low)
40		{
41		m_R.set_R(1.0 / netlist().gmin());
42		m_R.update_dev();
43		}
44		else if (in > high)
45		{
46		m_R.set_R(rON);
47		m_R.update_dev();
48		}
	39	if (in < low)
	40	{
	41	m_R.set_R(1.0 / netlist().gmin());
	42	m_R.update_dev();
	43	}
	44	else if (in > high)
	45	{
	46	m_R.set_R(rON);
	47	m_R.update_dev();
	48	}
49	49	}
50	50
51	51
52	52	NETLIB_START(4066_dip)
53	53	{
54		register_sub(m_supply, "supply");
55		m_A.m_supply = m_B.m_supply = m_C.m_supply = m_D.m_supply = &m_supply;
56		register_sub(m_A, "A");
57		register_sub(m_B, "B");
58		register_sub(m_C, "C");
59		register_sub(m_D, "D");
	54	register_sub(m_supply, "supply");
	55	m_A.m_supply = m_B.m_supply = m_C.m_supply = m_D.m_supply = &m_supply;
	56	register_sub(m_A, "A");
	57	register_sub(m_B, "B");
	58	register_sub(m_C, "C");
	59	register_sub(m_D, "D");
60	60
61		register_subalias("1", m_A.m_R.m_P);
62		register_subalias("2", m_A.m_R.m_N);
63		register_subalias("3", m_B.m_R.m_P);
64		register_subalias("4", m_B.m_R.m_N);
65		register_subalias("5", m_B.m_control);
66		register_subalias("6", m_C.m_control);
67		register_input("7", m_supply.m_vss);
	61	register_subalias("1", m_A.m_R.m_P);
	62	register_subalias("2", m_A.m_R.m_N);
	63	register_subalias("3", m_B.m_R.m_P);
	64	register_subalias("4", m_B.m_R.m_N);
	65	register_subalias("5", m_B.m_control);
	66	register_subalias("6", m_C.m_control);
	67	register_input("7", m_supply.m_vss);
68	68
69		register_subalias("8", m_C.m_R.m_P);
70		register_subalias("9", m_C.m_R.m_N);
71		register_subalias("10", m_D.m_R.m_P);
72		register_subalias("11", m_D.m_R.m_N);
73		register_subalias("12", m_D.m_control);
74		register_subalias("13", m_A.m_control);
75		register_input("14", m_supply.m_vdd);
	69	register_subalias("8", m_C.m_R.m_P);
	70	register_subalias("9", m_C.m_R.m_N);
	71	register_subalias("10", m_D.m_R.m_P);
	72	register_subalias("11", m_D.m_R.m_N);
	73	register_subalias("12", m_D.m_control);
	74	register_subalias("13", m_A.m_control);
	75	register_input("14", m_supply.m_vdd);
76	76
77	77	}
78	78
79	79	NETLIB_RESET(4066_dip)
80	80	{
81		m_A.do_reset();
82		m_B.do_reset();
83		m_C.do_reset();
84		m_D.do_reset();
	81	m_A.do_reset();
	82	m_B.do_reset();
	83	m_C.do_reset();
	84	m_D.do_reset();
85	85	}
86	86
87	87	NETLIB_UPDATE(4066_dip)
88	88	{
89		/* only called during startup */
90		m_A.update_dev();
91		m_B.update_dev();
92		m_C.update_dev();
93		m_D.update_dev();
	89	/* only called during startup */
	90	m_A.update_dev();
	91	m_B.update_dev();
	92	m_C.update_dev();
	93	m_D.update_dev();
94	94	}

trunk/src/emu/netlist/devices/nld_7410.h
r29404	r29405
43	43	NETLIB_SIGNAL(7410, 3, 0, 0);
44	44
45	45	#define TTL_7410_DIP(_name) \
46		NET_REGISTER_DEV(7410_dip, _name)
	46	NET_REGISTER_DEV(7410_dip, _name)
47	47
48	48	NETLIB_DEVICE(7410_dip,
49	49
50		NETLIB_NAME(7410) m_1;
51		NETLIB_NAME(7410) m_2;
52		NETLIB_NAME(7410) m_3;
	50	NETLIB_NAME(7410) m_1;
	51	NETLIB_NAME(7410) m_2;
	52	NETLIB_NAME(7410) m_3;
53	53	);
54	54
55	55	#endif /* NLD_7410_H_ */

trunk/src/emu/netlist/devices/nld_ne555.c
r29404	r29405
46	46
47	47	NETLIB_RESET(NE555)
48	48	{
49		m_R1.do_reset();
50		m_R2.do_reset();
51		m_R3.do_reset();
52		m_RDIS.do_reset();
	49	m_R1.do_reset();
	50	m_R2.do_reset();
	51	m_R3.do_reset();
	52	m_RDIS.do_reset();
53	53
54		m_R1.set_R(5000);
55		m_R2.set_R(5000);
56		m_R3.set_R(5000);
57		m_RDIS.set_R(R_OFF);
	54	m_R1.set_R(5000);
	55	m_R2.set_R(5000);
	56	m_R3.set_R(5000);
	57	m_RDIS.set_R(R_OFF);
58	58
59		m_last_out = false;
	59	m_last_out = false;
60	60	}
61	61
62	62	NETLIB_UPDATE(NE555)
r29404	r29405
93	93
94	94	NETLIB_START(NE555_dip)
95	95	{
96		NETLIB_NAME(NE555)::start();
	96	NETLIB_NAME(NE555)::start();
97	97
98		register_subalias("1", m_R3.m_N); // Pin 1
99		register_subalias("2", m_TRIG); // Pin 2
100		register_subalias("3", m_OUT); // Pin 3
101		register_subalias("4", m_RESET); // Pin 4
102		register_subalias("5", m_R1.m_N); // Pin 5
103		register_subalias("6", m_THRES); // Pin 6
104		register_subalias("7", m_RDIS.m_P); // Pin 7
105		register_subalias("8", m_R1.m_P); // Pin 8
	98	register_subalias("1", m_R3.m_N); // Pin 1
	99	register_subalias("2", m_TRIG); // Pin 2
	100	register_subalias("3", m_OUT); // Pin 3
	101	register_subalias("4", m_RESET); // Pin 4
	102	register_subalias("5", m_R1.m_N); // Pin 5
	103	register_subalias("6", m_THRES); // Pin 6
	104	register_subalias("7", m_RDIS.m_P); // Pin 7
	105	register_subalias("8", m_R1.m_P); // Pin 8
106	106
107	107	}
108	108
109	109	NETLIB_UPDATE(NE555_dip)
110	110	{
111		NETLIB_NAME(NE555)::update();
	111	NETLIB_NAME(NE555)::update();
112	112	}
113	113
114	114	NETLIB_RESET(NE555_dip)
115	115	{
116		NETLIB_NAME(NE555)::reset();
	116	NETLIB_NAME(NE555)::reset();
117	117	}

trunk/src/emu/netlist/devices/nld_7430.h
r29404	r29405
54	54	NETLIB_SIGNAL(7430, 8, 0, 0);
55	55
56	56	#define TTL_7430_DIP(_name) \
57		NET_REGISTER_DEV(7430_dip, _name)
	57	NET_REGISTER_DEV(7430_dip, _name)
58	58
59	59	NETLIB_DEVICE(7430_dip,
60	60
61		NETLIB_NAME(7430) m_1;
	61	NETLIB_NAME(7430) m_1;
62	62	);
63	63	#endif /* NLD_7430_H_ */

trunk/src/emu/netlist/devices/nld_9316.c
r29404	r29405
7	7
8	8	NETLIB_START(9316)
9	9	{
10		register_sub(subABCD, "subABCD");
11		sub.m_ABCD = &subABCD;
	10	register_sub(subABCD, "subABCD");
	11	sub.m_ABCD = &subABCD;
12	12	register_sub(sub, "sub");
13	13
14	14	register_subalias("CLK", sub.m_CLK);
r29404	r29405
33	33
34	34	NETLIB_RESET(9316)
35	35	{
36		sub.do_reset();
37		subABCD.do_reset();
	36	sub.do_reset();
	37	subABCD.do_reset();
38	38	}
39	39
40	40	NETLIB_START(9316_subABCD)
41	41	{
42		register_input("A", m_A);
43		register_input("B", m_B);
44		register_input("C", m_C);
45		register_input("D", m_D);
	42	register_input("A", m_A);
	43	register_input("B", m_B);
	44	register_input("C", m_C);
	45	register_input("D", m_D);
46	46
47	47	}
48	48
49	49	NETLIB_RESET(9316_subABCD)
50	50	{
51		if (1 \|\| !USE_ADD_REMOVE_LIST)
52		{
53		m_A.inactivate();
54		m_B.inactivate();
55		m_C.inactivate();
56		m_D.inactivate();
57		}
	51	if (1 \|\| !USE_ADD_REMOVE_LIST)
	52	{
	53	m_A.inactivate();
	54	m_B.inactivate();
	55	m_C.inactivate();
	56	m_D.inactivate();
	57	}
58	58	}
59	59
60	60	ATTR_HOT inline UINT8 NETLIB_NAME(9316_subABCD::read_ABCD)()
61	61	{
62		if (1 \|\| !USE_ADD_REMOVE_LIST)
63		return (INPLOGIC_PASSIVE(m_D) << 3) \| (INPLOGIC_PASSIVE(m_C) << 2) \| (INPLOGIC_PASSIVE(m_B) << 1) \| (INPLOGIC_PASSIVE(m_A) << 0);
64		else
65		return (INPLOGIC(m_D) << 3) \| (INPLOGIC(m_C) << 2) \| (INPLOGIC(m_B) << 1) \| (INPLOGIC(m_A) << 0);
	62	if (1 \|\| !USE_ADD_REMOVE_LIST)
	63	return (INPLOGIC_PASSIVE(m_D) << 3) \| (INPLOGIC_PASSIVE(m_C) << 2) \| (INPLOGIC_PASSIVE(m_B) << 1) \| (INPLOGIC_PASSIVE(m_A) << 0);
	64	else
	65	return (INPLOGIC(m_D) << 3) \| (INPLOGIC(m_C) << 2) \| (INPLOGIC(m_B) << 1) \| (INPLOGIC(m_A) << 0);
66	66	}
67	67
68	68	NETLIB_UPDATE(9316_subABCD)
r29404	r29405
86	86
87	87	NETLIB_RESET(9316_sub)
88	88	{
89		m_CLK.set_state(netlist_input_t::STATE_INP_LH);
90		m_cnt = 0;
91		m_loadq = 1;
92		m_ent = 1;
	89	m_CLK.set_state(netlist_input_t::STATE_INP_LH);
	90	m_cnt = 0;
	91	m_loadq = 1;
	92	m_ent = 1;
93	93	}
94	94
95	95	NETLIB_UPDATE(9316_sub)
r29404	r29405
99	99	{
100	100	cnt = ( cnt + 1) & 0x0f;
101	101	update_outputs(cnt);
102		OUTLOGIC(m_RC, m_ent & (cnt == 0x0f), NLTIME_FROM_NS(20));
	102	OUTLOGIC(m_RC, m_ent & (cnt == 0x0f), NLTIME_FROM_NS(20));
103	103	#if 0
104	104	if (cnt == 0x0f)
105	105	OUTLOGIC(m_RC, m_ent, NLTIME_FROM_NS(20));
r29404	r29405
128	128	}
129	129	else
130	130	{
131		UINT8 cnt = sub.m_cnt;
	131	UINT8 cnt = sub.m_cnt;
132	132	sub.m_CLK.inactivate();
133	133	if (!clrq & (cnt>0))
134	134	{
r29404	r29405
198	198
199	199	NETLIB_START(9316_dip)
200	200	{
201		NETLIB_NAME(9316)::start();
	201	NETLIB_NAME(9316)::start();
202	202
203		register_subalias("1", m_CLRQ);
204		register_subalias("2", sub.m_CLK);
205		register_subalias("3", subABCD.m_A);
206		register_subalias("4", subABCD.m_B);
207		register_subalias("5", subABCD.m_C);
208		register_subalias("6", subABCD.m_D);
209		register_subalias("7", m_ENP);
210		// register_subalias("8", ); --> GND
	203	register_subalias("1", m_CLRQ);
	204	register_subalias("2", sub.m_CLK);
	205	register_subalias("3", subABCD.m_A);
	206	register_subalias("4", subABCD.m_B);
	207	register_subalias("5", subABCD.m_C);
	208	register_subalias("6", subABCD.m_D);
	209	register_subalias("7", m_ENP);
	210	// register_subalias("8", ); --> GND
211	211
212		register_subalias("9", m_LOADQ);
213		register_subalias("10", m_ENT);
214		register_subalias("11", sub.m_QD);
215		register_subalias("12", sub.m_QC);
216		register_subalias("13", sub.m_QB);
217		register_subalias("14", sub.m_QA);
218		register_subalias("15", sub.m_RC);
219		// register_subalias("16", ); --> VCC
	212	register_subalias("9", m_LOADQ);
	213	register_subalias("10", m_ENT);
	214	register_subalias("11", sub.m_QD);
	215	register_subalias("12", sub.m_QC);
	216	register_subalias("13", sub.m_QB);
	217	register_subalias("14", sub.m_QA);
	218	register_subalias("15", sub.m_RC);
	219	// register_subalias("16", ); --> VCC
220	220	}
221	221
222	222	NETLIB_UPDATE(9316_dip)
223	223	{
224		NETLIB_NAME(9316)::update();
	224	NETLIB_NAME(9316)::update();
225	225	}
226	226
227	227	NETLIB_RESET(9316_dip)
228	228	{
229		NETLIB_NAME(9316)::reset();
	229	NETLIB_NAME(9316)::reset();
230	230	}
231

trunk/src/emu/netlist/devices/nld_7490.c
r29404	r29405
7	7
8	8	NETLIB_START(7490)
9	9	{
10		register_input("A", m_A);
11		register_input("B", m_B);
	10	register_input("A", m_A);
	11	register_input("B", m_B);
12	12	register_input("R1", m_R1);
13	13	register_input("R2", m_R2);
14	14	register_input("R91", m_R91);
r29404	r29405
25	25
26	26	NETLIB_RESET(7490)
27	27	{
28		m_cnt = 0;
	28	m_cnt = 0;
29	29	}
30	30
31	31	static const netlist_time delay[4] =
32	32	{
33		NLTIME_FROM_NS(18),
34		NLTIME_FROM_NS(36) - NLTIME_FROM_NS(18),
35		NLTIME_FROM_NS(54) - NLTIME_FROM_NS(18),
36		NLTIME_FROM_NS(72) - NLTIME_FROM_NS(18)};
	33	NLTIME_FROM_NS(18),
	34	NLTIME_FROM_NS(36) - NLTIME_FROM_NS(18),
	35	NLTIME_FROM_NS(54) - NLTIME_FROM_NS(18),
	36	NLTIME_FROM_NS(72) - NLTIME_FROM_NS(18)};
37	37
38	38	NETLIB_UPDATE(7490)
39	39	{
r29404	r29405
50	50	else if (INP_HL(m_A))
51	51	{
52	52	m_cnt ^= 1;
53		OUTLOGIC(m_Q[0], m_cnt & 1, delay[0]);
	53	OUTLOGIC(m_Q[0], m_cnt & 1, delay[0]);
54	54	}
55		else if (INP_HL(m_B))
56		{
57		m_cnt += 2;
58		if (m_cnt >= 10)
59		m_cnt = 0;
60		update_outputs();
61		}
	55	else if (INP_HL(m_B))
	56	{
	57	m_cnt += 2;
	58	if (m_cnt >= 10)
	59	m_cnt = 0;
	60	update_outputs();
	61	}
62	62	}
63	63
64	64	NETLIB_FUNC_VOID(7490, update_outputs, (void))
65	65	{
66
67	66	for (int i=0; i<4; i++)
68	67	OUTLOGIC(m_Q[i], (m_cnt >> i) & 1, delay[i]);
69	68	}
70	69
71	70	NETLIB_START(7490_dip)
72	71	{
73		NETLIB_NAME(7490)::start();
74		register_subalias("1", m_B);
75		register_subalias("2", m_R1);
76		register_subalias("3", m_R2);
	72	NETLIB_NAME(7490)::start();
	73	register_subalias("1", m_B);
	74	register_subalias("2", m_R1);
	75	register_subalias("3", m_R2);
77	76
78		// register_subalias("4", ); --> NC
79		// register_subalias("5", ); --> VCC
80		register_subalias("6", m_R91);
81		register_subalias("7", m_R92);
	77	// register_subalias("4", ); --> NC
	78	// register_subalias("5", ); --> VCC
	79	register_subalias("6", m_R91);
	80	register_subalias("7", m_R92);
82	81
83		register_subalias("8", m_Q[2]);
84		register_subalias("9", m_Q[1]);
85		// register_subalias("10", ); --> GND
86		register_subalias("11", m_Q[3]);
87		register_subalias("12", m_Q[0]);
88		// register_subalias("13", ); --> NC
89		register_subalias("14", m_A);
	82	register_subalias("8", m_Q[2]);
	83	register_subalias("9", m_Q[1]);
	84	// register_subalias("10", ); --> GND
	85	register_subalias("11", m_Q[3]);
	86	register_subalias("12", m_Q[0]);
	87	// register_subalias("13", ); --> NC
	88	register_subalias("14", m_A);
90	89
91	90	}
92	91
93	92	NETLIB_UPDATE(7490_dip)
94	93	{
95		NETLIB_NAME(7490)::update();
	94	NETLIB_NAME(7490)::update();
96	95	}
97	96
98	97	NETLIB_RESET(7490_dip)
99	98	{
100		NETLIB_NAME(7490)::reset();
	99	NETLIB_NAME(7490)::reset();
101	100	}

trunk/src/emu/netlist/devices/nld_7450.h
r29404	r29405
27	27	#include "nld_signal.h"
28	28
29	29	#define TTL_7450_ANDORINVERT(_name, _I1, _I2, _I3, _I4) \
30		NET_REGISTER_DEV(7450, _name) \
31		NET_CONNECT(_name, A, _I1) \
32		NET_CONNECT(_name, B, _I2) \
33		NET_CONNECT(_name, C, _I3) \
34		NET_CONNECT(_name, D, _I4)
	30	NET_REGISTER_DEV(7450, _name) \
	31	NET_CONNECT(_name, A, _I1) \
	32	NET_CONNECT(_name, B, _I2) \
	33	NET_CONNECT(_name, C, _I3) \
	34	NET_CONNECT(_name, D, _I4)
35	35
36	36	#define TTL_7450_DIP(_name) \
37		NET_REGISTER_DEV(7450_dip, _name)
	37	NET_REGISTER_DEV(7450_dip, _name)
38	38
39	39	NETLIB_DEVICE(7450,
40	40	public:
41		netlist_ttl_input_t m_A;
42		netlist_ttl_input_t m_B;
43		netlist_ttl_input_t m_C;
44		netlist_ttl_input_t m_D;
45		netlist_ttl_output_t m_Q;
	41	netlist_ttl_input_t m_A;
	42	netlist_ttl_input_t m_B;
	43	netlist_ttl_input_t m_C;
	44	netlist_ttl_input_t m_D;
	45	netlist_ttl_output_t m_Q;
46	46	);
47	47
48	48	NETLIB_DEVICE(7450_dip,

trunk/src/emu/netlist/devices/nld_4066.h
r29404	r29405
28	28	#include "../analog/nld_twoterm.h"
29	29
30	30	#define CD_4066_DIP(_name) \
31		NET_REGISTER_DEV(4066_dip, _name)
	31	NET_REGISTER_DEV(4066_dip, _name)
32	32
33	33	NETLIB_SUBDEVICE(vdd_vss,
34	34	netlist_analog_input_t m_vdd;
35		netlist_analog_input_t m_vss;
	35	netlist_analog_input_t m_vss;
36	36
37	37	public:
38		ATTR_HOT inline double vdd() { return INPANALOG(m_vdd); }
39		ATTR_HOT inline double vss() { return INPANALOG(m_vss); }
	38	ATTR_HOT inline double vdd() { return INPANALOG(m_vdd); }
	39	ATTR_HOT inline double vss() { return INPANALOG(m_vss); }
40	40	);
41	41
42	42	NETLIB_SUBDEVICE(4066,
r29404	r29405
50	50
51	51	NETLIB_DEVICE(4066_dip,
52	52
53		NETLIB_NAME(4066) m_A;
54		NETLIB_NAME(4066) m_B;
55		NETLIB_NAME(4066) m_C;
56		NETLIB_NAME(4066) m_D;
57		NETLIB_NAME(vdd_vss) m_supply;
	53	NETLIB_NAME(4066) m_A;
	54	NETLIB_NAME(4066) m_B;
	55	NETLIB_NAME(4066) m_C;
	56	NETLIB_NAME(4066) m_D;
	57	NETLIB_NAME(vdd_vss) m_supply;
58	58	);
59	59
60	60	#endif /* NLD_4066_H_ */

trunk/src/emu/netlist/devices/nld_7474.c
r29404	r29405
23	23
24	24	NETLIB_UPDATE(7474)
25	25	{
26		if (!INPLOGIC(m_PREQ) && !INPLOGIC(m_CLRQ))
27		{
28		sub.newstate(1, 1);
29		sub.m_CLK.inactivate();
30		}
	26	if (!INPLOGIC(m_PREQ) && !INPLOGIC(m_CLRQ))
	27	{
	28	sub.newstate(1, 1);
	29	sub.m_CLK.inactivate();
	30	}
31	31	if (!INPLOGIC(m_PREQ))
32	32	{
33	33	sub.newstate(1, 0);
r29404	r29405
64	64
65	65	NETLIB_RESET(7474)
66	66	{
67		sub.do_reset();
	67	sub.do_reset();
68	68	}
69	69
70	70	NETLIB_START(7474sub)
r29404	r29405
79	79
80	80	NETLIB_RESET(7474sub)
81	81	{
82		m_CLK.set_state(netlist_input_t::STATE_INP_LH);
	82	m_CLK.set_state(netlist_input_t::STATE_INP_LH);
83	83
84		m_nextD = 0;
85		/* FIXME: required by pong doubles - need a mechanism to set this from netlist */
86		m_Q.initial(1);
87		m_QQ.initial(0);
	84	m_nextD = 0;
	85	/* FIXME: required by pong doubles - need a mechanism to set this from netlist */
	86	m_Q.initial(1);
	87	m_QQ.initial(0);
88	88	}
89	89
90	90	NETLIB_START(7474_dip)
91	91	{
92		register_sub(m_1, "1");
93		register_sub(m_2, "2");
	92	register_sub(m_1, "1");
	93	register_sub(m_2, "2");
94	94
95		register_subalias("1", m_1.m_CLRQ);
96		register_subalias("2", m_1.m_D);
97		register_subalias("3", m_1.sub.m_CLK);
98		register_subalias("4", m_1.m_PREQ);
99		register_subalias("5", m_1.sub.m_Q);
100		register_subalias("6", m_1.sub.m_QQ);
101		// register_subalias("7", ); ==> GND
	95	register_subalias("1", m_1.m_CLRQ);
	96	register_subalias("2", m_1.m_D);
	97	register_subalias("3", m_1.sub.m_CLK);
	98	register_subalias("4", m_1.m_PREQ);
	99	register_subalias("5", m_1.sub.m_Q);
	100	register_subalias("6", m_1.sub.m_QQ);
	101	// register_subalias("7", ); ==> GND
102	102
103		register_subalias("8", m_2.sub.m_QQ);
104		register_subalias("9", m_2.sub.m_Q);
105		register_subalias("10", m_2.m_PREQ);
106		register_subalias("11", m_2.sub.m_CLK);
107		register_subalias("12", m_2.m_D);
108		register_subalias("13", m_2.m_CLRQ);
109		// register_subalias("14", ); ==> VCC
	103	register_subalias("8", m_2.sub.m_QQ);
	104	register_subalias("9", m_2.sub.m_Q);
	105	register_subalias("10", m_2.m_PREQ);
	106	register_subalias("11", m_2.sub.m_CLK);
	107	register_subalias("12", m_2.m_D);
	108	register_subalias("13", m_2.m_CLRQ);
	109	// register_subalias("14", ); ==> VCC
110	110	}
111	111
112	112	NETLIB_RESET(7474_dip)
113	113	{
114		m_1.do_reset();
115		m_2.do_reset();
	114	m_1.do_reset();
	115	m_2.do_reset();
116	116	}
117	117
118	118	NETLIB_UPDATE(7474_dip)
119	119	{
120		m_1.update_dev();
121		m_2.update_dev();
	120	m_1.update_dev();
	121	m_2.update_dev();
122	122	}

trunk/src/emu/netlist/devices/nld_ne555.h
r29404	r29405
44	44	);
45	45
46	46	#define NE555_DIP(_name) \
47		NET_REGISTER_DEV(NE555_dip, _name)
	47	NET_REGISTER_DEV(NE555_dip, _name)
48	48
49	49	NETLIB_DEVICE_DERIVED(NE555_dip, NE555,
50	50	);

trunk/src/emu/netlist/devices/nld_7493.c
r29404	r29405
29	29
30	30	NETLIB_RESET(7493)
31	31	{
32		A.do_reset();
33		B.do_reset();
34		C.do_reset();
35		D.do_reset();
	32	A.do_reset();
	33	B.do_reset();
	34	C.do_reset();
	35	D.do_reset();
36	36	}
37	37
38	38	NETLIB_START(7493ff)
r29404	r29405
45	45
46	46	NETLIB_RESET(7493ff)
47	47	{
48		m_reset = 1;
49		m_I.set_state(netlist_input_t::STATE_INP_HL);
	48	m_reset = 1;
	49	m_I.set_state(netlist_input_t::STATE_INP_HL);
50	50	}
51	51
52	52	NETLIB_UPDATE(7493ff)
53	53	{
54		const netlist_time out_delay = NLTIME_FROM_NS(18);
	54	const netlist_time out_delay = NLTIME_FROM_NS(18);
55	55	//if (m_reset == 0)
56	56	OUTLOGIC(m_Q, (!m_Q.net().new_Q()) & m_reset, out_delay);
57	57	}
r29404	r29405
68	68	OUTLOGIC(B.m_Q, 0, NLTIME_FROM_NS(40));
69	69	OUTLOGIC(C.m_Q, 0, NLTIME_FROM_NS(40));
70	70	OUTLOGIC(D.m_Q, 0, NLTIME_FROM_NS(40));
71		A.m_reset = B.m_reset = C.m_reset = D.m_reset = 0;
	71	A.m_reset = B.m_reset = C.m_reset = D.m_reset = 0;
72	72	}
73	73	else
74	74	{
75	75	A.m_I.activate_hl();
76	76	B.m_I.activate_hl();
77		A.m_reset = B.m_reset = C.m_reset = D.m_reset = 1;
	77	A.m_reset = B.m_reset = C.m_reset = D.m_reset = 1;
78	78	}
79	79	}
80	80
81	81	NETLIB_START(7493_dip)
82	82	{
83		NETLIB_NAME(7493)::start();
	83	NETLIB_NAME(7493)::start();
84	84
85		register_subalias("1", B.m_I);
86		register_subalias("2", m_R1);
87		register_subalias("3", m_R2);
	85	register_subalias("1", B.m_I);
	86	register_subalias("2", m_R1);
	87	register_subalias("3", m_R2);
88	88
89		// register_subalias("4", ); --> NC
90		// register_subalias("5", ); --> VCC
91		// register_subalias("6", ); --> NC
92		// register_subalias("7", ); --> NC
	89	// register_subalias("4", ); --> NC
	90	// register_subalias("5", ); --> VCC
	91	// register_subalias("6", ); --> NC
	92	// register_subalias("7", ); --> NC
93	93
94		register_subalias("8", C.m_Q);
95		register_subalias("9", B.m_Q);
96		// register_subalias("10", ); --> GND
97		register_subalias("11", D.m_Q);
98		register_subalias("12", A.m_Q);
99		// register_subalias("13", ); --> NC
100		register_subalias("14", A.m_I);
	94	register_subalias("8", C.m_Q);
	95	register_subalias("9", B.m_Q);
	96	// register_subalias("10", ); --> GND
	97	register_subalias("11", D.m_Q);
	98	register_subalias("12", A.m_Q);
	99	// register_subalias("13", ); --> NC
	100	register_subalias("14", A.m_I);
101	101	}
102	102
103	103
104	104	NETLIB_UPDATE(7493_dip)
105	105	{
106		NETLIB_NAME(7493)::update();
	106	NETLIB_NAME(7493)::update();
107	107	}
108	108
109	109	NETLIB_RESET(7493_dip)
110	110	{
111		NETLIB_NAME(7493)::reset();
	111	NETLIB_NAME(7493)::reset();
112	112	}

trunk/src/emu/netlist/devices/nld_9316.h
r29404	r29405
64	64	NET_CONNECT(_name, D, _D)
65	65
66	66	#define TTL_9316_DIP(_name) \
67		NET_REGISTER_DEV(9316_dip, _name)
	67	NET_REGISTER_DEV(9316_dip, _name)
68	68
69	69	NETLIB_SUBDEVICE(9316_subABCD,
70		netlist_ttl_input_t m_A;
71		netlist_ttl_input_t m_B;
72		netlist_ttl_input_t m_C;
73		netlist_ttl_input_t m_D;
	70	netlist_ttl_input_t m_A;
	71	netlist_ttl_input_t m_B;
	72	netlist_ttl_input_t m_C;
	73	netlist_ttl_input_t m_D;
74	74
75		ATTR_HOT inline UINT8 read_ABCD();
	75	ATTR_HOT inline UINT8 read_ABCD();
76	76	);
77	77
78	78	NETLIB_SUBDEVICE(9316_sub,
r29404	r29405
95	95
96	96	NETLIB_DEVICE(9316,
97	97	NETLIB_NAME(9316_sub) sub;
98		NETLIB_NAME(9316_subABCD) subABCD;
	98	NETLIB_NAME(9316_subABCD) subABCD;
99	99	netlist_ttl_input_t m_ENP;
100	100	netlist_ttl_input_t m_ENT;
101	101	netlist_ttl_input_t m_CLRQ;

trunk/src/emu/netlist/devices/nld_7490.h
r29404	r29405
60	60	#define TTL_7490(_name, _A, _B, _R1, _R2, _R91, _R92) \
61	61	NET_REGISTER_DEV(7490, _name) \
62	62	NET_CONNECT(_name, A, _A) \
63		NET_CONNECT(_name, B, _B) \
	63	NET_CONNECT(_name, B, _B) \
64	64	NET_CONNECT(_name, R1, _R1) \
65	65	NET_CONNECT(_name, R2, _R2) \
66	66	NET_CONNECT(_name, R91, _R91) \
67	67	NET_CONNECT(_name, R92, _R92)
68	68
69	69	#define TTL_7490_DIP(_name) \
70		NET_REGISTER_DEV(7490_dip, _name)
	70	NET_REGISTER_DEV(7490_dip, _name)
71	71
72	72
73	73	NETLIB_DEVICE(7490,
r29404	r29405
78	78	netlist_ttl_input_t m_R91;
79	79	netlist_ttl_input_t m_R92;
80	80	netlist_ttl_input_t m_A;
81		netlist_ttl_input_t m_B;
	81	netlist_ttl_input_t m_B;
82	82
83	83	UINT8 m_cnt;
84	84

trunk/src/emu/netlist/devices/nld_7474.h
r29404	r29405
52	52	NET_CONNECT(_name, PREQ, _PREQ)
53	53
54	54	#define TTL_7474_DIP(_name) \
55		NET_REGISTER_DEV(7474_dip, _name)
	55	NET_REGISTER_DEV(7474_dip, _name)
56	56
57	57	NETLIB_SUBDEVICE(7474sub,
58	58	netlist_ttl_input_t m_CLK;
r29404	r29405
75	75
76	76	NETLIB_DEVICE(7474_dip,
77	77
78		NETLIB_NAME(7474) m_1;
79		NETLIB_NAME(7474) m_2;
	78	NETLIB_NAME(7474) m_1;
	79	NETLIB_NAME(7474) m_2;
80	80	);
81	81
82	82	#endif /* NLD_7474_H_ */

trunk/src/emu/netlist/devices/nld_7493.h
r29404	r29405
67	67	NET_CONNECT(_name, R2, _R2)
68	68
69	69	#define TTL_7493_DIP(_name) \
70		NET_REGISTER_DEV(7493_dip, _name)
	70	NET_REGISTER_DEV(7493_dip, _name)
71	71
72	72	NETLIB_SUBDEVICE(7493ff,
73	73	netlist_ttl_input_t m_I;

trunk/src/emu/netlist/devices/net_lib.c
r29404	r29405
51	51	#include "nld_system.h"
52	52
53	53	NETLIST_START(diode_models)
54		NET_MODEL(".model 1N914 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
55		NET_MODEL(".model 1N4148 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
	54	NET_MODEL(".model 1N914 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
	55	NET_MODEL(".model 1N4148 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
56	56	NETLIST_END()
57	57
58	58	NETLIST_START(bjt_models)
59		NET_MODEL(".MODEL BC237B NPN(IS=1.8E-14 ISE=5.0E-14 ISC=1.72E-13 XTI=3 BF=400 BR=35.5 IKF=0.14 IKR=0.03 XTB=1.5 VAF=80 VAR=12.5 VJE=0.58 VJC=0.54 RE=0.6 RC=0.25 RB=0.56 CJE=13E-12 CJC=4E-12 XCJC=0.75 FC=0.5 NF=0.9955 NR=1.005 NE=1.46 NC=1.27 MJE=0.33 MJC=0.33 TF=0.64E-9 TR=50.72E-9 EG=1.11 KF=0 AF=1 VCEO=45V ICRATING=100M MFG=ZETEX)")
60		NET_MODEL(".model BC556B PNP(IS=3.83E-14 NF=1.008 ISE=1.22E-14 NE=1.528 BF=344.4 IKF=0.08039 VAF=21.11 NR=1.005 ISC=2.85E-13 NC=1.28 BR=14.84 IKR=0.047 VAR=32.02 RB=1 IRB=1.00E-06 RBM=1 RE=0.6202 RC=0.5713 XTB=0 EG=1.11 XTI=3 CJE=1.23E-11 VJE=0.6106 MJE=0.378 TF=5.60E-10 XTF=3.414 VTF=5.23 ITF=0.1483 PTF=0 CJC=1.08E-11 VJC=0.1022 MJC=0.3563 XCJC=0.6288 TR=1.00E-32 CJS=0 VJS=0.75 MJS=0.333 FC=0.8027 Vceo=65 Icrating=100m mfg=Philips)")
61		NET_MODEL(".model 2SA1015 PNP(Is=295.1E-18 Xti=3 Eg=1.11 Vaf=100 Bf=110 Xtb=1.5 Br=10.45 Rc=15 Cjc=66.2p Mjc=1.054 Vjc=.75 Fc=.5 Cje=5p Mje=.3333 Vje=.75 Tr=10n Tf=1.661n VCEO=45V ICrating=150M MFG=Toshiba)")
62		NET_MODEL(".model 2SC1815 NPN(Is=2.04f Xti=3 Eg=1.11 Vaf=6 Bf=400 Ikf=20m Xtb=1.5 Br=3.377 Rc=1 Cjc=1p Mjc=.3333 Vjc=.75 Fc=.5 Cje=25p Mje=.3333 Vje=.75 Tr=450n Tf=20n Itf=0 Vtf=0 Xtf=0 VCEO=45V ICrating=150M MFG=Toshiba)")
	59	NET_MODEL(".MODEL BC237B NPN(IS=1.8E-14 ISE=5.0E-14 ISC=1.72E-13 XTI=3 BF=400 BR=35.5 IKF=0.14 IKR=0.03 XTB=1.5 VAF=80 VAR=12.5 VJE=0.58 VJC=0.54 RE=0.6 RC=0.25 RB=0.56 CJE=13E-12 CJC=4E-12 XCJC=0.75 FC=0.5 NF=0.9955 NR=1.005 NE=1.46 NC=1.27 MJE=0.33 MJC=0.33 TF=0.64E-9 TR=50.72E-9 EG=1.11 KF=0 AF=1 VCEO=45V ICRATING=100M MFG=ZETEX)")
	60	NET_MODEL(".model BC556B PNP(IS=3.83E-14 NF=1.008 ISE=1.22E-14 NE=1.528 BF=344.4 IKF=0.08039 VAF=21.11 NR=1.005 ISC=2.85E-13 NC=1.28 BR=14.84 IKR=0.047 VAR=32.02 RB=1 IRB=1.00E-06 RBM=1 RE=0.6202 RC=0.5713 XTB=0 EG=1.11 XTI=3 CJE=1.23E-11 VJE=0.6106 MJE=0.378 TF=5.60E-10 XTF=3.414 VTF=5.23 ITF=0.1483 PTF=0 CJC=1.08E-11 VJC=0.1022 MJC=0.3563 XCJC=0.6288 TR=1.00E-32 CJS=0 VJS=0.75 MJS=0.333 FC=0.8027 Vceo=65 Icrating=100m mfg=Philips)")
	61	NET_MODEL(".model 2SA1015 PNP(Is=295.1E-18 Xti=3 Eg=1.11 Vaf=100 Bf=110 Xtb=1.5 Br=10.45 Rc=15 Cjc=66.2p Mjc=1.054 Vjc=.75 Fc=.5 Cje=5p Mje=.3333 Vje=.75 Tr=10n Tf=1.661n VCEO=45V ICrating=150M MFG=Toshiba)")
	62	NET_MODEL(".model 2SC1815 NPN(Is=2.04f Xti=3 Eg=1.11 Vaf=6 Bf=400 Ikf=20m Xtb=1.5 Br=3.377 Rc=1 Cjc=1p Mjc=.3333 Vjc=.75 Fc=.5 Cje=25p Mje=.3333 Vje=.75 Tr=450n Tf=20n Itf=0 Vtf=0 Xtf=0 VCEO=45V ICrating=150M MFG=Toshiba)")
63	63	NETLIST_END()
64	64
65	65
r29404	r29405
89	89	ENTRY(D, DIODE, "model")
90	90	ENTRY(VCVS, VCVS, "-") // FIXME: STD parameters ?
91	91	ENTRY(VCCS, VCCS, "-")
92		ENTRY(QBJT_EB, QBJT_EB, "model")
	92	ENTRY(QBJT_EB, QBJT_EB, "model")
93	93	ENTRY(QBJT_switch, QBJT_SW, "model")
94	94	ENTRY(ttl_input, TTL_INPUT, "IN")
95	95	ENTRY(analog_input, ANALOG_INPUT, "IN")
r29404	r29405
98	98	ENTRY(clock, CLOCK, "FREQ")
99	99	ENTRY(mainclock, MAINCLOCK, "FREQ")
100	100	ENTRY(solver, SOLVER, "FREQ")
101		ENTRY(gnd, GND, "-")
	101	ENTRY(gnd, GND, "-")
102	102	ENTRY(switch2, SWITCH2, "-")
103	103	ENTRY(nicRSFF, NETDEV_RSFF, "+S,R")
104	104	ENTRY(7400, TTL_7400_NAND, "+A,B")
r29404	r29405
119	119	ENTRY(74107, TTL_74107, "+CLK,J,K,CLRQ")
120	120	ENTRY(74107A, TTL_74107A, "+CLK,J,K,CLRQ")
121	121	ENTRY(74153, TTL_74153, "+C0,C1,C2,C3,A,B,G")
122		ENTRY(SN74LS629, SN74LS629, "CAP")
	122	ENTRY(SN74LS629, SN74LS629, "CAP")
123	123	ENTRY(9316, TTL_9316, "+CLK,ENP,ENT,CLRQ,LOADQ,A,B,C,D")
124	124	ENTRY(NE555, NE555, "-")
125		ENTRY(4066_dip, CD_4066_DIP, "-")
126		ENTRY(7400_dip, TTL_7400_DIP, "-")
127		ENTRY(7402_dip, TTL_7402_DIP, "-")
128		ENTRY(7404_dip, TTL_7404_DIP, "-")
129		ENTRY(7410_dip, TTL_7410_DIP, "-")
130		ENTRY(7420_dip, TTL_7420_DIP, "-")
131		ENTRY(7425_dip, TTL_7425_DIP, "-")
132		ENTRY(7427_dip, TTL_7427_DIP, "-")
133		ENTRY(7430_dip, TTL_7430_DIP, "-")
134		ENTRY(7448_dip, TTL_7448_DIP, "-")
135		ENTRY(7450_dip, TTL_7450_DIP, "-")
136		ENTRY(7474_dip, TTL_7474_DIP, "-")
137		ENTRY(7483_dip, TTL_7483_DIP, "-")
138		ENTRY(7486_dip, TTL_7486_DIP, "-")
139		ENTRY(7490_dip, TTL_7490_DIP, "-")
140		ENTRY(7493_dip, TTL_7493_DIP, "-")
141		ENTRY(74107_dip, TTL_74107_DIP, "-")
142		ENTRY(74153_dip, TTL_74153_DIP, "-")
143		ENTRY(9316_dip, TTL_9316_DIP, "-")
144		ENTRY(SN74LS629_dip, SN74LS629_DIP, "1.CAP1,2.CAP2")
145		ENTRY(NE555_dip, NE555_DIP, "-")
	125	ENTRY(4066_dip, CD_4066_DIP, "-")
	126	ENTRY(7400_dip, TTL_7400_DIP, "-")
	127	ENTRY(7402_dip, TTL_7402_DIP, "-")
	128	ENTRY(7404_dip, TTL_7404_DIP, "-")
	129	ENTRY(7410_dip, TTL_7410_DIP, "-")
	130	ENTRY(7420_dip, TTL_7420_DIP, "-")
	131	ENTRY(7425_dip, TTL_7425_DIP, "-")
	132	ENTRY(7427_dip, TTL_7427_DIP, "-")
	133	ENTRY(7430_dip, TTL_7430_DIP, "-")
	134	ENTRY(7448_dip, TTL_7448_DIP, "-")
	135	ENTRY(7450_dip, TTL_7450_DIP, "-")
	136	ENTRY(7474_dip, TTL_7474_DIP, "-")
	137	ENTRY(7483_dip, TTL_7483_DIP, "-")
	138	ENTRY(7486_dip, TTL_7486_DIP, "-")
	139	ENTRY(7490_dip, TTL_7490_DIP, "-")
	140	ENTRY(7493_dip, TTL_7493_DIP, "-")
	141	ENTRY(74107_dip, TTL_74107_DIP, "-")
	142	ENTRY(74153_dip, TTL_74153_DIP, "-")
	143	ENTRY(9316_dip, TTL_9316_DIP, "-")
	144	ENTRY(SN74LS629_dip, SN74LS629_DIP, "1.CAP1,2.CAP2")
	145	ENTRY(NE555_dip, NE555_DIP, "-")
146	146	}
147	147
148	148	netlist_device_t *netlist_factory_t::new_device_by_classname(const pstring &classname, netlist_setup_t &setup) const
r29404	r29405
163	163
164	164	netlist_device_t *netlist_factory_t::new_device_by_name(const pstring &name, netlist_setup_t &setup) const
165	165	{
166		net_device_t_base_factory *f = factory_by_name(name, setup);
167		return f->Create();
	166	net_device_t_base_factory *f = factory_by_name(name, setup);
	167	return f->Create();
168	168	}
169	169
170	170	net_device_t_base_factory * netlist_factory_t::factory_by_name(const pstring &name, netlist_setup_t &setup) const
171	171	{
172		for (net_device_t_base_factory * const *e = m_list.first(); e != NULL; e = m_list.next(e))
173		{
174		net_device_t_base_factory p = e;
175		if (strcmp(p->name(), name) == 0)
176		{
177		return p;
178		}
179		p++;
180		}
181		setup.netlist().error("Class %s not found!\n", name.cstr());
182		return NULL; // appease code analysis
	172	for (net_device_t_base_factory * const *e = m_list.first(); e != NULL; e = m_list.next(e))
	173	{
	174	net_device_t_base_factory p = e;
	175	if (strcmp(p->name(), name) == 0)
	176	{
	177	return p;
	178	}
	179	p++;
	180	}
	181	setup.netlist().error("Class %s not found!\n", name.cstr());
	182	return NULL; // appease code analysis
183	183	}

trunk/src/emu/netlist/nl_base.c
r29404	r29405
13	13
14	14	netlist_logic_family_desc_t netlist_family_ttl =
15	15	{
16		0.8, // m_low_thresh_V
17		2.0, // m_high_thresh_V
18		0.3, // m_low_V - these depend on sinked/sourced current. Values should be suitable for typical applications.
19		3.7, // m_high_V
20		1.0, // m_R_low;
21		130.0, // m_R_high;
	16	0.8, // m_low_thresh_V
	17	2.0, // m_high_thresh_V
	18	0.3, // m_low_V - these depend on sinked/sourced current. Values should be suitable for typical applications.
	19	3.7, // m_high_V
	20	1.0, // m_R_low;
	21	130.0, // m_R_high;
22	22	};
23	23
24	24	// ----------------------------------------------------------------------------------------
r29404	r29405
94	94	{
95	95	if (m_name == "")
96	96	netlist().error("object not initialized");
97		return m_name;
	97	return m_name;
98	98	}
99	99
100	100	// ----------------------------------------------------------------------------------------
r29404	r29405
142	142	{
143	143	for (int i=0; i < m_nets.count(); i++)
144	144	{
145		if (!m_nets[i]->isRailNet())
146		{
147		delete m_nets[i];
148		}
	145	if (!m_nets[i]->isRailNet())
	146	{
	147	delete m_nets[i];
	148	}
149	149	}
150	150
151	151	m_nets.clear();
r29404	r29405
157	157
158	158	ATTR_COLD void netlist_base_t::save_register()
159	159	{
160		save(NAME(m_queue.callback()));
161		save(NAME(m_time));
162		netlist_object_t::save_register();
	160	save(NAME(m_queue.callback()));
	161	save(NAME(m_time));
	162	netlist_object_t::save_register();
163	163	}
164	164
165	165	ATTR_HOT const double netlist_base_t::gmin() const
166	166	{
167		return solver()->gmin();
	167	return solver()->gmin();
168	168	}
169	169
170	170	ATTR_COLD void netlist_base_t::start()
171	171	{
172		/* find the main clock and solver ... */
	172	/* find the main clock and solver ... */
173	173
174		m_mainclock = get_single_device<NETLIB_NAME(mainclock)>("mainclock");
175		m_solver = get_single_device<NETLIB_NAME(solver)>("solver");
176		m_gnd = get_single_device<NETLIB_NAME(gnd)>("gnd");
	174	m_mainclock = get_single_device<NETLIB_NAME(mainclock)>("mainclock");
	175	m_solver = get_single_device<NETLIB_NAME(solver)>("solver");
	176	m_gnd = get_single_device<NETLIB_NAME(gnd)>("gnd");
177	177
178		/* make sure the solver is started first! */
	178	/* make sure the solver is started first! */
179	179
180		if (m_solver != NULL)
181		m_solver->start_dev();
	180	if (m_solver != NULL)
	181	m_solver->start_dev();
182	182
183		NL_VERBOSE_OUT(("Initializing devices ...\n"));
184		for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
185		{
186		netlist_device_t *dev = entry->object();
187		if (dev != m_solver)
188		dev->start_dev();
189		}
	183	NL_VERBOSE_OUT(("Initializing devices ...\n"));
	184	for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
	185	{
	186	netlist_device_t *dev = entry->object();
	187	if (dev != m_solver)
	188	dev->start_dev();
	189	}
190	190
191	191	}
192	192
r29404	r29405
202	202
203	203	ATTR_COLD void netlist_base_t::rebuild_lists()
204	204	{
205		for (int i = 0; i < m_nets.count(); i++)
206		m_nets[i]->rebuild_list();
	205	for (int i = 0; i < m_nets.count(); i++)
	206	m_nets[i]->rebuild_list();
207	207	}
208	208
209	209
r29404	r29405
213	213	m_queue.clear();
214	214	if (m_mainclock != NULL)
215	215	m_mainclock->m_Q.net().set_time(netlist_time::zero);
216		if (m_solver != NULL)
217		m_solver->do_reset();
	216	if (m_solver != NULL)
	217	m_solver->do_reset();
218	218
219		// Reset all nets once !
220		for (int i = 0; i < m_nets.count(); i++)
221		m_nets[i]->do_reset();
	219	// Reset all nets once !
	220	for (int i = 0; i < m_nets.count(); i++)
	221	m_nets[i]->do_reset();
222	222
223		// Reset all devices once !
224		for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
225		{
226		netlist_device_t *dev = entry->object();
227		dev->do_reset();
228		}
	223	// Reset all devices once !
	224	for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
	225	{
	226	netlist_device_t *dev = entry->object();
	227	dev->do_reset();
	228	}
229	229
230	230	// Step all devices once !
231	231	for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
r29404	r29405
235	235	}
236	236
237	237	// FIXME: some const devices rely on this
238		/* make sure params are set now .. */
239		for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
240		{
241		entry->object()->update_param();
242		}
	238	/* make sure params are set now .. */
	239	for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
	240	{
	241	entry->object()->update_param();
	242	}
243	243	}
244	244
245	245
246	246	ATTR_HOT ATTR_ALIGN void netlist_base_t::process_queue(const netlist_time delta)
247	247	{
248		m_stop = m_time + delta;
	248	m_stop = m_time + delta;
249	249
250		if (m_mainclock == NULL)
251		{
252		while ( (m_time < m_stop) && (m_queue.is_not_empty()))
253		{
254		const netlist_queue_t::entry_t *e = m_queue.pop();
255		m_time = e->exec_time();
256		e->object()->update_devs();
	250	if (m_mainclock == NULL)
	251	{
	252	while ( (m_time < m_stop) && (m_queue.is_not_empty()))
	253	{
	254	const netlist_queue_t::entry_t *e = m_queue.pop();
	255	m_time = e->exec_time();
	256	e->object()->update_devs();
257	257
258		add_to_stat(m_perf_out_processed, 1);
259		if (FATAL_ERROR_AFTER_NS)
260		if (time() > NLTIME_FROM_NS(FATAL_ERROR_AFTER_NS))
261		error("Stopped");
262		}
263		if (m_queue.is_empty())
264		m_time = m_stop;
	258	add_to_stat(m_perf_out_processed, 1);
	259	if (FATAL_ERROR_AFTER_NS)
	260	if (time() > NLTIME_FROM_NS(FATAL_ERROR_AFTER_NS))
	261	error("Stopped");
	262	}
	263	if (m_queue.is_empty())
	264	m_time = m_stop;
265	265
266		} else {
267		netlist_net_t &mc_net = m_mainclock->m_Q.net();
268		const netlist_time inc = m_mainclock->m_inc;
269		netlist_time mc_time = mc_net.time();
	266	} else {
	267	netlist_net_t &mc_net = m_mainclock->m_Q.net();
	268	const netlist_time inc = m_mainclock->m_inc;
	269	netlist_time mc_time = mc_net.time();
270	270
271		while (m_time < m_stop)
272		{
273		if (m_queue.is_not_empty())
274		{
275		while (m_queue.peek()->exec_time() > mc_time)
276		{
277		m_time = mc_time;
278		mc_time += inc;
279		NETLIB_NAME(mainclock)::mc_update(mc_net);
280		}
	271	while (m_time < m_stop)
	272	{
	273	if (m_queue.is_not_empty())
	274	{
	275	while (m_queue.peek()->exec_time() > mc_time)
	276	{
	277	m_time = mc_time;
	278	mc_time += inc;
	279	NETLIB_NAME(mainclock)::mc_update(mc_net);
	280	}
281	281
282		const netlist_queue_t::entry_t *e = m_queue.pop();
283		m_time = e->exec_time();
284		e->object()->update_devs();
	282	const netlist_queue_t::entry_t *e = m_queue.pop();
	283	m_time = e->exec_time();
	284	e->object()->update_devs();
285	285
286		} else {
287		m_time = mc_time;
288		mc_time += inc;
289		NETLIB_NAME(mainclock)::mc_update(mc_net);
290		}
291		if (FATAL_ERROR_AFTER_NS)
292		if (time() > NLTIME_FROM_NS(FATAL_ERROR_AFTER_NS))
293		error("Stopped");
	286	} else {
	287	m_time = mc_time;
	288	mc_time += inc;
	289	NETLIB_NAME(mainclock)::mc_update(mc_net);
	290	}
	291	if (FATAL_ERROR_AFTER_NS)
	292	if (time() > NLTIME_FROM_NS(FATAL_ERROR_AFTER_NS))
	293	error("Stopped");
294	294
295		add_to_stat(m_perf_out_processed, 1);
296		}
297		mc_net.set_time(mc_time);
298		}
	295	add_to_stat(m_perf_out_processed, 1);
	296	}
	297	mc_net.set_time(mc_time);
	298	}
299	299	}
300	300
301	301	ATTR_COLD void netlist_base_t::error(const char *format, ...) const
r29404	r29405
308	308
309	309	ATTR_COLD void netlist_base_t::warning(const char *format, ...) const
310	310	{
311		va_list ap;
312		va_start(ap, format);
313		verror(NL_WARNING, format, ap);
314		va_end(ap);
	311	va_list ap;
	312	va_start(ap, format);
	313	verror(NL_WARNING, format, ap);
	314	va_end(ap);
315	315	}
316	316
317	317	ATTR_COLD void netlist_base_t::log(const char *format, ...) const
318	318	{
319		va_list ap;
320		va_start(ap, format);
321		verror(NL_LOG, format, ap);
322		va_end(ap);
	319	va_list ap;
	320	va_start(ap, format);
	321	verror(NL_LOG, format, ap);
	322	va_end(ap);
323	323	}
324	324
325	325
r29404	r29405
361	361	ATTR_HOT ATTR_ALIGN const netlist_sig_t netlist_core_device_t::INPLOGIC_PASSIVE(netlist_logic_input_t &inp)
362	362	{
363	363	if (inp.state() != netlist_input_t::STATE_INP_PASSIVE)
364		return inp.Q();
	364	return inp.Q();
365	365	else
366		{
367		inp.activate();
368		const netlist_sig_t ret = inp.Q();
369		inp.inactivate();
370		return ret;
371		}
	366	{
	367	inp.activate();
	368	const netlist_sig_t ret = inp.Q();
	369	inp.inactivate();
	370	return ret;
	371	}
372	372	}
373	373
374	374
r29404	r29405
424	424	ATTR_COLD void netlist_device_t::register_terminal(const pstring &name, netlist_terminal_t &port)
425	425	{
426	426	setup().register_object(*this, name, port);
427		if (port.isType(netlist_terminal_t::INPUT) \|\| port.isType(netlist_terminal_t::TERMINAL))
428		m_terminals.add(port.name());
	427	if (port.isType(netlist_terminal_t::INPUT) \|\| port.isType(netlist_terminal_t::TERMINAL))
	428	m_terminals.add(port.name());
429	429	}
430	430
431	431	ATTR_COLD void netlist_device_t::register_output(const pstring &name, netlist_output_t &port)
432	432	{
433		port.m_family_desc = this->m_family_desc;
	433	port.m_family_desc = this->m_family_desc;
434	434	setup().register_object(*this, name, port);
435	435	}
436	436
437	437	ATTR_COLD void netlist_device_t::register_input(const pstring &name, netlist_input_t &inp)
438	438	{
439		inp.m_family_desc = this->m_family_desc;
	439	inp.m_family_desc = this->m_family_desc;
440	440	setup().register_object(*this, name, inp);
441		m_terminals.add(inp.name());
	441	m_terminals.add(inp.name());
442	442	}
443	443
444	444	ATTR_COLD void netlist_device_t::connect(netlist_core_terminal_t &t1, netlist_core_terminal_t &t2)
445	445	{
446		setup().connect(t1, t2);
	446	setup().connect(t1, t2);
447	447	}
448	448
449	449
r29404	r29405
470	470
471	471	ATTR_COLD netlist_net_t::netlist_net_t(const type_t atype, const family_t afamily)
472	472	: netlist_object_t(atype, afamily)
473		, m_solver(NULL)
474		, m_railterminal(NULL)
	473	, m_solver(NULL)
	474	, m_railterminal(NULL)
475	475	, m_num_cons(0)
476	476	, m_time(netlist_time::zero)
477	477	, m_active(0)
478	478	, m_in_queue(2)
479	479	{
480		m_last_Q = 0;
481		m_new_Q = 0;
482		m_cur_Q = 0;
483		m_last_Analog = 0.0;
484		m_new_Analog = 0.0;
485		m_cur_Analog = 0.0;
	480	m_last_Q = 0;
	481	m_new_Q = 0;
	482	m_cur_Q = 0;
	483	m_last_Analog = 0.0;
	484	m_new_Analog = 0.0;
	485	m_cur_Analog = 0.0;
486	486	};
487	487
488	488	ATTR_COLD netlist_net_t::~netlist_net_t()
489	489	{
490		netlist().remove_save_items(this);
	490	netlist().remove_save_items(this);
491	491	}
492	492
493	493	ATTR_HOT void netlist_net_t::inc_active(netlist_core_terminal_t &term)
494	494	{
495		m_active++;
	495	m_active++;
496	496
497		if (USE_ADD_REMOVE_LIST)
498		{
499		m_list.insert(term);
500		//m_list.add(term);
501		}
	497	if (USE_ADD_REMOVE_LIST)
	498	{
	499	m_list.insert(term);
	500	//m_list.add(term);
	501	}
502	502
503		if (USE_DEACTIVE_DEVICE)
504		{
505		if (m_active == 1 && m_in_queue > 0)
506		{
507		m_last_Q = m_cur_Q;
508		m_last_Analog = m_cur_Analog; // FIXME: Needed here ?
509		railterminal().netdev().inc_active();
510		m_cur_Q = m_new_Q;
511		m_cur_Analog = m_new_Analog;
512		}
513		}
	503	if (USE_DEACTIVE_DEVICE)
	504	{
	505	if (m_active == 1 && m_in_queue > 0)
	506	{
	507	m_last_Q = m_cur_Q;
	508	m_last_Analog = m_cur_Analog; // FIXME: Needed here ?
	509	railterminal().netdev().inc_active();
	510	m_cur_Q = m_new_Q;
	511	m_cur_Analog = m_new_Analog;
	512	}
	513	}
514	514
515		if (m_active == 1 && m_in_queue == 0)
516		{
517		if (m_time > netlist().time())
518		{
519		m_in_queue = 1; /* pending */
520		netlist().push_to_queue(this, m_time);
521		}
522		else
523		{
524		m_cur_Q = m_last_Q = m_new_Q;
525		m_cur_Analog = m_last_Analog = m_new_Analog; // FIXME: Needed here?
526		m_in_queue = 2;
527		}
528		}
	515	if (m_active == 1 && m_in_queue == 0)
	516	{
	517	if (m_time > netlist().time())
	518	{
	519	m_in_queue = 1; /* pending */
	520	netlist().push_to_queue(this, m_time);
	521	}
	522	else
	523	{
	524	m_cur_Q = m_last_Q = m_new_Q;
	525	m_cur_Analog = m_last_Analog = m_new_Analog; // FIXME: Needed here?
	526	m_in_queue = 2;
	527	}
	528	}
529	529	}
530	530
531	531	ATTR_HOT void netlist_net_t::dec_active(netlist_core_terminal_t &term)
532	532	{
533		m_active--;
	533	m_active--;
534	534
535		if (USE_ADD_REMOVE_LIST)
536		{
537		m_list.remove(term);
538		}
	535	if (USE_ADD_REMOVE_LIST)
	536	{
	537	m_list.remove(term);
	538	}
539	539
540		if (USE_DEACTIVE_DEVICE)
541		{
542		if (m_active == 0)
543		railterminal().netdev().dec_active();
544		}
	540	if (USE_DEACTIVE_DEVICE)
	541	{
	542	if (m_active == 0)
	543	railterminal().netdev().dec_active();
	544	}
545	545	}
546	546
547	547	ATTR_COLD void netlist_net_t::rebuild_list()
548	548	{
549		/* rebuild m_list */
	549	/* rebuild m_list */
550	550
551		m_list.clear();
552		for (int i=0; i < m_registered.count(); i++)
553		if (m_registered[i]->state() != netlist_input_t::STATE_INP_PASSIVE)
554		m_list.add(*m_registered[i]);
	551	m_list.clear();
	552	for (int i=0; i < m_registered.count(); i++)
	553	if (m_registered[i]->state() != netlist_input_t::STATE_INP_PASSIVE)
	554	m_list.add(*m_registered[i]);
555	555	}
556	556
557	557	ATTR_COLD void netlist_net_t::reset()
558	558	{
559		m_last_Analog = 0.0;
560		m_cur_Analog = 0.0;
561		m_new_Analog = 0.0;
562		m_last_Q = 0; // set to something we will never hit.
563		m_new_Q = 0;
564		m_cur_Q = 0;
565		m_time = netlist_time::zero;
566		m_active = 0;
567		m_in_queue = 2;
	559	m_last_Analog = 0.0;
	560	m_cur_Analog = 0.0;
	561	m_new_Analog = 0.0;
	562	m_last_Q = 0; // set to something we will never hit.
	563	m_new_Q = 0;
	564	m_cur_Q = 0;
	565	m_time = netlist_time::zero;
	566	m_active = 0;
	567	m_in_queue = 2;
568	568
569		/* rebuild m_list */
	569	/* rebuild m_list */
570	570
571		m_list.clear();
572		for (int i=0; i < m_registered.count(); i++)
573		m_list.add(*m_registered[i]);
	571	m_list.clear();
	572	for (int i=0; i < m_registered.count(); i++)
	573	m_list.add(*m_registered[i]);
574	574
575		for (netlist_core_terminal_t *t = m_list.first(); t != NULL; t = m_list.next(t))
576		{
577		t->do_reset();
578		}
579		for (netlist_core_terminal_t *t = m_list.first(); t != NULL; t = m_list.next(t))
580		{
581		if (t->state() != netlist_input_t::STATE_INP_PASSIVE)
582		m_active++;
583		}
	575	for (netlist_core_terminal_t *t = m_list.first(); t != NULL; t = m_list.next(t))
	576	{
	577	t->do_reset();
	578	}
	579	for (netlist_core_terminal_t *t = m_list.first(); t != NULL; t = m_list.next(t))
	580	{
	581	if (t->state() != netlist_input_t::STATE_INP_PASSIVE)
	582	m_active++;
	583	}
584	584	}
585	585
586	586	ATTR_COLD void netlist_net_t::init_object(netlist_base_t &nl, const pstring &aname)
r29404	r29405
591	591
592	592	ATTR_COLD void netlist_net_t::save_register()
593	593	{
594		save(NAME(m_last_Analog));
595		save(NAME(m_cur_Analog));
596		save(NAME(m_new_Analog));
597		save(NAME(m_last_Q));
598		save(NAME(m_cur_Q));
599		save(NAME(m_new_Q));
600		save(NAME(m_time));
601		save(NAME(m_active));
602		save(NAME(m_in_queue));
603		netlist_object_t::save_register();
	594	save(NAME(m_last_Analog));
	595	save(NAME(m_cur_Analog));
	596	save(NAME(m_new_Analog));
	597	save(NAME(m_last_Q));
	598	save(NAME(m_cur_Q));
	599	save(NAME(m_new_Q));
	600	save(NAME(m_time));
	601	save(NAME(m_active));
	602	save(NAME(m_in_queue));
	603	netlist_object_t::save_register();
604	604	}
605	605
606	606	ATTR_COLD void netlist_net_t::register_railterminal(netlist_output_t &mr)
r29404	r29405
666	666	assert(this->isRailNet());
667	667
668	668	const UINT32 masks[4] = { 1, 5, 3, 1 };
669		const UINT32 mask = masks[ (m_last_Q << 1) \| m_new_Q ];
670		netlist_core_terminal_t *p = m_list.first();
	669	const UINT32 mask = masks[ (m_last_Q << 1) \| m_new_Q ];
	670	netlist_core_terminal_t *p = m_list.first();
671	671
672		m_in_queue = 2; /* mark as taken ... */
673		m_cur_Q = m_new_Q;
	672	m_in_queue = 2; /* mark as taken ... */
	673	m_cur_Q = m_new_Q;
674	674
675		m_cur_Analog = m_new_Analog;
	675	m_cur_Analog = m_new_Analog;
676	676
677		if (USE_ADD_REMOVE_LIST)
678		{
679		switch (m_active)
680		{
681		case 2:
682		update_dev(p, mask);
683		p = m_list.next(p);
684		if (p == NULL) break;
685		case 1:
686		update_dev(p, mask);
687		break;
688		default:
689		while (p != NULL)
690		{
691		update_dev(p, mask);
692		p = m_list.next(p);
693		}
694		break;
695		}
696		}
697		else
698		{
699		switch (m_num_cons)
700		{
701		case 2:
702		update_dev(p, mask);
703		p = m_list.next(p);
704		case 1:
705		update_dev(p, mask);
706		break;
707		default:
708		do
709		{
710		update_dev(p, mask);
711		p = m_list.next(p);
712		} while (p != NULL);
713		break;
714		}
715		}
716		m_last_Q = m_cur_Q;
717		m_last_Analog = m_cur_Analog;
	677	if (USE_ADD_REMOVE_LIST)
	678	{
	679	switch (m_active)
	680	{
	681	case 2:
	682	update_dev(p, mask);
	683	p = m_list.next(p);
	684	if (p == NULL) break;
	685	case 1:
	686	update_dev(p, mask);
	687	break;
	688	default:
	689	while (p != NULL)
	690	{
	691	update_dev(p, mask);
	692	p = m_list.next(p);
	693	}
	694	break;
	695	}
	696	}
	697	else
	698	{
	699	switch (m_num_cons)
	700	{
	701	case 2:
	702	update_dev(p, mask);
	703	p = m_list.next(p);
	704	case 1:
	705	update_dev(p, mask);
	706	break;
	707	default:
	708	do
	709	{
	710	update_dev(p, mask);
	711	p = m_list.next(p);
	712	} while (p != NULL);
	713	break;
	714	}
	715	}
	716	m_last_Q = m_cur_Q;
	717	m_last_Analog = m_cur_Analog;
718	718	}
719	719
720	720	ATTR_HOT void netlist_net_t::solve()
721	721	{
722		if (m_solver != NULL)
723		m_solver->schedule();
	722	if (m_solver != NULL)
	723	m_solver->schedule();
724	724	}
725	725
726	726	// ----------------------------------------------------------------------------------------
r29404	r29405
748	748
749	749	ATTR_COLD void netlist_terminal_t::reset()
750	750	{
751		//netlist_terminal_core_terminal_t::reset();
752		set_state(STATE_INP_ACTIVE);
753		m_Idr = 0.0;
754		m_go = netlist().gmin();
755		m_gt = netlist().gmin();
	751	//netlist_terminal_core_terminal_t::reset();
	752	set_state(STATE_INP_ACTIVE);
	753	m_Idr = 0.0;
	754	m_go = netlist().gmin();
	755	m_gt = netlist().gmin();
756	756	}
757	757
758	758	ATTR_COLD void netlist_terminal_t::save_register()
759	759	{
760		save(NAME(m_Idr));
761		save(NAME(m_go));
762		save(NAME(m_gt));
763		netlist_core_terminal_t::save_register();
	760	save(NAME(m_Idr));
	761	save(NAME(m_go));
	762	save(NAME(m_gt));
	763	netlist_core_terminal_t::save_register();
764	764	}
765	765
766	766
r29404	r29405
782	782	, m_my_net(NET, afamily)
783	783	{
784	784	//m_net = new net_net_t(NET_DIGITAL);
785		set_state(STATE_OUT);
	785	set_state(STATE_OUT);
786	786	this->set_net(m_my_net);
787	787	}
788	788
r29404	r29405
798	798	// ----------------------------------------------------------------------------------------
799	799
800	800	ATTR_COLD netlist_logic_output_t::netlist_logic_output_t()
801		: netlist_output_t(OUTPUT, LOGIC), m_proxy(NULL)
	801	: netlist_output_t(OUTPUT, LOGIC), m_proxy(NULL)
802	802	{
803	803	}
804	804
r29404	r29405
806	806	{
807	807	net().m_cur_Q = val;
808	808	net().m_new_Q = val;
809		net().m_last_Q = val;
	809	net().m_last_Q = val;
810	810	}
811	811
812	812	// ----------------------------------------------------------------------------------------
r29404	r29405
825	825	ATTR_COLD netlist_analog_output_t::netlist_analog_output_t()
826	826	: netlist_output_t(OUTPUT, ANALOG)
827	827	{
828		net().m_last_Analog = 0.97;
	828	net().m_last_Analog = 0.97;
829	829	net().m_cur_Analog = 0.98;
830	830	net().m_new_Analog = 0.99;
831	831	}
832	832
833	833	ATTR_COLD void netlist_analog_output_t::initial(const double val)
834	834	{
835		net().m_cur_Analog = val * 0.98;
	835	net().m_cur_Analog = val * 0.98;
836	836	net().m_cur_Analog = val * 0.99;
837	837	net().m_new_Analog = val * 1.0;
838	838	}
r29404	r29405
878	878
879	879	ATTR_COLD const pstring netlist_param_model_t::model_type() const
880	880	{
881		pstring tmp = this->Value();
882		// .model 1N914 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)
883		int p = tmp.find("(");
884		int p1 = p;
885		while (--p >= 0 && tmp[p] != ' ')
886		;
	881	pstring tmp = this->Value();
	882	// .model 1N914 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)
	883	int p = tmp.find("(");
	884	int p1 = p;
	885	while (--p >= 0 && tmp[p] != ' ')
	886	;
887	887
888		return tmp.substr(p+1, p1-p-1).ucase();
	888	return tmp.substr(p+1, p1-p-1).ucase();
889	889	}
890	890
891	891
r29404	r29405
929	929
930	930	ATTR_HOT inline void NETLIB_NAME(mainclock)::mc_update(netlist_net_t &net)
931	931	{
932		net.m_new_Q ^= 1;
933		net.update_devs();
	932	net.m_new_Q ^= 1;
	933	net.update_devs();
934	934	}
935	935
936	936	NETLIB_START(mainclock)
r29404	r29405
943	943
944	944	NETLIB_RESET(mainclock)
945	945	{
946		m_Q.net().set_time(netlist_time::zero);
	946	m_Q.net().set_time(netlist_time::zero);
947	947	}
948	948
949	949	NETLIB_UPDATE_PARAM(mainclock)
r29404	r29405
965	965
966	966	ATTR_COLD const nl_util::pstring_list net_device_t_base_factory::term_param_list()
967	967	{
968		if (m_def_param.startsWith("+"))
969		return nl_util::split(m_def_param.substr(1), ",");
970		else
971		return nl_util::pstring_list();
	968	if (m_def_param.startsWith("+"))
	969	return nl_util::split(m_def_param.substr(1), ",");
	970	else
	971	return nl_util::pstring_list();
972	972	}
973	973
974	974	ATTR_COLD const nl_util::pstring_list net_device_t_base_factory::def_params()
975	975	{
976		if (m_def_param.startsWith("+") \|\| m_def_param.equals("-"))
977		return nl_util::pstring_list();
978		else
979		return nl_util::split(m_def_param, ",");
	976	if (m_def_param.startsWith("+") \|\| m_def_param.equals("-"))
	977	return nl_util::pstring_list();
	978	else
	979	return nl_util::split(m_def_param, ",");
980	980	}

trunk/src/emu/netlist/nl_dice_compat.h
r29404	r29405
29	29	struct Mono555Desc
30	30	{
31	31	public:
32		double r, c;
	32	double r, c;
33	33
34		Mono555Desc(double res, double cap) : r(res), c(cap) { }
	34	Mono555Desc(double res, double cap) : r(res), c(cap) { }
35	35	};
36	36
37	37	struct SeriesRCDesc
38	38	{
39	39	public:
40		double r, c;
	40	double r, c;
41	41
42		SeriesRCDesc(double res, double cap) : r(res), c(cap) { }
	42	SeriesRCDesc(double res, double cap) : r(res), c(cap) { }
43	43	};
44	44
45	45	#define CHIP_555_Mono(_name, _pdesc) \
46		CHIP(# _name, NE555) \
47		NET_C(_name.6, _name.7) \
48		RES(_name ## _R, (_pdesc)->r) \
49		CAP(_name ## _C, (_pdesc)->c) \
50		NET_C(_name.6, _name ## _R.1) \
51		NET_C(_name.6, _name ## _C.1) \
52		NET_C(_name ## _R.2, V5) \
53		NET_CSTR(# _name "_C.2", "GND") \
54		NET_C(_name.8, V5) \
55		NET_CSTR(# _name ".1", "GND")
	46	CHIP(# _name, NE555) \
	47	NET_C(_name.6, _name.7) \
	48	RES(_name ## _R, (_pdesc)->r) \
	49	CAP(_name ## _C, (_pdesc)->c) \
	50	NET_C(_name.6, _name ## _R.1) \
	51	NET_C(_name.6, _name ## _C.1) \
	52	NET_C(_name ## _R.2, V5) \
	53	NET_CSTR(# _name "_C.2", "GND") \
	54	NET_C(_name.8, V5) \
	55	NET_CSTR(# _name ".1", "GND")
56	56
57	57	#define CHIP_SERIES_RC(_name, _pdesc) \
58		RES(_name ## _R, (_pdesc)->r) \
59		CAP(_name ## _C, (_pdesc)->c) \
60		NET_C(_name ## _R.1, _name ## _C.2) \
61		ALIAS(_name.3, _name ## _R.1) \
62		ALIAS(_name.2, _name ## _R.2) \
63		ALIAS(_name.1, _name ## _C.1)
	58	RES(_name ## _R, (_pdesc)->r) \
	59	CAP(_name ## _C, (_pdesc)->c) \
	60	NET_C(_name ## _R.1, _name ## _C.2) \
	61	ALIAS(_name.3, _name ## _R.1) \
	62	ALIAS(_name.2, _name ## _R.2) \
	63	ALIAS(_name.1, _name ## _C.1)
64	64
65	65	#define CHIP_INPUT(_name) \
66	66	SWITCH2(_name ## _SW) \
67		NET_C(_name ## _SW.2, V5) \
68		NET_CSTR(# _name "_SW.1", "GND") \
69		ALIAS(_name.1, _name ## _SW.Q)
	67	NET_C(_name ## _SW.2, V5) \
	68	NET_CSTR(# _name "_SW.1", "GND") \
	69	ALIAS(_name.1, _name ## _SW.Q)
70	70
71	71	#define CHIP_LATCH(_name) \
72	72	NETDEV_RSFF(_name) \
73		ALIAS(_name.1, _name.S) \
74		ALIAS(_name.2, _name.R) \
75		ALIAS(_name.3, _name.QQ)
	73	ALIAS(_name.1, _name.S) \
	74	ALIAS(_name.2, _name.R) \
	75	ALIAS(_name.3, _name.QQ)
76	76
77	77
78	78

trunk/src/emu/netlist/pstate.h
r29404	r29405
29	29	DT_CUSTOM,
30	30	DT_DOUBLE,
31	31	DT_INT64,
32		DT_INT16,
	32	DT_INT16,
33	33	DT_INT8,
34	34	DT_INT,
35	35	DT_BOOLEAN
r29404	r29405
70	70
71	71	struct pstate_entry_t
72	72	{
73		typedef netlist_list_t<pstate_entry_t *> list_t;
	73	typedef netlist_list_t<pstate_entry_t *> list_t;
74	74
75		pstate_entry_t(const pstring &stname, const pstate_data_type_e dt, const void *owner,
76		const int size, const int count, void *ptr)
77		: m_name(stname), m_dt(dt), m_owner(owner), m_callback(NULL), m_size(size), m_count(count), m_ptr(ptr) { }
	75	pstate_entry_t(const pstring &stname, const pstate_data_type_e dt, const void *owner,
	76	const int size, const int count, void *ptr)
	77	: m_name(stname), m_dt(dt), m_owner(owner), m_callback(NULL), m_size(size), m_count(count), m_ptr(ptr) { }
78	78
79		pstate_entry_t(const pstring &stname, const void owner, pstate_callback_t callback)
80		: m_name(stname), m_dt(DT_CUSTOM), m_owner(owner), m_callback(callback), m_size(0), m_count(0), m_ptr(NULL) { }
	79	pstate_entry_t(const pstring &stname, const void owner, pstate_callback_t callback)
	80	: m_name(stname), m_dt(DT_CUSTOM), m_owner(owner), m_callback(callback), m_size(0), m_count(0), m_ptr(NULL) { }
81	81
82		pstring m_name;
83		const pstate_data_type_e m_dt;
84		const void *m_owner;
85		pstate_callback_t *m_callback;
86		const int m_size;
87		const int m_count;
88		void *m_ptr;
	82	pstring m_name;
	83	const pstate_data_type_e m_dt;
	84	const void *m_owner;
	85	pstate_callback_t *m_callback;
	86	const int m_size;
	87	const int m_count;
	88	void *m_ptr;
89	89	};
90	90
91	91	class pstate_manager_t
r29404	r29405
125	125	template<> ATTR_COLD inline void pstate_manager_t::save_item(pstate_callback_t &state, const void *owner, const pstring &stname)
126	126	{
127	127	//save_state_ptr(stname, DT_CUSTOM, 0, 1, &state);
128		pstate_entry_t *p = new pstate_entry_t(stname, owner, &state);
129		m_save.add(p);
	128	pstate_entry_t *p = new pstate_entry_t(stname, owner, &state);
	129	m_save.add(p);
130	130	state.register_state(*this, stname);
131	131	}
132	132

trunk/src/emu/netlist/nl_base.h
r29404	r29405
190	190	#define NETLIB_UPDATEI() ATTR_HOT ATTR_ALIGN inline void update(void)
191	191
192	192	#define NETLIB_DEVICE_BASE(_name, _pclass, _extra, _priv) \
193		class _name : public _pclass \
194		{ \
195		public: \
196		_name() \
197		: _pclass() { } \
198		protected: \
199		_extra \
200		ATTR_HOT void update(); \
201		ATTR_HOT void start(); \
202		ATTR_HOT void reset(); \
203		_priv \
204		}
	193	class _name : public _pclass \
	194	{ \
	195	public: \
	196	_name() \
	197	: _pclass() { } \
	198	protected: \
	199	_extra \
	200	ATTR_HOT void update(); \
	201	ATTR_HOT void start(); \
	202	ATTR_HOT void reset(); \
	203	_priv \
	204	}
205	205
206	206	#define NETLIB_DEVICE_DERIVED(_name, _pclass, _priv) \
207		NETLIB_DEVICE_BASE(NETLIB_NAME(_name), NETLIB_NAME(_pclass), , _priv)
	207	NETLIB_DEVICE_BASE(NETLIB_NAME(_name), NETLIB_NAME(_pclass), , _priv)
208	208
209	209	#define NETLIB_DEVICE(_name, _priv) \
210		NETLIB_DEVICE_BASE(NETLIB_NAME(_name), netlist_device_t, , _priv)
	210	NETLIB_DEVICE_BASE(NETLIB_NAME(_name), netlist_device_t, , _priv)
211	211
212	212	#define NETLIB_SUBDEVICE(_name, _priv) \
213		class NETLIB_NAME(_name) : public netlist_device_t \
214		{ \
215		public: \
216		NETLIB_NAME(_name) () \
217		: netlist_device_t() \
218		{ } \
219		/protected:/ \
220		ATTR_HOT void update(); \
221		ATTR_HOT void start(); \
222		ATTR_HOT void reset(); \
223		public: \
224		_priv \
225		}
	213	class NETLIB_NAME(_name) : public netlist_device_t \
	214	{ \
	215	public: \
	216	NETLIB_NAME(_name) () \
	217	: netlist_device_t() \
	218	{ } \
	219	/protected:/ \
	220	ATTR_HOT void update(); \
	221	ATTR_HOT void start(); \
	222	ATTR_HOT void reset(); \
	223	public: \
	224	_priv \
	225	}
226	226
227	227	#define NETLIB_DEVICE_WITH_PARAMS(_name, _priv) \
228		NETLIB_DEVICE_BASE(NETLIB_NAME(_name), netlist_device_t, \
229		ATTR_HOT void update_param(); \
230		, _priv)
	228	NETLIB_DEVICE_BASE(NETLIB_NAME(_name), netlist_device_t, \
	229	ATTR_HOT void update_param(); \
	230	, _priv)
231	231
232	232	#define NETLIB_DEVICE_WITH_PARAMS_DERIVED(_name, _pclass, _priv) \
233		NETLIB_DEVICE_BASE(NETLIB_NAME(_name), NETLIB_NAME(_pclass), \
234		ATTR_HOT void update_param(); \
235		, _priv)
	233	NETLIB_DEVICE_BASE(NETLIB_NAME(_name), NETLIB_NAME(_pclass), \
	234	ATTR_HOT void update_param(); \
	235	, _priv)
236	236
237	237	// ----------------------------------------------------------------------------------------
238	238	// forward definitions
r29404	r29405
255	255
256	256	struct netlist_logic_family_desc_t
257	257	{
258		double m_low_thresh_V;
259		double m_high_thresh_V;
260		double m_low_V;
261		double m_high_V;
262		double m_R_low;
263		double m_R_high;
	258	double m_low_thresh_V;
	259	double m_high_thresh_V;
	260	double m_low_V;
	261	double m_high_V;
	262	double m_R_low;
	263	double m_R_high;
264	264	};
265	265
266	266	/* Terminals inherit the family description from the netlist_device
r29404	r29405
278	278
279	279	class netlist_object_t
280	280	{
281		NETLIST_PREVENT_COPYING(netlist_object_t)
	281	NETLIST_PREVENT_COPYING(netlist_object_t)
282	282	public:
283		enum type_t {
284		TERMINAL = 0,
285		INPUT = 1,
286		OUTPUT = 2,
287		PARAM = 3,
288		NET = 4,
289		DEVICE = 5,
290		NETLIST = 6,
291		};
292		enum family_t {
293		// Terminal families
294		LOGIC = 1,
295		ANALOG = 2,
296		// Device families
297		GENERIC = 3, // <== devices usually fall into this category
298		RESISTOR = 4, // Resistor
299		CAPACITOR = 5, // Capacitor
300		DIODE = 6, // Diode
301		BJT_SWITCH = 7, // BJT(Switch)
302		VCVS = 8, // Voltage controlled voltage source
303		VCCS = 9, // Voltage controlled voltage source
304		BJT_EB = 10, // BJT(Ebers-Moll)
305		GND = 11, // BJT(Ebers-Moll)
306		};
	283	enum type_t {
	284	TERMINAL = 0,
	285	INPUT = 1,
	286	OUTPUT = 2,
	287	PARAM = 3,
	288	NET = 4,
	289	DEVICE = 5,
	290	NETLIST = 6,
	291	};
	292	enum family_t {
	293	// Terminal families
	294	LOGIC = 1,
	295	ANALOG = 2,
	296	// Device families
	297	GENERIC = 3, // <== devices usually fall into this category
	298	RESISTOR = 4, // Resistor
	299	CAPACITOR = 5, // Capacitor
	300	DIODE = 6, // Diode
	301	BJT_SWITCH = 7, // BJT(Switch)
	302	VCVS = 8, // Voltage controlled voltage source
	303	VCCS = 9, // Voltage controlled voltage source
	304	BJT_EB = 10, // BJT(Ebers-Moll)
	305	GND = 11, // BJT(Ebers-Moll)
	306	};
307	307
308		ATTR_COLD netlist_object_t(const type_t atype, const family_t afamily);
	308	ATTR_COLD netlist_object_t(const type_t atype, const family_t afamily);
309	309
310		virtual ~netlist_object_t();
	310	virtual ~netlist_object_t();
311	311
312		ATTR_COLD void init_object(netlist_base_t &nl, const pstring &aname);
313		ATTR_COLD bool isInitalized() { return (m_netlist != NULL); }
	312	ATTR_COLD void init_object(netlist_base_t &nl, const pstring &aname);
	313	ATTR_COLD bool isInitalized() { return (m_netlist != NULL); }
314	314
315		ATTR_COLD const pstring name() const;
	315	ATTR_COLD const pstring name() const;
316	316
317		PSTATE_INTERFACE_DECL()
	317	PSTATE_INTERFACE_DECL()
318	318
319		ATTR_HOT inline const type_t type() const { return m_objtype; }
320		ATTR_HOT inline const family_t family() const { return m_family; }
	319	ATTR_HOT inline const type_t type() const { return m_objtype; }
	320	ATTR_HOT inline const family_t family() const { return m_family; }
321	321
322		ATTR_HOT inline const bool isType(const type_t atype) const { return (m_objtype == atype); }
323		ATTR_HOT inline const bool isFamily(const family_t afamily) const { return (m_family == afamily); }
	322	ATTR_HOT inline const bool isType(const type_t atype) const { return (m_objtype == atype); }
	323	ATTR_HOT inline const bool isFamily(const family_t afamily) const { return (m_family == afamily); }
324	324
325		ATTR_HOT inline netlist_base_t & RESTRICT netlist() { return *m_netlist; }
326		ATTR_HOT inline const netlist_base_t & RESTRICT netlist() const { return *m_netlist; }
	325	ATTR_HOT inline netlist_base_t & RESTRICT netlist() { return *m_netlist; }
	326	ATTR_HOT inline const netlist_base_t & RESTRICT netlist() const { return *m_netlist; }
327	327
328		ATTR_COLD void inline do_reset()
329		{
330		reset();
331		}
	328	ATTR_COLD void inline do_reset()
	329	{
	330	reset();
	331	}
332	332
333	333	protected:
334	334
335		ATTR_COLD virtual void reset() = 0;
336		// must call parent save_register !
337		ATTR_COLD virtual void save_register() { };
	335	ATTR_COLD virtual void reset() = 0;
	336	// must call parent save_register !
	337	ATTR_COLD virtual void save_register() { };
338	338
339	339	private:
340		pstring m_name;
341		const type_t m_objtype;
342		const family_t m_family;
343		netlist_base_t * RESTRICT m_netlist;
	340	pstring m_name;
	341	const type_t m_objtype;
	342	const family_t m_family;
	343	netlist_base_t * RESTRICT m_netlist;
344	344	};
345	345
346	346	// ----------------------------------------------------------------------------------------
r29404	r29405
349	349
350	350	class netlist_owned_object_t : public netlist_object_t
351	351	{
352		NETLIST_PREVENT_COPYING(netlist_owned_object_t)
	352	NETLIST_PREVENT_COPYING(netlist_owned_object_t)
353	353	public:
354		ATTR_COLD netlist_owned_object_t(const type_t atype, const family_t afamily);
	354	ATTR_COLD netlist_owned_object_t(const type_t atype, const family_t afamily);
355	355
356		ATTR_COLD void init_object(netlist_core_device_t &dev, const pstring &aname);
	356	ATTR_COLD void init_object(netlist_core_device_t &dev, const pstring &aname);
357	357
358		ATTR_HOT inline netlist_core_device_t & RESTRICT netdev() const { return *m_netdev; }
	358	ATTR_HOT inline netlist_core_device_t & RESTRICT netdev() const { return *m_netdev; }
359	359	private:
360		netlist_core_device_t * RESTRICT m_netdev;
	360	netlist_core_device_t * RESTRICT m_netdev;
361	361	};
362	362
363	363	// ----------------------------------------------------------------------------------------
r29404	r29405
366	366
367	367	class netlist_core_terminal_t : public netlist_owned_object_t, public plinked_list_element<netlist_core_terminal_t>
368	368	{
369		NETLIST_PREVENT_COPYING(netlist_core_terminal_t)
	369	NETLIST_PREVENT_COPYING(netlist_core_terminal_t)
370	370	public:
371	371
372		typedef netlist_list_t<netlist_core_terminal_t *> list_t;
	372	typedef netlist_list_t<netlist_core_terminal_t *> list_t;
373	373
374		/* needed here ... */
	374	/* needed here ... */
375	375
376		enum state_e {
377		STATE_INP_PASSIVE = 0,
378		STATE_INP_ACTIVE = 1,
379		STATE_INP_HL = 2,
380		STATE_INP_LH = 4,
381		STATE_OUT = 128,
382		STATE_NONEX = 256
383		};
	376	enum state_e {
	377	STATE_INP_PASSIVE = 0,
	378	STATE_INP_ACTIVE = 1,
	379	STATE_INP_HL = 2,
	380	STATE_INP_LH = 4,
	381	STATE_OUT = 128,
	382	STATE_NONEX = 256
	383	};
384	384
385	385
386		ATTR_COLD netlist_core_terminal_t(const type_t atype, const family_t afamily);
	386	ATTR_COLD netlist_core_terminal_t(const type_t atype, const family_t afamily);
387	387
388		//ATTR_COLD void init_object(netlist_core_device_t &dev, const pstring &aname);
	388	//ATTR_COLD void init_object(netlist_core_device_t &dev, const pstring &aname);
389	389
390		ATTR_COLD void set_net(netlist_net_t &anet);
391		ATTR_COLD inline void clear_net() { m_net = NULL; }
392		ATTR_HOT inline bool has_net() const { return (m_net != NULL); }
393		ATTR_HOT inline const netlist_net_t & RESTRICT net() const { return *m_net;}
394		ATTR_HOT inline netlist_net_t & RESTRICT net() { return *m_net;}
	390	ATTR_COLD void set_net(netlist_net_t &anet);
	391	ATTR_COLD inline void clear_net() { m_net = NULL; }
	392	ATTR_HOT inline bool has_net() const { return (m_net != NULL); }
	393	ATTR_HOT inline const netlist_net_t & RESTRICT net() const { return *m_net;}
	394	ATTR_HOT inline netlist_net_t & RESTRICT net() { return *m_net;}
395	395
396		ATTR_HOT inline const bool is_state(const state_e astate) const { return (m_state == astate); }
397		ATTR_HOT inline const state_e state() const { return m_state; }
398		ATTR_HOT inline void set_state(const state_e astate)
399		{
400		assert(astate != STATE_NONEX);
401		m_state = astate;
402		}
	396	ATTR_HOT inline const bool is_state(const state_e astate) const { return (m_state == astate); }
	397	ATTR_HOT inline const state_e state() const { return m_state; }
	398	ATTR_HOT inline void set_state(const state_e astate)
	399	{
	400	assert(astate != STATE_NONEX);
	401	m_state = astate;
	402	}
403	403
404		const netlist_logic_family_desc_t *m_family_desc;
	404	const netlist_logic_family_desc_t *m_family_desc;
405	405
406	406	protected:
407		ATTR_COLD virtual void save_register()
408		{
409		save(NAME(m_state));
410		netlist_owned_object_t::save_register();
411		}
	407	ATTR_COLD virtual void save_register()
	408	{
	409	save(NAME(m_state));
	410	netlist_owned_object_t::save_register();
	411	}
412	412
413	413	private:
414		netlist_net_t * RESTRICT m_net;
415		state_e m_state;
	414	netlist_net_t * RESTRICT m_net;
	415	state_e m_state;
416	416	};
417	417
418	418	NETLIST_SAVE_TYPE(netlist_core_terminal_t::state_e, DT_INT);
r29404	r29405
420	420
421	421	class netlist_terminal_t : public netlist_core_terminal_t
422	422	{
423		NETLIST_PREVENT_COPYING(netlist_terminal_t)
	423	NETLIST_PREVENT_COPYING(netlist_terminal_t)
424	424	public:
425		ATTR_COLD netlist_terminal_t();
	425	ATTR_COLD netlist_terminal_t();
426	426
427		double m_Idr; // drive current
428		double m_go; // conductance for Voltage from other term
429		double m_gt; // conductance for total conductance
	427	double m_Idr; // drive current
	428	double m_go; // conductance for Voltage from other term
	429	double m_gt; // conductance for total conductance
430	430
431		ATTR_HOT inline void set(const double G)
432		{
433		m_Idr = 0;
434		m_go = m_gt = G;
435		}
	431	ATTR_HOT inline void set(const double G)
	432	{
	433	m_Idr = 0;
	434	m_go = m_gt = G;
	435	}
436	436
437		ATTR_HOT inline void set(const double GO, const double GT)
438		{
439		m_Idr = 0;
440		m_go = GO;
441		m_gt = GT;
442		}
	437	ATTR_HOT inline void set(const double GO, const double GT)
	438	{
	439	m_Idr = 0;
	440	m_go = GO;
	441	m_gt = GT;
	442	}
443	443
444		ATTR_HOT inline void set(const double GO, const double GT, const double I)
445		{
446		m_Idr = I;
447		m_go = GO;
448		m_gt = GT;
449		}
	444	ATTR_HOT inline void set(const double GO, const double GT, const double I)
	445	{
	446	m_Idr = I;
	447	m_go = GO;
	448	m_gt = GT;
	449	}
450	450
451	451
452		netlist_terminal_t *m_otherterm;
	452	netlist_terminal_t *m_otherterm;
453	453
454	454	protected:
455		ATTR_COLD virtual void save_register();
	455	ATTR_COLD virtual void save_register();
456	456
457		ATTR_COLD virtual void reset();
	457	ATTR_COLD virtual void reset();
458	458	};
459	459
460	460
r29404	r29405
467	467	public:
468	468
469	469
470		ATTR_COLD netlist_input_t(const type_t atype, const family_t afamily)
471		: netlist_core_terminal_t(atype, afamily)
472		{
473		set_state(STATE_INP_ACTIVE);
474		}
	470	ATTR_COLD netlist_input_t(const type_t atype, const family_t afamily)
	471	: netlist_core_terminal_t(atype, afamily)
	472	{
	473	set_state(STATE_INP_ACTIVE);
	474	}
475	475
476		ATTR_HOT inline void inactivate();
477		ATTR_HOT inline void activate();
478		ATTR_HOT inline void activate_hl();
479		ATTR_HOT inline void activate_lh();
	476	ATTR_HOT inline void inactivate();
	477	ATTR_HOT inline void activate();
	478	ATTR_HOT inline void activate_hl();
	479	ATTR_HOT inline void activate_lh();
480	480
481	481	protected:
482		ATTR_COLD virtual void reset()
483		{
484		//netlist_core_terminal_t::reset();
485		set_state(STATE_INP_ACTIVE);
486		}
	482	ATTR_COLD virtual void reset()
	483	{
	484	//netlist_core_terminal_t::reset();
	485	set_state(STATE_INP_ACTIVE);
	486	}
487	487
488	488	private:
489	489	};
r29404	r29405
495	495	class netlist_logic_input_t : public netlist_input_t
496	496	{
497	497	public:
498		ATTR_COLD netlist_logic_input_t()
499		: netlist_input_t(INPUT, LOGIC)
500		{
501		}
	498	ATTR_COLD netlist_logic_input_t()
	499	: netlist_input_t(INPUT, LOGIC)
	500	{
	501	}
502	502
503		ATTR_HOT inline const netlist_sig_t Q() const;
504		ATTR_HOT inline const netlist_sig_t last_Q() const;
	503	ATTR_HOT inline const netlist_sig_t Q() const;
	504	ATTR_HOT inline const netlist_sig_t last_Q() const;
505	505
506	506	};
507	507
r29404	r29405
512	512	class netlist_ttl_input_t : public netlist_logic_input_t
513	513	{
514	514	public:
515		ATTR_COLD netlist_ttl_input_t()
516		: netlist_logic_input_t() { }
	515	ATTR_COLD netlist_ttl_input_t()
	516	: netlist_logic_input_t() { }
517	517	};
518	518
519	519	// ----------------------------------------------------------------------------------------
r29404	r29405
523	523	class netlist_analog_input_t : public netlist_input_t
524	524	{
525	525	public:
526		ATTR_COLD netlist_analog_input_t()
527		: netlist_input_t(INPUT, ANALOG) { }
	526	ATTR_COLD netlist_analog_input_t()
	527	: netlist_input_t(INPUT, ANALOG) { }
528	528
529		ATTR_HOT inline const double Q_Analog() const;
	529	ATTR_HOT inline const double Q_Analog() const;
530	530	};
531	531
532	532	//#define INPVAL(_x) (_x).Q()
r29404	r29405
537	537
538	538	class netlist_net_t : public netlist_object_t
539	539	{
540		NETLIST_PREVENT_COPYING(netlist_net_t)
	540	NETLIST_PREVENT_COPYING(netlist_net_t)
541	541	public:
542	542
543		typedef netlist_list_t<netlist_net_t *> list_t;
	543	typedef netlist_list_t<netlist_net_t *> list_t;
544	544
545		friend class NETLIB_NAME(mainclock);
546		friend class netlist_matrix_solver_t;
547		friend class netlist_logic_output_t;
548		friend class netlist_analog_output_t;
549		friend class netlist_setup_t;
	545	friend class NETLIB_NAME(mainclock);
	546	friend class netlist_matrix_solver_t;
	547	friend class netlist_logic_output_t;
	548	friend class netlist_analog_output_t;
	549	friend class netlist_setup_t;
550	550
551		ATTR_COLD netlist_net_t(const type_t atype, const family_t afamily);
552		ATTR_COLD virtual ~netlist_net_t();
	551	ATTR_COLD netlist_net_t(const type_t atype, const family_t afamily);
	552	ATTR_COLD virtual ~netlist_net_t();
553	553
554		ATTR_COLD void init_object(netlist_base_t &nl, const pstring &aname);
	554	ATTR_COLD void init_object(netlist_base_t &nl, const pstring &aname);
555	555
556		ATTR_COLD void register_con(netlist_core_terminal_t &terminal);
557		ATTR_COLD void merge_net(netlist_net_t *othernet);
558		ATTR_COLD void register_railterminal(netlist_output_t &mr);
	556	ATTR_COLD void register_con(netlist_core_terminal_t &terminal);
	557	ATTR_COLD void merge_net(netlist_net_t *othernet);
	558	ATTR_COLD void register_railterminal(netlist_output_t &mr);
559	559
560		ATTR_HOT inline void update_devs();
	560	ATTR_HOT inline void update_devs();
561	561
562		ATTR_HOT inline const netlist_time time() const { return m_time; }
563		ATTR_HOT inline void set_time(const netlist_time ntime) { m_time = ntime; }
	562	ATTR_HOT inline const netlist_time time() const { return m_time; }
	563	ATTR_HOT inline void set_time(const netlist_time ntime) { m_time = ntime; }
564	564
565		ATTR_HOT inline bool isRailNet() const { return !(m_railterminal == NULL); }
566		ATTR_HOT inline const netlist_core_terminal_t & RESTRICT railterminal() const { return *m_railterminal; }
	565	ATTR_HOT inline bool isRailNet() const { return !(m_railterminal == NULL); }
	566	ATTR_HOT inline const netlist_core_terminal_t & RESTRICT railterminal() const { return *m_railterminal; }
567	567
568		/* Everything below is used by the logic subsystem */
569		ATTR_HOT void inc_active(netlist_core_terminal_t &term);
570		ATTR_HOT void dec_active(netlist_core_terminal_t &term);
	568	/* Everything below is used by the logic subsystem */
	569	ATTR_HOT void inc_active(netlist_core_terminal_t &term);
	570	ATTR_HOT void dec_active(netlist_core_terminal_t &term);
571	571
572		ATTR_HOT inline const netlist_sig_t Q() const
573		{
574		assert(family() == LOGIC);
575		return m_cur_Q;
576		}
	572	ATTR_HOT inline const netlist_sig_t Q() const
	573	{
	574	assert(family() == LOGIC);
	575	return m_cur_Q;
	576	}
577	577
578		ATTR_HOT inline const netlist_sig_t last_Q() const
579		{
580		assert(family() == LOGIC);
581		return m_last_Q;
582		}
	578	ATTR_HOT inline const netlist_sig_t last_Q() const
	579	{
	580	assert(family() == LOGIC);
	581	return m_last_Q;
	582	}
583	583
584		ATTR_HOT inline const netlist_sig_t new_Q() const
585		{
586		assert(family() == LOGIC);
587		return m_new_Q;
588		}
	584	ATTR_HOT inline const netlist_sig_t new_Q() const
	585	{
	586	assert(family() == LOGIC);
	587	return m_new_Q;
	588	}
589	589
590		ATTR_HOT inline const double Q_Analog() const
591		{
592		//assert(object_type(SIGNAL_MASK) == SIGNAL_ANALOG);
593		assert(family() == ANALOG);
594		return m_cur_Analog;
595		}
	590	ATTR_HOT inline const double Q_Analog() const
	591	{
	592	//assert(object_type(SIGNAL_MASK) == SIGNAL_ANALOG);
	593	assert(family() == ANALOG);
	594	return m_cur_Analog;
	595	}
596	596
597		ATTR_HOT inline void push_to_queue(const netlist_time delay);
598		ATTR_HOT bool inline is_queued() const { return m_in_queue == 1; }
	597	ATTR_HOT inline void push_to_queue(const netlist_time delay);
	598	ATTR_HOT bool inline is_queued() const { return m_in_queue == 1; }
599	599
600		/* internal state support
601		* FIXME: get rid of this and implement export/import in MAME
602		*/
603		ATTR_COLD inline netlist_sig_t &Q_state_ptr()
604		{
605		assert(family() == LOGIC);
606		return m_cur_Q;
607		}
	600	/* internal state support
	601	* FIXME: get rid of this and implement export/import in MAME
	602	*/
	603	ATTR_COLD inline netlist_sig_t &Q_state_ptr()
	604	{
	605	assert(family() == LOGIC);
	606	return m_cur_Q;
	607	}
608	608
609		ATTR_COLD inline double &Q_Analog_state_ptr()
610		{
611		//assert(object_type(SIGNAL_MASK) == SIGNAL_ANALOG);
612		assert(family() == ANALOG);
613		return m_cur_Analog;
614		}
	609	ATTR_COLD inline double &Q_Analog_state_ptr()
	610	{
	611	//assert(object_type(SIGNAL_MASK) == SIGNAL_ANALOG);
	612	assert(family() == ANALOG);
	613	return m_cur_Analog;
	614	}
615	615
616		ATTR_HOT inline int num_cons() const { return m_num_cons; }
	616	ATTR_HOT inline int num_cons() const { return m_num_cons; }
617	617
618		// m_terms is only used by analog subsystem
619		typedef netlist_list_t<netlist_terminal_t *> terminal_list_t;
	618	// m_terms is only used by analog subsystem
	619	typedef netlist_list_t<netlist_terminal_t *> terminal_list_t;
620	620
621		terminal_list_t m_terms;
622		terminal_list_t m_rails;
623		netlist_matrix_solver_t *m_solver;
624		netlist_core_terminal_t * RESTRICT m_railterminal;
	621	terminal_list_t m_terms;
	622	terminal_list_t m_rails;
	623	netlist_matrix_solver_t *m_solver;
	624	netlist_core_terminal_t * RESTRICT m_railterminal;
625	625
626		ATTR_HOT void solve();
	626	ATTR_HOT void solve();
627	627
628		netlist_list_t<netlist_core_terminal_t *> m_registered; // save post-start m_list ...
629		plinked_list<netlist_core_terminal_t> m_list;
	628	netlist_list_t<netlist_core_terminal_t *> m_registered; // save post-start m_list ...
	629	plinked_list<netlist_core_terminal_t> m_list;
630	630
631		ATTR_COLD void rebuild_list(); /* rebuild m_list after a load */
	631	ATTR_COLD void rebuild_list(); /* rebuild m_list after a load */
632	632
633	633	protected: //FIXME: needed by current solver code
634	634
635		UINT16 m_num_cons;
	635	UINT16 m_num_cons;
636	636
637		ATTR_COLD virtual void save_register();
638		ATTR_COLD virtual void reset();
	637	ATTR_COLD virtual void save_register();
	638	ATTR_COLD virtual void reset();
639	639
640	640
641	641	private:
642		netlist_sig_t m_new_Q;
643		netlist_sig_t m_cur_Q;
644		netlist_sig_t m_last_Q;
	642	netlist_sig_t m_new_Q;
	643	netlist_sig_t m_cur_Q;
	644	netlist_sig_t m_last_Q;
645	645
646		netlist_time m_time;
647		INT32 m_active;
648		UINT8 m_in_queue; /* 0: not in queue, 1: in queue, 2: last was taken */
	646	netlist_time m_time;
	647	INT32 m_active;
	648	UINT8 m_in_queue; /* 0: not in queue, 1: in queue, 2: last was taken */
649	649
650	650	public:
651		double m_last_Analog;
652		double m_cur_Analog;
653		double m_new_Analog;
	651	double m_last_Analog;
	652	double m_cur_Analog;
	653	double m_new_Analog;
654	654
655	655	};
656	656
r29404	r29405
661	661
662	662	class netlist_output_t : public netlist_core_terminal_t
663	663	{
664		NETLIST_PREVENT_COPYING(netlist_output_t)
	664	NETLIST_PREVENT_COPYING(netlist_output_t)
665	665	public:
666	666
667		ATTR_COLD netlist_output_t(const type_t atype, const family_t afamily);
668		ATTR_COLD virtual ~netlist_output_t() {}
	667	ATTR_COLD netlist_output_t(const type_t atype, const family_t afamily);
	668	ATTR_COLD virtual ~netlist_output_t() {}
669	669
670		ATTR_COLD void init_object(netlist_core_device_t &dev, const pstring &aname);
671		ATTR_COLD virtual void reset()
672		{
673		//netlist_core_terminal_t::reset();
674		set_state(STATE_OUT);
675		}
	670	ATTR_COLD void init_object(netlist_core_device_t &dev, const pstring &aname);
	671	ATTR_COLD virtual void reset()
	672	{
	673	//netlist_core_terminal_t::reset();
	674	set_state(STATE_OUT);
	675	}
676	676
677	677	private:
678		netlist_net_t m_my_net;
	678	netlist_net_t m_my_net;
679	679	};
680	680
681	681
682	682	class netlist_logic_output_t : public netlist_output_t
683	683	{
684		NETLIST_PREVENT_COPYING(netlist_logic_output_t)
	684	NETLIST_PREVENT_COPYING(netlist_logic_output_t)
685	685	public:
686	686
687		ATTR_COLD netlist_logic_output_t();
	687	ATTR_COLD netlist_logic_output_t();
688	688
689		ATTR_COLD void initial(const netlist_sig_t val);
	689	ATTR_COLD void initial(const netlist_sig_t val);
690	690
691		ATTR_COLD bool has_proxy() const { return (m_proxy != NULL); }
692		ATTR_COLD nld_base_d_to_a_proxy *get_proxy() const { return m_proxy; }
693		ATTR_COLD void set_proxy(nld_base_d_to_a_proxy *proxy) { m_proxy = proxy; }
	691	ATTR_COLD bool has_proxy() const { return (m_proxy != NULL); }
	692	ATTR_COLD nld_base_d_to_a_proxy *get_proxy() const { return m_proxy; }
	693	ATTR_COLD void set_proxy(nld_base_d_to_a_proxy *proxy) { m_proxy = proxy; }
694	694
695		ATTR_HOT inline void set_Q(const netlist_sig_t newQ, const netlist_time delay)
696		{
697		if (EXPECTED(newQ != net().m_new_Q))
698		{
699		net().m_new_Q = newQ;
700		net().push_to_queue(delay);
701		}
702		}
	695	ATTR_HOT inline void set_Q(const netlist_sig_t newQ, const netlist_time delay)
	696	{
	697	if (EXPECTED(newQ != net().m_new_Q))
	698	{
	699	net().m_new_Q = newQ;
	700	net().push_to_queue(delay);
	701	}
	702	}
703	703	private:
704		nld_base_d_to_a_proxy *m_proxy;
	704	nld_base_d_to_a_proxy *m_proxy;
705	705	};
706	706
707	707	class netlist_ttl_output_t : public netlist_logic_output_t
708	708	{
709	709	public:
710	710
711		ATTR_COLD netlist_ttl_output_t();
	711	ATTR_COLD netlist_ttl_output_t();
712	712
713	713	};
714	714
715	715	class netlist_analog_output_t : public netlist_output_t
716	716	{
717		NETLIST_PREVENT_COPYING(netlist_analog_output_t)
	717	NETLIST_PREVENT_COPYING(netlist_analog_output_t)
718	718	public:
719	719
720		ATTR_COLD netlist_analog_output_t();
	720	ATTR_COLD netlist_analog_output_t();
721	721
722		ATTR_COLD void initial(const double val);
	722	ATTR_COLD void initial(const double val);
723	723
724		ATTR_HOT inline void set_Q(const double newQ, const netlist_time delay)
725		{
726		if (newQ != net().m_new_Analog)
727		{
728		net().m_new_Analog = newQ;
729		net().push_to_queue(delay);
730		}
731		}
	724	ATTR_HOT inline void set_Q(const double newQ, const netlist_time delay)
	725	{
	726	if (newQ != net().m_new_Analog)
	727	{
	728	net().m_new_Analog = newQ;
	729	net().push_to_queue(delay);
	730	}
	731	}
732	732
733	733	};
734	734
r29404	r29405
738	738
739	739	class netlist_param_t : public netlist_owned_object_t
740	740	{
741		NETLIST_PREVENT_COPYING(netlist_param_t)
	741	NETLIST_PREVENT_COPYING(netlist_param_t)
742	742	public:
743	743
744		enum param_type_t {
745		MODEL,
746		STRING,
747		DOUBLE,
748		INTEGER,
749		LOGIC
750		};
	744	enum param_type_t {
	745	MODEL,
	746	STRING,
	747	DOUBLE,
	748	INTEGER,
	749	LOGIC
	750	};
751	751
752		ATTR_COLD netlist_param_t(const param_type_t atype);
	752	ATTR_COLD netlist_param_t(const param_type_t atype);
753	753
754		ATTR_HOT inline const param_type_t param_type() const { return m_param_type; }
	754	ATTR_HOT inline const param_type_t param_type() const { return m_param_type; }
755	755
756	756	protected:
757	757
758		ATTR_COLD virtual void reset() { }
	758	ATTR_COLD virtual void reset() { }
759	759
760	760	private:
761		const param_type_t m_param_type;
	761	const param_type_t m_param_type;
762	762	};
763	763
764	764	class netlist_param_double_t : public netlist_param_t
765	765	{
766		NETLIST_PREVENT_COPYING(netlist_param_double_t)
	766	NETLIST_PREVENT_COPYING(netlist_param_double_t)
767	767	public:
768		ATTR_COLD netlist_param_double_t();
	768	ATTR_COLD netlist_param_double_t();
769	769
770		ATTR_HOT inline void setTo(const double param);
771		ATTR_COLD inline void initial(const double val) { m_param = val; }
772		ATTR_HOT inline const double Value() const { return m_param; }
	770	ATTR_HOT inline void setTo(const double param);
	771	ATTR_COLD inline void initial(const double val) { m_param = val; }
	772	ATTR_HOT inline const double Value() const { return m_param; }
773	773
774	774	protected:
775		ATTR_COLD virtual void save_register()
776		{
777		save(NAME(m_param));
778		netlist_param_t::save_register();
779		}
	775	ATTR_COLD virtual void save_register()
	776	{
	777	save(NAME(m_param));
	778	netlist_param_t::save_register();
	779	}
780	780
781	781	private:
782		double m_param;
	782	double m_param;
783	783	};
784	784
785	785	class netlist_param_int_t : public netlist_param_t
786	786	{
787		NETLIST_PREVENT_COPYING(netlist_param_int_t)
	787	NETLIST_PREVENT_COPYING(netlist_param_int_t)
788	788	public:
789		ATTR_COLD netlist_param_int_t();
	789	ATTR_COLD netlist_param_int_t();
790	790
791		ATTR_HOT inline void setTo(const int param);
792		ATTR_COLD inline void initial(const int val) { m_param = val; }
	791	ATTR_HOT inline void setTo(const int param);
	792	ATTR_COLD inline void initial(const int val) { m_param = val; }
793	793
794		ATTR_HOT inline const int Value() const { return m_param; }
	794	ATTR_HOT inline const int Value() const { return m_param; }
795	795
796	796	protected:
797		ATTR_COLD virtual void save_register()
798		{
799		save(NAME(m_param));
800		netlist_param_t::save_register();
801		}
	797	ATTR_COLD virtual void save_register()
	798	{
	799	save(NAME(m_param));
	800	netlist_param_t::save_register();
	801	}
802	802
803	803	private:
804		int m_param;
	804	int m_param;
805	805	};
806	806
807	807	class netlist_param_logic_t : public netlist_param_int_t
808	808	{
809		NETLIST_PREVENT_COPYING(netlist_param_logic_t)
	809	NETLIST_PREVENT_COPYING(netlist_param_logic_t)
810	810	public:
811		ATTR_COLD netlist_param_logic_t();
	811	ATTR_COLD netlist_param_logic_t();
812	812	};
813	813
814	814	class netlist_param_str_t : public netlist_param_t
815	815	{
816		NETLIST_PREVENT_COPYING(netlist_param_str_t)
	816	NETLIST_PREVENT_COPYING(netlist_param_str_t)
817	817	public:
818		ATTR_COLD netlist_param_str_t();
	818	ATTR_COLD netlist_param_str_t();
819	819
820		ATTR_HOT inline void setTo(const pstring &param);
821		ATTR_COLD inline void initial(const pstring &val) { m_param = val; }
	820	ATTR_HOT inline void setTo(const pstring &param);
	821	ATTR_COLD inline void initial(const pstring &val) { m_param = val; }
822	822
823		ATTR_HOT inline const pstring &Value() const { return m_param; }
	823	ATTR_HOT inline const pstring &Value() const { return m_param; }
824	824
825	825	private:
826		pstring m_param;
	826	pstring m_param;
827	827	};
828	828
829	829	class netlist_param_model_t : public netlist_param_t
830	830	{
831		NETLIST_PREVENT_COPYING(netlist_param_model_t)
	831	NETLIST_PREVENT_COPYING(netlist_param_model_t)
832	832	public:
833		ATTR_COLD netlist_param_model_t();
	833	ATTR_COLD netlist_param_model_t();
834	834
835		ATTR_COLD inline void initial(const pstring &val) { m_param = val; }
	835	ATTR_COLD inline void initial(const pstring &val) { m_param = val; }
836	836
837		ATTR_HOT inline const pstring &Value() const { return m_param; }
	837	ATTR_HOT inline const pstring &Value() const { return m_param; }
838	838
839		/* these should be cached! */
840		ATTR_COLD double model_value(const pstring &entity, const double defval = 0.0) const;
841		ATTR_COLD const pstring model_type() const;
	839	/* these should be cached! */
	840	ATTR_COLD double model_value(const pstring &entity, const double defval = 0.0) const;
	841	ATTR_COLD const pstring model_type() const;
842	842
843	843	private:
844		pstring m_param;
	844	pstring m_param;
845	845	};
846	846
847	847	// ----------------------------------------------------------------------------------------
r29404	r29405
850	850
851	851	class netlist_core_device_t : public netlist_object_t
852	852	{
853		NETLIST_PREVENT_COPYING(netlist_core_device_t)
	853	NETLIST_PREVENT_COPYING(netlist_core_device_t)
854	854	public:
855	855
856		typedef netlist_list_t<netlist_core_device_t *> list_t;
	856	typedef netlist_list_t<netlist_core_device_t *> list_t;
857	857
858		//ATTR_COLD netlist_core_device_t();
859		ATTR_COLD netlist_core_device_t(const family_t afamily);
860		ATTR_COLD netlist_core_device_t(const netlist_logic_family_desc_t *family_desc);
	858	//ATTR_COLD netlist_core_device_t();
	859	ATTR_COLD netlist_core_device_t(const family_t afamily);
	860	ATTR_COLD netlist_core_device_t(const netlist_logic_family_desc_t *family_desc);
861	861
862		ATTR_COLD virtual ~netlist_core_device_t();
	862	ATTR_COLD virtual ~netlist_core_device_t();
863	863
864		ATTR_COLD virtual void init(netlist_base_t &anetlist, const pstring &name);
865		ATTR_HOT virtual void update_param() {}
	864	ATTR_COLD virtual void init(netlist_base_t &anetlist, const pstring &name);
	865	ATTR_HOT virtual void update_param() {}
866	866
867		ATTR_HOT inline void update_dev()
868		{
	867	ATTR_HOT inline void update_dev()
	868	{
869	869	#if USE_PMFDELEGATES
870		static_update(this);
	870	static_update(this);
871	871	#else
872		update();
	872	update();
873	873	#endif
874		}
875		ATTR_HOT inline void start_dev()
876		{
877		start();
878		}
	874	}
	875	ATTR_HOT inline void start_dev()
	876	{
	877	start();
	878	}
879	879
880		ATTR_HOT const netlist_sig_t INPLOGIC_PASSIVE(netlist_logic_input_t &inp);
	880	ATTR_HOT const netlist_sig_t INPLOGIC_PASSIVE(netlist_logic_input_t &inp);
881	881
882		ATTR_HOT inline const netlist_sig_t INPLOGIC(const netlist_logic_input_t &inp) const
883		{
884		assert(inp.state() != netlist_input_t::STATE_INP_PASSIVE);
885		return inp.Q();
886		}
	882	ATTR_HOT inline const netlist_sig_t INPLOGIC(const netlist_logic_input_t &inp) const
	883	{
	884	assert(inp.state() != netlist_input_t::STATE_INP_PASSIVE);
	885	return inp.Q();
	886	}
887	887
888		ATTR_HOT inline void OUTLOGIC(netlist_logic_output_t &out, const netlist_sig_t val, const netlist_time delay)
889		{
890		out.set_Q(val, delay);
891		}
	888	ATTR_HOT inline void OUTLOGIC(netlist_logic_output_t &out, const netlist_sig_t val, const netlist_time delay)
	889	{
	890	out.set_Q(val, delay);
	891	}
892	892
893		ATTR_HOT inline bool INP_HL(const netlist_logic_input_t &inp) const
894		{
895		return ((inp.last_Q() & !inp.Q()) == 1);
896		}
	893	ATTR_HOT inline bool INP_HL(const netlist_logic_input_t &inp) const
	894	{
	895	return ((inp.last_Q() & !inp.Q()) == 1);
	896	}
897	897
898		ATTR_HOT inline bool INP_LH(const netlist_logic_input_t &inp) const
899		{
900		return ((!inp.last_Q() & inp.Q()) == 1);
901		}
	898	ATTR_HOT inline bool INP_LH(const netlist_logic_input_t &inp) const
	899	{
	900	return ((!inp.last_Q() & inp.Q()) == 1);
	901	}
902	902
903		ATTR_HOT inline const double INPANALOG(const netlist_analog_input_t &inp) const { return inp.Q_Analog(); }
	903	ATTR_HOT inline const double INPANALOG(const netlist_analog_input_t &inp) const { return inp.Q_Analog(); }
904	904
905		ATTR_HOT inline const double TERMANALOG(const netlist_terminal_t &term) const { return term.net().Q_Analog(); }
	905	ATTR_HOT inline const double TERMANALOG(const netlist_terminal_t &term) const { return term.net().Q_Analog(); }
906	906
907		ATTR_HOT inline void OUTANALOG(netlist_analog_output_t &out, const double val, const netlist_time delay)
908		{
909		out.set_Q(val, delay);
910		}
	907	ATTR_HOT inline void OUTANALOG(netlist_analog_output_t &out, const double val, const netlist_time delay)
	908	{
	909	out.set_Q(val, delay);
	910	}
911	911
912		ATTR_HOT virtual void inc_active() { }
	912	ATTR_HOT virtual void inc_active() { }
913	913
914		ATTR_HOT virtual void dec_active() { }
	914	ATTR_HOT virtual void dec_active() { }
915	915
916		ATTR_HOT virtual void step_time(const double st) { }
917		ATTR_HOT virtual void update_terminals() { }
	916	ATTR_HOT virtual void step_time(const double st) { }
	917	ATTR_HOT virtual void update_terminals() { }
918	918
919	919
920	920
921	921	#if (NL_KEEP_STATISTICS)
922		/* stats */
923		osd_ticks_t total_time;
924		INT32 stat_count;
	922	/* stats */
	923	osd_ticks_t total_time;
	924	INT32 stat_count;
925	925	#endif
926	926
927	927	#if USE_PMFDELEGATES
928		net_update_delegate static_update;
	928	net_update_delegate static_update;
929	929	#endif
930	930
931		const netlist_logic_family_desc_t *m_family_desc;
	931	const netlist_logic_family_desc_t *m_family_desc;
932	932
933	933	protected:
934	934
935		ATTR_HOT virtual void update() { }
936		ATTR_COLD virtual void start() { }
	935	ATTR_HOT virtual void update() { }
	936	ATTR_COLD virtual void start() { }
937	937
938	938	private:
939	939	};
r29404	r29405
941	941
942	942	class netlist_device_t : public netlist_core_device_t
943	943	{
944		NETLIST_PREVENT_COPYING(netlist_device_t)
	944	NETLIST_PREVENT_COPYING(netlist_device_t)
945	945	public:
946	946
947		ATTR_COLD netlist_device_t();
948		ATTR_COLD netlist_device_t(const family_t afamily);
	947	ATTR_COLD netlist_device_t();
	948	ATTR_COLD netlist_device_t(const family_t afamily);
949	949
950		ATTR_COLD virtual ~netlist_device_t();
	950	ATTR_COLD virtual ~netlist_device_t();
951	951
952		ATTR_COLD virtual void init(netlist_base_t &anetlist, const pstring &name);
	952	ATTR_COLD virtual void init(netlist_base_t &anetlist, const pstring &name);
953	953
954		ATTR_COLD netlist_setup_t &setup();
	954	ATTR_COLD netlist_setup_t &setup();
955	955
956		ATTR_COLD void register_sub(netlist_device_t &dev, const pstring &name);
957		ATTR_COLD void register_subalias(const pstring &name, netlist_core_terminal_t &term);
958		ATTR_COLD void register_terminal(const pstring &name, netlist_terminal_t &port);
959		ATTR_COLD void register_output(const pstring &name, netlist_output_t &out);
960		ATTR_COLD void register_input(const pstring &name, netlist_input_t &in);
	956	ATTR_COLD void register_sub(netlist_device_t &dev, const pstring &name);
	957	ATTR_COLD void register_subalias(const pstring &name, netlist_core_terminal_t &term);
	958	ATTR_COLD void register_terminal(const pstring &name, netlist_terminal_t &port);
	959	ATTR_COLD void register_output(const pstring &name, netlist_output_t &out);
	960	ATTR_COLD void register_input(const pstring &name, netlist_input_t &in);
961	961
962		ATTR_COLD void connect(netlist_core_terminal_t &t1, netlist_core_terminal_t &t2);
	962	ATTR_COLD void connect(netlist_core_terminal_t &t1, netlist_core_terminal_t &t2);
963	963
964		netlist_list_t<pstring, 20> m_terminals;
	964	netlist_list_t<pstring, 20> m_terminals;
965	965
966	966	protected:
967	967
968		ATTR_HOT virtual void update() { }
969		ATTR_HOT virtual void start() { }
970		ATTR_HOT virtual void update_terminals() { }
	968	ATTR_HOT virtual void update() { }
	969	ATTR_HOT virtual void start() { }
	970	ATTR_HOT virtual void update_terminals() { }
971	971
972		template <class C, class T>
973		ATTR_COLD void register_param(const pstring &sname, C &param, const T initialVal);
	972	template <class C, class T>
	973	ATTR_COLD void register_param(const pstring &sname, C &param, const T initialVal);
974	974
975	975	private:
976	976	};
r29404	r29405
981	981	// ----------------------------------------------------------------------------------------
982	982
983	983	class netlist_queue_t : public netlist_timed_queue<netlist_net_t *, netlist_time, 512>,
984		public pstate_callback_t
	984	public pstate_callback_t
985	985	{
986	986	public:
987	987
988		netlist_queue_t(netlist_base_t &nl);
	988	netlist_queue_t(netlist_base_t &nl);
989	989
990		void register_state(pstate_manager_t &manager, const pstring &module);
991		void on_pre_save();
992		void on_post_load();
	990	void register_state(pstate_manager_t &manager, const pstring &module);
	991	void on_pre_save();
	992	void on_post_load();
993	993
994		pstate_callback_t &callback() { return *this; }
	994	pstate_callback_t &callback() { return *this; }
995	995
996	996	private:
997		netlist_base_t &m_netlist;
998		int m_qsize;
999		netlist_time::INTERNALTYPE m_times[512];
1000		char m_name[512][64];
	997	netlist_base_t &m_netlist;
	998	int m_qsize;
	999	netlist_time::INTERNALTYPE m_times[512];
	1000	char m_name[512][64];
1001	1001	};
1002	1002
1003	1003	// ----------------------------------------------------------------------------------------
r29404	r29405
1009	1009
1010	1010	class netlist_base_t : public netlist_object_t, public pstate_manager_t
1011	1011	{
1012		NETLIST_PREVENT_COPYING(netlist_base_t)
	1012	NETLIST_PREVENT_COPYING(netlist_base_t)
1013	1013	public:
1014	1014
1015		netlist_base_t();
1016		virtual ~netlist_base_t();
	1015	netlist_base_t();
	1016	virtual ~netlist_base_t();
1017	1017
1018		ATTR_COLD void start();
	1018	ATTR_COLD void start();
1019	1019
1020		ATTR_HOT inline const netlist_queue_t &queue() const { return m_queue; }
1021		ATTR_HOT inline netlist_queue_t &queue() { return m_queue; }
1022		ATTR_HOT inline const netlist_time time() const { return m_time; }
1023		ATTR_HOT inline NETLIB_NAME(solver) *solver() const { return m_solver; }
1024		ATTR_HOT inline NETLIB_NAME(gnd) *gnd() const { return m_gnd; }
1025		ATTR_HOT const double gmin() const;
	1020	ATTR_HOT inline const netlist_queue_t &queue() const { return m_queue; }
	1021	ATTR_HOT inline netlist_queue_t &queue() { return m_queue; }
	1022	ATTR_HOT inline const netlist_time time() const { return m_time; }
	1023	ATTR_HOT inline NETLIB_NAME(solver) *solver() const { return m_solver; }
	1024	ATTR_HOT inline NETLIB_NAME(gnd) *gnd() const { return m_gnd; }
	1025	ATTR_HOT const double gmin() const;
1026	1026
1027		ATTR_HOT inline void push_to_queue(netlist_net_t *out, const netlist_time attime)
1028		{
1029		m_queue.push(netlist_queue_t::entry_t(attime, out));
1030		}
	1027	ATTR_HOT inline void push_to_queue(netlist_net_t *out, const netlist_time attime)
	1028	{
	1029	m_queue.push(netlist_queue_t::entry_t(attime, out));
	1030	}
1031	1031
1032		ATTR_HOT void process_queue(const netlist_time delta);
1033		ATTR_HOT inline void abort_current_queue_slice() { m_stop = netlist_time::zero; }
	1032	ATTR_HOT void process_queue(const netlist_time delta);
	1033	ATTR_HOT inline void abort_current_queue_slice() { m_stop = netlist_time::zero; }
1034	1034
1035		ATTR_COLD void rebuild_lists(); /* must be called after post_load ! */
	1035	ATTR_COLD void rebuild_lists(); /* must be called after post_load ! */
1036	1036
1037		ATTR_COLD void set_setup(netlist_setup_t *asetup) { m_setup = asetup; }
1038		ATTR_COLD netlist_setup_t &setup() { return *m_setup; }
	1037	ATTR_COLD void set_setup(netlist_setup_t *asetup) { m_setup = asetup; }
	1038	ATTR_COLD netlist_setup_t &setup() { return *m_setup; }
1039	1039
1040		ATTR_COLD netlist_net_t *find_net(const pstring &name);
	1040	ATTR_COLD netlist_net_t *find_net(const pstring &name);
1041	1041
1042		ATTR_COLD void error(const char *format, ...) const ATTR_PRINTF(2,3);
1043		ATTR_COLD void warning(const char *format, ...) const ATTR_PRINTF(2,3);
1044		ATTR_COLD void log(const char *format, ...) const ATTR_PRINTF(2,3);
	1042	ATTR_COLD void error(const char *format, ...) const ATTR_PRINTF(2,3);
	1043	ATTR_COLD void warning(const char *format, ...) const ATTR_PRINTF(2,3);
	1044	ATTR_COLD void log(const char *format, ...) const ATTR_PRINTF(2,3);
1045	1045
1046		template<class _C>
1047		netlist_list_t<_C *> get_device_list()
1048		{
1049		netlist_list_t<_C *> tmp;
1050		for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
1051		{
1052		_C dev = dynamic_cast<_C >(entry->object());
1053		if (dev != NULL)
1054		tmp.add(dev);
1055		}
1056		return tmp;
1057		}
	1046	template<class _C>
	1047	netlist_list_t<_C *> get_device_list()
	1048	{
	1049	netlist_list_t<_C *> tmp;
	1050	for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
	1051	{
	1052	_C dev = dynamic_cast<_C >(entry->object());
	1053	if (dev != NULL)
	1054	tmp.add(dev);
	1055	}
	1056	return tmp;
	1057	}
1058	1058
1059		template<class _C>
1060		_C *get_first_device()
1061		{
1062		for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
1063		{
1064		_C dev = dynamic_cast<_C >(entry->object());
1065		if (dev != NULL)
1066		return dev;
1067		}
1068		return NULL;
1069		}
	1059	template<class _C>
	1060	_C *get_first_device()
	1061	{
	1062	for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
	1063	{
	1064	_C dev = dynamic_cast<_C >(entry->object());
	1065	if (dev != NULL)
	1066	return dev;
	1067	}
	1068	return NULL;
	1069	}
1070	1070
1071		template<class _C>
1072		_C get_single_device(const char classname)
1073		{
1074		_C *ret = NULL;
1075		for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
1076		{
1077		_C dev = dynamic_cast<_C >(entry->object());
1078		if (dev != NULL)
1079		{
1080		if (ret != NULL)
1081		this->error("more than one %s device found", classname);
1082		else
1083		ret = dev;
1084		}
1085		}
1086		return ret;
1087		}
	1071	template<class _C>
	1072	_C get_single_device(const char classname)
	1073	{
	1074	_C *ret = NULL;
	1075	for (tagmap_devices_t::entry_t *entry = m_devices.first(); entry != NULL; entry = m_devices.next(entry))
	1076	{
	1077	_C dev = dynamic_cast<_C >(entry->object());
	1078	if (dev != NULL)
	1079	{
	1080	if (ret != NULL)
	1081	this->error("more than one %s device found", classname);
	1082	else
	1083	ret = dev;
	1084	}
	1085	}
	1086	return ret;
	1087	}
1088	1088
1089		tagmap_devices_t m_devices;
1090		netlist_net_t::list_t m_nets;
	1089	tagmap_devices_t m_devices;
	1090	netlist_net_t::list_t m_nets;
1091	1091
1092	1092	protected:
1093	1093
1094		enum loglevel_e
1095		{
1096		NL_ERROR,
1097		NL_WARNING,
1098		NL_LOG,
1099		};
	1094	enum loglevel_e
	1095	{
	1096	NL_ERROR,
	1097	NL_WARNING,
	1098	NL_LOG,
	1099	};
1100	1100
1101		// any derived netlist must override this ...
1102		ATTR_COLD virtual void verror(const loglevel_e level,
1103		const char *format, va_list ap) const = 0;
	1101	// any derived netlist must override this ...
	1102	ATTR_COLD virtual void verror(const loglevel_e level,
	1103	const char *format, va_list ap) const = 0;
1104	1104
1105		/* from netlist_object */
1106		ATTR_COLD virtual void reset();
1107		ATTR_COLD virtual void save_register();
	1105	/* from netlist_object */
	1106	ATTR_COLD virtual void reset();
	1107	ATTR_COLD virtual void save_register();
1108	1108
1109	1109	#if (NL_KEEP_STATISTICS)
1110		// performance
1111		int m_perf_out_processed;
1112		int m_perf_inp_processed;
1113		int m_perf_inp_active;
	1110	// performance
	1111	int m_perf_out_processed;
	1112	int m_perf_inp_processed;
	1113	int m_perf_inp_active;
1114	1114	#endif
1115	1115
1116	1116	private:
1117		netlist_time m_stop; // target time for current queue processing
	1117	netlist_time m_stop; // target time for current queue processing
1118	1118
1119		netlist_time m_time;
1120		netlist_queue_t m_queue;
	1119	netlist_time m_time;
	1120	netlist_queue_t m_queue;
1121	1121
1122		NETLIB_NAME(mainclock) * m_mainclock;
1123		NETLIB_NAME(solver) * m_solver;
1124		NETLIB_NAME(gnd) * m_gnd;
	1122	NETLIB_NAME(mainclock) * m_mainclock;
	1123	NETLIB_NAME(solver) * m_solver;
	1124	NETLIB_NAME(gnd) * m_gnd;
1125	1125
1126		netlist_setup_t *m_setup;
	1126	netlist_setup_t *m_setup;
1127	1127	};
1128	1128
1129	1129	// ----------------------------------------------------------------------------------------
r29404	r29405
1134	1134
1135	1135	ATTR_HOT inline void netlist_param_str_t::setTo(const pstring &param)
1136	1136	{
1137		m_param = param;
1138		netdev().update_param();
	1137	m_param = param;
	1138	netdev().update_param();
1139	1139	}
1140	1140
1141	1141	ATTR_HOT inline void netlist_param_int_t::setTo(const int param)
1142	1142	{
1143		if (m_param != param)
1144		{
1145		m_param = param;
1146		netdev().update_param();
1147		}
	1143	if (m_param != param)
	1144	{
	1145	m_param = param;
	1146	netdev().update_param();
	1147	}
1148	1148	}
1149	1149
1150	1150	ATTR_HOT inline void netlist_param_double_t::setTo(const double param)
1151	1151	{
1152		if (m_param != param)
1153		{
1154		m_param = param;
1155		netdev().update_param();
1156		}
	1152	if (m_param != param)
	1153	{
	1154	m_param = param;
	1155	netdev().update_param();
	1156	}
1157	1157	}
1158	1158
1159	1159
1160	1160	ATTR_HOT inline void netlist_input_t::inactivate()
1161	1161	{
1162		if (EXPECTED(!is_state(STATE_INP_PASSIVE)))
1163		{
1164		set_state(STATE_INP_PASSIVE);
1165		net().dec_active(*this);
1166		}
	1162	if (EXPECTED(!is_state(STATE_INP_PASSIVE)))
	1163	{
	1164	set_state(STATE_INP_PASSIVE);
	1165	net().dec_active(*this);
	1166	}
1167	1167	}
1168	1168
1169	1169	ATTR_HOT inline void netlist_input_t::activate()
1170	1170	{
1171		if (is_state(STATE_INP_PASSIVE))
1172		{
1173		net().inc_active(*this);
1174		set_state(STATE_INP_ACTIVE);
1175		}
	1171	if (is_state(STATE_INP_PASSIVE))
	1172	{
	1173	net().inc_active(*this);
	1174	set_state(STATE_INP_ACTIVE);
	1175	}
1176	1176	}
1177	1177
1178	1178	ATTR_HOT inline void netlist_input_t::activate_hl()
1179	1179	{
1180		if (is_state(STATE_INP_PASSIVE))
1181		{
1182		net().inc_active(*this);
1183		set_state(STATE_INP_HL);
1184		}
	1180	if (is_state(STATE_INP_PASSIVE))
	1181	{
	1182	net().inc_active(*this);
	1183	set_state(STATE_INP_HL);
	1184	}
1185	1185	}
1186	1186
1187	1187	ATTR_HOT inline void netlist_input_t::activate_lh()
1188	1188	{
1189		if (is_state(STATE_INP_PASSIVE))
1190		{
1191		net().inc_active(*this);
1192		set_state(STATE_INP_LH);
1193		}
	1189	if (is_state(STATE_INP_PASSIVE))
	1190	{
	1191	net().inc_active(*this);
	1192	set_state(STATE_INP_LH);
	1193	}
1194	1194	}
1195	1195
1196	1196
1197	1197	ATTR_HOT inline void netlist_net_t::push_to_queue(const netlist_time delay)
1198	1198	{
1199		//if (UNEXPECTED(m_num_cons == 0 \|\| is_queued()))
1200		if (!is_queued())
1201		{
1202		m_time = netlist().time() + delay;
1203		m_in_queue = (m_active > 0); /* queued ? */
1204		if (EXPECTED(m_in_queue))
1205		{
1206		netlist().push_to_queue(this, m_time);
1207		}
1208		}
	1199	//if (UNEXPECTED(m_num_cons == 0 \|\| is_queued()))
	1200	if (!is_queued())
	1201	{
	1202	m_time = netlist().time() + delay;
	1203	m_in_queue = (m_active > 0); /* queued ? */
	1204	if (EXPECTED(m_in_queue))
	1205	{
	1206	netlist().push_to_queue(this, m_time);
	1207	}
	1208	}
1209	1209	}
1210	1210
1211	1211
1212	1212	ATTR_HOT inline const netlist_sig_t netlist_logic_input_t::Q() const
1213	1213	{
1214		return net().Q();
	1214	return net().Q();
1215	1215	}
1216	1216
1217	1217	ATTR_HOT inline const netlist_sig_t netlist_logic_input_t::last_Q() const
1218	1218	{
1219		return net().last_Q();
	1219	return net().last_Q();
1220	1220	}
1221	1221
1222	1222	ATTR_HOT inline const double netlist_analog_input_t::Q_Analog() const
1223	1223	{
1224		return net().Q_Analog();
	1224	return net().Q_Analog();
1225	1225	}
1226	1226
1227	1227
r29404	r29405
1231	1231
1232	1232	class net_device_t_base_factory
1233	1233	{
1234		NETLIST_PREVENT_COPYING(net_device_t_base_factory)
	1234	NETLIST_PREVENT_COPYING(net_device_t_base_factory)
1235	1235	public:
1236		ATTR_COLD net_device_t_base_factory(const pstring &name, const pstring &classname,
1237		const pstring &def_param)
1238		: m_name(name), m_classname(classname), m_def_param(def_param)
1239		{}
	1236	ATTR_COLD net_device_t_base_factory(const pstring &name, const pstring &classname,
	1237	const pstring &def_param)
	1238	: m_name(name), m_classname(classname), m_def_param(def_param)
	1239	{}
1240	1240
1241		ATTR_COLD virtual ~net_device_t_base_factory() {}
	1241	ATTR_COLD virtual ~net_device_t_base_factory() {}
1242	1242
1243		ATTR_COLD virtual netlist_device_t *Create() const = 0;
	1243	ATTR_COLD virtual netlist_device_t *Create() const = 0;
1244	1244
1245		ATTR_COLD const pstring &name() const { return m_name; }
1246		ATTR_COLD const pstring &classname() const { return m_classname; }
1247		ATTR_COLD const pstring &param_desc() const { return m_def_param; }
1248		ATTR_COLD const nl_util::pstring_list term_param_list();
1249		ATTR_COLD const nl_util::pstring_list def_params();
	1245	ATTR_COLD const pstring &name() const { return m_name; }
	1246	ATTR_COLD const pstring &classname() const { return m_classname; }
	1247	ATTR_COLD const pstring &param_desc() const { return m_def_param; }
	1248	ATTR_COLD const nl_util::pstring_list term_param_list();
	1249	ATTR_COLD const nl_util::pstring_list def_params();
1250	1250
1251	1251	protected:
1252		pstring m_name; /* device name */
1253		pstring m_classname; /* device class name */
1254		pstring m_def_param; /* default parameter */
	1252	pstring m_name; /* device name */
	1253	pstring m_classname; /* device class name */
	1254	pstring m_def_param; /* default parameter */
1255	1255	};
1256	1256
1257	1257	template <class C>
1258	1258	class net_device_t_factory : public net_device_t_base_factory
1259	1259	{
1260		NETLIST_PREVENT_COPYING(net_device_t_factory)
	1260	NETLIST_PREVENT_COPYING(net_device_t_factory)
1261	1261	public:
1262		ATTR_COLD net_device_t_factory(const pstring &name, const pstring &classname,
1263		const pstring &def_param)
1264		: net_device_t_base_factory(name, classname, def_param) { }
	1262	ATTR_COLD net_device_t_factory(const pstring &name, const pstring &classname,
	1263	const pstring &def_param)
	1264	: net_device_t_base_factory(name, classname, def_param) { }
1265	1265
1266		ATTR_COLD netlist_device_t *Create() const
1267		{
1268		netlist_device_t *r = new C();
1269		//r->init(setup, name);
1270		return r;
1271		}
	1266	ATTR_COLD netlist_device_t *Create() const
	1267	{
	1268	netlist_device_t *r = new C();
	1269	//r->init(setup, name);
	1270	return r;
	1271	}
1272	1272	};
1273	1273
1274	1274	class netlist_factory_t
1275	1275	{
1276	1276	public:
1277		typedef netlist_list_t<net_device_t_base_factory *> list_t;
	1277	typedef netlist_list_t<net_device_t_base_factory *> list_t;
1278	1278
1279		ATTR_COLD netlist_factory_t();
1280		ATTR_COLD ~netlist_factory_t();
	1279	ATTR_COLD netlist_factory_t();
	1280	ATTR_COLD ~netlist_factory_t();
1281	1281
1282		ATTR_COLD void initialize();
	1282	ATTR_COLD void initialize();
1283	1283
1284		template<class _C>
1285		ATTR_COLD void register_device(const pstring &name, const pstring &classname,
1286		const pstring &def_param)
1287		{
1288		m_list.add(new net_device_t_factory< _C >(name, classname, def_param) );
1289		}
	1284	template<class _C>
	1285	ATTR_COLD void register_device(const pstring &name, const pstring &classname,
	1286	const pstring &def_param)
	1287	{
	1288	m_list.add(new net_device_t_factory< _C >(name, classname, def_param) );
	1289	}
1290	1290
1291		ATTR_COLD netlist_device_t *new_device_by_classname(const pstring &classname, netlist_setup_t &setup) const;
1292		ATTR_COLD netlist_device_t *new_device_by_name(const pstring &name, netlist_setup_t &setup) const;
1293		ATTR_COLD net_device_t_base_factory * factory_by_name(const pstring &name, netlist_setup_t &setup) const;
	1291	ATTR_COLD netlist_device_t *new_device_by_classname(const pstring &classname, netlist_setup_t &setup) const;
	1292	ATTR_COLD netlist_device_t *new_device_by_name(const pstring &name, netlist_setup_t &setup) const;
	1293	ATTR_COLD net_device_t_base_factory * factory_by_name(const pstring &name, netlist_setup_t &setup) const;
1294	1294
1295		const list_t &list() { return m_list; }
	1295	const list_t &list() { return m_list; }
1296	1296
1297	1297	private:
1298		list_t m_list;
	1298	list_t m_list;
1299	1299
1300	1300	};
1301	1301

trunk/src/emu/netlist/analog/nld_switches.c
r29404	r29405
11	11
12	12	NETLIB_START(switch2)
13	13	{
14		register_sub(m_R[0], "R1");
15		register_sub(m_R[1], "R2");
	14	register_sub(m_R[0], "R1");
	15	register_sub(m_R[1], "R2");
16	16
17		register_param("POS", m_POS, 0);
	17	register_param("POS", m_POS, 0);
18	18
19		connect(m_R[0].m_N, m_R[1].m_N);
	19	connect(m_R[0].m_N, m_R[1].m_N);
20	20
21		register_subalias("1", m_R[0].m_P);
22		register_subalias("2", m_R[1].m_P);
	21	register_subalias("1", m_R[0].m_P);
	22	register_subalias("2", m_R[1].m_P);
23	23
24		register_subalias("Q", m_R[0].m_N);
	24	register_subalias("Q", m_R[0].m_N);
25	25	}
26	26
27	27	NETLIB_RESET(switch2)
28	28	{
29		m_R[0].do_reset();
30		m_R[1].do_reset();
	29	m_R[0].do_reset();
	30	m_R[1].do_reset();
31	31
32		m_R[0].set_R(R_ON);
33		m_R[1].set_R(R_OFF);
	32	m_R[0].set_R(R_ON);
	33	m_R[1].set_R(R_OFF);
34	34	}
35	35
36	36	NETLIB_UPDATE(switch2)
37	37	{
38		if (m_POS.Value() == 0)
39		{
40		m_R[0].set_R(R_ON);
41		m_R[1].set_R(R_OFF);
42		}
43		else
44		{
45		m_R[0].set_R(R_OFF);
46		m_R[1].set_R(R_ON);
47		}
	38	if (m_POS.Value() == 0)
	39	{
	40	m_R[0].set_R(R_ON);
	41	m_R[1].set_R(R_OFF);
	42	}
	43	else
	44	{
	45	m_R[0].set_R(R_OFF);
	46	m_R[1].set_R(R_ON);
	47	}
48	48
49		m_R[0].update_dev();
50		m_R[1].update_dev();
	49	m_R[0].update_dev();
	50	m_R[1].update_dev();
51	51	}
52	52
53	53	NETLIB_UPDATE_PARAM(switch2)
54	54	{
55		update();
	55	update();
56	56	}

trunk/src/emu/netlist/analog/nld_solver.c
r29404	r29405
20	20
21	21	ATTR_COLD void netlist_matrix_solver_t::setup(netlist_net_t::list_t &nets, NETLIB_NAME(solver) &aowner)
22	22	{
23		m_owner = &aowner;
	23	m_owner = &aowner;
24	24
25		NL_VERBOSE_OUT(("New solver setup\n"));
	25	NL_VERBOSE_OUT(("New solver setup\n"));
26	26
27		for (netlist_net_t * const * pn = nets.first(); pn != NULL; pn = nets.next(pn))
28		{
29		NL_VERBOSE_OUT(("setting up net\n"));
	27	for (netlist_net_t * const * pn = nets.first(); pn != NULL; pn = nets.next(pn))
	28	{
	29	NL_VERBOSE_OUT(("setting up net\n"));
30	30
31		m_nets.add(*pn);
	31	m_nets.add(*pn);
32	32
33		(*pn)->m_solver = this;
	33	(*pn)->m_solver = this;
34	34
35		for (netlist_core_terminal_t p = (pn)->m_list.first(); p != NULL; p = (*pn)->m_list.next(p))
36		{
37		NL_VERBOSE_OUT(("%s %s %d\n", p->name().cstr(), (pn)->name().cstr(), (int) (pn)->isRailNet()));
38		switch (p->type())
39		{
40		case netlist_terminal_t::TERMINAL:
41		switch (p->netdev().family())
42		{
43		case netlist_device_t::CAPACITOR:
44		if (!m_steps.contains(&p->netdev()))
45		m_steps.add(&p->netdev());
46		break;
47		case netlist_device_t::BJT_EB:
48		case netlist_device_t::DIODE:
49		//case netlist_device_t::VCVS:
50		case netlist_device_t::BJT_SWITCH:
51		NL_VERBOSE_OUT(("found BJT/Diode\n"));
52		if (!m_dynamic.contains(&p->netdev()))
53		m_dynamic.add(&p->netdev());
54		break;
55		default:
56		break;
57		}
58		{
59		netlist_terminal_t pterm = static_cast<netlist_terminal_t >(p);
60		if (pterm->m_otherterm->net().isRailNet())
61		(*pn)->m_rails.add(pterm);
62		else
63		(*pn)->m_terms.add(pterm);
64		}
65		NL_VERBOSE_OUT(("Added terminal\n"));
66		break;
67		case netlist_terminal_t::INPUT:
68		if (!m_inps.contains(p))
69		m_inps.add(p);
70		NL_VERBOSE_OUT(("Added input\n"));
71		break;
72		default:
73		owner().netlist().error("unhandled element found\n");
74		break;
75		}
76		}
77		NL_VERBOSE_OUT(("added net with %d populated connections (%d railnets)\n", (pn)->m_terms.count(), (pn)->m_rails.count()));
78		}
	35	for (netlist_core_terminal_t p = (pn)->m_list.first(); p != NULL; p = (*pn)->m_list.next(p))
	36	{
	37	NL_VERBOSE_OUT(("%s %s %d\n", p->name().cstr(), (pn)->name().cstr(), (int) (pn)->isRailNet()));
	38	switch (p->type())
	39	{
	40	case netlist_terminal_t::TERMINAL:
	41	switch (p->netdev().family())
	42	{
	43	case netlist_device_t::CAPACITOR:
	44	if (!m_steps.contains(&p->netdev()))
	45	m_steps.add(&p->netdev());
	46	break;
	47	case netlist_device_t::BJT_EB:
	48	case netlist_device_t::DIODE:
	49	//case netlist_device_t::VCVS:
	50	case netlist_device_t::BJT_SWITCH:
	51	NL_VERBOSE_OUT(("found BJT/Diode\n"));
	52	if (!m_dynamic.contains(&p->netdev()))
	53	m_dynamic.add(&p->netdev());
	54	break;
	55	default:
	56	break;
	57	}
	58	{
	59	netlist_terminal_t pterm = static_cast<netlist_terminal_t >(p);
	60	if (pterm->m_otherterm->net().isRailNet())
	61	(*pn)->m_rails.add(pterm);
	62	else
	63	(*pn)->m_terms.add(pterm);
	64	}
	65	NL_VERBOSE_OUT(("Added terminal\n"));
	66	break;
	67	case netlist_terminal_t::INPUT:
	68	if (!m_inps.contains(p))
	69	m_inps.add(p);
	70	NL_VERBOSE_OUT(("Added input\n"));
	71	break;
	72	default:
	73	owner().netlist().error("unhandled element found\n");
	74	break;
	75	}
	76	}
	77	NL_VERBOSE_OUT(("added net with %d populated connections (%d railnets)\n", (pn)->m_terms.count(), (pn)->m_rails.count()));
	78	}
79	79	}
80	80
81	81	ATTR_HOT void netlist_matrix_solver_t::update_inputs()
82	82	{
83		for (netlist_core_terminal_t * const *p = m_inps.first(); p != NULL; p = m_inps.next(p))
84		{
85		if ((p)->net().m_last_Analog != (p)->net().m_cur_Analog)
86		{
87		(*p)->netdev().update_dev();
88		}
89		}
90		for (netlist_core_terminal_t * const *p = m_inps.first(); p != NULL; p = m_inps.next(p))
91		{
92		(p)->net().m_last_Analog = (p)->net().m_cur_Analog;
93		}
	83	for (netlist_core_terminal_t * const *p = m_inps.first(); p != NULL; p = m_inps.next(p))
	84	{
	85	if ((p)->net().m_last_Analog != (p)->net().m_cur_Analog)
	86	{
	87	(*p)->netdev().update_dev();
	88	}
	89	}
	90	for (netlist_core_terminal_t * const *p = m_inps.first(); p != NULL; p = m_inps.next(p))
	91	{
	92	(p)->net().m_last_Analog = (p)->net().m_cur_Analog;
	93	}
94	94
95	95	}
96	96
97	97
98	98	ATTR_HOT void netlist_matrix_solver_t::update_dynamic()
99	99	{
100		/* update all non-linear devices */
101		for (netlist_core_device_t * const *p = m_dynamic.first(); p != NULL; p = m_dynamic.next(p))
102		switch ((*p)->family())
103		{
104		case netlist_device_t::DIODE:
105		static_cast<NETLIB_NAME(D) >((p))->update_terminals();
106		break;
107		default:
108		(*p)->update_terminals();
109		break;
110		}
	100	/* update all non-linear devices */
	101	for (netlist_core_device_t * const *p = m_dynamic.first(); p != NULL; p = m_dynamic.next(p))
	102	switch ((*p)->family())
	103	{
	104	case netlist_device_t::DIODE:
	105	static_cast<NETLIB_NAME(D) >((p))->update_terminals();
	106	break;
	107	default:
	108	(*p)->update_terminals();
	109	break;
	110	}
111	111	}
112	112
113	113	ATTR_HOT void netlist_matrix_solver_t::schedule()
114	114	{
115		if (!solve())
116		{
117		// NL_VERBOSE_OUT(("update_inputs\n");
118		update_inputs();
119		}
120		else
121		{
122		m_owner->netlist().warning("Matrix solver reschedule .. Consider increasing RESCHED_LOOPS");
123		if (m_owner != NULL)
124		this->m_owner->schedule();
125		}
126		//solve();
127		// update_inputs();
	115	if (!solve())
	116	{
	117	// NL_VERBOSE_OUT(("update_inputs\n");
	118	update_inputs();
	119	}
	120	else
	121	{
	122	m_owner->netlist().warning("Matrix solver reschedule .. Consider increasing RESCHED_LOOPS");
	123	if (m_owner != NULL)
	124	this->m_owner->schedule();
	125	}
	126	//solve();
	127	// update_inputs();
128	128	}
129	129
130	130	ATTR_COLD void netlist_matrix_solver_t::reset()
131	131	{
132		m_last_step = netlist_time::zero;
	132	m_last_step = netlist_time::zero;
133	133	}
134	134
135	135	ATTR_HOT void netlist_matrix_solver_t::step(const netlist_time delta)
136	136	{
137		const double dd = delta.as_double();
138		for (int k=0; k < m_steps.count(); k++)
139		m_steps[k]->step_time(dd);
	137	const double dd = delta.as_double();
	138	for (int k=0; k < m_steps.count(); k++)
	139	m_steps[k]->step_time(dd);
140	140	}
141	141
142	142	ATTR_HOT bool netlist_matrix_solver_t::solve()
143	143	{
144		int resched_cnt = 0;
	144	int resched_cnt = 0;
145	145
146		netlist_time now = owner().netlist().time();
147		netlist_time delta = now - m_last_step;
	146	netlist_time now = owner().netlist().time();
	147	netlist_time delta = now - m_last_step;
148	148
149		if (delta < netlist_time::from_nsec(1)) // always update capacitors
150		delta = netlist_time::from_nsec(1);
151		{
152		NL_VERBOSE_OUT(("Step!\n"));
153		/* update all terminals for new time step */
154		m_last_step = now;
155		step(delta);
156		}
	149	if (delta < netlist_time::from_nsec(1)) // always update capacitors
	150	delta = netlist_time::from_nsec(1);
	151	{
	152	NL_VERBOSE_OUT(("Step!\n"));
	153	/* update all terminals for new time step */
	154	m_last_step = now;
	155	step(delta);
	156	}
157	157
158		if (is_dynamic())
159		{
160		int this_resched;
161		do
162		{
163		update_dynamic();
164		this_resched = solve_non_dynamic();
165		resched_cnt += this_resched;
166		} while (this_resched > 1 && resched_cnt < m_params.m_resched_loops);
167		}
168		else
169		{
170		resched_cnt = solve_non_dynamic();
171		//printf("resched_cnt %d %d\n", resched_cnt, m_resched_loops);
172		}
173		return (resched_cnt >= m_params.m_resched_loops);
	158	if (is_dynamic())
	159	{
	160	int this_resched;
	161	do
	162	{
	163	update_dynamic();
	164	this_resched = solve_non_dynamic();
	165	resched_cnt += this_resched;
	166	} while (this_resched > 1 && resched_cnt < m_params.m_resched_loops);
	167	}
	168	else
	169	{
	170	resched_cnt = solve_non_dynamic();
	171	//printf("resched_cnt %d %d\n", resched_cnt, m_resched_loops);
	172	}
	173	return (resched_cnt >= m_params.m_resched_loops);
174	174	}
175	175
176	176	// ----------------------------------------------------------------------------------------
r29404	r29405
181	181	template <int m_N, int _storage_N>
182	182	ATTR_COLD int netlist_matrix_solver_direct_t<m_N, _storage_N>::get_net_idx(netlist_net_t *net)
183	183	{
184		for (int k = 0; k < N(); k++)
185		if (m_nets[k] == net)
186		return k;
187		return -1;
	184	for (int k = 0; k < N(); k++)
	185	if (m_nets[k] == net)
	186	return k;
	187	return -1;
188	188	}
189	189
190	190	template <int m_N, int _storage_N>
191	191	ATTR_COLD void netlist_matrix_solver_direct_t<m_N, _storage_N>::setup(netlist_net_t::list_t &nets, NETLIB_NAME(solver) &owner)
192	192	{
193		netlist_matrix_solver_t::setup(nets, owner);
	193	netlist_matrix_solver_t::setup(nets, owner);
194	194
195		m_term_num = 0;
196		m_rail_start = 0;
197		for (int k = 0; k < N(); k++)
198		{
199		netlist_net_t *net = m_nets[k];
200		const netlist_net_t::terminal_list_t &terms = net->m_terms;
201		for (int i = 0; i < terms.count(); i++)
202		{
203		m_terms[m_term_num].net_this = k;
204		int ot = get_net_idx(&terms[i]->m_otherterm->net());
205		m_terms[m_term_num].net_other = ot;
206		m_terms[m_term_num].term = terms[i];
207		if (ot>=0)
208		{
209		m_term_num++;
210		SOLVER_VERBOSE_OUT(("Net %d Term %s %f %f\n", k, terms[i]->name().cstr(), terms[i]->m_gt, terms[i]->m_go));
211		}
212		}
213		}
214		m_rail_start = m_term_num;
215		for (int k = 0; k < N(); k++)
216		{
217		netlist_net_t *net = m_nets[k];
218		const netlist_net_t::terminal_list_t &terms = net->m_terms;
219		const netlist_net_t::terminal_list_t &rails = net->m_rails;
220		for (int i = 0; i < terms.count(); i++)
221		{
222		m_terms[m_term_num].net_this = k;
223		int ot = get_net_idx(&terms[i]->m_otherterm->net());
224		m_terms[m_term_num].net_other = ot;
225		m_terms[m_term_num].term = terms[i];
226		if (ot<0)
227		{
228		m_term_num++;
229		SOLVER_VERBOSE_OUT(("found term with missing othernet %s\n", terms[i]->name().cstr()));
230		}
231		}
232		for (int i = 0; i < rails.count(); i++)
233		{
234		m_terms[m_term_num].net_this = k;
235		m_terms[m_term_num].net_other = -1; //get_net_idx(&rails[i]->m_otherterm->net());
236		m_terms[m_term_num].term = rails[i];
237		m_term_num++;
238		SOLVER_VERBOSE_OUT(("Net %d Rail %s %f %f\n", k, rails[i]->name().cstr(), rails[i]->m_gt, rails[i]->m_go));
239		}
240		}
	195	m_term_num = 0;
	196	m_rail_start = 0;
	197	for (int k = 0; k < N(); k++)
	198	{
	199	netlist_net_t *net = m_nets[k];
	200	const netlist_net_t::terminal_list_t &terms = net->m_terms;
	201	for (int i = 0; i < terms.count(); i++)
	202	{
	203	m_terms[m_term_num].net_this = k;
	204	int ot = get_net_idx(&terms[i]->m_otherterm->net());
	205	m_terms[m_term_num].net_other = ot;
	206	m_terms[m_term_num].term = terms[i];
	207	if (ot>=0)
	208	{
	209	m_term_num++;
	210	SOLVER_VERBOSE_OUT(("Net %d Term %s %f %f\n", k, terms[i]->name().cstr(), terms[i]->m_gt, terms[i]->m_go));
	211	}
	212	}
	213	}
	214	m_rail_start = m_term_num;
	215	for (int k = 0; k < N(); k++)
	216	{
	217	netlist_net_t *net = m_nets[k];
	218	const netlist_net_t::terminal_list_t &terms = net->m_terms;
	219	const netlist_net_t::terminal_list_t &rails = net->m_rails;
	220	for (int i = 0; i < terms.count(); i++)
	221	{
	222	m_terms[m_term_num].net_this = k;
	223	int ot = get_net_idx(&terms[i]->m_otherterm->net());
	224	m_terms[m_term_num].net_other = ot;
	225	m_terms[m_term_num].term = terms[i];
	226	if (ot<0)
	227	{
	228	m_term_num++;
	229	SOLVER_VERBOSE_OUT(("found term with missing othernet %s\n", terms[i]->name().cstr()));
	230	}
	231	}
	232	for (int i = 0; i < rails.count(); i++)
	233	{
	234	m_terms[m_term_num].net_this = k;
	235	m_terms[m_term_num].net_other = -1; //get_net_idx(&rails[i]->m_otherterm->net());
	236	m_terms[m_term_num].term = rails[i];
	237	m_term_num++;
	238	SOLVER_VERBOSE_OUT(("Net %d Rail %s %f %f\n", k, rails[i]->name().cstr(), rails[i]->m_gt, rails[i]->m_go));
	239	}
	240	}
241	241	}
242	242
243	243	template <int m_N, int _storage_N>
244	244	ATTR_HOT void netlist_matrix_solver_direct_t<m_N, _storage_N>::build_LE(
245		double (* RESTRICT A)[_storage_N],
246		double (* RESTRICT RHS))
	245	double (* RESTRICT A)[_storage_N],
	246	double (* RESTRICT RHS))
247	247	{
248
249	248	#if 0
250		for (int i = 0; i < m_term_num; i++)
251		{
252		terms_t &t = m_terms[i];
253		m_RHS[t.net_this] += t.term->m_Idr;
254		m_A[t.net_this][t.net_this] += t.term->m_gt;
255		if (t.net_other >= 0)
256		{
257		//m_A[t.net_other][t.net_other] += t.term->m_otherterm->m_gt;
258		m_A[t.net_this][t.net_other] += -t.term->m_go;
259		//m_A[t.net_other][t.net_this] += -t.term->m_otherterm->m_go;
260		}
261		else
262		m_RHS[t.net_this] += t.term->m_go * t.term->m_otherterm->net().Q_Analog();
263		}
	249	for (int i = 0; i < m_term_num; i++)
	250	{
	251	terms_t &t = m_terms[i];
	252	m_RHS[t.net_this] += t.term->m_Idr;
	253	m_A[t.net_this][t.net_this] += t.term->m_gt;
	254	if (t.net_other >= 0)
	255	{
	256	//m_A[t.net_other][t.net_other] += t.term->m_otherterm->m_gt;
	257	m_A[t.net_this][t.net_other] += -t.term->m_go;
	258	//m_A[t.net_other][t.net_this] += -t.term->m_otherterm->m_go;
	259	}
	260	else
	261	m_RHS[t.net_this] += t.term->m_go * t.term->m_otherterm->net().Q_Analog();
	262	}
264	263	#else
265		for (int i = 0; i < m_rail_start; i++)
266		{
267		terms_t &t = m_terms[i];
268		//printf("A %d %d %s %f %f\n",t.net_this, t.net_other, t.term->name().cstr(), t.term->m_gt, t.term->m_go);
269		RHS[t.net_this] += t.term->m_Idr;
270		A[t.net_this][t.net_this] += t.term->m_gt;
	264	for (int i = 0; i < m_rail_start; i++)
	265	{
	266	terms_t &t = m_terms[i];
	267	//printf("A %d %d %s %f %f\n",t.net_this, t.net_other, t.term->name().cstr(), t.term->m_gt, t.term->m_go);
	268	RHS[t.net_this] += t.term->m_Idr;
	269	A[t.net_this][t.net_this] += t.term->m_gt;
271	270
272		A[t.net_this][t.net_other] += -t.term->m_go;
273		}
274		for (int i = m_rail_start; i < m_term_num; i++)
275		{
276		terms_t &t = m_terms[i];
277		RHS[t.net_this] += t.term->m_Idr;
278		A[t.net_this][t.net_this] += t.term->m_gt;
	271	A[t.net_this][t.net_other] += -t.term->m_go;
	272	}
	273	for (int i = m_rail_start; i < m_term_num; i++)
	274	{
	275	terms_t &t = m_terms[i];
	276	RHS[t.net_this] += t.term->m_Idr;
	277	A[t.net_this][t.net_this] += t.term->m_gt;
279	278
280		RHS[t.net_this] += t.term->m_go * t.term->m_otherterm->net().Q_Analog();
281		}
	279	RHS[t.net_this] += t.term->m_go * t.term->m_otherterm->net().Q_Analog();
	280	}
282	281	#endif
283	282	}
284	283
285	284	template <int m_N, int _storage_N>
286	285	ATTR_HOT void netlist_matrix_solver_direct_t<m_N, _storage_N>::gauss_LE(
287		double (* RESTRICT A)[_storage_N],
288		double (* RESTRICT RHS),
289		double (* RESTRICT x))
	286	double (* RESTRICT A)[_storage_N],
	287	double (* RESTRICT RHS),
	288	double (* RESTRICT x))
290	289	{
291	290	#if 0
292		for (int i = 0; i < N(); i++)
293		{
294		for (int k = 0; k < N(); k++)
295		printf("%f ", A[i][k]);
296		printf("\| %f = %f \n", x[i], RHS[i]);
297		}
298		printf("\n");
	291	for (int i = 0; i < N(); i++)
	292	{
	293	for (int k = 0; k < N(); k++)
	294	printf("%f ", A[i][k]);
	295	printf("\| %f = %f \n", x[i], RHS[i]);
	296	}
	297	printf("\n");
299	298	#endif
300	299
301		for (int i = 0; i < N(); i++) {
302
	300	for (int i = 0; i < N(); i++) {
303	301	#if 0
304		/* Find the row with the largest first value */
305		maxrow = i;
306		for (j=i+1;j<n;j++) {
307		if (ABS(a[i][j]) > ABS(a[i][maxrow]))
308		maxrow = j;
309		}
	302	/* Find the row with the largest first value */
	303	maxrow = i;
	304	for (j=i+1;j<n;j++) {
	305	if (ABS(a[i][j]) > ABS(a[i][maxrow]))
	306	maxrow = j;
	307	}
310	308
311		/* Swap the maxrow and ith row */
312		for (k=i;k<n+1;k++) {
313		tmp = a[k][i];
314		a[k][i] = a[k][maxrow];
315		a[k][maxrow] = tmp;
316		}
	309	/* Swap the maxrow and ith row */
	310	for (k=i;k<n+1;k++) {
	311	tmp = a[k][i];
	312	a[k][i] = a[k][maxrow];
	313	a[k][maxrow] = tmp;
	314	}
317	315	#endif
318		/* Singular matrix? */
319		double f = A[i][i];
320		//if (fabs(f) < 1e-20) printf("Singular!");
321		f = 1.0 / f;
	316	/* Singular matrix? */
	317	double f = A[i][i];
	318	//if (fabs(f) < 1e-20) printf("Singular!");
	319	f = 1.0 / f;
322	320
323		/* Eliminate column i from row j */
324		for (int j = i + 1; j < N(); j++)
325		{
326		double f1 = A[j][i] * f;
	321	/* Eliminate column i from row j */
	322	for (int j = i + 1; j < N(); j++)
	323	{
	324	double f1 = A[j][i] * f;
327	325
328		if (f1 != 0.0)
329		{
330		for (int k = i; k < N(); k++)
331		{
332		A[j][k] -= A[i][k] * f1;
333		}
334		RHS[j] -= RHS[i] * f1;
335		}
336		}
337		}
338		/* back substitution */
339		for (int j = N() - 1; j >= 0; j--)
340		{
341		double tmp = 0;
342		for (int k = j + 1; k < N(); k++)
343		tmp += A[j][k] * x[k];
344		x[j] = (RHS[j] - tmp) / A[j][j];
345		}
	326	if (f1 != 0.0)
	327	{
	328	for (int k = i; k < N(); k++)
	329	{
	330	A[j][k] -= A[i][k] * f1;
	331	}
	332	RHS[j] -= RHS[i] * f1;
	333	}
	334	}
	335	}
	336	/* back substitution */
	337	for (int j = N() - 1; j >= 0; j--)
	338	{
	339	double tmp = 0;
	340	for (int k = j + 1; k < N(); k++)
	341	tmp += A[j][k] * x[k];
	342	x[j] = (RHS[j] - tmp) / A[j][j];
	343	}
346	344	#if 0
347		printf("Solution:\n");
348		for (int i = 0; i < N(); i++)
349		{
350		for (int k = 0; k < N(); k++)
351		printf("%f ", A[i][k]);
352		printf("\| %f = %f \n", x[i], RHS[i]);
353		}
354		printf("\n");
	345	printf("Solution:\n");
	346	for (int i = 0; i < N(); i++)
	347	{
	348	for (int k = 0; k < N(); k++)
	349	printf("%f ", A[i][k]);
	350	printf("\| %f = %f \n", x[i], RHS[i]);
	351	}
	352	printf("\n");
355	353	#endif
356	354
357	355	}
358	356
359	357	template <int m_N, int _storage_N>
360	358	ATTR_HOT double netlist_matrix_solver_direct_t<m_N, _storage_N>::delta(
361		const double (* RESTRICT RHS),
362		const double (* RESTRICT V))
	359	const double (* RESTRICT RHS),
	360	const double (* RESTRICT V))
363	361	{
364		double cerr = 0;
365		double cerr2 = 0;
366		for (int i = 0; i < this->N(); i++)
367		{
368		double e = (V[i] - this->m_nets[i]->m_cur_Analog);
369		double e2 = (RHS[i] - this->m_RHS[i]);
370		cerr += e * e;
371		cerr2 += e2 * e2;
372		}
373		return (cerr + cerr2(100000.0 100000.0)) / this->N();
	362	double cerr = 0;
	363	double cerr2 = 0;
	364	for (int i = 0; i < this->N(); i++)
	365	{
	366	double e = (V[i] - this->m_nets[i]->m_cur_Analog);
	367	double e2 = (RHS[i] - this->m_RHS[i]);
	368	cerr += e * e;
	369	cerr2 += e2 * e2;
	370	}
	371	return (cerr + cerr2(100000.0 100000.0)) / this->N();
374	372	}
375	373
376	374	template <int m_N, int _storage_N>
377	375	ATTR_HOT void netlist_matrix_solver_direct_t<m_N, _storage_N>::store(
378		const double (* RESTRICT RHS),
379		const double (* RESTRICT V))
	376	const double (* RESTRICT RHS),
	377	const double (* RESTRICT V))
380	378	{
381		for (int i = 0; i < this->N(); i++)
382		{
383		this->m_nets[i]->m_cur_Analog = this->m_nets[i]->m_new_Analog = V[i];
384		}
385		if (RHS != NULL)
386		{
387		for (int i = 0; i < this->N(); i++)
388		{
389		this->m_RHS[i] = RHS[i];
390		}
391		}
	379	for (int i = 0; i < this->N(); i++)
	380	{
	381	this->m_nets[i]->m_cur_Analog = this->m_nets[i]->m_new_Analog = V[i];
	382	}
	383	if (RHS != NULL)
	384	{
	385	for (int i = 0; i < this->N(); i++)
	386	{
	387	this->m_RHS[i] = RHS[i];
	388	}
	389	}
392	390	}
393	391
394	392	template <int m_N, int _storage_N>
395	393	ATTR_HOT int netlist_matrix_solver_direct_t<m_N, _storage_N>::solve_non_dynamic()
396	394	{
397		double A[_storage_N][_storage_N] = { { 0.0 } };
398		double RHS[_storage_N] = { 0.0 };
399		double new_v[_storage_N] = { 0.0 };
	395	double A[_storage_N][_storage_N] = { { 0.0 } };
	396	double RHS[_storage_N] = { 0.0 };
	397	double new_v[_storage_N] = { 0.0 };
400	398
401		this->build_LE(A, RHS);
	399	this->build_LE(A, RHS);
402	400
403		this->gauss_LE(A, RHS, new_v);
	401	this->gauss_LE(A, RHS, new_v);
404	402
405		if (this->is_dynamic())
406		{
407		double err = delta(RHS, new_v);
	403	if (this->is_dynamic())
	404	{
	405	double err = delta(RHS, new_v);
408	406
409		store(RHS, new_v);
	407	store(RHS, new_v);
410	408
411		if (err > this->m_params.m_accuracy * this->m_params.m_accuracy)
412		{
413		return 2;
414		}
415		return 1;
416		}
417		store(NULL, new_v); // ==> No need to store RHS
418		return 1;
	409	if (err > this->m_params.m_accuracy * this->m_params.m_accuracy)
	410	{
	411	return 2;
	412	}
	413	return 1;
	414	}
	415	store(NULL, new_v); // ==> No need to store RHS
	416	return 1;
419	417	}
420	418
421	419
r29404	r29405
427	425	{
428	426	#if 1
429	427
430		double gtot_t = 0.0;
431		double RHS_t = 0.0;
	428	double gtot_t = 0.0;
	429	double RHS_t = 0.0;
432	430
433		netlist_net_t *net = m_nets[0];
434		const netlist_net_t::terminal_list_t &rails = net->m_rails;
435		int rail_count = rails.count();
	431	netlist_net_t *net = m_nets[0];
	432	const netlist_net_t::terminal_list_t &rails = net->m_rails;
	433	int rail_count = rails.count();
436	434
437		for (int i = 0; i < rail_count; i++)
438		{
439		gtot_t += rails[i]->m_gt;
440		RHS_t += rails[i]->m_Idr;
441		RHS_t += rails[i]->m_go * rails[i]->m_otherterm->net().Q_Analog();
442		}
	435	for (int i = 0; i < rail_count; i++)
	436	{
	437	gtot_t += rails[i]->m_gt;
	438	RHS_t += rails[i]->m_Idr;
	439	RHS_t += rails[i]->m_go * rails[i]->m_otherterm->net().Q_Analog();
	440	}
443	441
444		double iIdr = RHS_t;
445		double new_val = iIdr / gtot_t;
	442	double iIdr = RHS_t;
	443	double new_val = iIdr / gtot_t;
446	444
447	445	#else
448		netlist_net_t *net = m_nets[0];
449		double m_A[1][1] = { {0.0} };
450		double m_RHS[1] = { 0.0 };
451		build_LE(m_A, m_RHS);
452		//NL_VERBOSE_OUT(("%f %f\n", new_val, m_RHS[0] / m_A[0][0]);
	446	netlist_net_t *net = m_nets[0];
	447	double m_A[1][1] = { {0.0} };
	448	double m_RHS[1] = { 0.0 };
	449	build_LE(m_A, m_RHS);
	450	//NL_VERBOSE_OUT(("%f %f\n", new_val, m_RHS[0] / m_A[0][0]);
453	451
454		double new_val = m_RHS[0] / m_A[0][0];
	452	double new_val = m_RHS[0] / m_A[0][0];
455	453	#endif
456		double e = (new_val - net->m_cur_Analog);
457		double cerr = e * e;
	454	double e = (new_val - net->m_cur_Analog);
	455	double cerr = e * e;
458	456
459		net->m_cur_Analog = net->m_new_Analog = new_val;
	457	net->m_cur_Analog = net->m_new_Analog = new_val;
460	458
461		if (is_dynamic() && (cerr > m_params.m_accuracy * m_params.m_accuracy))
462		{
463		return 2;
464		}
465		else
466		return 1;
	459	if (is_dynamic() && (cerr > m_params.m_accuracy * m_params.m_accuracy))
	460	{
	461	return 2;
	462	}
	463	else
	464	return 1;
467	465
468	466	}
469	467
r29404	r29405
475	473
476	474	ATTR_HOT int netlist_matrix_solver_direct2_t::solve_non_dynamic()
477	475	{
478		double A[2][2] = { { 0.0 } };
479		double RHS[2] = { 0.0 };
	476	double A[2][2] = { { 0.0 } };
	477	double RHS[2] = { 0.0 };
480	478
481		build_LE(A, RHS);
	479	build_LE(A, RHS);
482	480
483		//NL_VERBOSE_OUT(("%f %f\n", new_val, m_RHS[0] / m_A[0][0]);
	481	//NL_VERBOSE_OUT(("%f %f\n", new_val, m_RHS[0] / m_A[0][0]);
484	482
485		const double a = A[0][0];
486		const double b = A[0][1];
487		const double c = A[1][0];
488		const double d = A[1][1];
	483	const double a = A[0][0];
	484	const double b = A[0][1];
	485	const double c = A[1][0];
	486	const double d = A[1][1];
489	487
490		double new_val[2];
491		new_val[1] = a / (ad - bc) * (RHS[1] - c / a * RHS[0]);
492		new_val[0] = (RHS[0] - b * new_val[1]) / a;
	488	double new_val[2];
	489	new_val[1] = a / (ad - bc) * (RHS[1] - c / a * RHS[0]);
	490	new_val[0] = (RHS[0] - b * new_val[1]) / a;
493	491
494		if (is_dynamic())
495		{
496		double err = delta(RHS, new_val);
497		store(RHS, new_val);
498		if (err > m_params.m_accuracy * m_params.m_accuracy)
499		return 2;
500		else
501		return 1;
502		}
503		store(NULL, new_val);
504		return 1;
	492	if (is_dynamic())
	493	{
	494	double err = delta(RHS, new_val);
	495	store(RHS, new_val);
	496	if (err > m_params.m_accuracy * m_params.m_accuracy)
	497	return 2;
	498	else
	499	return 1;
	500	}
	501	store(NULL, new_val);
	502	return 1;
505	503	}
506	504
507	505	// ----------------------------------------------------------------------------------------
r29404	r29405
511	509	template <int m_N, int _storage_N>
512	510	ATTR_HOT int netlist_matrix_solver_gauss_seidel_t<m_N, _storage_N>::solve_non_dynamic()
513	511	{
514		bool resched = false;
	512	bool resched = false;
515	513
516		int resched_cnt = 0;
517		ATTR_UNUSED netlist_net_t *last_resched_net = NULL;
	514	int resched_cnt = 0;
	515	ATTR_UNUSED netlist_net_t *last_resched_net = NULL;
518	516
519		/* over-relaxation not really works on these matrices */
520		//const double w = 1.0; //2.0 / (1.0 + sin(3.14159 / (m_nets.count()+1)));
521		//const double w1 = 1.0 - w;
	517	/* over-relaxation not really works on these matrices */
	518	//const double w = 1.0; //2.0 / (1.0 + sin(3.14159 / (m_nets.count()+1)));
	519	//const double w1 = 1.0 - w;
522	520
523		double w[_storage_N];
524		double one_m_w[_storage_N];
525		double RHS[_storage_N];
	521	double w[_storage_N];
	522	double one_m_w[_storage_N];
	523	double RHS[_storage_N];
526	524
527		for (int k = 0; k < N(); k++)
528		{
529		double gtot_t = 0.0;
530		double gabs_t = 0.0;
531		double RHS_t = 0.0;
	525	for (int k = 0; k < N(); k++)
	526	{
	527	double gtot_t = 0.0;
	528	double gabs_t = 0.0;
	529	double RHS_t = 0.0;
532	530
533		netlist_net_t *net = m_nets[k];
534		const netlist_net_t::terminal_list_t &terms = net->m_terms;
535		const netlist_net_t::terminal_list_t &rails = net->m_rails;
536		const int term_count = terms.count();
537		const int rail_count = rails.count();
	531	netlist_net_t *net = m_nets[k];
	532	const netlist_net_t::terminal_list_t &terms = net->m_terms;
	533	const netlist_net_t::terminal_list_t &rails = net->m_rails;
	534	const int term_count = terms.count();
	535	const int rail_count = rails.count();
538	536
539		for (int i = 0; i < rail_count; i++)
540		{
541		gtot_t += rails[i]->m_gt;
542		gabs_t += fabs(rails[i]->m_go);
543		RHS_t += rails[i]->m_Idr;
544		RHS_t += rails[i]->m_go * rails[i]->m_otherterm->net().Q_Analog();
545		}
	537	for (int i = 0; i < rail_count; i++)
	538	{
	539	gtot_t += rails[i]->m_gt;
	540	gabs_t += fabs(rails[i]->m_go);
	541	RHS_t += rails[i]->m_Idr;
	542	RHS_t += rails[i]->m_go * rails[i]->m_otherterm->net().Q_Analog();
	543	}
546	544
547		for (int i = 0; i < term_count; i++)
548		{
549		gtot_t += terms[i]->m_gt;
550		gabs_t += fabs(terms[i]->m_go);
551		RHS_t += terms[i]->m_Idr;
552		}
	545	for (int i = 0; i < term_count; i++)
	546	{
	547	gtot_t += terms[i]->m_gt;
	548	gabs_t += fabs(terms[i]->m_go);
	549	RHS_t += terms[i]->m_Idr;
	550	}
553	551
554		gabs_t *= m_params.m_convergence_factor;
555		if (gabs_t > gtot_t)
556		{
557		// Actually 1.0 / g_tot * g_tot / (gtot_t + gabs_t)
558		w[k] = 1.0 / (gtot_t + gabs_t);
559		one_m_w[k] = gabs_t / (gtot_t + gabs_t);
560		}
561		else
562		{
563		w[k] = 1.0 / gtot_t;
564		one_m_w[k] = 0.0;
565		}
	552	gabs_t *= m_params.m_convergence_factor;
	553	if (gabs_t > gtot_t)
	554	{
	555	// Actually 1.0 / g_tot * g_tot / (gtot_t + gabs_t)
	556	w[k] = 1.0 / (gtot_t + gabs_t);
	557	one_m_w[k] = gabs_t / (gtot_t + gabs_t);
	558	}
	559	else
	560	{
	561	w[k] = 1.0 / gtot_t;
	562	one_m_w[k] = 0.0;
	563	}
566	564
567		RHS[k] = RHS_t;
568		}
	565	RHS[k] = RHS_t;
	566	}
569	567
570		//NL_VERBOSE_OUT(("%f %d\n", w, m_nets.count());
571		do {
572		resched = false;
573		double cerr = 0.0;
	568	//NL_VERBOSE_OUT(("%f %d\n", w, m_nets.count());
	569	do {
	570	resched = false;
	571	double cerr = 0.0;
574	572
575		for (int k = 0; k < N(); k++)
576		{
577		netlist_net_t *net = m_nets[k];
578		const netlist_net_t::terminal_list_t &terms = net->m_terms;
579		const int term_count = terms.count();
	573	for (int k = 0; k < N(); k++)
	574	{
	575	netlist_net_t *net = m_nets[k];
	576	const netlist_net_t::terminal_list_t &terms = net->m_terms;
	577	const int term_count = terms.count();
580	578
581		double iIdr = RHS[k];
	579	double iIdr = RHS[k];
582	580
583		for (int i = 0; i < term_count; i++)
584		{
585		iIdr += terms[i]->m_go * terms[i]->m_otherterm->net().Q_Analog();
586		}
	581	for (int i = 0; i < term_count; i++)
	582	{
	583	iIdr += terms[i]->m_go * terms[i]->m_otherterm->net().Q_Analog();
	584	}
587	585
588		//double new_val = (net->m_cur_Analog * gabs[k] + iIdr) / (gtot[k]);
589		double new_val = net->m_cur_Analog * one_m_w[k] + iIdr * w[k];
	586	//double new_val = (net->m_cur_Analog * gabs[k] + iIdr) / (gtot[k]);
	587	double new_val = net->m_cur_Analog * one_m_w[k] + iIdr * w[k];
590	588
591		double e = (new_val - net->m_cur_Analog);
592		cerr += e * e;
	589	double e = (new_val - net->m_cur_Analog);
	590	cerr += e * e;
593	591
594		net->m_cur_Analog = net->m_new_Analog = new_val;
595		}
596		if (resched \|\| cerr / m_nets.count() > m_params.m_accuracy * m_params.m_accuracy)
597		{
598		resched = true;
599		//last_resched_net = net;
600		}
601		resched_cnt++;
602		} while (resched && (resched_cnt < m_params.m_resched_loops / 3 ));
	592	net->m_cur_Analog = net->m_new_Analog = new_val;
	593	}
	594	if (resched \|\| cerr / m_nets.count() > m_params.m_accuracy * m_params.m_accuracy)
	595	{
	596	resched = true;
	597	//last_resched_net = net;
	598	}
	599	resched_cnt++;
	600	} while (resched && (resched_cnt < m_params.m_resched_loops / 3 ));
603	601
604		if (resched)
605		return m_fallback.solve_non_dynamic();
	602	if (resched)
	603	return m_fallback.solve_non_dynamic();
606	604
607		return resched_cnt;
	605	return resched_cnt;
608	606	}
609	607
610	608	// ----------------------------------------------------------------------------------------
r29404	r29405
615	613
616	614	ATTR_COLD static bool already_processed(net_groups_t groups, int &cur_group, netlist_net_t *net)
617	615	{
618		if (net->isRailNet())
619		return true;
620		for (int i = 0; i <= cur_group; i++)
621		{
622		if (groups[i].contains(net))
623		return true;
624		}
625		return false;
	616	if (net->isRailNet())
	617	return true;
	618	for (int i = 0; i <= cur_group; i++)
	619	{
	620	if (groups[i].contains(net))
	621	return true;
	622	}
	623	return false;
626	624	}
627	625
628	626	ATTR_COLD static void process_net(net_groups_t groups, int &cur_group, netlist_net_t *net)
629	627	{
630		if (net->m_list.is_empty())
631		return;
632		/* add the net */
633		SOLVER_VERBOSE_OUT(("add %d - %s\n", cur_group, net->name().cstr()));
634		groups[cur_group].add(net);
635		for (netlist_core_terminal_t *p = net->m_list.first(); p != NULL; p = net->m_list.next(p))
636		{
637		SOLVER_VERBOSE_OUT(("terminal %s\n", p->name().cstr()));
638		if (p->isType(netlist_terminal_t::TERMINAL))
639		{
640		SOLVER_VERBOSE_OUT(("isterminal\n"));
641		netlist_terminal_t pt = static_cast<netlist_terminal_t >(p);
642		netlist_net_t *other_net = &pt->m_otherterm->net();
643		if (!already_processed(groups, cur_group, other_net))
644		process_net(groups, cur_group, other_net);
645		}
646		}
	628	if (net->m_list.is_empty())
	629	return;
	630	/* add the net */
	631	SOLVER_VERBOSE_OUT(("add %d - %s\n", cur_group, net->name().cstr()));
	632	groups[cur_group].add(net);
	633	for (netlist_core_terminal_t *p = net->m_list.first(); p != NULL; p = net->m_list.next(p))
	634	{
	635	SOLVER_VERBOSE_OUT(("terminal %s\n", p->name().cstr()));
	636	if (p->isType(netlist_terminal_t::TERMINAL))
	637	{
	638	SOLVER_VERBOSE_OUT(("isterminal\n"));
	639	netlist_terminal_t pt = static_cast<netlist_terminal_t >(p);
	640	netlist_net_t *other_net = &pt->m_otherterm->net();
	641	if (!already_processed(groups, cur_group, other_net))
	642	process_net(groups, cur_group, other_net);
	643	}
	644	}
647	645	}
648	646
649	647
650	648	NETLIB_START(solver)
651	649	{
652		register_output("Q_sync", m_Q_sync);
653		register_output("Q_step", m_Q_step);
654		//register_input("FB", m_feedback);
	650	register_output("Q_sync", m_Q_sync);
	651	register_output("Q_step", m_Q_step);
	652	//register_input("FB", m_feedback);
655	653
656		register_param("SYNC_DELAY", m_sync_delay, NLTIME_FROM_NS(5).as_double());
657		m_nt_sync_delay = m_sync_delay.Value();
	654	register_param("SYNC_DELAY", m_sync_delay, NLTIME_FROM_NS(5).as_double());
	655	m_nt_sync_delay = m_sync_delay.Value();
658	656
659		register_param("FREQ", m_freq, 48000.0);
660		m_inc = netlist_time::from_hz(m_freq.Value());
	657	register_param("FREQ", m_freq, 48000.0);
	658	m_inc = netlist_time::from_hz(m_freq.Value());
661	659
662		register_param("ACCURACY", m_accuracy, 1e-7);
663		register_param("CONVERG", m_convergence, 0.3);
664		register_param("RESCHED_LOOPS", m_resched_loops, 35);
665		register_param("PARALLEL", m_parallel, 0);
666		register_param("GMIN", m_gmin, NETLIST_GMIN_DEFAULT);
	660	register_param("ACCURACY", m_accuracy, 1e-7);
	661	register_param("CONVERG", m_convergence, 0.3);
	662	register_param("RESCHED_LOOPS", m_resched_loops, 35);
	663	register_param("PARALLEL", m_parallel, 0);
	664	register_param("GMIN", m_gmin, NETLIST_GMIN_DEFAULT);
667	665
668		// internal staff
	666	// internal staff
669	667
670		register_input("FB_sync", m_fb_sync);
671		register_input("FB_step", m_fb_step);
	668	register_input("FB_sync", m_fb_sync);
	669	register_input("FB_step", m_fb_step);
672	670
673		connect(m_fb_sync, m_Q_sync);
674		connect(m_fb_step, m_Q_step);
	671	connect(m_fb_sync, m_Q_sync);
	672	connect(m_fb_step, m_Q_step);
675	673
676		save(NAME(m_last_step));
	674	save(NAME(m_last_step));
677	675
678	676	}
679	677
680	678	NETLIB_RESET(solver)
681	679	{
682		m_last_step = netlist_time::zero;
683		for (int i = 0; i < m_mat_solvers.count(); i++)
684		m_mat_solvers[i]->reset();
	680	m_last_step = netlist_time::zero;
	681	for (int i = 0; i < m_mat_solvers.count(); i++)
	682	m_mat_solvers[i]->reset();
685	683	}
686	684
687	685
688	686	NETLIB_UPDATE_PARAM(solver)
689	687	{
690		m_inc = netlist_time::from_hz(m_freq.Value());
	688	m_inc = netlist_time::from_hz(m_freq.Value());
691	689	}
692	690
693	691	NETLIB_NAME(solver)::~NETLIB_NAME(solver)()
694	692	{
695		netlist_matrix_solver_t * const *e = m_mat_solvers.first();
696		while (e != NULL)
697		{
698		netlist_matrix_solver_t * const *en = m_mat_solvers.next(e);
699		delete *e;
700		e = en;
701		}
	693	netlist_matrix_solver_t * const *e = m_mat_solvers.first();
	694	while (e != NULL)
	695	{
	696	netlist_matrix_solver_t * const *en = m_mat_solvers.next(e);
	697	delete *e;
	698	e = en;
	699	}
702	700
703	701	}
704	702
705	703	NETLIB_UPDATE(solver)
706	704	{
707		netlist_time now = netlist().time();
708		netlist_time delta = now - m_last_step;
709		bool do_full = false;
710		bool global_resched = false;
711		bool this_resched[100];
712		int t_cnt = m_mat_solvers.count();
	705	netlist_time now = netlist().time();
	706	netlist_time delta = now - m_last_step;
	707	bool do_full = false;
	708	bool global_resched = false;
	709	bool this_resched[100];
	710	int t_cnt = m_mat_solvers.count();
713	711
714		if (delta < m_inc)
715		do_full = true; // we have been called between updates
	712	if (delta < m_inc)
	713	do_full = true; // we have been called between updates
716	714
717		m_last_step = now;
	715	m_last_step = now;
718	716
719	717	#if HAS_OPENMP && USE_OPENMP
720		if (m_parallel.Value())
721		{
722		omp_set_num_threads(4);
723		omp_set_dynamic(0);
724		#pragma omp parallel
725		{
726		#pragma omp for nowait
727		for (int i = 0; i < t_cnt; i++)
728		{
729		this_resched[i] = m_mat_solvers[i]->solve();
730		}
731		}
732		}
733		else
734		for (int i = 0; i < t_cnt; i++)
735		{
736		if (do_full \|\| (m_mat_solvers[i]->is_timestep()))
737		this_resched[i] = m_mat_solvers[i]->solve();
738		}
	718	if (m_parallel.Value())
	719	{
	720	omp_set_num_threads(4);
	721	omp_set_dynamic(0);
	722	#pragma omp parallel
	723	{
	724	#pragma omp for nowait
	725	for (int i = 0; i < t_cnt; i++)
	726	{
	727	this_resched[i] = m_mat_solvers[i]->solve();
	728	}
	729	}
	730	}
	731	else
	732	for (int i = 0; i < t_cnt; i++)
	733	{
	734	if (do_full \|\| (m_mat_solvers[i]->is_timestep()))
	735	this_resched[i] = m_mat_solvers[i]->solve();
	736	}
739	737	#else
740		for (int i = 0; i < t_cnt; i++)
741		{
742		if (do_full \|\| (m_mat_solvers[i]->is_timestep()))
743		this_resched[i] = m_mat_solvers[i]->solve();
744		}
	738	for (int i = 0; i < t_cnt; i++)
	739	{
	740	if (do_full \|\| (m_mat_solvers[i]->is_timestep()))
	741	this_resched[i] = m_mat_solvers[i]->solve();
	742	}
745	743	#endif
746	744
747		for (int i = 0; i < t_cnt; i++)
748		{
749		if (do_full \|\| m_mat_solvers[i]->is_timestep())
750		{
751		global_resched = global_resched \|\| this_resched[i];
752		if (!this_resched[i])
753		m_mat_solvers[i]->update_inputs();
754		}
755		}
	745	for (int i = 0; i < t_cnt; i++)
	746	{
	747	if (do_full \|\| m_mat_solvers[i]->is_timestep())
	748	{
	749	global_resched = global_resched \|\| this_resched[i];
	750	if (!this_resched[i])
	751	m_mat_solvers[i]->update_inputs();
	752	}
	753	}
756	754
757		if (global_resched)
758		{
759		netlist().warning("Gobal reschedule .. Consider increasing RESCHED_LOOPS");
760		schedule();
761		}
762		else
763		{
764		/* step circuit */
765		if (!m_Q_step.net().is_queued())
766		m_Q_step.net().push_to_queue(m_inc);
767		}
	755	if (global_resched)
	756	{
	757	netlist().warning("Gobal reschedule .. Consider increasing RESCHED_LOOPS");
	758	schedule();
	759	}
	760	else
	761	{
	762	/* step circuit */
	763	if (!m_Q_step.net().is_queued())
	764	m_Q_step.net().push_to_queue(m_inc);
	765	}
768	766
769	767	}
770	768
771	769	ATTR_COLD void NETLIB_NAME(solver)::post_start()
772	770	{
773		netlist_net_t::list_t groups[100];
774		int cur_group = -1;
	771	netlist_net_t::list_t groups[100];
	772	int cur_group = -1;
775	773
776		SOLVER_VERBOSE_OUT(("Scanning net groups ...\n"));
777		// determine net groups
778		for (netlist_net_t * const *pn = netlist().m_nets.first(); pn != NULL; pn = netlist().m_nets.next(pn))
779		{
780		NL_VERBOSE_OUT(("proc %s\n", (*pn)->name().cstr()));
781		if (!already_processed(groups, cur_group, *pn))
782		{
783		cur_group++;
784		process_net(groups, cur_group, *pn);
785		}
786		}
	774	SOLVER_VERBOSE_OUT(("Scanning net groups ...\n"));
	775	// determine net groups
	776	for (netlist_net_t * const *pn = netlist().m_nets.first(); pn != NULL; pn = netlist().m_nets.next(pn))
	777	{
	778	NL_VERBOSE_OUT(("proc %s\n", (*pn)->name().cstr()));
	779	if (!already_processed(groups, cur_group, *pn))
	780	{
	781	cur_group++;
	782	process_net(groups, cur_group, *pn);
	783	}
	784	}
787	785
788		// setup the solvers
789		SOLVER_VERBOSE_OUT(("Found %d net groups in %d nets\n", cur_group + 1, netlist().m_nets.count()));
790		for (int i = 0; i <= cur_group; i++)
791		{
792		netlist_matrix_solver_t *ms;
793		int net_count = groups[i].count();
	786	// setup the solvers
	787	SOLVER_VERBOSE_OUT(("Found %d net groups in %d nets\n", cur_group + 1, netlist().m_nets.count()));
	788	for (int i = 0; i <= cur_group; i++)
	789	{
	790	netlist_matrix_solver_t *ms;
	791	int net_count = groups[i].count();
794	792
795		switch (net_count)
796		{
797		case 1:
798		ms = new netlist_matrix_solver_direct1_t();
799		break;
800		case 2:
801		ms = new netlist_matrix_solver_direct2_t();
802		break;
803		case 3:
804		ms = new netlist_matrix_solver_direct_t<3,3>();
805		//ms = new netlist_matrix_solver_gauss_seidel_t<3,3>();
806		break;
807		case 4:
808		ms = new netlist_matrix_solver_direct_t<4,4>();
809		//ms = new netlist_matrix_solver_gauss_seidel_t<4,4>();
810		break;
	793	switch (net_count)
	794	{
	795	case 1:
	796	ms = new netlist_matrix_solver_direct1_t();
	797	break;
	798	case 2:
	799	ms = new netlist_matrix_solver_direct2_t();
	800	break;
	801	case 3:
	802	ms = new netlist_matrix_solver_direct_t<3,3>();
	803	//ms = new netlist_matrix_solver_gauss_seidel_t<3,3>();
	804	break;
	805	case 4:
	806	ms = new netlist_matrix_solver_direct_t<4,4>();
	807	//ms = new netlist_matrix_solver_gauss_seidel_t<4,4>();
	808	break;
811	809	#if 0
812		case 5:
813		//ms = new netlist_matrix_solver_direct_t<5,5>();
814		ms = new netlist_matrix_solver_gauss_seidel_t<5,5>();
815		break;
816		case 6:
817		//ms = new netlist_matrix_solver_direct_t<6,6>();
818		ms = new netlist_matrix_solver_gauss_seidel_t<6,6>();
819		break;
	810	case 5:
	811	//ms = new netlist_matrix_solver_direct_t<5,5>();
	812	ms = new netlist_matrix_solver_gauss_seidel_t<5,5>();
	813	break;
	814	case 6:
	815	//ms = new netlist_matrix_solver_direct_t<6,6>();
	816	ms = new netlist_matrix_solver_gauss_seidel_t<6,6>();
	817	break;
820	818	#endif
821		default:
822		if (net_count <= 16)
823		{
824		//ms = new netlist_matrix_solver_direct_t<0,16>();
825		ms = new netlist_matrix_solver_gauss_seidel_t<0,16>();
826		}
827		else if (net_count <= 32)
828		{
829		//ms = new netlist_matrix_solver_direct_t<0,16>();
830		ms = new netlist_matrix_solver_gauss_seidel_t<0,32>();
831		}
832		else if (net_count <= 64)
833		{
834		//ms = new netlist_matrix_solver_direct_t<0,16>();
835		ms = new netlist_matrix_solver_gauss_seidel_t<0,64>();
836		}
837		else
838		{
839		netlist().error("Encountered netgroup with > 64 nets");
840		ms = NULL; /* tease compilers */
841		}
	819	default:
	820	if (net_count <= 16)
	821	{
	822	//ms = new netlist_matrix_solver_direct_t<0,16>();
	823	ms = new netlist_matrix_solver_gauss_seidel_t<0,16>();
	824	}
	825	else if (net_count <= 32)
	826	{
	827	//ms = new netlist_matrix_solver_direct_t<0,16>();
	828	ms = new netlist_matrix_solver_gauss_seidel_t<0,32>();
	829	}
	830	else if (net_count <= 64)
	831	{
	832	//ms = new netlist_matrix_solver_direct_t<0,16>();
	833	ms = new netlist_matrix_solver_gauss_seidel_t<0,64>();
	834	}
	835	else
	836	{
	837	netlist().error("Encountered netgroup with > 64 nets");
	838	ms = NULL; /* tease compilers */
	839	}
842	840
843		break;
844		}
	841	break;
	842	}
845	843
846		ms->m_params.m_accuracy = m_accuracy.Value();
847		ms->m_params.m_convergence_factor = m_convergence.Value();
848		ms->m_params.m_resched_loops = m_resched_loops.Value();
849		ms->setup(groups[i], *this);
850		m_mat_solvers.add(ms);
851		SOLVER_VERBOSE_OUT(("%d ==> %d nets %s\n", i, groups[i].count(), (*groups[i].first())->m_head->name().cstr()));
852		SOLVER_VERBOSE_OUT((" has %s elements\n", ms->is_dynamic() ? "dynamic" : "no dynamic"));
853		SOLVER_VERBOSE_OUT((" has %s elements\n", ms->is_timestep() ? "timestep" : "no timestep"));
854		for (int j=0; j<groups[i].count(); j++)
855		{
856		SOLVER_VERBOSE_OUT(("Net %d: %s\n", j, groups[i][j]->name().cstr()));
857		netlist_net_t *n = groups[i][j];
858		for (netlist_core_terminal_t *p = n->m_list.first(); p != NULL; p = n->m_list.next(p))
859		{
860		SOLVER_VERBOSE_OUT((" %s\n", p->name().cstr()));
861		}
862		}
863		}
	844	ms->m_params.m_accuracy = m_accuracy.Value();
	845	ms->m_params.m_convergence_factor = m_convergence.Value();
	846	ms->m_params.m_resched_loops = m_resched_loops.Value();
	847	ms->setup(groups[i], *this);
	848	m_mat_solvers.add(ms);
	849	SOLVER_VERBOSE_OUT(("%d ==> %d nets %s\n", i, groups[i].count(), (*groups[i].first())->m_head->name().cstr()));
	850	SOLVER_VERBOSE_OUT((" has %s elements\n", ms->is_dynamic() ? "dynamic" : "no dynamic"));
	851	SOLVER_VERBOSE_OUT((" has %s elements\n", ms->is_timestep() ? "timestep" : "no timestep"));
	852	for (int j=0; j<groups[i].count(); j++)
	853	{
	854	SOLVER_VERBOSE_OUT(("Net %d: %s\n", j, groups[i][j]->name().cstr()));
	855	netlist_net_t *n = groups[i][j];
	856	for (netlist_core_terminal_t *p = n->m_list.first(); p != NULL; p = n->m_list.next(p))
	857	{
	858	SOLVER_VERBOSE_OUT((" %s\n", p->name().cstr()));
	859	}
	860	}
	861	}
864	862
865	863	}

trunk/src/emu/netlist/analog/nld_switches.h
r29404	r29405
25	25	// ----------------------------------------------------------------------------------------
26	26
27	27	NETLIB_DEVICE_WITH_PARAMS(switch2,
28		NETLIB_NAME(R_base) m_R[2];
	28	NETLIB_NAME(R_base) m_R[2];
29	29
30	30	netlist_param_int_t m_POS;
31	31	);

trunk/src/emu/netlist/analog/nld_bjt.c
r29404	r29405
10	10	class diode
11	11	{
12	12	public:
13		diode() : m_Is(1e-15), m_VT(0.0258), m_VT_inv(1.0 / m_VT) {}
14		diode(const double Is, const double n)
15		{
16		m_Is = Is;
17		m_VT = 0.0258 * n;
18		m_VT_inv = 1.0 / m_VT;
19		}
20		void set(const double Is, const double n)
21		{
22		m_Is = Is;
23		m_VT = 0.0258 * n;
24		m_VT_inv = 1.0 / m_VT;
25		}
26		double I(const double V) const { return m_Is * exp(V * m_VT_inv) - m_Is; }
27		double g(const double V) const { return m_Is * m_VT_inv * exp(V * m_VT_inv); }
28		double V(const double I) const { return log(1.0 + I / m_Is) * m_VT; }
29		double gI(const double I) const { return m_VT_inv * (I + m_Is); }
	13	diode() : m_Is(1e-15), m_VT(0.0258), m_VT_inv(1.0 / m_VT) {}
	14	diode(const double Is, const double n)
	15	{
	16	m_Is = Is;
	17	m_VT = 0.0258 * n;
	18	m_VT_inv = 1.0 / m_VT;
	19	}
	20	void set(const double Is, const double n)
	21	{
	22	m_Is = Is;
	23	m_VT = 0.0258 * n;
	24	m_VT_inv = 1.0 / m_VT;
	25	}
	26	double I(const double V) const { return m_Is * exp(V * m_VT_inv) - m_Is; }
	27	double g(const double V) const { return m_Is * m_VT_inv * exp(V * m_VT_inv); }
	28	double V(const double I) const { return log(1.0 + I / m_Is) * m_VT; }
	29	double gI(const double I) const { return m_VT_inv * (I + m_Is); }
30	30
31	31	private:
32		double m_Is;
33		double m_VT;
34		double m_VT_inv;
	32	double m_Is;
	33	double m_VT;
	34	double m_VT_inv;
35	35	};
36	36
37	37
r29404	r29405
42	42
43	43	NETLIB_START(Q)
44	44	{
45		register_param("model", m_model, "");
	45	register_param("model", m_model, "");
46	46	}
47	47
48	48	NETLIB_RESET(Q)
r29404	r29405
60	60
61	61	NETLIB_START(QBJT_switch)
62	62	{
63		NETLIB_NAME(Q)::start();
	63	NETLIB_NAME(Q)::start();
64	64
65		register_terminal("B", m_RB.m_P);
66		register_terminal("E", m_RB.m_N);
67		register_terminal("C", m_RC.m_P);
68		register_terminal("_E1", m_RC.m_N);
	65	register_terminal("B", m_RB.m_P);
	66	register_terminal("E", m_RB.m_N);
	67	register_terminal("C", m_RC.m_P);
	68	register_terminal("_E1", m_RC.m_N);
69	69
70		register_terminal("_B1", m_BC_dummy.m_P);
71		register_terminal("_C1", m_BC_dummy.m_N);
	70	register_terminal("_B1", m_BC_dummy.m_P);
	71	register_terminal("_C1", m_BC_dummy.m_N);
72	72
73		connect(m_RB.m_N, m_RC.m_N);
	73	connect(m_RB.m_N, m_RC.m_N);
74	74
75		connect(m_RB.m_P, m_BC_dummy.m_P);
76		connect(m_RC.m_P, m_BC_dummy.m_N);
	75	connect(m_RB.m_P, m_BC_dummy.m_P);
	76	connect(m_RC.m_P, m_BC_dummy.m_N);
77	77
78		save(NAME(m_state_on));
	78	save(NAME(m_state_on));
79	79
80		m_RB.set(netlist().gmin(), 0.0, 0.0);
81		m_RC.set(netlist().gmin(), 0.0, 0.0);
	80	m_RB.set(netlist().gmin(), 0.0, 0.0);
	81	m_RC.set(netlist().gmin(), 0.0, 0.0);
82	82
83		m_BC_dummy.set(netlist().gmin(), 0.0, 0.0);
	83	m_BC_dummy.set(netlist().gmin(), 0.0, 0.0);
84	84
85		m_state_on = 0;
	85	m_state_on = 0;
86	86
87		{
88		double IS = m_model.model_value("IS", 1e-15);
89		double BF = m_model.model_value("BF", 100);
90		double NF = m_model.model_value("NF", 1);
91		//double VJE = m_model.dValue("VJE", 0.75);
	87	{
	88	double IS = m_model.model_value("IS", 1e-15);
	89	double BF = m_model.model_value("BF", 100);
	90	double NF = m_model.model_value("NF", 1);
	91	//double VJE = m_model.dValue("VJE", 0.75);
92	92
93		set_qtype((m_model.model_type() == "NPN") ? BJT_NPN : BJT_PNP);
	93	set_qtype((m_model.model_type() == "NPN") ? BJT_NPN : BJT_PNP);
94	94
95		double alpha = BF / (1.0 + BF);
	95	double alpha = BF / (1.0 + BF);
96	96
97		diode d(IS, NF);
	97	diode d(IS, NF);
98	98
99		// Assume 5mA Collector current for switch operation
	99	// Assume 5mA Collector current for switch operation
100	100
101		m_V = d.V(0.005 / alpha);
	101	m_V = d.V(0.005 / alpha);
102	102
103		/* Base current is 0.005 / beta
104		* as a rough estimate, we just scale the conductance down */
	103	/* Base current is 0.005 / beta
	104	* as a rough estimate, we just scale the conductance down */
105	105
106		m_gB = d.gI(0.005 / alpha);
	106	m_gB = d.gI(0.005 / alpha);
107	107
108		if (m_gB < netlist().gmin())
109		m_gB = netlist().gmin();
110		m_gC = d.gI(0.005); // very rough estimate
111		//printf("%f %f \n", m_V, m_gB);
112		}
	108	if (m_gB < netlist().gmin())
	109	m_gB = netlist().gmin();
	110	m_gC = d.gI(0.005); // very rough estimate
	111	//printf("%f %f \n", m_V, m_gB);
	112	}
113	113
114	114	}
115	115
r29404	r29405
125	125
126	126	NETLIB_START(QBJT_EB)
127	127	{
128		NETLIB_NAME(Q)::start();
	128	NETLIB_NAME(Q)::start();
129	129
130		register_terminal("E", m_D_EB.m_P); // Cathode
131		register_terminal("B", m_D_EB.m_N); // Anode
	130	register_terminal("E", m_D_EB.m_P); // Cathode
	131	register_terminal("B", m_D_EB.m_N); // Anode
132	132
133		register_terminal("C", m_D_CB.m_P); // Cathode
134		register_terminal("_B1", m_D_CB.m_N); // Anode
	133	register_terminal("C", m_D_CB.m_P); // Cathode
	134	register_terminal("_B1", m_D_CB.m_N); // Anode
135	135
136		register_terminal("_E1", m_D_EC.m_P);
137		register_terminal("_C1", m_D_EC.m_N);
	136	register_terminal("_E1", m_D_EC.m_P);
	137	register_terminal("_C1", m_D_EC.m_N);
138	138
139		connect(m_D_EB.m_P, m_D_EC.m_P);
140		connect(m_D_EB.m_N, m_D_CB.m_N);
141		connect(m_D_CB.m_P, m_D_EC.m_N);
	139	connect(m_D_EB.m_P, m_D_EC.m_P);
	140	connect(m_D_EB.m_N, m_D_CB.m_N);
	141	connect(m_D_CB.m_P, m_D_EC.m_N);
142	142
143		m_gD_BE.save("m_D_BE", *this);
144		m_gD_BC.save("m_D_BC", *this);
	143	m_gD_BE.save("m_D_BE", *this);
	144	m_gD_BC.save("m_D_BC", *this);
145	145
146		{
147		double IS = m_model.model_value("IS", 1e-15);
148		double BF = m_model.model_value("BF", 100);
149		double NF = m_model.model_value("NF", 1);
150		double BR = m_model.model_value("BR", 1);
151		double NR = m_model.model_value("NR", 1);
152		//double VJE = m_model.dValue("VJE", 0.75);
	146	{
	147	double IS = m_model.model_value("IS", 1e-15);
	148	double BF = m_model.model_value("BF", 100);
	149	double NF = m_model.model_value("NF", 1);
	150	double BR = m_model.model_value("BR", 1);
	151	double NR = m_model.model_value("NR", 1);
	152	//double VJE = m_model.dValue("VJE", 0.75);
153	153
154		set_qtype((m_model.model_type() == "NPN") ? BJT_NPN : BJT_PNP);
155		//printf("type %s\n", m_model.model_type().cstr());
	154	set_qtype((m_model.model_type() == "NPN") ? BJT_NPN : BJT_PNP);
	155	//printf("type %s\n", m_model.model_type().cstr());
156	156
157		m_alpha_f = BF / (1.0 + BF);
158		m_alpha_r = BR / (1.0 + BR);
	157	m_alpha_f = BF / (1.0 + BF);
	158	m_alpha_r = BR / (1.0 + BR);
159	159
160		m_gD_BE.set_param(IS / m_alpha_f, NF, netlist().gmin());
161		m_gD_BC.set_param(IS / m_alpha_r, NR, netlist().gmin());
162		}
	160	m_gD_BE.set_param(IS / m_alpha_f, NF, netlist().gmin());
	161	m_gD_BC.set_param(IS / m_alpha_r, NR, netlist().gmin());
	162	}
163	163	}
164	164
165	165	NETLIB_UPDATE(QBJT_EB)
166	166	{
167		if (!m_D_EB.m_P.net().isRailNet())
168		m_D_EB.m_P.net().solve(); // Basis
169		else if (!m_D_EB.m_N.net().isRailNet())
170		m_D_EB.m_N.net().solve(); // Emitter
171		else
172		m_D_CB.m_N.net().solve(); // Collector
	167	if (!m_D_EB.m_P.net().isRailNet())
	168	m_D_EB.m_P.net().solve(); // Basis
	169	else if (!m_D_EB.m_N.net().isRailNet())
	170	m_D_EB.m_N.net().solve(); // Emitter
	171	else
	172	m_D_CB.m_N.net().solve(); // Collector
173	173	}
174	174
175	175	NETLIB_RESET(QBJT_EB)
176	176	{
177		NETLIB_NAME(Q)::reset();
	177	NETLIB_NAME(Q)::reset();
178	178	}
179	179
180	180
r29404	r29405
182	182	NETLIB_UPDATE_PARAM(QBJT_EB)
183	183	{
184	184	}
185

trunk/src/emu/netlist/analog/nld_solver.h
r29404	r29405
15	15
16	16	#define SOLVER(_name, _freq) \
17	17	NET_REGISTER_DEV(solver, _name) \
18		PARAM(_name.FREQ, _freq)
	18	PARAM(_name.FREQ, _freq)
19	19
20	20	// ----------------------------------------------------------------------------------------
21	21	// solver
r29404	r29405
27	27
28	28	struct netlist_solver_parameters_t
29	29	{
30		double m_accuracy;
31		double m_convergence_factor;
32		int m_resched_loops;
	30	double m_accuracy;
	31	double m_convergence_factor;
	32	int m_resched_loops;
33	33	};
34	34
35	35	class netlist_matrix_solver_t
r29404	r29405
39	39	typedef netlist_core_device_t::list_t dev_list_t;
40	40
41	41	netlist_matrix_solver_t() : m_owner(NULL) {}
42		virtual ~netlist_matrix_solver_t() {}
	42	virtual ~netlist_matrix_solver_t() {}
43	43
44	44	ATTR_COLD virtual void setup(netlist_net_t::list_t &nets, NETLIB_NAME(solver) &owner);
45	45
46	46	// return true if a reschedule is needed ...
47		ATTR_HOT virtual int solve_non_dynamic() = 0;
	47	ATTR_HOT virtual int solve_non_dynamic() = 0;
48	48	ATTR_HOT virtual void step(const netlist_time delta);
49	49
50		ATTR_HOT bool solve();
	50	ATTR_HOT bool solve();
51	51
52	52	ATTR_HOT void update_inputs();
53		ATTR_HOT void update_dynamic();
	53	ATTR_HOT void update_dynamic();
54	54
55	55	ATTR_HOT void schedule();
56	56
57	57	ATTR_HOT inline bool is_dynamic() { return m_dynamic.count() > 0; }
58		ATTR_HOT inline bool is_timestep() { return m_steps.count() > 0; }
	58	ATTR_HOT inline bool is_timestep() { return m_steps.count() > 0; }
59	59
60	60	ATTR_HOT inline const NETLIB_NAME(solver) &owner() const;
61	61	ATTR_COLD virtual void reset();
r29404	r29405
67	67	dev_list_t m_dynamic;
68	68	netlist_core_terminal_t::list_t m_inps;
69	69	dev_list_t m_steps;
70		netlist_time m_last_step;
	70	netlist_time m_last_step;
71	71
72		NETLIB_NAME(solver) *m_owner;
	72	NETLIB_NAME(solver) *m_owner;
73	73	};
74	74
75	75	template <int m_N, int _storage_N>
r29404	r29405
77	77	{
78	78	public:
79	79
80		netlist_matrix_solver_direct_t() : netlist_matrix_solver_t() {}
	80	netlist_matrix_solver_direct_t() : netlist_matrix_solver_t() {}
81	81
82		virtual ~netlist_matrix_solver_direct_t() {}
	82	virtual ~netlist_matrix_solver_direct_t() {}
83	83
84		ATTR_COLD virtual void setup(netlist_net_t::list_t &nets, NETLIB_NAME(solver) &owner);
85		ATTR_COLD virtual void reset() { netlist_matrix_solver_t::reset(); }
86		ATTR_HOT virtual int solve_non_dynamic();
	84	ATTR_COLD virtual void setup(netlist_net_t::list_t &nets, NETLIB_NAME(solver) &owner);
	85	ATTR_COLD virtual void reset() { netlist_matrix_solver_t::reset(); }
	86	ATTR_HOT virtual int solve_non_dynamic();
87	87
88		ATTR_HOT inline const int N() const { return (m_N == 0) ? m_nets.count() : m_N; }
	88	ATTR_HOT inline const int N() const { return (m_N == 0) ? m_nets.count() : m_N; }
89	89
90	90	protected:
91		ATTR_HOT inline void build_LE(double (* RESTRICT A)[_storage_N], double (* RESTRICT RHS));
92		ATTR_HOT inline void gauss_LE(double (* RESTRICT A)[_storage_N],
93		double (* RESTRICT RHS),
94		double (* RESTRICT x));
95		ATTR_HOT inline double delta(
96		const double (* RESTRICT RHS),
97		const double (* RESTRICT V));
98		ATTR_HOT inline void store(const double (* RESTRICT RHS), const double (* RESTRICT V));
	91	ATTR_HOT inline void build_LE(double (* RESTRICT A)[_storage_N], double (* RESTRICT RHS));
	92	ATTR_HOT inline void gauss_LE(double (* RESTRICT A)[_storage_N],
	93	double (* RESTRICT RHS),
	94	double (* RESTRICT x));
	95	ATTR_HOT inline double delta(
	96	const double (* RESTRICT RHS),
	97	const double (* RESTRICT V));
	98	ATTR_HOT inline void store(const double (* RESTRICT RHS), const double (* RESTRICT V));
99	99
100		double m_RHS[_storage_N]; // right hand side - contains currents
	100	double m_RHS[_storage_N]; // right hand side - contains currents
101	101
102	102	private:
103	103
104		ATTR_COLD int get_net_idx(netlist_net_t *net);
	104	ATTR_COLD int get_net_idx(netlist_net_t *net);
105	105
106		struct terms_t{
107		int net_this;
108		int net_other;
109		netlist_terminal_t *term;
110		};
111		int m_term_num;
112		int m_rail_start;
113		terms_t m_terms[100];
	106	struct terms_t{
	107	int net_this;
	108	int net_other;
	109	netlist_terminal_t *term;
	110	};
	111	int m_term_num;
	112	int m_rail_start;
	113	terms_t m_terms[100];
114	114	};
115	115
116	116	template <int m_N, int _storage_N>
r29404	r29405
118	118	{
119	119	public:
120	120
121		netlist_matrix_solver_gauss_seidel_t() : netlist_matrix_solver_t() {}
	121	netlist_matrix_solver_gauss_seidel_t() : netlist_matrix_solver_t() {}
122	122
123		virtual ~netlist_matrix_solver_gauss_seidel_t() {}
	123	virtual ~netlist_matrix_solver_gauss_seidel_t() {}
124	124
125		ATTR_COLD virtual void setup(netlist_net_t::list_t &nets, NETLIB_NAME(solver) &owner)
126		{
127		netlist_matrix_solver_t::setup(nets, owner);
128		m_fallback.m_params = m_params;
129		m_fallback.setup(nets, owner);
130		}
	125	ATTR_COLD virtual void setup(netlist_net_t::list_t &nets, NETLIB_NAME(solver) &owner)
	126	{
	127	netlist_matrix_solver_t::setup(nets, owner);
	128	m_fallback.m_params = m_params;
	129	m_fallback.setup(nets, owner);
	130	}
131	131
132		ATTR_HOT int solve_non_dynamic();
	132	ATTR_HOT int solve_non_dynamic();
133	133
134		ATTR_HOT inline const int N() const { if (m_N == 0) return m_nets.count(); else return m_N; }
	134	ATTR_HOT inline const int N() const { if (m_N == 0) return m_nets.count(); else return m_N; }
135	135
136		ATTR_COLD virtual void reset()
137		{
138		netlist_matrix_solver_t::reset();
139		m_fallback.reset();
140		}
	136	ATTR_COLD virtual void reset()
	137	{
	138	netlist_matrix_solver_t::reset();
	139	m_fallback.reset();
	140	}
141	141
142	142	private:
143		netlist_matrix_solver_direct_t<m_N, _storage_N> m_fallback;
	143	netlist_matrix_solver_direct_t<m_N, _storage_N> m_fallback;
144	144	};
145	145
146	146	class netlist_matrix_solver_direct1_t: public netlist_matrix_solver_direct_t<1,1>
147	147	{
148	148	public:
149		ATTR_HOT int solve_non_dynamic();
	149	ATTR_HOT int solve_non_dynamic();
150	150	private:
151	151	};
152	152
153	153	class netlist_matrix_solver_direct2_t: public netlist_matrix_solver_direct_t<2,2>
154	154	{
155	155	public:
156		ATTR_HOT int solve_non_dynamic();
	156	ATTR_HOT int solve_non_dynamic();
157	157	private:
158	158	};
159	159
r29404	r29405
170	170	netlist_param_double_t m_sync_delay;
171	171	netlist_param_double_t m_accuracy;
172	172	netlist_param_double_t m_convergence;
173		netlist_param_double_t m_gmin;
174		netlist_param_int_t m_resched_loops;
175		netlist_param_int_t m_parallel;
	173	netlist_param_double_t m_gmin;
	174	netlist_param_int_t m_resched_loops;
	175	netlist_param_int_t m_parallel;
176	176
177	177	netlist_time m_inc;
178	178	netlist_time m_last_step;

trunk/src/emu/netlist/analog/nld_twoterm.c
r29404	r29405
12	12
13	13	ATTR_COLD netlist_generic_diode::netlist_generic_diode()
14	14	{
15		m_Vd = 0.7;
	15	m_Vd = 0.7;
16	16	}
17	17
18	18	ATTR_COLD void netlist_generic_diode::set_param(const double Is, const double n, double gmin)
19	19	{
20		m_Is = Is;
21		m_n = n;
22		m_gmin = gmin;
	20	m_Is = Is;
	21	m_n = n;
	22	m_gmin = gmin;
23	23
24		m_Vt = 0.0258 * m_n;
	24	m_Vt = 0.0258 * m_n;
25	25
26		m_Vcrit = m_Vt * log(m_Vt / m_Is / sqrt(2.0));
27		m_VtInv = 1.0 / m_Vt;
	26	m_Vcrit = m_Vt * log(m_Vt / m_Is / sqrt(2.0));
	27	m_VtInv = 1.0 / m_Vt;
28	28	}
29	29
30	30	ATTR_COLD void netlist_generic_diode::save(pstring name, netlist_object_t &parent)
31	31	{
32		parent.save(m_Vd, name + ".m_Vd");
33		parent.save(m_Id, name + ".m_Id");
34		parent.save(m_G, name + ".m_G");
	32	parent.save(m_Vd, name + ".m_Vd");
	33	parent.save(m_Id, name + ".m_Id");
	34	parent.save(m_G, name + ".m_G");
35	35	}
36	36
37	37	// ----------------------------------------------------------------------------------------
r29404	r29405
57	57	NETLIB_UPDATE(twoterm)
58	58	{
59	59	/* only called if connected to a rail net ==> notify the solver to recalculate */
60		/* we only need to call the non-rail terminal */
61		if (!m_P.net().isRailNet())
62		m_P.net().solve();
63		else
64		m_N.net().solve();
	60	/* we only need to call the non-rail terminal */
	61	if (!m_P.net().isRailNet())
	62	m_P.net().solve();
	63	else
	64	m_N.net().solve();
65	65	}
66	66
67	67	// ----------------------------------------------------------------------------------------
r29404	r29405
76	76
77	77	NETLIB_RESET(R_base)
78	78	{
79		NETLIB_NAME(twoterm)::reset();
80		set_R(1.0 / netlist().gmin());
	79	NETLIB_NAME(twoterm)::reset();
	80	set_R(1.0 / netlist().gmin());
81	81	}
82	82
83	83	NETLIB_UPDATE(R_base)
r29404	r29405
93	93
94	94	NETLIB_RESET(R)
95	95	{
96		NETLIB_NAME(R_base)::reset();
	96	NETLIB_NAME(R_base)::reset();
97	97	}
98	98
99	99	NETLIB_UPDATE(R)
r29404	r29405
105	105	{
106	106	//printf("updating %s to %f\n", name().cstr(), m_R.Value());
107	107	if (m_R.Value() > 1e-9)
108		set_R(m_R.Value());
	108	set_R(m_R.Value());
109	109	else
110		set_R(1e-9);
111		update_dev();
	110	set_R(1e-9);
	111	update_dev();
112	112	}
113	113
114	114	// ----------------------------------------------------------------------------------------
r29404	r29405
134	134
135	135	NETLIB_RESET(POT)
136	136	{
137		m_R1.do_reset();
138		m_R2.do_reset();
	137	m_R1.do_reset();
	138	m_R2.do_reset();
139	139	}
140	140
141	141	NETLIB_UPDATE(POT)
r29404	r29405
152	152	m_R1.set_R(MAX(m_R.Value() * v, netlist().gmin()));
153	153	m_R2.set_R(MAX(m_R.Value() * (1.0 - v), netlist().gmin()));
154	154	// force a schedule all
155		m_R1.update_dev();
156		m_R2.update_dev();
	155	m_R1.update_dev();
	156	m_R2.update_dev();
157	157	}
158	158
159	159	// ----------------------------------------------------------------------------------------
r29404	r29405
168	168	register_param("C", m_C, 1e-6);
169	169
170	170	// set up the element
171		set(netlist().gmin(), 0.0, -5.0 / netlist().gmin());
172		//set(1.0/NETLIST_GMIN, 0.0, -5.0 * NETLIST_GMIN);
	171	set(netlist().gmin(), 0.0, -5.0 / netlist().gmin());
	172	//set(1.0/NETLIST_GMIN, 0.0, -5.0 * NETLIST_GMIN);
173	173	}
174	174
175	175	NETLIB_RESET(C)
176	176	{
177		set(netlist().gmin(), 0.0, -5.0 / netlist().gmin());
178		//set(1.0/NETLIST_GMIN, 0.0, -5.0 * NETLIST_GMIN);
	177	set(netlist().gmin(), 0.0, -5.0 / netlist().gmin());
	178	//set(1.0/NETLIST_GMIN, 0.0, -5.0 * NETLIST_GMIN);
179	179	}
180	180
181	181	NETLIB_UPDATE_PARAM(C)
r29404	r29405
215	215	{
216	216	NETLIB_NAME(twoterm)::update();
217	217	}
218
219

trunk/src/emu/netlist/analog/nld_fourterm.c
r29404	r29405
13	13
14	14	NETLIB_START(VCCS)
15	15	{
16		register_param("G", m_G, 1.0);
17		register_param("RI", m_RI, 1.0 / netlist().gmin());
	16	register_param("G", m_G, 1.0);
	17	register_param("RI", m_RI, 1.0 / netlist().gmin());
18	18
19		register_terminal("IP", m_IP);
20		register_terminal("IN", m_IN);
21		register_terminal("OP", m_OP);
22		register_terminal("ON", m_ON);
	19	register_terminal("IP", m_IP);
	20	register_terminal("IN", m_IN);
	21	register_terminal("OP", m_OP);
	22	register_terminal("ON", m_ON);
23	23
24		register_terminal("_OP1", m_OP1);
25		register_terminal("_ON1", m_ON1);
	24	register_terminal("_OP1", m_OP1);
	25	register_terminal("_ON1", m_ON1);
26	26
27		m_IP.m_otherterm = &m_IN; // <= this should be NULL and terminal be filtered out prior to solving...
28		m_IN.m_otherterm = &m_IP; // <= this should be NULL and terminal be filtered out prior to solving...
	27	m_IP.m_otherterm = &m_IN; // <= this should be NULL and terminal be filtered out prior to solving...
	28	m_IN.m_otherterm = &m_IP; // <= this should be NULL and terminal be filtered out prior to solving...
29	29
30		m_OP.m_otherterm = &m_IP;
31		m_OP1.m_otherterm = &m_IN;
	30	m_OP.m_otherterm = &m_IP;
	31	m_OP1.m_otherterm = &m_IN;
32	32
33		m_ON.m_otherterm = &m_IP;
34		m_ON1.m_otherterm = &m_IN;
	33	m_ON.m_otherterm = &m_IP;
	34	m_ON1.m_otherterm = &m_IN;
35	35
36		connect(m_OP, m_OP1);
37		connect(m_ON, m_ON1);
	36	connect(m_OP, m_OP1);
	37	connect(m_ON, m_ON1);
38	38
39		m_gfac = 1.0;
	39	m_gfac = 1.0;
40	40	}
41	41
42	42	NETLIB_RESET(VCCS)
43	43	{
44		const double m_mult = m_G.Value() * m_gfac; // 1.0 ==> 1V ==> 1A
45		const double GI = 1.0 / m_RI.Value();
	44	const double m_mult = m_G.Value() * m_gfac; // 1.0 ==> 1V ==> 1A
	45	const double GI = 1.0 / m_RI.Value();
46	46
47		m_IP.set(GI);
48		m_IN.set(GI);
	47	m_IP.set(GI);
	48	m_IN.set(GI);
49	49
50		m_OP.set(m_mult, 0.0);
51		m_OP1.set(-m_mult, 0.0);
	50	m_OP.set(m_mult, 0.0);
	51	m_OP1.set(-m_mult, 0.0);
52	52
53		m_ON.set(-m_mult, 0.0);
54		m_ON1.set(m_mult, 0.0);
	53	m_ON.set(-m_mult, 0.0);
	54	m_ON1.set(m_mult, 0.0);
55	55	}
56	56
57	57	NETLIB_UPDATE_PARAM(VCCS)
r29404	r29405
60	60
61	61	NETLIB_UPDATE(VCCS)
62	62	{
63		/* only called if connected to a rail net ==> notify the solver to recalculate */
64		/* Big FIXME ... */
65		if (!m_IP.net().isRailNet())
66		m_IP.net().solve();
67		else if (!m_IN.net().isRailNet())
68		m_IN.net().solve();
69		else if (!m_OP.net().isRailNet())
70		m_OP.net().solve();
71		else if (!m_ON.net().isRailNet())
72		m_ON.net().solve();
	63	/* only called if connected to a rail net ==> notify the solver to recalculate */
	64	/* Big FIXME ... */
	65	if (!m_IP.net().isRailNet())
	66	m_IP.net().solve();
	67	else if (!m_IN.net().isRailNet())
	68	m_IN.net().solve();
	69	else if (!m_OP.net().isRailNet())
	70	m_OP.net().solve();
	71	else if (!m_ON.net().isRailNet())
	72	m_ON.net().solve();
73	73	}
74	74
75	75	// ----------------------------------------------------------------------------------------
r29404	r29405
78	78
79	79	NETLIB_START(VCVS)
80	80	{
81		NETLIB_NAME(VCCS)::start();
	81	NETLIB_NAME(VCCS)::start();
82	82
83		register_param("RO", m_RO, 1.0);
	83	register_param("RO", m_RO, 1.0);
84	84
85		register_terminal("_OP2", m_OP2);
86		register_terminal("_ON2", m_ON2);
	85	register_terminal("_OP2", m_OP2);
	86	register_terminal("_ON2", m_ON2);
87	87
88		m_OP2.m_otherterm = &m_ON2;
89		m_ON2.m_otherterm = &m_OP2;
	88	m_OP2.m_otherterm = &m_ON2;
	89	m_ON2.m_otherterm = &m_OP2;
90	90
91		connect(m_OP2, m_OP1);
92		connect(m_ON2, m_ON1);
	91	connect(m_OP2, m_OP1);
	92	connect(m_ON2, m_ON1);
93	93	}
94	94
95	95	NETLIB_RESET(VCVS)
96	96	{
97		m_gfac = 1.0 / m_RO.Value();
98		NETLIB_NAME(VCCS)::reset();
	97	m_gfac = 1.0 / m_RO.Value();
	98	NETLIB_NAME(VCCS)::reset();
99	99
100		m_OP2.set(1.0 / m_RO.Value());
101		m_ON2.set(1.0 / m_RO.Value());
	100	m_OP2.set(1.0 / m_RO.Value());
	101	m_ON2.set(1.0 / m_RO.Value());
102	102	}
103	103
104	104	NETLIB_UPDATE_PARAM(VCVS)
105	105	{
106	106	}
107

trunk/src/emu/netlist/analog/nld_bjt.h
r29404	r29405
14	14	// ----------------------------------------------------------------------------------------
15	15
16	16	#define QBJT_SW(_name, _model) \
17		NET_REGISTER_DEV(QBJT_switch, _name) \
18		NETDEV_PARAMI(_name, model, _model)
	17	NET_REGISTER_DEV(QBJT_switch, _name) \
	18	NETDEV_PARAMI(_name, model, _model)
19	19
20	20	#define QBJT_EB(_name, _model) \
21		NET_REGISTER_DEV(QBJT_EB, _name) \
22		NETDEV_PARAMI(_name, model, _model)
	21	NET_REGISTER_DEV(QBJT_EB, _name) \
	22	NETDEV_PARAMI(_name, model, _model)
23	23
24	24
25	25	// ----------------------------------------------------------------------------------------
r29404	r29405
31	31	class NETLIB_NAME(Q) : public netlist_device_t
32	32	{
33	33	public:
34		enum q_type {
35		BJT_NPN,
36		BJT_PNP
37		};
	34	enum q_type {
	35	BJT_NPN,
	36	BJT_PNP
	37	};
38	38
39		ATTR_COLD NETLIB_NAME(Q)(const family_t afamily)
40		: netlist_device_t(afamily)
41		, m_qtype(BJT_NPN) { }
	39	ATTR_COLD NETLIB_NAME(Q)(const family_t afamily)
	40	: netlist_device_t(afamily)
	41	, m_qtype(BJT_NPN) { }
42	42
43		inline q_type qtype() const { return m_qtype; }
44		inline bool is_qtype(q_type atype) const { return m_qtype == atype; }
45		inline void set_qtype(q_type atype) { m_qtype = atype; }
	43	inline q_type qtype() const { return m_qtype; }
	44	inline bool is_qtype(q_type atype) const { return m_qtype == atype; }
	45	inline void set_qtype(q_type atype) { m_qtype = atype; }
46	46	protected:
47		ATTR_COLD virtual void start();
48		ATTR_COLD virtual void reset();
49		ATTR_HOT ATTR_ALIGN void update();
	47	ATTR_COLD virtual void start();
	48	ATTR_COLD virtual void reset();
	49	ATTR_HOT ATTR_ALIGN void update();
50	50
51		netlist_param_model_t m_model;
	51	netlist_param_model_t m_model;
52	52	private:
53		q_type m_qtype;
	53	q_type m_qtype;
54	54	};
55	55
56	56	class NETLIB_NAME(QBJT) : public NETLIB_NAME(Q)
57	57	{
58	58	public:
59	59
60		ATTR_COLD NETLIB_NAME(QBJT)(const family_t afamily)
61		: NETLIB_NAME(Q)(afamily) { }
	60	ATTR_COLD NETLIB_NAME(QBJT)(const family_t afamily)
	61	: NETLIB_NAME(Q)(afamily) { }
62	62
63	63	protected:
64	64
r29404	r29405
89	89	class NETLIB_NAME(QBJT_switch) : public NETLIB_NAME(QBJT)
90	90	{
91	91	public:
92		ATTR_COLD NETLIB_NAME(QBJT_switch)()
93		: NETLIB_NAME(QBJT)(BJT_SWITCH),
94		m_RB(netlist_object_t::ANALOG),
95		m_RC(netlist_object_t::ANALOG),
96		m_BC_dummy(netlist_object_t::ANALOG),
97		m_gB(NETLIST_GMIN_DEFAULT), m_gC(NETLIST_GMIN_DEFAULT), m_V(0.0), m_state_on(0) { }
	92	ATTR_COLD NETLIB_NAME(QBJT_switch)()
	93	: NETLIB_NAME(QBJT)(BJT_SWITCH),
	94	m_RB(netlist_object_t::ANALOG),
	95	m_RC(netlist_object_t::ANALOG),
	96	m_BC_dummy(netlist_object_t::ANALOG),
	97	m_gB(NETLIST_GMIN_DEFAULT), m_gC(NETLIST_GMIN_DEFAULT), m_V(0.0), m_state_on(0) { }
98	98
99		NETLIB_UPDATE_TERMINALS()
100		{
101		double m = (is_qtype( BJT_NPN) ? 1 : -1);
	99	NETLIB_UPDATE_TERMINALS()
	100	{
	101	double m = (is_qtype( BJT_NPN) ? 1 : -1);
102	102
103		int new_state = (m_RB.deltaV() * m > m_V ) ? 1 : 0;
104		if (m_state_on ^ new_state)
105		{
106		double gb = m_gB;
107		double gc = m_gC;
108		double v = m_V * m;
109		if (!new_state )
110		{
111		// not conducting
112		gb = netlist().gmin();
113		v = 0;
114		gc = netlist().gmin();
115		}
116		m_RB.set(gb, v, 0.0);
117		m_RC.set(gc, 0.0, 0.0);
118		m_state_on = new_state;
119		}
120		}
	103	int new_state = (m_RB.deltaV() * m > m_V ) ? 1 : 0;
	104	if (m_state_on ^ new_state)
	105	{
	106	double gb = m_gB;
	107	double gc = m_gC;
	108	double v = m_V * m;
	109	if (!new_state )
	110	{
	111	// not conducting
	112	gb = netlist().gmin();
	113	v = 0;
	114	gc = netlist().gmin();
	115	}
	116	m_RB.set(gb, v, 0.0);
	117	m_RC.set(gc, 0.0, 0.0);
	118	m_state_on = new_state;
	119	}
	120	}
121	121
122		ATTR_HOT ATTR_ALIGN void virtual update()
123		{
124		if (!m_RB.m_P.net().isRailNet())
125		m_RB.m_P.net().solve(); // Basis
126		else if (!m_RB.m_N.net().isRailNet())
127		m_RB.m_N.net().solve(); // Emitter
128		else if (!m_RC.m_P.net().isRailNet())
129		m_RB.m_P.net().solve(); // Collector
130		}
	122	ATTR_HOT ATTR_ALIGN void virtual update()
	123	{
	124	if (!m_RB.m_P.net().isRailNet())
	125	m_RB.m_P.net().solve(); // Basis
	126	else if (!m_RB.m_N.net().isRailNet())
	127	m_RB.m_N.net().solve(); // Emitter
	128	else if (!m_RC.m_P.net().isRailNet())
	129	m_RB.m_P.net().solve(); // Collector
	130	}
131	131
132		nld_twoterm m_RB;
133		nld_twoterm m_RC;
	132	nld_twoterm m_RB;
	133	nld_twoterm m_RC;
134	134
135		// FIXME: the matrix solvers should be devices so we can properly
136		// schedule them. This is a workaround and blows netgroup size
	135	// FIXME: the matrix solvers should be devices so we can properly
	136	// schedule them. This is a workaround and blows netgroup size
137	137
138		nld_twoterm m_BC_dummy;
	138	nld_twoterm m_BC_dummy;
139	139
140	140	protected:
141	141
142		ATTR_COLD virtual void start();
143		ATTR_HOT void update_param();
	142	ATTR_COLD virtual void start();
	143	ATTR_HOT void update_param();
144	144
145		double m_gB; // base conductance / switch on
146		double m_gC; // collector conductance / switch on
147		double m_V; // internal voltage source
148		UINT8 m_state_on;
	145	double m_gB; // base conductance / switch on
	146	double m_gC; // collector conductance / switch on
	147	double m_V; // internal voltage source
	148	UINT8 m_state_on;
149	149
150	150	private:
151	151	};
r29404	r29405
158	158	class NETLIB_NAME(QBJT_EB) : public NETLIB_NAME(QBJT)
159	159	{
160	160	public:
161		ATTR_COLD NETLIB_NAME(QBJT_EB)()
162		: NETLIB_NAME(QBJT)(BJT_EB),
163		m_D_CB(netlist_object_t::ANALOG),
164		m_D_EB(netlist_object_t::ANALOG),
165		m_D_EC(netlist_object_t::ANALOG)
166		{ }
	161	ATTR_COLD NETLIB_NAME(QBJT_EB)()
	162	: NETLIB_NAME(QBJT)(BJT_EB),
	163	m_D_CB(netlist_object_t::ANALOG),
	164	m_D_EB(netlist_object_t::ANALOG),
	165	m_D_EC(netlist_object_t::ANALOG)
	166	{ }
167	167
168		NETLIB_UPDATE_TERMINALS()
169		{
170		double polarity = (qtype() == BJT_NPN ? 1.0 : -1.0);
	168	NETLIB_UPDATE_TERMINALS()
	169	{
	170	double polarity = (qtype() == BJT_NPN ? 1.0 : -1.0);
171	171
172		m_gD_BE.update_diode(-m_D_EB.deltaV() * polarity);
173		m_gD_BC.update_diode(-m_D_CB.deltaV() * polarity);
	172	m_gD_BE.update_diode(-m_D_EB.deltaV() * polarity);
	173	m_gD_BC.update_diode(-m_D_CB.deltaV() * polarity);
174	174
175		double gee = m_gD_BE.G();
176		double gcc = m_gD_BC.G();
177		double gec = m_alpha_r * gcc;
178		double gce = m_alpha_f * gee;
179		double sIe = -m_gD_BE.I() + m_alpha_r * m_gD_BC.I();
180		double sIc = m_alpha_f * m_gD_BE.I() - m_gD_BC.I();
181		double Ie = (sIe + gee * m_gD_BE.Vd() - gec * m_gD_BC.Vd()) * polarity;
182		double Ic = (sIc - gce * m_gD_BE.Vd() + gcc * m_gD_BC.Vd()) * polarity;
183		//double Ie = sIe + gee * -m_D_EB.deltaV() - gec * -m_D_CB.deltaV();
184		//double Ic = sIc - gce * -m_D_EB.deltaV() + gcc * -m_D_CB.deltaV();
185		//printf("EB %f sIe %f sIc %f\n", m_D_BE.deltaV(), sIe, sIc);
	175	double gee = m_gD_BE.G();
	176	double gcc = m_gD_BC.G();
	177	double gec = m_alpha_r * gcc;
	178	double gce = m_alpha_f * gee;
	179	double sIe = -m_gD_BE.I() + m_alpha_r * m_gD_BC.I();
	180	double sIc = m_alpha_f * m_gD_BE.I() - m_gD_BC.I();
	181	double Ie = (sIe + gee * m_gD_BE.Vd() - gec * m_gD_BC.Vd()) * polarity;
	182	double Ic = (sIc - gce * m_gD_BE.Vd() + gcc * m_gD_BC.Vd()) * polarity;
	183	//double Ie = sIe + gee * -m_D_EB.deltaV() - gec * -m_D_CB.deltaV();
	184	//double Ic = sIc - gce * -m_D_EB.deltaV() + gcc * -m_D_CB.deltaV();
	185	//printf("EB %f sIe %f sIc %f\n", m_D_BE.deltaV(), sIe, sIc);
186	186
187		m_D_EB.set_mat(gee, gec - gee, gce - gee, gee - gec, Ie, -Ie);
188		m_D_CB.set_mat(gcc, gce - gcc, gec - gcc, gcc - gce, Ic, -Ic);
189		m_D_EC.set_mat( 0, -gec, -gce, 0, 0, 0);
190		}
	187	m_D_EB.set_mat(gee, gec - gee, gce - gee, gee - gec, Ie, -Ie);
	188	m_D_CB.set_mat(gcc, gce - gcc, gec - gcc, gcc - gce, Ic, -Ic);
	189	m_D_EC.set_mat( 0, -gec, -gce, 0, 0, 0);
	190	}
191	191
192	192	protected:
193	193
194		ATTR_COLD virtual void start();
195		ATTR_COLD virtual void reset();
196		ATTR_HOT void update_param();
197		ATTR_HOT ATTR_ALIGN void virtual update();
	194	ATTR_COLD virtual void start();
	195	ATTR_COLD virtual void reset();
	196	ATTR_HOT void update_param();
	197	ATTR_HOT ATTR_ALIGN void virtual update();
198	198
199		netlist_generic_diode m_gD_BC;
200		netlist_generic_diode m_gD_BE;
	199	netlist_generic_diode m_gD_BC;
	200	netlist_generic_diode m_gD_BE;
201	201
202		nld_twoterm m_D_CB; // gcc, gce - gcc, gec - gcc, gcc - gce \| Ic
203		nld_twoterm m_D_EB; // gee, gec - gee, gce - gee, gee - gec \| Ie
204		nld_twoterm m_D_EC; // 0, -gec, -gcc, 0 \| 0
	202	nld_twoterm m_D_CB; // gcc, gce - gcc, gec - gcc, gcc - gce \| Ic
	203	nld_twoterm m_D_EB; // gee, gec - gee, gce - gee, gee - gec \| Ie
	204	nld_twoterm m_D_EC; // 0, -gec, -gcc, 0 \| 0
205	205
206		double m_alpha_f;
207		double m_alpha_r;
	206	double m_alpha_f;
	207	double m_alpha_r;
208	208
209	209	private:
210	210	};

trunk/src/emu/netlist/analog/nld_twoterm.h
r29404	r29405
84	84	m_P.m_Idr = ( V) * G - I;
85	85	}
86	86
87		ATTR_HOT inline double deltaV() { return m_P.net().Q_Analog()- m_N.net().Q_Analog(); }
	87	ATTR_HOT inline double deltaV() { return m_P.net().Q_Analog()- m_N.net().Q_Analog(); }
88	88
89		ATTR_HOT void set_mat(double a11, double a12, double a21, double a22, double r1, double r2)
90		{
91		m_P.m_gt = a11;
92		m_P.m_go = -a12;
93		m_N.m_gt = a22;
94		m_N.m_go = -a21;
	89	ATTR_HOT void set_mat(double a11, double a12, double a21, double a22, double r1, double r2)
	90	{
	91	m_P.m_gt = a11;
	92	m_P.m_go = -a12;
	93	m_N.m_gt = a22;
	94	m_N.m_go = -a21;
95	95
96		m_P.m_Idr = -r1;
97		m_N.m_Idr = -r2;
	96	m_P.m_Idr = -r1;
	97	m_N.m_Idr = -r2;
98	98
99		}
	99	}
100	100
101	101	protected:
102	102	ATTR_COLD virtual void start();
103		ATTR_COLD virtual void reset();
	103	ATTR_COLD virtual void reset();
104	104	ATTR_HOT ATTR_ALIGN void update();
105	105
106	106	private:
r29404	r29405
119	119
120	120	protected:
121	121	ATTR_COLD virtual void start();
122		ATTR_COLD virtual void reset();
	122	ATTR_COLD virtual void reset();
123	123	ATTR_HOT ATTR_ALIGN void update();
124	124	};
125	125
r29404	r29405
159	159
160	160	protected:
161	161	ATTR_COLD virtual void start();
162		ATTR_COLD virtual void reset();
	162	ATTR_COLD virtual void reset();
163	163	ATTR_COLD virtual void update_param();
164	164	ATTR_HOT ATTR_ALIGN void update();
165	165
r29404	r29405
175	175	class netlist_generic_diode
176	176	{
177	177	public:
178		ATTR_COLD netlist_generic_diode();
	178	ATTR_COLD netlist_generic_diode();
179	179
180		ATTR_HOT inline void update_diode(const double nVd)
181		{
182		//FIXME: Optimize cutoff case
	180	ATTR_HOT inline void update_diode(const double nVd)
	181	{
	182	//FIXME: Optimize cutoff case
183	183
184		if (nVd < -5.0 * m_Vt)
185		{
186		m_Vd = nVd;
187		m_G = m_gmin;
188		m_Id = - m_Is;
189		}
190		else if (nVd < m_Vcrit)
191		{
192		m_Vd = nVd;
	184	if (nVd < -5.0 * m_Vt)
	185	{
	186	m_Vd = nVd;
	187	m_G = m_gmin;
	188	m_Id = - m_Is;
	189	}
	190	else if (nVd < m_Vcrit)
	191	{
	192	m_Vd = nVd;
193	193
194		const double eVDVt = exp(m_Vd * m_VtInv);
195		m_Id = m_Is * (eVDVt - 1.0);
196		m_G = m_Is * m_VtInv * eVDVt + m_gmin;
197		}
198		else
199		{
	194	const double eVDVt = exp(m_Vd * m_VtInv);
	195	m_Id = m_Is * (eVDVt - 1.0);
	196	m_G = m_Is * m_VtInv * eVDVt + m_gmin;
	197	}
	198	else
	199	{
200	200	#if defined(_MSC_VER) && _MSC_VER < 1800
201		m_Vd = m_Vd + log((nVd - m_Vd) * m_VtInv + 1.0) * m_Vt;
	201	m_Vd = m_Vd + log((nVd - m_Vd) * m_VtInv + 1.0) * m_Vt;
202	202	#else
203		double a = (nVd - m_Vd) * m_VtInv;
204		if (a<1e-12 - 1.0) a = 1e-12 - 1.0;
205		m_Vd = m_Vd + log1p(a) * m_Vt;
	203	double a = (nVd - m_Vd) * m_VtInv;
	204	if (a<1e-12 - 1.0) a = 1e-12 - 1.0;
	205	m_Vd = m_Vd + log1p(a) * m_Vt;
206	206	#endif
207		const double eVDVt = exp(m_Vd * m_VtInv);
208		m_Id = m_Is * (eVDVt - 1.0);
	207	const double eVDVt = exp(m_Vd * m_VtInv);
	208	m_Id = m_Is * (eVDVt - 1.0);
209	209
210		m_G = m_Is * m_VtInv * eVDVt + m_gmin;
211		}
	210	m_G = m_Is * m_VtInv * eVDVt + m_gmin;
	211	}
212	212
213		//printf("nVd %f m_Vd %f Vcrit %f\n", nVd, m_Vd, m_Vcrit);
214		}
	213	//printf("nVd %f m_Vd %f Vcrit %f\n", nVd, m_Vd, m_Vcrit);
	214	}
215	215
216		ATTR_COLD void set_param(const double Is, const double n, double gmin);
	216	ATTR_COLD void set_param(const double Is, const double n, double gmin);
217	217
218		ATTR_HOT inline double I() const { return m_Id; }
219		ATTR_HOT inline double G() const { return m_G; }
220		ATTR_HOT inline double Ieq() const { return (m_Id - m_Vd * m_G); }
221		ATTR_HOT inline double Vd() const { return m_Vd; }
	218	ATTR_HOT inline double I() const { return m_Id; }
	219	ATTR_HOT inline double G() const { return m_G; }
	220	ATTR_HOT inline double Ieq() const { return (m_Id - m_Vd * m_G); }
	221	ATTR_HOT inline double Vd() const { return m_Vd; }
222	222
223		/* owning object must save those ... */
	223	/* owning object must save those ... */
224	224
225		ATTR_COLD void save(pstring name, netlist_object_t &parent);
	225	ATTR_COLD void save(pstring name, netlist_object_t &parent);
226	226
227	227	private:
228		double m_Vd;
229		double m_Id;
230		double m_G;
	228	double m_Vd;
	229	double m_Id;
	230	double m_G;
231	231
232		double m_Vt;
233		double m_Is;
234		double m_n;
235		double m_gmin;
	232	double m_Vt;
	233	double m_Is;
	234	double m_n;
	235	double m_gmin;
236	236
237		double m_VtInv;
238		double m_Vcrit;
	237	double m_VtInv;
	238	double m_Vcrit;
239	239	};
240	240
241	241	// ----------------------------------------------------------------------------------------
r29404	r29405
278	278
279	279	NETLIB_UPDATE_TERMINALS()
280	280	{
281		m_D.update_diode(deltaV());
	281	m_D.update_diode(deltaV());
282	282	set(m_D.G(), 0.0, m_D.Ieq());
283	283	}
284	284

trunk/src/emu/netlist/analog/nld_fourterm.h
r29404	r29405
15	15	// ----------------------------------------------------------------------------------------
16	16
17	17	#define VCCS(_name) \
18		NET_REGISTER_DEV(VCCS, _name)
	18	NET_REGISTER_DEV(VCCS, _name)
19	19
20	20	#define VCVS(_name) \
21		NET_REGISTER_DEV(VCVS, _name)
	21	NET_REGISTER_DEV(VCVS, _name)
22	22
23	23	// ----------------------------------------------------------------------------------------
24	24	// nld_CCCS
r29404	r29405
70	70	class NETLIB_NAME(VCCS) : public netlist_device_t
71	71	{
72	72	public:
73		ATTR_COLD NETLIB_NAME(VCCS)()
74		: netlist_device_t(VCCS) { }
75		ATTR_COLD NETLIB_NAME(VCCS)(const family_t afamily)
76		: netlist_device_t(afamily) { }
	73	ATTR_COLD NETLIB_NAME(VCCS)()
	74	: netlist_device_t(VCCS) { }
	75	ATTR_COLD NETLIB_NAME(VCCS)(const family_t afamily)
	76	: netlist_device_t(afamily) { }
77	77
78	78	protected:
79		ATTR_COLD virtual void start();
80		ATTR_COLD virtual void reset();
81		ATTR_COLD virtual void update_param();
82		ATTR_HOT ATTR_ALIGN void update();
	79	ATTR_COLD virtual void start();
	80	ATTR_COLD virtual void reset();
	81	ATTR_COLD virtual void update_param();
	82	ATTR_HOT ATTR_ALIGN void update();
83	83
84		netlist_terminal_t m_OP;
85		netlist_terminal_t m_ON;
	84	netlist_terminal_t m_OP;
	85	netlist_terminal_t m_ON;
86	86
87		netlist_terminal_t m_IP;
88		netlist_terminal_t m_IN;
	87	netlist_terminal_t m_IP;
	88	netlist_terminal_t m_IN;
89	89
90		netlist_terminal_t m_OP1;
91		netlist_terminal_t m_ON1;
	90	netlist_terminal_t m_OP1;
	91	netlist_terminal_t m_ON1;
92	92
93		netlist_param_double_t m_G;
94		netlist_param_double_t m_RI;
	93	netlist_param_double_t m_G;
	94	netlist_param_double_t m_RI;
95	95
96		double m_gfac;
	96	double m_gfac;
97	97	};
98	98
99	99	// ----------------------------------------------------------------------------------------
r29404	r29405
127	127	class NETLIB_NAME(VCVS) : public NETLIB_NAME(VCCS)
128	128	{
129	129	public:
130		ATTR_COLD NETLIB_NAME(VCVS)()
131		: NETLIB_NAME(VCCS)(VCVS) { }
	130	ATTR_COLD NETLIB_NAME(VCVS)()
	131	: NETLIB_NAME(VCCS)(VCVS) { }
132	132
133	133	protected:
134		ATTR_COLD virtual void start();
135		ATTR_COLD virtual void reset();
136		ATTR_COLD virtual void update_param();
137		//ATTR_HOT ATTR_ALIGN void update();
	134	ATTR_COLD virtual void start();
	135	ATTR_COLD virtual void reset();
	136	ATTR_COLD virtual void update_param();
	137	//ATTR_HOT ATTR_ALIGN void update();
138	138
139		netlist_terminal_t m_OP2;
140		netlist_terminal_t m_ON2;
	139	netlist_terminal_t m_OP2;
	140	netlist_terminal_t m_ON2;
141	141
142		netlist_param_double_t m_RO;
	142	netlist_param_double_t m_RO;
143	143	};
144	144
145	145

trunk/src/emu/digfx.c
r29404	r29405
89	89	device().tag(),
90	90	(m_palette_is_sibling ? "sibling " : "sub"),
91	91	m_palette_tag);
92
	92
93	93	// if palette device isn't started, wait for it
94	94	// if (!m_palette->started())
95		// throw device_missing_dependencies();
	95	// throw device_missing_dependencies();
96	96	}
97	97
98	98

trunk/src/emu/digfx.h
r29404	r29405
212	212
213	213	private:
214	214	// configuration
215		const gfx_decode_entry * m_gfxdecodeinfo; // pointer to array of gfx decode information
216		const char * m_palette_tag; // configured tag for palette device
217		bool m_palette_is_sibling; // is palette a sibling or a subdevice?
	215	const gfx_decode_entry * m_gfxdecodeinfo; // pointer to array of gfx decode information
	216	const char * m_palette_tag; // configured tag for palette device
	217	bool m_palette_is_sibling; // is palette a sibling or a subdevice?
218	218
219	219	// internal state
220		bool m_decoded; // have we processed our decode info yet?
221		palette_device * m_palette; // pointer to the palette device
222		auto_pointer<gfx_element> m_gfx[MAX_GFX_ELEMENTS]; // array of pointers to graphic sets
	220	bool m_decoded; // have we processed our decode info yet?
	221	palette_device * m_palette; // pointer to the palette device
	222	auto_pointer<gfx_element> m_gfx[MAX_GFX_ELEMENTS]; // array of pointers to graphic sets
223	223	};
224	224
225	225	// iterator

trunk/src/emu/screen.c
r29404	r29405
226	226
227	227
228	228	//-------------------------------------------------
229		// static_set_video_attributes - set the screen
	229	// static_set_video_attributes - set the screen
230	230	// video attributes
231	231	//-------------------------------------------------
232	232
r29404	r29405
260	260	// check for zero frame rate
261	261	if (m_refresh == 0)
262	262	mame_printf_error("Invalid (zero) refresh rate\n");
263
	263
264	264	texture_format texformat = !m_screen_update_ind16.isnull() ? TEXFORMAT_PALETTE16 : TEXFORMAT_RGB32;
265	265	if (m_palette == NULL && texformat == TEXFORMAT_PALETTE16)
266		mame_printf_error("Screen does not have palette defined\n");
	266	mame_printf_error("Screen does not have palette defined\n");
267	267	if (m_palette != NULL && texformat == TEXFORMAT_RGB32)
268	268	mame_printf_warning("Screen does not need palette defined\n");
269	269	}
r29404	r29405
279	279	m_screen_update_ind16.bind_relative_to(*owner());
280	280	m_screen_update_rgb32.bind_relative_to(*owner());
281	281	m_screen_vblank.bind_relative_to(*owner());
282
	282
283	283	// if we have a palette and it's not started, wait for it
284	284	if (m_palette != NULL && !m_palette->started())
285	285	throw device_missing_dependencies();

trunk/src/emu/screen.h
r29404	r29405
261	261	screen_update_ind16_delegate m_screen_update_ind16; // screen update callback (16-bit palette)
262	262	screen_update_rgb32_delegate m_screen_update_rgb32; // screen update callback (32-bit RGB)
263	263	screen_vblank_delegate m_screen_vblank; // screen vblank callback
264		optional_device<palette_device> m_palette; // our palette
	264	optional_device<palette_device> m_palette; // our palette
265	265	UINT32 m_video_attributes; // flags describing the video system
266	266
267	267	// internal state

trunk/src/emu/drivenum.c
r29404	r29405
244	244	{
245	245	memset(m_included, 1, sizeof(m_included[0]) * s_driver_count);
246	246	m_filtered_count = s_driver_count;
247
	247
248	248	// always exclude the empty driver
249	249	int empty = find("___empty");
250	250	assert(empty != -1);
r29404	r29405
385	385	//-------------------------------------------------
386	386	// release_current - release bulky memory
387	387	// structures from the current entry because
388		// we're done with it
	388	// we're done with it
389	389	//-------------------------------------------------
390	390
391	391	void driver_enumerator::release_current()
r29404	r29405
393	393	// skip if no current entry
394	394	if (m_current < 0 \|\| m_current >= s_driver_count)
395	395	return;
396
	396
397	397	// skip if we haven't cached a config
398	398	if (m_config[m_current] == NULL)
399	399	return;

trunk/src/emu/drawgfx.h
r29404	r29405
87	87	if (m_dirty[code]) decode(code);
88	88	return m_pen_usage[code];
89	89	}
90
	90
91	91	// ----- core graphics drawing -----
92	92
93	93	// specific drawgfx implementations for each transparency type

trunk/src/emu/delegate.h
r29404	r29405
93	93
94	94	// select which one we will be using
95	95	#if defined(__GNUC__)
96		/* does not work in versions over 4.7.x of 32bit MINGW */
	96	/* does not work in versions over 4.7.x of 32bit MINGW */
97	97	#if ((defined(__MINGW32__) && !defined(__x86_64) && defined(__i386__) && (__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)))
98	98	#define USE_DELEGATE_TYPE DELEGATE_TYPE_COMPATIBLE
99	99	#elif defined(SDLMAME_EMSCRIPTEN)
100	100	#define USE_DELEGATE_TYPE DELEGATE_TYPE_COMPATIBLE
101		#else
	101	#else
102	102	#define USE_DELEGATE_TYPE DELEGATE_TYPE_INTERNAL
103		#endif
	103	#endif
104	104	#else
105	105	#define USE_DELEGATE_TYPE DELEGATE_TYPE_COMPATIBLE
106	106	#endif
r29404	r29405
459	459	return reinterpret_cast<delegate_generic_function>(funcptr);
460	460	}
461	461
462
	462
463	463	struct raw_mfp_data
464	464	{
465	465	#if defined (__INTEL_COMPILER) && defined (PTR64) // needed for "Intel(R) C++ Intel(R) 64 Compiler XE for applications running on Intel(R) 64, Version 14.0.2.176 Build 20140130" at least

trunk/src/emu/cpu/g65816/g65816.h
r29404	r29405
66	66	{
67	67	public:
68	68	_5a22_device(const machine_config &mconfig, device_type type, const char tag, device_t owner, UINT32 clock);
69
	69
70	70	DECLARE_WRITE8_MEMBER( wrmpya_w );
71	71	DECLARE_WRITE8_MEMBER( wrmpyb_w );
72	72	DECLARE_WRITE8_MEMBER( wrdivl_w );
r29404	r29405
77	77	DECLARE_READ8_MEMBER( rddivh_r );
78	78	DECLARE_READ8_MEMBER( rdmpyl_r );
79	79	DECLARE_READ8_MEMBER( rdmpyh_r );
80
	80
81	81	void set_5a22_map();
82	82	};
83	83

trunk/src/emu/cpu/z180/z180.c
r29404	r29405
2600	2600	break;
2601	2601	}
2602	2602	}
2603

trunk/src/emu/cpu/z180/z180tbl.h
r29404	r29405
228	228	EXEC_PROTOTYPE(ed)
229	229	EXEC_PROTOTYPE(fd)
230	230	EXEC_PROTOTYPE(xycb)
231

trunk/src/emu/cpu/cosmac/cosmac.h
r29404	r29405
374	374	const address_space_config m_io_config;
375	375
376	376	// device callbacks
377		devcb2_read_line m_read_wait;
378		devcb2_read_line m_read_clear;
379		devcb2_read_line m_read_ef1;
380		devcb2_read_line m_read_ef2;
381		devcb2_read_line m_read_ef3;
382		devcb2_read_line m_read_ef4;
	377	devcb2_read_line m_read_wait;
	378	devcb2_read_line m_read_clear;
	379	devcb2_read_line m_read_ef1;
	380	devcb2_read_line m_read_ef2;
	381	devcb2_read_line m_read_ef3;
	382	devcb2_read_line m_read_ef4;
383	383	devcb2_write_line m_write_q;
384		devcb2_read8 m_read_dma;
385		devcb2_write8 m_write_dma;
386		devcb2_write8 m_write_sc;
	384	devcb2_read8 m_read_dma;
	385	devcb2_write8 m_write_dma;
	386	devcb2_write8 m_write_sc;
387	387
388	388	// control modes
389	389	enum cosmac_mode

trunk/src/emu/cpu/cubeqcpu/cubeqcpu.h
r29404	r29405
357	357	UINT32 m_clkcnt;
358	358
359	359	/* RAM */
360		UINT16 m_sram[4096]; /* Shared with rotate CPU */
361		UINT8 m_ptr_ram[1024]; /* Pointer RAM */
362		UINT32 m_e_stack[32768]; /* Stack DRAM: 32kx20 */
363		UINT32 m_o_stack[32768]; /* Stack DRAM: 32kx20 */
	360	UINT16 m_sram[4096]; /* Shared with rotate CPU */
	361	UINT8 m_ptr_ram[1024]; /* Pointer RAM */
	362	UINT32 m_e_stack[32768]; /* Stack DRAM: 32kx20 */
	363	UINT32 m_o_stack[32768]; /* Stack DRAM: 32kx20 */
364	364
365	365	address_space *m_program;
366	366	direct_read_data *m_direct;

trunk/src/emu/cpu/avr8/avr8.c
r29404	r29405
633	633	m_data_config("data", ENDIANNESS_LITTLE, 8, 16, 0, internal_map),
634	634	m_io_config("io", ENDIANNESS_LITTLE, 8, 4),
635	635	m_eeprom(NULL),
636		m_cpu_type(cpu_type),
637		m_lfuses(0x62),
638		m_hfuses(0x99),
639		m_efuses(0xFF),
640		m_lock_bits(0xFF),
	636	m_cpu_type(cpu_type),
	637	m_lfuses(0x62),
	638	m_hfuses(0x99),
	639	m_efuses(0xFF),
	640	m_lock_bits(0xFF),
641	641	m_pc(0),
642	642	m_spi_active(false),
643	643	m_spi_prescale(0),
r29404	r29405
649	649	{
650	650	// Allocate & setup
651	651
652		for (int t=0; t<=5; t++){
	652	for (int t=0; t<=5; t++){
653	653	m_timer_top[t] = 0;
654	654	m_timer_increment[t] = 1;
655	655	m_timer_prescale[t] = 0;
656	656	m_timer_prescale_count[t] = 0;
657		}
	657	}
658	658	}
659	659
660	660
r29404	r29405
675	675
676	676	void avr8_device::set_low_fuses(const UINT8 byte)
677	677	{
678		m_lfuses = byte;
	678	m_lfuses = byte;
679	679	}
680	680
681	681	//-------------------------------------------------
r29404	r29405
684	684
685	685	void avr8_device::set_high_fuses(const UINT8 byte)
686	686	{
687		m_hfuses = byte;
	687	m_hfuses = byte;
688	688	}
689	689
690	690	//-------------------------------------------------
r29404	r29405
693	693
694	694	void avr8_device::set_extended_fuses(const UINT8 byte)
695	695	{
696		m_efuses = byte;
	696	m_efuses = byte;
697	697	}
698	698
699	699	//-------------------------------------------------
r29404	r29405
702	702
703	703	void avr8_device::set_lock_bits(const UINT8 byte)
704	704	{
705		m_lock_bits = byte;
	705	m_lock_bits = byte;
706	706	}
707	707
708	708	//-------------------------------------------------
r29404	r29405
841	841
842	842	void avr8_device::device_reset()
843	843	{
844		logerror("AVR low fuse bits: 0x%02X\n", m_lfuses);
845		logerror("AVR high fuse bits: 0x%02X\n", m_hfuses);
846		logerror("AVR extended fuse bits: 0x%02X\n", m_efuses);
847		logerror("AVR lock bits: 0x%02X\n", m_lock_bits);
	844	logerror("AVR low fuse bits: 0x%02X\n", m_lfuses);
	845	logerror("AVR high fuse bits: 0x%02X\n", m_hfuses);
	846	logerror("AVR extended fuse bits: 0x%02X\n", m_efuses);
	847	logerror("AVR lock bits: 0x%02X\n", m_lock_bits);
848	848
849		switch ((m_hfuses & (BOOTSZ1\|BOOTSZ0)) >> 1){
850		case 0: m_boot_size = 4096; break;
851		case 1: m_boot_size = 2048; break;
852		case 2: m_boot_size = 1024; break;
853		case 3: m_boot_size = 512; break;
854		default: break;
855		}
	849	switch ((m_hfuses & (BOOTSZ1\|BOOTSZ0)) >> 1){
	850	case 0: m_boot_size = 4096; break;
	851	case 1: m_boot_size = 2048; break;
	852	case 2: m_boot_size = 1024; break;
	853	case 3: m_boot_size = 512; break;
	854	default: break;
	855	}
856	856
857		if (m_hfuses & BOOTRST){
858		m_shifted_pc = 0x0000;
859		logerror("Booting AVR core from address 0x0000\n");
860		} else {
861		m_shifted_pc = (m_addr_mask + 1) - 2*m_boot_size;
862		logerror("AVR Boot loader section size: %d words\n", m_boot_size);
863		}
	857	if (m_hfuses & BOOTRST){
	858	m_shifted_pc = 0x0000;
	859	logerror("Booting AVR core from address 0x0000\n");
	860	} else {
	861	m_shifted_pc = (m_addr_mask + 1) - 2*m_boot_size;
	862	logerror("AVR Boot loader section size: %d words\n", m_boot_size);
	863	}
864	864
865	865	for (int i = 0; i < 0x200; i++)
866	866	{
r29404	r29405
871	871	m_spi_prescale = 0;
872	872	m_spi_prescale_count = 0;
873	873
874		for (int t=0; t<=5; t++){
	874	for (int t=0; t<=5; t++){
875	875	m_timer_top[t] = 0;
876	876	m_timer_increment[t] = 1;
877	877	m_timer_prescale[t] = 0;
878	878	m_timer_prescale_count[t] = 0;
879		}
	879	}
880	880
881	881	m_interrupt_pending = false;
882	882	m_elapsed_cycles = 0;
r29404	r29405
1136	1136	}
1137	1137	}
1138	1138
1139		for (int t=0; t<=5; t++){
1140		if (m_timer_prescale[t] != 0)
1141		{
1142		m_timer_prescale_count[t]++;
1143		if (m_timer_prescale_count[t] >= m_timer_prescale[t])
1144		{
1145		switch (t){
1146		case 0: timer0_tick(); break;
1147		case 1: timer1_tick(); break;
1148		case 2: timer2_tick(); break;
1149		case 3: timer3_tick(); break;
1150		case 4: timer4_tick(); break;
1151		case 5: timer5_tick(); break;
1152		}
1153		m_timer_prescale_count[t] -= m_timer_prescale[t];
1154		}
1155		}
1156		}
	1139	for (int t=0; t<=5; t++){
	1140	if (m_timer_prescale[t] != 0)
	1141	{
	1142	m_timer_prescale_count[t]++;
	1143	if (m_timer_prescale_count[t] >= m_timer_prescale[t])
	1144	{
	1145	switch (t){
	1146	case 0: timer0_tick(); break;
	1147	case 1: timer1_tick(); break;
	1148	case 2: timer2_tick(); break;
	1149	case 3: timer3_tick(); break;
	1150	case 4: timer4_tick(); break;
	1151	case 5: timer5_tick(); break;
	1152	}
	1153	m_timer_prescale_count[t] -= m_timer_prescale[t];
	1154	}
	1155	}
	1156	}
1157	1157
1158	1158	}
1159	1159	}
1160	1160
1161		// UINT8 ocr0[2] = { m_r[AVR8_REGIDX_OCR0A], m_r[AVR8_REGIDX_OCR0B] };
1162		//TODO UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR4_OCF0B_SHIFT) };
1163		//TODO UINT8 int0[2] = { AVR8_INTIDX_OCF0A, AVR8_INTIDX_OCF0B };
	1161	// UINT8 ocr0[2] = { m_r[AVR8_REGIDX_OCR0A], m_r[AVR8_REGIDX_OCR0B] };
	1162	//TODO UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR4_OCF0B_SHIFT) };
	1163	//TODO UINT8 int0[2] = { AVR8_INTIDX_OCF0A, AVR8_INTIDX_OCF0B };
1164	1164
1165	1165	#define LOG_TIMER_0 0
1166	1166	#define LOG_TIMER_5 1
r29404	r29405
1168	1168	void avr8_device::timer0_tick()
1169	1169	{
1170	1170	#if LOG_TIMER_0
1171		printf("AVR8_WGM0: %d\n", AVR8_WGM0);
1172		printf("AVR8_TCCR0A_COM0B: %d\n", AVR8_TCCR0A_COM0B);
	1171	printf("AVR8_WGM0: %d\n", AVR8_WGM0);
	1172	printf("AVR8_TCCR0A_COM0B: %d\n", AVR8_TCCR0A_COM0B);
1173	1173	#endif
1174	1174
1175	1175	UINT8 count = m_r[AVR8_REGIDX_TCNT0];
r29404	r29405
1178	1178	switch(AVR8_WGM0)
1179	1179	{
1180	1180	case WGM02_NORMAL:
1181		printf("WGM02_NORMAL: Unimplemented timer#0 waveform generation mode\n");
1182		break;
	1181	printf("WGM02_NORMAL: Unimplemented timer#0 waveform generation mode\n");
	1182	break;
1183	1183
1184	1184	case WGM02_PWM_PC:
1185		printf("WGM02_PWM_PC: Unimplemented timer#0 waveform generation mode\n");
1186		break;
	1185	printf("WGM02_PWM_PC: Unimplemented timer#0 waveform generation mode\n");
	1186	break;
1187	1187
1188	1188	case WGM02_CTC_CMP:
1189		switch(AVR8_TCCR0A_COM0B){
1190		case 0: /* Normal Operation */
1191		if (count == m_timer_top[0]){
1192		m_timer_top[0] = 0;
1193		}
1194		break;
1195		case 1: /* Toggle OC0B on compare match */
1196		if (count == m_timer_top[0]){
1197		m_timer_top[0] = 0;
	1189	switch(AVR8_TCCR0A_COM0B){
	1190	case 0: /* Normal Operation */
	1191	if (count == m_timer_top[0]){
	1192	m_timer_top[0] = 0;
	1193	}
	1194	break;
	1195	case 1: /* Toggle OC0B on compare match */
	1196	if (count == m_timer_top[0]){
	1197	m_timer_top[0] = 0;
1198	1198	#if LOG_TIMER_0
1199		printf("[0] Toggle OC0B\n");
	1199	printf("[0] Toggle OC0B\n");
1200	1200	#endif
1201		m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) ^ (1 << 5));
1202		}
1203		break;
1204		case 2: /* Clear OC0B on compare match */
1205		if (count == m_timer_top[0]){
1206		m_timer_top[0] = 0;
1207		//Clear OC0B
	1201	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) ^ (1 << 5));
	1202	}
	1203	break;
	1204	case 2: /* Clear OC0B on compare match */
	1205	if (count == m_timer_top[0]){
	1206	m_timer_top[0] = 0;
	1207	//Clear OC0B
1208	1208	#if LOG_TIMER_0
1209		printf("[0] Clear OC0B\n");
	1209	printf("[0] Clear OC0B\n");
1210	1210	#endif
1211		m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) & ~(1 << 5));
1212		}
1213		break;
1214		case 3: /* Set OC0B on compare match */
1215		if (count == m_timer_top[0]){
1216		m_timer_top[0] = 0;
	1211	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) & ~(1 << 5));
	1212	}
	1213	break;
	1214	case 3: /* Set OC0B on compare match */
	1215	if (count == m_timer_top[0]){
	1216	m_timer_top[0] = 0;
1217	1217	#if LOG_TIMER_0
1218		printf("[0] Set OC0B\n");
	1218	printf("[0] Set OC0B\n");
1219	1219	#endif
1220		m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) \| (1 << 5));
1221		}
1222		break;
1223		}
1224		break;
	1220	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) \| (1 << 5));
	1221	}
	1222	break;
	1223	}
	1224	break;
1225	1225
1226	1226	case WGM02_FAST_PWM:
1227		printf("WGM02_FAST_PWM: Unimplemented timer#0 waveform generation mode\n");
1228		break;
	1227	printf("WGM02_FAST_PWM: Unimplemented timer#0 waveform generation mode\n");
	1228	break;
1229	1229
1230	1230	case WGM02_PWM_PC_CMP:
1231		printf("WGM02_PWM_PC_CMP: Unimplemented timer#0 waveform generation mode\n");
1232		break;
	1231	printf("WGM02_PWM_PC_CMP: Unimplemented timer#0 waveform generation mode\n");
	1232	break;
1233	1233
1234	1234	case WGM02_FAST_PWM_CMP:
1235		printf("WGM02_FAST_PWM_CMP: Unimplemented timer#0 waveform generation mode\n");
1236		break;
	1235	printf("WGM02_FAST_PWM_CMP: Unimplemented timer#0 waveform generation mode\n");
	1236	break;
1237	1237
1238	1238	default:
1239	1239	verboselog(m_pc, 0, "update_timer0_compare_mode: Unknown waveform generation mode: %02x\n", AVR8_WGM0);
1240	1240	break;
1241	1241	}
1242	1242
1243		count = count & 0xff;
	1243	count = count & 0xff;
1244	1244
1245	1245	count += increment;
1246	1246	m_r[AVR8_REGIDX_TCNT0] = count & 0xff;
r29404	r29405
1268	1268
1269	1269	void avr8_device::changed_tccr0b(UINT8 data)
1270	1270	{
1271		if (VERBOSE_LEVEL) printf("changed_tccr0b: data=0x%02X\n", data);
	1271	if (VERBOSE_LEVEL) printf("changed_tccr0b: data=0x%02X\n", data);
1272	1272
1273	1273	UINT8 oldtccr = AVR8_TCCR0B;
1274	1274	UINT8 newtccr = data;
r29404	r29405
1415	1415
1416	1416	void avr8_device::update_timer_waveform_gen_mode(UINT8 t, UINT8 mode)
1417	1417	{
1418		INT32 oc_val = -1, ic_val = -1;
	1418	INT32 oc_val = -1, ic_val = -1;
1419	1419
1420		switch (t){
1421		case 0:
1422		oc_val = AVR8_OCR0A;
1423		ic_val = -1;
1424		break;
1425		case 1:
1426		oc_val = AVR8_OCR1A;
1427		ic_val = AVR8_ICR1;
1428		break;
1429		case 2:
1430		oc_val = AVR8_OCR2A;
1431		ic_val = -1;
1432		break;
1433		case 3:
1434		oc_val = AVR8_OCR3A;
1435		ic_val = AVR8_ICR3;
1436		break;
1437		case 4:
1438		oc_val = AVR8_OCR4A;
1439		ic_val = AVR8_ICR4;
1440		break;
1441		case 5:
1442		oc_val = AVR8_OCR5A;
1443		ic_val = AVR8_ICR5;
1444		break;
1445		}
	1420	switch (t){
	1421	case 0:
	1422	oc_val = AVR8_OCR0A;
	1423	ic_val = -1;
	1424	break;
	1425	case 1:
	1426	oc_val = AVR8_OCR1A;
	1427	ic_val = AVR8_ICR1;
	1428	break;
	1429	case 2:
	1430	oc_val = AVR8_OCR2A;
	1431	ic_val = -1;
	1432	break;
	1433	case 3:
	1434	oc_val = AVR8_OCR3A;
	1435	ic_val = AVR8_ICR3;
	1436	break;
	1437	case 4:
	1438	oc_val = AVR8_OCR4A;
	1439	ic_val = AVR8_ICR4;
	1440	break;
	1441	case 5:
	1442	oc_val = AVR8_OCR5A;
	1443	ic_val = AVR8_ICR5;
	1444	break;
	1445	}
1446	1446
1447		INT32 top_values_02[8] = {0xFF, 0xFF, oc_val, 0xFF, -1, oc_val, -1, oc_val}; //table 20-8
	1447	INT32 top_values_02[8] = {0xFF, 0xFF, oc_val, 0xFF, -1, oc_val, -1, oc_val}; //table 20-8
1448	1448
1449		INT32 top_values_1345[16] = {0xFFFF, 0x00FF, 0x01FF, 0x03FF,
1450		oc_val, 0x00FF, 0x01FF, 0x03FF,
1451		ic_val, oc_val, ic_val, oc_val,
1452		ic_val, -1, ic_val, oc_val}; //table 17-2
	1449	INT32 top_values_1345[16] = {0xFFFF, 0x00FF, 0x01FF, 0x03FF,
	1450	oc_val, 0x00FF, 0x01FF, 0x03FF,
	1451	ic_val, oc_val, ic_val, oc_val,
	1452	ic_val, -1, ic_val, oc_val}; //table 17-2
1453	1453
1454		switch(t){
1455		case 0:
1456		case 2:
1457		m_timer_top[t] = top_values_02[mode];
1458		break;
1459		case 1:
1460		case 3:
1461		case 4:
1462		case 5:
1463		m_timer_top[t] = top_values_1345[mode];
1464		break;
1465		}
	1454	switch(t){
	1455	case 0:
	1456	case 2:
	1457	m_timer_top[t] = top_values_02[mode];
	1458	break;
	1459	case 1:
	1460	case 3:
	1461	case 4:
	1462	case 5:
	1463	m_timer_top[t] = top_values_1345[mode];
	1464	break;
	1465	}
1466	1466
1467		if (m_timer_top[t] == -1){
1468		m_timer_top[t] = 0;
	1467	if (m_timer_top[t] == -1){
	1468	m_timer_top[t] = 0;
1469	1469	printf("update_timer_waveform_gen_mode: Timer #%d - Unsupported waveform generation type: %d\n", t, mode);
1470	1470	}
1471	1471	}
r29404	r29405
1497	1497
1498	1498	void avr8_device::changed_tccr1b(UINT8 data)
1499	1499	{
1500		if (VERBOSE_LEVEL) printf("changed_tccr1b: data=0x%02X\n", data);
	1500	if (VERBOSE_LEVEL) printf("changed_tccr1b: data=0x%02X\n", data);
1501	1501
1502	1502	UINT8 oldtccr = AVR8_TCCR1B;
1503	1503	UINT8 newtccr = data;
r29404	r29405
1651	1651
1652	1652	void avr8_device::changed_tccr2b(UINT8 data)
1653	1653	{
1654		if (VERBOSE_LEVEL) printf("changed_tccr2b: data=0x%02X\n", data);
	1654	if (VERBOSE_LEVEL) printf("changed_tccr2b: data=0x%02X\n", data);
1655	1655
1656	1656	UINT8 oldtccr = AVR8_TCCR2B;
1657	1657	UINT8 newtccr = data;
r29404	r29405
1711	1711	//(m_r[AVR8_REGIDX_TCCR1A] & AVR8_TCCR1A_COM1B_MASK) >> AVR8_TCCR1A_COM1B_SHIFT };
1712	1712	UINT16 ocr4[2] = { (m_r[AVR8_REGIDX_OCR4AH] << 8) \| m_r[AVR8_REGIDX_OCR4AL],
1713	1713	(m_r[AVR8_REGIDX_OCR4BH] << 8) \| m_r[AVR8_REGIDX_OCR4BL] };
1714		//TODO UINT8 ocf4[2] = { (1 << AVR8_TIFR4_OCF4A_SHIFT), (1 << AVR8_TIFR4_OCF4B_SHIFT) };
1715		//TODO UINT8 int4[2] = { AVR8_INTIDX_OCF4A, AVR8_INTIDX_OCF4B };
	1714	//TODO UINT8 ocf4[2] = { (1 << AVR8_TIFR4_OCF4A_SHIFT), (1 << AVR8_TIFR4_OCF4B_SHIFT) };
	1715	//TODO UINT8 int4[2] = { AVR8_INTIDX_OCF4A, AVR8_INTIDX_OCF4B };
1716	1716	INT32 increment = m_timer_increment[4];
1717	1717
1718	1718	switch(AVR8_WGM4)
r29404	r29405
1720	1720	case WGM4_FAST_PWM_8:
1721	1721	case WGM4_FAST_PWM_9:
1722	1722	case WGM4_FAST_PWM_10:
1723		switch(AVR8_TCCR4A_COM4B){
1724		case 0: /* Normal Operation */
1725		break;
1726		case 1: /* TODO */
1727		break;
1728		case 2: /* Non-inverting mode */
1729		if (count == m_timer_top[4]){
1730		//Clear OC0B
1731		printf("[2] Clear OC0B\n");
1732		m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) & ~(1 << 5));
1733		} else if (count == 0){
1734		//Set OC0B
1735		printf("[2] Set OC0B\n");
1736		m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) \| (1 << 5));
1737		}
1738		break;
1739		case 3: /* Inverting mode */
1740		if (count == m_timer_top[4]){
1741		//Set OC0B
1742		printf("[3] Set OC0B\n");
1743		m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) \| (1 << 5));
1744		} else if (count == 0){
1745		//Clear OC0B
1746		printf("[3] Clear OC0B\n");
1747		m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) & ~(1 << 5));
1748		}
1749		break;
1750		}
1751		break;
	1723	switch(AVR8_TCCR4A_COM4B){
	1724	case 0: /* Normal Operation */
	1725	break;
	1726	case 1: /* TODO */
	1727	break;
	1728	case 2: /* Non-inverting mode */
	1729	if (count == m_timer_top[4]){
	1730	//Clear OC0B
	1731	printf("[2] Clear OC0B\n");
	1732	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) & ~(1 << 5));
	1733	} else if (count == 0){
	1734	//Set OC0B
	1735	printf("[2] Set OC0B\n");
	1736	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) \| (1 << 5));
	1737	}
	1738	break;
	1739	case 3: /* Inverting mode */
	1740	if (count == m_timer_top[4]){
	1741	//Set OC0B
	1742	printf("[3] Set OC0B\n");
	1743	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) \| (1 << 5));
	1744	} else if (count == 0){
	1745	//Clear OC0B
	1746	printf("[3] Clear OC0B\n");
	1747	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) & ~(1 << 5));
	1748	}
	1749	break;
	1750	}
	1751	break;
1752	1752
1753	1753	case WGM4_CTC_OCR:
1754		//printf("[T4] tick WGM4_CTC_OCR: %d\n", count);
	1754	//printf("[T4] tick WGM4_CTC_OCR: %d\n", count);
1755	1755	if (count == 0xffff)
1756	1756	{
1757	1757	m_r[AVR8_REGIDX_TIFR4] \|= AVR8_TIFR4_TOV4_MASK;
r29404	r29405
1785	1785
1786	1786	void avr8_device::update_timer_clock_source(UINT8 t, UINT8 clock_select)
1787	1787	{
1788		int prescale_values[8] = {0, 1, 8, 64, 256, 1024, -1, -1};
	1788	int prescale_values[8] = {0, 1, 8, 64, 256, 1024, -1, -1};
1789	1789	m_timer_prescale[t] = prescale_values[clock_select];
1790	1790
1791		if (VERBOSE_LEVEL) printf("update_timer_clock_source: t=%d cs=%d\n", t, clock_select);
	1791	if (VERBOSE_LEVEL) printf("update_timer_clock_source: t=%d cs=%d\n", t, clock_select);
1792	1792
1793		if (m_timer_prescale[t] == 0xFFFF){
1794		printf("[Timer #%d]: update_timer_clock_source: External trigger mode not implemented yet\n", t);
1795		m_timer_prescale[t] = 0;
1796		}
	1793	if (m_timer_prescale[t] == 0xFFFF){
	1794	printf("[Timer #%d]: update_timer_clock_source: External trigger mode not implemented yet\n", t);
	1795	m_timer_prescale[t] = 0;
	1796	}
1797	1797
1798	1798	if (m_timer_prescale_count[t] > m_timer_prescale[t])
1799	1799	m_timer_prescale_count[t] = m_timer_prescale[t] - 1;
r29404	r29405
1801	1801
1802	1802	void avr8_device::changed_tccr3a(UINT8 data)
1803	1803	{
1804		//TODO: Implement-me
1805		// AVR8_TCCR3A = data;
	1804	//TODO: Implement-me
	1805	// AVR8_TCCR3A = data;
1806	1806	}
1807	1807
1808	1808	void avr8_device::changed_tccr3b(UINT8 data)
1809	1809	{
1810		printf("IMPLEMENT-ME: changed_tccr4b: data=0x%02X\n", data);
	1810	printf("IMPLEMENT-ME: changed_tccr4b: data=0x%02X\n", data);
1811	1811	}
1812	1812
1813	1813	void avr8_device::changed_tccr3c(UINT8 data)
1814	1814	{
1815		// UINT8 oldtccr = AVR8_TCCR3C;
1816		// UINT8 newtccr = data;
1817		// UINT8 changed = newtccr ^ oldtccr;
1818		printf("IMPLEMENT-ME: changed_tccr3c: data=0x%02X\n", data);
	1815	// UINT8 oldtccr = AVR8_TCCR3C;
	1816	// UINT8 newtccr = data;
	1817	// UINT8 changed = newtccr ^ oldtccr;
	1818	printf("IMPLEMENT-ME: changed_tccr3c: data=0x%02X\n", data);
1819	1819
1820		// AVR8_TCCR3C = data;
	1820	// AVR8_TCCR3C = data;
1821	1821
1822		//TODO: Implement-me
	1822	//TODO: Implement-me
1823	1823	}
1824	1824
1825	1825	void avr8_device::changed_tccr4a(UINT8 data)
r29404	r29405
1838	1838
1839	1839	void avr8_device::changed_tccr4b(UINT8 data)
1840	1840	{
1841		printf("changed_tccr4b: data=0x%02X\n", data);
	1841	printf("changed_tccr4b: data=0x%02X\n", data);
1842	1842
1843	1843	UINT8 oldtccr = AVR8_TCCR4B;
1844	1844	UINT8 newtccr = data;
r29404	r29405
1849	1849	if(changed & AVR8_TCCR4B_FOC4A_MASK)
1850	1850	{
1851	1851	// TODO
1852		// timer4_force_output_compare(AVR8_REG_A);
	1852	// timer4_force_output_compare(AVR8_REG_A);
1853	1853	}
1854	1854
1855	1855	if(changed & AVR8_TCCR4B_FOC4B_MASK)
1856	1856	{
1857	1857	// TODO
1858		// timer4_force_output_compare(AVR8_REG_B);
	1858	// timer4_force_output_compare(AVR8_REG_B);
1859	1859	}
1860	1860
1861	1861	if(changed & AVR8_TCCR4B_WGM4_32_MASK)
r29404	r29405
1871	1871
1872	1872	void avr8_device::changed_tccr4c(UINT8 data)
1873	1873	{
1874		// UINT8 oldtccr = AVR8_TCCR4C;
1875		// UINT8 newtccr = data;
1876		// UINT8 changed = newtccr ^ oldtccr;
	1874	// UINT8 oldtccr = AVR8_TCCR4C;
	1875	// UINT8 newtccr = data;
	1876	// UINT8 changed = newtccr ^ oldtccr;
1877	1877
1878	1878	AVR8_TCCR4C = data;
1879	1879
1880		//TODO: Implement-me
	1880	//TODO: Implement-me
1881	1881	}
1882	1882
1883	1883	/************************************************************************************************/
r29404	r29405
1886	1886	void avr8_device::timer5_tick()
1887	1887	{
1888	1888	#if LOG_TIMER_5
1889		printf("AVR8_WGM5: %d\n", AVR8_WGM5);
1890		printf("AVR8_TCCR5A_COM5B: %d\n", AVR8_TCCR5A_COM5B);
	1889	printf("AVR8_WGM5: %d\n", AVR8_WGM5);
	1890	printf("AVR8_TCCR5A_COM5B: %d\n", AVR8_TCCR5A_COM5B);
1891	1891	#endif
1892	1892
1893	1893	UINT16 count = (AVR8_TCNT5H << 8) + AVR8_TCNT5L;
r29404	r29405
1896	1896	switch(AVR8_WGM5)
1897	1897	{
1898	1898	case WGM5_NORMAL:
1899		case WGM5_PWM_8_PC:
1900		case WGM5_PWM_9_PC:
1901		case WGM5_PWM_10_PC:
	1899	case WGM5_PWM_8_PC:
	1900	case WGM5_PWM_9_PC:
	1901	case WGM5_PWM_10_PC:
1902	1902	// case WGM5_CTC_OCR:
1903		case WGM5_FAST_PWM_8:
1904		case WGM5_FAST_PWM_9:
1905		case WGM5_FAST_PWM_10:
1906		case WGM5_PWM_PFC_ICR:
1907		case WGM5_PWM_PFC_OCR:
1908		case WGM5_PWM_PC_ICR:
1909		case WGM5_PWM_PC_OCR:
1910		case WGM5_CTC_ICR:
1911		case WGM5_FAST_PWM_ICR:
1912		case WGM5_FAST_PWM_OCR:
1913		printf("Unimplemented timer#5 waveform generation mode: WGMM5=0x%02X\n", AVR8_WGM5);
1914		break;
	1903	case WGM5_FAST_PWM_8:
	1904	case WGM5_FAST_PWM_9:
	1905	case WGM5_FAST_PWM_10:
	1906	case WGM5_PWM_PFC_ICR:
	1907	case WGM5_PWM_PFC_OCR:
	1908	case WGM5_PWM_PC_ICR:
	1909	case WGM5_PWM_PC_OCR:
	1910	case WGM5_CTC_ICR:
	1911	case WGM5_FAST_PWM_ICR:
	1912	case WGM5_FAST_PWM_OCR:
	1913	printf("Unimplemented timer#5 waveform generation mode: WGMM5=0x%02X\n", AVR8_WGM5);
	1914	break;
1915	1915
1916	1916	case WGM5_CTC_OCR:
1917		//TODO: verify this! Can be very wrong!!!
1918		switch(AVR8_TCCR5A_COM5B){
1919		case 0: /* Normal Operation */
1920		if (count == m_timer_top[5]){
1921		m_timer_top[5] = 0;
1922		}
1923		break;
1924		case 1: /* Toggle OC5B on compare match */
1925		if (count == m_timer_top[5]){
1926		m_timer_top[5] = 0;
	1917	//TODO: verify this! Can be very wrong!!!
	1918	switch(AVR8_TCCR5A_COM5B){
	1919	case 0: /* Normal Operation */
	1920	if (count == m_timer_top[5]){
	1921	m_timer_top[5] = 0;
	1922	}
	1923	break;
	1924	case 1: /* Toggle OC5B on compare match */
	1925	if (count == m_timer_top[5]){
	1926	m_timer_top[5] = 0;
1927	1927	#if LOG_TIMER_5
1928		printf("[5] Toggle OC5B\n");
	1928	printf("[5] Toggle OC5B\n");
1929	1929	#endif
1930		m_io->write_byte(AVR8_IO_PORTL, m_io->read_byte(AVR8_IO_PORTL) ^ (1 << 4));
1931		}
1932		break;
1933		case 2: /* Clear OC5B on compare match */
1934		if (count == m_timer_top[5]){
1935		m_timer_top[5] = 0;
1936		//Clear OC5B
	1930	m_io->write_byte(AVR8_IO_PORTL, m_io->read_byte(AVR8_IO_PORTL) ^ (1 << 4));
	1931	}
	1932	break;
	1933	case 2: /* Clear OC5B on compare match */
	1934	if (count == m_timer_top[5]){
	1935	m_timer_top[5] = 0;
	1936	//Clear OC5B
1937	1937	#if LOG_TIMER_5
1938		printf("[5] Clear OC5B\n");
	1938	printf("[5] Clear OC5B\n");
1939	1939	#endif
1940		m_io->write_byte(AVR8_IO_PORTL, m_io->read_byte(AVR8_IO_PORTL) & ~(1 << 4));
1941		}
1942		break;
1943		case 3: /* Set OC5B on compare match */
1944		if (count == m_timer_top[5]){
1945		m_timer_top[5] = 0;
	1940	m_io->write_byte(AVR8_IO_PORTL, m_io->read_byte(AVR8_IO_PORTL) & ~(1 << 4));
	1941	}
	1942	break;
	1943	case 3: /* Set OC5B on compare match */
	1944	if (count == m_timer_top[5]){
	1945	m_timer_top[5] = 0;
1946	1946	#if LOG_TIMER_5
1947		printf("[5] Set OC5B\n");
	1947	printf("[5] Set OC5B\n");
1948	1948	#endif
1949		m_io->write_byte(AVR8_IO_PORTL, m_io->read_byte(AVR8_IO_PORTL) \| (1 << 4));
1950		}
1951		break;
1952		}
1953		break;
	1949	m_io->write_byte(AVR8_IO_PORTL, m_io->read_byte(AVR8_IO_PORTL) \| (1 << 4));
	1950	}
	1951	break;
	1952	}
	1953	break;
1954	1954
1955	1955	default:
1956		printf("Timer #5: Unknown waveform generation mode: %02x\n", AVR8_WGM5);
	1956	printf("Timer #5: Unknown waveform generation mode: %02x\n", AVR8_WGM5);
1957	1957	break;
1958	1958	}
1959	1959
r29404	r29405
1978	1978
1979	1979	void avr8_device::changed_tccr5b(UINT8 data)
1980	1980	{
1981		printf("changed_tccr5b: data=0x%02X\n", data);
	1981	printf("changed_tccr5b: data=0x%02X\n", data);
1982	1982
1983	1983	UINT8 oldtccr = AVR8_TCCR5B;
1984	1984	UINT8 newtccr = data;
r29404	r29405
1989	1989	if(changed & AVR8_TCCR5C_FOC5A_MASK)
1990	1990	{
1991	1991	// TODO
1992		// timer5_force_output_compare(AVR8_REG_A);
	1992	// timer5_force_output_compare(AVR8_REG_A);
1993	1993	}
1994	1994
1995	1995	if(changed & AVR8_TCCR5C_FOC5B_MASK)
1996	1996	{
1997	1997	// TODO
1998		// timer5_force_output_compare(AVR8_REG_B);
	1998	// timer5_force_output_compare(AVR8_REG_B);
1999	1999	}
2000	2000
2001	2001	if(changed & AVR8_TCCR5C_FOC5C_MASK)
2002	2002	{
2003	2003	// TODO
2004		// timer5_force_output_compare(AVR8_REG_C);
	2004	// timer5_force_output_compare(AVR8_REG_C);
2005	2005	}
2006	2006
2007	2007	if(changed & AVR8_TCCR5B_WGM5_32_MASK)
r29404	r29405
2160	2160	break;
2161	2161
2162	2162	case AVR8_REGIDX_PORTA:
2163		m_io->write_byte(AVR8_IO_PORTA, data);
2164		m_r[AVR8_REGIDX_PORTA] = data;
2165		break;
	2163	m_io->write_byte(AVR8_IO_PORTA, data);
	2164	m_r[AVR8_REGIDX_PORTA] = data;
	2165	break;
2166	2166
2167	2167	case AVR8_REGIDX_PORTB:
2168		m_io->write_byte(AVR8_IO_PORTB, data);
2169		m_r[AVR8_REGIDX_PORTB] = data;
2170		break;
	2168	m_io->write_byte(AVR8_IO_PORTB, data);
	2169	m_r[AVR8_REGIDX_PORTB] = data;
	2170	break;
2171	2171
2172	2172	case AVR8_REGIDX_PORTC:
2173		m_io->write_byte(AVR8_IO_PORTC, data);
2174		m_r[AVR8_REGIDX_PORTC] = data;
2175		break;
	2173	m_io->write_byte(AVR8_IO_PORTC, data);
	2174	m_r[AVR8_REGIDX_PORTC] = data;
	2175	break;
2176	2176
2177	2177	case AVR8_REGIDX_PORTD:
2178		m_io->write_byte(AVR8_IO_PORTD, data);
2179		m_r[AVR8_REGIDX_PORTD] = data;
2180		break;
	2178	m_io->write_byte(AVR8_IO_PORTD, data);
	2179	m_r[AVR8_REGIDX_PORTD] = data;
	2180	break;
2181	2181
2182	2182	case AVR8_REGIDX_PORTE:
2183		m_io->write_byte(AVR8_IO_PORTE, data);
2184		m_r[AVR8_REGIDX_PORTE] = data;
2185		break;
	2183	m_io->write_byte(AVR8_IO_PORTE, data);
	2184	m_r[AVR8_REGIDX_PORTE] = data;
	2185	break;
2186	2186
2187	2187	case AVR8_REGIDX_PORTF:
2188		m_io->write_byte(AVR8_IO_PORTF, data);
2189		m_r[AVR8_REGIDX_PORTF] = data;
2190		break;
	2188	m_io->write_byte(AVR8_IO_PORTF, data);
	2189	m_r[AVR8_REGIDX_PORTF] = data;
	2190	break;
2191	2191
2192	2192	case AVR8_REGIDX_PORTG:
2193		m_io->write_byte(AVR8_IO_PORTG, data);
2194		m_r[AVR8_REGIDX_PORTG] = data;
2195		break;
	2193	m_io->write_byte(AVR8_IO_PORTG, data);
	2194	m_r[AVR8_REGIDX_PORTG] = data;
	2195	break;
2196	2196
2197	2197	case AVR8_REGIDX_PORTH:
2198		m_io->write_byte(AVR8_IO_PORTH, data);
2199		m_r[AVR8_REGIDX_PORTH] = data;
2200		break;
	2198	m_io->write_byte(AVR8_IO_PORTH, data);
	2199	m_r[AVR8_REGIDX_PORTH] = data;
	2200	break;
2201	2201
2202	2202	case AVR8_REGIDX_PORTJ:
2203		m_io->write_byte(AVR8_IO_PORTJ, data);
2204		m_r[AVR8_REGIDX_PORTJ] = data;
2205		break;
	2203	m_io->write_byte(AVR8_IO_PORTJ, data);
	2204	m_r[AVR8_REGIDX_PORTJ] = data;
	2205	break;
2206	2206
2207	2207	case AVR8_REGIDX_PORTK:
2208		m_io->write_byte(AVR8_IO_PORTK, data);
2209		m_r[AVR8_REGIDX_PORTK] = data;
2210		break;
	2208	m_io->write_byte(AVR8_IO_PORTK, data);
	2209	m_r[AVR8_REGIDX_PORTK] = data;
	2210	break;
2211	2211
2212	2212	case AVR8_REGIDX_PORTL:
2213		m_io->write_byte(AVR8_IO_PORTL, data);
2214		m_r[AVR8_REGIDX_PORTL] = data;
2215		break;
	2213	m_io->write_byte(AVR8_IO_PORTL, data);
	2214	m_r[AVR8_REGIDX_PORTL] = data;
	2215	break;
2216	2216
2217	2217	case AVR8_REGIDX_DDRA:
2218	2218	case AVR8_REGIDX_DDRB:
2219	2219	case AVR8_REGIDX_DDRC:
2220	2220	case AVR8_REGIDX_DDRD:
2221	2221	case AVR8_REGIDX_SREG:
2222		case AVR8_REGIDX_RAMPZ:
	2222	case AVR8_REGIDX_RAMPZ:
2223	2223	case AVR8_REGIDX_SPH:
2224	2224	case AVR8_REGIDX_SPL:
2225	2225	m_r[offset] = data;
r29404	r29405
2287	2287	case AVR8_REGIDX_EEARH:
2288	2288	case AVR8_REGIDX_EEDR:
2289	2289	m_r[offset] = data;
2290		break;
	2290	break;
2291	2291
2292	2292	case AVR8_REGIDX_EECR:
2293	2293	m_r[offset] = data;
r29404	r29405
2297	2297	UINT16 addr = (m_r[AVR8_REGIDX_EEARH] & AVR8_EEARH_MASK) << 8;
2298	2298	addr \|= m_r[AVR8_REGIDX_EEARL];
2299	2299	m_r[AVR8_REGIDX_EEDR] = m_eeprom[addr];
2300		if (VERBOSE_LEVEL) printf("EEPROM read @ 0x%04x data = 0x%02x\n", addr, m_eeprom[addr]);
	2300	if (VERBOSE_LEVEL) printf("EEPROM read @ 0x%04x data = 0x%02x\n", addr, m_eeprom[addr]);
2301	2301	}
2302	2302	if ((data & AVR8_EECR_EEPE_MASK) && (data & AVR8_EECR_EEMPE_MASK))
2303	2303	{
2304	2304	UINT16 addr = (m_r[AVR8_REGIDX_EEARH] & AVR8_EEARH_MASK) << 8;
2305	2305	addr \|= m_r[AVR8_REGIDX_EEARL];
2306	2306	m_eeprom[addr] = m_r[AVR8_REGIDX_EEDR];
2307		if (VERBOSE_LEVEL) printf("EEPROM write @ 0x%04x data = 0x%02x ('%c')\n", addr, m_eeprom[addr], m_eeprom[addr]);
	2307	if (VERBOSE_LEVEL) printf("EEPROM write @ 0x%04x data = 0x%02x ('%c')\n", addr, m_eeprom[addr], m_eeprom[addr]);
2308	2308
2309		m_r[offset] = data & ~AVR8_EECR_EEPE_MASK; //indicates that we've finished writing a value to the EEPROM.
2310		//TODO: shouldn't this happen only after a certain dalay?
	2309	m_r[offset] = data & ~AVR8_EECR_EEPE_MASK; //indicates that we've finished writing a value to the EEPROM.
	2310	//TODO: shouldn't this happen only after a certain dalay?
2311	2311	}
2312	2312	break;
2313	2313
r29404	r29405
2338	2338	break;
2339	2339	}
2340	2340
2341		case AVR8_REGIDX_WDTCSR:
	2341	case AVR8_REGIDX_WDTCSR:
2342	2342	verboselog(m_pc, 0, "AVR8: WDTCSR = %02x\n", data );
2343		//TODO: changed_wdtcsr(data);
2344		break;
	2343	//TODO: changed_wdtcsr(data);
	2344	break;
2345	2345
2346		case AVR8_REGIDX_CLKPR:
	2346	case AVR8_REGIDX_CLKPR:
2347	2347	verboselog(m_pc, 0, "AVR8: CLKPR = %02x\n", data );
2348		//TODO: changed_clkpr(data);
2349		break;
	2348	//TODO: changed_clkpr(data);
	2349	break;
2350	2350
2351		case AVR8_REGIDX_PRR0:
	2351	case AVR8_REGIDX_PRR0:
2352	2352	verboselog(m_pc, 0, "AVR8: PRR0 = %02x\n", data );
2353		//TODO: changed_prr0(data);
2354		break;
	2353	//TODO: changed_prr0(data);
	2354	break;
2355	2355
2356		case AVR8_REGIDX_PRR1:
	2356	case AVR8_REGIDX_PRR1:
2357	2357	verboselog(m_pc, 0, "AVR8: PRR1 = %02x\n", data );
2358		//TODO: changed_prr1(data);
2359		break;
	2358	//TODO: changed_prr1(data);
	2359	break;
2360	2360
2361		case AVR8_REGIDX_OSCCAL:
	2361	case AVR8_REGIDX_OSCCAL:
2362	2362	verboselog(m_pc, 0, "AVR8: OSCCAL = %02x\n", data );
2363		//TODO: changed_osccal(data);
2364		break;
	2363	//TODO: changed_osccal(data);
	2364	break;
2365	2365
2366		case AVR8_REGIDX_PCICR:
	2366	case AVR8_REGIDX_PCICR:
2367	2367	verboselog(m_pc, 0, "AVR8: PCICR = %02x\n", data );
2368		//TODO: changed_pcicr(data);
2369		break;
	2368	//TODO: changed_pcicr(data);
	2369	break;
2370	2370
2371		case AVR8_REGIDX_EICRA:
	2371	case AVR8_REGIDX_EICRA:
2372	2372	verboselog(m_pc, 0, "AVR8: EICRA = %02x\n", data );
2373		//TODO: changed_eicra(data);
2374		break;
	2373	//TODO: changed_eicra(data);
	2374	break;
2375	2375
2376		case AVR8_REGIDX_EICRB:
	2376	case AVR8_REGIDX_EICRB:
2377	2377	verboselog(m_pc, 0, "AVR8: EICRB = %02x\n", data );
2378		//TODO: changed_eicrb(data);
2379		break;
	2378	//TODO: changed_eicrb(data);
	2379	break;
2380	2380
2381		case AVR8_REGIDX_PCMSK0:
	2381	case AVR8_REGIDX_PCMSK0:
2382	2382	verboselog(m_pc, 0, "AVR8: PCMSK0 = %02x\n", data );
2383		//TODO: changed_pcmsk0(data);
2384		break;
	2383	//TODO: changed_pcmsk0(data);
	2384	break;
2385	2385
2386		case AVR8_REGIDX_PCMSK1:
	2386	case AVR8_REGIDX_PCMSK1:
2387	2387	verboselog(m_pc, 0, "AVR8: PCMSK1 = %02x\n", data );
2388		//TODO: changed_pcmsk1(data);
2389		break;
	2388	//TODO: changed_pcmsk1(data);
	2389	break;
2390	2390
2391		case AVR8_REGIDX_PCMSK2:
	2391	case AVR8_REGIDX_PCMSK2:
2392	2392	verboselog(m_pc, 0, "AVR8: PCMSK2 = %02x\n", data );
2393		//TODO: changed_pcmsk2(data);
2394		break;
	2393	//TODO: changed_pcmsk2(data);
	2394	break;
2395	2395
2396	2396	case AVR8_REGIDX_TIMSK0:
2397	2397	verboselog(m_pc, 0, "AVR8: TIMSK0 = %02x\n", data );
r29404	r29405
2442	2442	update_interrupt(AVR8_INTIDX_TOV5);
2443	2443	break;
2444	2444
2445		case AVR8_REGIDX_XMCRA:
	2445	case AVR8_REGIDX_XMCRA:
2446	2446	verboselog(m_pc, 0, "AVR8: XMCRA = %02x\n", data );
2447		//TODO: changed_xmcra(data);
2448		break;
	2447	//TODO: changed_xmcra(data);
	2448	break;
2449	2449
2450		case AVR8_REGIDX_XMCRB:
	2450	case AVR8_REGIDX_XMCRB:
2451	2451	verboselog(m_pc, 0, "AVR8: XMCRB = %02x\n", data );
2452		//TODO: changed_xmcrb(data);
2453		break;
	2452	//TODO: changed_xmcrb(data);
	2453	break;
2454	2454
2455		case AVR8_REGIDX_ADCL:
	2455	case AVR8_REGIDX_ADCL:
2456	2456	verboselog(m_pc, 0, "AVR8: ADCL = %02x\n", data );
2457		//TODO: changed_adcl(data);
2458		break;
	2457	//TODO: changed_adcl(data);
	2458	break;
2459	2459
2460		case AVR8_REGIDX_ADCH:
	2460	case AVR8_REGIDX_ADCH:
2461	2461	verboselog(m_pc, 0, "AVR8: ADCH = %02x\n", data );
2462		//TODO: changed_adch(data);
2463		break;
	2462	//TODO: changed_adch(data);
	2463	break;
2464	2464
2465		case AVR8_REGIDX_ADCSRA:
	2465	case AVR8_REGIDX_ADCSRA:
2466	2466	verboselog(m_pc, 0, "AVR8: ADCSRA = %02x\n", data );
2467		//TODO: changed_adcsra(data);
2468		break;
	2467	//TODO: changed_adcsra(data);
	2468	break;
2469	2469
2470		case AVR8_REGIDX_ADCSRB:
	2470	case AVR8_REGIDX_ADCSRB:
2471	2471	verboselog(m_pc, 0, "AVR8: ADCSRB = %02x\n", data );
2472		//TODO: changed_adcsrb(data);
2473		break;
	2472	//TODO: changed_adcsrb(data);
	2473	break;
2474	2474
2475		case AVR8_REGIDX_ADMUX:
	2475	case AVR8_REGIDX_ADMUX:
2476	2476	verboselog(m_pc, 0, "AVR8: ADMUX = %02x\n", data );
2477		//TODO: changed_admux(data);
2478		break;
	2477	//TODO: changed_admux(data);
	2478	break;
2479	2479
2480		case AVR8_REGIDX_DIDR0:
	2480	case AVR8_REGIDX_DIDR0:
2481	2481	verboselog(m_pc, 0, "AVR8: DIDR0 = %02x\n", data );
2482		//TODO: changed_didr0(data);
2483		break;
	2482	//TODO: changed_didr0(data);
	2483	break;
2484	2484
2485		case AVR8_REGIDX_DIDR1:
	2485	case AVR8_REGIDX_DIDR1:
2486	2486	verboselog(m_pc, 0, "AVR8: DIDR1 = %02x\n", data );
2487		//TODO: changed_didr1(data);
2488		break;
	2487	//TODO: changed_didr1(data);
	2488	break;
2489	2489
2490		case AVR8_REGIDX_DIDR2:
	2490	case AVR8_REGIDX_DIDR2:
2491	2491	verboselog(m_pc, 0, "AVR8: DIDR2 = %02x\n", data );
2492		//TODO: changed_didr2(data);
2493		break;
	2492	//TODO: changed_didr2(data);
	2493	break;
2494	2494
2495	2495	case AVR8_REGIDX_TCCR1A:
2496	2496	verboselog(m_pc, 0, "AVR8: TCCR1A = %02x\n", data );
r29404	r29405
2577	2577
2578	2578	case AVR8_REGIDX_TCCR3A:
2579	2579	verboselog(m_pc, 0, "AVR8: TCCR3A = %02x\n", data );
2580		changed_tccr3a(data);
	2580	changed_tccr3a(data);
2581	2581	break;
2582	2582
2583	2583	case AVR8_REGIDX_TCCR3B:
2584	2584	verboselog(m_pc, 0, "AVR8: TCCR3B = %02x\n", data );
2585		changed_tccr3b(data);
	2585	changed_tccr3b(data);
2586	2586	break;
2587	2587
2588	2588	case AVR8_REGIDX_TCCR3C:
2589	2589	verboselog(m_pc, 0, "AVR8: TCCR3C = %02x\n", data );
2590		changed_tccr3c(data);
	2590	changed_tccr3c(data);
2591	2591	break;
2592	2592
2593	2593	case AVR8_REGIDX_TCNT3L:
r29404	r29405
2632	2632
2633	2633	case AVR8_REGIDX_TCCR4A:
2634	2634	verboselog(m_pc, 0, "AVR8: TCCR4A = %02x\n", data );
2635		changed_tccr4a(data);
	2635	changed_tccr4a(data);
2636	2636	break;
2637	2637
2638	2638	case AVR8_REGIDX_TCCR4B:
2639	2639	verboselog(m_pc, 0, "AVR8: TCCR4B = %02x\n", data );
2640		changed_tccr4b(data);
	2640	changed_tccr4b(data);
2641	2641	break;
2642	2642
2643	2643	case AVR8_REGIDX_TCCR4C:
2644	2644	verboselog(m_pc, 0, "AVR8: TCCR4C = %02x\n", data );
2645		changed_tccr4c(data);
	2645	changed_tccr4c(data);
2646	2646	break;
2647	2647
2648	2648	case AVR8_REGIDX_TCNT4L:
r29404	r29405
2687	2687
2688	2688	case AVR8_REGIDX_TCCR5A:
2689	2689	verboselog(m_pc, 0, "AVR8: TCCR5A = %02x\n", data );
2690		changed_tccr5a(data);
	2690	changed_tccr5a(data);
2691	2691	break;
2692	2692
2693	2693	case AVR8_REGIDX_TCCR5B:
2694	2694	verboselog(m_pc, 0, "AVR8: TCCR5B = %02x\n", data );
2695		changed_tccr5b(data);
	2695	changed_tccr5b(data);
2696	2696	break;
2697	2697
2698	2698	case AVR8_REGIDX_ASSR:
r29404	r29405
2723	2723	case AVR8_REGIDX_TWCR:
2724	2724	verboselog(m_pc, 0, "AVR8: TWCR = %02x\n", data );
2725	2725	//TODO: changed_twcr(data);
2726		m_r[AVR8_REGIDX_TWCR] = data;
	2726	m_r[AVR8_REGIDX_TWCR] = data;
2727	2727	break;
2728	2728
2729	2729	case AVR8_REGIDX_TWAMR:
r29404	r29405
2746	2746	//TODO: changed_ucsr0c(data);
2747	2747	break;
2748	2748	/*
2749		case AVR8_REGIDX_:
2750		verboselog(m_pc, 0, "AVR8: = %02x\n", data );
2751		//TODO: changed_(data);
2752		break;
	2749	case AVR8_REGIDX_:
	2750	verboselog(m_pc, 0, "AVR8: = %02x\n", data );
	2751	//TODO: changed_(data);
	2752	break;
2753	2753	*/
2754	2754	default:
2755	2755	verboselog(m_pc, 0, "AVR8: Unknown Register Write: %03x = %02x\n", offset, data);
r29404	r29405
2759	2759
2760	2760	READ8_MEMBER( avr8_device::regs_r )
2761	2761	{
2762		// printf("--- READ offset %04x ---\n", offset);
	2762	// printf("--- READ offset %04x ---\n", offset);
2763	2763
2764	2764	switch( offset )
2765	2765	{
r29404	r29405
2798	2798	return m_r[offset];
2799	2799
2800	2800	case AVR8_REGIDX_PINA:
2801		// TODO: consider the DDRA
2802		return m_io->read_byte(AVR8_REG_A);
	2801	// TODO: consider the DDRA
	2802	return m_io->read_byte(AVR8_REG_A);
2803	2803
2804	2804	case AVR8_REGIDX_PINB:
2805		// TODO: consider the DDRB
2806		return m_io->read_byte(AVR8_REG_B);
	2805	// TODO: consider the DDRB
	2806	return m_io->read_byte(AVR8_REG_B);
2807	2807
2808	2808	case AVR8_REGIDX_PINC:
2809		// TODO: consider the DDRC
2810		return m_io->read_byte(AVR8_REG_C);
	2809	// TODO: consider the DDRC
	2810	return m_io->read_byte(AVR8_REG_C);
2811	2811
2812	2812	case AVR8_REGIDX_PIND:
2813		// TODO: consider the DDRD
2814		return m_io->read_byte(AVR8_REG_D);
	2813	// TODO: consider the DDRD
	2814	return m_io->read_byte(AVR8_REG_D);
2815	2815
2816	2816	case AVR8_REGIDX_PINE:
2817		// TODO: consider the DDRE
2818		return m_io->read_byte(AVR8_REG_E);
	2817	// TODO: consider the DDRE
	2818	return m_io->read_byte(AVR8_REG_E);
2819	2819
2820	2820	case AVR8_REGIDX_PINF:
2821		// TODO: consider the DDRF
2822		return m_io->read_byte(AVR8_REG_F);
	2821	// TODO: consider the DDRF
	2822	return m_io->read_byte(AVR8_REG_F);
2823	2823
2824	2824	case AVR8_REGIDX_PING:
2825		// TODO: consider the DDRG
2826		return m_io->read_byte(AVR8_REG_G);
	2825	// TODO: consider the DDRG
	2826	return m_io->read_byte(AVR8_REG_G);
2827	2827
2828	2828	case AVR8_REGIDX_PINH:
2829		// TODO: consider the DDRH
2830		return m_io->read_byte(AVR8_REG_H);
	2829	// TODO: consider the DDRH
	2830	return m_io->read_byte(AVR8_REG_H);
2831	2831
2832	2832	case AVR8_REGIDX_PINJ:
2833		// TODO: consider the DDRJ
2834		return m_io->read_byte(AVR8_REG_J);
	2833	// TODO: consider the DDRJ
	2834	return m_io->read_byte(AVR8_REG_J);
2835	2835
2836	2836	case AVR8_REGIDX_PINK:
2837		// TODO: consider the DDRK
2838		return m_io->read_byte(AVR8_REG_K);
	2837	// TODO: consider the DDRK
	2838	return m_io->read_byte(AVR8_REG_K);
2839	2839
2840	2840	case AVR8_REGIDX_PINL:
2841		// TODO: consider the DDRL
2842		return m_io->read_byte(AVR8_REG_L);
	2841	// TODO: consider the DDRL
	2842	return m_io->read_byte(AVR8_REG_L);
2843	2843
2844	2844	case AVR8_REGIDX_PORTA:
2845	2845	case AVR8_REGIDX_PORTB:
r29404	r29405
2868	2868	return m_r[offset];
2869	2869
2870	2870	// EEPROM registers:
2871		case AVR8_REGIDX_EECR:
	2871	case AVR8_REGIDX_EECR:
2872	2872	case AVR8_REGIDX_EEDR:
2873	2873	return m_r[offset];
2874	2874
r29404	r29405
2878	2878	case AVR8_REGIDX_GPIOR0:
2879	2879	case AVR8_REGIDX_GPIOR1:
2880	2880	case AVR8_REGIDX_GPIOR2:
2881		// case AVR8_REGIDX_UCSR0B:/TODO: needed for Replicator 1 /
	2881	// case AVR8_REGIDX_UCSR0B:/TODO: needed for Replicator 1 /
2882	2882	case AVR8_REGIDX_SPDR: /TODO: needed for Replicator 1 /
2883	2883	case AVR8_REGIDX_SPSR: /TODO: needed for Replicator 1 /
2884	2884	// case AVR8_REGIDX_ADCSRA: /TODO: needed for Replicator 1 /
r29404	r29405
2886	2886	case AVR8_REGIDX_SPL:
2887	2887	case AVR8_REGIDX_SPH:
2888	2888	case AVR8_REGIDX_SREG:
2889		case AVR8_REGIDX_TIMSK0:
2890		case AVR8_REGIDX_TIMSK1:
2891		case AVR8_REGIDX_TIMSK2:
	2889	case AVR8_REGIDX_TIMSK0:
	2890	case AVR8_REGIDX_TIMSK1:
	2891	case AVR8_REGIDX_TIMSK2:
2892	2892	// case AVR8_REGIDX_TIMSK3: /TODO: needed for Replicator 1 /
2893		case AVR8_REGIDX_TIMSK4:
2894		case AVR8_REGIDX_TIMSK5:
	2893	case AVR8_REGIDX_TIMSK4:
	2894	case AVR8_REGIDX_TIMSK5:
2895	2895	return m_r[offset];
2896	2896
2897	2897	/* Two-wire registers: */
2898	2898	case AVR8_REGIDX_TWCR:
2899		/*TODO: needed for Replicator 1
2900		BLOQUEIA PROGRESSO DA EXECUÇÃO DO FIRMWARE no endereço 105EC*/
	2899	/*TODO: needed for Replicator 1
	2900	BLOQUEIA PROGRESSO DA EXECU??O DO FIRMWARE no endere?o 105EC*/
2901	2901	return m_r[offset];
2902	2902
2903	2903	case AVR8_REGIDX_TWSR:
2904		//quick hack: by returning a value != 0x08 we induce an error state that makes the object code jump out of the wait loop and continue execution failing the 2-wire write operation.
2905		//TODO: implement-me!
	2904	//quick hack: by returning a value != 0x08 we induce an error state that makes the object code jump out of the wait loop and continue execution failing the 2-wire write operation.
	2905	//TODO: implement-me!
2906	2906	return 0x00; /TODO: needed for Replicator 1 /
2907	2907
2908	2908
r29404	r29405
3309	3309	break;
3310	3310	case 0x0007: // ELPM Rd,Z+
3311	3311	pd32 = (m_r[AVR8_REGIDX_RAMPZ] << 16) \| ZREG;
3312		m_r[RD5(op)] = m_program->read_byte(pd32);
3313		pd32++;
3314		m_r[AVR8_REGIDX_RAMPZ] = (pd32 >> 16) & 0x00ff;
3315		m_r[31] = (pd32 >> 8) & 0x00ff;
	3312	m_r[RD5(op)] = m_program->read_byte(pd32);
	3313	pd32++;
	3314	m_r[AVR8_REGIDX_RAMPZ] = (pd32 >> 16) & 0x00ff;
	3315	m_r[31] = (pd32 >> 8) & 0x00ff;
3316	3316	m_r[30] = pd32 & 0x00ff;
3317		opcycles = 3;
	3317	opcycles = 3;
3318	3318	break;
3319	3319	case 0x0009: // LD Rd,Y+
3320	3320	pd = YREG;
r29404	r29405
3323	3323	m_r[29] = (pd >> 8) & 0x00ff;
3324	3324	m_r[28] = pd & 0x00ff;
3325	3325	opcycles = 2;
3326		break;
	3326	break;
3327	3327	case 0x000a: // LD Rd,-Y
3328	3328	pd = YREG;
3329	3329	pd--;
r29404	r29405
3679	3679	case 0x00a0: // WDR
3680	3680	//output += sprintf( output, "WDR" );
3681	3681	//unimplemented_opcode(op); //TODO: necessary for emulating the Replicator 1
3682		//printf("Watchdot Reset!\n");
	3682	//printf("Watchdot Reset!\n");
3683	3683	opcycles = 1;
3684	3684	break;
3685	3685	case 0x00c0: // LPM

trunk/src/emu/cpu/avr8/avr8.h
r29404	r29405
90	90	// inline configuration helpers
91	91	static void static_set_config(device_t &device, const avr8_config &config);
92	92
93		// fuse configs
	93	// fuse configs
94	94	void set_low_fuses(UINT8 byte);
95	95	void set_high_fuses(UINT8 byte);
96	96	void set_extended_fuses(UINT8 byte);
r29404	r29405
147	147	const address_space_config m_io_config;
148	148	UINT8 *m_eeprom;
149	149
150		// bootloader
	150	// bootloader
151	151	UINT16 m_boot_size;
152	152	UINT8 m_cpu_type;
153	153
154		// Fuses
155		UINT8 m_lfuses;
156		UINT8 m_hfuses;
157		UINT8 m_efuses;
158		UINT8 m_lock_bits;
	154	// Fuses
	155	UINT8 m_lfuses;
	156	UINT8 m_hfuses;
	157	UINT8 m_efuses;
	158	UINT8 m_lock_bits;
159	159
160	160	// CPU registers
161	161	UINT32 m_pc;
r29404	r29405
241	241	void changed_tccr3a(UINT8 data);
242	242	void changed_tccr3b(UINT8 data);
243	243	void changed_tccr3c(UINT8 data);
244		// void update_ocr3(UINT8 newval, UINT8 reg);
245		// void timer3_force_output_compare(int reg);
	244	// void update_ocr3(UINT8 newval, UINT8 reg);
	245	// void timer3_force_output_compare(int reg);
246	246
247	247	// timer 4
248	248	void timer4_tick();
r29404	r29405
256	256	void timer5_tick();
257	257	void changed_tccr5a(UINT8 data);
258	258	void changed_tccr5b(UINT8 data);
259		// void update_ocr5(UINT8 newval, UINT8 reg);
260		// void timer5_force_output_compare(int reg);
	259	// void update_ocr5(UINT8 newval, UINT8 reg);
	260	// void timer5_force_output_compare(int reg);
261	261
262	262	// address spaces
263	263	address_space *m_program;
r29404	r29405
496	496	AVR8_REGIDX_TCNT0,
497	497	AVR8_REGIDX_OCR0A,
498	498	AVR8_REGIDX_OCR0B,
499		//0x49: Reserved
	499	//0x49: Reserved
500	500	AVR8_REGIDX_GPIOR1 = 0x4A,
501	501	AVR8_REGIDX_GPIOR2,
502	502	AVR8_REGIDX_SPCR,
503	503	AVR8_REGIDX_SPSR,
504	504	AVR8_REGIDX_SPDR,
505		//0x4F: Reserved
	505	//0x4F: Reserved
506	506	AVR8_REGIDX_ACSR = 0x50,
507	507	AVR8_REGIDX_OCDR,
508		//0x52: Reserved
	508	//0x52: Reserved
509	509	AVR8_REGIDX_SMCR = 0x53,
510	510	AVR8_REGIDX_MCUSR,
511	511	AVR8_REGIDX_MCUCR,
512		//0x56: Reserved
	512	//0x56: Reserved
513	513	AVR8_REGIDX_SPMCSR = 0x57,
514		//0x58: Reserved
515		//0x59: Reserved
516		//0x5A: Reserved
	514	//0x58: Reserved
	515	//0x59: Reserved
	516	//0x5A: Reserved
517	517	AVR8_REGIDX_RAMPZ = 0x5B,
518	518	AVR8_REGIDX_EIND,
519	519	AVR8_REGIDX_SPL,
r29404	r29405
522	522	//--------------------------
523	523	AVR8_REGIDX_WDTCSR = 0x60,
524	524	AVR8_REGIDX_CLKPR,
525		//0x62: Reserved
526		//0x63: Reserved
	525	//0x62: Reserved
	526	//0x63: Reserved
527	527	AVR8_REGIDX_PRR0 = 0x64,
528	528	AVR8_REGIDX_PRR1,
529	529	AVR8_REGIDX_OSCCAL,
530		//0x67: Reserved
	530	//0x67: Reserved
531	531	AVR8_REGIDX_PCICR = 0x68,
532	532	AVR8_REGIDX_EICRA,
533	533	AVR8_REGIDX_EICRB,
r29404	r29405
542	542	AVR8_REGIDX_TIMSK5,
543	543	AVR8_REGIDX_XMCRA,
544	544	AVR8_REGIDX_XMCRB,
545		//0x76: Reserved
546		//0x77: Reserved
	545	//0x76: Reserved
	546	//0x77: Reserved
547	547	AVR8_REGIDX_ADCL = 0x78,
548	548	AVR8_REGIDX_ADCH,
549	549	AVR8_REGIDX_ADCSRA,
r29404	r29405
555	555	AVR8_REGIDX_TCCR1A,
556	556	AVR8_REGIDX_TCCR1B,
557	557	AVR8_REGIDX_TCCR1C,
558		//0x83: Reserved
	558	//0x83: Reserved
559	559	AVR8_REGIDX_TCNT1L = 0x84,
560	560	AVR8_REGIDX_TCNT1H,
561	561	AVR8_REGIDX_ICR1L,
r29404	r29405
566	566	AVR8_REGIDX_OCR1BH,
567	567	AVR8_REGIDX_OCR1CL,
568	568	AVR8_REGIDX_OCR1CH,
569		//0x8E: Reserved
570		//0x8F: Reserved
	569	//0x8E: Reserved
	570	//0x8F: Reserved
571	571	AVR8_REGIDX_TCCR3A = 0x90,
572	572	AVR8_REGIDX_TCCR3B,
573	573	AVR8_REGIDX_TCCR3C,
574		//0x93: Reserved
	574	//0x93: Reserved
575	575	AVR8_REGIDX_TCNT3L = 0x94,
576	576	AVR8_REGIDX_TCNT3H,
577	577	AVR8_REGIDX_ICR3L,
r29404	r29405
582	582	AVR8_REGIDX_OCR3BH,
583	583	AVR8_REGIDX_OCR3CL,
584	584	AVR8_REGIDX_OCR3CH,
585		//0x9E: Reserved
586		//0x9F: Reserved
	585	//0x9E: Reserved
	586	//0x9F: Reserved
587	587	AVR8_REGIDX_TCCR4A = 0xA0,
588	588	AVR8_REGIDX_TCCR4B,
589	589	AVR8_REGIDX_TCCR4C,
590		//0xA3: Reserved
	590	//0xA3: Reserved
591	591	AVR8_REGIDX_TCNT4L = 0xA4,
592	592	AVR8_REGIDX_TCNT4H,
593	593	AVR8_REGIDX_ICR4L,
r29404	r29405
598	598	AVR8_REGIDX_OCR4BH,
599	599	AVR8_REGIDX_OCR4CL,
600	600	AVR8_REGIDX_OCR4CH,
601		//0xAE: Reserved
602		//0xAF: Reserved
	601	//0xAE: Reserved
	602	//0xAF: Reserved
603	603	AVR8_REGIDX_TCCR2A = 0xB0,
604	604	AVR8_REGIDX_TCCR2B,
605	605	AVR8_REGIDX_TCNT2,
606	606	AVR8_REGIDX_OCR2A,
607	607	AVR8_REGIDX_OCR2B,
608		//0xB5: Reserved
	608	//0xB5: Reserved
609	609	AVR8_REGIDX_ASSR = 0xB6,
610		//0xB7: Reserved
	610	//0xB7: Reserved
611	611	AVR8_REGIDX_TWBR = 0xB8,
612	612	AVR8_REGIDX_TWSR,
613	613	AVR8_REGIDX_TWAR,
614	614	AVR8_REGIDX_TWDR,
615	615	AVR8_REGIDX_TWCR,
616	616	AVR8_REGIDX_TWAMR,
617		//0xBE: Reserved
618		//0xBF: Reserved
	617	//0xBE: Reserved
	618	//0xBF: Reserved
619	619	AVR8_REGIDX_UCSR0A = 0xC0,
620	620	AVR8_REGIDX_UCSR0B,
621	621	AVR8_REGIDX_UCSR0C,
622		//0xC3: Reserved
	622	//0xC3: Reserved
623	623	AVR8_REGIDX_UBRR0L = 0xC4,
624	624	AVR8_REGIDX_UBRR0H,
625	625	AVR8_REGIDX_UDR0,
626		//0xC7: Reserved
	626	//0xC7: Reserved
627	627	AVR8_REGIDX_UCSR1A = 0xC8,
628	628	AVR8_REGIDX_UCSR1B,
629	629	AVR8_REGIDX_UCSR1C,
630		//0xCB: Reserved
	630	//0xCB: Reserved
631	631	AVR8_REGIDX_UBRR1L = 0xCC,
632	632	AVR8_REGIDX_UBRR1H,
633	633	AVR8_REGIDX_UDR1,
634		//0xCF: Reserved
	634	//0xCF: Reserved
635	635	AVR8_REGIDX_UCSR2A = 0xD0,
636	636	AVR8_REGIDX_UCSR2B,
637	637	AVR8_REGIDX_UCSR2C,
638		//0xD3: Reserved
	638	//0xD3: Reserved
639	639	AVR8_REGIDX_UBRR2L = 0xD4,
640	640	AVR8_REGIDX_UBRR2H,
641	641	AVR8_REGIDX_UDR2,
642		//0xD7: Reserved
643		//0xD8: Reserved
644		//0xD9: Reserved
645		//0xDA: Reserved
646		//0xDB: Reserved
647		//0xDC: Reserved
648		//0xDD: Reserved
649		//0xDE: Reserved
650		//0xDF: Reserved
651		//0xE0: Reserved
652		//0xE1: Reserved
653		//0xE2: Reserved
654		//0xE3: Reserved
655		//0xE4: Reserved
656		//0xE5: Reserved
657		//0xE6: Reserved
658		//0xE7: Reserved
659		//0xE8: Reserved
660		//0xE9: Reserved
661		//0xEA: Reserved
662		//0xEB: Reserved
663		//0xEC: Reserved
664		//0xED: Reserved
665		//0xEE: Reserved
666		//0xEF: Reserved
667		//0xF0: Reserved
668		//0xF1: Reserved
669		//0xF2: Reserved
670		//0xF3: Reserved
671		//0xF4: Reserved
672		//0xF5: Reserved
673		//0xF6: Reserved
674		//0xF7: Reserved
675		//0xF8: Reserved
676		//0xF9: Reserved
677		//0xFA: Reserved
678		//0xFB: Reserved
679		//0xFC: Reserved
680		//0xFD: Reserved
681		//0xFE: Reserved
682		//0xFF: Reserved
	642	//0xD7: Reserved
	643	//0xD8: Reserved
	644	//0xD9: Reserved
	645	//0xDA: Reserved
	646	//0xDB: Reserved
	647	//0xDC: Reserved
	648	//0xDD: Reserved
	649	//0xDE: Reserved
	650	//0xDF: Reserved
	651	//0xE0: Reserved
	652	//0xE1: Reserved
	653	//0xE2: Reserved
	654	//0xE3: Reserved
	655	//0xE4: Reserved
	656	//0xE5: Reserved
	657	//0xE6: Reserved
	658	//0xE7: Reserved
	659	//0xE8: Reserved
	660	//0xE9: Reserved
	661	//0xEA: Reserved
	662	//0xEB: Reserved
	663	//0xEC: Reserved
	664	//0xED: Reserved
	665	//0xEE: Reserved
	666	//0xEF: Reserved
	667	//0xF0: Reserved
	668	//0xF1: Reserved
	669	//0xF2: Reserved
	670	//0xF3: Reserved
	671	//0xF4: Reserved
	672	//0xF5: Reserved
	673	//0xF6: Reserved
	674	//0xF7: Reserved
	675	//0xF8: Reserved
	676	//0xF9: Reserved
	677	//0xFA: Reserved
	678	//0xFB: Reserved
	679	//0xFC: Reserved
	680	//0xFD: Reserved
	681	//0xFE: Reserved
	682	//0xFF: Reserved
683	683	AVR8_REGIDX_PINH = 0x100,
684	684	AVR8_REGIDX_DDRH,
685	685	AVR8_REGIDX_PORTH,
r29404	r29405
692	692	AVR8_REGIDX_PINL,
693	693	AVR8_REGIDX_DDRL,
694	694	AVR8_REGIDX_PORTL,
695		//0x10C: Reserved
696		//0x10D: Reserved
697		//0x10E: Reserved
698		//0x10F: Reserved
699		//0x110: Reserved
700		//0x111: Reserved
701		//0x112: Reserved
702		//0x113: Reserved
703		//0x114: Reserved
704		//0x115: Reserved
705		//0x116: Reserved
706		//0x117: Reserved
707		//0x118: Reserved
708		//0x119: Reserved
709		//0x11A: Reserved
710		//0x11B: Reserved
711		//0x11C: Reserved
712		//0x11D: Reserved
713		//0x11E: Reserved
714		//0x11F: Reserved
	695	//0x10C: Reserved
	696	//0x10D: Reserved
	697	//0x10E: Reserved
	698	//0x10F: Reserved
	699	//0x110: Reserved
	700	//0x111: Reserved
	701	//0x112: Reserved
	702	//0x113: Reserved
	703	//0x114: Reserved
	704	//0x115: Reserved
	705	//0x116: Reserved
	706	//0x117: Reserved
	707	//0x118: Reserved
	708	//0x119: Reserved
	709	//0x11A: Reserved
	710	//0x11B: Reserved
	711	//0x11C: Reserved
	712	//0x11D: Reserved
	713	//0x11E: Reserved
	714	//0x11F: Reserved
715	715	AVR8_REGIDX_TCCR5A,
716	716	AVR8_REGIDX_TCCR5B,
717	717	AVR8_REGIDX_TCCR5C,
718		//0x123: Reserved
	718	//0x123: Reserved
719	719	AVR8_REGIDX_TCNT5L,
720	720	AVR8_REGIDX_TCNT5H,
721	721	AVR8_REGIDX_ICR5L,
r29404	r29405
726	726	AVR8_REGIDX_OCR5BH,
727	727	AVR8_REGIDX_OCR5CL,
728	728	AVR8_REGIDX_OCR5CH,
729		//0x12E: Reserved
730		//0x12F: Reserved
	729	//0x12E: Reserved
	730	//0x12F: Reserved
731	731	AVR8_REGIDX_UCSR3A,
732	732	AVR8_REGIDX_UCSR3B,
733	733	AVR8_REGIDX_UCSR3C,
734		//0x133: Reserved
	734	//0x133: Reserved
735	735	AVR8_REGIDX_UBRR3L,
736	736	AVR8_REGIDX_UBRR3H,
737	737	AVR8_REGIDX_UDR3,
738		//0x137: Reserved
739		// .
740		// . up to
741		// .
742		//0x1FF: Reserved
	738	//0x137: Reserved
	739	// .
	740	// . up to
	741	// .
	742	//0x1FF: Reserved
743	743	};
744	744
745	745	enum {
746		AVR8_IO_PORTA = 0,
747		AVR8_IO_PORTB,
748		AVR8_IO_PORTC,
749		AVR8_IO_PORTD,
750		AVR8_IO_PORTE,
751		AVR8_IO_PORTF,
752		AVR8_IO_PORTG,
753		AVR8_IO_PORTH,
754		AVR8_IO_PORTJ,
755		AVR8_IO_PORTK,
756		AVR8_IO_PORTL
	746	AVR8_IO_PORTA = 0,
	747	AVR8_IO_PORTB,
	748	AVR8_IO_PORTC,
	749	AVR8_IO_PORTD,
	750	AVR8_IO_PORTE,
	751	AVR8_IO_PORTF,
	752	AVR8_IO_PORTG,
	753	AVR8_IO_PORTH,
	754	AVR8_IO_PORTJ,
	755	AVR8_IO_PORTK,
	756	AVR8_IO_PORTL
757	757	};
758	758
759	759	//TODO: AVR8_REG_* and AVR8_IO_PORT* seem to serve the same purpose and thus should be unified. Verify this!
r29404	r29405
810	810	//lock bit masks
811	811	enum
812	812	{
813		LB1 = (1 << 0),
814		LB2 = (1 << 1),
815		BLB01 = (1 << 2),
816		BLB02 = (1 << 3),
817		BLB11 = (1 << 4),
818		BLB12 = (1 << 5),
	813	LB1 = (1 << 0),
	814	LB2 = (1 << 1),
	815	BLB01 = (1 << 2),
	816	BLB02 = (1 << 3),
	817	BLB11 = (1 << 4),
	818	BLB12 = (1 << 5),
819	819	};
820	820
821	821	//extended fuses bit masks
822	822	enum
823	823	{
824		BODLEVEL0 = (1 << 0),
825		BODLEVEL1 = (1 << 1),
826		BODLEVEL2 = (1 << 2),
	824	BODLEVEL0 = (1 << 0),
	825	BODLEVEL1 = (1 << 1),
	826	BODLEVEL2 = (1 << 2),
827	827	};
828	828
829	829	//high fuses bit masks
830	830	enum
831	831	{
832		BOOTRST = (1 << 0),
833		BOOTSZ0 = (1 << 1),
834		BOOTSZ1 = (1 << 2),
835		EESAVE = (1 << 3),
836		WDTON = (1 << 4),
837		SPIEN = (1 << 5),
838		JTAGEN = (1 << 6),
839		OCDEN = (1 << 7),
	832	BOOTRST = (1 << 0),
	833	BOOTSZ0 = (1 << 1),
	834	BOOTSZ1 = (1 << 2),
	835	EESAVE = (1 << 3),
	836	WDTON = (1 << 4),
	837	SPIEN = (1 << 5),
	838	JTAGEN = (1 << 6),
	839	OCDEN = (1 << 7),
840	840	};
841	841
842	842	//low fuses bit masks
843	843	enum
844	844	{
845		CKSEL0 = (1 << 0),
846		CKSEL1 = (1 << 1),
847		CKSEL2 = (1 << 2),
848		CKSEL3 = (1 << 3),
849		SUT0 = (1 << 4),
850		SUT1 = (1 << 5),
851		CKOUT = (1 << 6),
852		CKDIV8 = (1 << 7),
	845	CKSEL0 = (1 << 0),
	846	CKSEL1 = (1 << 1),
	847	CKSEL2 = (1 << 2),
	848	CKSEL3 = (1 << 3),
	849	SUT0 = (1 << 4),
	850	SUT1 = (1 << 5),
	851	CKOUT = (1 << 6),
	852	CKDIV8 = (1 << 7),
853	853	};
854	854
855	855	#define AVR8_EEARH_MASK 0x01

trunk/src/emu/cpu/avr8/avr8dasm.c
r29404	r29405
30	30	UINT32 op = oprom[pos++];
31	31	op \|= oprom[pos++] << 8;
32	32	UINT32 addr = 0;
33		const char* register_names[0x40] = {"PINA", "DDRA", "PORTA", "PINB", "DDRB", "PORTB", "PINC", "DDRC", "PORTC", "PIND", "DDRD", "PORTD", "PINE", "DDRE", "PORTE", "PINF", "DDRF", "PORTF", "PING", "DDRG", "PORTG", "TIFR0", "TIFR1", "TIFR2","TIFR3", "TIFR4", "TIFR5", "PCIFR", "EIFR", "EIMSK", "GPIOR0", "EECR", "EEDR", "EEARL", "EEARH", "GTCCR", "TCCR0A", "TCCR0B", "TCNT0", "OCR0A", "OCR0B", "0x29", "GPIOR1", "GPIOR2", "SPCR", "SPSR", "SPDR", "0x2F", "ACSR", "OCDR", "0x32", "SMCR", "MCUSR", "MCUCR", "0x36", "SPMCSR", "0x38", "0x39", "0x3A", "RAMPZ", "EIND", "SPL", "SPH", "SREG"};
	33	const char* register_names[0x40] = {"PINA", "DDRA", "PORTA", "PINB", "DDRB", "PORTB", "PINC", "DDRC", "PORTC", "PIND", "DDRD", "PORTD", "PINE", "DDRE", "PORTE", "PINF", "DDRF", "PORTF", "PING", "DDRG", "PORTG", "TIFR0", "TIFR1", "TIFR2","TIFR3", "TIFR4", "TIFR5", "PCIFR", "EIFR", "EIMSK", "GPIOR0", "EECR", "EEDR", "EEARL", "EEARH", "GTCCR", "TCCR0A", "TCCR0B", "TCNT0", "OCR0A", "OCR0B", "0x29", "GPIOR1", "GPIOR2", "SPCR", "SPSR", "SPDR", "0x2F", "ACSR", "OCDR", "0x32", "SMCR", "MCUSR", "MCUCR", "0x36", "SPMCSR", "0x38", "0x39", "0x3A", "RAMPZ", "EIND", "SPL", "SPH", "SREG"};
34	34
35		const char* register_bit_names[0x40][8] = {
36		/* PINA */ { "0", "1", "2", "3", "4", "5", "6", "7"},
37		/* DDRA */ { "0", "1", "2", "3", "4", "5", "6", "7"},
38		/* PORTA */ { "0", "1", "2", "3", "4", "5", "6", "7"},
39		/* PINB */ { "0", "1", "2", "3", "4", "5", "6", "7"},
40		/* DDRB */ { "0", "1", "2", "3", "4", "5", "6", "7"},
41		/* PORTB */ { "0", "1", "2", "3", "4", "5", "6", "7"},
42		/* PINC */ { "0", "1", "2", "3", "4", "5", "6", "7"},
43		/* DDRC */ { "0", "1", "2", "3", "4", "5", "6", "7"},
44		/* PORTC */ { "0", "1", "2", "3", "4", "5", "6", "7"},
45		/* PIND */ { "0", "1", "2", "3", "4", "5", "6", "7"},
46		/* DDRD */ { "0", "1", "2", "3", "4", "5", "6", "7"},
47		/* PORTD */ { "0", "1", "2", "3", "4", "5", "6", "7"},
48		/* PINE */ { "0", "1", "2", "3", "4", "5", "6", "7"},
49		/* DDRE */ { "0", "1", "2", "3", "4", "5", "6", "7"},
50		/* PORTE */ { "0", "1", "2", "3", "4", "5", "6", "7"},
51		/* PINF */ { "0", "1", "2", "3", "4", "5", "6", "7"},
52		/* DDRF */ { "0", "1", "2", "3", "4", "5", "6", "7"},
53		/* PORTF */ { "0", "1", "2", "3", "4", "5", "6", "7"},
54		/* PING */ { "0", "1", "2", "3", "4", "5", "6", "7"},
55		/* DDRG */ { "0", "1", "2", "3", "4", "5", "6", "7"},
56		/* PORTG */ { "0", "1", "2", "3", "4", "5", "6", "7"},
57		/* TIFR0 */ { "TOV0", "OCF0A", "OCF0B", "3", "4", "5", "6", "7"},
58		/* TIFR1 */ { "TOV1", "OCF1A", "OCF1B", "OCF1C", "4", "ICF1", "6", "7"},
59		/* TIFR2 */ { "TOV2", "OCF2A", "OCF2B", "3", "4", "5", "6", "7"},
60		/* TIFR3 */ { "TOV3", "OCF3A", "OCF3B", "OCF3C", "4", "ICF3", "6", "7"},
61		/* TIFR4 */ { "TOV4", "OCF4A", "OCF4B", "OCF4C", "4", "ICF4", "6", "7"},
62		/* TIFR5 */ { "TOV5", "OCF5A", "OCF5B", "OCF5C", "4", "ICF5", "6", "7"},
63		/* PCIFR */ {"PCIF0", "PCIF1", "PCIF2", "3", "4", "5", "6", "7"},
64		/* EIFR */ {"INTF0", "INTF1", "INTF2", "INTF3", "INTF4", "INTF5", "INTF6", "INTF7"},
65		/* EIMSK */ { "INT0", "INT1", "INT2", "INT3", "INT4", "INT5", "INT6", "INT7"},
66		/* GPIOR0 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
67		/* EECR */ { "EERE", "EEPE", "EEMPE", "EERIE", "EEPM0", "EEPM1", "6", "7"},
68		/* EEDR */ { "0", "1", "2", "3", "4", "5", "6", "7"},
69		/* EEARL */ { "0", "1", "2", "3", "4", "5", "6", "7"},
70		/* EEARH */ { "0", "1", "2", "3", "4", "5", "6", "7"},
71		/* GTCCR */ {"PSRSYNC", "PSRASY", "2", "3", "4", "5", "6", "TSM"},
72		/* TCCR0A */ {"WGM00", "WGM01", "2", "3","COM0B0","COM0B1","COM0A0","COM0A1"},
73		/* TCCR0B */ { "CS0", "CS1", "CS2", "WGM02", "4", "5", "FOC0B", "FOC0A"},
74		/* TCNT0 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
75		/* OCR0A */ { "0", "1", "2", "3", "4", "5", "6", "7"},
76		/* OCR0B */ { "0", "1", "2", "3", "4", "5", "6", "7"},
77		/* 0x29 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
78		/* GPIOR1 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
79		/* GPIOR2 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
80		/* SPCR */ { "SPR0", "SPR1", "CPHA", "CPOL", "MSTR", "DORD", "SPE", "SPIE"},
81		/* SPSR */ {"SPI2X", "1", "2", "3", "4", "5", "WCOL", "SPIF"},
82		/* SPDR */ { "0", "1", "2", "3", "4", "5", "6", "7"},
83		/* 0x2F */ { "0", "1", "2", "3", "4", "5", "6", "7"},
84		/* ACSR */ {"ACIS0", "ACIS1", "ACIC", "ACIE", "ACI", "ACO", "ACBG", "ACD"},
85		/* OCDR */ { "0", "1", "2", "3", "4", "5", "6", "7"},
86		/* 0x32 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
87		/* SMCR */ { "SE", "SM0", "SM1", "SM2", "4", "5", "6", "7"},
88		/* MCUSR */ { "PORF", "EXTRF", "BORF", "WDRF", "JTRF", "5", "6", "7"},
89		/* MCUCR */ { "IVCE", "IVSEL", "2", "3", "PUD", "5", "6", "JTD"},
90		/* 0x36 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
91		/* SPMCSR */ {"SPMEN", "PGERS", "PGWRT","BLBSET","RWWSRE", "SIGRD", "RWWSB", "SPMIE"},
92		/* 0x38 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
93		/* 0x39 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
94		/* 0x3A */ { "0", "1", "2", "3", "4", "5", "6", "7"},
95		/* RAMPZ */ {"RAMPZ0","RAMPZ1", "2", "3", "4", "5", "6", "7"},
96		/* EIND */ {"EIND0", "1", "2", "3", "4", "5", "6", "7"},
97		/* SPL */ { "SP0", "SP1", "SP2", "SP3", "SP4", "SP5", "SP6", "SP7"},
98		/* SPH */ { "SP8", "SP9", "SP10", "SP11", "SP12", "SP13", "SP14", "SP15"},
99		/* SREG */ { "C", "Z", "N", "V", "S", "H", "T", "I"}};
	35	const char* register_bit_names[0x40][8] = {
	36	/* PINA */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	37	/* DDRA */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	38	/* PORTA */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	39	/* PINB */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	40	/* DDRB */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	41	/* PORTB */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	42	/* PINC */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	43	/* DDRC */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	44	/* PORTC */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	45	/* PIND */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	46	/* DDRD */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	47	/* PORTD */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	48	/* PINE */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	49	/* DDRE */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	50	/* PORTE */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	51	/* PINF */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	52	/* DDRF */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	53	/* PORTF */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	54	/* PING */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	55	/* DDRG */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	56	/* PORTG */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	57	/* TIFR0 */ { "TOV0", "OCF0A", "OCF0B", "3", "4", "5", "6", "7"},
	58	/* TIFR1 */ { "TOV1", "OCF1A", "OCF1B", "OCF1C", "4", "ICF1", "6", "7"},
	59	/* TIFR2 */ { "TOV2", "OCF2A", "OCF2B", "3", "4", "5", "6", "7"},
	60	/* TIFR3 */ { "TOV3", "OCF3A", "OCF3B", "OCF3C", "4", "ICF3", "6", "7"},
	61	/* TIFR4 */ { "TOV4", "OCF4A", "OCF4B", "OCF4C", "4", "ICF4", "6", "7"},
	62	/* TIFR5 */ { "TOV5", "OCF5A", "OCF5B", "OCF5C", "4", "ICF5", "6", "7"},
	63	/* PCIFR */ {"PCIF0", "PCIF1", "PCIF2", "3", "4", "5", "6", "7"},
	64	/* EIFR */ {"INTF0", "INTF1", "INTF2", "INTF3", "INTF4", "INTF5", "INTF6", "INTF7"},
	65	/* EIMSK */ { "INT0", "INT1", "INT2", "INT3", "INT4", "INT5", "INT6", "INT7"},
	66	/* GPIOR0 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	67	/* EECR */ { "EERE", "EEPE", "EEMPE", "EERIE", "EEPM0", "EEPM1", "6", "7"},
	68	/* EEDR */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	69	/* EEARL */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	70	/* EEARH */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	71	/* GTCCR */ {"PSRSYNC", "PSRASY", "2", "3", "4", "5", "6", "TSM"},
	72	/* TCCR0A */ {"WGM00", "WGM01", "2", "3","COM0B0","COM0B1","COM0A0","COM0A1"},
	73	/* TCCR0B */ { "CS0", "CS1", "CS2", "WGM02", "4", "5", "FOC0B", "FOC0A"},
	74	/* TCNT0 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	75	/* OCR0A */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	76	/* OCR0B */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	77	/* 0x29 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	78	/* GPIOR1 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	79	/* GPIOR2 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	80	/* SPCR */ { "SPR0", "SPR1", "CPHA", "CPOL", "MSTR", "DORD", "SPE", "SPIE"},
	81	/* SPSR */ {"SPI2X", "1", "2", "3", "4", "5", "WCOL", "SPIF"},
	82	/* SPDR */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	83	/* 0x2F */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	84	/* ACSR */ {"ACIS0", "ACIS1", "ACIC", "ACIE", "ACI", "ACO", "ACBG", "ACD"},
	85	/* OCDR */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	86	/* 0x32 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	87	/* SMCR */ { "SE", "SM0", "SM1", "SM2", "4", "5", "6", "7"},
	88	/* MCUSR */ { "PORF", "EXTRF", "BORF", "WDRF", "JTRF", "5", "6", "7"},
	89	/* MCUCR */ { "IVCE", "IVSEL", "2", "3", "PUD", "5", "6", "JTD"},
	90	/* 0x36 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	91	/* SPMCSR */ {"SPMEN", "PGERS", "PGWRT","BLBSET","RWWSRE", "SIGRD", "RWWSB", "SPMIE"},
	92	/* 0x38 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	93	/* 0x39 */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	94	/* 0x3A */ { "0", "1", "2", "3", "4", "5", "6", "7"},
	95	/* RAMPZ */ {"RAMPZ0","RAMPZ1", "2", "3", "4", "5", "6", "7"},
	96	/* EIND */ {"EIND0", "1", "2", "3", "4", "5", "6", "7"},
	97	/* SPL */ { "SP0", "SP1", "SP2", "SP3", "SP4", "SP5", "SP6", "SP7"},
	98	/* SPH */ { "SP8", "SP9", "SP10", "SP11", "SP12", "SP13", "SP14", "SP15"},
	99	/* SREG */ { "C", "Z", "N", "V", "S", "H", "T", "I"}};
100	100
101	101	switch(op & 0xf000)
102	102	{
r29404	r29405
524	524	output += sprintf( output, "SBIW R%d:R%d, 0x%02x", 24+(RD2(op) << 1)+1, 24+(RD2(op) << 1), KCONST6(op) );
525	525	break;
526	526	case 0x0800:
527		if (ACONST5(op) < 0x20)
528		output += sprintf( output, "CBI %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
529		else
530		output += sprintf( output, "CBI 0x%02x, %d", ACONST5(op), RR3(op) );
	527	if (ACONST5(op) < 0x20)
	528	output += sprintf( output, "CBI %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
	529	else
	530	output += sprintf( output, "CBI 0x%02x, %d", ACONST5(op), RR3(op) );
531	531	break;
532	532	case 0x0900:
533		if (ACONST5(op) < 0x20)
534		output += sprintf( output, "SBIC %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
535		else
536		output += sprintf( output, "SBIC 0x%02x, %d", ACONST5(op), RR3(op) );
	533	if (ACONST5(op) < 0x20)
	534	output += sprintf( output, "SBIC %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
	535	else
	536	output += sprintf( output, "SBIC 0x%02x, %d", ACONST5(op), RR3(op) );
537	537	break;
538	538	case 0x0a00:
539		if (ACONST5(op) < 0x20)
540		output += sprintf( output, "SBI %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
541		else
542		output += sprintf( output, "SBI 0x%02x, %d", ACONST5(op), RR3(op) );
	539	if (ACONST5(op) < 0x20)
	540	output += sprintf( output, "SBI %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
	541	else
	542	output += sprintf( output, "SBI 0x%02x, %d", ACONST5(op), RR3(op) );
543	543	break;
544	544	case 0x0b00:
545		if (ACONST5(op) < 0x20)
546		output += sprintf( output, "SBIS %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
547		else
548		output += sprintf( output, "SBIS 0x%02x, %d", ACONST5(op), RR3(op) );
	545	if (ACONST5(op) < 0x20)
	546	output += sprintf( output, "SBIS %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
	547	else
	548	output += sprintf( output, "SBIS 0x%02x, %d", ACONST5(op), RR3(op) );
549	549	break;
550	550	case 0x0c00:
551	551	case 0x0d00:
r29404	r29405
558	558	case 0xb000:
559	559	if(op & 0x0800)
560	560	{
561		if (ACONST6(op) < 0x40 ) {
562		output += sprintf( output, "OUT %s, R%d", register_names[ACONST6(op)], RD5(op) );
563		} else {
564		output += sprintf( output, "OUT 0x%02x, R%d", ACONST6(op), RD5(op) );
565		}
	561	if (ACONST6(op) < 0x40 ) {
	562	output += sprintf( output, "OUT %s, R%d", register_names[ACONST6(op)], RD5(op) );
	563	} else {
	564	output += sprintf( output, "OUT 0x%02x, R%d", ACONST6(op), RD5(op) );
	565	}
566	566	}
567	567	else
568	568	{
569		if (ACONST6(op) < 0x40 ) {
570		output += sprintf( output, "IN R%d, %s", RD5(op), register_names[ACONST6(op)] );
571		} else {
572		output += sprintf( output, "IN R%d, 0x%02x", RD5(op), ACONST6(op) );
573		}
	569	if (ACONST6(op) < 0x40 ) {
	570	output += sprintf( output, "IN R%d, %s", RD5(op), register_names[ACONST6(op)] );
	571	} else {
	572	output += sprintf( output, "IN R%d, 0x%02x", RD5(op), ACONST6(op) );
	573	}
574	574	}
575	575	break;
576	576	case 0xc000:
577		//I'm not sure if this is correct. why pc + ... : pc + 8 + ... ?
	577	//I'm not sure if this is correct. why pc + ... : pc + 8 + ... ?
578	578	output += sprintf( output, "RJMP %08x", (((op & 0x0800) ? pc + ((op & 0x0fff) \| 0xfffff000) : pc + 8 + (op & 0x0fff)) << 0) );
579	579	break;
580	580	case 0xd000:

trunk/src/emu/cpu/z8000/z8000.c
r29404	r29405
834	834	}
835	835	}
836	836	}
837

trunk/src/emu/cpu/z8000/z8000.h
r29404	r29405
655	655	virtual UINT32 PSA_ADDR();
656	656	virtual UINT32 read_irq_vector();
657	657	};
658
659	658
	659
660	660	extern const device_type Z8001;
661	661	extern const device_type Z8002;
662	662

trunk/src/emu/cpu/z8000/z8000ops.inc
r29404	r29405
69	69	if (fcw & F_S_N) /* new mode is system mode */
70	70	{
71	71	if (!(m_fcw & F_S_N) /* old mode was user mode */
72		\|\| ((fcw ^ m_fcw) & F_SEG)) /* or switch between segmented and non-segmented */
	72	\|\| ((fcw ^ m_fcw) & F_SEG)) /* or switch between segmented and non-segmented */
73	73	{
74	74	tmp = RW(14);
75	75	RW(14) = m_nspseg;
r29404	r29405
79	79	else /* new mode is user mode */
80	80	{
81	81	if (m_fcw & F_S_N /* old mode was system mode */
82		&& m_fcw & F_SEG) /* and was segmented */
	82	&& m_fcw & F_SEG) /* and was segmented */
83	83	{
84	84	tmp = RW(14);
85	85	RW(14) = m_nspseg;

trunk/src/emu/cpu/i386/i386.c
r29404	r29405
4326	4326
4327	4327	CHANGE_PC(m_eip);
4328	4328	}
4329

trunk/src/emu/cpu/superfx/superfx.c
r29404	r29405
1432	1432	{
1433	1433	extern offs_t superfx_dasm_one(char *buffer, offs_t pc, UINT8 op, UINT8 param0, UINT8 param1, UINT16 alt);
1434	1434
1435		UINT8 op = (UINT8 )(opram + 0);
1436		UINT8 param0 = (UINT8 )(opram + 1);
1437		UINT8 param1 = (UINT8 )(opram + 2);
1438		UINT16 alt = m_sfr & SUPERFX_SFR_ALT;
	1435	UINT8 op = (UINT8 )(opram + 0);
	1436	UINT8 param0 = (UINT8 )(opram + 1);
	1437	UINT8 param1 = (UINT8 )(opram + 2);
	1438	UINT16 alt = m_sfr & SUPERFX_SFR_ALT;
1439	1439
1440		return superfx_dasm_one(buffer, pc, op, param0, param1, alt);
	1440	return superfx_dasm_one(buffer, pc, op, param0, param1, alt);
1441	1441	}
1442

trunk/src/emu/cpu/cpu.mak
r29404	r29405
489	489	ifneq ($(filter H8,$(CPUS)),)
490	490	OBJDIRS += $(CPUOBJ)/h8
491	491	CPUOBJS += $(CPUOBJ)/h8/h8.o $(CPUOBJ)/h8/h8h.o $(CPUOBJ)/h8/h8s2000.o $(CPUOBJ)/h8/h8s2600.o \
492		$(CPUOBJ)/h8/h83337.o \
493		$(CPUOBJ)/h8/h83002.o $(CPUOBJ)/h8/h83006.o $(CPUOBJ)/h8/h83008.o \
494		$(CPUOBJ)/h8/h83048.o \
495		$(CPUOBJ)/h8/h8s2245.o $(CPUOBJ)/h8/h8s2320.o $(CPUOBJ)/h8/h8s2357.o \
496		$(CPUOBJ)/h8/h8s2655.o \
497		$(CPUOBJ)/h8/h8_adc.o $(CPUOBJ)/h8/h8_port.o $(CPUOBJ)/h8/h8_intc.o \
498		$(CPUOBJ)/h8/h8_timer8.o $(CPUOBJ)/h8/h8_timer16.o $(CPUOBJ)/h8/h8_sci.o
	492	$(CPUOBJ)/h8/h83337.o \
	493	$(CPUOBJ)/h8/h83002.o $(CPUOBJ)/h8/h83006.o $(CPUOBJ)/h8/h83008.o \
	494	$(CPUOBJ)/h8/h83048.o \
	495	$(CPUOBJ)/h8/h8s2245.o $(CPUOBJ)/h8/h8s2320.o $(CPUOBJ)/h8/h8s2357.o \
	496	$(CPUOBJ)/h8/h8s2655.o \
	497	$(CPUOBJ)/h8/h8_adc.o $(CPUOBJ)/h8/h8_port.o $(CPUOBJ)/h8/h8_intc.o \
	498	$(CPUOBJ)/h8/h8_timer8.o $(CPUOBJ)/h8/h8_timer16.o $(CPUOBJ)/h8/h8_sci.o
499	499	DASMOBJS +=
500	500	endif
501	501
502		$(CPUOBJ)/h8/h8.o: $(CPUSRC)/h8/h8.c \
	502	$(CPUOBJ)/h8/h8.o: $(CPUSRC)/h8/h8.c \
503	503	$(CPUOBJ)/h8/h8.inc \
504	504	$(CPUSRC)/h8/h8.h
505	505
506		$(CPUOBJ)/h8/h8h.o: $(CPUSRC)/h8/h8h.c \
	506	$(CPUOBJ)/h8/h8h.o: $(CPUSRC)/h8/h8h.c \
507	507	$(CPUOBJ)/h8/h8h.inc \
508	508	$(CPUSRC)/h8/h8h.h \
509	509	$(CPUSRC)/h8/h8.h
510	510
511		$(CPUOBJ)/h8/h8s2000.o: $(CPUSRC)/h8/h8s2000.c \
	511	$(CPUOBJ)/h8/h8s2000.o: $(CPUSRC)/h8/h8s2000.c \
512	512	$(CPUOBJ)/h8/h8s2000.inc \
513	513	$(CPUSRC)/h8/h8s2000.h \
514	514	$(CPUSRC)/h8/h8h.h \
515	515	$(CPUSRC)/h8/h8.h
516	516
517		$(CPUOBJ)/h8/h8s2600.o: $(CPUSRC)/h8/h8s2600.c \
	517	$(CPUOBJ)/h8/h8s2600.o: $(CPUSRC)/h8/h8s2600.c \
518	518	$(CPUOBJ)/h8/h8s2600.inc \
519	519	$(CPUSRC)/h8/h8s2600.h \
520	520	$(CPUSRC)/h8/h8s2000.h \
521	521	$(CPUSRC)/h8/h8h.h \
522	522	$(CPUSRC)/h8/h8.h
523	523
524		$(CPUOBJ)/h8/h83337.o: $(CPUSRC)/h8/h83337.c \
	524	$(CPUOBJ)/h8/h83337.o: $(CPUSRC)/h8/h83337.c \
525	525	$(CPUSRC)/h8/h83337.h \
526	526	$(CPUSRC)/h8/h8.h \
527	527	$(CPUSRC)/h8/h8_intc.h \
r29404	r29405
531	531	$(CPUSRC)/h8/h8_timer16.h \
532	532	$(CPUSRC)/h8/h8_sci.h
533	533
534		$(CPUOBJ)/h8/h83002.o: $(CPUSRC)/h8/h83002.c \
	534	$(CPUOBJ)/h8/h83002.o: $(CPUSRC)/h8/h83002.c \
535	535	$(CPUSRC)/h8/h83002.h \
536	536	$(CPUSRC)/h8/h8h.h \
537	537	$(CPUSRC)/h8/h8.h \
r29404	r29405
541	541	$(CPUSRC)/h8/h8_timer16.h \
542	542	$(CPUSRC)/h8/h8_sci.h
543	543
544		$(CPUOBJ)/h8/h83006.o: $(CPUSRC)/h8/h83006.c \
	544	$(CPUOBJ)/h8/h83006.o: $(CPUSRC)/h8/h83006.c \
545	545	$(CPUSRC)/h8/h83006.h \
546	546	$(CPUSRC)/h8/h8h.h \
547	547	$(CPUSRC)/h8/h8.h \
r29404	r29405
552	552	$(CPUSRC)/h8/h8_timer16.h \
553	553	$(CPUSRC)/h8/h8_sci.h
554	554
555		$(CPUOBJ)/h8/h83008.o: $(CPUSRC)/h8/h83008.c \
	555	$(CPUOBJ)/h8/h83008.o: $(CPUSRC)/h8/h83008.c \
556	556	$(CPUSRC)/h8/h83008.h \
557	557	$(CPUSRC)/h8/h8h.h \
558	558	$(CPUSRC)/h8/h8.h \
r29404	r29405
563	563	$(CPUSRC)/h8/h8_timer16.h \
564	564	$(CPUSRC)/h8/h8_sci.h
565	565
566		$(CPUOBJ)/h8/h83048.o: $(CPUSRC)/h8/h83048.c \
	566	$(CPUOBJ)/h8/h83048.o: $(CPUSRC)/h8/h83048.c \
567	567	$(CPUSRC)/h8/h83048.h \
568	568	$(CPUSRC)/h8/h8h.h \
569	569	$(CPUSRC)/h8/h8.h \
r29404	r29405
573	573	$(CPUSRC)/h8/h8_timer16.h \
574	574	$(CPUSRC)/h8/h8_sci.h
575	575
576		$(CPUOBJ)/h8/h8s2245.o: $(CPUSRC)/h8/h8s2245.c \
	576	$(CPUOBJ)/h8/h8s2245.o: $(CPUSRC)/h8/h8s2245.c \
577	577	$(CPUSRC)/h8/h8s2245.h \
578	578	$(CPUSRC)/h8/h8s2000.h \
579	579	$(CPUSRC)/h8/h8h.h \
r29404	r29405
585	585	$(CPUSRC)/h8/h8_timer16.h \
586	586	$(CPUSRC)/h8/h8_sci.h
587	587
588		$(CPUOBJ)/h8/h8s2320.o: $(CPUSRC)/h8/h8s2320.c \
	588	$(CPUOBJ)/h8/h8s2320.o: $(CPUSRC)/h8/h8s2320.c \
589	589	$(CPUSRC)/h8/h8s2320.h \
590	590	$(CPUSRC)/h8/h8s2000.h \
591	591	$(CPUSRC)/h8/h8h.h \
r29404	r29405
597	597	$(CPUSRC)/h8/h8_timer16.h \
598	598	$(CPUSRC)/h8/h8_sci.h
599	599
600		$(CPUOBJ)/h8/h8s2357.o: $(CPUSRC)/h8/h8s2357.c \
	600	$(CPUOBJ)/h8/h8s2357.o: $(CPUSRC)/h8/h8s2357.c \
601	601	$(CPUSRC)/h8/h8s2357.h \
602	602	$(CPUSRC)/h8/h8s2000.h \
603	603	$(CPUSRC)/h8/h8h.h \
r29404	r29405
609	609	$(CPUSRC)/h8/h8_timer16.h \
610	610	$(CPUSRC)/h8/h8_sci.h
611	611
612		$(CPUOBJ)/h8/h8s2655.o: $(CPUSRC)/h8/h8s2655.c \
	612	$(CPUOBJ)/h8/h8s2655.o: $(CPUSRC)/h8/h8s2655.c \
613	613	$(CPUSRC)/h8/h8s2655.h \
614	614	$(CPUSRC)/h8/h8s2600.h \
615	615	$(CPUSRC)/h8/h8s2000.h \
r29404	r29405
622	622	$(CPUSRC)/h8/h8_timer16.h \
623	623	$(CPUSRC)/h8/h8_sci.h
624	624
625		$(CPUOBJ)/h8/h8_intc.o: $(CPUSRC)/h8/h8_intc.c \
	625	$(CPUOBJ)/h8/h8_intc.o: $(CPUSRC)/h8/h8_intc.c \
626	626	$(CPUSRC)/h8/h8_intc.h \
627	627	$(CPUSRC)/h8/h8.h
628	628
629		$(CPUOBJ)/h8/h8_adc.o: $(CPUSRC)/h8/h8_adc.c \
	629	$(CPUOBJ)/h8/h8_adc.o: $(CPUSRC)/h8/h8_adc.c \
630	630	$(CPUSRC)/h8/h8_adc.h \
631	631	$(CPUSRC)/h8/h8_intc.h \
632	632	$(CPUSRC)/h8/h8.h
633	633
634		$(CPUOBJ)/h8/h8_port.o: $(CPUSRC)/h8/h8_port.c \
	634	$(CPUOBJ)/h8/h8_port.o: $(CPUSRC)/h8/h8_port.c \
635	635	$(CPUSRC)/h8/h8_port.h \
636	636	$(CPUSRC)/h8/h8.h
637	637
638		$(CPUOBJ)/h8/h8_timer16.o: $(CPUSRC)/h8/h8_timer16.c \
	638	$(CPUOBJ)/h8/h8_timer16.o: $(CPUSRC)/h8/h8_timer16.c \
639	639	$(CPUSRC)/h8/h8_timer16.h \
640	640	$(CPUSRC)/h8/h8_intc.h \
641	641	$(CPUSRC)/h8/h8.h
642	642
643		$(CPUOBJ)/h8/h8_sci.o: $(CPUSRC)/h8/h8_sci.c \
	643	$(CPUOBJ)/h8/h8_sci.o: $(CPUSRC)/h8/h8_sci.c \
644	644	$(CPUSRC)/h8/h8_sci.h \
645	645	$(CPUSRC)/h8/h8_intc.h \
646	646	$(CPUSRC)/h8/h8.h

trunk/src/emu/cpu/scmp/scmp.c
r29404	r29405
564	564	break;
565	565	}
566	566	}
567

trunk/src/emu/cpu/i86/i186.c
r29404	r29405
642	642	m_timer[0].control = 0;
643	643	m_timer[1].control = 0;
644	644	m_timer[2].control = 0;
645
	645
646	646	set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(i80186_cpu_device::int_callback),this));
647	647	}
648	648

trunk/src/emu/cpu/upd7810/upd7810.c
r29404	r29405
487	487	}
488	488
489	489	upd78c05_device::upd78c05_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
490		: upd7810_device(mconfig, UPD78C05, "uPD78C05", tag, owner, clock, "upd78c05", __FILE__)
	490	: upd7810_device(mconfig, UPD78C05, "uPD78C05", tag, owner, clock, "upd78c05", __FILE__)
491	491	{
492	492	m_op48 = s_op48_78c05;
493	493	m_op4C = s_op4C_78c05;
r29404	r29405
2250	2250	}
2251	2251	/* resetting interrupt requests is done with the SKIT/SKNIT opcodes only! */
2252	2252	}
2253

trunk/src/emu/cpu/upd7810/upd7810.h
r29404	r29405
81	81	upd7810_device::set_an7_func(*device, DEVCB2_##_devcb);
82	82
83	83
84		class upd7810_device : public cpu_device
	84	class upd7810_device : public cpu_device
85	85	{
86	86	public:
87	87	// construction/destruction

trunk/src/emu/cpu/sc61860/sc61860.c
r29404	r29405
259	259
260	260	} while (m_icount > 0);
261	261	}
262

trunk/src/emu/cpu/v60/v60.c
r29404	r29405
550	550	v60_try_irq();
551	551	}
552	552	}
553

trunk/src/emu/cpu/v60/v60.h
r29404	r29405
157	157	UINT8 OV;
158	158	UINT8 S;
159	159	UINT8 Z;
160		} m_flags;
	160	} m_flags;
161	161	UINT8 m_irq_line;
162	162	UINT8 m_nmi_line;
163	163	address_space *m_program;

trunk/src/emu/cpu/ssp1601/ssp1601.c
r29404	r29405
780	780	{
781	781	fatalerror("ssp1610: execute_set_input not implemented yet!\n");
782	782	}
783

trunk/src/emu/cpu/esrip/esrip.h
r29404	r29405
27	27
28	28	#define MCFG_ESRIP_FDT_R_CALLBACK(_read) \
29	29	devcb = &esrip_device::static_set_fdt_r_callback(*device, DEVCB2_##_read);
30
	30
31	31	#define MCFG_ESRIP_FDT_W_CALLBACK(_write) \
32	32	devcb = &esrip_device::static_set_fdt_w_callback(*device, DEVCB2_##_write);
33
	33
34	34	#define MCFG_ESRIP_STATUS_IN_CALLBACK(_read) \
35	35	devcb = &esrip_device::static_set_status_in_callback(*device, DEVCB2_##_read);
36
	36
37	37	#define MCFG_ESRIP_DRAW_CALLBACK_OWNER(_class, _method) \
38	38	esrip_device::static_set_draw_callback(device, esrip_draw_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
39	39

trunk/src/emu/cpu/tms32010/tms32010.c
r29404	r29405
882	882
883	883	void tms32010_device::device_reset()
884	884	{
885		m_PC = 0;
886		m_ACC.d = 0;
887		m_INTF = TMS32010_INT_NONE;
888		/* Setup Status Register : 7efe */
889		CLR((OV_FLAG \| ARP_REG \| DP_REG));
890		SET_FLAG((OVM_FLAG \| INTM_FLAG));
	885	m_PC = 0;
	886	m_ACC.d = 0;
	887	m_INTF = TMS32010_INT_NONE;
	888	/* Setup Status Register : 7efe */
	889	CLR((OV_FLAG \| ARP_REG \| DP_REG));
	890	SET_FLAG((OVM_FLAG \| INTM_FLAG));
891	891	}
892	892
893	893
r29404	r29405
981	981	}
982	982	} while (m_icount > 0);
983	983	}
984

trunk/src/emu/cpu/tms32051/tms32051.c
r29404	r29405
520	520	}
521	521	return 1;
522	522	}
523

trunk/src/emu/cpu/tms32051/tms32051.h
r29404	r29405
61	61
62	62	// device_memory_interface overrides
63	63	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ); }
64		virtual bool memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value);
	64	virtual bool memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value);
65	65
66	66	// device_disasm_interface overrides
67	67	virtual UINT32 disasm_min_opcode_bytes() const { return 2; }

trunk/src/emu/cpu/rsp/rsp.h
r29404	r29405
17	17	#define __RSP_H__
18	18
19	19	#define USE_SIMD (0)
20		#define SIMUL_SIMD (0)
	20	#define SIMUL_SIMD (0)
21	21
22	22	#if USE_SIMD
23	23	#include <tmmintrin.h>

trunk/src/emu/cpu/rsp/rspdrc.c
r29404	r29405
3829	3829	}
3830	3830	VEC_WRITEBACK_RESULT();
3831	3831	/*
3832		__m128i loProduct, hiProduct, unpackLo, unpackHi;
3833		__m128i vaccHigh;
3834		__m128i vdReg, vdRegLo, vdRegHi;
	3832	__m128i loProduct, hiProduct, unpackLo, unpackHi;
	3833	__m128i vaccHigh;
	3834	__m128i vdReg, vdRegLo, vdRegHi;
3835	3835
3836		__m128i vsReg = rsp->xv[VS1REG];
3837		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	3836	__m128i vsReg = rsp->xv[VS1REG];
	3837	__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
3838	3838
3839		__m128i vaccLow = rsp->accum_l;
	3839	__m128i vaccLow = rsp->accum_l;
3840	3840
3841		// Unpack to obtain for 32-bit precision.
3842		RSPZeroExtend16to32(vaccLow, &vaccLow, &vaccHigh);
	3841	// Unpack to obtain for 32-bit precision.
	3842	RSPZeroExtend16to32(vaccLow, &vaccLow, &vaccHigh);
3843	3843
3844		// Begin accumulating the products.
3845		unpackLo = _mm_mullo_epi16(vsReg, vtReg);
3846		unpackHi = _mm_mulhi_epi16(vsReg, vtReg);
3847		loProduct = _mm_unpacklo_epi16(unpackLo, unpackHi);
3848		hiProduct = _mm_unpackhi_epi16(unpackLo, unpackHi);
3849		loProduct = _mm_slli_epi32(loProduct, 1);
3850		hiProduct = _mm_slli_epi32(hiProduct, 1);
	3844	// Begin accumulating the products.
	3845	unpackLo = _mm_mullo_epi16(vsReg, vtReg);
	3846	unpackHi = _mm_mulhi_epi16(vsReg, vtReg);
	3847	loProduct = _mm_unpacklo_epi16(unpackLo, unpackHi);
	3848	hiProduct = _mm_unpackhi_epi16(unpackLo, unpackHi);
	3849	loProduct = _mm_slli_epi32(loProduct, 1);
	3850	hiProduct = _mm_slli_epi32(hiProduct, 1);
3851	3851
3852		vdRegLo = _mm_srli_epi32(loProduct, 16);
3853		vdRegHi = _mm_srli_epi32(hiProduct, 16);
3854		vdRegLo = _mm_slli_epi32(vdRegLo, 16);
3855		vdRegHi = _mm_slli_epi32(vdRegHi, 16);
3856		vdRegLo = _mm_xor_si128(vdRegLo, loProduct);
3857		vdRegHi = _mm_xor_si128(vdRegHi, hiProduct);
	3852	vdRegLo = _mm_srli_epi32(loProduct, 16);
	3853	vdRegHi = _mm_srli_epi32(hiProduct, 16);
	3854	vdRegLo = _mm_slli_epi32(vdRegLo, 16);
	3855	vdRegHi = _mm_slli_epi32(vdRegHi, 16);
	3856	vdRegLo = _mm_xor_si128(vdRegLo, loProduct);
	3857	vdRegHi = _mm_xor_si128(vdRegHi, hiProduct);
3858	3858
3859		vaccLow = _mm_add_epi32(vaccLow, vdRegLo);
3860		vaccHigh = _mm_add_epi32(vaccHigh, vdRegHi);
	3859	vaccLow = _mm_add_epi32(vaccLow, vdRegLo);
	3860	vaccHigh = _mm_add_epi32(vaccHigh, vdRegHi);
3861	3861
3862		rsp->accum_l = vdReg = RSPPackLo32to16(vaccLow, vaccHigh);
	3862	rsp->accum_l = vdReg = RSPPackLo32to16(vaccLow, vaccHigh);
3863	3863
3864		// Multiply the MSB of sources, accumulate the product.
3865		vdRegLo = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
3866		vdRegHi = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
	3864	// Multiply the MSB of sources, accumulate the product.
	3865	vdRegLo = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
	3866	vdRegHi = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
3867	3867
3868		loProduct = _mm_srai_epi32(loProduct, 16);
3869		hiProduct = _mm_srai_epi32(hiProduct, 16);
3870		vaccLow = _mm_srai_epi32(vaccLow, 16);
3871		vaccHigh = _mm_srai_epi32(vaccHigh, 16);
	3868	loProduct = _mm_srai_epi32(loProduct, 16);
	3869	hiProduct = _mm_srai_epi32(hiProduct, 16);
	3870	vaccLow = _mm_srai_epi32(vaccLow, 16);
	3871	vaccHigh = _mm_srai_epi32(vaccHigh, 16);
3872	3872
3873		vaccLow = _mm_add_epi32(loProduct, vaccLow);
3874		vaccHigh = _mm_add_epi32(hiProduct, vaccHigh);
3875		vaccLow = _mm_add_epi32(vdRegLo, vaccLow);
3876		vaccHigh = _mm_add_epi32(vdRegHi, vaccHigh);
	3873	vaccLow = _mm_add_epi32(loProduct, vaccLow);
	3874	vaccHigh = _mm_add_epi32(hiProduct, vaccHigh);
	3875	vaccLow = _mm_add_epi32(vdRegLo, vaccLow);
	3876	vaccHigh = _mm_add_epi32(vdRegHi, vaccHigh);
3877	3877
3878		// Clamp the accumulator and write it all out.
3879		rsp->xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
3880		rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
3881		rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
	3878	// Clamp the accumulator and write it all out.
	3879	rsp->xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
	3880	rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
	3881	rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
3882	3882	*/
3883	3883	}
3884	3884
r29404	r29405
4269	4269	}
4270	4270	/INLINE void cfunc_rsp_vmadn_simd(void param)
4271	4271	{
4272		rsp_state rsp = (rsp_state)param;
4273		int op = rsp->impstate->arg0;
	4272	rsp_state rsp = (rsp_state)param;
	4273	int op = rsp->impstate->arg0;
4274	4274
4275		__m128i vaccLow, vaccHigh, loProduct, hiProduct;
4276		__m128i vsRegLo, vsRegHi, vtRegLo, vtRegHi, vdRegLo, vdRegHi;
	4275	__m128i vaccLow, vaccHigh, loProduct, hiProduct;
	4276	__m128i vsRegLo, vsRegHi, vtRegLo, vtRegHi, vdRegLo, vdRegHi;
4277	4277
4278		__m128i vsReg = rsp->xv[VS1REG];
4279		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	4278	__m128i vsReg = rsp->xv[VS1REG];
	4279	__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
4280	4280
4281		vaccLow = rsp->accum_l;
	4281	vaccLow = rsp->accum_l;
4282	4282
4283		RSPZeroExtend16to32(vsReg, &vsRegLo, &vsRegHi);
4284		RSPSignExtend16to32(vtReg, &vtRegLo, &vtRegHi);
4285		RSPZeroExtend16to32(vaccLow, &vaccLow, &vaccHigh);
	4283	RSPZeroExtend16to32(vsReg, &vsRegLo, &vsRegHi);
	4284	RSPSignExtend16to32(vtReg, &vtRegLo, &vtRegHi);
	4285	RSPZeroExtend16to32(vaccLow, &vaccLow, &vaccHigh);
4286	4286
4287		// Begin accumulating the products.
4288		loProduct = _mm_mullo_epi32(vsRegLo, vtRegLo);
4289		hiProduct = _mm_mullo_epi32(vsRegHi, vtRegHi);
	4287	// Begin accumulating the products.
	4288	loProduct = _mm_mullo_epi32(vsRegLo, vtRegLo);
	4289	hiProduct = _mm_mullo_epi32(vsRegHi, vtRegHi);
4290	4290
4291		vdRegLo = _mm_srli_epi32(loProduct, 16);
4292		vdRegHi = _mm_srli_epi32(hiProduct, 16);
4293		vdRegLo = _mm_slli_epi32(vdRegLo, 16);
4294		vdRegHi = _mm_slli_epi32(vdRegHi, 16);
4295		vdRegLo = _mm_xor_si128(vdRegLo, loProduct);
4296		vdRegHi = _mm_xor_si128(vdRegHi, hiProduct);
	4291	vdRegLo = _mm_srli_epi32(loProduct, 16);
	4292	vdRegHi = _mm_srli_epi32(hiProduct, 16);
	4293	vdRegLo = _mm_slli_epi32(vdRegLo, 16);
	4294	vdRegHi = _mm_slli_epi32(vdRegHi, 16);
	4295	vdRegLo = _mm_xor_si128(vdRegLo, loProduct);
	4296	vdRegHi = _mm_xor_si128(vdRegHi, hiProduct);
4297	4297
4298		vaccLow = _mm_add_epi32(vaccLow, vdRegLo);
4299		vaccHigh = _mm_add_epi32(vaccHigh, vdRegHi);
	4298	vaccLow = _mm_add_epi32(vaccLow, vdRegLo);
	4299	vaccHigh = _mm_add_epi32(vaccHigh, vdRegHi);
4300	4300
4301		rsp->accum_l = RSPPackLo32to16(vaccLow, vaccHigh);
	4301	rsp->accum_l = RSPPackLo32to16(vaccLow, vaccHigh);
4302	4302
4303		// Multiply the MSB of sources, accumulate the product.
4304		vdRegLo = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
4305		vdRegHi = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
	4303	// Multiply the MSB of sources, accumulate the product.
	4304	vdRegLo = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
	4305	vdRegHi = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
4306	4306
4307		loProduct = _mm_srai_epi32(loProduct, 16);
4308		hiProduct = _mm_srai_epi32(hiProduct, 16);
4309		vaccLow = _mm_srai_epi32(vaccLow, 16);
4310		vaccHigh = _mm_srai_epi32(vaccHigh, 16);
	4307	loProduct = _mm_srai_epi32(loProduct, 16);
	4308	hiProduct = _mm_srai_epi32(hiProduct, 16);
	4309	vaccLow = _mm_srai_epi32(vaccLow, 16);
	4310	vaccHigh = _mm_srai_epi32(vaccHigh, 16);
4311	4311
4312		vaccLow = _mm_add_epi32(loProduct, vaccLow);
4313		vaccHigh = _mm_add_epi32(hiProduct, vaccHigh);
4314		vaccLow = _mm_add_epi32(vdRegLo, vaccLow);
4315		vaccHigh = _mm_add_epi32(vdRegHi, vaccHigh);
	4312	vaccLow = _mm_add_epi32(loProduct, vaccLow);
	4313	vaccHigh = _mm_add_epi32(hiProduct, vaccHigh);
	4314	vaccLow = _mm_add_epi32(vdRegLo, vaccLow);
	4315	vaccHigh = _mm_add_epi32(vdRegHi, vaccHigh);
4316	4316
4317		// Clamp the accumulator and write it all out.
4318		rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
4319		rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
4320		rsp->xv[VDREG] = RSPClampLowToVal(rsp->accum_l, rsp->accum_m, rsp->accum_h);
	4317	// Clamp the accumulator and write it all out.
	4318	rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
	4319	rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
	4320	rsp->xv[VDREG] = RSPClampLowToVal(rsp->accum_l, rsp->accum_m, rsp->accum_h);
4321	4321	}*/
4322	4322
4323	4323	#endif

trunk/src/emu/cpu/tlcs90/tlcs90.c
r29404	r29405
2788	2788	break;
2789	2789	}
2790	2790	}
2791

trunk/src/emu/cpu/powerpc/ppccom.c
r29404	r29405
2489	2489	}
2490	2490
2491	2491	/*-------------------------------------------------
2492		ppc4xx_set_dcr_read_handler
	2492	ppc4xx_set_dcr_read_handler
2493	2493	-------------------------------------------------*/
2494	2494
2495	2495	void ppc4xx_set_dcr_read_handler(device_t *device, read32_delegate dcr_read_func)
r29404	r29405
2500	2500	}
2501	2501
2502	2502	/*-------------------------------------------------
2503		ppc4xx_set_dcr_write_handler
	2503	ppc4xx_set_dcr_write_handler
2504	2504	-------------------------------------------------*/
2505	2505
2506	2506	void ppc4xx_set_dcr_write_handler(device_t *device, write32_delegate dcr_write_func)

trunk/src/emu/cpu/h8/h8_sci.c
r29404	r29405
32	32	{
33	33	smr = data;
34	34	logerror("%s: smr_w %02x %s %c%c%c%s /%d (%06x)\n", tag(), data,
35		data & SMR_CA ? "sync" : "async",
36		data & SMR_CHR ? '7' : '8',
37		data & SMR_PE ? data & SMR_OE ? 'o' : 'e' : 'n',
38		data & SMR_STOP ? '2' : '1',
39		data & SMR_MP ? " mp" : "",
40		1 << 2*(data & SMR_CKS),
41		cpu->pc());
	35	data & SMR_CA ? "sync" : "async",
	36	data & SMR_CHR ? '7' : '8',
	37	data & SMR_PE ? data & SMR_OE ? 'o' : 'e' : 'n',
	38	data & SMR_STOP ? '2' : '1',
	39	data & SMR_MP ? " mp" : "",
	40	1 << 2*(data & SMR_CKS),
	41	cpu->pc());
42	42	clock_update();
43	43	}
44	44
r29404	r29405
64	64	WRITE8_MEMBER(h8_sci_device::scr_w)
65	65	{
66	66	logerror("%s: scr_w %02x%s%s%s%s%s%s clk=%d (%06x)\n", tag(), data,
67		data & SCR_TIE ? " txi" : "",
68		data & SCR_RIE ? " rxi" : "",
69		data & SCR_TE ? " tx" : "",
70		data & SCR_RE ? " rx" : "",
71		data & SCR_MPIE ? " mpi" : "",
72		data & SCR_TEIE ? " tei" : "",
73		data & SCR_CKE,
74		cpu->pc());
	67	data & SCR_TIE ? " txi" : "",
	68	data & SCR_RIE ? " rxi" : "",
	69	data & SCR_TE ? " tx" : "",
	70	data & SCR_RE ? " rx" : "",
	71	data & SCR_MPIE ? " mpi" : "",
	72	data & SCR_TEIE ? " tei" : "",
	73	data & SCR_CKE,
	74	cpu->pc());
75	75
76	76	UINT8 delta = scr ^ data;
77	77	scr = data;
r29404	r29405
217	217	external_to_internal_ratio = (external_clock_period*cpu->clock()).as_double();
218	218	internal_to_external_ratio = 1/external_to_internal_ratio;
219	219	}
220
	220
221	221	intc = siblingdevice<h8_intc_device>(intc_tag);
222	222	save_item(NAME(rdr));
223	223	save_item(NAME(tdr));
r29404	r29405
301	301	case CLKM_EXTERNAL_SYNC:
302	302	if((!ext_clock_value) && (clock_state & CLK_TX))
303	303	tx_dropped_edge();
304
	304
305	305	else if(ext_clock_value && (clock_state & CLK_RX))
306	306	rx_raised_edge();
307	307	break;
r29404	r29405
324	324	clock_base += fp;
325	325	}
326	326	assert(delta < fp);
327
	327
328	328	bool new_clock = delta >= divider;
329	329	if(new_clock != clock_value) {
330	330	cpu->synchronize();
331	331	if((!new_clock) && (clock_state & CLK_TX))
332	332	tx_dropped_edge();
333
	333
334	334	else if(new_clock && (clock_state & CLK_RX))
335	335	rx_raised_edge();
336
	336
337	337	clock_value = new_clock;
338	338	if(clock_state \|\| clock_value)
339	339	clk_cb(clock_value);
r29404	r29405
359	359	cpu->synchronize();
360	360	if((!new_clock) && (clock_state & CLK_TX))
361	361	tx_dropped_edge();
362
	362
363	363	else if(new_clock && (clock_state & CLK_RX))
364	364	rx_raised_edge();
365
	365
366	366	clock_value = new_clock;
367	367	if(clock_mode == CLKM_INTERNAL_ASYNC_OUT && (clock_state \|\| !clock_value))
368	368	clk_cb(clock_value);
369	369	}
370	370	}
371
	371
372	372	event = clock_base + (clock_value ? fp : divider*8);
373	373	}
374	374	break;
r29404	r29405
385	385	cpu->synchronize();
386	386	if((!new_clock) && (clock_state & CLK_TX))
387	387	tx_dropped_edge();
388
	388
389	389	else if(new_clock && (clock_state & CLK_RX))
390	390	rx_raised_edge();
391
	391
392	392	clock_value = new_clock;
393	393	}
394	394	}
395
	395
396	396	event = UINT64((clock_base + (clock_value ? 2 : 1))*external_to_internal_ratio)+1;
397	397	}
398	398	break;
r29404	r29405
409	409	cpu->synchronize();
410	410	if((!new_clock) && (clock_state & CLK_TX))
411	411	tx_dropped_edge();
412
	412
413	413	else if(new_clock && (clock_state & CLK_RX))
414	414	rx_raised_edge();
415
	415
416	416	clock_value = new_clock;
417	417	}
418	418	}
419
	419
420	420	event = UINT64((clock_base + (clock_value ? 16 : 8))*external_to_internal_ratio)+1;
421	421	}
422	422	break;
r29404	r29405
503	503	}
504	504	clock_start(CLK_TX);
505	505	}
506
	506
507	507	void h8_sci_device::tx_dropped_edge()
508	508	{
509	509	logerror("%s: tx_dropped_edge state=%s bit=%d\n", tag(), state_names[tx_state], tx_bit);
r29404	r29405
676	676	}
677	677	logerror("%s: -> state=%s, bit=%d\n", tag(), state_names[rx_state], rx_bit);
678	678	}
679

trunk/src/emu/cpu/h8/h8s2320.h
r29404	r29405
68	68	h8s2320_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
69	69
70	70	DECLARE_READ8_MEMBER(syscr_r);
71		DECLARE_WRITE8_MEMBER(syscr_w);
	71	DECLARE_WRITE8_MEMBER(syscr_w);
72	72
73	73	protected:
74	74	required_device<h8s_intc_device> intc;

trunk/src/emu/cpu/h8/h8s2245.c
r29404	r29405
101	101	MCFG_H8H_TIMER8_CHANNEL_ADD("timer8_1", "intc", 68, 69, 70, "timer8_0", h8_timer8_channel_device::CHAIN_A, false, false)
102	102	MCFG_H8_TIMER16_ADD("timer16", 3, 0x00)
103	103	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:0", 4, 0x60, "intc", 32,
104		h8_timer16_channel_device::DIV_1,
105		h8_timer16_channel_device::DIV_4,
106		h8_timer16_channel_device::DIV_16,
107		h8_timer16_channel_device::DIV_64,
108		h8_timer16_channel_device::INPUT_A,
109		h8_timer16_channel_device::INPUT_B,
110		h8_timer16_channel_device::INPUT_C,
111		h8_timer16_channel_device::INPUT_D)
	104	h8_timer16_channel_device::DIV_1,
	105	h8_timer16_channel_device::DIV_4,
	106	h8_timer16_channel_device::DIV_16,
	107	h8_timer16_channel_device::DIV_64,
	108	h8_timer16_channel_device::INPUT_A,
	109	h8_timer16_channel_device::INPUT_B,
	110	h8_timer16_channel_device::INPUT_C,
	111	h8_timer16_channel_device::INPUT_D)
112	112	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:1", 2, 0x4c, "intc", 40,
113		h8_timer16_channel_device::DIV_1,
114		h8_timer16_channel_device::DIV_4,
115		h8_timer16_channel_device::DIV_16,
116		h8_timer16_channel_device::DIV_64,
117		h8_timer16_channel_device::INPUT_A,
118		h8_timer16_channel_device::INPUT_B,
119		h8_timer16_channel_device::DIV_256,
120		h8_timer16_channel_device::CHAIN)
	113	h8_timer16_channel_device::DIV_1,
	114	h8_timer16_channel_device::DIV_4,
	115	h8_timer16_channel_device::DIV_16,
	116	h8_timer16_channel_device::DIV_64,
	117	h8_timer16_channel_device::INPUT_A,
	118	h8_timer16_channel_device::INPUT_B,
	119	h8_timer16_channel_device::DIV_256,
	120	h8_timer16_channel_device::CHAIN)
121	121	MCFG_H8S_TIMER16_CHANNEL_SET_CHAIN("timer16:2")
122	122	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:2", 2, 0x4c, "intc", 44,
123		h8_timer16_channel_device::DIV_1,
124		h8_timer16_channel_device::DIV_4,
125		h8_timer16_channel_device::DIV_16,
126		h8_timer16_channel_device::DIV_64,
127		h8_timer16_channel_device::INPUT_A,
128		h8_timer16_channel_device::INPUT_B,
129		h8_timer16_channel_device::INPUT_C,
130		h8_timer16_channel_device::DIV_1024)
	123	h8_timer16_channel_device::DIV_1,
	124	h8_timer16_channel_device::DIV_4,
	125	h8_timer16_channel_device::DIV_16,
	126	h8_timer16_channel_device::DIV_64,
	127	h8_timer16_channel_device::INPUT_A,
	128	h8_timer16_channel_device::INPUT_B,
	129	h8_timer16_channel_device::INPUT_C,
	130	h8_timer16_channel_device::DIV_1024)
131	131	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
132	132	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
133	133	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)

trunk/src/emu/cpu/h8/h8_sci.h
r29404	r29405
84	84	template<class _Object> static devcb2_base &set_clk_cb(device_t &device, _Object object) { return downcast<h8_sci_device &>(device).clk_cb.set_callback(object); }
85	85
86	86	UINT64 internal_update(UINT64 current_time);
87
	87
88	88	protected:
89	89	enum {
90	90	ST_IDLE, ST_START, ST_BIT, ST_PARITY, ST_STOP, ST_LAST_TICK,

trunk/src/emu/cpu/h8/h8s2245.h
r29404	r29405
63	63	h8s2245_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
64	64
65	65	DECLARE_READ8_MEMBER(syscr_r);
66		DECLARE_WRITE8_MEMBER(syscr_w);
	66	DECLARE_WRITE8_MEMBER(syscr_w);
67	67
68	68	protected:
69	69	required_device<h8s_intc_device> intc;

trunk/src/emu/cpu/h8/h8_adc.c
r29404	r29405
124	124	mode = IDLE;
125	125	channel = 0;
126	126	count = 0;
127		next_event = 0;
	127	next_event = 0;
128	128	mode_update();
129	129	analog_powered = !analog_power_control;
130	130	adtrg = true;
r29404	r29405
188	188	count = start_count;
189	189	sampling();
190	190	conversion_wait(true, !analog_powered);
191		analog_powered = true;
	191	analog_powered = true;
192	192	}
193	193
194	194	void h8_adc_device::timeout(UINT64 current_time)
r29404	r29405
450	450
451	451	if(adcsr & 0x03) {
452	452	mode \|= BUFFER;
453
	453
454	454	}
455	455
456	456	if(adcsr & 0x08) {

trunk/src/emu/cpu/h8/h8_timer16.c
r29404	r29405
94	94	tier = data;
95	95	tier_update();
96	96	logerror("%s: irq %c%c%c%c%c%c trigger=%d\n",
97		tag(),
98		ier & IRQ_A ? 'a' : '.',
99		ier & IRQ_B ? 'b' : '.',
100		ier & IRQ_C ? 'c' : '.',
101		ier & IRQ_D ? 'd' : '.',
102		ier & IRQ_V ? 'v' : '.',
103		ier & IRQ_U ? 'u' : '.',
104		ier & IRQ_TRIG ? 1 : 0);
	97	tag(),
	98	ier & IRQ_A ? 'a' : '.',
	99	ier & IRQ_B ? 'b' : '.',
	100	ier & IRQ_C ? 'c' : '.',
	101	ier & IRQ_D ? 'd' : '.',
	102	ier & IRQ_V ? 'v' : '.',
	103	ier & IRQ_U ? 'u' : '.',
	104	ier & IRQ_TRIG ? 1 : 0);
105	105	recalc_event();
106	106	}
107	107
r29404	r29405
218	218	tcnt = tt % counter_cycle;
219	219	if(0)
220	220	logerror("%s: Updating %d (%ld %ld) (%ld %ld) -> %d/%d\n",
221		tag(),
222		ott,
223		long(last_clock_update), long(cur_time),
224		long(base_time), long(new_time),
225		tt, tcnt);
	221	tag(),
	222	ott,
	223	long(last_clock_update), long(cur_time),
	224	long(base_time), long(new_time),
	225	tt, tcnt);
226	226
227	227	for(int i=0; i<tgr_count; i++)
228	228	if((ier & (1 << i)) && (tt == tgr[i] \|\| tcnt == tgr[i]) && interrupt[i] != -1) {
r29404	r29405
284	284
285	285	if(0)
286	286	logerror("%s: tcnt=%d tgr%c=%d cycle=%d -> delay=%d\n",
287		tag(), tcnt, 'a'+i, tgr[i], counter_cycle, new_delay);
	287	tag(), tcnt, 'a'+i, tgr[i], counter_cycle, new_delay);
288	288	if(event_delay > new_delay)
289	289	event_delay = new_delay;
290	290	}
r29404	r29405
292	292	event_time = ((((cur_time + (1ULL << clock_divider) - phase) >> clock_divider) + event_delay - 1) << clock_divider) + phase;
293	293	else
294	294	event_time = 0;
295
	295
296	296	if(event_time && 0)
297	297	logerror("%s: next event in %d cycles (%ld)\n", tag(), int(event_time - cpu->get_cycle()), long(event_time));
298
	298
299	299	} else {
300	300	logerror("decrementing counter\n");
301	301	exit(1);
r29404	r29405
622	622	}
623	623
624	624	void h8s_timer16_channel_device::set_info(int _tgr_count, UINT8 _tier_mask, const char *intc, int irq_base,
625		int t0, int t1, int t2, int t3, int t4, int t5, int t6, int t7)
	625	int t0, int t1, int t2, int t3, int t4, int t5, int t6, int t7)
626	626	{
627	627	tgr_count = _tgr_count;
628	628	tbr_count = 0;

trunk/src/emu/cpu/h8/h83002.h
r29404	r29405
54	54	h83002_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
55	55
56	56	DECLARE_READ8_MEMBER(syscr_r);
57		DECLARE_WRITE8_MEMBER(syscr_w);
	57	DECLARE_WRITE8_MEMBER(syscr_w);
58	58
59	59	protected:
60	60	required_device<h8h_intc_device> intc;

trunk/src/emu/cpu/h8/h8_adc.h
r29404	r29405
43	43	#include "h8.h"
44	44	#include "h8_intc.h"
45	45
46		#define MCFG_H8_ADC_GENERIC_ADD( _tag, _type, intc, vect ) \
	46	#define MCFG_H8_ADC_GENERIC_ADD( _tag, _type, intc, vect ) \
47	47	MCFG_DEVICE_ADD( _tag, _type, 0 ) \
48	48	downcast<h8_adc_device *>(device)->set_info(intc, vect);
49	49

trunk/src/emu/cpu/h8/h8_timer16.h
r29404	r29405
43	43	#include "h8.h"
44	44	#include "h8_intc.h"
45	45
46		#define MCFG_H8_TIMER16_ADD( _tag, _count, _tstr ) \
47		MCFG_DEVICE_ADD( _tag, H8_TIMER16, 0 ) \
	46	#define MCFG_H8_TIMER16_ADD( _tag, _count, _tstr ) \
	47	MCFG_DEVICE_ADD( _tag, H8_TIMER16, 0 ) \
48	48	downcast<h8_timer16_device *>(device)->set_info(_count, _tstr);
49	49
50	50	#define MCFG_H8_TIMER16_CHANNEL_ADD( _tag, tgr_count, tbr_count, intc, irq_base ) \
51		MCFG_DEVICE_ADD( _tag, H8_TIMER16_CHANNEL, 0 ) \
	51	MCFG_DEVICE_ADD( _tag, H8_TIMER16_CHANNEL, 0 ) \
52	52	downcast<h8_timer16_channel_device *>(device)->set_info(tgr_count, tbr_count, intc, irq_base);
53	53
54	54	#define MCFG_H8H_TIMER16_CHANNEL_ADD( _tag, tgr_count, tbr_count, intc, irq_base ) \
55		MCFG_DEVICE_ADD( _tag, H8H_TIMER16_CHANNEL, 0 ) \
	55	MCFG_DEVICE_ADD( _tag, H8H_TIMER16_CHANNEL, 0 ) \
56	56	downcast<h8h_timer16_channel_device *>(device)->set_info(tgr_count, tbr_count, intc, irq_base);
57	57
58	58	#define MCFG_H8S_TIMER16_CHANNEL_ADD( _tag, tgr_count, tier_mask, intc, irq_base, t0, t1, t2, t3, t4, t5, t6, t7 ) \
59		MCFG_DEVICE_ADD( _tag, H8S_TIMER16_CHANNEL, 0 ) \
	59	MCFG_DEVICE_ADD( _tag, H8S_TIMER16_CHANNEL, 0 ) \
60	60	downcast<h8s_timer16_channel_device *>(device)->set_info(tgr_count, tier_mask, intc, irq_base, t0, t1, t2, t3, t4, t5, t6, t7);
61	61
62		#define MCFG_H8S_TIMER16_CHANNEL_SET_CHAIN( _tag ) \
	62	#define MCFG_H8S_TIMER16_CHANNEL_SET_CHAIN( _tag ) \
63	63	downcast<h8s_timer16_channel_device *>(device)->set_chain(_tag);
64	64
65	65	class h8_timer16_channel_device : public device_t {
r29404	r29405
180	180	virtual ~h8s_timer16_channel_device();
181	181
182	182	void set_info(int tgr_count, UINT8 _tier_mask, const char *intc, int irq_base,
183		int t0, int t1, int t2, int t3, int t4, int t5, int t6, int t7);
	183	int t0, int t1, int t2, int t3, int t4, int t5, int t6, int t7);
184	184	void set_chain(const char *chain_tag);
185	185
186	186	protected:

trunk/src/emu/cpu/h8/h83006.h
r29404	r29405
56	56	h83006_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
57	57
58	58	DECLARE_READ8_MEMBER(syscr_r);
59		DECLARE_WRITE8_MEMBER(syscr_w);
	59	DECLARE_WRITE8_MEMBER(syscr_w);
60	60
61	61	protected:
62	62	required_device<h8h_intc_device> intc;

trunk/src/emu/cpu/h8/h83008.h
r29404	r29405
56	56	h83008_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
57	57
58	58	DECLARE_READ8_MEMBER(syscr_r);
59		DECLARE_WRITE8_MEMBER(syscr_w);
	59	DECLARE_WRITE8_MEMBER(syscr_w);
60	60
61	61	protected:
62	62	required_device<h8h_intc_device> intc;

trunk/src/emu/cpu/h8/h83048.h
r29404	r29405
63	63	h83048_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
64	64
65	65	DECLARE_READ8_MEMBER(syscr_r);
66		DECLARE_WRITE8_MEMBER(syscr_w);
	66	DECLARE_WRITE8_MEMBER(syscr_w);
67	67
68	68	protected:
69	69	required_device<h8h_intc_device> intc;

trunk/src/emu/cpu/h8/h8_timer8.c
r29404	r29405
92	92	clock_type = INPUT_UPDOWN;
93	93	clock_divider = 0;
94	94	logerror("%s: clock external both edges", tag());
95		break;
	95	break;
96	96	}
97	97
98	98	switch(tcr & TCR_CCLR) {
r29404	r29405
118	118	}
119	119
120	120	logerror(", irq=%c%c%c\n",
121		tcr & TCR_CMIEB ? 'b' : '-',
122		tcr & TCR_CMIEA ? 'a' : '-',
123		tcr & TCR_OVIE ? 'o' : '-');
	121	tcr & TCR_CMIEB ? 'b' : '-',
	122	tcr & TCR_CMIEA ? 'a' : '-',
	123	tcr & TCR_OVIE ? 'o' : '-');
124	124	}
125	125
126	126	READ8_MEMBER(h8_timer8_channel_device::tcsr_r)
r29404	r29405
223	223	if(tt == tcor[0] \|\| tcnt == tcor[0]) {
224	224	if(chained_timer)
225	225	chained_timer->chained_timer_tcora();
226
	226
227	227	if(!(tcsr & TCSR_CMFA)) {
228	228	tcsr \|= TCSR_CMFA;
229	229	if(tcr & TCR_CMIEA)
r29404	r29405
317	317	if(tcnt == tcor[0]) {
318	318	if(chained_timer)
319	319	chained_timer->chained_timer_tcora();
320
	320
321	321	if(!(tcsr & TCSR_CMFA)) {
322	322	tcsr \|= TCSR_CMFA;
323	323	if(tcr & TCR_CMIEA)

trunk/src/emu/cpu/h8/h8_timer8.h
r29404	r29405
44	44	#include "h8_intc.h"
45	45
46	46	#define MCFG_H8_TIMER8_CHANNEL_ADD( _tag, intc, irq_ca, irq_cb, irq_v, div1, div2, div3, div4, div5, div6 ) \
47		MCFG_DEVICE_ADD( _tag, H8_TIMER8_CHANNEL, 0 ) \
	47	MCFG_DEVICE_ADD( _tag, H8_TIMER8_CHANNEL, 0 ) \
48	48	downcast<h8_timer8_channel_device *>(device)->set_info(intc, irq_ca, irq_cb, irq_v, div1, div2, div3, div4, div5, div6);
49	49
50	50	#define MCFG_H8H_TIMER8_CHANNEL_ADD( _tag, intc, irq_ca, irq_cb, irq_v, chain, chain_mode, has_adte, has_ice ) \
51		MCFG_DEVICE_ADD( _tag, H8H_TIMER8_CHANNEL, 0 ) \
	51	MCFG_DEVICE_ADD( _tag, H8H_TIMER8_CHANNEL, 0 ) \
52	52	downcast<h8h_timer8_channel_device *>(device)->set_info(intc, irq_ca, irq_cb, irq_v, chain, chain_mode, has_adte, has_ice);
53	53
54	54	class h8_timer8_channel_device : public device_t {
r29404	r29405
95	95	TCSR_ADTE = 0x10,
96	96	TCSR_OVF = 0x20,
97	97	TCSR_CMFA = 0x40,
98		TCSR_CMFB = 0x80
	98	TCSR_CMFB = 0x80
99	99	};
100	100
101	101	enum {

trunk/src/emu/cpu/h8/h8.c
r29404	r29405
252	252	case STATE_GENFLAGS:
253	253	if(has_exr)
254	254	string.printf("%c%c %c%c%c%c%c%c%c%c",
255		(EXR & EXR_T) ? 'T' : '-',
256		'0' + (EXR & EXR_I),
257		(CCR & F_I) ? 'I' : '-',
258		(CCR & F_UI) ? 'u' : '-',
259		(CCR & F_H) ? 'H' : '-',
260		(CCR & F_U) ? 'U' : '-',
261		(CCR & F_N) ? 'N' : '-',
262		(CCR & F_Z) ? 'Z' : '-',
263		(CCR & F_V) ? 'V' : '-',
264		(CCR & F_C) ? 'C' : '-');
	255	(EXR & EXR_T) ? 'T' : '-',
	256	'0' + (EXR & EXR_I),
	257	(CCR & F_I) ? 'I' : '-',
	258	(CCR & F_UI) ? 'u' : '-',
	259	(CCR & F_H) ? 'H' : '-',
	260	(CCR & F_U) ? 'U' : '-',
	261	(CCR & F_N) ? 'N' : '-',
	262	(CCR & F_Z) ? 'Z' : '-',
	263	(CCR & F_V) ? 'V' : '-',
	264	(CCR & F_C) ? 'C' : '-');
265	265	else
266		string.printf("%c%c%c%c%c%c%c%c",
267		(CCR & F_I) ? 'I' : '-',
268		(CCR & F_UI) ? 'u' : '-',
269		(CCR & F_H) ? 'H' : '-',
270		(CCR & F_U) ? 'U' : '-',
271		(CCR & F_N) ? 'N' : '-',
272		(CCR & F_Z) ? 'Z' : '-',
273		(CCR & F_V) ? 'V' : '-',
274		(CCR & F_C) ? 'C' : '-');
	266	string.printf("%c%c%c%c%c%c%c%c",
	267	(CCR & F_I) ? 'I' : '-',
	268	(CCR & F_UI) ? 'u' : '-',
	269	(CCR & F_H) ? 'H' : '-',
	270	(CCR & F_U) ? 'U' : '-',
	271	(CCR & F_N) ? 'N' : '-',
	272	(CCR & F_Z) ? 'Z' : '-',
	273	(CCR & F_V) ? 'V' : '-',
	274	(CCR & F_C) ? 'C' : '-');
275	275	break;
276	276	case H8_R0:
277	277	case H8_R1:
r29404	r29405
554	554
555	555	void h8_device::write8(UINT32 adr, UINT8 data)
556	556	{
557		// logerror("W %06x %02x\n", adr & 0xffffff, data);
	557	// logerror("W %06x %02x\n", adr & 0xffffff, data);
558	558	icount--;
559	559	program->write_byte(adr, data);
560	560	}
r29404	r29405
567	567
568	568	void h8_device::write16(UINT32 adr, UINT16 data)
569	569	{
570		// logerror("W %06x %04x\n", adr & 0xfffffe, data);
	570	// logerror("W %06x %04x\n", adr & 0xfffffe, data);
571	571	icount--;
572	572	program->write_word(adr & ~1, data);
573	573	}
r29404	r29405
644	644	if(res & 0x100)
645	645	CCR \|= F_C;
646	646	return res;
647
	647
648	648	}
649	649
650	650	UINT8 h8_device::do_subx8(UINT8 v1, UINT8 v2)
r29404	r29405
662	662	if(res & 0x100)
663	663	CCR \|= F_C;
664	664	return res;
665
	665
666	666	}
667	667
668	668	UINT8 h8_device::do_inc8(UINT8 v1, UINT8 v2)
r29404	r29405
675	675	CCR \|= F_N;
676	676	if((v1^v2) & (v1^res) & 0x80)
677	677	CCR \|= F_V;
678		return res;
	678	return res;
679	679	}
680	680
681	681	UINT16 h8_device::do_inc16(UINT16 v1, UINT16 v2)
r29404	r29405
688	688	CCR \|= F_N;
689	689	if((v1^v2) & (v1^res) & 0x8000)
690	690	CCR \|= F_V;
691		return res;
	691	return res;
692	692	}
693	693
694	694	UINT32 h8_device::do_inc32(UINT32 v1, UINT32 v2)
r29404	r29405
701	701	CCR \|= F_N;
702	702	if((v1^v2) & (v1^res) & 0x80000000)
703	703	CCR \|= F_V;
704		return res;
	704	return res;
705	705	}
706	706
707	707	UINT8 h8_device::do_add8(UINT8 v1, UINT8 v2)
r29404	r29405
719	719	if(res & 0x100)
720	720	CCR \|= F_C;
721	721	return res;
722
	722
723	723	}
724	724
725	725	UINT16 h8_device::do_add16(UINT16 v1, UINT16 v2)
r29404	r29405
737	737	if(res & 0x10000)
738	738	CCR \|= F_C;
739	739	return res;
740
	740
741	741	}
742	742
743	743	UINT32 h8_device::do_add32(UINT32 v1, UINT32 v2)
r29404	r29405
754	754	CCR \|= F_V;
755	755	if(res & U64(0x100000000))
756	756	CCR \|= F_C;
757		return res;
	757	return res;
758	758	}
759	759
760	760	UINT8 h8_device::do_dec8(UINT8 v1, UINT8 v2)
r29404	r29405
767	767	CCR \|= F_N;
768	768	if((v1^v2) & (v1^res) & 0x80)
769	769	CCR \|= F_V;
770		return res;
	770	return res;
771	771	}
772	772
773	773	UINT16 h8_device::do_dec16(UINT16 v1, UINT16 v2)
r29404	r29405
780	780	CCR \|= F_N;
781	781	if((v1^v2) & (v1^res) & 0x8000)
782	782	CCR \|= F_V;
783		return res;
	783	return res;
784	784	}
785	785
786	786	UINT32 h8_device::do_dec32(UINT32 v1, UINT32 v2)
r29404	r29405
793	793	CCR \|= F_N;
794	794	if((v1^v2) & (v1^res) & 0x80000000)
795	795	CCR \|= F_V;
796		return res;
	796	return res;
797	797	}
798	798
799	799	UINT8 h8_device::do_sub8(UINT8 v1, UINT8 v2)
r29404	r29405
811	811	if(res & 0x100)
812	812	CCR \|= F_C;
813	813	return res;
814
	814
815	815	}
816	816
817	817	UINT16 h8_device::do_sub16(UINT16 v1, UINT16 v2)
r29404	r29405
829	829	if(res & 0x10000)
830	830	CCR \|= F_C;
831	831	return res;
832
	832
833	833	}
834	834
835	835	UINT32 h8_device::do_sub32(UINT32 v1, UINT32 v2)
r29404	r29405
846	846	CCR \|= F_V;
847	847	if(res & U64(0x100000000))
848	848	CCR \|= F_C;
849		return res;
	849	return res;
850	850	}
851	851
852	852	UINT8 h8_device::do_shal8(UINT8 v)
r29404	r29405
1017	1017	if(v & 0x40)
1018	1018	CCR \|= F_C;
1019	1019	if((v & 0xc0) == 0x40 \|\| (v & 0xc0) == 0x80 \|\|
1020		(v & 0x60) == 0x20 \|\| (v & 0x60) == 0x40)
	1020	(v & 0x60) == 0x20 \|\| (v & 0x60) == 0x40)
1021	1021	CCR \|= F_V;
1022	1022	v <<= 2;
1023	1023	if(!v)
r29404	r29405
1033	1033	if(v & 0x4000)
1034	1034	CCR \|= F_C;
1035	1035	if((v & 0xc000) == 0x4000 \|\| (v & 0xc000) == 0x8000 \|\|
1036		(v & 0x6000) == 0x2000 \|\| (v & 0x6000) == 0x4000)
	1036	(v & 0x6000) == 0x2000 \|\| (v & 0x6000) == 0x4000)
1037	1037	CCR \|= F_V;
1038	1038	v <<= 2;
1039	1039	if(!v)
r29404	r29405
1049	1049	if(v & 0x40000000)
1050	1050	CCR \|= F_C;
1051	1051	if((v & 0xc0000000) == 0x40000000 \|\| (v & 0xc0000000) == 0x80000000 \|\|
1052		(v & 0x60000000) == 0x20000000 \|\| (v & 0x60000000) == 0x40000000)
	1052	(v & 0x60000000) == 0x20000000 \|\| (v & 0x60000000) == 0x40000000)
1053	1053	CCR \|= F_V;
1054	1054	v <<= 2;
1055	1055	if(!v)

trunk/src/emu/cpu/h8/h8s2357.c
r29404	r29405
123	123	MCFG_H8H_TIMER8_CHANNEL_ADD("timer8_1", "intc", 68, 69, 70, "timer8_0", h8_timer8_channel_device::CHAIN_A, false, false)
124	124	MCFG_H8_TIMER16_ADD("timer16", 6, 0x00)
125	125	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:0", 4, 0x60, "intc", 32,
126		h8_timer16_channel_device::DIV_1,
127		h8_timer16_channel_device::DIV_4,
128		h8_timer16_channel_device::DIV_16,
129		h8_timer16_channel_device::DIV_64,
130		h8_timer16_channel_device::INPUT_A,
131		h8_timer16_channel_device::INPUT_B,
132		h8_timer16_channel_device::INPUT_C,
133		h8_timer16_channel_device::INPUT_D)
	126	h8_timer16_channel_device::DIV_1,
	127	h8_timer16_channel_device::DIV_4,
	128	h8_timer16_channel_device::DIV_16,
	129	h8_timer16_channel_device::DIV_64,
	130	h8_timer16_channel_device::INPUT_A,
	131	h8_timer16_channel_device::INPUT_B,
	132	h8_timer16_channel_device::INPUT_C,
	133	h8_timer16_channel_device::INPUT_D)
134	134	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:1", 2, 0x4c, "intc", 40,
135		h8_timer16_channel_device::DIV_1,
136		h8_timer16_channel_device::DIV_4,
137		h8_timer16_channel_device::DIV_16,
138		h8_timer16_channel_device::DIV_64,
139		h8_timer16_channel_device::INPUT_A,
140		h8_timer16_channel_device::INPUT_B,
141		h8_timer16_channel_device::DIV_256,
142		h8_timer16_channel_device::CHAIN)
	135	h8_timer16_channel_device::DIV_1,
	136	h8_timer16_channel_device::DIV_4,
	137	h8_timer16_channel_device::DIV_16,
	138	h8_timer16_channel_device::DIV_64,
	139	h8_timer16_channel_device::INPUT_A,
	140	h8_timer16_channel_device::INPUT_B,
	141	h8_timer16_channel_device::DIV_256,
	142	h8_timer16_channel_device::CHAIN)
143	143	MCFG_H8S_TIMER16_CHANNEL_SET_CHAIN("timer16:2")
144	144	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:2", 2, 0x4c, "intc", 44,
145		h8_timer16_channel_device::DIV_1,
146		h8_timer16_channel_device::DIV_4,
147		h8_timer16_channel_device::DIV_16,
148		h8_timer16_channel_device::DIV_64,
149		h8_timer16_channel_device::INPUT_A,
150		h8_timer16_channel_device::INPUT_B,
151		h8_timer16_channel_device::INPUT_C,
152		h8_timer16_channel_device::DIV_1024)
	145	h8_timer16_channel_device::DIV_1,
	146	h8_timer16_channel_device::DIV_4,
	147	h8_timer16_channel_device::DIV_16,
	148	h8_timer16_channel_device::DIV_64,
	149	h8_timer16_channel_device::INPUT_A,
	150	h8_timer16_channel_device::INPUT_B,
	151	h8_timer16_channel_device::INPUT_C,
	152	h8_timer16_channel_device::DIV_1024)
153	153	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:3", 4, 0x60, "intc", 48,
154		h8_timer16_channel_device::DIV_1,
155		h8_timer16_channel_device::DIV_4,
156		h8_timer16_channel_device::DIV_16,
157		h8_timer16_channel_device::DIV_64,
158		h8_timer16_channel_device::INPUT_A,
159		h8_timer16_channel_device::DIV_1024,
160		h8_timer16_channel_device::DIV_256,
161		h8_timer16_channel_device::DIV_4096)
	154	h8_timer16_channel_device::DIV_1,
	155	h8_timer16_channel_device::DIV_4,
	156	h8_timer16_channel_device::DIV_16,
	157	h8_timer16_channel_device::DIV_64,
	158	h8_timer16_channel_device::INPUT_A,
	159	h8_timer16_channel_device::DIV_1024,
	160	h8_timer16_channel_device::DIV_256,
	161	h8_timer16_channel_device::DIV_4096)
162	162	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:4", 2, 0x4c, "intc", 56,
163		h8_timer16_channel_device::DIV_1,
164		h8_timer16_channel_device::DIV_4,
165		h8_timer16_channel_device::DIV_16,
166		h8_timer16_channel_device::DIV_64,
167		h8_timer16_channel_device::INPUT_A,
168		h8_timer16_channel_device::INPUT_C,
169		h8_timer16_channel_device::DIV_1024,
170		h8_timer16_channel_device::CHAIN)
	163	h8_timer16_channel_device::DIV_1,
	164	h8_timer16_channel_device::DIV_4,
	165	h8_timer16_channel_device::DIV_16,
	166	h8_timer16_channel_device::DIV_64,
	167	h8_timer16_channel_device::INPUT_A,
	168	h8_timer16_channel_device::INPUT_C,
	169	h8_timer16_channel_device::DIV_1024,
	170	h8_timer16_channel_device::CHAIN)
171	171	MCFG_H8S_TIMER16_CHANNEL_SET_CHAIN("timer16:5")
172	172	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:5", 2, 0x4c, "intc", 60,
173		h8_timer16_channel_device::DIV_1,
174		h8_timer16_channel_device::DIV_4,
175		h8_timer16_channel_device::DIV_16,
176		h8_timer16_channel_device::DIV_64,
177		h8_timer16_channel_device::INPUT_A,
178		h8_timer16_channel_device::INPUT_C,
179		h8_timer16_channel_device::DIV_256,
180		h8_timer16_channel_device::INPUT_D)
	173	h8_timer16_channel_device::DIV_1,
	174	h8_timer16_channel_device::DIV_4,
	175	h8_timer16_channel_device::DIV_16,
	176	h8_timer16_channel_device::DIV_64,
	177	h8_timer16_channel_device::INPUT_A,
	178	h8_timer16_channel_device::INPUT_C,
	179	h8_timer16_channel_device::DIV_256,
	180	h8_timer16_channel_device::INPUT_D)
181	181	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
182	182	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
183	183	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)

trunk/src/emu/cpu/h8/h8_port.c
r29404	r29405
18	18
19	19	WRITE8_MEMBER(h8_port_device::ddr_w)
20	20	{
21		// logerror("%s: ddr_w %02x\n", tag(), data);
	21	// logerror("%s: ddr_w %02x\n", tag(), data);
22	22	ddr = data;
23	23	update_output();
24	24	}
25	25
26	26	WRITE8_MEMBER(h8_port_device::dr_w)
27	27	{
28		// logerror("%s: dr_w %02x\n", tag(), data);
	28	// logerror("%s: dr_w %02x\n", tag(), data);
29	29	dr = data;
30	30	update_output();
31	31	}
32	32
33	33	READ8_MEMBER(h8_port_device::dr_r)
34	34	{
35		// logerror("%s: dr_r %02x\n", tag(), (dr \| mask) & 0xff);
	35	// logerror("%s: dr_r %02x\n", tag(), (dr \| mask) & 0xff);
36	36	return dr \| mask;
37	37	}
38	38
r29404	r29405
41	41	UINT8 res = mask \| (dr & ddr);
42	42	if((ddr & ~mask) != UINT8(~mask))
43	43	res \|= io->read_word(address) & ~ddr;
44
45		// logerror("%s: port_r %02x (%02x %02x)\n", tag(), res, ddr & ~mask, UINT8(~mask));
	44
	45	// logerror("%s: port_r %02x (%02x %02x)\n", tag(), res, ddr & ~mask, UINT8(~mask));
46	46	return res;
47	47	}
48	48

trunk/src/emu/cpu/h8/h8s2655.c
r29404	r29405
96	96	MCFG_H8H_TIMER8_CHANNEL_ADD("timer8_1", "intc", 68, 69, 70, "timer8_0", h8_timer8_channel_device::CHAIN_A, false, false)
97	97	MCFG_H8_TIMER16_ADD("timer16", 6, 0x00)
98	98	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:0", 4, 0x60, "intc", 32,
99		h8_timer16_channel_device::DIV_1,
100		h8_timer16_channel_device::DIV_4,
101		h8_timer16_channel_device::DIV_16,
102		h8_timer16_channel_device::DIV_64,
103		h8_timer16_channel_device::INPUT_A,
104		h8_timer16_channel_device::INPUT_B,
105		h8_timer16_channel_device::INPUT_C,
106		h8_timer16_channel_device::INPUT_D)
	99	h8_timer16_channel_device::DIV_1,
	100	h8_timer16_channel_device::DIV_4,
	101	h8_timer16_channel_device::DIV_16,
	102	h8_timer16_channel_device::DIV_64,
	103	h8_timer16_channel_device::INPUT_A,
	104	h8_timer16_channel_device::INPUT_B,
	105	h8_timer16_channel_device::INPUT_C,
	106	h8_timer16_channel_device::INPUT_D)
107	107	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:1", 2, 0x4c, "intc", 40,
108		h8_timer16_channel_device::DIV_1,
109		h8_timer16_channel_device::DIV_4,
110		h8_timer16_channel_device::DIV_16,
111		h8_timer16_channel_device::DIV_64,
112		h8_timer16_channel_device::INPUT_A,
113		h8_timer16_channel_device::INPUT_B,
114		h8_timer16_channel_device::DIV_256,
115		h8_timer16_channel_device::CHAIN)
	108	h8_timer16_channel_device::DIV_1,
	109	h8_timer16_channel_device::DIV_4,
	110	h8_timer16_channel_device::DIV_16,
	111	h8_timer16_channel_device::DIV_64,
	112	h8_timer16_channel_device::INPUT_A,
	113	h8_timer16_channel_device::INPUT_B,
	114	h8_timer16_channel_device::DIV_256,
	115	h8_timer16_channel_device::CHAIN)
116	116	MCFG_H8S_TIMER16_CHANNEL_SET_CHAIN("timer16:2")
117	117	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:2", 2, 0x4c, "intc", 44,
118		h8_timer16_channel_device::DIV_1,
119		h8_timer16_channel_device::DIV_4,
120		h8_timer16_channel_device::DIV_16,
121		h8_timer16_channel_device::DIV_64,
122		h8_timer16_channel_device::INPUT_A,
123		h8_timer16_channel_device::INPUT_B,
124		h8_timer16_channel_device::INPUT_C,
125		h8_timer16_channel_device::DIV_1024)
	118	h8_timer16_channel_device::DIV_1,
	119	h8_timer16_channel_device::DIV_4,
	120	h8_timer16_channel_device::DIV_16,
	121	h8_timer16_channel_device::DIV_64,
	122	h8_timer16_channel_device::INPUT_A,
	123	h8_timer16_channel_device::INPUT_B,
	124	h8_timer16_channel_device::INPUT_C,
	125	h8_timer16_channel_device::DIV_1024)
126	126	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:3", 4, 0x60, "intc", 48,
127		h8_timer16_channel_device::DIV_1,
128		h8_timer16_channel_device::DIV_4,
129		h8_timer16_channel_device::DIV_16,
130		h8_timer16_channel_device::DIV_64,
131		h8_timer16_channel_device::INPUT_A,
132		h8_timer16_channel_device::DIV_1024,
133		h8_timer16_channel_device::DIV_256,
134		h8_timer16_channel_device::DIV_4096)
	127	h8_timer16_channel_device::DIV_1,
	128	h8_timer16_channel_device::DIV_4,
	129	h8_timer16_channel_device::DIV_16,
	130	h8_timer16_channel_device::DIV_64,
	131	h8_timer16_channel_device::INPUT_A,
	132	h8_timer16_channel_device::DIV_1024,
	133	h8_timer16_channel_device::DIV_256,
	134	h8_timer16_channel_device::DIV_4096)
135	135	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:4", 2, 0x4c, "intc", 56,
136		h8_timer16_channel_device::DIV_1,
137		h8_timer16_channel_device::DIV_4,
138		h8_timer16_channel_device::DIV_16,
139		h8_timer16_channel_device::DIV_64,
140		h8_timer16_channel_device::INPUT_A,
141		h8_timer16_channel_device::INPUT_C,
142		h8_timer16_channel_device::DIV_1024,
143		h8_timer16_channel_device::CHAIN)
	136	h8_timer16_channel_device::DIV_1,
	137	h8_timer16_channel_device::DIV_4,
	138	h8_timer16_channel_device::DIV_16,
	139	h8_timer16_channel_device::DIV_64,
	140	h8_timer16_channel_device::INPUT_A,
	141	h8_timer16_channel_device::INPUT_C,
	142	h8_timer16_channel_device::DIV_1024,
	143	h8_timer16_channel_device::CHAIN)
144	144	MCFG_H8S_TIMER16_CHANNEL_SET_CHAIN("timer16:5")
145	145	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:5", 2, 0x4c, "intc", 60,
146		h8_timer16_channel_device::DIV_1,
147		h8_timer16_channel_device::DIV_4,
148		h8_timer16_channel_device::DIV_16,
149		h8_timer16_channel_device::DIV_64,
150		h8_timer16_channel_device::INPUT_A,
151		h8_timer16_channel_device::INPUT_C,
152		h8_timer16_channel_device::DIV_256,
153		h8_timer16_channel_device::INPUT_D)
	146	h8_timer16_channel_device::DIV_1,
	147	h8_timer16_channel_device::DIV_4,
	148	h8_timer16_channel_device::DIV_16,
	149	h8_timer16_channel_device::DIV_64,
	150	h8_timer16_channel_device::INPUT_A,
	151	h8_timer16_channel_device::INPUT_C,
	152	h8_timer16_channel_device::DIV_256,
	153	h8_timer16_channel_device::INPUT_D)
154	154	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
155	155	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
156	156	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)

trunk/src/emu/cpu/h8/h8.h
r29404	r29405
499	499	H8_E6,
500	500	H8_E7,
501	501	H8_CCR,
502		H8_EXR,
	502	H8_EXR,
503	503	};
504	504
505	505	#endif

trunk/src/emu/cpu/h8/h8s2357.h
r29404	r29405
65	65	h8s2357_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
66	66
67	67	DECLARE_READ8_MEMBER(syscr_r);
68		DECLARE_WRITE8_MEMBER(syscr_w);
	68	DECLARE_WRITE8_MEMBER(syscr_w);
69	69
70	70	protected:
71	71	required_device<h8s_intc_device> intc;

trunk/src/emu/cpu/h8/h8_port.h
r29404	r29405
42	42
43	43	#include "h8.h"
44	44
45		#define MCFG_H8_PORT_ADD( _tag, address, ddr, mask ) \
	45	#define MCFG_H8_PORT_ADD( _tag, address, ddr, mask ) \
46	46	MCFG_DEVICE_ADD( _tag, H8_PORT, 0 ) \
47	47	downcast<h8_port_device *>(device)->set_info(address, ddr, mask);
48	48

trunk/src/emu/cpu/h8/h8s2655.h
r29404	r29405
57	57	h8s2655_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
58	58
59	59	DECLARE_READ8_MEMBER(syscr_r);
60		DECLARE_WRITE8_MEMBER(syscr_w);
	60	DECLARE_WRITE8_MEMBER(syscr_w);
61	61
62	62	protected:
63	63	required_device<h8s_intc_device> intc;

trunk/src/emu/cpu/h8/h8_intc.c
r29404	r29405
280	280	const int h8h_intc_device::vector_to_slot[64] = {
281	281	-1, -1, -1, -1, -1, -1, -1, -1, // NMI at 7
282	282	-1, -1, -1, -1, 0, 1, 2, 2, // IRQ 0-3
283		3, 3, 3, 3, 4, 4, 4, 4, // IRQ 4-5, (reservedx2), WOVI, CMI, (reserved), ADI
284		5, 5, 5, 5, 6, 6, 6, 6, // IMIA0, IMIB0, OVI0, (reserved), IMIA1, IMIB1, OVI1, (reserved)
285		7, 7, 7, 7, 8, 8, 8, 8, // IMIA2, IMIB2, OVI2, (reserved), CMIA0, CMIB0, CMIx1, TOVI0/1
286		9, 9, 9, 9, 10, 10, 10, 10, // CMIA2, CMIB2, CMIx3, TOVI2/3, DEND0A, DEND0B, DEND1A, DEND1B
	283	3, 3, 3, 3, 4, 4, 4, 4, // IRQ 4-5, (reservedx2), WOVI, CMI, (reserved), ADI
	284	5, 5, 5, 5, 6, 6, 6, 6, // IMIA0, IMIB0, OVI0, (reserved), IMIA1, IMIB1, OVI1, (reserved)
	285	7, 7, 7, 7, 8, 8, 8, 8, // IMIA2, IMIB2, OVI2, (reserved), CMIA0, CMIB0, CMIx1, TOVI0/1
	286	9, 9, 9, 9, 10, 10, 10, 10, // CMIA2, CMIB2, CMIx3, TOVI2/3, DEND0A, DEND0B, DEND1A, DEND1B
287	287	11, 11, 11, 11, 12, 12, 12, 12, // (reservedx4), ERI0, RXI0, TXI0, TEI0
288	288	13, 13, 13, 13, 14, 14, 14, 14 // ERI1, RXI1, TXI1, TEI1, ERI2, RXI2, TXI2, TEI2
289	289	};
r29404	r29405
342	342	const int h8s_intc_device::vector_to_slot[92] = {
343	343	-1, -1, -1, -1, -1, -1, -1, -1, // NMI at 7
344	344	-1, -1, -1, -1, -1, -1, -1, -1,
345		0, 1, 2, 2, 3, 3, 4, 4, // IRQ 0-7
346		5, 6, 7, 8, 9, 9, 9, 9, // SWDTEND, WOVI, CMI, (reserved), ADI
	345	0, 1, 2, 2, 3, 3, 4, 4, // IRQ 0-7
	346	5, 6, 7, 8, 9, 9, 9, 9, // SWDTEND, WOVI, CMI, (reserved), ADI
347	347	10, 10, 10, 10, 10, 10, 10, 10, // TGI0A, TGI0B, TGI0C, TGI0D, TGI0V
348	348	11, 11, 11, 11, 12, 12, 12, 12, // TGI1A, TGI1B, TGI1V, TGI1U, TGI2A, TGI2B, TGI2V, TGI2U
349	349	13, 13, 13, 13, 13, 13, 13, 13, // TGI3A, TGI3B, TGI3C, TGI3D, TGI3V

trunk/src/emu/cpu/h8/h8.lst
r29404	r29405
937	937	}
938	938	r8_w(IR[0], do_add8(TMP1, TMP2));
939	939	prefetch();
940
	940
941	941	0f80 ff88 0 mov.l r32h r32l h
942	942	TMP1 = r32_r(IR[0] >> 4);
943	943	set_nzv32(TMP1);
r29404	r29405
1303	1303	}
1304	1304	r8_w(IR[0], do_add8(TMP1, TMP2));
1305	1305	prefetch();
1306
	1306
1307	1307	1f80 ff88 0 cmp.l r32h r32l h
1308	1308	do_sub32(r32_r(IR[0]), r32_r(IR[0] >> 4));
1309	1309	prefetch();
r29404	r29405
2206	2206	7000 ff80 0 bset imm3 r8l
2207	2207	TMP1 = r8_r(IR[0]);
2208	2208	bset IR[0] >> 4
2209		r8_w(IR[0], TMP1);
	2209	r8_w(IR[0], TMP1);
2210	2210	prefetch();
2211	2211
2212	2212	7100 ff80 0 bnot imm3 r8l
2213	2213	TMP1 = r8_r(IR[0]);
2214	2214	bnot IR[0] >> 4
2215		r8_w(IR[0], TMP1);
	2215	r8_w(IR[0], TMP1);
2216	2216	prefetch();
2217	2217
2218	2218	7200 ff80 0 bclr imm3 r8l
2219	2219	TMP1 = r8_r(IR[0]);
2220	2220	bclr IR[0] >> 4
2221		r8_w(IR[0], TMP1);
	2221	r8_w(IR[0], TMP1);
2222	2222	prefetch();
2223	2223
2224	2224	7300 ff80 0 btst imm3 r8l

trunk/src/emu/cpu/h8/h83337.c
r29404	r29405
95	95	AM_RANGE(0xff90, 0xff91) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
96	96	AM_RANGE(0xff90, 0xff91) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
97	97	AM_RANGE(0xff92, 0xff93) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tcnt_r, tcnt_w )
98		// AM_RANGE(0xff94, 0xff95) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, ocr_r, ocr_w )
	98	// AM_RANGE(0xff94, 0xff95) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, ocr_r, ocr_w )
99	99	AM_RANGE(0xff96, 0xff97) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
100		// AM_RANGE(0xff96, 0xff97) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tocr_r, tocr_w, 0x00ff)
	100	// AM_RANGE(0xff96, 0xff97) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tocr_r, tocr_w, 0x00ff)
101	101	AM_RANGE(0xff98, 0xff9f) AM_DEVREAD( "timer16:0", h8_timer16_channel_device, tgr_r )
102	102
103	103	AM_RANGE(0xffac, 0xffad) AM_DEVREADWRITE8("port1", h8_port_device, pcr_r, pcr_w, 0xff00)

trunk/src/emu/cpu/h8/h8_intc.h
r29404	r29405
42	42
43	43	#include "h8.h"
44	44
45		#define MCFG_H8_INTC_ADD( _tag ) \
	45	#define MCFG_H8_INTC_ADD( _tag ) \
46	46	MCFG_DEVICE_ADD( _tag, H8_INTC, 0 )
47	47
48		#define MCFG_H8H_INTC_ADD( _tag ) \
	48	#define MCFG_H8H_INTC_ADD( _tag ) \
49	49	MCFG_DEVICE_ADD( _tag, H8H_INTC, 0 )
50	50
51		#define MCFG_H8S_INTC_ADD( _tag ) \
	51	#define MCFG_H8S_INTC_ADD( _tag ) \
52	52	MCFG_DEVICE_ADD( _tag, H8S_INTC, 0 )
53	53
54	54
r29404	r29405
100	100	h8h_intc_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
101	101
102	102	DECLARE_READ8_MEMBER(isr_r);
103		DECLARE_WRITE8_MEMBER(isr_w);
	103	DECLARE_WRITE8_MEMBER(isr_w);
104	104	DECLARE_READ8_MEMBER(icr_r);
105	105	DECLARE_WRITE8_MEMBER(icr_w);
106	106	DECLARE_READ8_MEMBER(icrc_r);

trunk/src/emu/cpu/h8/h83337.h
r29404	r29405
63	63	h83337_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
64	64
65	65	DECLARE_READ8_MEMBER(wscr_r);
66		DECLARE_WRITE8_MEMBER(wscr_w);
	66	DECLARE_WRITE8_MEMBER(wscr_w);
67	67	DECLARE_READ8_MEMBER(stcr_r);
68		DECLARE_WRITE8_MEMBER(stcr_w);
	68	DECLARE_WRITE8_MEMBER(stcr_w);
69	69	DECLARE_READ8_MEMBER(syscr_r);
70		DECLARE_WRITE8_MEMBER(syscr_w);
	70	DECLARE_WRITE8_MEMBER(syscr_w);
71	71	DECLARE_READ8_MEMBER(mdcr_r);
72		DECLARE_WRITE8_MEMBER(mdcr_w);
	72	DECLARE_WRITE8_MEMBER(mdcr_w);
73	73
74	74	protected:
75	75	required_device<h8_intc_device> intc;

trunk/src/emu/cpu/h8/h8s2320.c
r29404	r29405
145	145	MCFG_H8H_TIMER8_CHANNEL_ADD("timer8_1", "intc", 68, 69, 70, "timer8_0", h8_timer8_channel_device::CHAIN_A, false, false)
146	146	MCFG_H8_TIMER16_ADD("timer16", 6, 0x00)
147	147	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:0", 4, 0x60, "intc", 32,
148		h8_timer16_channel_device::DIV_1,
149		h8_timer16_channel_device::DIV_4,
150		h8_timer16_channel_device::DIV_16,
151		h8_timer16_channel_device::DIV_64,
152		h8_timer16_channel_device::INPUT_A,
153		h8_timer16_channel_device::INPUT_B,
154		h8_timer16_channel_device::INPUT_C,
155		h8_timer16_channel_device::INPUT_D)
	148	h8_timer16_channel_device::DIV_1,
	149	h8_timer16_channel_device::DIV_4,
	150	h8_timer16_channel_device::DIV_16,
	151	h8_timer16_channel_device::DIV_64,
	152	h8_timer16_channel_device::INPUT_A,
	153	h8_timer16_channel_device::INPUT_B,
	154	h8_timer16_channel_device::INPUT_C,
	155	h8_timer16_channel_device::INPUT_D)
156	156	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:1", 2, 0x4c, "intc", 40,
157		h8_timer16_channel_device::DIV_1,
158		h8_timer16_channel_device::DIV_4,
159		h8_timer16_channel_device::DIV_16,
160		h8_timer16_channel_device::DIV_64,
161		h8_timer16_channel_device::INPUT_A,
162		h8_timer16_channel_device::INPUT_B,
163		h8_timer16_channel_device::DIV_256,
164		h8_timer16_channel_device::CHAIN)
	157	h8_timer16_channel_device::DIV_1,
	158	h8_timer16_channel_device::DIV_4,
	159	h8_timer16_channel_device::DIV_16,
	160	h8_timer16_channel_device::DIV_64,
	161	h8_timer16_channel_device::INPUT_A,
	162	h8_timer16_channel_device::INPUT_B,
	163	h8_timer16_channel_device::DIV_256,
	164	h8_timer16_channel_device::CHAIN)
165	165	MCFG_H8S_TIMER16_CHANNEL_SET_CHAIN("timer16:2")
166	166	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:2", 2, 0x4c, "intc", 44,
167		h8_timer16_channel_device::DIV_1,
168		h8_timer16_channel_device::DIV_4,
169		h8_timer16_channel_device::DIV_16,
170		h8_timer16_channel_device::DIV_64,
171		h8_timer16_channel_device::INPUT_A,
172		h8_timer16_channel_device::INPUT_B,
173		h8_timer16_channel_device::INPUT_C,
174		h8_timer16_channel_device::DIV_1024)
	167	h8_timer16_channel_device::DIV_1,
	168	h8_timer16_channel_device::DIV_4,
	169	h8_timer16_channel_device::DIV_16,
	170	h8_timer16_channel_device::DIV_64,
	171	h8_timer16_channel_device::INPUT_A,
	172	h8_timer16_channel_device::INPUT_B,
	173	h8_timer16_channel_device::INPUT_C,
	174	h8_timer16_channel_device::DIV_1024)
175	175	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:3", 4, 0x60, "intc", 48,
176		h8_timer16_channel_device::DIV_1,
177		h8_timer16_channel_device::DIV_4,
178		h8_timer16_channel_device::DIV_16,
179		h8_timer16_channel_device::DIV_64,
180		h8_timer16_channel_device::INPUT_A,
181		h8_timer16_channel_device::DIV_1024,
182		h8_timer16_channel_device::DIV_256,
183		h8_timer16_channel_device::DIV_4096)
	176	h8_timer16_channel_device::DIV_1,
	177	h8_timer16_channel_device::DIV_4,
	178	h8_timer16_channel_device::DIV_16,
	179	h8_timer16_channel_device::DIV_64,
	180	h8_timer16_channel_device::INPUT_A,
	181	h8_timer16_channel_device::DIV_1024,
	182	h8_timer16_channel_device::DIV_256,
	183	h8_timer16_channel_device::DIV_4096)
184	184	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:4", 2, 0x4c, "intc", 56,
185		h8_timer16_channel_device::DIV_1,
186		h8_timer16_channel_device::DIV_4,
187		h8_timer16_channel_device::DIV_16,
188		h8_timer16_channel_device::DIV_64,
189		h8_timer16_channel_device::INPUT_A,
190		h8_timer16_channel_device::INPUT_C,
191		h8_timer16_channel_device::DIV_1024,
192		h8_timer16_channel_device::CHAIN)
	185	h8_timer16_channel_device::DIV_1,
	186	h8_timer16_channel_device::DIV_4,
	187	h8_timer16_channel_device::DIV_16,
	188	h8_timer16_channel_device::DIV_64,
	189	h8_timer16_channel_device::INPUT_A,
	190	h8_timer16_channel_device::INPUT_C,
	191	h8_timer16_channel_device::DIV_1024,
	192	h8_timer16_channel_device::CHAIN)
193	193	MCFG_H8S_TIMER16_CHANNEL_SET_CHAIN("timer16:5")
194	194	MCFG_H8S_TIMER16_CHANNEL_ADD("timer16:5", 2, 0x4c, "intc", 60,
195		h8_timer16_channel_device::DIV_1,
196		h8_timer16_channel_device::DIV_4,
197		h8_timer16_channel_device::DIV_16,
198		h8_timer16_channel_device::DIV_64,
199		h8_timer16_channel_device::INPUT_A,
200		h8_timer16_channel_device::INPUT_C,
201		h8_timer16_channel_device::DIV_256,
202		h8_timer16_channel_device::INPUT_D)
	195	h8_timer16_channel_device::DIV_1,
	196	h8_timer16_channel_device::DIV_4,
	197	h8_timer16_channel_device::DIV_16,
	198	h8_timer16_channel_device::DIV_64,
	199	h8_timer16_channel_device::INPUT_A,
	200	h8_timer16_channel_device::INPUT_C,
	201	h8_timer16_channel_device::DIV_256,
	202	h8_timer16_channel_device::INPUT_D)
203	203	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
204	204	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
205	205	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)

trunk/src/emu/cpu/se3208/se3208.c
r29404	r29405
1830	1830	extern CPU_DISASSEMBLE( se3208 );
1831	1831	return CPU_DISASSEMBLE_NAME(se3208)(this, buffer, pc, oprom, opram, options);
1832	1832	}
1833
1834

trunk/src/emu/cpu/se3208/se3208.h
r29404	r29405
165	165
166	166
167	167	extern const device_type SE3208;
168

trunk/src/emu/cpu/sh2/sh2comn.c
r29404	r29405
538	538	{
539	539	case 0x00:
540	540	//if(mem_mask == 0xff)
541		// printf("%c",data & 0xff);
	541	// printf("%c",data & 0xff);
542	542	break;
543	543	case 0x01:
544	544	//printf("%08x %02x %02x\n",mem_mask,offset,data);

trunk/src/emu/cpu/mn10200/mn10200.h
r29404	r29405
43	43	MN10200_IRQ1,
44	44	MN10200_IRQ2,
45	45	MN10200_IRQ3,
46
	46
47	47	MN10200_MAX_EXT_IRQ
48	48	};
49	49
r29404	r29405
155	155	UINT8 ctrlh;
156	156	UINT8 buf;
157	157	} m_serial[2];
158
	158
159	159	// ports
160	160	UINT8 m_pplul;
161	161	UINT8 m_ppluh;
r29404	r29405
167	167	UINT8 out;
168	168	UINT8 dir;
169	169	} m_port[4];
170
	170
171	171	// internal read/write
172	172	inline UINT8 read_arg8(UINT32 address) { return m_program->read_byte(address); }
173	173	inline UINT16 read_arg16(UINT32 address) { return m_program->read_byte(address) \| m_program->read_byte(address + 1) << 8; }

trunk/src/emu/cpu/mn10200/mn10200.c
r29404	r29405
74	74	save_item(NAME(m_icrl));
75	75	save_item(NAME(m_icrh));
76	76	save_item(NAME(m_possible_irq));
77
	77
78	78	// timers
79	79	m_sysclock_base = attotime::from_hz(unscaled_clock() / 2);
80	80
r29404	r29405
94	94	save_item(NAME(m_simple_timer[i].base), i);
95	95	save_item(NAME(m_simple_timer[i].cur), i);
96	96	}
97
	97
98	98	for (int i = 0; i < MN10200_NUM_PRESCALERS; i++)
99	99	{
100	100	m_prescaler[i].mode = 0;
r29404	r29405
105	105	save_item(NAME(m_prescaler[i].base), i);
106	106	save_item(NAME(m_prescaler[i].cur), i);
107	107	}
108
	108
109	109	// dma
110	110	for (int i = 0; i < 8; i++)
111	111	{
r29404	r29405
123	123	save_item(NAME(m_dma[i].ctrlh), i);
124	124	save_item(NAME(m_dma[i].irq), i);
125	125	}
126
	126
127	127	// serial
128	128	for (int i = 0; i < 2; i++)
129	129	{
r29404	r29405
135	135	save_item(NAME(m_serial[i].ctrlh), i);
136	136	save_item(NAME(m_serial[i].buf), i);
137	137	}
138
	138
139	139	// ports
140	140	m_p4 = 0xf;
141	141
r29404	r29405
211	211	{
212	212	change_pc(0x80000);
213	213	m_psw = 0;
214
	214
215	215	// note: officially, these registers are reset to 'undefined'
216	216	memset(m_d, 0, sizeof(m_d));
217	217	memset(m_a, 0, sizeof(m_a));
218	218	m_mdr = 0;
219
	219
220	220	// reset internal peripherals
221	221	m_nmicr = 0;
222	222	m_iagr = 0;
223	223	write_mem16(0xfc00, 0x8000);
224	224	write_mem16(0xfc02, 0x0737);
225
	225
226	226	// need to clear them twice since some rely on the value of others
227	227	for (int i = 0; i < 2; i++)
228	228	for (int address = 0xfc04; address < 0x10000; address++)
r29404	r29405
250	250	{
251	251	if (!m_nmicr && !(m_psw & FLAG_IE))
252	252	return;
253
	253
254	254	int level = m_psw >> 8 & 7;
255	255	int group = 0;
256
	256
257	257	// find highest valid level
258	258	for (int i = 1; i < 11; i++)
259	259	{
r29404	r29405
263	263	group = i;
264	264	}
265	265	}
266
	266
267	267	// take interrupt
268	268	if (m_nmicr && group)
269	269	take_irq(level, 0);
r29404	r29405
271	271	take_irq(0, 0);
272	272	else if (group)
273	273	take_irq(level, group);
274
	274
275	275	return;
276	276	}
277	277
r29404	r29405
283	283	if ((m_p4 >> i & 1) == (m_extmdl >> (i * 2) & 3))
284	284	m_icrl[8] \|= (1 << (4 + i));
285	285	}
286
	286
287	287	m_possible_irq = true;
288	288	}
289	289
r29404	r29405
295	295	int pin = state ? 0 : 1;
296	296	int old = m_p4 >> irqnum & 1;
297	297	bool active = false;
298
	298
299	299	switch (m_extmdl >> (irqnum * 2) & 3)
300	300	{
301	301	// 'L' level
302	302	case 0:
303	303	active = (pin == 0);
304	304	break;
305
	305
306	306	// 'H' level
307	307	case 1:
308	308	active = (pin == 1);
309	309	break;
310
	310
311	311	// falling edge
312	312	case 2:
313	313	active = (pin == 0 && old == 1);
314	314	break;
315
	315
316	316	// rising edge
317	317	case 3:
318	318	active = (pin == 1 && old == 0);
319	319	break;
320	320	}
321
	321
322	322	m_p4 &= ~(1 << irqnum);
323	323	m_p4 \|= pin << irqnum;
324
	324
325	325	if (active)
326	326	{
327	327	m_icrl[8] \|= (1 << (4 + irqnum));
r29404	r29405
335	335	int mn10200_device::timer_tick_simple(int tmr)
336	336	{
337	337	int next = tmr + 1;
338
	338
339	339	// is it a cascaded timer, and enabled?
340	340	if (next < MN10200_NUM_TIMERS_8BIT && m_simple_timer[next].mode & 0x83 && (m_simple_timer[next].mode & 0x83) == 0x81)
341	341	{
r29404	r29405
391	391	TIMER_CALLBACK_MEMBER( mn10200_device::simple_timer_cb )
392	392	{
393	393	int tmr = param;
394
	394
395	395	// handle our expiring and also tick our cascaded children
396	396	if (timer_tick_simple(tmr) == 2)
397	397	m_simple_timer[tmr].cur = 0xff; // cascaded and no underflow occured
398	398	else
399	399	m_simple_timer[tmr].cur = m_simple_timer[tmr].base;
400
	400
401	401	// refresh this timer
402	402	refresh_timer(tmr);
403	403	}
r29404	r29405
492	492	{
493	493	while (m_cycles > 0)
494	494	{
495
496	495	// internal peripheral, external pin, or prev instruction may have changed irq state
497	496	while (m_possible_irq)
498	497	{
r29404	r29405
780	779
781	780	switch (op)
782	781	{
783
784	782	// jmp (an)
785	783	case 0x00: case 0x04: case 0x08: case 0x0c:
786	784	m_cycles -= 1;
r29404	r29405
868	866
869	867	switch (op & 0xc0)
870	868	{
871
872	869	// mov (di, an), am
873	870	case 0x00:
874	871	m_cycles -= 1;
r29404	r29405
903	900
904	901	switch (op & 0xf0)
905	902	{
906
907	903	// add dm, an
908	904	case 0x00:
909	905	m_a[op&3] = do_add(m_a[op&3], m_d[op>>2&3], 0);
r29404	r29405
999	995
1000	996	switch (op)
1001	997	{
1002
1003	998	// and dn, dm
1004	999	case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
1005	1000	case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
r29404	r29405
1180	1175
1181	1176	switch (op)
1182	1177	{
1183
1184	1178	// mov dm, (d24, an)
1185	1179	case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
1186	1180	case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
r29404	r29405
1346	1340
1347	1341	switch (op)
1348	1342	{
1349
1350	1343	// and imm8, dn
1351	1344	case 0x00: case 0x01: case 0x02: case 0x03:
1352	1345	test_nz16(m_d[op&3] &= 0xff0000 \| read_arg8(m_pc));
r29404	r29405
1507	1500
1508	1501	switch (op)
1509	1502	{
1510
1511	1503	// and imm16, dn
1512	1504	case 0x00: case 0x01: case 0x02: case 0x03:
1513	1505	test_nz16(m_d[op&3] &= 0xff0000 \| read_arg16(m_pc));
r29404	r29405
2164	2156	return (m_io->read_byte(MN10200_PORT2) & 0x0f) \| m_port[2].dir;
2165	2157	case 0x3d3:
2166	2158	return (m_io->read_byte(MN10200_PORT3) & 0x1f) \| m_port[3].dir;
2167
	2159
2168	2160	// directions (0=input, 1=output)
2169	2161	case 0x3e0:
2170	2162	return m_port[0].dir;
r29404	r29405
2184	2176	log_event("MN102", "internal_r %04x (%03x)", offset+0xfc00, adr);
2185	2177	break;
2186	2178	}
2187
	2179
2188	2180	return 0;
2189	2181	}

trunk/src/emu/cpu/v810/v810.c
r29404	r29405
1392	1392	m_irq_state = state;
1393	1393	m_irq_line = irqline;
1394	1394	}
1395

trunk/src/emu/cpu/tms32025/tms32025.c
r29404	r29405
2279	2279
2280	2280	return 1;
2281	2281	}
2282

trunk/src/emu/cpu/tms32025/tms32025.h
r29404	r29405
88	88
89	89	// device_memory_interface overrides
90	90	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) ); }
91		virtual bool memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value);
92		virtual bool memory_write(address_spacenum spacenum, offs_t offset, int size, UINT64 value);
	91	virtual bool memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value);
	92	virtual bool memory_write(address_spacenum spacenum, offs_t offset, int size, UINT64 value);
93	93	virtual bool memory_readop(offs_t offset, int size, UINT64 &value);
94	94
95	95	// device_state_interface overrides

trunk/src/emu/cpu/sharc/sharc.c
r29404	r29405
659	659	{
660	660	m_irq_active &= ~(1 << (8-irqline));
661	661	}
662		}
	662	}
663	663	else if (irqline >= SHARC_INPUT_FLAG0 && irqline <= SHARC_INPUT_FLAG3)
664		{
665		set_flag_input(irqline - SHARC_INPUT_FLAG0, state);
666		}
	664	{
	665	set_flag_input(irqline - SHARC_INPUT_FLAG0, state);
	666	}
667	667	}
668	668
669	669	void adsp21062_device::set_flag_input(int flag_num, int state)
r29404	r29405
917	917
918	918	return false;
919	919	}
920

trunk/src/emu/cpu/sharc/sharc.h
r29404	r29405
212	212	UINT32 m_astat_old_old;
213	213	UINT32 m_astat_old_old_old;
214	214
215		UINT16 m_internal_ram[2 * 0x10000]; // 2x 128KB
	215	UINT16 m_internal_ram[2 * 0x10000]; // 2x 128KB
216	216
217	217	inline void CHANGE_PC(UINT32 newpc);
218	218	inline void CHANGE_PC_DELAYED(UINT32 newpc);

trunk/src/emu/cpu/pdp1/tx0.h
r29404	r29405
96	96	unsigned int m_run; /* processor is running */
97	97	unsigned int m_rim; /* processor is in read-in mode */
98	98	unsigned int m_cycle; /* 0 -> fetch */
99		/* 1 -> execute (except for taken branches) */
100		/* 2 -> extra execute cycle for SXA and ADO */
	99	/* 1 -> execute (except for taken branches) */
	100	/* 2 -> extra execute cycle for SXA and ADO */
101	101
102	102	unsigned int m_ioh; /* i-o halt: processor is executing an Input-Output Transfer wait */
103	103	unsigned int m_ios; /* i-o synchronizer: set on i-o operation completion */

trunk/src/emu/cpu/pdp1/pdp1.c
r29404	r29405
1813	1813	if (m_io_sc_callback)
1814	1814	(*m_io_sc_callback)(this);
1815	1815	}
1816

trunk/src/emu/cpu/pdp1/pdp1.h
r29404	r29405
73	73
74	74
75	75	class pdp1_device : public cpu_device
76		, public pdp1_reset_param_t
	76	, public pdp1_reset_param_t
77	77	{
78	78	public:
79	79	// construction/destruction

trunk/src/emu/cpu/pdp1/tx0.c
r29404	r29405
1068	1068	extern CPU_DISASSEMBLE( tx0_64kw );
1069	1069	return CPU_DISASSEMBLE_NAME(tx0_64kw)(this, buffer, pc, oprom, opram, options);
1070	1070	}
1071

trunk/src/emu/cpu/tms7000/tms7000.c
r29404	r29405
572	572	{
573	573	return m_rf[ offset ];
574	574	}
575

trunk/src/emu/cpu/z80/z80.c
r29404	r29405
639	639	***************************************************************/
640	640	inline void z80_device::retn()
641	641	{
642		LOG(("Z80 '%s' RETN m_iff1:%d m_iff2:%d\n",
	642	LOG(("Z80 '%s' RETN m_iff1:%d m_iff2:%d\n",
643	643	tag(), m_iff1, m_iff2));
644	644	pop(m_pc);
645	645	WZ = PC;
r29404	r29405
2649	2649	OP(ed,55) { retn(); } /* RETN */
2650	2650	OP(ed,56) { m_im = 1; } /* IM 1 */
2651	2651	OP(ed,57) { ld_a_i(); } /* LD A,i */
2652
	2652
2653	2653	OP(ed,58) { E = in(BC); F = (F & CF) \| SZP[E]; } /* IN E,(C) */
2654	2654	OP(ed,59) { out(BC, E); } /* OUT (C),E */
2655	2655	OP(ed,5a) { adc_hl(m_de); } /* ADC HL,DE */

trunk/src/emu/cpu/z80/tlcs_z80.c
r29404	r29405
40	40	static const z80sio_interface sio_intf =
41	41	{
42	42	DEVCB_CPU_INPUT_LINE(DEVICE_SELF_OWNER, INPUT_LINE_IRQ0), /* interrupt handler */
43		DEVCB_NULL, /* DTR changed handler */
	43	DEVCB_NULL, /* DTR changed handler */
44	44	DEVCB_NULL, /* RTS changed handler */
45	45	DEVCB_NULL, /* BREAK changed handler */
46	46	DEVCB_NULL, /* transmit handler */
r29404	r29405
63	63	AM_RANGE(0x10, 0x13) AM_DEVREADWRITE(TLCSZ80_INTERNAL_CTC_TAG, z80ctc_device, read, write)
64	64	AM_RANGE(0x18, 0x1B) AM_DEVREADWRITE(TLCSZ80_INTERNAL_SIO_TAG, z80sio_device, read, write)
65	65	AM_RANGE(0x1C, 0x1F) AM_DEVREADWRITE(TLCSZ80_INTERNAL_PIO_TAG, z80pio_device, read, write)
66		// AM_RANGE(0xF0, 0xF0) TODO: Watchdog Timer: Stand-by mode Register
67		// AM_RANGE(0xF1, 0xF1) TODO: Watchdog Timer: command Register
68		// AM_RANGE(0xF4, 0xF4) TODO: Daisy chain interrupt precedence Register
	66	// AM_RANGE(0xF0, 0xF0) TODO: Watchdog Timer: Stand-by mode Register
	67	// AM_RANGE(0xF1, 0xF1) TODO: Watchdog Timer: command Register
	68	// AM_RANGE(0xF4, 0xF4) TODO: Daisy chain interrupt precedence Register
69	69	ADDRESS_MAP_END
70	70
71	71	//This is wrong!
r29404	r29405
79	79	MACHINE_CONFIG_END
80	80
81	81	tlcs_z80_device::tlcs_z80_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
82		: z80_device(mconfig, TLCS_Z80, "TLCS-Z80", tag, owner, clock, "tlcs_z80", __FILE__),
	82	: z80_device(mconfig, TLCS_Z80, "TLCS-Z80", tag, owner, clock, "tlcs_z80", __FILE__),
83	83	m_z80ctc(*this, TLCSZ80_INTERNAL_CTC_TAG),
84	84	m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 8, 0, ADDRESS_MAP_NAME( tlcs_z80_internal_io_map ) )
85	85	{ }
r29404	r29405
97	97	}
98	98
99	99	const device_type TLCS_Z80 = &device_creator<tlcs_z80_device>;
100

trunk/src/emu/cpu/unsp/unsp.c
r29404	r29405
162	162
163	163	void unsp_device::state_import(const device_state_entry &entry)
164	164	{
165		switch (entry.index())
166		{
167		case UNSP_PC:
	165	switch (entry.index())
	166	{
	167	case UNSP_PC:
168	168	UNSP_REG(PC) = (m_debugger_temp & 0x0001fffe) >> 1;
169	169	UNSP_REG(SR) = (UNSP_REG(SR) & 0xffc0) \| ((m_debugger_temp & 0x007e0000) >> 17);
170		break;
171		}
	170	break;
	171	}
172	172	}
173	173
174	174	void unsp_device::device_reset()
r29404	r29405
863	863	UNSP_REG(PC) = READ16(irq_vector);
864	864	UNSP_REG(SR) = 0;
865	865	}
866

trunk/src/emu/cpu/tms34010/tms34010.h
r29404	r29405
216	216	/* Reads & writes to the 34010 I/O registers; place at 0xc0000000 */
217	217	DECLARE_WRITE16_MEMBER( io_register_w );
218	218	DECLARE_READ16_MEMBER( io_register_r );
219
	219
220	220	DECLARE_WRITE16_MEMBER(host_w);
221	221	DECLARE_READ16_MEMBER(host_r);
222	222	};

trunk/src/emu/cpu/tms34010/tms34010.c
r29404	r29405
1659	1659	tms34010_state *tms = get_safe_token(this);
1660	1660	unsigned int addr;
1661	1661	int result = 0;
1662
	1662
1663	1663	/* swap to the target cpu */
1664	1664
1665	1665	switch (reg)

trunk/src/emu/cpu/tms34010/34010gfx.c
r29404	r29405
109	109	/* clip Y */
110	110	diff = WSTART_Y(tms) - sy;
111	111	if (diff > 0)
112		{
	112	{
113	113	#if 0 // littlerb and megaphx do not work correctly with this enabled, see items dropping into playfield from top
114	114	if (srcaddr)
115	115	srcaddr += diff SPTCH(tms);

trunk/src/emu/cpu/dsp32/dsp32.c
r29404	r29405
188	188	void dsp32c_device::device_start()
189	189	{
190	190	m_output_pins_changed.resolve_safe();
191
	191
192	192	// get our address spaces
193	193	m_program = &space(AS_PROGRAM);
194	194	m_direct = &m_program->direct();

trunk/src/emu/video/pc_vga.c
r29404	r29405
128	128
129	129	vga_device::vga_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source)
130	130	: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
131		m_palette(*this, "^palette")
	131	m_palette(*this, "^palette")
132	132	{
133	133	}
134	134
135	135	vga_device::vga_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
136	136	: device_t(mconfig, VGA, "VGA", tag, owner, clock, "vga", __FILE__),
137		m_palette(*this, "^palette")
	137	m_palette(*this, "^palette")
138	138	{
139	139	}
140	140
r29404	r29405
2873	2873	// DCLK calculation
2874	2874	freq = ((double)(s3.clk_pll_m+2) / (double)((s3.clk_pll_n+2)(pow(2.0,s3.clk_pll_r)))) 14.318f; // clock between XIN and XOUT
2875	2875	xtal = freq * 1000000;
2876		}
	2876	}
2877	2877
2878	2878	if((s3.ext_misc_ctrl_2) >> 4)
2879	2879	{

trunk/src/emu/video/tms34061.c
r29404	r29405
54	54	{
55	55	/* resolve callbak */
56	56	m_interrupt_cb.resolve();
57
	57
58	58	/* reset the data */
59	59	m_vrammask = m_vramsize - 1;
60	60

trunk/src/emu/video/tms34061.h
r29404	r29405
20	20
21	21	#define MCFG_TMS34061_INTERRUPT_CB(_devcb) \
22	22	devcb = &tms34061_device::set_interrupt_callback(*device, DEVCB2_##_devcb);
23
24	23
	24
25	25	/* register constants */
26	26	enum
27	27	{
r29404	r29405
67	67	public:
68	68	// construction/destruction
69	69	tms34061_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
70
	70
71	71	static void set_rowshift(device_t &device, UINT8 rowshift) { downcast<tms34061_device &>(device).m_rowshift = rowshift; }
72	72	static void set_vram_size(device_t &device, UINT32 vramsize) { downcast<tms34061_device &>(device).m_vramsize = vramsize; }
73	73	template<class _Object> static devcb2_base &set_interrupt_callback(device_t &device, _Object object) { return downcast<tms34061_device &>(device).m_interrupt_cb.set_callback(object); }
r29404	r29405
91	91	virtual void device_reset();
92	92
93	93	private:
94		UINT8 m_rowshift; /* VRAM address is (row << rowshift) \| col */
95		UINT32 m_vramsize; /* size of video RAM */
96		devcb2_write_line m_interrupt_cb; /* interrupt gen callback */
97
	94	UINT8 m_rowshift; /* VRAM address is (row << rowshift) \| col */
	95	UINT32 m_vramsize; /* size of video RAM */
	96	devcb2_write_line m_interrupt_cb; /* interrupt gen callback */
	97
98	98	UINT16 m_regs[TMS34061_REGCOUNT];
99	99	UINT16 m_xmask;
100	100	UINT8 m_yshift;

trunk/src/emu/video/hd44780.h
r29404	r29405
125	125	int m_rw_state;
126	126	bool m_nibble;
127	127	int m_charset_type;
128		UINT8 m_render_buf[80*16];
	128	UINT8 m_render_buf[80*16];
129	129
130	130	enum { DDRAM, CGRAM };
131	131	};

trunk/src/emu/video/crt9212.h
r29404	r29405
72	72	public:
73	73	// construction/destruction
74	74	crt9212_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
75
	75
76	76	static void static_set_wen2(device_t &device, int state) { downcast<crt9212_t &>(device).m_wen2 = state; }
77	77
78	78	template<class _Object> static devcb2_base &set_dout_wr_callback(device_t &device, _Object object) { return downcast<crt9212_t &>(device).m_write_dout.set_callback(object); }
r29404	r29405
94	94	virtual void device_start();
95	95
96	96	private:
97		devcb2_write8 m_write_dout;
	97	devcb2_write8 m_write_dout;
98	98	devcb2_write_line m_write_rof;
99	99	devcb2_write_line m_write_wof;
100	100

trunk/src/emu/video/epic12_blit2.c
r29404	r29405
553	553	#undef FLIPX
554	554	#undef TINT
555	555	#undef TRANSPARENT
556		#undef REALLY_SIMPLE
		No newline at end of file
	556	#undef REALLY_SIMPLE

trunk/src/emu/video/epic12_blit6.c
r29404	r29405
554	554	#undef TINT
555	555	#undef TRANSPARENT
556	556	#undef REALLY_SIMPLE
557
558

trunk/src/emu/video/crt9021.h
r29404	r29405
56	56	// ======================> crt9021_t
57	57
58	58	class crt9021_t : public device_t,
59		public device_video_interface
	59	public device_video_interface
60	60	{
61	61	public:
62	62	// construction/destruction
63	63	crt9021_t(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
64
	64
65	65	static void static_set_display_callback(device_t &device, crt9021_draw_character_delegate callback) { downcast<crt9021_t &>(device).m_display_cb = callback; }
66	66
67	67	void write(UINT8 data) { m_data = data; }

trunk/src/emu/video/mb_vcu.h
r29404	r29405
19	19
20	20	#define MCFG_MB_VCU_ADD(_tag,_freq,_config, _palette_tag) \
21	21	MCFG_DEVICE_ADD(_tag, MB_VCU, _freq) \
22		MCFG_DEVICE_CONFIG(_config) \
	22	MCFG_DEVICE_CONFIG(_config) \
23	23	mb_vcu_device::static_set_palette_tag(*device, "^" _palette_tag);
24	24
25	25	//**************************************************************************

trunk/src/emu/video/ramdac.h
r29404	r29405
19	19	#define MCFG_RAMDAC_ADD(_tag,_config,_map,_palette_tag) \
20	20	MCFG_DEVICE_ADD(_tag, RAMDAC, 0) \
21	21	MCFG_DEVICE_CONFIG(_config) \
22		MCFG_DEVICE_ADDRESS_MAP(AS_0, _map) \
23		ramdac_device::static_set_palette_tag(*device, "^" _palette_tag);
	22	MCFG_DEVICE_ADDRESS_MAP(AS_0, _map) \
	23	ramdac_device::static_set_palette_tag(*device, "^" _palette_tag);
24	24
25	25	#define RAMDAC_INTERFACE(name) \
26	26	const ramdac_interface (name) =
r29404	r29405
79	79	UINT8 m_int_index[2];
80	80	UINT8 *m_palram;
81	81
82		const address_space_config m_space_config;
	82	const address_space_config m_space_config;
83	83	required_device<palette_device> m_palette;
84	84	};
85	85

trunk/src/emu/video/hd61830.h
r29404	r29405
93	93
94	94	emu_timer *m_busy_timer;
95	95	//address_space *m_data;
96
	96
97	97	bool m_bf; // busy flag
98	98
99	99	UINT8 m_ir; // instruction register

trunk/src/emu/video/epic12_blit3.c
r29404	r29405
553	553	#undef FLIPX
554	554	#undef TINT
555	555	#undef TRANSPARENT
556		#undef REALLY_SIMPLE
		No newline at end of file
	556	#undef REALLY_SIMPLE

trunk/src/emu/video/epic12_blit7.c
r29404	r29405
554	554	#undef TINT
555	555	#undef TRANSPARENT
556	556	#undef REALLY_SIMPLE
557
558

trunk/src/emu/video/mc6847.c
r29404	r29405
1858	1858	//-------------------------------------------------
1859	1859
1860	1860	s68047_device::s68047_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1861		: mc6847_base_device(mconfig, S68047, "S68047", tag, owner, clock, s68047_fontdata8x12, 262.0, "s68047", __FILE__)
	1861	: mc6847_base_device(mconfig, S68047, "S68047", tag, owner, clock, s68047_fontdata8x12, 262.0, "s68047", __FILE__)
1862	1862	{
1863	1863	}
1864	1864
r29404	r29405
1879	1879
1880	1880	const UINT32 s68047_device::s_s68047_hack_palette[16] =
1881	1881	{
1882		rgb_t(0x07, 0xff, 0x00), /* GREEN */
1883		rgb_t(0xff, 0xff, 0x00), /* YELLOW */
1884		rgb_t(0x3b, 0x08, 0xff), /* BLUE */
1885		rgb_t(0xcc, 0x00, 0x3b), /* RED */
1886		rgb_t(0xff, 0xff, 0xff), /* BUFF */
1887		rgb_t(0x07, 0xe3, 0x99), /* CYAN */
1888		rgb_t(0xff, 0x1c, 0xff), /* MAGENTA */
1889		rgb_t(0xff, 0x81, 0x00), /* ORANGE */
	1882	rgb_t(0x07, 0xff, 0x00), /* GREEN */
	1883	rgb_t(0xff, 0xff, 0x00), /* YELLOW */
	1884	rgb_t(0x3b, 0x08, 0xff), /* BLUE */
	1885	rgb_t(0xcc, 0x00, 0x3b), /* RED */
	1886	rgb_t(0xff, 0xff, 0xff), /* BUFF */
	1887	rgb_t(0x07, 0xe3, 0x99), /* CYAN */
	1888	rgb_t(0xff, 0x1c, 0xff), /* MAGENTA */
	1889	rgb_t(0xff, 0x81, 0x00), /* ORANGE */
1890	1890
1891		rgb_t(0x00, 0x00, 0x00), /* BLACK */
1892		rgb_t(0x07, 0xff, 0x00), /* GREEN */
1893		rgb_t(0x3b, 0x08, 0xff), /* BLUE */
1894		rgb_t(0xff, 0xff, 0xff), /* BUFF */
	1891	rgb_t(0x00, 0x00, 0x00), /* BLACK */
	1892	rgb_t(0x07, 0xff, 0x00), /* GREEN */
	1893	rgb_t(0x3b, 0x08, 0xff), /* BLUE */
	1894	rgb_t(0xff, 0xff, 0xff), /* BUFF */
1895	1895
1896		rgb_t(0x00, 0x7c, 0x00), /* ALPHANUMERIC DARK GREEN */
1897		rgb_t(0x07, 0xff, 0x00), /* ALPHANUMERIC BRIGHT GREEN */
1898		rgb_t(0x91, 0x00, 0x00), /* ALPHANUMERIC DARK ORANGE */
1899		rgb_t(0xff, 0x81, 0x00) /* ALPHANUMERIC BRIGHT ORANGE */
	1896	rgb_t(0x00, 0x7c, 0x00), /* ALPHANUMERIC DARK GREEN */
	1897	rgb_t(0x07, 0xff, 0x00), /* ALPHANUMERIC BRIGHT GREEN */
	1898	rgb_t(0x91, 0x00, 0x00), /* ALPHANUMERIC DARK ORANGE */
	1899	rgb_t(0xff, 0x81, 0x00) /* ALPHANUMERIC BRIGHT ORANGE */
1900	1900	};
1901

trunk/src/emu/video/mc6847.h
r29404	r29405
44	44	#define MCFG_MC6847_FSYNC_CALLBACK(_write) \
45	45	devcb = &mc6847_friend_device::set_fsync_wr_callback(*device, DEVCB2_##_write);
46	46
47
	47
48	48	/* interface */
49	49	struct mc6847_interface
50	50	{
r29404	r29405
668	668	class s68047_device : public mc6847_base_device
669	669	{
670	670	public:
671		s68047_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	671	s68047_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
672	672
673	673	void hack_black_becomes_blue(bool flag);
674	674
675	675	private:
676		static const UINT32 s_s68047_hack_palette[16];
	676	static const UINT32 s_s68047_hack_palette[16];
677	677	};
678	678
679	679

trunk/src/emu/video/upd3301.c
r29404	r29405
636	636	update_hrtc_timer(0);
637	637	update_vrtc_timer(0);
638	638	}
639

trunk/src/emu/video/hd44352.h
r29404	r29405
30	30	hd44352_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
31	31
32	32	template<class _Object> static devcb2_base &set_on_callback(device_t &device, _Object object) { return downcast<hd44352_device &>(device).m_on_cb.set_callback(object); }
33
	33
34	34	// device interface
35	35	UINT8 data_read();
36	36	void data_write(UINT8 data);

trunk/src/emu/video/huc6260.h
r29404	r29405
20	20
21	21	#define MCFG_HUC6260_NEXT_PIXEL_DATA_CB(_devcb) \
22	22	devcb = &huc6260_device::set_next_pixel_data_callback(*device, DEVCB2_##_devcb);
23
	23
24	24	#define MCFG_HUC6260_TIME_TIL_NEXT_EVENT_CB(_devcb) \
25	25	devcb = &huc6260_device::set_time_til_next_event_callback(*device, DEVCB2_##_devcb);
26
	26
27	27	#define MCFG_HUC6260_VSYNC_CHANGED_CB(_devcb) \
28	28	devcb = &huc6260_device::set_vsync_changed_callback(*device, DEVCB2_##_devcb);
29
	29
30	30	#define MCFG_HUC6260_HSYNC_CHANGED_CB(_devcb) \
31	31	devcb = &huc6260_device::set_hsync_changed_callback(*device, DEVCB2_##_devcb);
32
33	32
	33
34	34	class huc6260_device : public device_t,
35	35	public device_video_interface
36	36	{
r29404	r29405
42	42	template<class _Object> static devcb2_base &set_time_til_next_event_callback(device_t &device, _Object object) { return downcast<huc6260_device &>(device).m_time_til_next_event_cb.set_callback(object); }
43	43	template<class _Object> static devcb2_base &set_vsync_changed_callback(device_t &device, _Object object) { return downcast<huc6260_device &>(device).m_vsync_changed_cb.set_callback(object); }
44	44	template<class _Object> static devcb2_base &set_hsync_changed_callback(device_t &device, _Object object) { return downcast<huc6260_device &>(device).m_hsync_changed_cb.set_callback(object); }
45
	45
46	46	void video_update(bitmap_ind16 &bitmap, const rectangle &cliprect);
47	47	DECLARE_READ8_MEMBER( read );
48	48	DECLARE_WRITE8_MEMBER( write );

trunk/src/emu/video/fixfreq.c
r29404	r29405
268	268	{
269	269	int colv = (int) ((m_vid - m_sync_threshold) / 3.7 * 255.0);
270	270	if (colv > 255)
271		colv = 255;
	271	colv = 255;
272	272	col = rgb_t(colv, colv, colv);
273	273	}
274	274

trunk/src/emu/video/epic12.c
r29404	r29405
42	42	}
43	43
44	44	// static
45		void epic12_device::set_rambase(device_t &device, UINT16* rambase)
	45	void epic12_device::set_rambase(device_t &device, UINT16* rambase)
46	46	{
47	47	epic12_device &dev = downcast<epic12_device &>(device);
48	48	dev.epic12_device_ram16 = rambase;
r29404	r29405
87	87
88	88	void epic12_device::device_reset()
89	89	{
90
91	90	if (m_is_unsafe)
92	91	{
93	92	use_ram = epic12_device_ram16;
r29404	r29405
138	137	{
139	138	// UINT16 data = space.read_word(*addr); // going through the memory system is 'more correct' but noticably slower
140	139	UINT16 data = use_ram[((*addr & m_main_rammask) >> 1) ^ NATIVE_ENDIAN_VALUE_LE_BE(3, 0)];
141
	140
142	141	*addr += 2;
143	142
144	143	// printf("data %04x\n", data);
r29404	r29405
229	228
230	229	epic12_device_blitfunction epic12_device_f0_ti1_tr1_blit_funcs[] =
231	230	{
232
233	231	epic12_device::draw_sprite_f0_ti1_tr1_s0_d0, epic12_device::draw_sprite_f0_ti1_tr1_s1_d0, epic12_device::draw_sprite_f0_ti1_tr1_s2_d0, epic12_device::draw_sprite_f0_ti1_tr1_s3_d0, epic12_device::draw_sprite_f0_ti1_tr1_s4_d0, epic12_device::draw_sprite_f0_ti1_tr1_s5_d0, epic12_device::draw_sprite_f0_ti1_tr1_s6_d0, epic12_device::draw_sprite_f0_ti1_tr1_s7_d0,
234	232	epic12_device::draw_sprite_f0_ti1_tr1_s0_d1, epic12_device::draw_sprite_f0_ti1_tr1_s1_d1, epic12_device::draw_sprite_f0_ti1_tr1_s2_d1, epic12_device::draw_sprite_f0_ti1_tr1_s3_d1, epic12_device::draw_sprite_f0_ti1_tr1_s4_d1, epic12_device::draw_sprite_f0_ti1_tr1_s5_d1, epic12_device::draw_sprite_f0_ti1_tr1_s6_d1, epic12_device::draw_sprite_f0_ti1_tr1_s7_d1,
235	233	epic12_device::draw_sprite_f0_ti1_tr1_s0_d2, epic12_device::draw_sprite_f0_ti1_tr1_s1_d2, epic12_device::draw_sprite_f0_ti1_tr1_s2_d2, epic12_device::draw_sprite_f0_ti1_tr1_s3_d2, epic12_device::draw_sprite_f0_ti1_tr1_s4_d2, epic12_device::draw_sprite_f0_ti1_tr1_s5_d2, epic12_device::draw_sprite_f0_ti1_tr1_s6_d2, epic12_device::draw_sprite_f0_ti1_tr1_s7_d2,
r29404	r29405
242	240
243	241	epic12_device_blitfunction epic12_device_f0_ti1_tr0_blit_funcs[] =
244	242	{
245
246	243	epic12_device::draw_sprite_f0_ti1_tr0_s0_d0, epic12_device::draw_sprite_f0_ti1_tr0_s1_d0, epic12_device::draw_sprite_f0_ti1_tr0_s2_d0, epic12_device::draw_sprite_f0_ti1_tr0_s3_d0, epic12_device::draw_sprite_f0_ti1_tr0_s4_d0, epic12_device::draw_sprite_f0_ti1_tr0_s5_d0, epic12_device::draw_sprite_f0_ti1_tr0_s6_d0, epic12_device::draw_sprite_f0_ti1_tr0_s7_d0,
247	244	epic12_device::draw_sprite_f0_ti1_tr0_s0_d1, epic12_device::draw_sprite_f0_ti1_tr0_s1_d1, epic12_device::draw_sprite_f0_ti1_tr0_s2_d1, epic12_device::draw_sprite_f0_ti1_tr0_s3_d1, epic12_device::draw_sprite_f0_ti1_tr0_s4_d1, epic12_device::draw_sprite_f0_ti1_tr0_s5_d1, epic12_device::draw_sprite_f0_ti1_tr0_s6_d1, epic12_device::draw_sprite_f0_ti1_tr0_s7_d1,
248	245	epic12_device::draw_sprite_f0_ti1_tr0_s0_d2, epic12_device::draw_sprite_f0_ti1_tr0_s1_d2, epic12_device::draw_sprite_f0_ti1_tr0_s2_d2, epic12_device::draw_sprite_f0_ti1_tr0_s3_d2, epic12_device::draw_sprite_f0_ti1_tr0_s4_d2, epic12_device::draw_sprite_f0_ti1_tr0_s5_d2, epic12_device::draw_sprite_f0_ti1_tr0_s6_d2, epic12_device::draw_sprite_f0_ti1_tr0_s7_d2,
r29404	r29405
255	252
256	253	epic12_device_blitfunction epic12_device_f1_ti1_tr1_blit_funcs[] =
257	254	{
258
259	255	epic12_device::draw_sprite_f1_ti1_tr1_s0_d0, epic12_device::draw_sprite_f1_ti1_tr1_s1_d0, epic12_device::draw_sprite_f1_ti1_tr1_s2_d0, epic12_device::draw_sprite_f1_ti1_tr1_s3_d0, epic12_device::draw_sprite_f1_ti1_tr1_s4_d0, epic12_device::draw_sprite_f1_ti1_tr1_s5_d0, epic12_device::draw_sprite_f1_ti1_tr1_s6_d0, epic12_device::draw_sprite_f1_ti1_tr1_s7_d0,
260	256	epic12_device::draw_sprite_f1_ti1_tr1_s0_d1, epic12_device::draw_sprite_f1_ti1_tr1_s1_d1, epic12_device::draw_sprite_f1_ti1_tr1_s2_d1, epic12_device::draw_sprite_f1_ti1_tr1_s3_d1, epic12_device::draw_sprite_f1_ti1_tr1_s4_d1, epic12_device::draw_sprite_f1_ti1_tr1_s5_d1, epic12_device::draw_sprite_f1_ti1_tr1_s6_d1, epic12_device::draw_sprite_f1_ti1_tr1_s7_d1,
261	257	epic12_device::draw_sprite_f1_ti1_tr1_s0_d2, epic12_device::draw_sprite_f1_ti1_tr1_s1_d2, epic12_device::draw_sprite_f1_ti1_tr1_s2_d2, epic12_device::draw_sprite_f1_ti1_tr1_s3_d2, epic12_device::draw_sprite_f1_ti1_tr1_s4_d2, epic12_device::draw_sprite_f1_ti1_tr1_s5_d2, epic12_device::draw_sprite_f1_ti1_tr1_s6_d2, epic12_device::draw_sprite_f1_ti1_tr1_s7_d2,
r29404	r29405
268	264
269	265	epic12_device_blitfunction epic12_device_f1_ti1_tr0_blit_funcs[] =
270	266	{
271
272	267	epic12_device::draw_sprite_f1_ti1_tr0_s0_d0, epic12_device::draw_sprite_f1_ti1_tr0_s1_d0, epic12_device::draw_sprite_f1_ti1_tr0_s2_d0, epic12_device::draw_sprite_f1_ti1_tr0_s3_d0, epic12_device::draw_sprite_f1_ti1_tr0_s4_d0, epic12_device::draw_sprite_f1_ti1_tr0_s5_d0, epic12_device::draw_sprite_f1_ti1_tr0_s6_d0, epic12_device::draw_sprite_f1_ti1_tr0_s7_d0,
273	268	epic12_device::draw_sprite_f1_ti1_tr0_s0_d1, epic12_device::draw_sprite_f1_ti1_tr0_s1_d1, epic12_device::draw_sprite_f1_ti1_tr0_s2_d1, epic12_device::draw_sprite_f1_ti1_tr0_s3_d1, epic12_device::draw_sprite_f1_ti1_tr0_s4_d1, epic12_device::draw_sprite_f1_ti1_tr0_s5_d1, epic12_device::draw_sprite_f1_ti1_tr0_s6_d1, epic12_device::draw_sprite_f1_ti1_tr0_s7_d1,
274	269	epic12_device::draw_sprite_f1_ti1_tr0_s0_d2, epic12_device::draw_sprite_f1_ti1_tr0_s1_d2, epic12_device::draw_sprite_f1_ti1_tr0_s2_d2, epic12_device::draw_sprite_f1_ti1_tr0_s3_d2, epic12_device::draw_sprite_f1_ti1_tr0_s4_d2, epic12_device::draw_sprite_f1_ti1_tr0_s5_d2, epic12_device::draw_sprite_f1_ti1_tr0_s6_d2, epic12_device::draw_sprite_f1_ti1_tr0_s7_d2,
r29404	r29405
283	278
284	279	epic12_device_blitfunction epic12_device_f0_ti0_tr1_blit_funcs[] =
285	280	{
286
287	281	epic12_device::draw_sprite_f0_ti0_tr1_s0_d0, epic12_device::draw_sprite_f0_ti0_tr1_s1_d0, epic12_device::draw_sprite_f0_ti0_tr1_s2_d0, epic12_device::draw_sprite_f0_ti0_tr1_s3_d0, epic12_device::draw_sprite_f0_ti0_tr1_s4_d0, epic12_device::draw_sprite_f0_ti0_tr1_s5_d0, epic12_device::draw_sprite_f0_ti0_tr1_s6_d0, epic12_device::draw_sprite_f0_ti0_tr1_s7_d0,
288	282	epic12_device::draw_sprite_f0_ti0_tr1_s0_d1, epic12_device::draw_sprite_f0_ti0_tr1_s1_d1, epic12_device::draw_sprite_f0_ti0_tr1_s2_d1, epic12_device::draw_sprite_f0_ti0_tr1_s3_d1, epic12_device::draw_sprite_f0_ti0_tr1_s4_d1, epic12_device::draw_sprite_f0_ti0_tr1_s5_d1, epic12_device::draw_sprite_f0_ti0_tr1_s6_d1, epic12_device::draw_sprite_f0_ti0_tr1_s7_d1,
289	283	epic12_device::draw_sprite_f0_ti0_tr1_s0_d2, epic12_device::draw_sprite_f0_ti0_tr1_s1_d2, epic12_device::draw_sprite_f0_ti0_tr1_s2_d2, epic12_device::draw_sprite_f0_ti0_tr1_s3_d2, epic12_device::draw_sprite_f0_ti0_tr1_s4_d2, epic12_device::draw_sprite_f0_ti0_tr1_s5_d2, epic12_device::draw_sprite_f0_ti0_tr1_s6_d2, epic12_device::draw_sprite_f0_ti0_tr1_s7_d2,
r29404	r29405
296	290
297	291	epic12_device_blitfunction epic12_device_f0_ti0_tr0_blit_funcs[] =
298	292	{
299
300	293	epic12_device::draw_sprite_f0_ti0_tr0_s0_d0, epic12_device::draw_sprite_f0_ti0_tr0_s1_d0, epic12_device::draw_sprite_f0_ti0_tr0_s2_d0, epic12_device::draw_sprite_f0_ti0_tr0_s3_d0, epic12_device::draw_sprite_f0_ti0_tr0_s4_d0, epic12_device::draw_sprite_f0_ti0_tr0_s5_d0, epic12_device::draw_sprite_f0_ti0_tr0_s6_d0, epic12_device::draw_sprite_f0_ti0_tr0_s7_d0,
301	294	epic12_device::draw_sprite_f0_ti0_tr0_s0_d1, epic12_device::draw_sprite_f0_ti0_tr0_s1_d1, epic12_device::draw_sprite_f0_ti0_tr0_s2_d1, epic12_device::draw_sprite_f0_ti0_tr0_s3_d1, epic12_device::draw_sprite_f0_ti0_tr0_s4_d1, epic12_device::draw_sprite_f0_ti0_tr0_s5_d1, epic12_device::draw_sprite_f0_ti0_tr0_s6_d1, epic12_device::draw_sprite_f0_ti0_tr0_s7_d1,
302	295	epic12_device::draw_sprite_f0_ti0_tr0_s0_d2, epic12_device::draw_sprite_f0_ti0_tr0_s1_d2, epic12_device::draw_sprite_f0_ti0_tr0_s2_d2, epic12_device::draw_sprite_f0_ti0_tr0_s3_d2, epic12_device::draw_sprite_f0_ti0_tr0_s4_d2, epic12_device::draw_sprite_f0_ti0_tr0_s5_d2, epic12_device::draw_sprite_f0_ti0_tr0_s6_d2, epic12_device::draw_sprite_f0_ti0_tr0_s7_d2,
r29404	r29405
309	302
310	303	epic12_device_blitfunction epic12_device_f1_ti0_tr1_blit_funcs[] =
311	304	{
312
313	305	epic12_device::draw_sprite_f1_ti0_tr1_s0_d0, epic12_device::draw_sprite_f1_ti0_tr1_s1_d0, epic12_device::draw_sprite_f1_ti0_tr1_s2_d0, epic12_device::draw_sprite_f1_ti0_tr1_s3_d0, epic12_device::draw_sprite_f1_ti0_tr1_s4_d0, epic12_device::draw_sprite_f1_ti0_tr1_s5_d0, epic12_device::draw_sprite_f1_ti0_tr1_s6_d0, epic12_device::draw_sprite_f1_ti0_tr1_s7_d0,
314	306	epic12_device::draw_sprite_f1_ti0_tr1_s0_d1, epic12_device::draw_sprite_f1_ti0_tr1_s1_d1, epic12_device::draw_sprite_f1_ti0_tr1_s2_d1, epic12_device::draw_sprite_f1_ti0_tr1_s3_d1, epic12_device::draw_sprite_f1_ti0_tr1_s4_d1, epic12_device::draw_sprite_f1_ti0_tr1_s5_d1, epic12_device::draw_sprite_f1_ti0_tr1_s6_d1, epic12_device::draw_sprite_f1_ti0_tr1_s7_d1,
315	307	epic12_device::draw_sprite_f1_ti0_tr1_s0_d2, epic12_device::draw_sprite_f1_ti0_tr1_s1_d2, epic12_device::draw_sprite_f1_ti0_tr1_s2_d2, epic12_device::draw_sprite_f1_ti0_tr1_s3_d2, epic12_device::draw_sprite_f1_ti0_tr1_s4_d2, epic12_device::draw_sprite_f1_ti0_tr1_s5_d2, epic12_device::draw_sprite_f1_ti0_tr1_s6_d2, epic12_device::draw_sprite_f1_ti0_tr1_s7_d2,
r29404	r29405
322	314
323	315	epic12_device_blitfunction epic12_device_f1_ti0_tr0_blit_funcs[] =
324	316	{
325
326	317	epic12_device::draw_sprite_f1_ti0_tr0_s0_d0, epic12_device::draw_sprite_f1_ti0_tr0_s1_d0, epic12_device::draw_sprite_f1_ti0_tr0_s2_d0, epic12_device::draw_sprite_f1_ti0_tr0_s3_d0, epic12_device::draw_sprite_f1_ti0_tr0_s4_d0, epic12_device::draw_sprite_f1_ti0_tr0_s5_d0, epic12_device::draw_sprite_f1_ti0_tr0_s6_d0, epic12_device::draw_sprite_f1_ti0_tr0_s7_d0,
327	318	epic12_device::draw_sprite_f1_ti0_tr0_s0_d1, epic12_device::draw_sprite_f1_ti0_tr0_s1_d1, epic12_device::draw_sprite_f1_ti0_tr0_s2_d1, epic12_device::draw_sprite_f1_ti0_tr0_s3_d1, epic12_device::draw_sprite_f1_ti0_tr0_s4_d1, epic12_device::draw_sprite_f1_ti0_tr0_s5_d1, epic12_device::draw_sprite_f1_ti0_tr0_s6_d1, epic12_device::draw_sprite_f1_ti0_tr0_s7_d1,
328	319	epic12_device::draw_sprite_f1_ti0_tr0_s0_d2, epic12_device::draw_sprite_f1_ti0_tr0_s1_d2, epic12_device::draw_sprite_f1_ti0_tr0_s2_d2, epic12_device::draw_sprite_f1_ti0_tr0_s3_d2, epic12_device::draw_sprite_f1_ti0_tr0_s4_d2, epic12_device::draw_sprite_f1_ti0_tr0_s5_d2, epic12_device::draw_sprite_f1_ti0_tr0_s6_d2, epic12_device::draw_sprite_f1_ti0_tr0_s7_d2,
r29404	r29405
343	334	COPY_NEXT_WORD(space, addr);
344	335	COPY_NEXT_WORD(space, addr); // UINT16 dst_x_start = COPY_NEXT_WORD(space, addr);
345	336	COPY_NEXT_WORD(space, addr); // UINT16 dst_y_start = COPY_NEXT_WORD(space, addr);
346		UINT16 w = COPY_NEXT_WORD(space, addr);
347		UINT16 h = COPY_NEXT_WORD(space, addr);
	337	UINT16 w = COPY_NEXT_WORD(space, addr);
	338	UINT16 h = COPY_NEXT_WORD(space, addr);
348	339	COPY_NEXT_WORD(space, addr);
349	340	COPY_NEXT_WORD(space, addr);
350	341
r29404	r29405
359	350
360	351	inline void epic12_device::epic12_device_gfx_draw(offs_t *addr)
361	352	{
362		int x,y, dimx,dimy, flipx,flipy;//, src_p;
	353	int x,y, dimx,dimy, flipx,flipy;//, src_p;
363	354	int trans,blend, s_mode, d_mode;
364	355	clr_t tint_clr;
365	356	int tinted = 0;
366	357
367		UINT16 attr = READ_NEXT_WORD(addr);
368		UINT16 alpha = READ_NEXT_WORD(addr);
369		UINT16 src_x = READ_NEXT_WORD(addr);
370		UINT16 src_y = READ_NEXT_WORD(addr);
371		UINT16 dst_x_start = READ_NEXT_WORD(addr);
372		UINT16 dst_y_start = READ_NEXT_WORD(addr);
373		UINT16 w = READ_NEXT_WORD(addr);
374		UINT16 h = READ_NEXT_WORD(addr);
375		UINT16 tint_r = READ_NEXT_WORD(addr);
376		UINT16 tint_gb = READ_NEXT_WORD(addr);
	358	UINT16 attr = READ_NEXT_WORD(addr);
	359	UINT16 alpha = READ_NEXT_WORD(addr);
	360	UINT16 src_x = READ_NEXT_WORD(addr);
	361	UINT16 src_y = READ_NEXT_WORD(addr);
	362	UINT16 dst_x_start = READ_NEXT_WORD(addr);
	363	UINT16 dst_y_start = READ_NEXT_WORD(addr);
	364	UINT16 w = READ_NEXT_WORD(addr);
	365	UINT16 h = READ_NEXT_WORD(addr);
	366	UINT16 tint_r = READ_NEXT_WORD(addr);
	367	UINT16 tint_gb = READ_NEXT_WORD(addr);
377	368
378	369	// 0: +alpha
379	370	// 1: +source
r29404	r29405
384	375	// 6: -dest
385	376	// 7: *
386	377
387		d_mode = attr & 0x0007;
388		s_mode = (attr & 0x0070) >> 4;
	378	d_mode = attr & 0x0007;
	379	s_mode = (attr & 0x0070) >> 4;
389	380
390		trans = attr & 0x0100;
391		blend = attr & 0x0200;
	381	trans = attr & 0x0100;
	382	blend = attr & 0x0200;
392	383
393		flipy = attr & 0x0400;
394		flipx = attr & 0x0800;
	384	flipy = attr & 0x0400;
	385	flipx = attr & 0x0800;
395	386
396		const UINT8 d_alpha = ((alpha & 0x00ff) )>>3;
397		const UINT8 s_alpha = ((alpha & 0xff00) >> 8 )>>3;
	387	const UINT8 d_alpha = ((alpha & 0x00ff) )>>3;
	388	const UINT8 s_alpha = ((alpha & 0xff00) >> 8 )>>3;
398	389
399	390	// src_p = 0;
400		src_x = src_x & 0x1fff;
401		src_y = src_y & 0x0fff;
	391	src_x = src_x & 0x1fff;
	392	src_y = src_y & 0x0fff;
402	393
403	394
404		x = (dst_x_start & 0x7fff) - (dst_x_start & 0x8000);
405		y = (dst_y_start & 0x7fff) - (dst_y_start & 0x8000);
	395	x = (dst_x_start & 0x7fff) - (dst_x_start & 0x8000);
	396	y = (dst_y_start & 0x7fff) - (dst_y_start & 0x8000);
406	397
407		dimx = (w & 0x1fff) + 1;
408		dimy = (h & 0x0fff) + 1;
	398	dimx = (w & 0x1fff) + 1;
	399	dimy = (h & 0x0fff) + 1;
409	400
410	401	// convert parameters to clr
411	402
r29404	r29405
483	474	}
484	475	else
485	476	{
486
487	477	if (blend==0 && tinted==0)
488	478	{
489	479	if (!flipx)
r29404	r29405
903	893
904	894
905	895
906
	896
907	897	READ32_MEMBER( epic12_device::epic12_device_blitter_r )
908	898	{
909	899	switch (offset*4)

trunk/src/emu/video/ef9345.h
r29404	r29405
21	21
22	22	#define MCFG_EF9345_PALETTE(_palette_tag) \
23	23	ef9345_device::static_set_palette_tag(*device, "^" _palette_tag);
24
	24
25	25	//**************************************************************************
26	26	// TYPE DEFINITIONS
27	27	//**************************************************************************
r29404	r29405
38	38
39	39	// static configuration
40	40	static void static_set_palette_tag(device_t &device, const char *tag);
41
	41
42	42	// device interface
43	43	DECLARE_READ8_MEMBER( data_r );
44	44	DECLARE_WRITE8_MEMBER( data_w );
r29404	r29405
112	112	// timers
113	113	emu_timer *m_busy_timer;
114	114	emu_timer *m_blink_timer;
115
	115
116	116	required_device<palette_device> m_palette;
117	117	};
118	118

trunk/src/emu/video/315_5124.h
r29404	r29405
64	64	static void set_signal_type(device_t &device, bool is_pal) { downcast<sega315_5124_device &>(device).m_is_pal = is_pal; }
65	65	template<class _Object> static devcb2_base &set_int_callback(device_t &device, _Object object) { return downcast<sega315_5124_device &>(device).m_int_cb.set_callback(object); }
66	66	template<class _Object> static devcb2_base &set_pause_callback(device_t &device, _Object object) { return downcast<sega315_5124_device &>(device).m_pause_cb.set_callback(object); }
67
	67
68	68	DECLARE_READ8_MEMBER( vram_read );
69	69	DECLARE_WRITE8_MEMBER( vram_write );
70	70	DECLARE_READ8_MEMBER( register_read );
r29404	r29405
164	164	static const device_timer_id TIMER_DRAW = 1;
165	165	static const device_timer_id TIMER_CHECK_HINT = 2;
166	166	static const device_timer_id TIMER_CHECK_VINT = 3;
167
	167
168	168	required_device<palette_device> m_palette;
169	169	};
170	170
r29404	r29405
209	209
210	210	#define MCFG_SEGA315_5124_INT_CB(_devcb) \
211	211	devcb = &sega315_5124_device::set_int_callback(*device, DEVCB2_##_devcb);
212
	212
213	213	#define MCFG_SEGA315_5124_PAUSE_CB(_devcb) \
214	214	devcb = &sega315_5124_device::set_pause_callback(*device, DEVCB2_##_devcb);
215	215
216	216
217	217	#define MCFG_SEGA315_5246_SET_SCREEN MCFG_VIDEO_SET_SCREEN
218
	218
219	219	#define MCFG_SEGA315_5246_IS_PAL(_bool) \
220	220	sega315_5246_device::set_signal_type(*device, _bool);
221	221
222	222	#define MCFG_SEGA315_5246_INT_CB(_devcb) \
223	223	devcb = &sega315_5246_device::set_int_callback(*device, DEVCB2_##_devcb);
224
	224
225	225	#define MCFG_SEGA315_5246_PAUSE_CB(_devcb) \
226	226	devcb = &sega315_5246_device::set_pause_callback(*device, DEVCB2_##_devcb);
227	227
228	228
229	229	#define MCFG_SEGA315_5378_SET_SCREEN MCFG_VIDEO_SET_SCREEN
230
	230
231	231	#define MCFG_SEGA315_5378_IS_PAL(_bool) \
232	232	sega315_5378_device::set_signal_type(*device, _bool);
233	233
234	234	#define MCFG_SEGA315_5378_INT_CB(_devcb) \
235	235	devcb = &sega315_5378_device::set_int_callback(*device, DEVCB2_##_devcb);
236
	236
237	237	#define MCFG_SEGA315_5378_PAUSE_CB(_devcb) \
238	238	devcb = &sega315_5378_device::set_pause_callback(*device, DEVCB2_##_devcb);
239	239

trunk/src/emu/video/epic12.h
r29404	r29405
3	3	MCFG_DEVICE_ADD(_tag, EPIC12, 0)
4	4
5	5	//#define MCFG_EP1C12_ADD(_tag,_config,_map)
6		// MCFG_DEVICE_CONFIG(_config)
7		// MCFG_DEVICE_ADDRESS_MAP(AS_0, _map)
	6	// MCFG_DEVICE_CONFIG(_config)
	7	// MCFG_DEVICE_ADDRESS_MAP(AS_0, _map)
8	8
9	9	#define MCFG_EPIC12_SET_MAINRAMSIZE( _rgn ) \
10	10	epic12_device::set_mainramsize(*device, _rgn);
r29404	r29405
29	29	};
30	30
31	31	typedef const void (epic12_device_blitfunction)(bitmap_rgb32 ,
32		const rectangle *,
33		UINT32 , / gfx */
34		int , /* src_x */
35		int , /* src_y */
36		const int , /* dst_x_start */
37		const int , /* dst_y_start */
38		int , /* dimx */
39		int , /* dimy */
40		const int , /* flipy */
41		const UINT8 , /* s_alpha */
42		const UINT8 , /* d_alpha */
43		//int , /* tint */
44		const clr_t * );
	32	const rectangle *,
	33	UINT32 , / gfx */
	34	int , /* src_x */
	35	int , /* src_y */
	36	const int , /* dst_x_start */
	37	const int , /* dst_y_start */
	38	int , /* dimx */
	39	int , /* dimy */
	40	const int , /* flipy */
	41	const UINT8 , /* s_alpha */
	42	const UINT8 , /* d_alpha */
	43	//int , /* tint */
	44	const clr_t * );
45	45
46	46
47	47	class epic12_device : public device_t,
r29404	r29405
79	79	bitmap_rgb32 *epic12_device_bitmaps;
80	80	rectangle epic12_device_clip;
81	81
82
	82
83	83	UINT16* use_ram;
84	84	int m_main_ramsize; // type D has double the main ram
85	85	int m_main_rammask;
r29404	r29405
676	676	// convert separate r,g,b biases (0..80..ff) to clr_t (-1f..0..1f)
677	677	static inline void tint_to_clr(UINT8 r, UINT8 g, UINT8 b, clr_t *clr)
678	678	{
679		clr->r = r>>2;
680		clr->g = g>>2;
681		clr->b = b>>2;
	679	clr->r = r>>2;
	680	clr->g = g>>2;
	681	clr->b = b>>2;
682	682	};
683	683
684	684	// clr_t to r5g5b5
685	685	static inline UINT32 clr_to_pen(const clr_t *clr)
686	686	{
687
688	687	// --t- ---- rrrr r--- gggg g--- bbbb b--- format
689	688	return (clr->r << (16+3)) \| (clr->g << (8+3)) \| (clr->b << 3);
690	689
r29404	r29405
739	738	static inline void clr_add(clr_t clr, const clr_t clr0, const clr_t *clr1)
740	739	{
741	740	/*
742		clr->r = clr0->r + clr1->r;
743		clr->g = clr0->g + clr1->g;
744		clr->b = clr0->b + clr1->b;
	741	clr->r = clr0->r + clr1->r;
	742	clr->g = clr0->g + clr1->g;
	743	clr->b = clr0->b + clr1->b;
745	744	*/
746	745	// use pre-clamped lookup table
747	746	clr->r = epic12_device_colrtable_add[clr0->r][clr1->r];
r29404	r29405
834	833
835	834
836	835
837		osd_work_queue * queue; /* work queue */
	836	osd_work_queue * queue; /* work queue */
838	837	osd_work_item * blitter_request;
839	838
840	839	// blit timing

trunk/src/emu/video/v9938.h
r29404	r29405
233	233	void (v99x8_device::draw_sprite_16)(const pen_t , UINT16, UINT8);
234	234	void (v99x8_device::draw_sprite_16s)(const pen_t , UINT16, UINT8);
235	235	} ;
236		static const v99x8_mode s_modes[];
	236	static const v99x8_mode s_modes[];
237	237	required_device<palette_device> m_palette;
238	238	protected:
239	239	static UINT16 s_pal_indYJK[0x20000];

trunk/src/emu/video/epic12_blit4.c
r29404	r29405
553	553	#undef FLIPX
554	554	#undef TINT
555	555	#undef TRANSPARENT
556		#undef REALLY_SIMPLE
		No newline at end of file
	556	#undef REALLY_SIMPLE

trunk/src/emu/video/epic12_blit8.c
r29404	r29405
38	38
39	39	#undef BLENDED
40	40	#undef REALLY_SIMPLE
41
42
43

trunk/src/emu/video/dl1416.h
r29404	r29405
34	34	public:
35	35	dl1416_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
36	36	~dl1416_device() {}
37
	37
38	38	template<class _Object> static devcb2_base &set_update_handler(device_t &device, _Object object) { return downcast<dl1416_device &>(device).m_update.set_callback(object); }
39	39
40	40	/* inputs */

trunk/src/emu/video/epic12in.inc
r29404	r29405
3	3
4	4	const void epic12_device::FUNCNAME(BLIT_PARAMS)
5	5	{
6
7
8	6	UINT32* gfx2;
9	7	int y, yf;
10	8
r29404	r29405
47	45	src_x += (dimx-1);
48	46	#endif
49	47
50		if (flipy) { yf = -1; src_y += (dimy-1); }
51		else { yf = +1; }
	48	if (flipy) { yf = -1; src_y += (dimy-1); }
	49	else { yf = +1; }
52	50
53	51	int starty = 0;
54	52	const int dst_y_end = dst_y_start+dimy;
r29404	r29405
64	62	#if FLIPX == 1
65	63	if ((src_x &0x1fff) < ((src_x-(dimx-1))&0x1fff))
66	64	{
67		// popmessage("sprite gets clipped off src_x %04x dimx %04x\n", src_x, dimx);
	65	// popmessage("sprite gets clipped off src_x %04x dimx %04x\n", src_x, dimx);
68	66	return;
69	67	}
70	68	#else
71	69	if ((src_x &0x1fff) > ((src_x+(dimx-1))&0x1fff))
72	70	{
73		// popmessage("sprite gets clipped off src_x %04x dimx %04x\n", src_x, dimx);
	71	// popmessage("sprite gets clipped off src_x %04x dimx %04x\n", src_x, dimx);
74	72	return;
75	73	}
76	74	#endif

trunk/src/emu/video/huc6270.h
r29404	r29405
20	20	public:
21	21	// construction/destruction
22	22	huc6270_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
23
	23
24	24	static void set_vram_size(device_t &device, UINT32 vram_size) { downcast<huc6270_device &>(device).m_vram_size = vram_size; }
25	25	template<class _Object> static devcb2_base &set_irq_changed_callback(device_t &device, _Object object) { return downcast<huc6270_device &>(device).m_irq_changed_cb.set_callback(object); }
26	26
r29404	r29405
66	66	HUC6270_HSW
67	67	};
68	68
69
	69
70	70	/* Size of Video ram (mandatory) */
71	71	UINT32 m_vram_size;
72
	72
73	73	/* Callback for when the irq line may have changed (mandatory) */
74	74	devcb2_write_line m_irq_changed_cb;
75	75

trunk/src/emu/video/epic12pixel.inc
r29404	r29405
3	3	#if FLIPX == 1
4	4	#define LOOP_INCREMENTS \
5	5	bmp++; \
6		gfx2--; \
7
	6	gfx2--;
8	7	#else
9	8
10	9	#define LOOP_INCREMENTS \
11	10	bmp++; \
12		gfx2++; \
13
	11	gfx2++;
14	12	#endif
15	13
16	14
r29404	r29405
49	47
50	48	// convert destination to clr
51	49	pen_to_clr(*bmp, &d_clr.trgb);
52		//d_clr.u32 = *bmp >> 3; // using the union is actually significantly slower than our pen_to_clr to function!
	50	//d_clr.u32 = *bmp >> 3; // using the union is actually significantly slower than our pen_to_clr to function!
53	51	#if _SMODE == 0
54	52	//g_profiler.start(PROFILER_USER7);
55	53
r29404	r29405
193	191	}
194	192	#endif
195	193	LOOP_INCREMENTS
196

trunk/src/emu/video/315_5313.c
r29404	r29405
2530	2530	lineptr[x] = m_palette_lookup[(dat & 0x3f)];
2531	2531	m_render_line_raw[x] \|= (dat & 0x3f) \| 0x040;
2532	2532	}
2533
	2533
2534	2534	}
2535	2535	else
2536	2536	{
r29404	r29405
2546	2546	lineptr[x] = m_palette_lookup_shadow[(dat & 0x3f)];
2547	2547	m_render_line_raw[x] \|= (dat & 0x3f) \| 0x000;
2548	2548	break;
2549
	2549
2550	2550	case 0x4000: // normal pri, no shadow sprite, no highlight = normal;
2551	2551	case 0x8000: // low pri, highlight sprite = normal;
2552	2552	lineptr[x] = m_palette_lookup[(dat & 0x3f)];
2553	2553	m_render_line_raw[x] \|= (dat & 0x3f) \| 0x040;
2554	2554	break;
2555
	2555
2556	2556	case 0x14000: // (sprite) normal pri, no shadow sprite, no highlight = normal;
2557	2557	case 0x18000: // (sprite) low pri, highlight sprite = normal;
2558	2558	lineptr[x] = m_palette_lookup_sprite[(dat & 0x3f)];
2559	2559	m_render_line_raw[x] \|= (dat & 0x3f) \| 0x080;
2560	2560	break;
2561
2562
	2561
	2562
2563	2563	case 0x0c000: // normal pri, highlight set = highlight?
2564	2564	case 0x1c000: // (sprite) normal pri, highlight set = highlight?
2565	2565	lineptr[x] = m_palette_lookup_highlight[(dat & 0x3f)];
2566	2566	m_render_line_raw[x] \|= (dat & 0x3f) \| 0x0c0;
2567	2567	break;
2568
	2568
2569	2569	case 0x0a000: // shadow set, highlight set - not possible
2570	2570	case 0x0e000: // shadow set, highlight set, normal set, not possible
2571	2571	case 0x1a000: // (sprite)shadow set, highlight set - not possible

trunk/src/emu/video/mc6845.c
r29404	r29405
1472	1472
1473	1473	machine_config_constructor mos8563_device::device_mconfig_additions() const
1474	1474	{
1475		return MACHINE_CONFIG_NAME( mos8563 );
	1475	return MACHINE_CONFIG_NAME( mos8563 );
1476	1476	}
1477	1477
1478	1478

trunk/src/emu/video/315_5313.h
r29404	r29405
149	149
150	150	#define MCFG_SEGA315_5313_INT_CB(_devcb) \
151	151	devcb = &sega315_5313_device::set_int_callback(*device, DEVCB2_##_devcb);
152
	152
153	153	#define MCFG_SEGA315_5313_PAUSE_CB(_devcb) \
154	154	devcb = &sega315_5313_device::set_pause_callback(*device, DEVCB2_##_devcb);
155	155
156	156	#define MCFG_SEGA315_5313_SND_IRQ_CALLBACK(_write) \
157	157	devcb = &sega315_5313_device::set_sndirqline_callback(*device, DEVCB2_##_write);
158
	158
159	159	#define MCFG_SEGA315_5313_LV6_IRQ_CALLBACK(_write) \
160	160	devcb = &sega315_5313_device::set_lv6irqline_callback(*device, DEVCB2_##_write);
161
	161
162	162	#define MCFG_SEGA315_5313_LV4_IRQ_CALLBACK(_write) \
163	163	devcb = &sega315_5313_device::set_lv4irqline_callback(*device, DEVCB2_##_write);
164
	164
165	165	#define MCFG_SEGA315_5313_ALT_TIMING(_data) \
166	166	sega315_5313_device::set_alt_timing(*device, _data);
167
	167
168	168	#define MCFG_SEGA315_5313_PAL_WRITE_BASE(_data) \
169	169	sega315_5313_device::set_palwrite_base(*device, _data);
170
	170
171	171	#define MCFG_SEGA315_5313_PALETTE(_palette_tag) \
172	172	sega315_5313_device::static_set_palette_tag(*device, "^" _palette_tag);
173	173
r29404	r29405
257	257	devcb2_write_line m_sndirqline_callback;
258	258	devcb2_write_line m_lv6irqline_callback;
259	259	devcb2_write_line m_lv4irqline_callback;
260
	260
261	261	md_32x_scanline_delegate m_32x_scanline_func;
262	262	md_32x_interrupt_delegate m_32x_interrupt_func;
263	263	md_32x_scanline_helper_delegate m_32x_scanline_helper_func;
264
	264
265	265	private:
266	266
267	267	int m_command_pending; // 2nd half of command pending..
r29404	r29405
291	291	int m_framerate;
292	292	int m_vdp_pal;
293	293	int m_use_cram; // c2 uses it's own palette ram, so it sets this to 0
294		int m_dma_delay; // SVP and SegaCD have some 'lag' in DMA transfers
	294	int m_dma_delay; // SVP and SegaCD have some 'lag' in DMA transfers
295	295
296	296	UINT16* m_regs;
297	297	UINT16* m_vram;

trunk/src/emu/video/upd7220.h
r29404	r29405
153	153	void draw_graphics_line(bitmap_rgb32 &bitmap, UINT32 addr, int y, int wd);
154	154	void update_graphics(bitmap_rgb32 &bitmap, const rectangle &cliprect, int force_bitmap);
155	155
156		upd7220_display_pixels_delegate m_display_cb;
157		upd7220_draw_text_delegate m_draw_text_cb;
	156	upd7220_display_pixels_delegate m_display_cb;
	157	upd7220_draw_text_delegate m_draw_text_cb;
158	158
159	159	devcb2_write_line m_write_drq;
160	160	devcb2_write_line m_write_hsync;

trunk/src/emu/video/vic4567.h
r29404	r29405
241	241	UINT8 m_palette_green[0x100];
242	242	UINT8 m_palette_blue[0x100];
243	243	int m_palette_dirty;
244
	244
245	245	required_device<palette_device> m_palette;
246	246	};
247	247

trunk/src/emu/video/crt9007.h
r29404	r29405
97	97	// ======================> crt9007_t
98	98
99	99	class crt9007_t : public device_t,
100		public device_memory_interface,
101		public device_video_interface
	100	public device_memory_interface,
	101	public device_video_interface
102	102	{
103	103	public:
104	104	// construction/destruction

trunk/src/emu/emuopts.c
r29404	r29405
491	491	astring error;
492	492	set_value(OPTION_SYSTEMNAME, name, OPTION_PRIORITY_CMDLINE, error);
493	493	assert(!error);
494
	494
495	495	// remove any existing device options and then add them afresh
496	496	remove_device_options();
497	497	if (add_slot_options(true))

trunk/src/emu/tilemap.h
r29404	r29405
438	438	UINT8 flags; // defaults to 0; one or more of TILE_* flags above
439	439	UINT8 pen_mask; // defaults to 0xff; mask to apply to pen_data while rendering the tile
440	440	UINT8 gfxnum; // defaults to 0xff; specify index of gfx for auto-invalidation on dirty
441
	441
442	442	void set(int _gfxnum, int rawcode, int rawcolor, int _flags)
443	443	{
444	444	gfx_element *gfx = decoder->gfx(_gfxnum);

trunk/src/emu/video.c
r29404	r29405
1247	1247	}
1248	1248
1249	1249	//-------------------------------------------------
1250		// toggle_throttle
	1250	// toggle_throttle
1251	1251	//-------------------------------------------------
1252	1252
1253	1253	void video_manager::toggle_throttle()
r29404	r29405
1257	1257
1258	1258
1259	1259	//-------------------------------------------------
1260		// toggle_record_movie
	1260	// toggle_record_movie
1261	1261	//-------------------------------------------------
1262	1262
1263	1263	void video_manager::toggle_record_movie()

trunk/src/lib/formats/d64_dsk.c
r29404	r29405
228	228
229	229	build_sector_description(f, img, track_offset, error_offset, sectors, sector_count);
230	230	generate_track(desc, physical_track, head, sectors, sector_count, total_size, image);
231
	231
232	232	track_offset += track_size;
233	233	error_offset += sector_count;
234	234	}

trunk/src/lib/formats/g64_dsk.c
r29404	r29405
54	54	for (int track = 0; track < track_count; track++)
55	55	{
56	56	offs_t track_offset = pick_integer_le(img, TRACK_OFFSET + (track * 4), 4);
57
	57
58	58	if (!track_offset)
59	59	continue;
60	60
r29404	r29405
68	68
69	69	UINT16 track_bytes = pick_integer_le(img, track_offset, 2);
70	70	int track_size = track_bytes * 8;
71
	71
72	72	LOG_FORMATS("track %u size %u cell %ld\n", track, track_size, 200000000L/track_size);
73	73
74	74	generate_track_from_bitstream(track, head, &img[track_offset+2], track_size, image);
r29404	r29405
82	82	int g64_format::generate_bitstream(int track, int head, int speed_zone, UINT8 trackbuf, int &track_size, floppy_image image)
83	83	{
84	84	int cell_size = c1541_cell_size[speed_zone];
85
	85
86	86	generate_bitstream_from_track(track, head, cell_size, trackbuf, track_size, image);
87
	87
88	88	int actual_cell_size = 200000000L/track_size;
89	89
90	90	// allow a tolerance of +- 10 us (3990..4010 -> 4000)
r29404	r29405
96	96	UINT8 header[] = { 'G', 'C', 'R', '-', '1', '5', '4', '1', 0x00, 0x54, TRACK_LENGTH & 0xff, TRACK_LENGTH >> 8 };
97	97
98	98	io_generic_write(io, header, SIGNATURE, sizeof(header));
99
	99
100	100	int head = 0;
101	101	int tracks_written = 0;
102	102
r29404	r29405
137	137	io_generic_write_filler(io, 0xff, dpos, TRACK_LENGTH);
138	138	io_generic_write(io, track_length, dpos, 2);
139	139	io_generic_write(io, trackbuf, dpos + 2, track_size);
140
	140
141	141	tracks_written++;
142	142	}
143	143

trunk/src/lib/formats/mbee_cas.h
r29404	r29405
12	12	#include "cassimg.h"
13	13
14	14	CASSETTE_FORMATLIST_EXTERN(mbee_cassette_formats);
15

trunk/src/lib/formats/spc1000_cas.h
r29404	r29405
12	12	#include "cassimg.h"
13	13
14	14	CASSETTE_FORMATLIST_EXTERN(spc1000_cassette_formats);
15

trunk/src/lib/formats/sol_cas.c
r29404	r29405
177	177	}
178	178	return data;
179	179	}
180
	180
181	181	// Turn digits into decimal
182	182	static int sol20_read_dec(const UINT8 *bytes)
183	183	{
r29404	r29405
191	191
192	192	return data;
193	193	}
194
	194
195	195	static int sol20_handle_cassette(INT16 buffer, const UINT8 bytes)
196	196	{
197	197	UINT32 sample_count = 0;
r29404	r29405
283	283	sample_count += sol20_output_byte(buffer, sample_count, sol20_header[i]);
284	284	// write checksum
285	285	sample_count += sol20_output_byte(buffer, sample_count, sol20_cksm_byte);
286
	286
287	287	sol20_cksm_byte = 0;
288	288	process_d = 1;
289	289	sol20_scan_to_eol(bytes);

trunk/src/lib/formats/cassimg.c
r29404	r29405
379	379	/* is this block beyond the edge of our waveform? */
380	380	if (sample_blocknum >= cassette->blocks.count())
381	381	cassette->blocks.resize_keep_and_clear_new(sample_blocknum + 1);
382
	382
383	383	if (cassette->blocks[sample_blocknum] == NULL)
384	384	cassette->blocks[sample_blocknum] = global_alloc(sample_block);
385	385

trunk/src/lib/formats/sol_cas.h
r29404	r29405
12	12	#include "cassimg.h"
13	13
14	14	CASSETTE_FORMATLIST_EXTERN(sol20_cassette_formats);
15

trunk/src/lib/formats/z80ne_dsk.c
r29404	r29405
208	208
209	209	/* set up sector map */
210	210	sector_map.resize_and_clear(sectors, 0xFF);
211
	211
212	212	physical_sector = 0;
213	213	for (logical_sector = 0; logical_sector < sectors; logical_sector++)
214	214	{

trunk/src/lib/formats/fmtowns_dsk.c
r29404	r29405
1	1	/*
2	2	* fmtowns_dsk.c
3	3	*
4		* FM Towns floppy image format
	4	* FM Towns floppy image format
5	5	*
6	6	* Created on: 23/03/2014
7	7	*/

trunk/src/lib/formats/ccvf_dsk.c
r29404	r29405
100	100	astring line;
101	101	offs_t byteoffs = 0;
102	102	char hex[3] = {0};
103
	103
104	104	do {
105	105	end = ccvf.chr(start, 10);
106	106	line.cpysubstr(ccvf, start, end);
107		if (line.find(0, "Compucolor Virtual Floppy Disk Image") && line.find(0, "Label") && line.find(0, "Track")) {
	107	if (line.find(0, "Compucolor Virtual Floppy Disk Image") && line.find(0, "Label") && line.find(0, "Track")) {
108	108	for (int byte = 0; byte < 32; byte++) {
109	109	if (byteoffs==78720) break;
110	110	hex[0]=line[byte * 2];
r29404	r29405
117	117
118	118	UINT64 pos = 0;
119	119	int total_size = 200000000/f.cell_size;
120
	120
121	121	for(int track=0; track < f.track_count; track++) {
122	122	dynamic_array<UINT32> buffer(total_size);
123	123	int offset = 0;
124
	124
125	125	for (int i=0; i<1920 && pos<size; i++, pos++) {
126	126	for (int bit=0; bit<8; bit++) {
127	127	bit_w(buffer, offset++, BIT(bytes[pos], bit), f.cell_size);

trunk/src/lib/formats/sorc_cas.h
r29404	r29405
12	12	#include "cassimg.h"
13	13
14	14	CASSETTE_FORMATLIST_EXTERN(sorcerer_cassette_formats);
15

trunk/src/lib/formats/phc25_cas.c
r29404	r29405
97	97	UINT32 i;
98	98
99	99	// silence
100		// sample_count += phc25_put_samples(buffer, 6640, 2, WAVEENTRY_HIGH);
	100	// sample_count += phc25_put_samples(buffer, 6640, 2, WAVEENTRY_HIGH);
101	101
102	102	/* start */
103		// for (i=0; i<12155; i++)
	103	// for (i=0; i<12155; i++)
104	104	for (i=0; i<2155; i++)
105	105	sample_count += phc25_output_bit(buffer, sample_count, 1);
106	106

trunk/src/lib/formats/phc25_cas.h
r29404	r29405
12	12	#include "cassimg.h"
13	13
14	14	CASSETTE_FORMATLIST_EXTERN(phc25_cassette_formats);
15

trunk/src/lib/libflac/include/FLAC/stream_encoder.h
r29404	r29405
238	238	* must be deleted with FLAC__stream_encoder_delete().
239	239	*/
240	240	typedef enum {
241
242	241	FLAC__STREAM_ENCODER_OK = 0,
243	242	/*< The encoder is in the normal OK state and samples can be processed. /
244	243
r29404	r29405
290	289	/** Possible return values for the FLAC__stream_encoder_init_*() functions.
291	290	*/
292	291	typedef enum {
293
294	292	FLAC__STREAM_ENCODER_INIT_STATUS_OK = 0,
295	293	/*< Initialization was successful. /
296	294
r29404	r29405
360	358	/** Return values for the FLAC__StreamEncoder read callback.
361	359	*/
362	360	typedef enum {
363
364	361	FLAC__STREAM_ENCODER_READ_STATUS_CONTINUE,
365	362	/*< The read was OK and decoding can continue. /
366	363
r29404	r29405
386	383	/** Return values for the FLAC__StreamEncoder write callback.
387	384	*/
388	385	typedef enum {
389
390	386	FLAC__STREAM_ENCODER_WRITE_STATUS_OK = 0,
391	387	/*< The write was OK and encoding can continue. /
392	388
r29404	r29405
406	402	/** Return values for the FLAC__StreamEncoder seek callback.
407	403	*/
408	404	typedef enum {
409
410	405	FLAC__STREAM_ENCODER_SEEK_STATUS_OK,
411	406	/*< The seek was OK and encoding can continue. /
412	407
r29404	r29405
429	424	/** Return values for the FLAC__StreamEncoder tell callback.
430	425	*/
431	426	typedef enum {
432
433	427	FLAC__STREAM_ENCODER_TELL_STATUS_OK,
434	428	/*< The tell was OK and encoding can continue. /
435	429

trunk/src/lib/libflac/include/FLAC/metadata.h
r29404	r29405
306	306	* The iterator's current status can be obtained by calling FLAC__metadata_simple_iterator_status().
307	307	*/
308	308	typedef enum {
309
310	309	FLAC__METADATA_SIMPLE_ITERATOR_STATUS_OK = 0,
311	310	/*< The iterator is in the normal OK state /
312	311
r29404	r29405
763	762	FLAC__METADATA_CHAIN_STATUS_READ_WRITE_MISMATCH,
764	763	/**< FLAC__metadata_chain_write() was called on a chain read by
765	764	* FLAC__metadata_chain_read_with_callbacks()/FLAC__metadata_chain_read_ogg_with_callbacks(),
766		* or
	765	* or
767	766	* FLAC__metadata_chain_write_with_callbacks()/FLAC__metadata_chain_write_with_callbacks_and_tempfile()
768	767	* was called on a chain read by
769	768	* FLAC__metadata_chain_read()/FLAC__metadata_chain_read_ogg().

trunk/src/lib/libflac/include/FLAC/stream_decoder.h
r29404	r29405
199	199	* The decoder's state can be obtained by calling FLAC__stream_decoder_get_state().
200	200	*/
201	201	typedef enum {
202
203	202	FLAC__STREAM_DECODER_SEARCH_FOR_METADATA = 0,
204	203	/*< The decoder is ready to search for metadata. /
205	204
r29404	r29405
253	252	/** Possible return values for the FLAC__stream_decoder_init_*() functions.
254	253	*/
255	254	typedef enum {
256
257	255	FLAC__STREAM_DECODER_INIT_STATUS_OK = 0,
258	256	/*< Initialization was successful. /
259	257
r29404	r29405
291	289	/** Return values for the FLAC__StreamDecoder read callback.
292	290	*/
293	291	typedef enum {
294
295	292	FLAC__STREAM_DECODER_READ_STATUS_CONTINUE,
296	293	/*< The read was OK and decoding can continue. /
297	294
r29404	r29405
322	319	/** Return values for the FLAC__StreamDecoder seek callback.
323	320	*/
324	321	typedef enum {
325
326	322	FLAC__STREAM_DECODER_SEEK_STATUS_OK,
327	323	/*< The seek was OK and decoding can continue. /
328	324
r29404	r29405
345	341	/** Return values for the FLAC__StreamDecoder tell callback.
346	342	*/
347	343	typedef enum {
348
349	344	FLAC__STREAM_DECODER_TELL_STATUS_OK,
350	345	/*< The tell was OK and decoding can continue. /
351	346
r29404	r29405
368	363	/** Return values for the FLAC__StreamDecoder length callback.
369	364	*/
370	365	typedef enum {
371
372	366	FLAC__STREAM_DECODER_LENGTH_STATUS_OK,
373	367	/*< The length call was OK and decoding can continue. /
374	368
r29404	r29405
391	385	/** Return values for the FLAC__StreamDecoder write callback.
392	386	*/
393	387	typedef enum {
394
395	388	FLAC__STREAM_DECODER_WRITE_STATUS_CONTINUE,
396	389	/*< The write was OK and decoding can continue. /
397	390
r29404	r29405
424	417	* a future encoder.
425	418	*/
426	419	typedef enum {
427
428	420	FLAC__STREAM_DECODER_ERROR_STATUS_LOST_SYNC,
429	421	/*< An error in the stream caused the decoder to lose synchronization. /
430	422

trunk/src/lib/libflac/include/FLAC/export.h
r29404	r29405
61	61	#else
62	62
63	63	#ifdef FLAC_API_EXPORTS
64		#define FLAC_API _declspec(dllexport)
	64	#define FLAC_API _declspec(dllexport)
65	65	#else
66		#define FLAC_API _declspec(dllimport)
	66	#define FLAC_API _declspec(dllimport)
67	67
68	68	#endif
69	69	#endif

trunk/src/lib/libflac/include/FLAC/format.h
r29404	r29405
84	84
85	85
86	86	/*
87		Most of the values described in this file are defined by the FLAC
88		format specification. There is nothing to tune here.
	87	Most of the values described in this file are defined by the FLAC
	88	format specification. There is nothing to tune here.
89	89	*/
90	90
91	91	/** The largest legal metadata type code. */
r29404	r29405
211	211	/** Contents of a Rice partitioned residual
212	212	*/
213	213	typedef struct {
214
215	214	unsigned *parameters;
216	215	/*< The Rice parameters for each context. /
217	216
r29404	r29405
230	229	/** Header for a Rice partitioned residual. (c.f. <A HREF="../format.html#partitioned_rice">format specification</A>)
231	230	*/
232	231	typedef struct {
233
234	232	unsigned order;
235	233	/*< The partition order, i.e. # of contexts = 2 ^ \a order. /
236	234
r29404	r29405
486	484
487	485	/** An enumeration of the available metadata block types. */
488	486	typedef enum {
489
490	487	FLAC__METADATA_TYPE_STREAMINFO = 0,
491	488	/*< <A HREF="../format.html#metadata_block_streaminfo">STREAMINFO</A> block /
492	489

trunk/src/lib/libflac/include/private/float.h
r29404	r29405
74	74	#define FLAC__fixedpoint_div(x, y) ( (FLAC__fixedpoint) ( ( ((FLAC__int64)(x)<<32) / (FLAC__int64)(y) ) >> 16 ) )
75	75
76	76	/*
77		* FLAC__fixedpoint_log2()
78		* --------------------------------------------------------------------
79		* Returns the base-2 logarithm of the fixed-point number 'x' using an
80		* algorithm by Knuth for x >= 1.0
	77	* FLAC__fixedpoint_log2()
	78	* --------------------------------------------------------------------
	79	* Returns the base-2 logarithm of the fixed-point number 'x' using an
	80	* algorithm by Knuth for x >= 1.0
81	81	*
82		* 'fracbits' is the number of fractional bits of 'x'. 'fracbits' must
83		* be < 32 and evenly divisible by 4 (0 is OK but not very precise).
	82	* 'fracbits' is the number of fractional bits of 'x'. 'fracbits' must
	83	* be < 32 and evenly divisible by 4 (0 is OK but not very precise).
84	84	*
85		* 'precision' roughly limits the number of iterations that are done;
86		* use (unsigned)(-1) for maximum precision.
	85	* 'precision' roughly limits the number of iterations that are done;
	86	* use (unsigned)(-1) for maximum precision.
87	87	*
88		* If 'x' is less than one -- that is, x < (1<<fracbits) -- then this
89		* function will punt and return 0.
	88	* If 'x' is less than one -- that is, x < (1<<fracbits) -- then this
	89	* function will punt and return 0.
90	90	*
91		* The return value will also have 'fracbits' fractional bits.
	91	* The return value will also have 'fracbits' fractional bits.
92	92	*/
93	93	FLAC__uint32 FLAC__fixedpoint_log2(FLAC__uint32 x, unsigned fracbits, unsigned precision);
94	94

trunk/src/lib/libflac/include/private/window.h
r29404	r29405
42	42	#ifndef FLAC__INTEGER_ONLY_LIBRARY
43	43
44	44	/*
45		* FLAC__window_*()
46		* --------------------------------------------------------------------
47		* Calculates window coefficients according to different apodization
48		* functions.
	45	* FLAC__window_*()
	46	* --------------------------------------------------------------------
	47	* Calculates window coefficients according to different apodization
	48	* functions.
49	49	*
50		* OUT window[0,L-1]
51		* IN L (number of points in window)
	50	* OUT window[0,L-1]
	51	* IN L (number of points in window)
52	52	*/
53	53	void FLAC__window_bartlett(FLAC__real *window, const FLAC__int32 L);
54	54	void FLAC__window_bartlett_hann(FLAC__real *window, const FLAC__int32 L);

trunk/src/lib/libflac/include/private/lpc.h
r29404	r29405
42	42	#ifndef FLAC__INTEGER_ONLY_LIBRARY
43	43
44	44	/*
45		* FLAC__lpc_window_data()
46		* --------------------------------------------------------------------
47		* Applies the given window to the data.
	45	* FLAC__lpc_window_data()
	46	* --------------------------------------------------------------------
	47	* Applies the given window to the data.
48	48	* OPT: asm implementation
49	49	*
50		* IN in[0,data_len-1]
51		* IN window[0,data_len-1]
52		* OUT out[0,lag-1]
53		* IN data_len
	50	* IN in[0,data_len-1]
	51	* IN window[0,data_len-1]
	52	* OUT out[0,lag-1]
	53	* IN data_len
54	54	*/
55	55	void FLAC__lpc_window_data(const FLAC__int32 in[], const FLAC__real window[], FLAC__real out[], unsigned data_len);
56	56
57	57	/*
58		* FLAC__lpc_compute_autocorrelation()
59		* --------------------------------------------------------------------
60		* Compute the autocorrelation for lags between 0 and lag-1.
61		* Assumes data[] outside of [0,data_len-1] == 0.
62		* Asserts that lag > 0.
	58	* FLAC__lpc_compute_autocorrelation()
	59	* --------------------------------------------------------------------
	60	* Compute the autocorrelation for lags between 0 and lag-1.
	61	* Assumes data[] outside of [0,data_len-1] == 0.
	62	* Asserts that lag > 0.
63	63	*
64		* IN data[0,data_len-1]
65		* IN data_len
66		* IN 0 < lag <= data_len
67		* OUT autoc[0,lag-1]
	64	* IN data[0,data_len-1]
	65	* IN data_len
	66	* IN 0 < lag <= data_len
	67	* OUT autoc[0,lag-1]
68	68	*/
69	69	void FLAC__lpc_compute_autocorrelation(const FLAC__real data[], unsigned data_len, unsigned lag, FLAC__real autoc[]);
70	70	#ifndef FLAC__NO_ASM
r29404	r29405
80	80	#endif
81	81
82	82	/*
83		* FLAC__lpc_compute_lp_coefficients()
84		* --------------------------------------------------------------------
85		* Computes LP coefficients for orders 1..max_order.
86		* Do not call if autoc[0] == 0.0. This means the signal is zero
87		* and there is no point in calculating a predictor.
	83	* FLAC__lpc_compute_lp_coefficients()
	84	* --------------------------------------------------------------------
	85	* Computes LP coefficients for orders 1..max_order.
	86	* Do not call if autoc[0] == 0.0. This means the signal is zero
	87	* and there is no point in calculating a predictor.
88	88	*
89		* IN autoc[0,max_order] autocorrelation values
90		* IN 0 < max_order <= FLAC__MAX_LPC_ORDER max LP order to compute
91		* OUT lp_coeff[0,max_order-1][0,max_order-1] LP coefficients for each order
92		* *** IMPORTANT:
93		* *** lp_coeff[0,max_order-1][max_order,FLAC__MAX_LPC_ORDER-1] are untouched
94		* OUT error[0,max_order-1] error for each order (more
95		* specifically, the variance of
96		* the error signal times # of
97		* samples in the signal)
	89	* IN autoc[0,max_order] autocorrelation values
	90	* IN 0 < max_order <= FLAC__MAX_LPC_ORDER max LP order to compute
	91	* OUT lp_coeff[0,max_order-1][0,max_order-1] LP coefficients for each order
	92	* *** IMPORTANT:
	93	* *** lp_coeff[0,max_order-1][max_order,FLAC__MAX_LPC_ORDER-1] are untouched
	94	* OUT error[0,max_order-1] error for each order (more
	95	* specifically, the variance of
	96	* the error signal times # of
	97	* samples in the signal)
98	98	*
99		* Example: if max_order is 9, the LP coefficients for order 9 will be
100		* in lp_coeff[8][0,8], the LP coefficients for order 8 will be
101		* in lp_coeff[7][0,7], etc.
	99	* Example: if max_order is 9, the LP coefficients for order 9 will be
	100	* in lp_coeff[8][0,8], the LP coefficients for order 8 will be
	101	* in lp_coeff[7][0,7], etc.
102	102	*/
103	103	void FLAC__lpc_compute_lp_coefficients(const FLAC__real autoc[], unsigned *max_order, FLAC__real lp_coeff[][FLAC__MAX_LPC_ORDER], FLAC__double error[]);
104	104
105	105	/*
106		* FLAC__lpc_quantize_coefficients()
107		* --------------------------------------------------------------------
108		* Quantizes the LP coefficients. NOTE: precision + bits_per_sample
109		* must be less than 32 (sizeof(FLAC__int32)*8).
	106	* FLAC__lpc_quantize_coefficients()
	107	* --------------------------------------------------------------------
	108	* Quantizes the LP coefficients. NOTE: precision + bits_per_sample
	109	* must be less than 32 (sizeof(FLAC__int32)*8).
110	110	*
111		* IN lp_coeff[0,order-1] LP coefficients
112		* IN order LP order
113		* IN FLAC__MIN_QLP_COEFF_PRECISION < precision
114		* desired precision (in bits, including sign
115		* bit) of largest coefficient
116		* OUT qlp_coeff[0,order-1] quantized coefficients
117		* OUT shift # of bits to shift right to get approximated
118		* LP coefficients. NOTE: could be negative.
119		* RETURN 0 => quantization OK
120		* 1 => coefficients require too much shifting for *shift to
	111	* IN lp_coeff[0,order-1] LP coefficients
	112	* IN order LP order
	113	* IN FLAC__MIN_QLP_COEFF_PRECISION < precision
	114	* desired precision (in bits, including sign
	115	* bit) of largest coefficient
	116	* OUT qlp_coeff[0,order-1] quantized coefficients
	117	* OUT shift # of bits to shift right to get approximated
	118	* LP coefficients. NOTE: could be negative.
	119	* RETURN 0 => quantization OK
	120	* 1 => coefficients require too much shifting for *shift to
121	121	* fit in the LPC subframe header. 'shift' is unset.
122	122	* 2 => coefficients are all zero, which is bad. 'shift' is
123	123	* unset.
r29404	r29405
125	125	int FLAC__lpc_quantize_coefficients(const FLAC__real lp_coeff[], unsigned order, unsigned precision, FLAC__int32 qlp_coeff[], int *shift);
126	126
127	127	/*
128		* FLAC__lpc_compute_residual_from_qlp_coefficients()
129		* --------------------------------------------------------------------
130		* Compute the residual signal obtained from sutracting the predicted
131		* signal from the original.
	128	* FLAC__lpc_compute_residual_from_qlp_coefficients()
	129	* --------------------------------------------------------------------
	130	* Compute the residual signal obtained from sutracting the predicted
	131	* signal from the original.
132	132	*
133		* IN data[-order,data_len-1] original signal (NOTE THE INDICES!)
134		* IN data_len length of original signal
135		* IN qlp_coeff[0,order-1] quantized LP coefficients
136		* IN order > 0 LP order
137		* IN lp_quantization quantization of LP coefficients in bits
138		* OUT residual[0,data_len-1] residual signal
	133	* IN data[-order,data_len-1] original signal (NOTE THE INDICES!)
	134	* IN data_len length of original signal
	135	* IN qlp_coeff[0,order-1] quantized LP coefficients
	136	* IN order > 0 LP order
	137	* IN lp_quantization quantization of LP coefficients in bits
	138	* OUT residual[0,data_len-1] residual signal
139	139	*/
140	140	void FLAC__lpc_compute_residual_from_qlp_coefficients(const FLAC__int32 *data, unsigned data_len, const FLAC__int32 qlp_coeff[], unsigned order, int lp_quantization, FLAC__int32 residual[]);
141	141	void FLAC__lpc_compute_residual_from_qlp_coefficients_wide(const FLAC__int32 *data, unsigned data_len, const FLAC__int32 qlp_coeff[], unsigned order, int lp_quantization, FLAC__int32 residual[]);
r29404	r29405
151	151	#endif /* !defined FLAC__INTEGER_ONLY_LIBRARY */
152	152
153	153	/*
154		* FLAC__lpc_restore_signal()
155		* --------------------------------------------------------------------
156		* Restore the original signal by summing the residual and the
157		* predictor.
	154	* FLAC__lpc_restore_signal()
	155	* --------------------------------------------------------------------
	156	* Restore the original signal by summing the residual and the
	157	* predictor.
158	158	*
159		* IN residual[0,data_len-1] residual signal
160		* IN data_len length of original signal
161		* IN qlp_coeff[0,order-1] quantized LP coefficients
162		* IN order > 0 LP order
163		* IN lp_quantization quantization of LP coefficients in bits
164		* *** IMPORTANT: the caller must pass in the historical samples:
165		* IN data[-order,-1] previously-reconstructed historical samples
166		* OUT data[0,data_len-1] original signal
	159	* IN residual[0,data_len-1] residual signal
	160	* IN data_len length of original signal
	161	* IN qlp_coeff[0,order-1] quantized LP coefficients
	162	* IN order > 0 LP order
	163	* IN lp_quantization quantization of LP coefficients in bits
	164	* *** IMPORTANT: the caller must pass in the historical samples:
	165	* IN data[-order,-1] previously-reconstructed historical samples
	166	* OUT data[0,data_len-1] original signal
167	167	*/
168	168	void FLAC__lpc_restore_signal(const FLAC__int32 residual[], unsigned data_len, const FLAC__int32 qlp_coeff[], unsigned order, int lp_quantization, FLAC__int32 data[]);
169	169	void FLAC__lpc_restore_signal_wide(const FLAC__int32 residual[], unsigned data_len, const FLAC__int32 qlp_coeff[], unsigned order, int lp_quantization, FLAC__int32 data[]);
r29404	r29405
182	182	#ifndef FLAC__INTEGER_ONLY_LIBRARY
183	183
184	184	/*
185		* FLAC__lpc_compute_expected_bits_per_residual_sample()
186		* --------------------------------------------------------------------
187		* Compute the expected number of bits per residual signal sample
188		* based on the LP error (which is related to the residual variance).
	185	* FLAC__lpc_compute_expected_bits_per_residual_sample()
	186	* --------------------------------------------------------------------
	187	* Compute the expected number of bits per residual signal sample
	188	* based on the LP error (which is related to the residual variance).
189	189	*
190		* IN lpc_error >= 0.0 error returned from calculating LP coefficients
191		* IN total_samples > 0 # of samples in residual signal
192		* RETURN expected bits per sample
	190	* IN lpc_error >= 0.0 error returned from calculating LP coefficients
	191	* IN total_samples > 0 # of samples in residual signal
	192	* RETURN expected bits per sample
193	193	*/
194	194	FLAC__double FLAC__lpc_compute_expected_bits_per_residual_sample(FLAC__double lpc_error, unsigned total_samples);
195	195	FLAC__double FLAC__lpc_compute_expected_bits_per_residual_sample_with_error_scale(FLAC__double lpc_error, FLAC__double error_scale);
196	196
197	197	/*
198		* FLAC__lpc_compute_best_order()
199		* --------------------------------------------------------------------
200		* Compute the best order from the array of signal errors returned
201		* during coefficient computation.
	198	* FLAC__lpc_compute_best_order()
	199	* --------------------------------------------------------------------
	200	* Compute the best order from the array of signal errors returned
	201	* during coefficient computation.
202	202	*
203		* IN lpc_error[0,max_order-1] >= 0.0 error returned from calculating LP coefficients
204		* IN max_order > 0 max LP order
205		* IN total_samples > 0 # of samples in residual signal
206		* IN overhead_bits_per_order # of bits overhead for each increased LP order
207		* (includes warmup sample size and quantized LP coefficient)
208		* RETURN [1,max_order] best order
	203	* IN lpc_error[0,max_order-1] >= 0.0 error returned from calculating LP coefficients
	204	* IN max_order > 0 max LP order
	205	* IN total_samples > 0 # of samples in residual signal
	206	* IN overhead_bits_per_order # of bits overhead for each increased LP order
	207	* (includes warmup sample size and quantized LP coefficient)
	208	* RETURN [1,max_order] best order
209	209	*/
210	210	unsigned FLAC__lpc_compute_best_order(const FLAC__double lpc_error[], unsigned max_order, unsigned total_samples, unsigned overhead_bits_per_order);
211	211

trunk/src/lib/libflac/include/private/fixed.h
r29404	r29405
40	40	#include "FLAC/format.h"
41	41
42	42	/*
43		* FLAC__fixed_compute_best_predictor()
44		* --------------------------------------------------------------------
45		* Compute the best fixed predictor and the expected bits-per-sample
	43	* FLAC__fixed_compute_best_predictor()
	44	* --------------------------------------------------------------------
	45	* Compute the best fixed predictor and the expected bits-per-sample
46	46	* of the residual signal for each order. The _wide() version uses
47	47	* 64-bit integers which is statistically necessary when bits-per-
48	48	* sample + log2(blocksize) > 30
49	49	*
50		* IN data[0,data_len-1]
51		* IN data_len
52		* OUT residual_bits_per_sample[0,FLAC__MAX_FIXED_ORDER]
	50	* IN data[0,data_len-1]
	51	* IN data_len
	52	* OUT residual_bits_per_sample[0,FLAC__MAX_FIXED_ORDER]
53	53	*/
54	54	#ifndef FLAC__INTEGER_ONLY_LIBRARY
55	55	unsigned FLAC__fixed_compute_best_predictor(const FLAC__int32 data[], unsigned data_len, FLAC__float residual_bits_per_sample[FLAC__MAX_FIXED_ORDER+1]);
r29404	r29405
67	67	#endif
68	68
69	69	/*
70		* FLAC__fixed_compute_residual()
71		* --------------------------------------------------------------------
72		* Compute the residual signal obtained from sutracting the predicted
73		* signal from the original.
	70	* FLAC__fixed_compute_residual()
	71	* --------------------------------------------------------------------
	72	* Compute the residual signal obtained from sutracting the predicted
	73	* signal from the original.
74	74	*
75		* IN data[-order,data_len-1] original signal (NOTE THE INDICES!)
76		* IN data_len length of original signal
77		* IN order <= FLAC__MAX_FIXED_ORDER fixed-predictor order
78		* OUT residual[0,data_len-1] residual signal
	75	* IN data[-order,data_len-1] original signal (NOTE THE INDICES!)
	76	* IN data_len length of original signal
	77	* IN order <= FLAC__MAX_FIXED_ORDER fixed-predictor order
	78	* OUT residual[0,data_len-1] residual signal
79	79	*/
80	80	void FLAC__fixed_compute_residual(const FLAC__int32 data[], unsigned data_len, unsigned order, FLAC__int32 residual[]);
81	81
82	82	/*
83		* FLAC__fixed_restore_signal()
84		* --------------------------------------------------------------------
85		* Restore the original signal by summing the residual and the
86		* predictor.
	83	* FLAC__fixed_restore_signal()
	84	* --------------------------------------------------------------------
	85	* Restore the original signal by summing the residual and the
	86	* predictor.
87	87	*
88		* IN residual[0,data_len-1] residual signal
89		* IN data_len length of original signal
90		* IN order <= FLAC__MAX_FIXED_ORDER fixed-predictor order
91		* *** IMPORTANT: the caller must pass in the historical samples:
92		* IN data[-order,-1] previously-reconstructed historical samples
93		* OUT data[0,data_len-1] original signal
	88	* IN residual[0,data_len-1] residual signal
	89	* IN data_len length of original signal
	90	* IN order <= FLAC__MAX_FIXED_ORDER fixed-predictor order
	91	* *** IMPORTANT: the caller must pass in the historical samples:
	92	* IN data[-order,-1] previously-reconstructed historical samples
	93	* OUT data[0,data_len-1] original signal
94	94	*/
95	95	void FLAC__fixed_restore_signal(const FLAC__int32 residual[], unsigned data_len, unsigned order, FLAC__int32 data[]);
96	96

trunk/src/lib/libflac/libFLAC/bitreader.c
r29404	r29405
301	301	FLAC__BitReader br = (FLAC__BitReader)calloc(1, sizeof(FLAC__BitReader));
302	302
303	303	/* calloc() implies:
304		memset(br, 0, sizeof(FLAC__BitReader));
305		br->buffer = 0;
306		br->capacity = 0;
307		br->words = br->bytes = 0;
308		br->consumed_words = br->consumed_bits = 0;
309		br->read_callback = 0;
310		br->client_data = 0;
	304	memset(br, 0, sizeof(FLAC__BitReader));
	305	br->buffer = 0;
	306	br->capacity = 0;
	307	br->words = br->bytes = 0;
	308	br->consumed_words = br->consumed_bits = 0;
	309	br->read_callback = 0;
	310	br->client_data = 0;
311	311	*/
312	312	return br;
313	313	}
r29404	r29405
835	835	cwords = br->consumed_words;
836	836
837	837	while(1) {
838
839	838	/* read unary part */
840	839	while(1) {
841	840	while(cwords < br->words) { /* if we've not consumed up to a partial tail word... */
r29404	r29405
1018	1017	ucbits = (br->words-cwords)FLAC__BITS_PER_WORD + br->bytes8 - cbits;
1019	1018
1020	1019	while(1) {
1021
1022	1020	/* read unary part */
1023	1021	while(1) {
1024	1022	while(cwords < br->words) { /* if we've not consumed up to a partial tail word... */

trunk/src/lib/libflac/libFLAC/float.c
r29404	r29405
282	282
283	283	if(x < ONE)
284	284	return 0;
285
	285
286	286	if(precision > LOG2_LOOKUP_PRECISION)
287	287	precision = LOG2_LOOKUP_PRECISION;
288	288

trunk/src/lib/libflac/libFLAC/metadata_object.c
r29404	r29405
1330	1330	memcpy(entry->entry+nn+1, field_value, nv);
1331	1331	entry->entry[entry->length] = '\0';
1332	1332	}
1333
	1333
1334	1334	return true;
1335	1335	}
1336	1336

trunk/src/lib/libflac/libFLAC/metadata_iterators.c
r29404	r29405
1835	1835	FLAC__Metadata_Iterator iterator = (FLAC__Metadata_Iterator)calloc(1, sizeof(FLAC__Metadata_Iterator));
1836	1836
1837	1837	/* calloc() implies:
1838		iterator->current = 0;
1839		iterator->chain = 0;
	1838	iterator->current = 0;
	1839	iterator->chain = 0;
1840	1840	*/
1841	1841
1842	1842	return iterator;

trunk/src/lib/libflac/libFLAC/lpc.c
r29404	r29405
305	305
306	306	/* Here's a slower but clearer version:
307	307	for(i = 0; i < data_len; i++) {
308		sum = 0;
309		for(j = 0; j < order; j++)
310		sum += qlp_coeff[j] * data[i-j-1];
311		residual[i] = data[i] - (sum >> lp_quantization);
	308	sum = 0;
	309	for(j = 0; j < order; j++)
	310	sum += qlp_coeff[j] * data[i-j-1];
	311	residual[i] = data[i] - (sum >> lp_quantization);
312	312	}
313	313	*/
314	314	}
r29404	r29405
516	516	case 15: sum += qlp_coeff[14] * data[i-15];
517	517	case 14: sum += qlp_coeff[13] * data[i-14];
518	518	case 13: sum += qlp_coeff[12] * data[i-13];
519		sum += qlp_coeff[11] * data[i-12];
520		sum += qlp_coeff[10] * data[i-11];
521		sum += qlp_coeff[ 9] * data[i-10];
522		sum += qlp_coeff[ 8] * data[i- 9];
523		sum += qlp_coeff[ 7] * data[i- 8];
524		sum += qlp_coeff[ 6] * data[i- 7];
525		sum += qlp_coeff[ 5] * data[i- 6];
526		sum += qlp_coeff[ 4] * data[i- 5];
527		sum += qlp_coeff[ 3] * data[i- 4];
528		sum += qlp_coeff[ 2] * data[i- 3];
529		sum += qlp_coeff[ 1] * data[i- 2];
530		sum += qlp_coeff[ 0] * data[i- 1];
	519	sum += qlp_coeff[11] * data[i-12];
	520	sum += qlp_coeff[10] * data[i-11];
	521	sum += qlp_coeff[ 9] * data[i-10];
	522	sum += qlp_coeff[ 8] * data[i- 9];
	523	sum += qlp_coeff[ 7] * data[i- 8];
	524	sum += qlp_coeff[ 6] * data[i- 7];
	525	sum += qlp_coeff[ 5] * data[i- 6];
	526	sum += qlp_coeff[ 4] * data[i- 5];
	527	sum += qlp_coeff[ 3] * data[i- 4];
	528	sum += qlp_coeff[ 2] * data[i- 3];
	529	sum += qlp_coeff[ 1] * data[i- 2];
	530	sum += qlp_coeff[ 0] * data[i- 1];
531	531	}
532	532	residual[i] = data[i] - (sum >> lp_quantization);
533	533	}
r29404	r29405
778	778	case 15: sum += qlp_coeff[14] * (FLAC__int64)data[i-15];
779	779	case 14: sum += qlp_coeff[13] * (FLAC__int64)data[i-14];
780	780	case 13: sum += qlp_coeff[12] * (FLAC__int64)data[i-13];
781		sum += qlp_coeff[11] * (FLAC__int64)data[i-12];
782		sum += qlp_coeff[10] * (FLAC__int64)data[i-11];
783		sum += qlp_coeff[ 9] * (FLAC__int64)data[i-10];
784		sum += qlp_coeff[ 8] * (FLAC__int64)data[i- 9];
785		sum += qlp_coeff[ 7] * (FLAC__int64)data[i- 8];
786		sum += qlp_coeff[ 6] * (FLAC__int64)data[i- 7];
787		sum += qlp_coeff[ 5] * (FLAC__int64)data[i- 6];
788		sum += qlp_coeff[ 4] * (FLAC__int64)data[i- 5];
789		sum += qlp_coeff[ 3] * (FLAC__int64)data[i- 4];
790		sum += qlp_coeff[ 2] * (FLAC__int64)data[i- 3];
791		sum += qlp_coeff[ 1] * (FLAC__int64)data[i- 2];
792		sum += qlp_coeff[ 0] * (FLAC__int64)data[i- 1];
	781	sum += qlp_coeff[11] * (FLAC__int64)data[i-12];
	782	sum += qlp_coeff[10] * (FLAC__int64)data[i-11];
	783	sum += qlp_coeff[ 9] * (FLAC__int64)data[i-10];
	784	sum += qlp_coeff[ 8] * (FLAC__int64)data[i- 9];
	785	sum += qlp_coeff[ 7] * (FLAC__int64)data[i- 8];
	786	sum += qlp_coeff[ 6] * (FLAC__int64)data[i- 7];
	787	sum += qlp_coeff[ 5] * (FLAC__int64)data[i- 6];
	788	sum += qlp_coeff[ 4] * (FLAC__int64)data[i- 5];
	789	sum += qlp_coeff[ 3] * (FLAC__int64)data[i- 4];
	790	sum += qlp_coeff[ 2] * (FLAC__int64)data[i- 3];
	791	sum += qlp_coeff[ 1] * (FLAC__int64)data[i- 2];
	792	sum += qlp_coeff[ 0] * (FLAC__int64)data[i- 1];
793	793	}
794	794	residual[i] = data[i] - (FLAC__int32)(sum >> lp_quantization);
795	795	}
r29404	r29405
835	835
836	836	/* Here's a slower but clearer version:
837	837	for(i = 0; i < data_len; i++) {
838		sum = 0;
839		for(j = 0; j < order; j++)
840		sum += qlp_coeff[j] * data[i-j-1];
841		data[i] = residual[i] + (sum >> lp_quantization);
	838	sum = 0;
	839	for(j = 0; j < order; j++)
	840	sum += qlp_coeff[j] * data[i-j-1];
	841	data[i] = residual[i] + (sum >> lp_quantization);
842	842	}
843	843	*/
844	844	}
r29404	r29405
1046	1046	case 15: sum += qlp_coeff[14] * data[i-15];
1047	1047	case 14: sum += qlp_coeff[13] * data[i-14];
1048	1048	case 13: sum += qlp_coeff[12] * data[i-13];
1049		sum += qlp_coeff[11] * data[i-12];
1050		sum += qlp_coeff[10] * data[i-11];
1051		sum += qlp_coeff[ 9] * data[i-10];
1052		sum += qlp_coeff[ 8] * data[i- 9];
1053		sum += qlp_coeff[ 7] * data[i- 8];
1054		sum += qlp_coeff[ 6] * data[i- 7];
1055		sum += qlp_coeff[ 5] * data[i- 6];
1056		sum += qlp_coeff[ 4] * data[i- 5];
1057		sum += qlp_coeff[ 3] * data[i- 4];
1058		sum += qlp_coeff[ 2] * data[i- 3];
1059		sum += qlp_coeff[ 1] * data[i- 2];
1060		sum += qlp_coeff[ 0] * data[i- 1];
	1049	sum += qlp_coeff[11] * data[i-12];
	1050	sum += qlp_coeff[10] * data[i-11];
	1051	sum += qlp_coeff[ 9] * data[i-10];
	1052	sum += qlp_coeff[ 8] * data[i- 9];
	1053	sum += qlp_coeff[ 7] * data[i- 8];
	1054	sum += qlp_coeff[ 6] * data[i- 7];
	1055	sum += qlp_coeff[ 5] * data[i- 6];
	1056	sum += qlp_coeff[ 4] * data[i- 5];
	1057	sum += qlp_coeff[ 3] * data[i- 4];
	1058	sum += qlp_coeff[ 2] * data[i- 3];
	1059	sum += qlp_coeff[ 1] * data[i- 2];
	1060	sum += qlp_coeff[ 0] * data[i- 1];
1061	1061	}
1062	1062	data[i] = residual[i] + (sum >> lp_quantization);
1063	1063	}
r29404	r29405
1308	1308	case 15: sum += qlp_coeff[14] * (FLAC__int64)data[i-15];
1309	1309	case 14: sum += qlp_coeff[13] * (FLAC__int64)data[i-14];
1310	1310	case 13: sum += qlp_coeff[12] * (FLAC__int64)data[i-13];
1311		sum += qlp_coeff[11] * (FLAC__int64)data[i-12];
1312		sum += qlp_coeff[10] * (FLAC__int64)data[i-11];
1313		sum += qlp_coeff[ 9] * (FLAC__int64)data[i-10];
1314		sum += qlp_coeff[ 8] * (FLAC__int64)data[i- 9];
1315		sum += qlp_coeff[ 7] * (FLAC__int64)data[i- 8];
1316		sum += qlp_coeff[ 6] * (FLAC__int64)data[i- 7];
1317		sum += qlp_coeff[ 5] * (FLAC__int64)data[i- 6];
1318		sum += qlp_coeff[ 4] * (FLAC__int64)data[i- 5];
1319		sum += qlp_coeff[ 3] * (FLAC__int64)data[i- 4];
1320		sum += qlp_coeff[ 2] * (FLAC__int64)data[i- 3];
1321		sum += qlp_coeff[ 1] * (FLAC__int64)data[i- 2];
1322		sum += qlp_coeff[ 0] * (FLAC__int64)data[i- 1];
	1311	sum += qlp_coeff[11] * (FLAC__int64)data[i-12];
	1312	sum += qlp_coeff[10] * (FLAC__int64)data[i-11];
	1313	sum += qlp_coeff[ 9] * (FLAC__int64)data[i-10];
	1314	sum += qlp_coeff[ 8] * (FLAC__int64)data[i- 9];
	1315	sum += qlp_coeff[ 7] * (FLAC__int64)data[i- 8];
	1316	sum += qlp_coeff[ 6] * (FLAC__int64)data[i- 7];
	1317	sum += qlp_coeff[ 5] * (FLAC__int64)data[i- 6];
	1318	sum += qlp_coeff[ 4] * (FLAC__int64)data[i- 5];
	1319	sum += qlp_coeff[ 3] * (FLAC__int64)data[i- 4];
	1320	sum += qlp_coeff[ 2] * (FLAC__int64)data[i- 3];
	1321	sum += qlp_coeff[ 1] * (FLAC__int64)data[i- 2];
	1322	sum += qlp_coeff[ 0] * (FLAC__int64)data[i- 1];
1323	1323	}
1324	1324	data[i] = residual[i] + (FLAC__int32)(sum >> lp_quantization);
1325	1325	}

trunk/src/lib/libflac/libFLAC/stream_decoder.c
r29404	r29405
1290	1290	*/
1291	1291	#if defined _MSC_VER \|\| defined __MINGW32__
1292	1292	_setmode(_fileno(stdin), _O_BINARY);
1293		#elif defined __CYGWIN__
	1293	#elif defined __CYGWIN__
1294	1294	/* almost certainly not needed for any modern Cygwin, but let's be safe... */
1295	1295	setmode(_fileno(stdin), _O_BINARY);
1296	1296	#elif defined __EMX__
r29404	r29405
3152	3152	}
3153	3153	/* our last move backwards wasn't big enough, try again */
3154	3154	approx_bytes_per_frame = approx_bytes_per_frame? approx_bytes_per_frame * 2 : 16;
3155		continue;
	3155	continue;
3156	3156	}
3157	3157	/* allow one seek over upper bound, so we can get a correct upper_bound_sample for streams with unknown total_samples */
3158	3158	first_seek = false;
3159
	3159
3160	3160	/* make sure we are not seeking in corrupted stream */
3161	3161	if (this_frame_sample < lower_bound_sample) {
3162	3162	decoder->protected_->state = FLAC__STREAM_DECODER_SEEK_ERROR;
r29404	r29405
3196	3196	FLAC__bool did_a_seek;
3197	3197	unsigned iteration = 0;
3198	3198
3199		/* In the first iterations, we will calculate the target byte position
	3199	/* In the first iterations, we will calculate the target byte position
3200	3200	* by the distance from the target sample to left_sample and
3201	3201	* right_sample (let's call it "proportional search"). After that, we
3202	3202	* will switch to binary search.

trunk/src/lib/libflac/libFLAC/md5.c
r29404	r29405
2	2	# include <config.h>
3	3	#endif
4	4
5		#include <stdlib.h> /* for malloc() */
6		#include <string.h> /* for memcpy() */
	5	#include <stdlib.h> /* for malloc() */
	6	#include <string.h> /* for memcpy() */
7	7
8	8	#include "private/md5.h"
9	9	#include "share/alloc.h"
r29404	r29405
47	47
48	48	/* This is the central step in the MD5 algorithm. */
49	49	#define MD5STEP(f,w,x,y,z,in,s) \
50		(w += f(x,y,z) + in, w = (w<<s \| w>>(32-s)) + x)
	50	(w += f(x,y,z) + in, w = (w<<s \| w>>(32-s)) + x)
51	51
52	52	/*
53	53	* The core of the MD5 algorithm, this alters an existing MD5 hash to
r29404	r29405
143	143	{
144	144	register FLAC__uint32 x;
145	145	do {
146		x = *buf;
	146	x = *buf;
147	147	x = ((x << 8) & 0xff00ff00) \| ((x >> 8) & 0x00ff00ff);
148	148	*buf++ = (x >> 16) \| (x << 16);
149	149	} while (--words);
r29404	r29405
186	186
187	187	t = ctx->bytes[0];
188	188	if ((ctx->bytes[0] = t + len) < t)
189		ctx->bytes[1]++; /* Carry from low to high */
	189	ctx->bytes[1]++; /* Carry from low to high */
190	190
191		t = 64 - (t & 0x3f); /* Space available in ctx->in (at least 1) */
	191	t = 64 - (t & 0x3f); /* Space available in ctx->in (at least 1) */
192	192	if (t > len) {
193	193	memcpy((FLAC__byte *)ctx->in + 64 - t, buf, len);
194	194	return;
r29404	r29405
237	237	*/
238	238	void FLAC__MD5Final(FLAC__byte digest[16], FLAC__MD5Context *ctx)
239	239	{
240		int count = ctx->bytes[0] & 0x3f; /* Number of bytes in ctx->in */
	240	int count = ctx->bytes[0] & 0x3f; /* Number of bytes in ctx->in */
241	241	FLAC__byte p = (FLAC__byte )ctx->in + count;
242	242
243	243	/* Set the first char of padding to 0x80. There is always room. */
r29404	r29405
246	246	/* Bytes of padding needed to make 56 bytes (-8..55) */
247	247	count = 56 - 1 - count;
248	248
249		if (count < 0) { /* Padding forces an extra block */
	249	if (count < 0) { /* Padding forces an extra block */
250	250	memset(p, 0, count + 8);
251	251	byteSwapX16(ctx->in);
252	252	FLAC__MD5Transform(ctx->buf, ctx->in);

trunk/src/lib/libflac/libFLAC/stream_encoder.c
r29404	r29405
98	98	* parameter estimation in this encoder is very good, almost always
99	99	* yielding compression within 0.1% of the optimal parameters.
100	100	*/
101		#undef ENABLE_RICE_PARAMETER_SEARCH
	101	#undef ENABLE_RICE_PARAMETER_SEARCH
102	102
103	103
104	104	typedef struct {
r29404	r29405
234	234	#endif
235	235
236	236	static unsigned evaluate_verbatim_subframe_(
237		FLAC__StreamEncoder *encoder,
	237	FLAC__StreamEncoder *encoder,
238	238	const FLAC__int32 signal[],
239	239	unsigned blocksize,
240	240	unsigned subframe_bps,
r29404	r29405
835	835	metadata_picture_has_type1 = true;
836	836	/* standard icon must be 32x32 pixel PNG */
837	837	if(
838		m->data.picture.type == FLAC__STREAM_METADATA_PICTURE_TYPE_FILE_ICON_STANDARD &&
	838	m->data.picture.type == FLAC__STREAM_METADATA_PICTURE_TYPE_FILE_ICON_STANDARD &&
839	839	(
840	840	(strcmp(m->data.picture.mime_type, "image/png") && strcmp(m->data.picture.mime_type, "-->")) \|\|
841	841	m->data.picture.width != 32 \|\|
r29404	r29405
1182	1182	/is_ogg=/true
1183	1183	);
1184	1184	}
1185
	1185
1186	1186	static FLAC__StreamEncoderInitStatus init_FILE_internal_(
1187	1187	FLAC__StreamEncoder *encoder,
1188	1188	FILE *file,
r29404	r29405
1244	1244
1245	1245	return init_status;
1246	1246	}
1247
	1247
1248	1248	FLAC_API FLAC__StreamEncoderInitStatus FLAC__stream_encoder_init_FILE(
1249	1249	FLAC__StreamEncoder *encoder,
1250	1250	FILE *file,
r29404	r29405
1254	1254	{
1255	1255	return init_FILE_internal_(encoder, file, progress_callback, client_data, /is_ogg=/false);
1256	1256	}
1257
	1257
1258	1258	FLAC_API FLAC__StreamEncoderInitStatus FLAC__stream_encoder_init_ogg_FILE(
1259	1259	FLAC__StreamEncoder *encoder,
1260	1260	FILE *file,
r29404	r29405
4134	4134
4135	4135	if(shift > 0) {
4136	4136	for(i = 0; i < samples; i++)
4137		signal[i] >>= shift;
	4137	signal[i] >>= shift;
4138	4138	}
4139	4139
4140	4140	return shift;

trunk/src/lib/util/corealloc.c
r29404	r29405
46	46	const char * m_file; // file the allocation was made from
47	47	int m_line; // line number within that file
48	48	UINT64 m_id; // unique id
49		bool m_array; // array?
	49	bool m_array; // array?
50	50
51	51	// hashing prime number
52	52	static const int k_hash_prime = 6151;
r29404	r29405
115	115	if (clear)
116	116	memset(result, 0, size);
117	117	else
118		{
	118	{
119	119	#if !__has_feature(memory_sanitizer) && defined(INITIALIZE_ALLOCATED_MEMORY)
120	120	memset(result, 0xdd, size);
121	121	#endif
r29404	r29405
145	145	osd_break_into_debugger("Error: attempt to free untracked memory");
146	146	return;
147	147	}
148
	148
149	149	// warn about mismatched arrays
150	150	if (!array && entry->m_array)
151	151	{
r29404	r29405
182	182
183	183
184	184	//-------------------------------------------------
185		// next_memory_id - return the ID of the next
186		// allocated block
	185	// next_memory_id - return the ID of the next
	186	// allocated block
187	187	//-------------------------------------------------
188	188
189	189	UINT64 next_memory_id()

trunk/src/lib/util/tagmap.c
r29404	r29405
12	12
13	13	#ifdef MAME_DEBUG
14	14	INT32 g_tagmap_finds = 0;
15		#endif
		No newline at end of file
	15	#endif

trunk/src/lib/util/tagmap.h
r29404	r29405
203	203	tagged_list &operator=(const tagged_list &);
204	204
205	205	public:
206		class add_exception
	206	class add_exception
207	207	{
208	208	public:
209	209	add_exception(const char *tag) : m_tag(tag) { }
r29404	r29405
211	211	private:
212	212	const char *m_tag;
213	213	};
214
	214
215	215	// construction
216	216	tagged_list() { }
217	217

trunk/src/lib/util/palette.c
r29404	r29405
47	47
48	48	palette_client::dirty_state::dirty_state()
49	49	: m_mindirty(0),
50		m_maxdirty(0)
	50	m_maxdirty(0)
51	51	{
52	52	}
53	53
54	54
55	55	//-------------------------------------------------
56	56	// dirty_list - return the current list and
57		// min/max values
	57	// min/max values
58	58	//-------------------------------------------------
59	59
60	60	const UINT32 *palette_client::dirty_state::dirty_list(UINT32 &mindirty, UINT32 &maxdirty)
r29404	r29405
70	70
71	71	//-------------------------------------------------
72	72	// resize - resize the dirty array and mark all
73		// dirty
	73	// dirty
74	74	//-------------------------------------------------
75	75
76	76	void palette_client::dirty_state::resize(UINT32 colors)
r29404	r29405
82	82	// mark all entries dirty
83	83	m_dirty[dirty_dwords - 1] &= (1 << (colors % 32)) - 1;
84	84
85		// set min/max
	85	// set min/max
86	86	m_mindirty = 0;
87	87	m_maxdirty = colors - 1;
88	88	}
r29404	r29405
102	102
103	103	//-------------------------------------------------
104	104	// reset - clear the dirty array to mark all
105		// entries as clean
	105	// entries as clean
106	106	//-------------------------------------------------
107	107
108	108	void palette_client::dirty_state::reset()
r29404	r29405
125	125
126	126	palette_client::palette_client(palette_t &palette)
127	127	: m_palette(palette),
128		m_next(NULL),
129		m_live(&m_dirty[0]),
130		m_previous(&m_dirty[1])
	128	m_next(NULL),
	129	m_live(&m_dirty[0]),
	130	m_previous(&m_dirty[1])
131	131	{
132	132	// add a reference to the palette
133	133	palette.ref();
r29404	r29405
163	163
164	164
165	165	//-------------------------------------------------
166		// dirty_list - atomically get the current dirty
	166	// dirty_list - atomically get the current dirty
167	167	// list for a client
168	168	//-------------------------------------------------
169	169
r29404	r29405
206	206
207	207	palette_t::palette_t(UINT32 numcolors, UINT32 numgroups)
208	208	: m_refcount(1),
209		m_numcolors(numcolors),
210		m_numgroups(numgroups),
211		m_brightness(0.0f),
212		m_contrast(1.0f),
213		m_gamma(1.0f),
214		m_entry_color(numcolors),
215		m_entry_contrast(numcolors),
216		m_adjusted_color(numcolors * numgroups + 2),
217		m_adjusted_rgb15(numcolors * numgroups + 2),
218		m_group_bright(numgroups),
219		m_group_contrast(numgroups),
220		m_client_list(NULL)
	209	m_numcolors(numcolors),
	210	m_numgroups(numgroups),
	211	m_brightness(0.0f),
	212	m_contrast(1.0f),
	213	m_gamma(1.0f),
	214	m_entry_color(numcolors),
	215	m_entry_contrast(numcolors),
	216	m_adjusted_color(numcolors * numgroups + 2),
	217	m_adjusted_rgb15(numcolors * numgroups + 2),
	218	m_group_bright(numgroups),
	219	m_group_contrast(numgroups),
	220	m_client_list(NULL)
221	221	{
222	222	// initialize gamma map
223	223	for (UINT32 index = 0; index < 256; index++)
r29404	r29405
273	273
274	274
275	275	//-------------------------------------------------
276		// set_brightness - set the overall brightness
	276	// set_brightness - set the overall brightness
277	277	// for the palette
278	278	//-------------------------------------------------
279	279
r29404	r29405
295	295
296	296
297	297	//-------------------------------------------------
298		// set_contrast - set the overall contrast for
	298	// set_contrast - set the overall contrast for
299	299	// the palette
300	300	//-------------------------------------------------
301	301
r29404	r29405
314	314
315	315
316	316	//-------------------------------------------------
317		// set_gamma - set the overall gamma for the
	317	// set_gamma - set the overall gamma for the
318	318	// palette
319	319	//-------------------------------------------------
320	320
r29404	r29405
342	342
343	343
344	344	//-------------------------------------------------
345		// entry_set_color - set the raw RGB color for a
	345	// entry_set_color - set the raw RGB color for a
346	346	// given palette index
347	347	//-------------------------------------------------
348	348
r29404	r29405
362	362
363	363
364	364	//-------------------------------------------------
365		// entry_set_contrast - set the contrast
	365	// entry_set_contrast - set the contrast
366	366	// adjustment for a single palette index
367	367	//-------------------------------------------------
368	368
r29404	r29405
382	382
383	383
384	384	//-------------------------------------------------
385		// group_set_brightness - configure overall
	385	// group_set_brightness - configure overall
386	386	// brightness for a palette group
387	387	//-------------------------------------------------
388	388
r29404	r29405
405	405
406	406
407	407	//-------------------------------------------------
408		// group_set_contrast - configure overall
	408	// group_set_contrast - configure overall
409	409	// contrast for a palette group
410	410	//-------------------------------------------------
411	411
r29404	r29405
425	425
426	426
427	427	//-------------------------------------------------
428		// normalize_range - normalize a range of palette
	428	// normalize_range - normalize a range of palette
429	429	// entries
430	430	//-------------------------------------------------
431	431
r29404	r29405
474	474	{
475	475	// compute the adjusted value
476	476	rgb_t adjusted = adjust_palette_entry(m_entry_color[index],
477		m_group_bright[group] + m_brightness,
478		m_group_contrast[group] * m_entry_contrast[index] * m_contrast,
479		m_gamma_map);
	477	m_group_bright[group] + m_brightness,
	478	m_group_contrast[group] * m_entry_contrast[index] * m_contrast,
	479	m_gamma_map);
480	480
481	481	// if not different, ignore
482	482	UINT32 finalindex = group * m_numcolors + index;

trunk/src/lib/util/options.h
r29404	r29405
175	175	bool validate_and_set_data(entry &curentry, const char *newdata, int priority, astring &error_string);
176	176
177	177	// internal state
178		simple_list<entry> m_entrylist; // head of list of entries
	178	simple_list<entry> m_entrylist; // head of list of entries
179	179	tagmap_t<entry *> m_entrymap; // map for fast lookup
180	180	astring m_command; // command found
181	181	static const char *const s_option_unadorned[]; // array of unadorned option "names"

trunk/src/lib/util/chd.h
r29404	r29405
526	526	, m_compression(0)
527	527	, m_codecs(NULL)
528	528	{ }
529
	529
530	530	osd_work_item * m_osd; // OSD work item running on this block
531	531	chd_file_compressor *m_compressor; // pointer back to the compressor
532	532	volatile work_status m_status; // current status of this item

trunk/src/lib/util/palette.h
r29404	r29405
39	39	rgb_t(UINT32 data) { m_data = data; }
40	40	rgb_t(UINT8 r, UINT8 g, UINT8 b) { m_data = (255 << 24) \| (r << 16) \| (g << 8) \| b; }
41	41	rgb_t(UINT8 a, UINT8 r, UINT8 g, UINT8 b) { m_data = (a << 24) \| (r << 16) \| (g << 8) \| b; }
42
	42
43	43	// getters
44	44	UINT8 a() const { return m_data >> 24; }
45	45	UINT8 r() const { return m_data >> 16; }
r29404	r29405
53	53	rgb_t &set_r(UINT8 r) { m_data &= ~0x00ff0000; m_data \|= r << 16; return *this; }
54	54	rgb_t &set_g(UINT8 g) { m_data &= ~0x0000ff00; m_data \|= g << 8; return *this; }
55	55	rgb_t &set_b(UINT8 b) { m_data &= ~0x000000ff; m_data \|= b << 0; return *this; }
56
	56
57	57	// implicit conversion operators
58	58	operator UINT32() const { return m_data; }
59	59
r29404	r29405
64	64	rgb_t &operator=(UINT32 rhs) { m_data = rhs; return *this; }
65	65	rgb_t &operator+=(const rgb_t &rhs) { m_data = rgb_t(clamphi(a() + rhs.a()), clamphi(r() + rhs.r()), clamphi(g() + rhs.g()), clamphi(b() + rhs.b())); return *this; }
66	66	rgb_t &operator-=(const rgb_t &rhs) { m_data = rgb_t(clamplo(a() - rhs.a()), clamplo(r() - rhs.r()), clamplo(g() - rhs.g()), clamplo(b() - rhs.b())); return *this; }
67
	67
68	68	// arithmetic operators
69	69	const rgb_t operator+(const rgb_t &rhs) const { rgb_t result = *this; result += rhs; return result; }
70	70	const rgb_t operator-(const rgb_t &rhs) const { rgb_t result = *this; result -= rhs; return result; }
71
	71
72	72	// static helpers
73	73	static UINT8 clamp(INT32 value) { return (value < 0) ? 0 : (value > 255) ? 255 : value; }
74	74	static UINT8 clamphi(INT32 value) { return (value > 255) ? 255 : value; }
r29404	r29405
79	79	static const rgb_t white;
80	80
81	81	private:
82		UINT32 m_data;
	82	UINT32 m_data;
83	83	};
84	84
85	85
r29404	r29405
108	108	public:
109	109	// construction
110	110	dirty_state();
111
	111
112	112	// operations
113	113	const UINT32 *dirty_list(UINT32 &mindirty, UINT32 &maxdirty);
114	114	void resize(UINT32 colors);
r29404	r29405
127	127	palette_client *m_next; // pointer to next client
128	128	dirty_state * m_live; // live dirty state
129	129	dirty_state * m_previous; // previous dirty state
130		dirty_state m_dirty[2]; // two dirty states
	130	dirty_state m_dirty[2]; // two dirty states
131	131	};
132	132
133	133
r29404	r29405
141	141	public:
142	142	// static constructor: used to ensure same new/delete is used
143	143	static palette_t *alloc(UINT32 numcolors, UINT32 numgroups = 1);
144
	144
145	145	// reference counting
146	146	void ref() { m_refcount++; }
147	147	void deref();
r29404	r29405
152	152	int max_index() const { return m_numcolors * m_numgroups + 2; }
153	153	UINT32 black_entry() const { return m_numcolors * m_numgroups + 0; }
154	154	UINT32 white_entry() const { return m_numcolors * m_numgroups + 1; }
155
	155
156	156	// overall adjustments
157	157	void set_brightness(float brightness);
158	158	void set_contrast(float contrast);
159	159	void set_gamma(float gamma);
160
	160
161	161	// entry getters
162	162	rgb_t entry_color(UINT32 index) const { return (index < m_numcolors) ? m_entry_color[index] : rgb_t::black; }
163	163	rgb_t entry_adjusted_color(UINT32 index) const { return (index < m_numcolors * m_numgroups) ? m_adjusted_color[index] : rgb_t::black; }
r29404	r29405
166	166	// entry setters
167	167	void entry_set_color(UINT32 index, rgb_t rgb);
168	168	void entry_set_contrast(UINT32 index, float contrast);
169
	169
170	170	// entry list getters
171	171	const rgb_t *entry_list_raw() const { return m_entry_color; }
172	172	const rgb_t *entry_list_adjusted() const { return m_adjusted_color; }
173	173	const rgb_t *entry_list_adjusted_rgb15() const { return m_adjusted_rgb15; }
174
	174
175	175	// group adjustments
176	176	void group_set_brightness(UINT32 group, float brightness);
177	177	void group_set_contrast(UINT32 group, float contrast);
178
	178
179	179	// utilities
180	180	void normalize_range(UINT32 start, UINT32 end, int lum_min = 0, int lum_max = 255);
181
	181
182	182	private:
183	183	// construction/destruction
184	184	palette_t(UINT32 numcolors, UINT32 numgroups = 1);

trunk/src/lib/util/cstrpool.c
r29404	r29405
39	39	if (result != NULL)
40	40	return result;
41	41	}
42
	42
43	43	// no space anywhere, create a new pool and prepend it (so it gets used first)
44	44	const char result = m_chunklist.prepend(global_alloc(pool_chunk)).add(string);
45	45	assert(result != NULL);
r29404	r29405
48	48
49	49
50	50	//-------------------------------------------------
51		// contains - determine if the given string
	51	// contains - determine if the given string
52	52	// pointer lives in the pool
53	53	//-------------------------------------------------
54	54
r29404	r29405
62	62	for (pool_chunk *chunk = m_chunklist.first(); chunk != NULL; chunk = chunk->next())
63	63	if (chunk->contains(string))
64	64	return true;
65
	65
66	66	return false;
67	67	}
68	68
r29404	r29405
72	72	//-------------------------------------------------
73	73
74	74	const_string_pool::pool_chunk::pool_chunk()
75		: m_next(NULL),
76		m_used(0)
	75	: m_next(NULL),
	76	m_used(0)
77	77	{
78	78	}
79	79
r29404	r29405
87	87	// get the length of the string (no string can be longer than a full pool)
88	88	int bytes = strlen(string) + 1;
89	89	assert(bytes < POOL_SIZE);
90
	90
91	91	// if too big, return NULL
92	92	if (m_used + bytes > POOL_SIZE)
93	93	return NULL;

trunk/src/lib/util/cstrpool.h
r29404	r29405
26	26	public:
27	27	// construction
28	28	const_string_pool();
29
	29
30	30	// operations
31	31	void reset() { m_chunklist.reset(); }
32	32	const char add(const char string);
33	33	bool contains(const char *string);
34
	34
35	35	private:
36	36	// shared string pool
37	37	class pool_chunk
38	38	{
39	39	static const int POOL_SIZE = 4096;
40	40	friend class simple_list<pool_chunk>;
41
	41
42	42	public:
43	43	// construction
44	44	pool_chunk();
45
	45
46	46	// getters
47	47	pool_chunk *next() const { return m_next; }
48	48
r29404	r29405
52	52
53	53	private:
54	54	// internal state
55		pool_chunk * m_next;
56		UINT32 m_used;
57		char m_buffer[POOL_SIZE];
	55	pool_chunk * m_next;
	56	UINT32 m_used;
	57	char m_buffer[POOL_SIZE];
58	58	};
59		simple_list<pool_chunk> m_chunklist;
	59	simple_list<pool_chunk> m_chunklist;
60	60	};
61	61
62	62

trunk/src/version.c
r29404	r29405
9	9	***************************************************************************/
10	10
11	11	extern const char build_version[];
12		const char build_version[] = "0.152 ("__DATE__")";
	12	const char build_version[] = "0.153 ("__DATE__")";

trunk/src/mess/audio/upd1771.h
r29404	r29405
27	27	~upd1771c_device() {}
28	28
29	29	template<class _Object> static devcb2_base &set_ack_handler(device_t &device, _Object object) { return downcast<upd1771c_device &>(device).m_ack_handler.set_callback(object); }
30
	30
31	31	DECLARE_READ8_MEMBER( read );
32	32	DECLARE_WRITE8_MEMBER( write );
33	33	WRITE_LINE_MEMBER( pcm_write );

trunk/src/mess/machine/mega32x.h
r29404	r29405
41	41	// set some variables at start, depending on region (shall be moved to a device interface?)
42	42	void set_framerate(int rate) { m_framerate = rate; }
43	43	void set_32x_pal(bool pal) { m_32x_pal = pal ? 1 : 0; }
44		void set_total_scanlines(int total) { m_base_total_scanlines = total; } // this get set at start only
45		void update_total_scanlines(bool mode3) { m_total_scanlines = mode3 ? (m_base_total_scanlines * 2) : m_base_total_scanlines; } // this gets set at each EOF
46
	44	void set_total_scanlines(int total) { m_base_total_scanlines = total; } // this get set at start only
	45	void update_total_scanlines(bool mode3) { m_total_scanlines = mode3 ? (m_base_total_scanlines * 2) : m_base_total_scanlines; } // this gets set at each EOF
	46
47	47	// static configuration
48	48	static void static_set_palette_tag(device_t &device, const char *tag);
49	49
r29404	r29405
192	192	UINT16 m_32x_display_dram, m_32x_access_dram;
193	193	UINT16* m_32x_palette;
194	194	UINT16* m_32x_palette_lookup;
195
	195
196	196	required_device<palette_device> m_palette;
197	197	};
198	198

trunk/src/mess/machine/apple3.c
r29404	r29405
3	3	machine/apple3.c
4	4
5	5	Apple ///
6
	6
7	7	VIA #0 (D VIA)
8		CA1: IRQ from the MM58167 RTC
9		CA2: 1 if key pressed, 0 otherwise
10		CB1/CB2: connected to VBL
11
12		Port A: Environment register (all bits out)
13		bit 7: 1 for 1 MHz, 0 for 2 MHz
14		bit 6: 1 for I/O at C000-CFFF
15		bit 5: 1 to enable video
16		bit 4: 1 to enable NMI/Reset
17		bit 3: 1 to write-protect RAM in system bank C000-FFFF
18		bit 2: 1 to force primary stack at 0100-01FF
19		bit 1: 1 for primary ROM, 0 for secondary (Apple III doesn't have a secondary ROM, so this should always be '1' when bit 0 is)
20		bit 0: 1 to enable ROM in F000-FFFF
21
22		Port B: Zero page high 8 address bits, also MM58167 RTC register select (all bits out)
23
	8	CA1: IRQ from the MM58167 RTC
	9	CA2: 1 if key pressed, 0 otherwise
	10	CB1/CB2: connected to VBL
	11
	12	Port A: Environment register (all bits out)
	13	bit 7: 1 for 1 MHz, 0 for 2 MHz
	14	bit 6: 1 for I/O at C000-CFFF
	15	bit 5: 1 to enable video
	16	bit 4: 1 to enable NMI/Reset
	17	bit 3: 1 to write-protect RAM in system bank C000-FFFF
	18	bit 2: 1 to force primary stack at 0100-01FF
	19	bit 1: 1 for primary ROM, 0 for secondary (Apple III doesn't have a secondary ROM, so this should always be '1' when bit 0 is)
	20	bit 0: 1 to enable ROM in F000-FFFF
	21
	22	Port B: Zero page high 8 address bits, also MM58167 RTC register select (all bits out)
	23
24	24	VIA #1 (E VIA)
25		CA1: OR of all 4 slots' IRQ status
26		CA2: SW1 (Open Apple key?)
27		CB1: SW3/SCO
28		CB2: SER
29
30		Port A:
31		bits 0-2: bank select for $2000-$9FFF range
32		bit 3: n/c
33		bit 4: slot 4 IRQ (in)
34		bit 5: slot 3 IRQ (in)
35		bit 6: Apple II mode trap output (out)
36		bit 7: IRQ status (in) (0 = IRQ, 1 = no IRQ)
37
38		Port B:
39		bits 0-5: 6-bit audio DAC output
40		bit 6: screen blank
41		bit 7: OR of NMI from slots
42
	25	CA1: OR of all 4 slots' IRQ status
	26	CA2: SW1 (Open Apple key?)
	27	CB1: SW3/SCO
	28	CB2: SER
	29
	30	Port A:
	31	bits 0-2: bank select for $2000-$9FFF range
	32	bit 3: n/c
	33	bit 4: slot 4 IRQ (in)
	34	bit 5: slot 3 IRQ (in)
	35	bit 6: Apple II mode trap output (out)
	36	bit 7: IRQ status (in) (0 = IRQ, 1 = no IRQ)
	37
	38	Port B:
	39	bits 0-5: 6-bit audio DAC output
	40	bit 6: screen blank
	41	bit 7: OR of NMI from slots
	42
43	43	***************************************************************************/
44	44
45	45	#include "emu.h"
r29404	r29405
53	53	#define LOG_MEMORY 1
54	54	#define LOG_INDXADDR 1
55	55
56		#define ENV_SLOWSPEED (0x80)
57		#define ENV_IOENABLE (0x40)
58		#define ENV_VIDENABLE (0x20)
59		#define ENV_NMIENABLE (0x10)
60		#define ENV_WRITEPROT (0x08)
61		#define ENV_STACK1XX (0x04)
62		#define ENV_PRIMARYROM (0x02)
63		#define ENV_ROMENABLE (0x01)
	56	#define ENV_SLOWSPEED (0x80)
	57	#define ENV_IOENABLE (0x40)
	58	#define ENV_VIDENABLE (0x20)
	59	#define ENV_NMIENABLE (0x10)
	60	#define ENV_WRITEPROT (0x08)
	61	#define ENV_STACK1XX (0x04)
	62	#define ENV_PRIMARYROM (0x02)
	63	#define ENV_ROMENABLE (0x01)
64	64
65	65	READ8_MEMBER(apple3_state::apple3_c0xx_r)
66	66	{
r29404	r29405
109	109	result &= ~0x20;
110	110	}
111	111	}
112		// printf("modifier = %02x\n", result);
	112	// printf("modifier = %02x\n", result);
113	113	break;
114	114
115	115	case 0x10: case 0x11: case 0x12: case 0x13:
r29404	r29405
174	174	{
175	175	result = slotdevice->read_c0nx(space, offset&0xf);
176	176	}
177		break;
	177	break;
178	178
179	179	case 0xa0: case 0xa1: case 0xa2: case 0xa3:
180	180	case 0xa4: case 0xa5: case 0xa6: case 0xa7:
r29404	r29405
185	185	{
186	186	result = slotdevice->read_c0nx(space, offset&0xf);
187	187	}
188		break;
	188	break;
189	189
190	190	case 0xb0: case 0xb1: case 0xb2: case 0xb3:
191	191	case 0xb4: case 0xb5: case 0xb6: case 0xb7:
r29404	r29405
196	196	{
197	197	result = slotdevice->read_c0nx(space, offset&0xf);
198	198	}
199		break;
	199	break;
200	200
201	201	case 0xc0: case 0xc1: case 0xc2: case 0xc3:
202	202	case 0xc4: case 0xc5: case 0xc6: case 0xc7:
r29404	r29405
207	207	{
208	208	result = slotdevice->read_c0nx(space, offset&0xf);
209	209	}
210		break;
	210	break;
211	211
212	212	case 0xD0: case 0xD1: case 0xD2: case 0xD3:
213	213	case 0xD4: case 0xD5: case 0xD6: case 0xD7:
r29404	r29405
305	305	{
306	306	slotdevice->write_c0nx(space, offset&0xf, data);
307	307	}
308		break;
	308	break;
309	309
310	310	case 0xa0: case 0xa1: case 0xa2: case 0xa3:
311	311	case 0xa4: case 0xa5: case 0xa6: case 0xa7:
r29404	r29405
316	316	{
317	317	slotdevice->write_c0nx(space, offset&0xf, data);
318	318	}
319		break;
	319	break;
320	320
321	321	case 0xb0: case 0xb1: case 0xb2: case 0xb3:
322	322	case 0xb4: case 0xb5: case 0xb6: case 0xb7:
r29404	r29405
327	327	{
328	328	slotdevice->write_c0nx(space, offset&0xf, data);
329	329	}
330		break;
	330	break;
331	331
332	332	case 0xc0: case 0xc1: case 0xc2: case 0xc3:
333	333	case 0xc4: case 0xc5: case 0xc6: case 0xc7:
r29404	r29405
338	338	{
339	339	slotdevice->write_c0nx(space, offset&0xf, data);
340	340	}
341		break;
	341	break;
342	342
343	343	case 0xD0: case 0xD1: case 0xD2: case 0xD3:
344	344	case 0xD4: case 0xD5: case 0xD6: case 0xD7:
r29404	r29405
372	372
373	373	TIMER_DEVICE_CALLBACK_MEMBER(apple3_state::apple3_interrupt)
374	374	{
375		m_via_1->write_cb1(machine().first_screen()->vblank());
	375	m_via_1->write_cb1(machine().first_screen()->vblank());
376	376	m_via_1->write_cb2(machine().first_screen()->vblank());
377	377	}
378	378
r29404	r29405
437	437	bank = ~0;
438	438	page = 0x01;
439	439	}
440		m_bank2 = apple3_bankaddr(bank, ((offs_t) page) * 0x100);
	440	m_bank2 = apple3_bankaddr(bank, ((offs_t) page) * 0x100);
441	441
442	442	/* bank 3 (0200-1FFF) */
443		m_bank3 = apple3_bankaddr(~0, 0x0200);
	443	m_bank3 = apple3_bankaddr(~0, 0x0200);
444	444
445	445	/* bank 4 (2000-9FFF) */
446		m_bank4 = apple3_bankaddr(m_via_1_a, 0x0000);
	446	m_bank4 = apple3_bankaddr(m_via_1_a, 0x0000);
447	447
448	448	/* bank 5 (A000-BFFF) */
449		m_bank5 = apple3_bankaddr(~0, 0x2000);
	449	m_bank5 = apple3_bankaddr(~0, 0x2000);
450	450
451	451	/* bank 8 (C000-C0FF) */
452	452	if (!(m_via_0_a & ENV_IOENABLE))
453	453	{
454		m_bank8 = apple3_bankaddr(~0, 0x4000);
	454	m_bank8 = apple3_bankaddr(~0, 0x4000);
455	455	}
456	456
457	457	/* bank 9 (C100-C4FF) */
458	458	if (!(m_via_0_a & ENV_IOENABLE))
459	459	{
460		m_bank9 = apple3_bankaddr(~0, 0x4100);
	460	m_bank9 = apple3_bankaddr(~0, 0x4100);
461	461	}
462	462
463	463	/* bank 10 (C500-C7FF) */
464		m_bank10 = apple3_bankaddr(~0, 0x4500);
	464	m_bank10 = apple3_bankaddr(~0, 0x4500);
465	465
466	466	/* bank 11 (C800-CFFF) */
467	467	if (!(m_via_0_a & ENV_IOENABLE))
r29404	r29405
507	507
508	508	WRITE8_MEMBER(apple3_state::apple3_via_0_out_b)
509	509	{
510		// printf("ZP to %02x\n", data);
	510	// printf("ZP to %02x\n", data);
511	511	apple3_via_out(&m_via_0_b, data);
512	512	}
513	513
r29404	r29405
529	529	// HACK: SOS floppy driver enables ROM at Fxxx before trying to
530	530	// suppress IRQs. IRQ hits at inopportune time -> bad vector -> system crash.
531	531	// This breaks the Confidence Test, but the Confidence Test
532		// never disables the ROM so checking for that gets us
	532	// never disables the ROM so checking for that gets us
533	533	// working in all cases.
534	534	// Bonus points: for some reason this isn't a problem with -debug.
535	535	// m6502 heisenbug maybe?
r29404	r29405
537	537	{
538	538	return;
539	539	}
540		// printf(" setting IRQ\n");
	540	// printf(" setting IRQ\n");
541	541	m_maincpu->set_input_line(M6502_IRQ_LINE, ASSERT_LINE);
542		m_via_1->write_pa7(0); // this is active low
	542	m_via_1->write_pa7(0); // this is active low
543	543	}
544	544	else
545	545	{
546		// printf(" clearing IRQ\n");
	546	// printf(" clearing IRQ\n");
547	547	m_maincpu->set_input_line(M6502_IRQ_LINE, CLEAR_LINE);
548	548	m_via_1->write_pa7(1);
549	549	}
r29404	r29405
551	551
552	552	WRITE_LINE_MEMBER(apple3_state::apple3_acia_irq_func)
553	553	{
554		// printf("acia IRQ: %d\n", state);
	554	// printf("acia IRQ: %d\n", state);
555	555	m_acia_irq = state;
556	556	apple3_irq_update();
557	557	}
558	558
559	559	WRITE_LINE_MEMBER(apple3_state::apple3_via_1_irq_func)
560	560	{
561		// printf("via 1 IRQ: %d\n", state);
	561	// printf("via 1 IRQ: %d\n", state);
562	562	m_via_1_irq = state;
563	563	apple3_irq_update();
564	564	}
r29404	r29405
566	566
567	567	WRITE_LINE_MEMBER(apple3_state::apple3_via_0_irq_func)
568	568	{
569		// printf("via 0 IRQ: %d\n", state);
	569	// printf("via 0 IRQ: %d\n", state);
570	570	m_via_0_irq = state;
571	571	apple3_irq_update();
572	572	}
r29404	r29405
745	745
746	746	if (offset < 0x100)
747	747	{
748		rv = *apple3_get_zpa_addr(offset);
	748	rv = *apple3_get_zpa_addr(offset);
749	749
750	750	if ((!m_sync) && (m_via_0_b >= 0x18) && (m_via_0_b <= 0x1F))
751	751	{
r29404	r29405
849	849	}
850	850	else
851	851	{
852		rv = m_bank7rd[offset - 0xf000];
	852	rv = m_bank7rd[offset - 0xf000];
853	853	}
854	854	}
855	855
r29404	r29405
1002	1002
1003	1003	WRITE_LINE_MEMBER(apple3_state::apple3_sync_w)
1004	1004	{
1005		// printf("sync: %d\n", state);
	1005	// printf("sync: %d\n", state);
1006	1006	m_sync = (state == ASSERT_LINE) ? true : false;
1007	1007
1008	1008	if (m_sync)
r29404	r29405
1044	1044
1045	1045	static const UINT8 key_remap[0x50][4] =
1046	1046	{
1047		/* norm shft ctrl both */
	1047	/* norm shft ctrl both */
1048	1048	{ 0x9b,0x9b,0x9b,0x9b }, /* Escape 00 */
1049	1049	{ 0x31,0x21,0x31,0x31 }, /* 1 ! 01 */
1050	1050	{ 0x32,0x40,0x32,0x00 }, /* 2 @ 02 */
r29404	r29405
1135	1135	{
1136	1136	UINT16 trans;
1137	1137	int mod = 0;
1138		m_lastchar = m_ay3600->b_r();
	1138	m_lastchar = m_ay3600->b_r();
1139	1139
1140		trans = m_lastchar & ~(0x1c0); // clear the 3600's control/shift stuff
1141		trans \|= (m_lastchar & 0x100)>>2; // bring the 0x100 bit down to the 0x40 place
	1140	trans = m_lastchar & ~(0x1c0); // clear the 3600's control/shift stuff
	1141	trans \|= (m_lastchar & 0x100)>>2; // bring the 0x100 bit down to the 0x40 place
1142	1142
1143	1143	mod = (m_kbspecial->read() & 0x06) ? 0x01 : 0x00;
1144	1144	mod \|= (m_kbspecial->read() & 0x08) ? 0x02 : 0x00;
r29404	r29405
1148	1148	if (m_transchar != 0)
1149	1149	{
1150	1150	m_strobe = 0x80;
1151		// printf("new char = %04x (%02x)\n", trans, m_transchar);
	1151	// printf("new char = %04x (%02x)\n", trans, m_transchar);
1152	1152	}
1153	1153	}
1154	1154	}
1155

trunk/src/mess/machine/thomson.c
r29404	r29405
4161	4161	{
4162	4162	if ( bank_is_read_only )
4163	4163	{
4164		space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
4165		space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
4166		space.nop_write( 0xb000, 0xefff);
	4164	space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
	4165	space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
	4166	space.nop_write( 0xb000, 0xefff);
4167	4167	}
4168	4168	else
4169	4169	{
4170	4170	space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
4171		space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
	4171	space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
4172	4172	}
4173	4173	}
4174	4174	}
r29404	r29405
4186	4186	{
4187	4187	if (m_to8_cart_vpage < 4)
4188	4188	{
4189		space.install_write_handler( 0xb000, 0xbfff, write8_delegate(FUNC(thomson_state::mo6_vcart_lo_w),this));
4190		space.install_write_handler( 0xc000, 0xefff, write8_delegate(FUNC(thomson_state::mo6_vcart_hi_w),this));
	4189	space.install_write_handler( 0xb000, 0xbfff, write8_delegate(FUNC(thomson_state::mo6_vcart_lo_w),this));
	4190	space.install_write_handler( 0xc000, 0xefff, write8_delegate(FUNC(thomson_state::mo6_vcart_hi_w),this));
4191	4191
4192	4192	}
4193	4193	else
4194	4194	{
4195		space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
4196		space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
	4195	space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
	4196	space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
4197	4197	}
4198	4198	}
4199	4199	LOG_BANK(( "mo6_update_cart_bank: update CART bank %i write status to %s\n",
r29404	r29405
4210	4210	{
4211	4211	if ( m_old_cart_bank < 0 \|\| m_old_cart_bank > 3 )
4212	4212	{
4213		space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
4214		space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
	4213	space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
	4214	space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
4215	4215	space.nop_write( 0xb000, 0xefff);
4216	4216	}
4217	4217	LOG_BANK(( "mo6_update_cart_bank: CART is external cartridge bank %i (A7CB style)\n", bank ));
r29404	r29405
4229	4229	{
4230	4230	if ( bank_is_read_only )
4231	4231	{
4232		space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
4233		space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
	4232	space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
	4233	space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
4234	4234	space.nop_write( 0xb000, 0xefff);
4235	4235	}
4236	4236	else
4237	4237	{
4238		space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
4239		space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
	4238	space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
	4239	space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
4240	4240	}
4241	4241	}
4242	4242	LOG_BANK(( "mo6_update_cart_bank: CART is RAM bank %i (MO5 compat.) (%s)\n",
r29404	r29405
4247	4247	{
4248	4248	if ( bank_is_read_only )
4249	4249	{
4250		space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
4251		space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
	4250	space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
	4251	space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
4252	4252	space.nop_write( 0xb000, 0xefff);
4253	4253	}
4254	4254	else
4255	4255	{
4256		space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
4257		space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
	4256	space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
	4257	space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
4258	4258	}
4259	4259	LOG_BANK(( "mo5_update_cart_bank: update CART bank %i write status to %s\n",
4260	4260	m_to8_cart_vpage,
r29404	r29405
4281	4281	{
4282	4282	if ( m_old_cart_bank < 4 \|\| m_old_cart_bank > 7 )
4283	4283	{
4284		space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
4285		space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
	4284	space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
	4285	space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
4286	4286	space.install_write_handler( 0xb000, 0xefff, write8_delegate(FUNC(thomson_state::mo6_cartridge_w),this) );
4287	4287	}
4288	4288	LOG_BANK(( "mo6_update_cart_bank: CART is internal ROM bank %i\n", b ));
r29404	r29405
4296	4296	bank = m_thom_cart_bank % m_thom_cart_nb_banks;
4297	4297	if ( bank != m_old_cart_bank )
4298	4298	{
4299		if ( m_old_cart_bank < 0 \|\| m_old_cart_bank > 3 )
	4299	if ( m_old_cart_bank < 0 \|\| m_old_cart_bank > 3 )
4300	4300	{
4301		space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
4302		space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
	4301	space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
	4302	space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
4303	4303	space.install_write_handler( 0xb000, 0xefff, write8_delegate(FUNC(thomson_state::mo6_cartridge_w),this) );
4304	4304	space.install_read_handler( 0xbffc, 0xbfff, read8_delegate(FUNC(thomson_state::mo6_cartridge_r),this) );
4305	4305	}

trunk/src/mess/machine/pecom.c
r29404	r29405
170	170	// DMA acknowledge clears the DMAOUT request
171	171	m_cdp1802->set_input_line(COSMAC_INPUT_LINE_DMAOUT, CLEAR_LINE);
172	172	break;
173
	173
174	174	case COSMAC_STATE_CODE_S3_INTERRUPT:
175	175	break;
176	176	}

trunk/src/mess/machine/ti99/grom.c
r29404	r29405
94	94	*/
95	95	ti99_grom_device::ti99_grom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
96	96	: bus8z_device(mconfig, GROM, "TI-99 GROM device", tag, owner, clock, "ti99_grom", __FILE__),
97		m_gromready(*this)
	97	m_gromready(*this)
98	98	{
99	99	}
100	100

trunk/src/mess/machine/ti99/speech8.h
r29404	r29405
27	27	{
28	28	public:
29	29	ti998_spsyn_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
30
	30
31	31	template<class _Object> static devcb2_base &set_ready_wr_callback(device_t &device, _Object object) { return downcast<ti998_spsyn_device &>(device).m_ready.set_callback(object); }
32	32
33	33	DECLARE_READ8Z_MEMBER(readz);

trunk/src/mess/machine/ti99/gromport.c
r29404	r29405
1391	1391	*/
1392	1392	static MACHINE_CONFIG_FRAGMENT( ti99_cartridge )
1393	1393	MCFG_GROM_ADD( GROM3_TAG, grom3_config )
1394		MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
	1394	MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
1395	1395	MCFG_GROM_ADD( GROM4_TAG, grom4_config )
1396		MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
	1396	MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
1397	1397	MCFG_GROM_ADD( GROM5_TAG, grom5_config )
1398		MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
	1398	MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
1399	1399	MCFG_GROM_ADD( GROM6_TAG, grom6_config )
1400		MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
	1400	MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
1401	1401	MCFG_GROM_ADD( GROM7_TAG, grom7_config )
1402		MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
	1402	MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
1403	1403	MACHINE_CONFIG_END
1404	1404
1405	1405	machine_config_constructor ti99_cartridge_device::device_mconfig_additions() const
r29404	r29405
2428	2428	catch (rpk_exception &exp)
2429	2429	{
2430	2430	newrpk->close();
2431		if (layout_xml != NULL) xml_file_free(layout_xml);
	2431	if (layout_xml != NULL) xml_file_free(layout_xml);
2432	2432	if (zipfile != NULL) zip_file_close(zipfile);
2433	2433	if (layout_text != NULL) global_free_array(layout_text);
2434	2434
r29404	r29405
2436	2436	throw exp;
2437	2437	}
2438	2438
2439		if (layout_xml != NULL) xml_file_free(layout_xml);
	2439	if (layout_xml != NULL) xml_file_free(layout_xml);
2440	2440	if (zipfile != NULL) zip_file_close(zipfile);
2441	2441	if (layout_text != NULL) global_free_array(layout_text);
2442	2442

trunk/src/mess/machine/ti99/grom.h
r29404	r29405
40	40	{
41	41	public:
42	42	ti99_grom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
43
	43
44	44	template<class _Object> static devcb2_base &set_ready_wr_callback(device_t &device, _Object object) { return downcast<ti99_grom_device &>(device).m_gromready.set_callback(object); }
45
	45
46	46	DECLARE_READ8Z_MEMBER(readz);
47	47	DECLARE_WRITE8_MEMBER(write);
48	48

trunk/src/mess/machine/ti99/990_hd.h
r29404	r29405
14	14	{
15	15	public:
16	16	ti990_hdc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
17
	17
18	18	template<class _Object> static devcb2_base &static_set_int_callback(device_t &device, _Object object) { return downcast<ti990_hdc_device &>(device).m_interrupt_callback.set_callback(object); }
19	19
20	20	DECLARE_READ16_MEMBER(read);
r29404	r29405
62	62	/* disk geometry */
63	63	unsigned int cylinders, heads, sectors_per_track, bytes_per_sector;
64	64	};
65
	65
66	66	UINT16 m_w[8];
67	67
68	68	devcb2_write_line m_interrupt_callback;

trunk/src/mess/machine/6883sam.h
r29404	r29405
170	170
171	171	// incidentals
172	172	address_space * m_cpu_space;
173		devcb2_read8 m_read_res;
	173	devcb2_read8 m_read_res;
174	174	sam_bank m_banks[8];
175	175	sam_space<0x0000, 0x7FFF> m_space_0000;
176	176	sam_space<0x8000, 0x9FFF> m_space_8000;

trunk/src/mess/machine/partner.c
r29404	r29405
77	77	}
78	78	}
79	79
80		READ8_MEMBER(partner_state::partner_floppy_r){
	80	READ8_MEMBER(partner_state::partner_floppy_r){
81	81	if (offset<0x100) {
82	82	switch(offset & 3) {
83	83	case 0x00 : return m_fdc->status_r(space, 0);

trunk/src/mess/machine/apollo.c
r29404	r29405
23	23	* - http://www.freescale.com/files/32bit/doc/inactive/MC68681UM.pdf
24	24	*
25	25	* SIO usage:
26		* SIO: ch A keyboard, ch B serial console
27		* SIO2: modem/printer?
	26	* SIO: ch A keyboard, ch B serial console
	27	* SIO2: modem/printer?
28	28	*
29	29	*/
30	30
r29404	r29405
190	190
191	191	/*static int apollo_csr_get_servicemode()
192	192	{
193		return cpu_status_register & APOLLO_CSR_SR_SERVICE ? 0 : 1;
	193	return cpu_status_register & APOLLO_CSR_SR_SERVICE ? 0 : 1;
194	194	}*/
195	195
196	196	static void apollo_csr_set_servicemode(int mode)
r29404	r29405
569	569	#undef VERBOSE
570	570	#define VERBOSE 0
571	571
572		void apollo_state::apollo_pic_set_irq_line(int irq, int state)
	572	void apollo_state::apollo_pic_set_irq_line(int irq, int state)
573	573	{
574	574	switch (irq) {
575	575	case 0: m_pic8259_master->ir0_w(state); break;
r29404	r29405
665	665	{
666	666	if ((state) && (m_ptm->started()))
667	667	{
668		ptm_counter++;
	668	ptm_counter++;
669	669	m_ptm->set_c1( 1);
670	670	m_ptm->set_c1( 0);
671	671	m_ptm->set_c2(ptm_counter & 1);
r29404	r29405
751	751
752	752	WRITE8_MEMBER(apollo_state::sio_output)
753	753	{
754		if ((data & 0x80) != (sio_output_data & 0x80))
	754	if ((data & 0x80) != (sio_output_data & 0x80))
755	755	{
756	756	apollo_pic_set_irq_line(APOLLO_IRQ_DIAG, (data & 0x80) ? 1 : 0);
757	757	sio_output_data = data;
r29404	r29405
762	762	// The period of the output is 15 microseconds.
763	763
764	764	// toggle memory refresh counter
765		// sio_input_data ^= 0x01;
	765	// sio_input_data ^= 0x01;
766	766
767	767	//##########################################################################
768	768	// machine/apollo_sio2.c - APOLLO DS3500 SIO2
r29404	r29405
808	808	};
809	809
810	810	static SLOT_INTERFACE_START(apollo_isa_cards)
811		SLOT_INTERFACE("wdc", ISA16_OMTI8621) // Combo ESDI/AT floppy controller
812		SLOT_INTERFACE("ctape", ISA8_SC499) // Archive SC499 cartridge tape
813		SLOT_INTERFACE("3c505", ISA16_3C505) // 3Com 3C505 Ethernet card
	811	SLOT_INTERFACE("wdc", ISA16_OMTI8621) // Combo ESDI/AT floppy controller
	812	SLOT_INTERFACE("ctape", ISA8_SC499) // Archive SC499 cartridge tape
	813	SLOT_INTERFACE("3c505", ISA16_3C505) // 3Com 3C505 Ethernet card
814	814	SLOT_INTERFACE_END
815	815
816	816	MACHINE_CONFIG_FRAGMENT( common )
r29404	r29405
849	849
850	850	MCFG_MC68681_ADD( APOLLO_SIO_TAG, XTAL_3_6864MHz )
851	851	MCFG_MC68681_IRQ_CALLBACK(WRITELINE(apollo_state, sio_irq_handler))
852		MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(apollo_state, sio_output))
	852	MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(apollo_state, sio_output))
853	853	MCFG_MC68681_A_TX_CALLBACK(DEVWRITELINE(APOLLO_KBD_TAG, apollo_kbd_device, rx_w))
854	854	MACHINE_CONFIG_END
855	855
r29404	r29405
868	868
869	869	MCFG_MC68681_ADD( APOLLO_SIO_TAG, XTAL_3_6864MHz )
870	870	MCFG_MC68681_IRQ_CALLBACK(WRITELINE(apollo_state, sio_irq_handler))
871		MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(apollo_state, sio_output))
	871	MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(apollo_state, sio_output))
872	872	MCFG_MC68681_B_TX_CALLBACK(DEVWRITELINE("rs232", rs232_port_device, write_txd))
873	873
874	874	MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "serial_terminal")

trunk/src/mess/machine/dec_lk201.c
r29404	r29405
116	116	// SERIAL COMMUNICATIONS INTERFACE
117	117	//-------------------------------------------------
118	118
119		#define SCI_BAUD 0 // Baud rate register
120		#define BAUD_SCR 0x07 // SCI baud rate select
121		#define BAUD_SCP 0x30 // SCI prescaler select
	119	#define SCI_BAUD 0 // Baud rate register
	120	#define BAUD_SCR 0x07 // SCI baud rate select
	121	#define BAUD_SCP 0x30 // SCI prescaler select
122	122
123		#define SCI_SCCR1 1 // Control register 1
124		#define SCCR1_WAKE 0x08 // Wakeup method
125		#define SCCR1_M 0x10 // Character length
126		#define SCCR1_T8 0x40 // Transmit bit 8
127		#define SCCR1_R8 0x80 // Receive bit 8
	123	#define SCI_SCCR1 1 // Control register 1
	124	#define SCCR1_WAKE 0x08 // Wakeup method
	125	#define SCCR1_M 0x10 // Character length
	126	#define SCCR1_T8 0x40 // Transmit bit 8
	127	#define SCCR1_R8 0x80 // Receive bit 8
128	128
129		#define SCI_SCCR2 2 // Control register 2
130		#define SCCR2_SBK 0x01 // Send break
131		#define SCCR2_RWU 0x02 // Receiver wakeup enable
132		#define SCCR2_RE 0x04 // Receiver enable
133		#define SCCR2_TE 0x08 // Transmitter enable
134		#define SCCR2_ILIE 0x10 // Idle line interrupt enable
135		#define SCCR2_RIE 0x20 // Receiver interrupt enable
136		#define SCCR2_TCIE 0x40 // Transmit complete interrupt enable
137		#define SCCR2_TIE 0x80 // Transmit interrupt enable
	129	#define SCI_SCCR2 2 // Control register 2
	130	#define SCCR2_SBK 0x01 // Send break
	131	#define SCCR2_RWU 0x02 // Receiver wakeup enable
	132	#define SCCR2_RE 0x04 // Receiver enable
	133	#define SCCR2_TE 0x08 // Transmitter enable
	134	#define SCCR2_ILIE 0x10 // Idle line interrupt enable
	135	#define SCCR2_RIE 0x20 // Receiver interrupt enable
	136	#define SCCR2_TCIE 0x40 // Transmit complete interrupt enable
	137	#define SCCR2_TIE 0x80 // Transmit interrupt enable
138	138
139		#define SCI_SCSR 3 // Status register
140		#define SCSR_FE 0x02 // Receiver framing error
141		#define SCSR_NF 0x04 // Receiver noise
142		#define SCSR_OR 0x08 // Receiver overrun
143		#define SCSR_IDLE 0x10 // Receiver idle
144		#define SCSR_RDRF 0x20 // Receive data register full
145		#define SCSR_TC 0x40 // Transmit complete
146		#define SCSR_TDRE 0x80 // Transmit data register empty
147		#define SCSR_INT (SCSR_IDLE \| SCSR_RDRF\| \
148		SCSR_TC \| SCSR_TDRE) // Interrupt sources
	139	#define SCI_SCSR 3 // Status register
	140	#define SCSR_FE 0x02 // Receiver framing error
	141	#define SCSR_NF 0x04 // Receiver noise
	142	#define SCSR_OR 0x08 // Receiver overrun
	143	#define SCSR_IDLE 0x10 // Receiver idle
	144	#define SCSR_RDRF 0x20 // Receive data register full
	145	#define SCSR_TC 0x40 // Transmit complete
	146	#define SCSR_TDRE 0x80 // Transmit data register empty
	147	#define SCSR_INT (SCSR_IDLE \| SCSR_RDRF\| \
	148	SCSR_TC \| SCSR_TDRE) // Interrupt sources
149	149
150		#define SCI_SCDR 4 // Data register
	150	#define SCI_SCDR 4 // Data register
151	151
152	152	//-------------------------------------------------
153	153	// SERIAL PERIPHERAL INTERFACE
154	154	//-------------------------------------------------
155	155
156		#define SPI_SPCR 0 // Control register
157		#define SPCR_SPR 0x03 // SPI clock rate select
158		#define SPCR_CPHA 0x04 // Clock phase
159		#define SPCR_CPOL 0x08 // Clock polarity
160		#define SPCR_MSTR 0x10 // Master mode select
161		#define SPCR_DWOM 0x20 // Port D wire-or mode option
162		#define SPCR_SPE 0x40 // Serial peripheral system enable
163		#define SPCR_SPIE 0x80 // Serial peripheral interrupt enable
	156	#define SPI_SPCR 0 // Control register
	157	#define SPCR_SPR 0x03 // SPI clock rate select
	158	#define SPCR_CPHA 0x04 // Clock phase
	159	#define SPCR_CPOL 0x08 // Clock polarity
	160	#define SPCR_MSTR 0x10 // Master mode select
	161	#define SPCR_DWOM 0x20 // Port D wire-or mode option
	162	#define SPCR_SPE 0x40 // Serial peripheral system enable
	163	#define SPCR_SPIE 0x80 // Serial peripheral interrupt enable
164	164
165		#define SPI_SPSR 1 // Status register
166		#define SPSR_MODF 0x10 // Mode fault flag
167		#define SPSR_WCOL 0x40 // Write collision
168		#define SPSR_SPIF 0x80 // SPI transfer complete
	165	#define SPI_SPSR 1 // Status register
	166	#define SPSR_MODF 0x10 // Mode fault flag
	167	#define SPSR_WCOL 0x40 // Write collision
	168	#define SPSR_SPIF 0x80 // SPI transfer complete
169	169
170		#define SPI_SPDR 2 // Data I/O Register
	170	#define SPI_SPDR 2 // Data I/O Register
171	171
172	172	//**************************************************************************
173	173	// DEVICE DEFINITIONS
r29404	r29405
338	338	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
339	339
340	340	PORT_START("KBD11")
341		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/") PORT_CODE(KEYCODE_SLASH)
342		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(";") PORT_CODE(KEYCODE_COLON)
	341	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/") PORT_CODE(KEYCODE_SLASH)
	342	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(";") PORT_CODE(KEYCODE_COLON)
343	343	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED ) // FIXME - duplicate "Return"
344	344	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("P") PORT_CODE(KEYCODE_P)
345	345	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("0") PORT_CODE(KEYCODE_0)
r29404	r29405
363	363	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("'") PORT_CODE(KEYCODE_QUOTE)
364	364	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("[") PORT_CODE(KEYCODE_OPENBRACE)
365	365	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Previous") PORT_CODE(KEYCODE_END)
366		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Do (F16)")
	366	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Do (F16)")
367	367	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("-") PORT_CODE(KEYCODE_MINUS)
368	368	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Insert Here") PORT_CODE(KEYCODE_HOME)
369	369
r29404	r29405
494	494	sci_status \|= SCSR_RDRF;
495	495	update_interrupts();
496	496	receive_register_extract();
497		// printf("lk201 got %02x\n", get_received_char());
	497	// printf("lk201 got %02x\n", get_received_char());
498	498	}
499	499
500	500	void lk201_device::tra_complete()
r29404	r29405
527	527
528	528	WRITE8_MEMBER( lk201_device::ddr_w )
529	529	{
530		// printf("%02x to PORT %c DDR (PC=%x)\n", data, 'A' + offset, m_maincpu->pc());
	530	// printf("%02x to PORT %c DDR (PC=%x)\n", data, 'A' + offset, m_maincpu->pc());
531	531
532	532	send_port(space, offset, ports[offset] & data);
533	533
r29404	r29405
543	543	// add in ddr-masked version of port writes
544	544	incoming \|= (ports[offset] & ddrs[offset]);
545	545
546		// printf("PORT %c read = %02x (DDR = %02x latch = %02x) (PC=%x)\n", 'A' + offset, ports[offset], ddrs[offset], ports[offset], m_maincpu->pc());
	546	// printf("PORT %c read = %02x (DDR = %02x latch = %02x) (PC=%x)\n", 'A' + offset, ports[offset], ddrs[offset], ports[offset], m_maincpu->pc());
547	547
548	548	return incoming;
549	549	}
r29404	r29405
557	557
558	558	void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 data)
559	559	{
560		// printf("PORT %c write %02x (DDR = %02x) (PC=%x)\n", 'A' + offset, data, ddrs[offset], m_maincpu->pc());
	560	// printf("PORT %c write %02x (DDR = %02x) (PC=%x)\n", 'A' + offset, data, ddrs[offset], m_maincpu->pc());
561	561
562	562	switch (offset)
563	563	{
r29404	r29405
609	609
610	610	switch (offset)
611	611	{
612		case SCI_BAUD: // Baud rate
	612	case SCI_BAUD: // Baud rate
613	613	break;
614	614
615		case SCI_SCCR1: // Control 1
	615	case SCI_SCCR1: // Control 1
616	616	break;
617	617
618		case SCI_SCCR2: // Control 2
	618	case SCI_SCCR2: // Control 2
619	619	incoming = sci_ctl2;
620	620	break;
621	621
622		case SCI_SCSR: // Status
	622	case SCI_SCSR: // Status
623	623	incoming = sci_status;
624	624	break;
625	625
626		case SCI_SCDR: // Data
	626	case SCI_SCDR: // Data
627	627	incoming = get_received_char();
628	628	sci_status &= ~SCSR_RDRF;
629	629	m_maincpu->set_input_line(M68HC05EG_INT_CPI, 0);
r29404	r29405
631	631	break;
632	632	}
633	633
634		// printf("SCI read @ %x = %02x (PC=%x)\n", offset, incoming, m_maincpu->pc());
	634	// printf("SCI read @ %x = %02x (PC=%x)\n", offset, incoming, m_maincpu->pc());
635	635
636	636	return incoming;
637	637	}
r29404	r29405
640	640	{
641	641	switch (offset)
642	642	{
643		case SCI_BAUD: // Baud rate
	643	case SCI_BAUD: // Baud rate
644	644	break;
645	645
646		case SCI_SCCR1: // Control 1
	646	case SCI_SCCR1: // Control 1
647	647	break;
648	648
649		case SCI_SCCR2: // Control 2
	649	case SCI_SCCR2: // Control 2
650	650	sci_ctl2 = data;
651	651	update_interrupts();
652	652	break;
653	653
654		case SCI_SCSR: // Status
	654	case SCI_SCSR: // Status
655	655	break;
656	656
657		case SCI_SCDR: // Data
658		// printf("LK201: sending %02x\n", data);
	657	case SCI_SCDR: // Data
	658	// printf("LK201: sending %02x\n", data);
659	659	transmit_register_setup(data);
660	660	sci_status &= ~(SCSR_TC \| SCSR_TDRE);
661	661	m_maincpu->set_input_line(M68HC05EG_INT_CPI, 0);
r29404	r29405
663	663	break;
664	664	}
665	665
666		// printf("SCI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
	666	// printf("SCI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
667	667	}
668	668
669	669	READ8_MEMBER( lk201_device::spi_r )
r29404	r29405
672	672
673	673	switch (offset)
674	674	{
675		case SPI_SPCR: // Control
	675	case SPI_SPCR: // Control
676	676	break;
677	677
678		case SPI_SPSR: // Status
	678	case SPI_SPSR: // Status
679	679	incoming = spi_status;
680	680	spi_status &= ~SPSR_SPIF;
681	681	break;
682	682
683		case SPI_SPDR: // Data I/O
	683	case SPI_SPDR: // Data I/O
684	684	incoming = spi_data;
685	685	break;
686	686	}
687	687
688		// printf("SPI read @ %x = %02x (PC=%x)\n", offset, incoming, m_maincpu->pc());
	688	// printf("SPI read @ %x = %02x (PC=%x)\n", offset, incoming, m_maincpu->pc());
689	689
690	690	return incoming;
691	691	}
r29404	r29405
694	694	{
695	695	switch (offset)
696	696	{
697		case SPI_SPCR: // Control
	697	case SPI_SPCR: // Control
698	698	break;
699	699
700		case SPI_SPSR: // Status (read only)
	700	case SPI_SPSR: // Status (read only)
701	701	break;
702	702
703		case SPI_SPDR: // Data I/O
	703	case SPI_SPDR: // Data I/O
704	704	spi_data = data;
705	705
706	706	// Transfer only allowed if transfer complete flag has been acknowleged
r29404	r29405
718	718	break;
719	719	}
720	720
721		// printf("SPI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
	721	// printf("SPI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
722	722	}
723

trunk/src/mess/machine/atarifdc.c
r29404	r29405
763	763	m_serout_count(0),
764	764	m_serout_offs(0),
765	765	m_serout_chksum(0),
766		// m_serout_delay(0),
	766	// m_serout_delay(0),
767	767	m_serin_count(0),
768	768	m_serin_offs(0),
769	769	m_serin_chksum(0),

trunk/src/mess/machine/atarifdc.h
r29404	r29405
51	51	int m_serout_offs;
52	52	UINT8 m_serout_buff[512];
53	53	UINT8 m_serout_chksum;
54		// int m_serout_delay;
	54	// int m_serout_delay;
55	55
56	56	int m_serin_count;
57	57	int m_serin_offs;

trunk/src/mess/machine/amstrad.c
r29404	r29405
2669	2669	return (keyrow[m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F]->read_safe(0) & 0x80) \| 0x7f;
2670	2670	}
2671	2671	}
2672
	2672
2673	2673	return keyrow[m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F]->read_safe(0) & 0xFF;
2674	2674	}
2675	2675	return 0xFF;

trunk/src/mess/machine/sms.c
r29404	r29405
698	698	// a bunch of SG1000 carts (compatible with SG1000 Mark III) use their own RAM...
699	699	// TODO: are BASIC and Music actually compatible with Mark III??
700	700	if (m_cartslot->get_type() == SEGA8_BASIC_L3 \|\|
701		m_cartslot->get_type() == SEGA8_MUSIC_EDITOR \|\|
702		m_cartslot->get_type() == SEGA8_DAHJEE_TYPEA \|\|
703		m_cartslot->get_type() == SEGA8_DAHJEE_TYPEB)
	701	m_cartslot->get_type() == SEGA8_MUSIC_EDITOR \|\|
	702	m_cartslot->get_type() == SEGA8_DAHJEE_TYPEA \|\|
	703	m_cartslot->get_type() == SEGA8_DAHJEE_TYPEB)
704	704	{
705	705	m_mem_device_enabled \|= ENABLE_EXT_RAM;
706	706	}
r29404	r29405
773	773	// the "call $4010" without a following RET statement. That is basically
774	774	// a bug in the program code. The only way this cartridge could have run
775	775	// successfully on a real unit is if the RAM would be initialized with
776		// a F0 pattern on power up; F0 = RET P.
777		// This initialization breaks the some Game Gear games though (e.g.
	776	// a F0 pattern on power up; F0 = RET P.
	777	// This initialization breaks the some Game Gear games though (e.g.
778	778	// tempojr), suggesting that not all systems had the same initialization.
779		// For the moment we apply this to systems that have the Japanese SMS
	779	// For the moment we apply this to systems that have the Japanese SMS
780	780	// cartridge slot.
781	781	if (m_has_jpn_sms_cart_slot)
782	782	{
r29404	r29405
888	888	// - the one with 16 cart slots and 3 card slots;
889	889	// - the one with 16 cart slots and 16 card slots.
890	890	//
891		// On front panel of both models there are only 16 game switches,
	891	// On front panel of both models there are only 16 game switches,
892	892	// that seems to change the active cart/card slot pair or, for the 4th
893	893	// game switch onward of the 16-3 model, the active cart slot only.
894	894

trunk/src/mess/machine/dgn_beta.c
r29404	r29405
931	931
932	932	/******************************* Machine/Driver Initialization **************************************/
933	933	void dgn_beta_state::machine_reset()
934		{
	934	{
935	935	wd2797_device *fdc = machine().device<wd2797_device>(FDC_TAG);
936	936	pia6821_device *pia_0 = machine().device<pia6821_device>( PIA_0_TAG );
937	937	pia6821_device *pia_1 = machine().device<pia6821_device>( PIA_1_TAG );

trunk/src/mess/machine/swtpc09.c
r29404	r29405
1	1	/***************************************************************************
2		swtpc09 machine file
3		Robert Justice ,2009-2014
	2	swtpc09 machine file
	3	Robert Justice ,2009-2014
4	4
5	5	****************************************************************************/
6	6
r29404	r29405
21	21
22	22	#define VERBOSE 0
23	23
24		#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
	24	#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
25	25
26	26
27	27	/***** MC6840 PTM on MPID Board *****/
r29404	r29405
41	41
42	42	m_pia_counter++;
43	43	//pia_counter = pia_counter && 0xff;
44		if (m_pia_counter & 0x80) pia->ca1_w(1);
	44	if (m_pia_counter & 0x80) pia->ca1_w(1);
45	45	}
46	46
47	47	WRITE8_MEMBER( swtpc09_state::ptm_o3_callback )
r29404	r29405
54	54	WRITE_LINE_MEMBER( swtpc09_state::ptm_irq )
55	55	{
56	56	if (state)
57		swtpc09_irq_handler(PTM_IRQ, ASSERT_LINE);
	57	swtpc09_irq_handler(PTM_IRQ, ASSERT_LINE);
58	58	else
59		swtpc09_irq_handler(PTM_IRQ, CLEAR_LINE);
	59	swtpc09_irq_handler(PTM_IRQ, CLEAR_LINE);
60	60	}
61	61
62	62	/***** MC6821 PIA on MPID Board *****/
r29404	r29405
64	64
65	65	READ8_MEMBER( swtpc09_state::pia0_a_r )
66	66	{
67		return m_pia_counter;
	67	return m_pia_counter;
68	68	}
69	69
70	70	READ8_MEMBER( swtpc09_state::pia0_ca1_r )
r29404	r29405
74	74
75	75	WRITE_LINE_MEMBER( swtpc09_state::pia0_irq_a )
76	76	{
77		pia6821_device *pia = machine().device<pia6821_device>("pia");
	77	pia6821_device *pia = machine().device<pia6821_device>("pia");
78	78
79	79	if ( pia->irq_a_state())
80		swtpc09_irq_handler(PIA_IRQ, ASSERT_LINE);
	80	swtpc09_irq_handler(PIA_IRQ, ASSERT_LINE);
81	81	else
82		swtpc09_irq_handler(PIA_IRQ, CLEAR_LINE);
	82	swtpc09_irq_handler(PIA_IRQ, CLEAR_LINE);
83	83
84	84	}
85	85
r29404	r29405
90	90	{
91	91	if (state)
92	92	{
93		swtpc09_irq_handler(ACIA_IRQ, ASSERT_LINE);
	93	swtpc09_irq_handler(ACIA_IRQ, ASSERT_LINE);
94	94	LOG(("swtpc09_acia_irq_assert\n"));
95		}
	95	}
96	96	else
97	97	{
98		swtpc09_irq_handler(ACIA_IRQ, CLEAR_LINE);
	98	swtpc09_irq_handler(ACIA_IRQ, CLEAR_LINE);
99	99	LOG(("swtpc09_acia_irq_clear\n"));
100		}
	100	}
101	101	}
102	102
103	103	/*********************************************************************/
r29404	r29405
107	107	/* DMF2 dma extended address register */
108	108	READ8_MEMBER ( swtpc09_state::dmf2_dma_address_reg_r )
109	109	{
110		return m_fdc_dma_address_reg;
	110	return m_fdc_dma_address_reg;
111	111	}
112	112
113	113	WRITE8_MEMBER ( swtpc09_state::dmf2_dma_address_reg_w )
114	114	{
115		m_fdc_dma_address_reg = data;
116
	115	m_fdc_dma_address_reg = data;
	116
117	117	// bit 4 controls a gate enable/disable for DMF2 fdc irq line
118	118	if ((m_fdc_dma_address_reg & 0x10) && (m_system_type == UNIFLEX_DMF2 \|\| m_system_type == FLEX_DMF2))
119		swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE); //then clear the irq to cpu
120
	119	swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE); //then clear the irq to cpu
	120
121	121	LOG(("swtpc09_dmf2_dma_address_reg_w %02X\n", data));
122	122	}
123	123
r29404	r29405
134	134
135	135	switch (data & 0x0F)
136	136	{
137		case 0x0e:
138		m_fdc->set_drive(0);
139		// need to set drive ready as sw checks before doing anything
140		machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
	137	case 0x0e:
	138	m_fdc->set_drive(0);
	139	// need to set drive ready as sw checks before doing anything
	140	machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
141	141	break;
142		case 0x0d:
143		m_fdc->set_drive(1);
144		machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
	142	case 0x0d:
	143	m_fdc->set_drive(1);
	144	machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
145	145	break;
146	146
147		case 0x0b:
148		m_fdc->set_drive(2);
149		machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
150		break;
	147	case 0x0b:
	148	m_fdc->set_drive(2);
	149	machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
	150	break;
151	151
152		case 0x07:
153		m_fdc->set_drive(3);
154		machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
155		break;
	152	case 0x07:
	153	m_fdc->set_drive(3);
	154	machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
	155	break;
156	156
157	157	default:
158	158	break;
159		}
	159	}
160	160
161		// ignore side select in emulation due to sector numbering
	161	// ignore side select in emulation due to sector numbering
162	162	////side select
163	163	//if (!(data & 0x10)) {
164	164	// wd17xx_set_side(fdc, 1);
r29404	r29405
168	168	//}
169	169
170	170
171		/* bit 5 dden select */
	171	/* bit 5 dden select */
172	172
173	173	if (!(data & 0x20)) {
174		m_fdc->dden_w(0);
175		LOG(("Density single\n"));
	174	m_fdc->dden_w(0);
	175	LOG(("Density single\n"));
176	176	}
177	177	if (data & 0x20) {
178		m_fdc->dden_w(1);
179		LOG(("Density double\n"));
	178	m_fdc->dden_w(1);
	179	LOG(("Density double\n"));
180	180	}
181	181	}
182	182
r29404	r29405
184	184	void swtpc09_state::swtpc09_fdc_dma_transfer()
185	185	{
186	186	UINT8 *RAM = memregion("maincpu")->base();
187		UINT32 offset;
	187	UINT32 offset;
188	188	address_space &space = m_maincpu->space(AS_PROGRAM);
189	189
190		offset = (m_fdc_dma_address_reg & 0x0f)<<16;
	190	offset = (m_fdc_dma_address_reg & 0x0f)<<16;
191	191
192	192	if (m_m6844_channel[0].active == 1) //active dma transfer
193	193	{
r29404	r29405
211	211
212	212	if (m_m6844_channel[0].counter == 0) // dma transfer has finished
213	213	{
214		m_m6844_channel[0].control \|= 0x80; // set dend flag
215		if (m_m6844_interrupt & 0x01) // interrupt for channel 0 is enabled?
216		{
217		m_m6844_interrupt \|= 0x80; // set bit 7 to indicate active interrupt
218		swtpc09_irq_handler(DMAC_IRQ, ASSERT_LINE);
219		}
	214	m_m6844_channel[0].control \|= 0x80; // set dend flag
	215	if (m_m6844_interrupt & 0x01) // interrupt for channel 0 is enabled?
	216	{
	217	m_m6844_interrupt \|= 0x80; // set bit 7 to indicate active interrupt
	218	swtpc09_irq_handler(DMAC_IRQ, ASSERT_LINE);
	219	}
220	220	}
221	221	}
222	222
r29404	r29405
230	230	switch (state)
231	231	{
232	232	case ASSERT_LINE:
233		m_interrupt \|= peripheral;
234		break;
	233	m_interrupt \|= peripheral;
	234	break;
235	235
236	236	case CLEAR_LINE:
237		m_interrupt &= (~peripheral & 0x3f);
238		break;
239		}
	237	m_interrupt &= (~peripheral & 0x3f);
	238	break;
	239	}
240	240
241		if (!m_active_interrupt && m_interrupt) //no active interrupt and it needs to be asserted
242		{
243		m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
244		m_active_interrupt=TRUE;
245		LOG(("swtpc09_irq_assert %02X\n", peripheral));
246		}
	241	if (!m_active_interrupt && m_interrupt) //no active interrupt and it needs to be asserted
	242	{
	243	m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
	244	m_active_interrupt=TRUE;
	245	LOG(("swtpc09_irq_assert %02X\n", peripheral));
	246	}
247	247	else if (m_active_interrupt && !m_interrupt) //active interrupt and it needs to be cleared
248	248	{
249	249	m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
250	250	LOG(("swtpc09_irq_clear %02X\n", peripheral));
251	251	m_active_interrupt=FALSE;
252		}
	252	}
253	253	}
254	254
255	255	/***** WD1791 FDC *****/
r29404	r29405
258	258	{
259	259	DEVCB_NULL,
260	260	DEVCB_DRIVER_LINE_MEMBER(swtpc09_state, fdc_intrq_w),
261		DEVCB_DRIVER_LINE_MEMBER(swtpc09_state, fdc_drq_w),
	261	DEVCB_DRIVER_LINE_MEMBER(swtpc09_state, fdc_drq_w),
262	262	{FLOPPY_0, FLOPPY_1, FLOPPY_2, FLOPPY_3 }
263	263	};
264	264
265	265	/* handlers for fdc */
266	266	WRITE_LINE_MEMBER( swtpc09_state::fdc_intrq_w )
267	267	{
268		LOG(("swtpc09_fdc_intrq_w %02X\n", state));
	268	LOG(("swtpc09_fdc_intrq_w %02X\n", state));
269	269	if ( m_system_type == UNIFLEX_DMF3 ) //IRQ from 1791 is connect into VIA ca2
270	270	{
271		if (state)
272		{
273		m_fdc_status \|= 0x40;
	271	if (state)
	272	{
	273	m_fdc_status \|= 0x40;
274	274	m_via->write_cb2(0); //fdc interrupt is connected to CA1
275		m_dmf3_via_porta &= 0xfb; //clear pa3
	275	m_dmf3_via_porta &= 0xfb; //clear pa3
276	276	//m_via->write_porta(m_dmf3_via_porta); //and connected to PA3
277		//swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE);
	277	//swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE);
278	278	}
279	279	else
280	280	{
281		m_fdc_status &= ~0x40;
	281	m_fdc_status &= ~0x40;
282	282	m_via->write_cb2(1);
283	283	m_dmf3_via_porta \|= 0x04; //and connected to PA3
284	284	//m_via->write_porta(m_dmf3_via_porta); //and connected to PA3
285		//swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE);
	285	//swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE);
286	286	}
287		}
	287	}
288	288	else if ( m_system_type == FLEX_DC4_PIAIDE ) //for dc4 emulate irq jumper out
289	289	{
290		if (state)
291		{
292		m_fdc_status \|= 0x40;
	290	if (state)
	291	{
	292	m_fdc_status \|= 0x40;
293	293	}
294	294	else
295	295	{
296		m_fdc_status &= ~0x40;
	296	m_fdc_status &= ~0x40;
297	297	}
298	298	}
299	299	else //for dmf2 it is connected directly to cpu via a gate
300	300	{
301		if (state)
302		{
303		m_fdc_status \|= 0x40;
	301	if (state)
	302	{
	303	m_fdc_status \|= 0x40;
304	304	if (!(m_fdc_dma_address_reg & 0x10)) // is dmf2 fdc irq enabled
305	305	{
306		LOG(("swtpc09_fdc_int ** assert\n"));
	306	LOG(("swtpc09_fdc_int ** assert\n"));
307	307	swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE);
308	308	}
309	309	}
310	310	else
311	311	{
312		m_fdc_status &= ~0x40;
313		if (!(m_fdc_dma_address_reg & 0x10)) // is dmf2 fdc irq enabled
	312	m_fdc_status &= ~0x40;
	313	if (!(m_fdc_dma_address_reg & 0x10)) // is dmf2 fdc irq enabled
314	314	{
315		LOG(("swtpc09_fdc_int ** clear\n"));
	315	LOG(("swtpc09_fdc_int ** clear\n"));
316	316	swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE);
317	317	}
318	318	}
r29404	r29405
323	323	{
324	324	if (m_system_type == FLEX_DC4_PIAIDE) //for dc4 no dma
325	325	{
326		if (state)
327		{
328		m_fdc_status \|= 0x80;
329		}
330		else
331		m_fdc_status &= 0x7f;
332		}
	326	if (state)
	327	{
	328	m_fdc_status \|= 0x80;
	329	}
	330	else
	331	m_fdc_status &= 0x7f;
	332	}
333	333	else
334	334	{
335		if (state)
336		{
337		m_fdc_status \|= 0x80;
338		swtpc09_fdc_dma_transfer();
339		}
340		else
341		m_fdc_status &= 0x7f;
342		}
	335	if (state)
	336	{
	337	m_fdc_status \|= 0x80;
	338	swtpc09_fdc_dma_transfer();
	339	}
	340	else
	341	m_fdc_status &= 0x7f;
	342	}
343	343	}
344	344
345	345	/*********************************************************************/
r29404	r29405
364	364
365	365	//WRITE_LINE_MEMBER( swtpc09_state::dmf3_via_write_ca1 )
366	366	//{
367		// return m_via_ca1_input;
	367	// return m_via_ca1_input;
368	368	// LOG(("swtpc09_dmf3_via_write_ca1 %02X\n", state));
369	369
370	370	//}
r29404	r29405
372	372	WRITE_LINE_MEMBER( swtpc09_state::dmf3_via_irq )
373	373	{
374	374	if (state)
375		swtpc09_irq_handler(VIA_IRQ, ASSERT_LINE);
376		else
377		swtpc09_irq_handler(VIA_IRQ, CLEAR_LINE);
	375	swtpc09_irq_handler(VIA_IRQ, ASSERT_LINE);
	376	else
	377	swtpc09_irq_handler(VIA_IRQ, CLEAR_LINE);
378	378	}
379	379
380	380	/* DMF3 dma extended address register */
381	381	READ8_MEMBER ( swtpc09_state::dmf3_dma_address_reg_r )
382	382	{
383		return m_fdc_dma_address_reg;
	383	return m_fdc_dma_address_reg;
384	384	}
385	385
386	386	WRITE8_MEMBER ( swtpc09_state::dmf3_dma_address_reg_w )
387	387	{
388		m_fdc_dma_address_reg = data;
389		LOG(("swtpc09_dmf3_dma_address_reg_w %02X\n", data));
	388	m_fdc_dma_address_reg = data;
	389	LOG(("swtpc09_dmf3_dma_address_reg_w %02X\n", data));
390	390	}
391	391
392	392	/* DMF3 fdc control register */
r29404	r29405
402	402
403	403	switch (data & 0x0F)
404	404	{
405		case 0x01:
406		m_fdc->set_drive(0);
407		// need to set drive ready as sw checks before doing anything
408		machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
	405	case 0x01:
	406	m_fdc->set_drive(0);
	407	// need to set drive ready as sw checks before doing anything
	408	machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
409	409	break;
410		case 0x02:
411		m_fdc->set_drive(1);
412		machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
	410	case 0x02:
	411	m_fdc->set_drive(1);
	412	machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
413	413	break;
414	414
415		case 0x04:
416		m_fdc->set_drive(2);
417		machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
418		break;
	415	case 0x04:
	416	m_fdc->set_drive(2);
	417	machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
	418	break;
419	419
420		case 0x08:
421		m_fdc->set_drive(3);
422		machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
423		break;
	420	case 0x08:
	421	m_fdc->set_drive(3);
	422	machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
	423	break;
424	424
425	425	default:
426	426	break;
427		}
	427	}
428	428
429		// ignore side select in emulation due to sector numbering
	429	// ignore side select in emulation due to sector numbering
430	430	////side select
431	431	//if (!(data & 0x10)) {
432	432	// wd17xx_set_side(fdc, 1);
r29404	r29405
436	436	//}
437	437
438	438
439		/* bit 5 dden select */
	439	/* bit 5 dden select */
440	440
441	441	if (data & 0x20) {
442		m_fdc->dden_w(0);
443		LOG(("Density single\n"));
	442	m_fdc->dden_w(0);
	443	LOG(("Density single\n"));
444	444	}
445	445	if (!(data & 0x20)) {
446		m_fdc->dden_w(1);
447		LOG(("Density double\n"));
	446	m_fdc->dden_w(1);
	447	LOG(("Density double\n"));
448	448	}
449	449	}
450	450
r29404	r29405
456	456
457	457	switch (data & 0x03)
458	458	{
459		case 0x00:
460		m_fdc->set_drive(0);
461		// need to set drive ready as sw checks before doing anything
462		machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
	459	case 0x00:
	460	m_fdc->set_drive(0);
	461	// need to set drive ready as sw checks before doing anything
	462	machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
463	463	break;
464		case 0x01:
465		m_fdc->set_drive(1);
466		machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
	464	case 0x01:
	465	m_fdc->set_drive(1);
	466	machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
467	467	break;
468	468
469		case 0x02:
470		m_fdc->set_drive(2);
471		machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
472		break;
	469	case 0x02:
	470	m_fdc->set_drive(2);
	471	machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
	472	break;
473	473
474		case 0x03:
475		m_fdc->set_drive(3);
476		machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
477		break;
	474	case 0x03:
	475	m_fdc->set_drive(3);
	476	machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
	477	break;
478	478
479	479	default:
480	480	break;
481		}
	481	}
482	482
483		// ignore side select in emulation due to sector numbering
	483	// ignore side select in emulation due to sector numbering
484	484	}
485	485
486	486
r29404	r29405
490	490
491	491	READ8_MEMBER( swtpc09_state::piaide_a_r )
492	492	{
493		return m_piaide_porta;
	493	return m_piaide_porta;
494	494	}
495	495
496	496	READ8_MEMBER( swtpc09_state::piaide_b_r )
r29404	r29405
500	500
501	501	WRITE8_MEMBER( swtpc09_state::piaide_a_w )
502	502	{
503		m_piaide_porta = data;
	503	m_piaide_porta = data;
504	504	}
505	505
506	506	WRITE8_MEMBER( swtpc09_state::piaide_b_w )
507	507	{
508		int tempidedata;
	508	int tempidedata;
509	509
510		m_piaide_portb = data;
	510	m_piaide_portb = data;
511	511
512		if ((data & 0x40)&&(!(data&0x20))) //cs0=0 cs1=1 bit 5&6
513		{
514		if (!(data & 0x02)) //rd line bit 1
515		{
516		tempidedata = m_ide->read_cs0(space, (data&0x1c)>>2, 0xffff);
517		LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
518		m_piaide_porta = tempidedata & 0x00ff;
519		}
520		else if (!(data & 0x01)) //wr line bit 0
	512	if ((data & 0x40)&&(!(data&0x20))) //cs0=0 cs1=1 bit 5&6
	513	{
	514	if (!(data & 0x02)) //rd line bit 1
521	515	{
	516	tempidedata = m_ide->read_cs0(space, (data&0x1c)>>2, 0xffff);
	517	LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
	518	m_piaide_porta = tempidedata & 0x00ff;
	519	}
	520	else if (!(data & 0x01)) //wr line bit 0
	521	{
522	522	m_ide->write_cs0(space, (data&0x1c)>>2, m_piaide_porta, 0xffff);
523		LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
524		}
525		}
526		else if ((data & 0x20)&&(!(data&0x40))) //cs0=1 cs1=0 bit 5&6
527		{
528		if (!(data & 0x02)) //rd line bit 1
529		{
530		tempidedata = m_ide->read_cs1(space, (data&0x1c)>>2, 0xffff);
531		LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
532		m_piaide_porta = tempidedata & 0x00ff;
533		}
534		else if (!(data & 0x01)) //wr line bit 0
	523	LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
	524	}
	525	}
	526	else if ((data & 0x20)&&(!(data&0x40))) //cs0=1 cs1=0 bit 5&6
	527	{
	528	if (!(data & 0x02)) //rd line bit 1
535	529	{
	530	tempidedata = m_ide->read_cs1(space, (data&0x1c)>>2, 0xffff);
	531	LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
	532	m_piaide_porta = tempidedata & 0x00ff;
	533	}
	534	else if (!(data & 0x01)) //wr line bit 0
	535	{
536	536	m_ide->write_cs1(space, (data&0x1c)>>2, m_piaide_porta, 0xffff);
537		LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
538		}
539		}
	537	LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
	538	}
	539	}
540	540	}
541	541
542	542
r29404	r29405
547	547
548	548	WRITE8_MEMBER(swtpc09_state::dat_w)
549	549	{
550		UINT8 a16_to_a19, a12_to_a15;
551		UINT8 *RAM = memregion("maincpu")->base();
552		UINT32 physical_address, logical_address;
	550	UINT8 a16_to_a19, a12_to_a15;
	551	UINT8 *RAM = memregion("maincpu")->base();
	552	UINT32 physical_address, logical_address;
553	553
554		address_space &mem = m_maincpu->space(AS_PROGRAM);
	554	address_space &mem = m_maincpu->space(AS_PROGRAM);
555	555
556	556	fd1793_device *fdc = machine().device<fd1793_device>("fdc");
557		pia6821_device *pia = machine().device<pia6821_device>("pia");
558		ptm6840_device *ptm = machine().device<ptm6840_device>("ptm");
559		acia6850_device *acia = machine().device<acia6850_device>("acia");
560		via6522_device *via = machine().device<via6522_device>("via");
561		pia6821_device *piaide = machine().device<pia6821_device>("piaide");
	557	pia6821_device *pia = machine().device<pia6821_device>("pia");
	558	ptm6840_device *ptm = machine().device<ptm6840_device>("ptm");
	559	acia6850_device *acia = machine().device<acia6850_device>("acia");
	560	via6522_device *via = machine().device<via6522_device>("via");
	561	pia6821_device *piaide = machine().device<pia6821_device>("piaide");
562	562
563		a16_to_a19 = data & 0xf0;
564		a12_to_a15 = ~data & 0x0f; //lower 4 bits are inverted
565		physical_address = ((a16_to_a19 + a12_to_a15) << 12);
566		logical_address = offset << 12;
567		LOG(("swtpc09_dat_bank_unmap Logical address:%04X\n", offset << 12 ));
568		LOG(("swtpc09_dat_bank_set dat:%02X Logical address:%04X Physical address:%05X\n", data, offset << 12, physical_address ));
	563	a16_to_a19 = data & 0xf0;
	564	a12_to_a15 = ~data & 0x0f; //lower 4 bits are inverted
	565	physical_address = ((a16_to_a19 + a12_to_a15) << 12);
	566	logical_address = offset << 12;
	567	LOG(("swtpc09_dat_bank_unmap Logical address:%04X\n", offset << 12 ));
	568	LOG(("swtpc09_dat_bank_set dat:%02X Logical address:%04X Physical address:%05X\n", data, offset << 12, physical_address ));
569	569
570	570
571		// unmap page to be changed
	571	// unmap page to be changed
572	572	mem.unmap_readwrite(offset << 12, (offset << 12)+0x0fff);
573	573
574		// map in new page
575		if (a12_to_a15 == 0x0e) // 0xE000 address range to be mapped in at this page
576		{
577		if (m_system_type == FLEX_DMF2) // if flex/sbug, map in acia at 0xE004
578		{
	574	// map in new page
	575	if (a12_to_a15 == 0x0e) // 0xE000 address range to be mapped in at this page
	576	{
	577	if (m_system_type == FLEX_DMF2) // if flex/sbug, map in acia at 0xE004
	578	{
579	579	mem.nop_readwrite(logical_address+0x000, logical_address+0x003);
580		mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
581		mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
582		mem.nop_readwrite(logical_address+0x006, logical_address+0x07f);
583		mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
584		mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
585		mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
	580	mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
	581	mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
	582	mem.nop_readwrite(logical_address+0x006, logical_address+0x07f);
	583	mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
	584	mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
	585	mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
586	586	}
587		else if (m_system_type == FLEX_DC4_PIAIDE) // if flex/sbug and dc4 and piaide
588		{
	587	else if (m_system_type == FLEX_DC4_PIAIDE) // if flex/sbug and dc4 and piaide
	588	{
589	589	mem.nop_readwrite(logical_address+0x000, logical_address+0x003);
590		mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
591		mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
592		mem.install_write_handler(logical_address+0x014, logical_address+0x014, write8_delegate(FUNC(swtpc09_state::dc4_control_reg_w),this));
593		mem.install_readwrite_handler(logical_address+0x018, logical_address+0x01b, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
594		//mem.nop_readwrite(logical_address+0x01c, logical_address+0x05f);
595		mem.install_readwrite_handler(logical_address+0x060, logical_address+0x06f, read8_delegate(FUNC(pia6821_device::read), piaide), write8_delegate(FUNC(pia6821_device::write), piaide));
596		//mem.nop_readwrite(logical_address+0x070, logical_address+0x07f);
597		mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
598		mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
599		//mem.nop_readwrite(logical_address+0x0a0, logical_address+0x7ff);
600		mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xe800]); //piaide rom
	590	mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
	591	mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
	592	mem.install_write_handler(logical_address+0x014, logical_address+0x014, write8_delegate(FUNC(swtpc09_state::dc4_control_reg_w),this));
	593	mem.install_readwrite_handler(logical_address+0x018, logical_address+0x01b, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
	594	//mem.nop_readwrite(logical_address+0x01c, logical_address+0x05f);
	595	mem.install_readwrite_handler(logical_address+0x060, logical_address+0x06f, read8_delegate(FUNC(pia6821_device::read), piaide), write8_delegate(FUNC(pia6821_device::write), piaide));
	596	//mem.nop_readwrite(logical_address+0x070, logical_address+0x07f);
	597	mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
	598	mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
	599	//mem.nop_readwrite(logical_address+0x0a0, logical_address+0x7ff);
	600	mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xe800]); //piaide rom
601	601	}
602	602	else // assume unibug, map in acia at 0xE000
603	603	{
604		mem.install_readwrite_handler(logical_address+0x000, logical_address+0x000, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w), acia));
605		mem.install_readwrite_handler(logical_address+0x001, logical_address+0x001, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w), acia));
	604	mem.install_readwrite_handler(logical_address+0x000, logical_address+0x000, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w), acia));
	605	mem.install_readwrite_handler(logical_address+0x001, logical_address+0x001, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w), acia));
606	606	mem.nop_readwrite(logical_address+0x002, logical_address+0x07f);
607		mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
608		mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
609		mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
610		}
611		}
612		else if (a12_to_a15 == 0x0f) // 0xF000 address range to be mapped in at this page
613		{
614		if (m_system_type == UNIFLEX_DMF2 \|\| m_system_type == FLEX_DMF2) // if DMF2 conroller this is the map
615		{
616		mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
617		mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
618		mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
619		mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
620		//mem.nop_readwrite(logical_address+0x042, logical_address+0x7ff);
621		mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
622		mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
623		}
624		else if (m_system_type == FLEX_DC4_PIAIDE) // 2k ram for piaide on s09 board
625		{
626		//mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
627		//mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
628		//mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
629		//mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
630		mem.install_ram(logical_address+0x000, logical_address+0x7ff, &RAM[0xf000]);
631		mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
632		mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
633		}
634		else // assume DMF3 controller
635		{
	607	mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
	608	mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
	609	mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
	610	}
	611	}
	612	else if (a12_to_a15 == 0x0f) // 0xF000 address range to be mapped in at this page
	613	{
	614	if (m_system_type == UNIFLEX_DMF2 \|\| m_system_type == FLEX_DMF2) // if DMF2 conroller this is the map
	615	{
636	616	mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
637		mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
638		mem.install_readwrite_handler(logical_address+0x024, logical_address+0x024, read8_delegate(FUNC(swtpc09_state::dmf3_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_control_reg_w),this));
639		mem.install_readwrite_handler(logical_address+0x025, logical_address+0x025, read8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_w),this));
640		//mem.nop_readwrite(logical_address+0x030, logical_address+0x03f);
641		mem.install_readwrite_handler(logical_address+0x040, logical_address+0x04f, read8_delegate(FUNC(via6522_device::read), via), write8_delegate(FUNC(via6522_device::write), via));
642		//mem.nop_readwrite(logical_address+0x050, logical_address+0x7ff);
643		mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
644		mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
645		}
646		}
647		else if (offset==0x0f) // then we need to leave in top part of ram and dat write
648		{
649		mem.install_ram(logical_address, logical_address+0x0eff, 0, 0, &RAM[physical_address]);
650		mem.install_rom(logical_address+0xf00, logical_address+0xfff, 0, 0, &RAM[0xff00]);
651		mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
	617	mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
	618	mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
	619	mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
	620	//mem.nop_readwrite(logical_address+0x042, logical_address+0x7ff);
	621	mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
	622	mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
	623	}
	624	else if (m_system_type == FLEX_DC4_PIAIDE) // 2k ram for piaide on s09 board
	625	{
	626	//mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
	627	//mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
	628	//mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
	629	//mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
	630	mem.install_ram(logical_address+0x000, logical_address+0x7ff, &RAM[0xf000]);
	631	mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
	632	mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
	633	}
	634	else // assume DMF3 controller
	635	{
	636	mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
	637	mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
	638	mem.install_readwrite_handler(logical_address+0x024, logical_address+0x024, read8_delegate(FUNC(swtpc09_state::dmf3_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_control_reg_w),this));
	639	mem.install_readwrite_handler(logical_address+0x025, logical_address+0x025, read8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_w),this));
	640	//mem.nop_readwrite(logical_address+0x030, logical_address+0x03f);
	641	mem.install_readwrite_handler(logical_address+0x040, logical_address+0x04f, read8_delegate(FUNC(via6522_device::read), via), write8_delegate(FUNC(via6522_device::write), via));
	642	//mem.nop_readwrite(logical_address+0x050, logical_address+0x7ff);
	643	mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
	644	mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
	645	}
	646	}
	647	else if (offset==0x0f) // then we need to leave in top part of ram and dat write
	648	{
	649	mem.install_ram(logical_address, logical_address+0x0eff, 0, 0, &RAM[physical_address]);
	650	mem.install_rom(logical_address+0xf00, logical_address+0xfff, 0, 0, &RAM[0xff00]);
	651	mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
652	652
653	653	}
654		else // all the rest is treated as ram, 1MB ram emulated
655		{
656		mem.install_ram(logical_address, logical_address+0x0fff, &RAM[physical_address]);
657		}
	654	else // all the rest is treated as ram, 1MB ram emulated
	655	{
	656	mem.install_ram(logical_address, logical_address+0x0fff, &RAM[physical_address]);
	657	}
658	658
659		// unused code to limit to 256k ram
	659	// unused code to limit to 256k ram
660	660	// else if (!(a12_to_a15 & 0x0c) ) // limit ram to 256k \|\| a12_to_a15 == 0x02
661	661	// {
662	662	// memory_install_ram(space, logical_address, logical_address+0x0fff, 0, 0, &RAM[physical_address]);
663		// }
	663	// }
664	664	//
665		// else // all the rest is treated as unallocated
	665	// else // all the rest is treated as unallocated
666	666	// {
667	667	// memory_nop_readwrite(space, logical_address, logical_address+0x0fff, 0, 0);
668		// }
	668	// }
669	669
670	670	}
671	671
r29404	r29405
720	720
721	721	/* a read here clears the DMA end flag */
722	722	m_m6844_channel[offset - 0x10].control &= ~0x80;
723		if (m_m6844_interrupt & 0x80) // if interrupt is active, then clear
724		{
725		swtpc09_irq_handler(0x01, CLEAR_LINE);
726		m_m6844_interrupt &= 0x7f; // clear interrupt indication bit 7
727		LOG(("swtpc09_6844_r interrupt cleared \n"));
	723	if (m_m6844_interrupt & 0x80) // if interrupt is active, then clear
	724	{
	725	swtpc09_irq_handler(0x01, CLEAR_LINE);
	726	m_m6844_interrupt &= 0x7f; // clear interrupt indication bit 7
	727	LOG(("swtpc09_6844_r interrupt cleared \n"));
728	728	}
729	729	break;
730	730
r29404	r29405
746	746	/* 0x17-0x1f not used */
747	747	default: break;
748	748	}
749		//LOG(("swtpc09_6844_r %02X %02X\n", offset, result & 0xff));
	749	//LOG(("swtpc09_6844_r %02X %02X\n", offset, result & 0xff));
750	750
751		if (m_system_type == UNIFLEX_DMF2 \|\| m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844
752		{
753		return ~result & 0xff;
	751	if (m_system_type == UNIFLEX_DMF2 \|\| m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844
	752	{
	753	return ~result & 0xff;
754	754	}
755		else
756		{
757		return result & 0xff;
758		}
	755	else
	756	{
	757	return result & 0xff;
	758	}
759	759	}
760	760
761	761
r29404	r29405
763	763	{
764	764	int i;
765	765
766		if (m_system_type == UNIFLEX_DMF2 \|\| m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844
767		data = ~data & 0xff;
	766	if (m_system_type == UNIFLEX_DMF2 \|\| m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844
	767	data = ~data & 0xff;
768	768
769		LOG(("swtpc09_6844_w %02X %02X\n", offset, data));
	769	LOG(("swtpc09_6844_w %02X %02X\n", offset, data));
770	770	/* switch off the offset we were given */
771	771	switch (offset)
772	772	{
r29404	r29405
849	849	/* interrupt control */
850	850	case 0x15:
851	851	m_m6844_interrupt = (m_m6844_interrupt & 0x80) \| (data & 0x7f);
852		LOG(("swtpc09_m_m6844_interrupt_w %02X\n", m_m6844_interrupt));
	852	LOG(("swtpc09_m_m6844_interrupt_w %02X\n", m_m6844_interrupt));
853	853	break;
854	854
855	855	/* chaining control */
r29404	r29405
865	865
866	866	DRIVER_INIT_MEMBER( swtpc09_state, swtpc09 )
867	867	{
868		int i;
869		m_pia_counter = 0; // init ptm/pia counter to 0
870		m_term_data = 0; // terminal keyboard input
871		m_fdc_status = 0; // for floppy controller
872		m_system_type = FLEX_DMF2;
873		m_interrupt = 0;
874		m_active_interrupt = FALSE;
	868	int i;
	869	m_pia_counter = 0; // init ptm/pia counter to 0
	870	m_term_data = 0; // terminal keyboard input
	871	m_fdc_status = 0; // for floppy controller
	872	m_system_type = FLEX_DMF2;
	873	m_interrupt = 0;
	874	m_active_interrupt = FALSE;
875	875
876	876	/* reset the 6844 */
877	877	for (i = 0; i < 4; i++)
r29404	r29405
887	887
888	888	DRIVER_INIT_MEMBER( swtpc09_state, swtpc09i )
889	889	{
890		int i;
891		m_pia_counter = 0; // init ptm/pia counter to 0
892		m_term_data = 0; // terminal keyboard input
893		m_fdc_status = 0; // for floppy controller
894		m_system_type = FLEX_DC4_PIAIDE;
895		m_interrupt = 0;
896		m_active_interrupt = FALSE;
	890	int i;
	891	m_pia_counter = 0; // init ptm/pia counter to 0
	892	m_term_data = 0; // terminal keyboard input
	893	m_fdc_status = 0; // for floppy controller
	894	m_system_type = FLEX_DC4_PIAIDE;
	895	m_interrupt = 0;
	896	m_active_interrupt = FALSE;
897	897
898	898	/* reset the 6844 */
899	899	for (i = 0; i < 4; i++)
r29404	r29405
909	909
910	910	DRIVER_INIT_MEMBER( swtpc09_state, swtpc09u )
911	911	{
912		int i;
913		m_pia_counter = 0; //init ptm/pia counter to 0
914		m_term_data = 0; //terminal keyboard input
915		m_fdc_status = 0; // for floppy controller
916		m_system_type = UNIFLEX_DMF2;
917		m_interrupt = 0;
918		m_active_interrupt = FALSE;
	912	int i;
	913	m_pia_counter = 0; //init ptm/pia counter to 0
	914	m_term_data = 0; //terminal keyboard input
	915	m_fdc_status = 0; // for floppy controller
	916	m_system_type = UNIFLEX_DMF2;
	917	m_interrupt = 0;
	918	m_active_interrupt = FALSE;
919	919
920	920	/* reset the 6844 */
921	921	for (i = 0; i < 4; i++)
r29404	r29405
931	931
932	932	DRIVER_INIT_MEMBER( swtpc09_state, swtpc09d3 )
933	933	{
934		int i;
935		m_pia_counter = 0; //init ptm/pia counter to 0
936		m_term_data = 0; //terminal keyboard input
937		m_fdc_status = 0; // for floppy controller
938		m_via_ca1_input = 0;
939		m_system_type = UNIFLEX_DMF3;
940		m_interrupt = 0;
941		m_active_interrupt = FALSE;
	934	int i;
	935	m_pia_counter = 0; //init ptm/pia counter to 0
	936	m_term_data = 0; //terminal keyboard input
	937	m_fdc_status = 0; // for floppy controller
	938	m_via_ca1_input = 0;
	939	m_system_type = UNIFLEX_DMF3;
	940	m_interrupt = 0;
	941	m_active_interrupt = FALSE;
942	942
943	943
944	944	/* reset the 6844 */

trunk/src/mess/machine/apple2gs.c
r29404	r29405
946	946	result = 0;
947	947	{
948	948	UINT8 temp = m_kbspecial->read();
949		if (temp & 1) // capslock
	949	if (temp & 1) // capslock
950	950	{
951	951	result \|= 4;
952	952	}
953		if (temp & 6) // shift
	953	if (temp & 6) // shift
954	954	{
955	955	result \|= 1;
956	956	}
957		if (temp & 8) // control
	957	if (temp & 8) // control
958	958	{
959	959	result \|= 2;
960	960	}
961		if (temp & 0x10) // open apple/command
	961	if (temp & 0x10) // open apple/command
962	962	{
963	963	result \|= 0x40;
964	964	}
965		if (temp & 0x20) // option
	965	if (temp & 0x20) // option
966	966	{
967	967	result \|= 0x80;
968	968	}

trunk/src/mess/machine/x68k_kbd.c
r29404	r29405
355	355	//m_mfp.rsr \|= 0x80; // Buffer full
356	356	//if(ioport("options")->read() & 0x01)
357	357	//{
358		// m_current_vector[6] = 0x4c;
359		// m_maincpu->set_input_line_and_vector(6,ASSERT_LINE,0x4c);
360		// logerror("MFP: Receive buffer full IRQ sent\n");
	358	// m_current_vector[6] = 0x4c;
	359	// m_maincpu->set_input_line_and_vector(6,ASSERT_LINE,0x4c);
	360	// logerror("MFP: Receive buffer full IRQ sent\n");
361	361	//}
362	362	}
363	363	}

trunk/src/mess/machine/hp48.c
r29404	r29405
450	450	bit 1: transmitting
451	451	bit 2: irq enable on buffer empty
452	452	bit 3: led on (direct mode)
453		on HP49 G, flash ROM write enable
	453	on HP49 G, flash ROM write enable
454	454
455	455	- 0x1d: I/R output buffer
456	456	*/
r29404	r29405
576	576
577	577	READ8_MEMBER(hp48_state::hp48_bank_r)
578	578	{
579		/* HP48 GX
	579	/* HP48 GX
580	580	bit 0: ignored
581	581	bits 2-5: bank number
582		bit 6: enable
	582	bit 6: enable
583	583	*/
584	584
585	585	/* HP49 G
r29404	r29405
746	746	else
747	747	{
748	748	/* NCE3 */
749		nce3_enable = m_bank_switch >> 6;
	749	nce3_enable = m_bank_switch >> 6;
750	750	LOG(( "hp48_apply_modules: A19 disabled, NCE3 %s\n", nce3_enable ? "enabled" : "disabled" ));
751	751	space.install_read_bank( 0, 0x7ffff, 0, 0x80000, "bank5" );
752	752	}
r29404	r29405
1130	1130	m_model = model;
1131	1131
1132	1132	/* internal RAM */
1133		ram_size =
	1133	ram_size =
1134	1134	HP49_G_MODEL ? (512 * 1024) :
1135	1135	HP48_GX_MODEL ? (128 * 1024) : (32 * 1024);
1136	1136
r29404	r29405
1139	1139
1140	1140
1141	1141	/* ROM load */
1142		rom_size =
	1142	rom_size =
1143	1143	HP49_G_MODEL ? (2048 * 1024) :
1144	1144	HP48_S_SERIES ? (256 * 1024) : (512 * 1024);
1145	1145	m_rom = auto_alloc_array(machine(), UINT8, 2 * rom_size);

trunk/src/mess/machine/apricotkb.c
r29404	r29405
52	52
53	53	#ifdef UPD7507_EMULATED
54	54	static ADDRESS_MAP_START( apricot_keyboard_io, AS_IO, 8, apricot_keyboard_device )
55		AM_RANGE(0x00, 0x00) AM_READ(kb_lo_r)
56		AM_RANGE(0x01, 0x01) AM_READ(kb_hi_r)
57		AM_RANGE(0x03, 0x03) AM_WRITE(kb_p3_w)
58		AM_RANGE(0x04, 0x04) AM_WRITE(kb_y0_w)
59		AM_RANGE(0x05, 0x05) AM_WRITE(kb_y4_w)
60		AM_RANGE(0x06, 0x06) AM_READWRITE(kb_p6_r, kb_yc_w)
61		AM_RANGE(0x07, 0x07) AM_WRITE(kb_y8_w)
	55	AM_RANGE(0x00, 0x00) AM_READ(kb_lo_r)
	56	AM_RANGE(0x01, 0x01) AM_READ(kb_hi_r)
	57	AM_RANGE(0x03, 0x03) AM_WRITE(kb_p3_w)
	58	AM_RANGE(0x04, 0x04) AM_WRITE(kb_y0_w)
	59	AM_RANGE(0x05, 0x05) AM_WRITE(kb_y4_w)
	60	AM_RANGE(0x06, 0x06) AM_READWRITE(kb_p6_r, kb_yc_w)
	61	AM_RANGE(0x07, 0x07) AM_WRITE(kb_y8_w)
62	62	ADDRESS_MAP_END
63	63	#endif
64	64
r29404	r29405
69	69
70	70	static MACHINE_CONFIG_FRAGMENT( apricot_keyboard )
71	71	#ifdef UPD7507_EMULATED
72		MCFG_CPU_ADD(UPD7507C_TAG, UPD7507, XTAL_32_768kHz)
73		MCFG_CPU_IO_MAP(apricot_keyboard_io)
	72	MCFG_CPU_ADD(UPD7507C_TAG, UPD7507, XTAL_32_768kHz)
	73	MCFG_CPU_IO_MAP(apricot_keyboard_io)
74	74	#endif
75	75	MACHINE_CONFIG_END
76	76

trunk/src/mess/machine/sgi.c
r29404	r29405
88	88	}
89	89
90	90	timer_init();
91
	91
92	92	save_item(NAME(m_nCPUControl0));
93	93	save_item(NAME(m_nCPUControl1));
94	94	save_item(NAME(m_nWatchdog));

trunk/src/mess/machine/apricotkb.h
r29404	r29405
46	46	apricot_keyboard_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
47	47
48	48	template<class _Object> static devcb2_base &set_txd_wr_callback(device_t &device, _Object object) { return downcast<apricot_keyboard_device &>(device).m_write_txd.set_callback(object); }
49
	49
50	50	// optional information overrides
51	51	virtual const rom_entry *device_rom_region() const;
52	52	virtual machine_config_constructor device_mconfig_additions() const;

trunk/src/mess/machine/micropolis.h
r29404	r29405
38	38	***************************************************************************/
39	39
40	40	class micropolis_device : public device_t,
41		public micropolis_interface
	41	public micropolis_interface
42	42	{
43	43	public:
44	44	micropolis_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);

trunk/src/mess/machine/bbc.c
r29404	r29405
1445	1445	WRITE_LINE_MEMBER(bbc_state::write_acia_clock)
1446	1446	{
1447	1447	m_acia->write_txc(state);
1448
	1448
1449	1449	if (m_serproc_data & 0x40)
1450	1450	m_acia->write_rxc(state);
1451	1451	}
r29404	r29405
1965	1965	UINT8 *RAM = m_region_user1->base();
1966	1966	int size, read_;
1967	1967	int addr = 0x8000 + (0x4000 * index);
1968
	1968
1969	1969	if (image.software_entry() == NULL)
1970	1970	{
1971	1971	size = image.length();
1972	1972	logerror("loading rom %s, at %.4x size:%.4x\n", image.filename(), addr, size);
1973
	1973
1974	1974	switch (size)
1975	1975	{
1976	1976	case 0x2000:
r29404	r29405
1988	1988	logerror("bad rom file size of %.4x\n", size);
1989	1989	break;
1990	1990	}
1991
	1991
1992	1992	if (read_ != size)
1993	1993	return IMAGE_INIT_FAIL;
1994	1994	}
r29404	r29405
2005	2005
2006	2006	if (strcmp(image.device().tag(),":exp_rom3") == 0)
2007	2007	return exp_rom_load(image, 2);
2008
	2008
2009	2009	if (strcmp(image.device().tag(),":exp_rom4") == 0)
2010	2010	return exp_rom_load(image, 3);
2011	2011
r29404	r29405
2038	2038	image.seterror(IMAGE_ERROR_UNSUPPORTED, "Invalid rom file size");
2039	2039	return IMAGE_INIT_FAIL;
2040	2040	}
2041
	2041
2042	2042	image.fread(RAM + addr, size);
2043	2043	}
2044	2044	else

trunk/src/mess/machine/sgi.h
r29404	r29405
66	66	UINT32 m_nDMAMode;
67	67	UINT32 m_nDMAZoomByteCnt;
68	68	UINT32 m_nDMARunning;
69
	69
70	70	void update();
71	71	TIMER_CALLBACK_MEMBER(update_callback);
72	72	void timer_init();

trunk/src/mess/machine/smartmed.c
r29404	r29405
76	76
77	77	nand_device::nand_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
78	78	: device_t(mconfig, NAND, "NAND Flash Memory", tag, owner, clock, "nand", __FILE__),
79		m_write_rnb(*this)
	79	m_write_rnb(*this)
80	80	{
81	81	}
82	82	nand_device::nand_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source)
83	83	: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
84		m_write_rnb(*this)
	84	m_write_rnb(*this)
85	85	{
86	86	}
87	87

trunk/src/mess/machine/zx8302.h
r29404	r29405
64	64
65	65	#define MCFG_ZX8302_OUT_NETOUT_CB(_devcb) \
66	66	devcb = &zx8302_device::set_out_netout_callback(*device, DEVCB2_##_devcb);
67
	67
68	68	#define MCFG_ZX8302_OUT_MDSELCK_CB(_devcb) \
69	69	devcb = &zx8302_device::set_out_mdselck_callback(*device, DEVCB2_##_devcb);
70	70
r29404	r29405
79	79
80	80	#define MCFG_ZX8302_OUT_RAW1_CB(_devcb) \
81	81	devcb = &zx8302_device::set_out_raw1_callback(*device, DEVCB2_##_devcb);
82
	82
83	83	#define MCFG_ZX8302_IN_RAW1_CB(_devcb) \
84	84	devcb = &zx8302_device::set_in_raw1_callback(*device, DEVCB2_##_devcb);
85	85
r29404	r29405
102	102	public:
103	103	// construction/destruction
104	104	zx8302_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
105
	105
106	106	static void set_rtc_clock(device_t &device, int rtc_clock) { downcast<zx8302_device &>(device).m_rtc_clock = rtc_clock; }
107	107	template<class _Object> static devcb2_base &set_out_ipl1l_callback(device_t &device, _Object object) { return downcast<zx8302_device &>(device).m_out_ipl1l_cb.set_callback(object); }
108	108	template<class _Object> static devcb2_base &set_out_baudx4_callback(device_t &device, _Object object) { return downcast<zx8302_device &>(device).m_out_baudx4_cb.set_callback(object); }
r29404	r29405
239	239	UINT8 m_status; // status register
240	240
241	241	// IPC communication state
242		int m_comdata_from_ipc; // pending data from IPC->68000
243		int m_comdata_to_cpu; // communication data IPC->68000
244		int m_comdata_to_ipc; // communication data 68000->IPC
	242	int m_comdata_from_ipc; // pending data from IPC->68000
	243	int m_comdata_to_cpu; // communication data IPC->68000
	244	int m_comdata_to_ipc; // communication data 68000->IPC
245	245	int m_comctl; // communication control
246	246	int m_ipc_state; // communication state
247	247	int m_ipc_busy; // IPC busy

trunk/src/mess/machine/apple2.c
r29404	r29405
2374	2374
2375	2375	static const UINT8 a2_key_remap[0x32][4] =
2376	2376	{
2377		/* norm shft ctrl both */
	2377	/* norm shft ctrl both */
2378	2378	{ 0x33,0x23,0x33,0x23 }, /* 3 # 00 */
2379	2379	{ 0x34,0x24,0x34,0x24 }, /* 4 $ 01 */
2380	2380	{ 0x35,0x25,0x35,0x25 }, /* 5 % 02 */
r29404	r29405
2432	2432	if (state == ASSERT_LINE)
2433	2433	{
2434	2434	int mod = 0;
2435		m_lastchar = m_ay3600->b_r();
	2435	m_lastchar = m_ay3600->b_r();
2436	2436
2437	2437	mod = (m_kbspecial->read() & 0x06) ? 0x01 : 0x00;
2438	2438	mod \|= (m_kbspecial->read() & 0x08) ? 0x02 : 0x00;
r29404	r29405
2442	2442	if (m_transchar != 0)
2443	2443	{
2444	2444	m_strobe = 0x80;
2445		// printf("new char = %04x (%02x)\n", m_lastchar&0x3f, m_transchar);
	2445	// printf("new char = %04x (%02x)\n", m_lastchar&0x3f, m_transchar);
2446	2446	}
2447	2447	}
2448	2448	}
r29404	r29405
2456	2456
2457	2457	m_lastchar = m_ay3600->b_r();
2458	2458
2459		trans = m_lastchar & ~(0x1c0); // clear the 3600's control/shift stuff
2460		trans \|= (m_lastchar & 0x100)>>2; // bring the 0x100 bit down to the 0x40 place
2461		trans <<= 2; // 4 entries per key
2462		trans \|= (m_kbspecial->read() & 0x06) ? 0x00 : 0x01; // shift is bit 1 (active low)
2463		trans \|= (m_kbspecial->read() & 0x08) ? 0x00 : 0x02; // control is bit 2 (active low)
2464		trans \|= (m_kbspecial->read() & 0x01) ? 0x0000 : 0x0200; // caps lock is bit 9 (active low)
	2459	trans = m_lastchar & ~(0x1c0); // clear the 3600's control/shift stuff
	2460	trans \|= (m_lastchar & 0x100)>>2; // bring the 0x100 bit down to the 0x40 place
	2461	trans <<= 2; // 4 entries per key
	2462	trans \|= (m_kbspecial->read() & 0x06) ? 0x00 : 0x01; // shift is bit 1 (active low)
	2463	trans \|= (m_kbspecial->read() & 0x08) ? 0x00 : 0x02; // control is bit 2 (active low)
	2464	trans \|= (m_kbspecial->read() & 0x01) ? 0x0000 : 0x0200; // caps lock is bit 9 (active low)
2465	2465
2466	2466	m_transchar = decode[trans];
2467	2467	m_strobe = 0x80;
2468	2468
2469		// printf("new char = %04x (%02x)\n", m_lastchar, m_transchar);
	2469	// printf("new char = %04x (%02x)\n", m_lastchar, m_transchar);
2470	2470	}
2471	2471	}

trunk/src/mess/machine/megacd.h
r29404	r29405
111	111
112	112	// set some variables at start, depending on region (shall be moved to a device interface?)
113	113	void set_framerate(int rate) { m_framerate = rate; }
114		void set_total_scanlines(int total) { m_base_total_scanlines = total; } // this gets set at start only
115		void update_total_scanlines(bool mode3) { m_total_scanlines = mode3 ? (m_base_total_scanlines * 2) : m_base_total_scanlines; } // this gets set at each EOF
	114	void set_total_scanlines(int total) { m_base_total_scanlines = total; } // this gets set at start only
	115	void update_total_scanlines(bool mode3) { m_total_scanlines = mode3 ? (m_base_total_scanlines * 2) : m_base_total_scanlines; } // this gets set at each EOF
116	116
117	117	void SCD_GET_TILE_INFO_16x16_1x1( int& tile_region, int& tileno, int tile_index );
118	118	void SCD_GET_TILE_INFO_32x32_1x1( int& tile_region, int& tileno, int tile_index );

trunk/src/mess/machine/svi318.c
r29404	r29405
741	741	{
742	742	return 0xff;
743	743	}
744
	744
745	745	fd1793_device *fdc = machine().device<fd1793_device>("wd179x");
746	746
747	747	switch( offset )
r29404	r29405
804	804	{
805	805	return;
806	806	}
807
	807
808	808	fd1793_device *fdc = machine().device<fd1793_device>("wd179x");
809	809
810	810	switch( offset )

trunk/src/mess/machine/a7800.c
r29404	r29405
19	19	added Activision bank select type
20	20	19-Feb-2010 DanB Added return values for TIA collision registers
21	21
22		04-Apr-2014 Mike Saarna Fix to controller button RIOT behavior and
23		expanded cart handling (bit 05).
	22	04-Apr-2014 Mike Saarna Fix to controller button RIOT behavior and
	23	expanded cart handling (bit 05).
24	24	***************************************************************************/
25	25
26	26	#include "emu.h"
r29404	r29405
406	406	if(m_cart_type & 0x04)
407	407	{
408	408	//adjust write location if supercart bankram is in use
409		if(m_cart_type & 0x20)
	409	if(m_cart_type & 0x20)
410	410	{
411	411	UINT8 currentbank1 = (UINT8 )m_bank1->base();
412	412	currentbank1[offset] = data;
r29404	r29405
435	435	if( m_cart_size == 0x10000 )
436	436	{
437	437	data &= 0x03;
438		}
	438	}
439	439	else if( m_cart_size == 0x40000 )
440	440	{
441	441	data &= 0x0f;

trunk/src/mess/machine/mac.c
r29404	r29405
1242	1242	// printf("VIA1 IN_A (PC %x)\n", m_maincpu->safe_pc());
1243	1243
1244	1244	#if LOG_ADB
1245		// printf("Read PM data %x\n", m_pm_data_recv);
	1245	// printf("Read PM data %x\n", m_pm_data_recv);
1246	1246	#endif
1247	1247	return m_pm_data_recv;
1248	1248	}
r29404	r29405
1312	1312	READ8_MEMBER(mac_state::mac_via_in_b_pmu)
1313	1313	{
1314	1314	int val = 0;
1315		// printf("Read VIA B: PM_ACK %x\n", m_pm_ack);
	1315	// printf("Read VIA B: PM_ACK %x\n", m_pm_ack);
1316	1316	val = 0x80 \| 0x04 \| m_pm_ack; // SCC wait/request (bit 2 must be set at 900c1a or startup tests always fail)
1317	1317
1318	1318	// printf("VIA1 IN_B = %02x (PC %x)\n", val, m_maincpu->safe_pc());
r29404	r29405
1358	1358	// printf("VIA1 OUT A: %02x (PC %x)\n", data, m_maincpu->safe_pc());
1359	1359
1360	1360	#if LOG_ADB
1361		// printf("%02x to PM\n", data);
	1361	// printf("%02x to PM\n", data);
1362	1362	#endif
1363	1363	m_pm_data_send = data;
1364	1364	return;
r29404	r29405
1657	1657
1658	1658	WRITE8_MEMBER(mac_state::mac_via2_out_b_pmu)
1659	1659	{
1660		// logerror("VIA2 OUT B PMU: %02x (PC %x)\n", data, m_maincpu->pc());
	1660	// logerror("VIA2 OUT B PMU: %02x (PC %x)\n", data, m_maincpu->pc());
1661	1661
1662	1662	if ((data & 4) && !(m_pm_req & 4))
1663	1663	{

trunk/src/mess/machine/beta.h
r29404	r29405
20	20	public:
21	21	beta_disk_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
22	22	~beta_disk_device() {}
23
	23
24	24	DECLARE_READ8_MEMBER(status_r);
25	25	DECLARE_READ8_MEMBER(track_r);
26	26	DECLARE_READ8_MEMBER(sector_r);
r29404	r29405
32	32	DECLARE_WRITE8_MEMBER(track_w);
33	33	DECLARE_WRITE8_MEMBER(sector_w);
34	34	DECLARE_WRITE8_MEMBER(data_w);
35
	35
36	36	DECLARE_WRITE_LINE_MEMBER(wd179x_intrq_w);
37	37	DECLARE_WRITE_LINE_MEMBER(wd179x_drq_w);
38
	38
39	39	int is_active();
40	40	void enable();
41	41	void disable();
42	42	void clear_status();
43
	43
44	44	UINT8 m_betadisk_status;
45	45	UINT8 m_betadisk_active;
46
	46
47	47	protected:
48	48	// device-level overrides
49	49	virtual void device_start();

trunk/src/mess/machine/nes.c
r29404	r29405
159	159
160	160	// install additional handlers (read_h, read_ex, write_ex)
161	161	if (m_cartslot->get_pcb_id() == STD_NROM368 \|\| m_cartslot->get_pcb_id() == GG_NROM \|\| m_cartslot->get_pcb_id() == CAMERICA_ALADDIN \|\| m_cartslot->get_pcb_id() == SUNSOFT_DCS
162		\|\| m_cartslot->get_pcb_id() == BANDAI_DATACH \|\| m_cartslot->get_pcb_id() == BANDAI_KARAOKE \|\| m_cartslot->get_pcb_id() == AVE_MAXI15
	162	\|\| m_cartslot->get_pcb_id() == BANDAI_DATACH \|\| m_cartslot->get_pcb_id() == BANDAI_KARAOKE \|\| m_cartslot->get_pcb_id() == AVE_MAXI15
163	163	\|\| m_cartslot->get_pcb_id() == KAISER_KS7022 \|\| m_cartslot->get_pcb_id() == KAISER_KS7031 \|\| m_cartslot->get_pcb_id() == BMC_VT5201
164	164	\|\| m_cartslot->get_pcb_id() == UNL_LH32 \|\| m_cartslot->get_pcb_id() == UNL_LH10 \|\| m_cartslot->get_pcb_id() == UNL_2708
165	165	\|\| m_cartslot->get_pcb_id() == UNL_43272 \|\| m_cartslot->get_pcb_id() == BMC_G63IN1 \|\| m_cartslot->get_pcb_id() == BMC_8157

trunk/src/mess/machine/mackbd.h
r29404	r29405
12	12	//**************************************************************************
13	13
14	14	#define MCFG_MACKBD_ADD(_tag) \
15		MCFG_DEVICE_ADD(_tag, MACKBD, 0)
	15	MCFG_DEVICE_ADD(_tag, MACKBD, 0)
16	16
17	17	#define MCFG_MACKBD_REPLACE(_tag) \
18		MCFG_DEVICE_REPLACE(_tag, MACKBD, 0)
	18	MCFG_DEVICE_REPLACE(_tag, MACKBD, 0)
19	19
20	20	#define MCFG_MACKBD_REMOVE(_tag) \
21		MCFG_DEVICE_REMOVE(_tag)
	21	MCFG_DEVICE_REMOVE(_tag)
22	22
23	23	#define MCFG_MACKBD_CLKOUT_HANDLER(_devcb) \
24	24	devcb = &mackbd_device::set_clkout_handler(*device, DEVCB2_##_devcb);

trunk/src/mess/machine/oric.c
r29404	r29405
55	55	if (m_is_telestrat==0)
56	56	{
57	57	/* oric 1 or oric atmos */
58
	58
59	59	/* if floppy disc hardware is disabled, do not allow interrupts from it */
60	60	if ((m_io_floppy->manager().safe_to_read()) && ((m_io_floppy->read() & 0x07) == ORIC_FLOPPY_INTERFACE_NONE))
61	61	{

trunk/src/mess/machine/mega32x.c
r29404	r29405
1582	1582	_32x_check_framebuffer_swap(scanline >= irq6);
1583	1583
1584	1584	m_32x_hcount_compare_val++;
1585
	1585
1586	1586	if (m_32x_hcount_compare_val >= m_32x_hcount_reg)
1587	1587	{
1588	1588	m_32x_hcount_compare_val = -1;
1589
	1589
1590	1590	if (scanline < 224 \|\| m_sh2_hint_in_vbl)
1591	1591	{
1592		if (m_sh2_master_hint_enable)
	1592	if (m_sh2_master_hint_enable)
1593	1593	m_master_cpu->set_input_line(SH2_HINT_IRQ_LEVEL, ASSERT_LINE);
1594	1594	if (m_sh2_slave_hint_enable)
1595	1595	m_slave_cpu->set_input_line(SH2_HINT_IRQ_LEVEL, ASSERT_LINE);

trunk/src/mess/machine/apollo_kbd.c
r29404	r29405
201	201
202	202	int apollo_kbd_device::beeper::keyboard_has_beeper()
203	203	{
204		return true; // driver has no facility to return false here, so go with it
	204	return true; // driver has no facility to return false here, so go with it
205	205	}
206	206
207	207	void apollo_kbd_device::beeper::beeper_callback()

trunk/src/mess/includes/apollo.h
r29404	r29405
301	301	apollo_graphics_15i(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock, device_type type, const char name, const char shortname, const char *source);
302	302	~apollo_graphics_15i();
303	303
304		UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	304	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
305	305
306	306	// monochrome control
307	307	DECLARE_READ8_MEMBER( apollo_mcr_r );
r29404	r29405
314	314	// color control
315	315	DECLARE_READ8_MEMBER( apollo_ccr_r );
316	316	DECLARE_WRITE8_MEMBER( apollo_ccr_w );
317
	317
318	318	DECLARE_READ16_MEMBER( apollo_mgm_r );
319	319	DECLARE_WRITE16_MEMBER( apollo_mgm_w );
320	320
321	321	DECLARE_READ16_MEMBER( apollo_cgm_r );
322	322	DECLARE_WRITE16_MEMBER( apollo_cgm_w );
323
	323
324	324	void vblank_state_changed(screen_device &screen, bool vblank_state);
325	325
326	326	int is_mono() { return m_n_planes == 1; }
r29404	r29405
347	347	void set_lut_cr(UINT8 data);
348	348
349	349	void register_vblank_callback();
350
	350
351	351	UINT32 set_msb0(UINT32 value, UINT8 data)
352	352	{
353	353	return (value & 0xffffff00) \| data;

trunk/src/mess/includes/tvc.h
r29404	r29405
38	38	// ======================> tvc_sound_device
39	39
40	40	class tvc_sound_device : public device_t,
41		public device_sound_interface
	41	public device_sound_interface
42	42	{
43	43	public:
44	44	// construction/destruction

trunk/src/mess/includes/nascom1.h
r29404	r29405
41	41	m_ram(*this, RAM_TAG),
42	42	m_videoram(*this, "videoram"),
43	43	m_gfxdecode(*this, "gfxdecode"),
44		m_palette(*this, "palette")
	44	m_palette(*this, "palette")
45	45	{ }
46	46
47	47	required_device<cpu_device> m_maincpu;

trunk/src/mess/includes/kaypro.h
r29404	r29405
101	101	required_device<floppy_connector> m_floppy1;
102	102	optional_device<mc6845_device> m_crtc;
103	103	required_device<beep_device> m_beep;
104		public:
	104	public:
105	105	required_device<palette_device> m_palette;
106	106	};
107	107

trunk/src/mess/includes/special.h
r29404	r29405
169	169	public:
170	170	specimx_sound_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
171	171	~specimx_sound_device() { }
172
	172
173	173	DECLARE_WRITE_LINE_MEMBER(set_input_ch0);
174	174	DECLARE_WRITE_LINE_MEMBER(set_input_ch1);
175	175	DECLARE_WRITE_LINE_MEMBER(set_input_ch2);
176
	176
177	177	protected:
178	178	// device-level overrides
179	179	virtual void device_start();

trunk/src/mess/includes/p2000t.h
r29404	r29405
22	22	m_speaker(*this, "speaker"),
23	23	m_videoram(*this, "videoram"),
24	24	m_gfxdecode(*this, "gfxdecode"),
25		m_palette(*this, "palette")
	25	m_palette(*this, "palette")
26	26	{ }
27	27
28	28	required_device<cpu_device> m_maincpu;

trunk/src/mess/includes/amstrad.h
r29404	r29405
288	288	optional_ioport m_io_analog4;
289	289	required_device<screen_device> m_screen;
290	290	required_device<palette_device> m_palette;
291
	291
292	292	void amstrad_init_lookups();
293	293	void amstrad_vh_update_mode();
294	294	void amstrad_plus_dma_parse(int channel);

trunk/src/mess/includes/dm7000.h
r29404	r29405
41	41
42	42	DECLARE_WRITE16_MEMBER ( dm7000_enet_w );
43	43	DECLARE_READ16_MEMBER ( dm7000_enet_r );
44
	44
45	45	DECLARE_READ32_MEMBER( dcr_r );
46	46	DECLARE_WRITE32_MEMBER( dcr_w );
47
48
	47
	48
49	49	UINT16 m_enet_regs[32];
50	50
51	51	UINT32 dcr[1024];

trunk/src/mess/includes/swtpc09.h
r29404	r29405
1	1	/***************************************************************************
2		swtpc09 include file
3		Robert Justice ,2009-2014
	2	swtpc09 include file
	3	Robert Justice ,2009-2014
4	4
5	5	****************************************************************************/
6	6
r29404	r29405
32	32	swtpc09_state(const machine_config &mconfig, device_type type, const char *tag)
33	33	: driver_device(mconfig, type, tag),
34	34	m_maincpu(*this, "maincpu"),
35		m_pia(*this, "pia"),
36		m_ptm(*this, "ptm"),
	35	m_pia(*this, "pia"),
	36	m_ptm(*this, "ptm"),
37	37	m_acia(*this, "acia"),
38	38	m_fdc(*this, "fdc"),
39	39	m_via(*this, "via"),
40		m_piaide(*this, "piaide"),
41		m_harddisk(*this, "harddisk"),
42		m_ide(*this, "ide")
	40	m_piaide(*this, "piaide"),
	41	m_harddisk(*this, "harddisk"),
	42	m_ide(*this, "ide")
43	43	{ }
44	44
45	45	required_device<cpu_device> m_maincpu;
r29404	r29405
56	56	DECLARE_READ8_MEMBER(pia0_ca1_r);
57	57	DECLARE_WRITE_LINE_MEMBER( pia0_irq_a );
58	58
59		DECLARE_WRITE8_MEMBER( ptm_o1_callback );
60		DECLARE_WRITE8_MEMBER( ptm_o3_callback );
61		DECLARE_WRITE_LINE_MEMBER( ptm_irq );
	59	DECLARE_WRITE8_MEMBER( ptm_o1_callback );
	60	DECLARE_WRITE8_MEMBER( ptm_o3_callback );
	61	DECLARE_WRITE_LINE_MEMBER( ptm_irq );
62	62
63	63	DECLARE_WRITE_LINE_MEMBER( acia_interrupt );
64	64	DECLARE_WRITE_LINE_MEMBER( write_acia_clock );
65	65
66		DECLARE_WRITE_LINE_MEMBER( fdc_intrq_w );
67		DECLARE_WRITE_LINE_MEMBER( fdc_drq_w );
	66	DECLARE_WRITE_LINE_MEMBER( fdc_intrq_w );
	67	DECLARE_WRITE_LINE_MEMBER( fdc_drq_w );
68	68
69	69	DECLARE_READ8_MEMBER( dmf3_via_read_porta );
70	70	DECLARE_READ8_MEMBER( dmf3_via_read_portb );
r29404	r29405
74	74
75	75	DECLARE_READ8_MEMBER(piaide_a_r);
76	76	DECLARE_READ8_MEMBER(piaide_b_r);
77		DECLARE_WRITE8_MEMBER(piaide_a_w);
78		DECLARE_WRITE8_MEMBER(piaide_b_w);
	77	DECLARE_WRITE8_MEMBER(piaide_a_w);
	78	DECLARE_WRITE8_MEMBER(piaide_b_w);
79	79
80	80	DECLARE_WRITE8_MEMBER(swtpc09_kbd_put);
81	81
82		DECLARE_READ8_MEMBER ( dmf2_dma_address_reg_r );
83		DECLARE_WRITE8_MEMBER ( dmf2_dma_address_reg_w );
84		DECLARE_READ8_MEMBER ( dmf2_control_reg_r );
85		DECLARE_WRITE8_MEMBER ( dmf2_control_reg_w );
	82	DECLARE_READ8_MEMBER ( dmf2_dma_address_reg_r );
	83	DECLARE_WRITE8_MEMBER ( dmf2_dma_address_reg_w );
	84	DECLARE_READ8_MEMBER ( dmf2_control_reg_r );
	85	DECLARE_WRITE8_MEMBER ( dmf2_control_reg_w );
86	86
87		DECLARE_READ8_MEMBER ( dmf3_dma_address_reg_r );
88		DECLARE_WRITE8_MEMBER ( dmf3_dma_address_reg_w );
89		DECLARE_READ8_MEMBER ( dmf3_control_reg_r );
90		DECLARE_WRITE8_MEMBER ( dmf3_control_reg_w );
	87	DECLARE_READ8_MEMBER ( dmf3_dma_address_reg_r );
	88	DECLARE_WRITE8_MEMBER ( dmf3_dma_address_reg_w );
	89	DECLARE_READ8_MEMBER ( dmf3_control_reg_r );
	90	DECLARE_WRITE8_MEMBER ( dmf3_control_reg_w );
91	91
92		DECLARE_WRITE8_MEMBER ( dc4_control_reg_w );
	92	DECLARE_WRITE8_MEMBER ( dc4_control_reg_w );
93	93
94		DECLARE_WRITE8_MEMBER(dat_w);
95
96		DECLARE_DRIVER_INIT( swtpc09 );
97		DECLARE_DRIVER_INIT( swtpc09i );
98		DECLARE_DRIVER_INIT( swtpc09u );
99		DECLARE_DRIVER_INIT( swtpc09d3 );
100
	94	DECLARE_WRITE8_MEMBER(dat_w);
	95
	96	DECLARE_DRIVER_INIT( swtpc09 );
	97	DECLARE_DRIVER_INIT( swtpc09i );
	98	DECLARE_DRIVER_INIT( swtpc09u );
	99	DECLARE_DRIVER_INIT( swtpc09d3 );
	100
101	101	void swtpc09_fdc_dma_transfer();
102		void swtpc09_irq_handler(UINT8 peripheral, UINT8 state);
	102	void swtpc09_irq_handler(UINT8 peripheral, UINT8 state);
103	103
104	104	UINT8 m_term_data; // terminal keyboard value
105	105	UINT8 m_pia_counter; // this is the counter on pia porta
r29404	r29405
112	112	UINT8 m_piaide_portb;
113	113	UINT8 m_active_interrupt;
114	114	UINT8 m_interrupt;
115
116
	115
	116
117	117	// TODO: move this in proper device
118
	118
119	119	/* channel_data structure holds info about each 6844 DMA channel */
120	120	typedef struct m6844_channel_data
121	121	{
r29404	r29405
143	143	extern const ptm6840_interface swtpc09_6840_intf;
144	144
145	145	#endif /* swtpc09_H_ */
146
147
148

trunk/src/mess/includes/ql.h
r29404	r29405
32	32	#define X3 XTAL_4_436MHz
33	33	#define X4 XTAL_11MHz
34	34
35		#define QL_CONFIG_PORT "config"
36		#define QIMI_PORT_MASK 0x01
37		#define QIMI_NONE 0x00
38		#define QIMI_MOUSE 0x01
39		#define DISK_TYPE_MASK 0x06
40		#define DISK_TYPE_NONE 0x00
41		#define DISK_TYPE_TRUMP 0x02
42		#define DISK_TYPE_SANDY_SD 0x04
43		#define DISK_TYPE_SANDY_SQB 0x06
44		#define IS_SANDY_DISK(__dtype__) ((__dtype__ == DISK_TYPE_SANDY_SD) \|\| (__dtype__ == DISK_TYPE_SANDY_SQB))
	35	#define QL_CONFIG_PORT "config"
	36	#define QIMI_PORT_MASK 0x01
	37	#define QIMI_NONE 0x00
	38	#define QIMI_MOUSE 0x01
	39	#define DISK_TYPE_MASK 0x06
	40	#define DISK_TYPE_NONE 0x00
	41	#define DISK_TYPE_TRUMP 0x02
	42	#define DISK_TYPE_SANDY_SD 0x04
	43	#define DISK_TYPE_SANDY_SQB 0x06
	44	#define IS_SANDY_DISK(__dtype__) ((__dtype__ == DISK_TYPE_SANDY_SD) \|\| (__dtype__ == DISK_TYPE_SANDY_SQB))
45	45
46		#define TRUMP_DRIVE1_MASK 0x01
47		#define TRUMP_DRIVE0_MASK 0x02
48		#define TRUMP_MOTOR_MASK 0x04
49		#define TRUMP_SIDE_SHIFT 3
50		#define TRUMP_SIDE_MASK (1 << TRUMP_SIDE_SHIFT)
	46	#define TRUMP_DRIVE1_MASK 0x01
	47	#define TRUMP_DRIVE0_MASK 0x02
	48	#define TRUMP_MOTOR_MASK 0x04
	49	#define TRUMP_SIDE_SHIFT 3
	50	#define TRUMP_SIDE_MASK (1 << TRUMP_SIDE_SHIFT)
51	51
52		#define CART_ROM_BASE 0x0c000
53		#define CART_ROM_END 0x0ffff
	52	#define CART_ROM_BASE 0x0c000
	53	#define CART_ROM_END 0x0ffff
54	54
55		#define TRUMP_ROM_MBASE 0x10000
56		#define TRUMP_ROM_BASE 0x14000
57		#define TRUMP_ROM_LEN 0x08000
58		#define TRUMP_ROM_END (TRUMP_ROM_MBASE+(TRUMP_ROM_LEN-1))
	55	#define TRUMP_ROM_MBASE 0x10000
	56	#define TRUMP_ROM_BASE 0x14000
	57	#define TRUMP_ROM_LEN 0x08000
	58	#define TRUMP_ROM_END (TRUMP_ROM_MBASE+(TRUMP_ROM_LEN-1))
59	59
60		#define TRUMP_IO_BASE 0x1c000
61		#define TRUMP_IO_LEN 0x04000
62		#define TRUMP_IO_END (TRUMP_IO_BASE+(TRUMP_IO_LEN-1))
	60	#define TRUMP_IO_BASE 0x1c000
	61	#define TRUMP_IO_LEN 0x04000
	62	#define TRUMP_IO_END (TRUMP_IO_BASE+(TRUMP_IO_LEN-1))
63	63
64		#define SANDY_ROM_BASE_SD 0x1c000
65		#define SANDY_ROM_BASE_SQB 0x20000
66		#define SANDY_IO_BASE 0xc3fc0
67		#define SANDY_IO_LEN 0x00040
68		#define SANDY_IO_END (SANDY_IO_BASE+(SANDY_IO_LEN-1))
	64	#define SANDY_ROM_BASE_SD 0x1c000
	65	#define SANDY_ROM_BASE_SQB 0x20000
	66	#define SANDY_IO_BASE 0xc3fc0
	67	#define SANDY_IO_LEN 0x00040
	68	#define SANDY_IO_END (SANDY_IO_BASE+(SANDY_IO_LEN-1))
69	69
70	70	#define SANDY_DRIVE0_MASK 0x02
71	71	#define SANDY_DRIVE1_MASK 0x04
r29404	r29405
76	76	#define SANDY_DDEN_MASK (1 << SANDY_DDEN_SHIFT)
77	77	#define SANDY_PRINTER_STROBE 0x20
78	78	#define SANDY_PRINTER_INTMASK 0x40
79		#define SANDY_MOUSE_INTMASK 0x80
	79	#define SANDY_MOUSE_INTMASK 0x80
80	80
81		#define MOUSEX_TAG "MOUSEX"
82		#define MOUSEY_TAG "MOUSEY"
83		#define MOUSEB_TAG "MOUSEB"
	81	#define MOUSEX_TAG "MOUSEX"
	82	#define MOUSEY_TAG "MOUSEY"
	83	#define MOUSEB_TAG "MOUSEB"
84	84
85	85	// Mouse bits in Sandy port order
86		#define MOUSE_MIDDLE 0x02
87		#define MOUSE_RIGHT 0x04
88		#define MOUSE_LEFT 0x08
89		#define MOUSE_DIRY 0x10
90		#define MOUSE_DIRX 0x20
91		#define MOUSE_INTY 0x40
92		#define MOUSE_INTX 0x80
93		#define MOUSE_INT_MASK (MOUSE_INTX \| MOUSE_INTY)
	86	#define MOUSE_MIDDLE 0x02
	87	#define MOUSE_RIGHT 0x04
	88	#define MOUSE_LEFT 0x08
	89	#define MOUSE_DIRY 0x10
	90	#define MOUSE_DIRX 0x20
	91	#define MOUSE_INTY 0x40
	92	#define MOUSE_INTX 0x80
	93	#define MOUSE_INT_MASK (MOUSE_INTX \| MOUSE_INTY)
94	94
95		#define QIMI_IO_BASE 0x1bf9c
96		#define QIMI_IO_LEN 0x22
97		#define QIMI_IO_END (QIMI_IO_BASE + QIMI_IO_LEN )
	95	#define QIMI_IO_BASE 0x1bf9c
	96	#define QIMI_IO_LEN 0x22
	97	#define QIMI_IO_END (QIMI_IO_BASE + QIMI_IO_LEN )
98	98
99		#define QIMI_INTX 0x04
100		#define QIMI_INTY 0x20
101		#define QIMI_DIRX 0x10
102		#define QIMI_DIRY 0x01
103		#define QIMI_LEFT 0x20
104		#define QIMI_RIGHT 0x10
105		#define QIMI_INT_MASK (QIMI_INTX \| QIMI_INTY)
	99	#define QIMI_INTX 0x04
	100	#define QIMI_INTY 0x20
	101	#define QIMI_DIRX 0x10
	102	#define QIMI_DIRY 0x01
	103	#define QIMI_LEFT 0x20
	104	#define QIMI_RIGHT 0x10
	105	#define QIMI_INT_MASK (QIMI_INTX \| QIMI_INTY)
106	106
107	107
108	108	class ql_state : public driver_device
r29404	r29405
206	206	void trump_card_set_control(UINT8 data);
207	207	void sandy_set_control(UINT8 data);
208	208	void sandy_print_char(UINT8 data);
209
	209
210	210	UINT8 m_disk_type;
211	211	int m_disk_io_base;
212	212	UINT8 m_disk_io_byte;
r29404	r29405
214	214	DECLARE_READ_LINE_MEMBER(disk_io_dden_r);
215	215	DECLARE_WRITE_LINE_MEMBER(disk_io_intrq_w);
216	216	DECLARE_WRITE_LINE_MEMBER(disk_io_drq_w);
217
	217
218	218	DECLARE_WRITE_LINE_MEMBER( sandy_printer_busy );
219	219
220	220	// QIMI or Sandy mouse
221	221	void mouse_tick();
222
	222
223	223	DECLARE_READ8_MEMBER( qimi_io_r );
224	224	DECLARE_WRITE8_MEMBER( qimi_io_w );
225
226		UINT8 m_mouse_int;
227
	225
	226	UINT8 m_mouse_int;
	227
228	228	emu_timer *m_mouse_timer;
229
	229
230	230	UINT8 m_ql_mouse_x;
231	231	UINT8 m_ql_mouse_y;
232	232
233	233	protected:
234		virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	234	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
235	235
236	236	};
237	237

trunk/src/mess/includes/apple2gs.h
r29404	r29405
99	99	#endif
100	100	m_adb_mousex(*this, "adb_mouse_x"),
101	101	m_adb_mousey(*this, "adb_mouse_y"),
102		m_palette(*this, "palette")
	102	m_palette(*this, "palette")
103	103	{ }
104	104
105	105	required_device<cpu_device> m_maincpu;

trunk/src/mess/includes/tiki100.h
r29404	r29405
67	67	m_y10(*this, "Y10"),
68	68	m_y11(*this, "Y11"),
69	69	m_y12(*this, "Y12"),
70		m_palette(*this, "palette")
	70	m_palette(*this, "palette")
71	71	{ }
72	72
73	73	required_device<cpu_device> m_maincpu;

trunk/src/mess/includes/bbc.h
r29404	r29405
152	152	DECLARE_WRITE_LINE_MEMBER(write_dcd_serial);
153	153	DECLARE_WRITE_LINE_MEMBER(write_cts_serial);
154	154	DECLARE_INPUT_CHANGED_MEMBER( trigger_reset );
155
	155
156	156	DECLARE_WRITE_LINE_MEMBER(bbc_i8271_interrupt);
157	157
158	158	int exp_rom_load(device_image_interface &image, int index);

trunk/src/mess/includes/fm7.h
r29404	r29405
141	141	m_joy1(*this, "joy1"),
142	142	m_joy2(*this, "joy2"),
143	143	m_dsw(*this, "DSW"),
144		m_palette(*this, "palette")
	144	m_palette(*this, "palette")
145	145	{
146	146	}
147	147

trunk/src/mess/includes/genpc.h
r29404	r29405
103	103	DECLARE_WRITE_LINE_MEMBER( pc_dack3_w );
104	104
105	105	DECLARE_WRITE_LINE_MEMBER( pc_speaker_set_spkrdata );
106
	106
107	107	DECLARE_READ8_MEMBER(pc_page_r);
108	108	DECLARE_WRITE8_MEMBER(pc_page_w);
109	109	DECLARE_WRITE8_MEMBER(nmi_enable_w);
r29404	r29405
175	175	public:
176	176	virtual DECLARE_READ8_MEMBER ( pc_ppi_portc_r );
177	177	virtual DECLARE_WRITE8_MEMBER( pc_ppi_portb_w );
178
	178
179	179	virtual DECLARE_WRITE_LINE_MEMBER( keyboard_clock_w );
180	180	};
181	181

trunk/src/mess/includes/advision.h
r29404	r29405
21	21	m_maincpu(*this, I8048_TAG),
22	22	m_soundcpu(*this, COP411_TAG),
23	23	m_dac(*this, "dac"),
24		m_palette(*this, "palette")
	24	m_palette(*this, "palette")
25	25	{ }
26	26
27	27	required_device<cpu_device> m_maincpu;

trunk/src/mess/includes/softbox.h
r29404	r29405
21	21	#define I8255_1_TAG "ic16"
22	22	#define COM8116_TAG "ic14"
23	23	#define RS232_TAG "rs232"
24		#define CORVUS_HDC_TAG "corvus"
	24	#define CORVUS_HDC_TAG "corvus"
25	25
26	26	class softbox_state : public driver_device
27	27	{

trunk/src/mess/includes/lisa.h
r29404	r29405
120	120	m_io_line7(*this, "LINE7"),
121	121	m_io_mouse_x(*this, "MOUSE_X"),
122	122	m_io_mouse_y(*this, "MOUSE_Y"),
123		m_palette(*this, "palette")
	123	m_palette(*this, "palette")
124	124	{ }
125	125
126	126	required_device<m68000_base_device> m_maincpu;
r29404	r29405
144	144	required_ioport m_io_line7;
145	145	required_ioport m_io_mouse_x;
146	146	required_ioport m_io_mouse_y;
147
	147
148	148	required_device<palette_device> m_palette;
149	149
150	150	UINT8 *m_ram_ptr;

trunk/src/mess/includes/aquarius.h
r29404	r29405
57	57	required_ioport m_y7;
58	58	required_device<gfxdecode_device> m_gfxdecode;
59	59	required_device<screen_device> m_screen;
60		required_device<palette_device> m_palette;
	60	required_device<palette_device> m_palette;
61	61
62	62	UINT8 m_scrambler;
63	63	tilemap_t *m_tilemap;

trunk/src/mess/includes/svi318.h
r29404	r29405
142	142	required_ioport m_line10;
143	143	required_ioport m_joysticks;
144	144	required_ioport m_buttons;
145		public:
	145	public:
146	146	optional_device<palette_device> m_palette;
147	147	protected:
148	148	void svi318_set_banks();

trunk/src/mess/includes/a7800.h
r29404	r29405
114	114	required_ioport m_io_console_buttons;
115	115	memory_bank *m_bank10;
116	116	memory_bank *m_bank11;
117		required_device<screen_device> m_screen;
	117	required_device<screen_device> m_screen;
118	118
119	119	void maria_draw_scanline();
120	120	int is_holey(unsigned int addr);

trunk/src/mess/includes/x68k.h
r29404	r29405
248	248	DECLARE_WRITE_LINE_MEMBER(mfp_irq_callback);
249	249	DECLARE_WRITE_LINE_MEMBER(x68k_scsi_irq);
250	250	DECLARE_WRITE_LINE_MEMBER(x68k_scsi_drq);
251
	251
252	252	//dmac
253	253	void dma_irq(int channel);
254	254	DECLARE_WRITE8_MEMBER(dma_end);

trunk/src/mess/includes/vc4000.h
r29404	r29405
136	136	#else
137	137	required_ioport m_joys;
138	138	required_ioport m_config;
139		#endif
	139	#endif
140	140	inline UINT8 vc4000_joystick_return_to_centre(UINT8 joy);
141	141	void vc4000_draw_digit(bitmap_ind16 &bitmap, int x, int y, int d, int line);
142	142	inline void vc4000_collision_plot(UINT8 *collision, UINT8 data, UINT8 color, int scale);

trunk/src/mess/includes/mikromik.h
r29404	r29405
30	30	#define RS232_A_TAG "rs232a"
31	31	#define RS232_B_TAG "rs232b"
32	32	#define RS232_C_TAG "rs232c"
33		#define KB_TAG "kb"
	33	#define KB_TAG "kb"
34	34
35	35	class mm1_state : public driver_device
36	36	{

trunk/src/mess/includes/pocketc.h
r29404	r29405
16	16	: driver_device(mconfig, type, tag) { }
17	17
18	18	DECLARE_PALETTE_INIT(pocketc);
19
	19
20	20	static const unsigned short pocketc_colortable[8][2];
21	21	void pocketc_draw_special(bitmap_ind16 &bitmap,int x, int y, const POCKETC_FIGURE fig, int color);
22	22	};

trunk/src/mess/includes/z88.h
r29404	r29405
49	49	: driver_device(mconfig, type, tag),
50	50	m_maincpu(*this, "maincpu"),
51	51	m_ram(*this, RAM_TAG),
52		m_palette(*this, "palette")
	52	m_palette(*this, "palette")
53	53	{ }
54	54
55	55	required_device<cpu_device> m_maincpu;

trunk/src/mess/includes/zx.h
r29404	r29405
102	102	required_ioport m_io_row7;
103	103	optional_ioport m_io_config;
104	104	required_device<screen_device> m_screen;
105
	105
106	106	void zx_ula_r(int offs, memory_region *region, const UINT8 param);
107	107	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
108	108	};

trunk/src/mess/includes/avigo.h
r29404	r29405
36	36	m_speaker(*this, "speaker"),
37	37	m_uart(*this, "ns16550"),
38	38	m_serport(*this, "serport"),
39		m_palette(*this, "palette")
	39	m_palette(*this, "palette")
40	40	{ }
41	41
42	42	required_device<cpu_device> m_maincpu;

trunk/src/mess/includes/vector06.h
r29404	r29405
31	31	m_ppi(*this, "ppi8255"),
32	32	m_ppi2(*this, "ppi8255_2"),
33	33	m_ram(*this, RAM_TAG),
34		m_palette(*this, "palette")
	34	m_palette(*this, "palette")
35	35	{ }
36	36
37	37	required_device<cpu_device> m_maincpu;

trunk/src/mess/includes/b2m.h
r29404	r29405
45	45	required_device<pit8253_device> m_pit;
46	46	required_device<ram_device> m_ram;
47	47	required_device<palette_device> m_palette;
48
	48
49	49	/* devices */
50	50	fd1793_t *m_fdc;
51	51	pic8259_device *m_pic;

trunk/src/mess/includes/apple3.h
r29404	r29405
30	30	#define VAR_EXTPOWER 0x0040
31	31	#define VAR_EXTSIDE 0x0080
32	32
33		#define SPEAKER_TAG "a3spkr"
34		#define DAC_TAG "a3dac"
	33	#define SPEAKER_TAG "a3spkr"
	34	#define DAC_TAG "a3dac"
35	35
36	36	class apple3_state : public driver_device
37	37	{
r29404	r29405
50	50	m_speaker(*this, SPEAKER_TAG),
51	51	m_dac(*this, DAC_TAG),
52	52	m_kbspecial(*this, "keyb_special"),
53		m_palette(*this, "palette")
	53	m_palette(*this, "palette")
54	54	{
55	55	}
56	56

trunk/src/mess/includes/thomson.h
r29404	r29405
306	306	WRITE_LINE_MEMBER( fdc_index_3_w );
307	307	void thomson_index_callback(legacy_floppy_image_device *device, int state);
308	308	DECLARE_PALETTE_INIT(thom);
309
	309
310	310	optional_device<mc6854_device> m_mc6854;
311	311
312	312	DECLARE_WRITE_LINE_MEMBER(write_centronics_perror);

trunk/src/mess/includes/super80.h
r29404	r29405
42	42	m_io_x6(*this, "X6"),
43	43	m_io_x7(*this, "X7"),
44	44	m_io_config(*this, "CONFIG"),
45		m_palette(*this, "palette")
	45	m_palette(*this, "palette")
46	46	{ }
47	47
48	48	DECLARE_READ8_MEMBER( super80v_low_r );

trunk/src/mess/includes/atarist.h
r29404	r29405
118	118	m_ikbd_mouse_pc(0),
119	119	m_ikbd_joy(1),
120	120	m_monochrome(1),
121		m_palette(*this, "palette")
	121	m_palette(*this, "palette")
122	122	{ }
123	123
124	124	required_device<cpu_device> m_maincpu;

trunk/src/mess/includes/mc1502.h
r29404	r29405
36	36	m_ram(*this, RAM_TAG) { }
37	37
38	38	required_device<cpu_device> m_maincpu;
39		required_device<i8251_device> m_upd8251;
	39	required_device<i8251_device> m_upd8251;
40	40	required_device<pic8259_device> m_pic8259;
41	41	required_device<pit8253_device> m_pit8253;
42	42	required_device<i8255_device> m_ppi8255n1;
r29404	r29405
86	86	int fdc_motor_on;
87	87	emu_timer *fdc_motor_timer;
88	88	} m_motor;
89		const char *m_cputag;
	89	const char *m_cputag;
90	90	*/
91	91	};
92	92

trunk/src/mess/includes/apricotf.h
r29404	r29405
55	55	m_sio_int(CLEAR_LINE),
56	56	m_p_scrollram(*this, "p_scrollram"),
57	57	m_p_paletteram(*this, "p_paletteram"),
58		m_palette(*this, "palette")
	58	m_palette(*this, "palette")
59	59	{ }
60	60
61	61	virtual void machine_start();

trunk/src/mess/includes/einstein.h
r29404	r29405
151	151	required_ioport m_buttons;
152	152	required_ioport m_config;
153	153	optional_ioport m_80column_dips;
154		public:
	154	public:
155	155	optional_device<palette_device> m_palette;
156	156
157	157	void einstein_scan_keyboard();

trunk/src/mess/includes/intv.h
r29404	r29405
142	142	required_ioport m_io_options;
143	143	optional_ioport m_io_ecs_cntrlsel;
144	144	optional_ioport m_io_test;
145
	145
146	146	optional_device<gfxdecode_device> m_gfxdecode;
147	147	required_device<palette_device> m_palette;
148	148

trunk/src/mess/includes/studio2.h
r29404	r29405
45	45	required_ioport m_a;
46	46	required_ioport m_b;
47	47	required_device<screen_device> m_screen;
48
	48
49	49	virtual void machine_start();
50	50	virtual void machine_reset();
51	51

trunk/src/mess/includes/pcw.h
r29404	r29405
124	124	required_device<beep_device> m_beeper;
125	125	required_device<screen_device> m_screen;
126	126	required_device<palette_device> m_palette;
127
	127
128	128	inline void pcw_plot_pixel(bitmap_ind16 &bitmap, int x, int y, UINT32 color);
129	129	void pcw_update_interrupt_counter();
130	130	void pcw_update_irqs();

trunk/src/mess/includes/rmnimbus.h
r29404	r29405
398	398	m_eeprom(*this, ER59256_TAG),
399	399	m_via(*this, VIA_TAG),
400	400	m_centronics(*this, CENTRONICS_TAG),
401		m_palette(*this, "palette")
	401	m_palette(*this, "palette")
402	402	{
403	403	}
404	404

trunk/src/mess/includes/partner.h
r29404	r29405
31	31	DECLARE_MACHINE_RESET(partner);
32	32	DECLARE_WRITE_LINE_MEMBER(partner_wd17xx_drq_w);
33	33	DECLARE_WRITE_LINE_MEMBER(hrq_w);
34
	34
35	35	//to remove trampoline once it use new wd17xx core
36	36	DECLARE_READ8_MEMBER(partner_fdc_r);
37	37	DECLARE_WRITE8_MEMBER(partner_fdc_w);
38
	38
39	39	void partner_window_1(UINT8 bank_num, UINT16 offset,UINT8 *rom);
40	40	void partner_window_2(UINT8 bank_num, UINT16 offset,UINT8 *rom);
41	41	void partner_iomap_bank(UINT8 *rom);

trunk/src/mess/video/nascom1.c
r29404	r29405
16	16
17	17	for (sx = 0; sx < 48; sx++)
18	18	{
19
20	19	m_gfxdecode->gfx(0)->opaque(bitmap,cliprect, videoram[0x03ca + sx],
21	20	1, 0, 0, sx * 8, 0);
22	21	}
r29404	r29405
25	24	{
26	25	for (sx = 0; sx < 48; sx++)
27	26	{
28
29	27	m_gfxdecode->gfx(0)->opaque(bitmap,cliprect, videoram[0x000a + (sy * 64) + sx],
30	28	1, 0, 0, sx * 8, (sy + 1) * 16);
31	29	}
r29404	r29405
40	38
41	39	for (sx = 0; sx < 48; sx++)
42	40	{
43
44	41	m_gfxdecode->gfx(0)->opaque(bitmap,cliprect, videoram[0x03ca + sx],
45	42	1, 0, 0, sx * 8, 0);
46	43	}
r29404	r29405
49	46	{
50	47	for (sx = 0; sx < 48; sx++)
51	48	{
52
53	49	m_gfxdecode->gfx(0)->opaque(bitmap,cliprect, videoram[0x000a + (sy * 64) + sx],
54	50	1, 0, 0, sx * 8, (sy + 1) * 14);
55	51	}

trunk/src/mess/video/gime.h
r29404	r29405
21	21	// GIME CONFIG/INTERFACE
22	22	//**************************************************************************
23	23
24		#define MCFG_GIME_HSYNC_CALLBACK MCFG_MC6847_HSYNC_CALLBACK
	24	#define MCFG_GIME_HSYNC_CALLBACK MCFG_MC6847_HSYNC_CALLBACK
25	25
26		#define MCFG_GIME_FSYNC_CALLBACK MCFG_MC6847_FSYNC_CALLBACK
	26	#define MCFG_GIME_FSYNC_CALLBACK MCFG_MC6847_FSYNC_CALLBACK
27	27
28	28	#define MCFG_GIME_IRQ_CALLBACK(_write) \
29	29	devcb = &gime_base_device::set_irq_wr_callback(*device, DEVCB2_##_write);

trunk/src/mess/video/zx8301.h
r29404	r29405
103	103	required_device<cpu_device> m_cpu;
104	104
105	105	devcb2_write_line m_write_vsync;
106
	106
107	107	//address_space *m_data;
108	108
109	109	int m_dispoff; // display off

trunk/src/mess/video/abc80.c
r29404	r29405
203	203	MCFG_SCREEN_UPDATE_DRIVER(abc80_state, screen_update)
204	204
205	205	MCFG_SCREEN_RAW_PARAMS(XTAL_11_9808MHz/2, ABC80_HTOTAL, ABC80_HBEND, ABC80_HBSTART, ABC80_VTOTAL, ABC80_VBEND, ABC80_VBSTART)
206
	206
207	207	MCFG_GFXDECODE_ADD("gfxdecode", "palette", abc80)
208	208	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
209	209	MACHINE_CONFIG_END

trunk/src/mess/video/gb_lcd.c
r29404	r29405
1166	1166	{
1167	1167	data = ((UINT16 ) &m_vram[((oam[3] & 0x8)<<10) + (oam[2] & tilemask) * 16 + (line - oam[0]) * 2]);
1168	1168	}
1169
	1169
1170	1170	data = LITTLE_ENDIANIZE_INT16(data);
1171	1171
1172	1172	switch (oam[3] & 0xA0)

trunk/src/mess/video/v1050.c
r29404	r29405
132	132	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
133	133	MCFG_SCREEN_SIZE(640, 400)
134	134	MCFG_SCREEN_VISIBLE_AREA(0,640-1, 0, 400-1)
135
	135
136	136	MCFG_PALETTE_ADD_MONOCHROME_GREEN_HIGHLIGHT("palette")
137	137	MACHINE_CONFIG_END

trunk/src/mess/video/a7800.c
r29404	r29405
4	4
5	5	Routines to control the Atari 7800 video hardware
6	6
7		2014-03-24 Mike Saarna Fixed DMA regarding startup, shutdown and
	7	2014-03-24 Mike Saarna Fixed DMA regarding startup, shutdown and
8	8	cycle stealing.
9	9
10	10	2013-05-08 huygens rewrite to emulate line ram buffers (mostly fixes Kung-Fu Master
r29404	r29405
126	126	int x, d, c, i, pixel_cell, cells;
127	127	int maria_cycles;
128	128
129		if ( m_maria_offset == 0 )
130		maria_cycles = 5+21; // DMA startup + last line shutdown
131		else
132		maria_cycles = 5+16; // DMA startup + other line shutdown
133
	129	if ( m_maria_offset == 0 )
	130	maria_cycles = 5+21; // DMA startup + last line shutdown
	131	else
	132	maria_cycles = 5+16; // DMA startup + other line shutdown
	133
134	134	cells = 0;
135	135
136	136	/* Process this DLL entry */
r29404	r29405
202	202	}
203	203	}
204	204	}
205		// spin the CPU for Maria DMA, if it's not already spinning for WSYNC
206		if ( ! m_maria_wsync )
207		m_maincpu->spin_until_time(m_maincpu->cycles_to_attotime(maria_cycles/4)); // Maria clock rate is 4 times that of the CPU
	205	// spin the CPU for Maria DMA, if it's not already spinning for WSYNC
	206	if ( ! m_maria_wsync )
	207	m_maincpu->spin_until_time(m_maincpu->cycles_to_attotime(maria_cycles/4)); // Maria clock rate is 4 times that of the CPU
208	208
209	209	// draw line buffer to screen
210	210	m_active_buffer = !m_active_buffer; // switch buffers

trunk/src/mess/video/pc1251.c
r29404	r29405
4	4	#include "includes/pc1251.h"
5	5
6	6	static const POCKETC_FIGURE /*busy={
7		"11 1 1 11 1 1",
8		"1 1 1 1 1 1 1",
9		"11 1 1 1 1 1",
10		"1 1 1 1 1 1",
11		"11 1 11 1e"
	7	"11 1 1 11 1 1",
	8	"1 1 1 1 1 1 1",
	9	"11 1 1 1 1 1",
	10	"1 1 1 1 1 1",
	11	"11 1 11 1e"
12	12	},*/ def={
13	13	"11 111 111",
14	14	"1 1 1 1",
r29404	r29405
22	22	" 1 1 1 1 1 1",
23	23	"11 1 1 1 1 1e"
24	24	}, /*hyp={
25		"1 1 1 1 11",
26		"1 1 1 1 1 1",
27		"111 1 1 11",
28		"1 1 1 1",
29		"1 1 1 1e"
	25	"1 1 1 1 11",
	26	"1 1 1 1 1 1",
	27	"111 1 1 11",
	28	"1 1 1 1",
	29	"1 1 1 1e"
30	30	},*/ de={
31	31	"11 111",
32	32	"1 1 1",
r29404	r29405
46	46	"1 1 1 1 1 1",
47	47	"1 1 1 1 11e"
48	48	}, /*braces={
49		" 1 1",
50		"1 1",
51		"1 1",
52		"1 1",
53		" 1 1e"
	49	" 1 1",
	50	"1 1",
	51	"1 1",
	52	"1 1",
	53	" 1 1e"
54	54	}, m={
55		"1 1",
56		"11 11",
57		"1 1 1",
58		"1 1",
59		"1 1e"
	55	"1 1",
	56	"11 11",
	57	"1 1 1",
	58	"1 1",
	59	"1 1e"
60	60	}, e={
61		"111",
62		"1",
63		"111",
64		"1",
65		"111e"
	61	"111",
	62	"1",
	63	"111",
	64	"1",
	65	"111e"
66	66	},*/ run={
67	67	"11 1 1 1 1",
68	68	"1 1 1 1 11 1",
r29404	r29405
76	76	"1 1 1 1 1",
77	77	"1 1 1 1e"
78	78	}, /*japan={
79		" 1 1 11 1 1 1",
80		" 1 1 1 1 1 1 1 11 1",
81		" 1 111 11 111 1 11",
82		"1 1 1 1 1 1 1 1 1",
83		" 1 1 1 1 1 1 1 1e"
	79	" 1 1 11 1 1 1",
	80	" 1 1 1 1 1 1 1 11 1",
	81	" 1 111 11 111 1 11",
	82	"1 1 1 1 1 1 1 1 1",
	83	" 1 1 1 1 1 1 1 1e"
84	84	}, sml={
85		" 11 1 1 1",
86		"1 111 1",
87		" 1 1 1 1",
88		" 1 1 1 1",
89		"11 1 1 111e"
	85	" 11 1 1 1",
	86	"1 111 1",
	87	" 1 1 1 1",
	88	" 1 1 1 1",
	89	"11 1 1 111e"
90	90	},*/ rsv={
91	91	"11 11 1 1",
92	92	"1 1 1 1 1",

trunk/src/mess/video/mikromik.c
r29404	r29405
121	121
122	122	MCFG_DEVICE_ADD(UPD7220_TAG, UPD7220, XTAL_18_720MHz/8)
123	123	MCFG_DEVICE_ADDRESS_MAP(AS_0, mm1_upd7220_map)
124		MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(mm1_state, hgdc_display_pixels)
	124	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(mm1_state, hgdc_display_pixels)
125	125	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
126	126	MACHINE_CONFIG_END

trunk/src/mess/video/pc1401.c
r29404	r29405
93	93	"1",
94	94	"111e"
95	95	}/*, run={
96		"11 1 1 1 1",
97		"1 1 1 1 11 1",
98		"11 1 1 1 11",
99		"1 1 1 1 1 1",
100		"1 1 1 1 1e"
	96	"11 1 1 1 1",
	97	"1 1 1 1 11 1",
	98	"11 1 1 1 11",
	99	"1 1 1 1 1 1",
	100	"1 1 1 1 1e"
101	101	}, pro={
102		"11 11 1 ",
103		"1 1 1 1 1 1",
104		"11 11 1 1",
105		"1 1 1 1 1",
106		"1 1 1 1e"
	102	"11 11 1 ",
	103	"1 1 1 1 1 1",
	104	"11 11 1 1",
	105	"1 1 1 1 1",
	106	"1 1 1 1e"
107	107	}, japan={
108		" 1 1 11 1 1 1",
109		" 1 1 1 1 1 1 1 11 1",
110		" 1 111 11 111 1 11",
111		"1 1 1 1 1 1 1 1 1",
112		" 1 1 1 1 1 1 1 1e"
	108	" 1 1 11 1 1 1",
	109	" 1 1 1 1 1 1 1 11 1",
	110	" 1 111 11 111 1 11",
	111	"1 1 1 1 1 1 1 1 1",
	112	" 1 1 1 1 1 1 1 1e"
113	113	}, sml={
114		" 11 1 1 1",
115		"1 111 1",
116		" 1 1 1 1",
117		" 1 1 1 1",
118		"11 1 1 111e"
	114	" 11 1 1 1",
	115	"1 111 1",
	116	" 1 1 1 1",
	117	" 1 1 1 1",
	118	"11 1 1 111e"
119	119	}, rsv={
120		"11 11 1 1",
121		"1 1 1 1 1",
122		"11 1 1 1",
123		"1 1 1 1 1",
124		"1 1 11 1e"
	120	"11 11 1 1",
	121	"1 1 1 1 1",
	122	"11 1 1 1",
	123	"1 1 1 1 1",
	124	"1 1 11 1e"
125	125	}*/;
126	126
127	127	#define DOWN 57

trunk/src/mess/video/apple3.c
r29404	r29405
19	19	#define DKGRAY 5
20	20	#define BLUE 6
21	21	#define LTBLUE 7
22		#define BROWN 8
	22	#define BROWN 8
23	23	#define ORANGE 9
24	24	#define GRAY 10
25	25	#define PINK 11
r29404	r29405
411	411
412	412	UINT32 apple3_state::screen_update_apple3(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
413	413	{
414		// printf("gfx mode %x\n", m_flags & (VAR_VM3\|VAR_VM1\|VAR_VM0));
	414	// printf("gfx mode %x\n", m_flags & (VAR_VM3\|VAR_VM1\|VAR_VM0));
415	415
416	416	switch(m_flags & (VAR_VM3\|VAR_VM1\|VAR_VM0))
417	417	{

trunk/src/mess/video/pc1350.c
r29404	r29405
4	4	#include "includes/pc1350.h"
5	5
6	6	static const POCKETC_FIGURE /*busy={
7		"11 1 1 11 1 1",
8		"1 1 1 1 1 1 1",
9		"11 1 1 1 1 1",
10		"1 1 1 1 1 1",
11		"11 1 11 1e"
	7	"11 1 1 11 1 1",
	8	"1 1 1 1 1 1 1",
	9	"11 1 1 1 1 1",
	10	"1 1 1 1 1 1",
	11	"11 1 11 1e"
12	12	},*/ def={
13	13	"11 111 111",
14	14	"1 1 1 1",
r29404	r29405
22	22	" 1 1 1 1 1 1",
23	23	"11 1 1 1 1 1e"
24	24	}, /*hyp={
25		"1 1 1 1 11",
26		"1 1 1 1 1 1",
27		"111 1 1 11",
28		"1 1 1 1",
29		"1 1 1 1e"
	25	"1 1 1 1 11",
	26	"1 1 1 1 1 1",
	27	"111 1 1 11",
	28	"1 1 1 1",
	29	"1 1 1 1e"
30	30	}, de={
31		"11 111",
32		"1 1 1",
33		"1 1 111",
34		"1 1 1",
35		"11 111e"
	31	"11 111",
	32	"1 1 1",
	33	"1 1 111",
	34	"1 1 1",
	35	"11 111e"
36	36	}, g={
37		" 11",
38		"1",
39		"1 1",
40		"1 1",
41		" 11e"
	37	" 11",
	38	"1",
	39	"1 1",
	40	"1 1",
	41	" 11e"
42	42	}, rad={
43		"11 1 11",
44		"1 1 1 1 1 1",
45		"11 111 1 1",
46		"1 1 1 1 1 1",
47		"1 1 1 1 11e"
	43	"11 1 11",
	44	"1 1 1 1 1 1",
	45	"11 111 1 1",
	46	"1 1 1 1 1 1",
	47	"1 1 1 1 11e"
48	48	}, braces={
49		" 1 1",
50		"1 1",
51		"1 1",
52		"1 1",
53		" 1 1e"
	49	" 1 1",
	50	"1 1",
	51	"1 1",
	52	"1 1",
	53	" 1 1e"
54	54	}, m={
55		"1 1",
56		"11 11",
57		"1 1 1",
58		"1 1",
59		"1 1e"
	55	"1 1",
	56	"11 11",
	57	"1 1 1",
	58	"1 1",
	59	"1 1e"
60	60	}, e={
61		"111",
62		"1",
63		"111",
64		"1",
65		"111e"
	61	"111",
	62	"1",
	63	"111",
	64	"1",
	65	"111e"
66	66	},*/ run={
67	67	"11 1 1 1 1",
68	68	"1 1 1 1 11 1",
r29404	r29405
88	88	" 1 1 1 1",
89	89	"11 1 1 111e"
90	90	}/*, rsv={
91		"11 11 1 1",
92		"1 1 1 1 1",
93		"11 1 1 1",
94		"1 1 1 1 1",
95		"1 1 11 1e"
	91	"11 11 1 1",
	92	"1 1 1 1 1",
	93	"11 1 1 1",
	94	"1 1 1 1 1",
	95	"1 1 11 1e"
96	96	}*/;
97	97
98	98	READ8_MEMBER(pc1350_state::pc1350_lcd_read)

trunk/src/mess/video/intv.c
r29404	r29405
82	82	for(x=0;x<40;x++)
83	83	{
84	84	offs = current_row*64+x;
85
	85
86	86	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect,
87	87	videoram[offs],
88	88	7, /* white */
r29404	r29405
93	93	{
94	94	/* draw the cursor as a solid white block */
95	95	/* (should use a filled rect here!) */
96
	96
97	97	m_gfxdecode->gfx(0)->transpen(bitmap,cliprect,
98	98	191, /* a block */
99	99	7, /* white */

trunk/src/mess/video/osi.c
r29404	r29405
158	158	MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
159	159	MCFG_SCREEN_REFRESH_RATE(50)
160	160	MCFG_SCREEN_UPDATE_DRIVER(uk101_state, screen_update)
161		MCFG_SCREEN_SIZE(648, 1616)
	161	MCFG_SCREEN_SIZE(648, 1616)
162	162	MCFG_SCREEN_VISIBLE_AREA(0, 648-1, 0, 1616-1)
163	163	MCFG_SCREEN_PALETTE("palette")
164	164

trunk/src/mess/video/tmc600.c
r29404	r29405
127	127	// video hardware
128	128	MCFG_CDP1869_SCREEN_PAL_ADD(CDP1869_TAG, SCREEN_TAG, CDP1869_DOT_CLK_PAL)
129	129	MCFG_TIMER_DRIVER_ADD_PERIODIC("blink", tmc600_state, blink_tick, attotime::from_hz(2))
130
	130
131	131	MCFG_GFXDECODE_ADD("gfxdecode", CDP1869_TAG":palette", tmc600)
132	132
133	133	// sound hardware
r29404	r29405
135	135	MCFG_CDP1869_ADD(CDP1869_TAG, CDP1869_DOT_CLK_PAL, cdp1869_page_ram)
136	136	MCFG_CDP1869_COLOR_CLOCK(CDP1869_COLOR_CLK_PAL)
137	137	MCFG_CDP1869_CHAR_PCB_READ_OWNER(tmc600_state, tmc600_pcb_r)
138		MCFG_CDP1869_CHAR_RAM_READ_OWNER(tmc600_state, tmc600_char_ram_r)
	138	MCFG_CDP1869_CHAR_RAM_READ_OWNER(tmc600_state, tmc600_char_ram_r)
139	139	MCFG_CDP1869_PAL_NTSC_CALLBACK(VCC)
140	140	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
141	141	MACHINE_CONFIG_END

trunk/src/mess/video/abc800.c
r29404	r29405
71	71	void abc800c_state::hr_update(bitmap_rgb32 &bitmap, const rectangle &cliprect)
72	72	{
73	73	const pen_t *pen = m_palette->pens();
74
	74
75	75	UINT16 addr = 0;
76	76
77	77	for (int y = m_hrs; y < MIN(cliprect.max_y + 1, m_hrs + 480); y += 2)
r29404	r29405
201	201	void abc800m_state::hr_update(bitmap_rgb32 &bitmap, const rectangle &cliprect)
202	202	{
203	203	UINT16 addr = 0;
204
	204
205	205	const pen_t *pen = m_palette->pens();
206	206
207	207	for (int y = m_hrs + VERTICAL_PORCH_HACK; y < MIN(cliprect.max_y + 1, m_hrs + VERTICAL_PORCH_HACK + 240); y++)

trunk/src/mess/video/vtvideo.c
r29404	r29405
10	10	----------------------------------
11	11	- TESTS REQUIRED : do line and character attributes (plus combinations) match real hardware?
12	12
13		- JUMPY SOFT SCROLL : Soft scroll should be synced with beam or DMA (line linking/unlinking is done during VBI, in less than 550ms).
	13	- JUMPY SOFT SCROLL : Soft scroll should be synced with beam or DMA (line linking/unlinking is done during VBI, in less than 550ms).
14	14	See 4.7.4 and up in VT manual.
15	15
16	16	- UNDOCUMENTED FEATURES of DC011 / DC012 (CLUES WANTED)
r29404	r29405
253	253	// set higher part scroll
254	254	m_scroll_latch = (m_scroll_latch & 0x03) \| ((data & 0x03) << 2);
255	255
256		m_scroll_latch_valid = 1; // MSB is written last.
	256	m_scroll_latch_valid = 1; // MSB is written last.
257	257	}
258	258	}
259	259	else
r29404	r29405
570	570	// Offset to bitmap in char-rom (used later below)
571	571	int i = scan_line;
572	572
573		// Affects 'i' / 'y_preset' / 'scan_line' (= LOOP VARIABLE)
574		if ( m_scroll_latch_valid == 1)
575		{
576		// **** START IF SCROLL REGION:
577		if ( (old_scroll_region == 0) && (scroll_region == 1) )
578		{
	573	// Affects 'i' / 'y_preset' / 'scan_line' (= LOOP VARIABLE)
	574	if ( m_scroll_latch_valid == 1)
	575	{
	576	// **** START IF SCROLL REGION:
	577	if ( (old_scroll_region == 0) && (scroll_region == 1) )
	578	{
579	579	if (scan_line == 0) // * EXECUTED ONCE *
580		{
581		scan_line = m_scroll_latch; // write less lines ! SIDE EFFECT ON LOOP !
	580	{
	581	scan_line = m_scroll_latch; // write less lines ! SIDE EFFECT ON LOOP !
582	582	i = m_scroll_latch; // set hard offset to char-rom
583	583	}
584		}
	584	}
585	585
586		// **** MIDDLE OF REGION:
587		if ( (old_scroll_region == 1) && (scroll_region == 1) )
588		{
589		if ( ( y * 10 + scan_line - m_scroll_latch ) >= 0 )
590		y_preset = y * 10 + scan_line - m_scroll_latch;
591		}
	586	// **** MIDDLE OF REGION:
	587	if ( (old_scroll_region == 1) && (scroll_region == 1) )
	588	{
	589	if ( ( y * 10 + scan_line - m_scroll_latch ) >= 0 )
	590	y_preset = y * 10 + scan_line - m_scroll_latch;
	591	}
592	592
593		// **** END OF SCROLL REGION:
594		if ( (old_scroll_region == 1) && (scroll_region == 0) )
595		{
	593	// **** END OF SCROLL REGION:
	594	if ( (old_scroll_region == 1) && (scroll_region == 0) )
	595	{
596	596	if (i > (9 - m_scroll_latch) )
597		{ old_scroll_region = m_scroll_latch_valid; // keep track
598		return; // WHAT HAPPENS WITH THE REST OF THE LINE (BLANK ?)
	597	{ old_scroll_region = m_scroll_latch_valid; // keep track
	598	return; // WHAT HAPPENS WITH THE REST OF THE LINE (BLANK ?)
599	599	}
600		}
601		} // (IF) scroll latch valid
	600	}
	601	} // (IF) scroll latch valid
602	602
603	603	switch (display_type)
604	604	{

trunk/src/mess/video/vtvideo.h
r29404	r29405
115	115	MCFG_DEVICE_ADD(_tag, RAINBOW_VIDEO, 0) \
116	116	MCFG_DEVICE_CONFIG(_intrf) \
117	117	MCFG_VIDEO_SET_SCREEN(_screen_tag)
118
119	118
120	119
	120
121	121	#endif

trunk/src/mess/video/apollo.c
r29404	r29405
1725	1725	m_lut_fifo(NULL),
1726	1726	m_bt458(NULL)
1727	1727	{
1728
1729	1728	}
1730	1729
1731	1730	apollo_graphics_15i::apollo_graphics_15i(const machine_config &mconfig,const char tag, device_t owner, UINT32 clock, device_type type,const char name, const char shortname, const char *source) :
r29404	r29405
1884	1883	memset(m_image_memory, 0, m_image_memory_size * 2);
1885	1884
1886	1885	// register_vblank_callback(this);
1887
	1886
1888	1887	/* FIXME: register for VBLANK callbacks */
1889	1888	register_vblank_callback();
1890	1889	}
r29404	r29405
1960	1959
1961	1960
1962	1961	READ16_MEMBER( apollo_graphics_15i::apollo_mgm_r )
1963		{
	1962	{
1964	1963	if (is_mono())
1965	1964	{
1966	1965	return apollo_mem_r(space, offset, mem_mask);

trunk/src/mess/mess.lst
r29404	r29405
1885	1885	// SWTPC S/09
1886	1886	swtpc09 // S09, DMF2 Floppy SBUG rom - FLEX
1887	1887	swtpc09i // S09, DC4 Floppy + PIA IDE SBUG rom - FLEX
1888		swtpc09u // S09, DMF2 Floppy UNIBUG rom - UniFLEX
	1888	swtpc09u // S09, DMF2 Floppy UNIBUG rom - UniFLEX
1889	1889	swtpc09d3 // S09, DMF3 Floppy UNIBUG U3 rom - UniFLEX U3
1890	1890
1891	1891
r29404	r29405
1955	1955	harriet // 1990
1956	1956
1957	1957	// Fanuc
1958		fanucspg // 1983
	1958	fanucspg // 1983
1959	1959	fanucs15 // 1990
1960	1960
1961	1961	//******** Misc ********************************************************

trunk/src/mess/layout/pve500.lay
r29404	r29405
5	5	<color red="0.75" green="0.0" blue="0.0" />
6	6	</led7seg>
7	7	</element>
8
	8
9	9	<element name="led" defstate="0">
10	10	<disk state="1">
11	11	<color red="0.75" green="0.0" blue="0.0" />
r29404	r29405
14	14	<color red="0.09375" green="0.0" blue="0.0" />
15	15	</disk>
16	16	</element>
17
	17
18	18	<element name="background">
19	19	<rect>
20		<bounds left="0" top="0" right="1" bottom="1" />
	20	<bounds left="0" top="0" right="1" bottom="1" />
21	21	<color red="0.0" green="0.0" blue="0.0" />
22		</rect>
	22	</rect>
23	23	</element>
24	24
25	25	<view name="Default Layout">
r29404	r29405
126	126	</bezel>
127	127	<bezel name="digit23" element="digit">
128	128	<bounds x="2302" y="15" width="50" height="80" />
129		</bezel>
	129	</bezel>
130	130	</view>
131	131	</mamelayout>

trunk/src/mess/layout/rainbow.lay
r29404	r29405
94	94	<text string="LOCK">
95	95	<color red="1.0" green="1.0" blue="1.0" />
96	96	</text>
97		</element>
	97	</element>
98	98	<element name="l10_comp">
99	99	<text string="COMP">
100	100	<color red="1.0" green="1.0" blue="1.0" />

trunk/src/mess/drivers/z80ne.c
r29404	r29405
513	513	MCFG_CASSETTE_ADD( "cassette", z80ne_cassettea_config )
514	514	MCFG_CASSETTE_ADD( "cassette2", z80ne_cassetteb_config )
515	515
516		MCFG_DEVICE_ADD("lx388_kr2376", KR2376, 50000)
	516	MCFG_DEVICE_ADD("lx388_kr2376", KR2376, 50000)
517	517
518	518	/* video hardware */
519	519	MCFG_SCREEN_MC6847_PAL_ADD("lx388", "mc6847")
r29404	r29405
541	541	MCFG_CASSETTE_ADD( "cassette", z80ne_cassettea_config )
542	542	MCFG_CASSETTE_ADD( "cassette2", z80ne_cassetteb_config )
543	543
544		MCFG_DEVICE_ADD("lx388_kr2376", KR2376, 50000)
	544	MCFG_DEVICE_ADD("lx388_kr2376", KR2376, 50000)
545	545
546	546	/* video hardware */
547	547	MCFG_SCREEN_MC6847_PAL_ADD("lx388", "mc6847")

trunk/src/mess/drivers/apf.c
r29404	r29405
318	318	static INPUT_PORTS_START( apfm1000 )
319	319
320	320	/*
321		This simple Basic program can be used to read the joysticks and the keyboard:
	321	This simple Basic program can be used to read the joysticks and the keyboard:
322	322
323		10 PRINT KEY$(n);
324		20 GOTO 10
	323	10 PRINT KEY$(n);
	324	20 GOTO 10
325	325
326		where n = 0, 1 or 2 - 0 = keyboard, 1,2 = joysticks #1 and #2
	326	where n = 0, 1 or 2 - 0 = keyboard, 1,2 = joysticks #1 and #2
327	327
328		When reading the keyboard KEY$(0) returns the character associated to the key, with the
329		following exceptions:
	328	When reading the keyboard KEY$(0) returns the character associated to the key, with the
	329	following exceptions:
330	330
331		Ctrl = CHR$(1)
332		Rept = CHR$(2)
333		Here Is = CHR$(4)
334		Rubout = CHR$(8)
	331	Ctrl = CHR$(1)
	332	Rept = CHR$(2)
	333	Here Is = CHR$(4)
	334	Rubout = CHR$(8)
335	335
336		When reading the joysticks, KEY$() = "N", "S", "E", "W" for the directions
337		"0" - "9" for the keypad digits
338		"?" for "Cl"
339		"!" for "En"
	336	When reading the joysticks, KEY$() = "N", "S", "E", "W" for the directions
	337	"0" - "9" for the keypad digits
	338	"?" for "Cl"
	339	"!" for "En"
340	340
341	341
342	342	? player right is player 1

trunk/src/mess/drivers/paso1600.c
r29404	r29405
352	352	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
353	353	MCFG_SCREEN_UPDATE_DRIVER(paso1600_state, screen_update_paso1600)
354	354	MCFG_SCREEN_PALETTE("palette")
355
	355
356	356	MCFG_GFXDECODE_ADD("gfxdecode", "palette", paso1600)
357	357	MCFG_PALETTE_ADD("palette", 8)
358	358	// MCFG_PALETTE_INIT(black_and_white)

trunk/src/mess/drivers/vt320.c
r29404	r29405
94	94	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
95	95	MCFG_SCREEN_UPDATE_DRIVER(vt320_state, screen_update_vt320)
96	96	MCFG_SCREEN_PALETTE("palette")
97
	97
98	98	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
99	99
100	100	/* internal ram */

trunk/src/mess/drivers/mbc200.c
r29404	r29405
271	271	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 400-1)
272	272	MCFG_SCREEN_UPDATE_DRIVER(mbc200_state, screen_update_mbc200)
273	273	MCFG_SCREEN_PALETTE("palette")
274
	274
275	275	MCFG_GFXDECODE_ADD("gfxdecode", "palette", mbc200)
276	276	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
277	277

trunk/src/mess/drivers/dct11em.c
r29404	r29405
62	62	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
63	63	MCFG_SCREEN_UPDATE_DRIVER(dct11em_state, screen_update_dct11em)
64	64	MCFG_SCREEN_PALETTE("palette")
65
	65
66	66	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
67	67	MACHINE_CONFIG_END
68	68

trunk/src/mess/drivers/ptcsol.c
r29404	r29405
758	758	MCFG_SCREEN_SIZE(576, 208)
759	759	MCFG_SCREEN_VISIBLE_AREA(0, 575, 0, 207)
760	760	MCFG_SCREEN_PALETTE("palette")
761
	761
762	762	MCFG_GFXDECODE_ADD("gfxdecode", "palette", sol20)
763	763	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
764	764

trunk/src/mess/drivers/victor9k.c
r29404	r29405
629	629
630	630	/*
631	631
632		bit description
	632	bit description
633	633
634		PA0 E0
635		PA1 E1
636		PA2 I1
637		PA3 E2
638		PA4 E4
639		PA5 E5
640		PA6 I7
641		PA7 E6
	634	PA0 E0
	635	PA1 E1
	636	PA2 I1
	637	PA3 E2
	638	PA4 E4
	639	PA5 E5
	640	PA6 I7
	641	PA7 E6
642	642
643	643	*/
644	644

trunk/src/mess/drivers/ip22.c
r29404	r29405
110	110	m_dac(*this, "dac"),
111	111	m_kbdc8042(*this, "kbdc")
112	112	{ }
113
	113
114	114	required_device<cpu_device> m_maincpu;
115	115	required_device<wd33c93_device> m_wd33c93;
116	116	required_shared_ptr<UINT32> m_unkpbus0;
r29404	r29405
1623	1623	MCFG_PALETTE_ADD("palette", 65536)
1624	1624
1625	1625	MCFG_NEWPORT_ADD("newport")
1626
	1626
1627	1627	MCFG_DEVICE_ADD("sgi_mc", SGI_MC, 0)
1628	1628
1629	1629	MCFG_DEVICE_ADD("lpt_0", PC_LPT, 0)

trunk/src/mess/drivers/socrates.c
r29404	r29405
127	127	required_device<cpu_device> m_maincpu;
128	128	required_device<socrates_snd_device> m_sound;
129	129	required_device<screen_device> m_screen;
130
	130
131	131	rgb_t m_palette_val[256];
132	132
133	133	UINT8 m_data[8];
r29404	r29405
1459	1459	MCFG_SCREEN_SIZE(256, 224)
1460	1460	MCFG_SCREEN_VISIBLE_AREA(0, 256-1, 0, 224-1)
1461	1461	MCFG_SCREEN_PALETTE("palette")
1462
	1462
1463	1463	MCFG_PALETTE_ADD("palette", 256)
1464	1464	MCFG_PALETTE_INIT_OWNER(socrates_state, socrates)
1465	1465

trunk/src/mess/drivers/amstrad.c
r29404	r29405
361	361
362	362	static INPUT_PORTS_START( amx_mouse )
363	363	PORT_START("mouse_input1")
364		PORT_BIT(0xff , 0, IPT_MOUSE_X) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) PORT_CONDITION("controller_type", 0x01, EQUALS, 0x01)
	364	PORT_BIT(0xff , 0, IPT_MOUSE_X) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) PORT_CONDITION("controller_type", 0x01, EQUALS, 0x01)
365	365
366	366	PORT_START("mouse_input2")
367		PORT_BIT(0xff , 0, IPT_MOUSE_Y) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) PORT_CONDITION("controller_type", 0x01, EQUALS, 0x01)
	367	PORT_BIT(0xff , 0, IPT_MOUSE_Y) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) PORT_CONDITION("controller_type", 0x01, EQUALS, 0x01)
368	368
369	369	PORT_START("mouse_input3")
370	370	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_BUTTON4) PORT_NAME("Left mouse button") PORT_CODE(MOUSECODE_BUTTON1) PORT_CONDITION("controller_type", 0x01, EQUALS, 0x01)
r29404	r29405
1052	1052	MCFG_SOUND_REPLACE("ay", AY8912, XTAL_16MHz / 16)
1053	1053	MCFG_SOUND_CONFIG(ay8912_interface)
1054	1054	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
1055
	1055
1056	1056	MCFG_PALETTE_MODIFY("palette")
1057	1057	MCFG_PALETTE_ENTRIES(32+64)
1058	1058	MCFG_PALETTE_INIT_OWNER(amstrad_state,aleste)

trunk/src/mess/drivers/portfoli.c
r29404	r29405
844	844	MCFG_SCREEN_SIZE(240, 64)
845	845	MCFG_SCREEN_VISIBLE_AREA(0, 240-1, 0, 64-1)
846	846	MCFG_SCREEN_PALETTE("palette")
847
	847
848	848	MCFG_DEFAULT_LAYOUT(layout_lcd)
849	849
850	850	MCFG_PALETTE_ADD("palette", 2)

trunk/src/mess/drivers/pcw16.c
r29404	r29405
1081	1081	MCFG_RAM_DEFAULT_SIZE("2M")
1082	1082	MCFG_INTEL_E28F008SA_ADD("flash0")
1083	1083	MCFG_INTEL_E28F008SA_ADD("flash1")
1084
	1084
1085	1085	MCFG_AT_KEYB_ADD("at_keyboard", 3, WRITELINE(pcw16_state, pcw16_keyboard_callback))
1086	1086
1087	1087	/* video ints */

trunk/src/mess/drivers/swtpc09.c
r29404	r29405
1	1	/**************************************************************************
2	2
3		SWTPC S/09 Mess driver
4		Robert Justice ,2009-2014
5
6		Emulates four different fixed combinations of hardware
7		1. swtpc09
8		MP-09 with SBUG rom, MP-ID, MP-S2, DMF2.
9		Will boot Flex operating system
10		2. swtpc09i
11		MP-09 with SBUG rom + HDrom, MP-ID, MP-S2, DMF2, PIAIDE.
12		Will boot Flex operating system
13		TODO: finish ide part and get this one working.
14		3. swtpc09u
15		MP-09 with UniBUG rom, MP-ID, MP-S2, DMF2.
16		Will boot UniFlex operating system
17		4. swtpc09d3
18		MP-09 with UniBUG U3 rom, MP-ID, MP-S2, DMF3.
19		Will boot UniFlex operating system
20		TODO: add Harddisk support, DMF3 has WD1000 interface
21
	3	SWTPC S/09 Mess driver
	4	Robert Justice ,2009-2014
	5
	6	Emulates four different fixed combinations of hardware
	7	1. swtpc09
	8	MP-09 with SBUG rom, MP-ID, MP-S2, DMF2.
	9	Will boot Flex operating system
	10	2. swtpc09i
	11	MP-09 with SBUG rom + HDrom, MP-ID, MP-S2, DMF2, PIAIDE.
	12	Will boot Flex operating system
	13	TODO: finish ide part and get this one working.
	14	3. swtpc09u
	15	MP-09 with UniBUG rom, MP-ID, MP-S2, DMF2.
	16	Will boot UniFlex operating system
	17	4. swtpc09d3
	18	MP-09 with UniBUG U3 rom, MP-ID, MP-S2, DMF3.
	19	Will boot UniFlex operating system
	20	TODO: add Harddisk support, DMF3 has WD1000 interface
	21
22	22	***************************************************************************/
23	23
24	24	#include "emu.h"
r29404	r29405
52	52	F024 - F024 DMF3 Drive select register
53	53	F025 - F025 DMF3 DMA Address register
54	54	F040 - F04F DMF3 6522 VIA
55
	55
56	56	***************************************************************************/
57	57
58	58	/* Address map is dynamically setup when DAT memory is written to */
59	59	/* only ROM from FF00-FFFF and DAT memory at FFF0-FFFF (write only) is guaranteed always*/
60	60
61	61	static ADDRESS_MAP_START(swtpc09_mem, AS_PROGRAM, 8, swtpc09_state)
62		AM_RANGE(0xff00, 0xffef) AM_ROM
63		AM_RANGE(0xfff0, 0xffff) AM_ROM AM_WRITE(dat_w)
	62	AM_RANGE(0xff00, 0xffef) AM_ROM
	63	AM_RANGE(0xfff0, 0xffff) AM_ROM AM_WRITE(dat_w)
64	64	ADDRESS_MAP_END
65	65
66	66
r29404	r29405
146	146	/* Machine driver */
147	147	/* MPU09, MPID, MPS2 DMF2 */
148	148	static MACHINE_CONFIG_START( swtpc09, swtpc09_state )
149		/* basic machine hardware */
150		MCFG_CPU_ADD("maincpu", M6809, 1000000)
151		MCFG_CPU_PROGRAM_MAP(swtpc09_mem)
	149	/* basic machine hardware */
	150	MCFG_CPU_ADD("maincpu", M6809, 1000000)
	151	MCFG_CPU_PROGRAM_MAP(swtpc09_mem)
152	152
153	153	/* video hardware */
154	154	MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "serial_terminal")
155	155	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_rxd))
156	156	MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
157
158		MCFG_PTM6840_ADD("ptm", swtpc09_6840_intf)
159
	157
	158	MCFG_PTM6840_ADD("ptm", swtpc09_6840_intf)
	159
160	160	MCFG_DEVICE_ADD("pia", PIA6821, 0)
161	161	MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_a_r))
162	162	MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_ca1_r))
163	163	MCFG_PIA_IRQA_HANDLER(WRITELINE(swtpc09_state, pia0_irq_a))
164	164
165		MCFG_DEVICE_ADD("acia", ACIA6850, 0)
	165	MCFG_DEVICE_ADD("acia", ACIA6850, 0)
166	166	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
167	167	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
168		MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(swtpc09_state, acia_interrupt))
	168	MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(swtpc09_state, acia_interrupt))
169	169
170	170	MCFG_DEVICE_ADD("acia_clock", CLOCK, 153600)
171	171	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(swtpc09_state, write_acia_clock))
172
173		MCFG_FD1793_ADD("fdc", swtpc09_wd17xx_interface )
174		MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(swtpc09_floppy_interface)
175	172
	173	MCFG_FD1793_ADD("fdc", swtpc09_wd17xx_interface )
	174	MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(swtpc09_floppy_interface)
176	175
	176
177	177	MACHINE_CONFIG_END
178	178
179	179	/* MPU09, MPID, MPS2 DC4 PIAIDE*/
180	180	static MACHINE_CONFIG_START( swtpc09i, swtpc09_state )
181		/* basic machine hardware */
182		MCFG_CPU_ADD("maincpu", M6809, 1000000)
183		MCFG_CPU_PROGRAM_MAP(swtpc09_mem)
	181	/* basic machine hardware */
	182	MCFG_CPU_ADD("maincpu", M6809, 1000000)
	183	MCFG_CPU_PROGRAM_MAP(swtpc09_mem)
184	184
185	185	/* video hardware */
186	186	MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "serial_terminal")
187	187	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_rxd))
188	188	MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
189	189
190		MCFG_PTM6840_ADD("ptm", swtpc09_6840_intf)
	190	MCFG_PTM6840_ADD("ptm", swtpc09_6840_intf)
191	191
192	192	MCFG_DEVICE_ADD("pia", PIA6821, 0)
193	193	MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_a_r))
194	194	MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_ca1_r))
195	195	MCFG_PIA_IRQA_HANDLER(WRITELINE(swtpc09_state, pia0_irq_a))
196	196
197		MCFG_DEVICE_ADD("acia", ACIA6850, 0)
	197	MCFG_DEVICE_ADD("acia", ACIA6850, 0)
198	198	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
199	199	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
200		MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(swtpc09_state, acia_interrupt))
	200	MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(swtpc09_state, acia_interrupt))
201	201
202	202	MCFG_DEVICE_ADD("acia_clock", CLOCK, 153600)
203	203	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(swtpc09_state, write_acia_clock))
204	204
205		MCFG_FD1793_ADD("fdc", swtpc09_wd17xx_interface )
206		MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(swtpc09_floppy_interface)
	205	MCFG_FD1793_ADD("fdc", swtpc09_wd17xx_interface )
	206	MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(swtpc09_floppy_interface)
207	207
208		MCFG_DEVICE_ADD("piaide", PIA6821, 0)
	208	MCFG_DEVICE_ADD("piaide", PIA6821, 0)
209	209
210	210	/* old start to adding ide support, needs major updating */
211	211	/* this is to support an add on card driving IDE from a PIA */
212		// MCFG_HARDDISK_ADD("harddisk")
213		// MCFG_IDE_CONTROLLER_ADD("ide", NULL)
214		// MCFG_IDE_CONTROLLER_REGIONS("harddisk", NULL)
215		// MCFG_IDE_CONTROLLER_ADD( "ide", ide_intf, "hdd", NULL, false ) /* FIXME */ bebox
	212	// MCFG_HARDDISK_ADD("harddisk")
	213	// MCFG_IDE_CONTROLLER_ADD("ide", NULL)
	214	// MCFG_IDE_CONTROLLER_REGIONS("harddisk", NULL)
	215	// MCFG_IDE_CONTROLLER_ADD( "ide", ide_intf, "hdd", NULL, false ) /* FIXME */ bebox
216	216
217	217
218	218	MACHINE_CONFIG_END
r29404	r29405
220	220
221	221	/* MPU09, MPID, MPS2 DMF3 */
222	222	static MACHINE_CONFIG_START( swtpc09d3, swtpc09_state )
223		/* basic machine hardware */
224		MCFG_CPU_ADD("maincpu", M6809, 2000000)
225		MCFG_CPU_PROGRAM_MAP(swtpc09_mem)
	223	/* basic machine hardware */
	224	MCFG_CPU_ADD("maincpu", M6809, 2000000)
	225	MCFG_CPU_PROGRAM_MAP(swtpc09_mem)
226	226
227	227	/* video hardware */
228	228	MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "serial_terminal")
229	229	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_rxd))
230	230	MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
231	231
232		MCFG_PTM6840_ADD("ptm", swtpc09_6840_intf)
233
	232	MCFG_PTM6840_ADD("ptm", swtpc09_6840_intf)
	233
234	234	MCFG_DEVICE_ADD("pia", PIA6821, 0)
235	235	MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_a_r))
236	236	MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_ca1_r))
237	237	MCFG_PIA_IRQA_HANDLER(WRITELINE(swtpc09_state, pia0_irq_a))
238
239		MCFG_DEVICE_ADD("acia", ACIA6850, 0)
	238
	239	MCFG_DEVICE_ADD("acia", ACIA6850, 0)
240	240	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
241	241	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
242		MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(swtpc09_state, acia_interrupt))
	242	MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(swtpc09_state, acia_interrupt))
243	243	MCFG_ACIA6850_IRQ_HANDLER(DEVWRITELINE("maincpu", m6809_device, irq_line))
244
	244
245	245	MCFG_DEVICE_ADD("acia_clock", CLOCK, 153600)
246	246	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(swtpc09_state, write_acia_clock))
247	247
248		MCFG_FD1793_ADD("fdc", swtpc09_wd17xx_interface )
249		MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(swtpc09_floppy_interface)
	248	MCFG_FD1793_ADD("fdc", swtpc09_wd17xx_interface )
	249	MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(swtpc09_floppy_interface)
250	250
251		MCFG_DEVICE_ADD("via", VIA6522, XTAL_4MHz / 4)
	251	MCFG_DEVICE_ADD("via", VIA6522, XTAL_4MHz / 4)
252	252	MCFG_VIA6522_READPA_HANDLER(READ8(swtpc09_state, dmf3_via_read_porta))
253	253	MCFG_VIA6522_READPB_HANDLER(READ8(swtpc09_state, dmf3_via_read_portb))
254	254	MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(swtpc09_state, dmf3_via_write_porta))
255	255	//MCFG_VIA6522_CA1_HANDLER(WRITELINE(swtpc09_state, dmf3_via_write_ca1))
256	256	MCFG_VIA6522_IRQ_HANDLER(WRITELINE(swtpc09_state, dmf3_via_irq))
257
258	257
	258
259	259	MACHINE_CONFIG_END
260	260
261	261
262	262	/* ROM definition */
263	263	ROM_START( swtpc09 )
264		ROM_REGION( 0x100000, "maincpu", 0 )
265		ROM_LOAD ( "sbugh1-8.bin", 0xf800, 0x0800, CRC(10a045a7) SHA1(de547b77653951c7424a069520d52c5b0432e98d) )
	264	ROM_REGION( 0x100000, "maincpu", 0 )
	265	ROM_LOAD ( "sbugh1-8.bin", 0xf800, 0x0800, CRC(10a045a7) SHA1(de547b77653951c7424a069520d52c5b0432e98d) )
266	266	ROM_END
267	267
268	268	ROM_START( swtpc09i )
269		ROM_REGION( 0x100000, "maincpu", 0 )
270		ROM_LOAD ( "hd-rom.bin", 0xe800, 0x0800, CRC(b898b4d7) SHA1(2806633eda7da4e9a243fc534f15526ee928b6bc) )
271		ROM_LOAD ( "sbugh1-8.bin", 0xf800, 0x0800, CRC(10a045a7) SHA1(de547b77653951c7424a069520d52c5b0432e98d) )
	269	ROM_REGION( 0x100000, "maincpu", 0 )
	270	ROM_LOAD ( "hd-rom.bin", 0xe800, 0x0800, CRC(b898b4d7) SHA1(2806633eda7da4e9a243fc534f15526ee928b6bc) )
	271	ROM_LOAD ( "sbugh1-8.bin", 0xf800, 0x0800, CRC(10a045a7) SHA1(de547b77653951c7424a069520d52c5b0432e98d) )
272	272	ROM_END
273	273
274	274	ROM_START( swtpc09u )
275		ROM_REGION( 0x100000, "maincpu", 0 )
276		ROM_LOAD ( "unibug.bin", 0xf800, 0x0800, CRC(92e1cbf2) SHA1(db00f17ee9accdbfa1775fe0162d3556159b8e70) )
	275	ROM_REGION( 0x100000, "maincpu", 0 )
	276	ROM_LOAD ( "unibug.bin", 0xf800, 0x0800, CRC(92e1cbf2) SHA1(db00f17ee9accdbfa1775fe0162d3556159b8e70) )
277	277	ROM_END
278	278
279	279	ROM_START( swtpc09d3 )
280		ROM_REGION( 0x100000, "maincpu", 0 )
281		ROM_LOAD ( "uos3.bin", 0xf800, 0x0800, CRC(e95eb3e0) SHA1(3e971d3b7e143bc87e4b506e18a8c928c089c25a) )
	280	ROM_REGION( 0x100000, "maincpu", 0 )
	281	ROM_LOAD ( "uos3.bin", 0xf800, 0x0800, CRC(e95eb3e0) SHA1(3e971d3b7e143bc87e4b506e18a8c928c089c25a) )
282	282	ROM_END
283	283
284	284	/* Driver */

trunk/src/mess/drivers/tandy1t.c
r29404	r29405
434	434	PORT_MODIFY("pc_keyboard_2")
435	435	PORT_BIT(0x0200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Cursor Up") PORT_CODE(KEYCODE_UP) /* 29 A9 */
436	436	PORT_BIT(0x0800, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Cursor Left") PORT_CODE(KEYCODE_LEFT) /* 2B AB */
437
	437
438	438	PORT_MODIFY("pc_keyboard_3")
439	439	PORT_BIT(0x0400, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Caps") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE /* Caps Lock 3A BA */
440	440
r29404	r29405
566	566
567	567	MCFG_ISA8_SLOT_ADD("mb:isa", "isa_fdc", pc_isa8_cards, "fdc_xt", true)
568	568	MCFG_SLOT_OPTION_MACHINE_CONFIG("fdc_xt", cfg_fdc_35)
569
	569
570	570	MCFG_ISA8_SLOT_ADD("mb:isa", "isa_lpt", pc_isa8_cards, "lpt", true)
571	571	MCFG_ISA8_SLOT_ADD("mb:isa", "isa_com", pc_isa8_cards, "com", true)
572
	572
573	573	MCFG_PC_JOY_ADD("pc_joy")
574	574	MCFG_PC_KEYB_ADD("pc_keyboard", DEVWRITELINE("mb:pic8259", pic8259_device, ir1_w))
575	575
r29404	r29405
579	579	MACHINE_CONFIG_END
580	580
581	581	static MACHINE_CONFIG_START( t1000hx, tandy1000_state )
582		MCFG_CPU_ADD("maincpu", I8088, 8000000)
	582	MCFG_CPU_ADD("maincpu", I8088, 8000000)
583	583	MCFG_CPU_PROGRAM_MAP(tandy1000_map)
584	584	MCFG_CPU_IO_MAP(tandy1000_io)
585	585
586	586	MCFG_FRAGMENT_ADD(tandy1000_common)
587
	587
588	588	// plus cards are isa with a nonstandard conntector
589	589	MCFG_ISA8_SLOT_ADD("mb:isa", "plus1", pc_isa8_cards, NULL, false)
590	590	MACHINE_CONFIG_END
r29404	r29405
809	809	COMP( 1989, t1000rl, ibm5150, 0, t1000_16, tandy1t, tandy1000_state, t1000hx, "Tandy Radio Shack", "Tandy 1000 RL", 0)
810	810	COMP( 1989, t1000tl2, ibm5150, 0, t1000_286, tandy1t, tandy1000_state, t1000hx, "Tandy Radio Shack", "Tandy 1000 TL/2", 0)
811	811	COMP( 1988, t1000sl2, ibm5150, 0, t1000_16_8, tandy1t, tandy1000_state, t1000sl, "Tandy Radio Shack", "Tandy 1000 SL/2", 0)
812

trunk/src/mess/drivers/pc9801.c
r29404	r29405
452	452	m_beeper(*this, "beeper"),
453	453	m_ram(*this, RAM_TAG),
454	454	m_gfxdecode(*this, "gfxdecode"),
455		m_palette(*this, "palette")
	455	m_palette(*this, "palette")
456	456	{
457	457	}
458	458
r29404	r29405
683	683	DECLARE_WRITE8_MEMBER(pc9821_ext2_video_ff_w);
684	684
685	685	DECLARE_FLOPPY_FORMATS( floppy_formats );
686		UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
687		UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
	686	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
	687	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
688	688
689	689	private:
690	690	UINT8 m_sdip_read(UINT16 port, UINT8 sdip_offset);
r29404	r29405
726	726	DECLARE_WRITE8_MEMBER(ppi_fdd_portc_w);
727	727
728	728	DECLARE_WRITE_LINE_MEMBER(fdc_2dd_irq);
729		DECLARE_WRITE_LINE_MEMBER(pc9801rs_fdc_irq);
730		DECLARE_WRITE_LINE_MEMBER(pc9801rs_fdc_drq);
	729	DECLARE_WRITE_LINE_MEMBER(pc9801rs_fdc_irq);
	730	DECLARE_WRITE_LINE_MEMBER(pc9801rs_fdc_drq);
731	731
732	732	DECLARE_READ8_MEMBER(ppi_mouse_porta_r);
733	733	DECLARE_WRITE8_MEMBER(ppi_mouse_porta_w);
r29404	r29405
3566	3566	}
3567	3567
3568	3568	static MACHINE_CONFIG_FRAGMENT( pc9801_keyboard )
3569		MCFG_DEVICE_ADD("keyb", PC9801_KBD, 53)
3570		MCFG_PC9801_KBD_IRQ_CALLBACK(WRITELINE(pc9801_state, keyboard_irq))
	3569	MCFG_DEVICE_ADD("keyb", PC9801_KBD, 53)
	3570	MCFG_PC9801_KBD_IRQ_CALLBACK(WRITELINE(pc9801_state, keyboard_irq))
3571	3571	MACHINE_CONFIG_END
3572	3572
3573	3573	static MACHINE_CONFIG_FRAGMENT( pc9801_mouse )
r29404	r29405
3627	3627	MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
3628	3628
3629	3629	MCFG_UPD765A_ADD("upd765_2hd", false, true)
3630		MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE("pic8259_slave", pic8259_device, ir3_w))
3631		MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq2_w)) MCFG_DEVCB_INVERT
	3630	MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE("pic8259_slave", pic8259_device, ir3_w))
	3631	MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq2_w)) MCFG_DEVCB_INVERT
3632	3632	MCFG_UPD765A_ADD("upd765_2dd", false, true)
3633		MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc9801_state, fdc_2dd_irq))
3634		MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq3_w)) MCFG_DEVCB_INVERT
	3633	MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc9801_state, fdc_2dd_irq))
	3634	MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq3_w)) MCFG_DEVCB_INVERT
3635	3635	MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:0", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3636	3636	MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:1", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3637	3637	MCFG_FLOPPY_DRIVE_ADD("upd765_2dd:0", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
r29404	r29405
3654	3654	MCFG_SCREEN_SIZE(640, 480)
3655	3655	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
3656	3656
3657		MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
3658		MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
3659		MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
3660		MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
	3657	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
	3658	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
	3659	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
	3660	MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
3661	3661
3662		MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
3663		MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
3664		MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
	3662	MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
	3663	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
	3664	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
3665	3665
3666	3666	MCFG_PALETTE_ADD("palette", 16)
3667	3667	MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)
r29404	r29405
3711	3711	MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
3712	3712
3713	3713	MCFG_UPD765A_ADD("upd765_2hd", false, true)
3714		MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_irq))
3715		MCFG_UPD765_DRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_drq))
	3714	MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_irq))
	3715	MCFG_UPD765_DRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_drq))
3716	3716	//"upd765_2dd"
3717	3717	MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:0", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3718	3718	MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:1", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
r29404	r29405
3732	3732	MCFG_SCREEN_SIZE(640, 480)
3733	3733	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
3734	3734
3735		MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
3736		MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
3737		MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
3738		MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
	3735	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
	3736	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
	3737	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
	3738	MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
3739	3739
3740		MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
3741		MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
3742		MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
	3740	MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
	3741	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
	3742	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
3743	3743
3744	3744	MCFG_PALETTE_ADD("palette", 16+16)
3745	3745	MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)
r29404	r29405
3803	3803	MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
3804	3804
3805	3805	MCFG_UPD765A_ADD("upd765_2hd", false, true)
3806		MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE("pic8259_slave", pic8259_device, ir3_w))
3807		MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq2_w)) MCFG_DEVCB_INVERT
	3806	MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE("pic8259_slave", pic8259_device, ir3_w))
	3807	MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq2_w)) MCFG_DEVCB_INVERT
3808	3808	//"upd765_2dd"
3809	3809	MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:0", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3810	3810	MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:1", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
r29404	r29405
3824	3824	MCFG_SCREEN_SIZE(640, 480)
3825	3825	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
3826	3826
3827		MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
3828		MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
3829		MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
3830		MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
	3827	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
	3828	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
	3829	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
	3830	MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
3831	3831
3832		MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
3833		MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
3834		MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
	3832	MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
	3833	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
	3834	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
3835	3835
3836	3836	MCFG_PALETTE_ADD("palette", 16+16+256)
3837	3837	MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)

trunk/src/mess/drivers/qx10.c
r29404	r29405
70	70	m_vram_bank(0),
71	71	m_maincpu(*this, "maincpu"),
72	72	m_ram(*this, RAM_TAG),
73		m_palette(*this, "palette")
	73	m_palette(*this, "palette")
74	74	{
75	75	}
76	76
r29404	r29405
849	849	MCFG_I8255_ADD("i8255", qx10_i8255_interface)
850	850	MCFG_I8237_ADD("8237dma_1", MAIN_CLK/4, qx10_dma8237_1_interface)
851	851	MCFG_I8237_ADD("8237dma_2", MAIN_CLK/4, qx10_dma8237_2_interface)
852
	852
853	853	MCFG_DEVICE_ADD("upd7220", UPD7220, MAIN_CLK/6) // unk clock
854	854	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
855	855	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(qx10_state, hgdc_display_pixels)

trunk/src/mess/drivers/uknc.c
r29404	r29405
73	73	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
74	74	MCFG_SCREEN_UPDATE_DRIVER(uknc_state, screen_update_uknc)
75	75	MCFG_SCREEN_PALETTE("palette")
76
	76
77	77	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
78	78	MACHINE_CONFIG_END
79	79

trunk/src/mess/drivers/sv8000.c
r29404	r29405
274	274
275	275	static I8255_INTERFACE( sv8000_i8255_interface )
276	276	{
277		DEVCB_DRIVER_MEMBER(sv8000_state, i8255_porta_r), /* port A read */
278		DEVCB_DRIVER_MEMBER(sv8000_state, i8255_porta_w), /* port A write */
279		DEVCB_DRIVER_MEMBER(sv8000_state, i8255_portb_r), /* port B read */
280		DEVCB_DRIVER_MEMBER(sv8000_state, i8255_portb_w), /* port B write */
281		DEVCB_DRIVER_MEMBER(sv8000_state, i8255_portc_r), /* port C read */
282		DEVCB_DRIVER_MEMBER(sv8000_state, i8255_portc_w) /* port C write */
	277	DEVCB_DRIVER_MEMBER(sv8000_state, i8255_porta_r), /* port A read */
	278	DEVCB_DRIVER_MEMBER(sv8000_state, i8255_porta_w), /* port A write */
	279	DEVCB_DRIVER_MEMBER(sv8000_state, i8255_portb_r), /* port B read */
	280	DEVCB_DRIVER_MEMBER(sv8000_state, i8255_portb_w), /* port B write */
	281	DEVCB_DRIVER_MEMBER(sv8000_state, i8255_portc_r), /* port C read */
	282	DEVCB_DRIVER_MEMBER(sv8000_state, i8255_portc_w) /* port C write */
283	283	};
284	284
285	285
r29404	r29405
379	379	offset = ( ( offset & 0x1fc0 ) >> 1 ) \| ( offset & 0x1f );
380	380	return m_videoram[offset % 0xc00];
381	381	}
382		else
	382	else
383	383	{
384	384	// 256 x 96 / 3KB
385	385	return m_videoram[offset % 0xc00];
r29404	r29405
455	455
456	456	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
457	457	CONS( 1979, sv8000, 0, 0, sv8000, sv8000, driver_device, 0, "Bandai", "Super Vision 8000 (TV Jack 8000)", 0 )
458

trunk/src/mess/drivers/rm380z.c
r29404	r29405
158	158	MCFG_SCREEN_VISIBLE_AREA(0, (RM380Z_SCREENCOLS(RM380Z_CHDIMX+1))-1, 0, (RM380Z_SCREENROWS(RM380Z_CHDIMY+1))-1)
159	159	MCFG_SCREEN_UPDATE_DRIVER(rm380z_state, screen_update_rm380z)
160	160	MCFG_SCREEN_PALETTE("palette")
161
	161
162	162	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
163	163
164	164	/* RAM configurations */

trunk/src/mess/drivers/apricotf.c
r29404	r29405
312	312	MCFG_SCREEN_SIZE(640, 256)
313	313	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 256-1)
314	314	MCFG_SCREEN_PALETTE("palette")
315
	315
316	316	MCFG_PALETTE_ADD("palette", 16)
317	317	MCFG_GFXDECODE_ADD("gfxdecode", "palette", act_f1)
318	318

trunk/src/mess/drivers/hprot1.c
r29404	r29405
158	158	/*
159	159	WRITE8_MEMBER(hprot1_state::henry_io_w)
160	160	{
161		static UINT8 p0=0, p1=0, p2=0, p3=0;
162		switch (offset)
163		{
164		case 0x00:
165		{
166		if (data != p0)
167		{
168		p0=data;
	161	static UINT8 p0=0, p1=0, p2=0, p3=0;
	162	switch (offset)
	163	{
	164	case 0x00:
	165	{
	166	if (data != p0)
	167	{
	168	p0=data;
169	169	#if LOG_IO_PORTS
170		printf("Write to P0: %02X\n", data);
	170	printf("Write to P0: %02X\n", data);
171	171	#endif
172		}
173		break;
174		}
175		case 0x01:
176		{
177		if (data != p1)
178		{
179		p1=data;
180		if (data != 0xFF && data != 0xEF)
	172	}
	173	break;
	174	}
	175	case 0x01:
	176	{
	177	if (data != p1)
	178	{
	179	p1=data;
	180	if (data != 0xFF && data != 0xEF)
181	181	#if LOG_IO_PORTS
182		printf("Write to P1: %02X\n", data);
	182	printf("Write to P1: %02X\n", data);
183	183	#endif
184		}
185		break;
186		}
187		case 0x02:
188		{
189		if (data != p2)
190		{
191		p2=data;
	184	}
	185	break;
	186	}
	187	case 0x02:
	188	{
	189	if (data != p2)
	190	{
	191	p2=data;
192	192	#if LOG_IO_PORTS
193		printf("Write to P2: %02X\n", data);
	193	printf("Write to P2: %02X\n", data);
194	194	#endif
195		}
196		break;
197		}
198		case 0x03:
199		{
200		if (data != p3)
201		{
202		p3=data;
	195	}
	196	break;
	197	}
	198	case 0x03:
	199	{
	200	if (data != p3)
	201	{
	202	p3=data;
203	203	#if LOG_IO_PORTS
204		printf("Write to P3: %02X\n", data);
	204	printf("Write to P3: %02X\n", data);
205	205	#endif
206		}
207		break;
208		}
209		}
	206	}
	207	break;
	208	}
	209	}
210	210	}
211	211	*/
212	212
r29404	r29405
245	245	MCFG_SCREEN_SIZE(616, 92)
246	246	MCFG_SCREEN_VISIBLE_AREA(0, 616-1, 0, 92-1)
247	247	MCFG_SCREEN_PALETTE("palette")
248
	248
249	249	MCFG_DEFAULT_LAYOUT(layout_lcd)
250	250	MCFG_PALETTE_ADD("palette", 2)
251	251	MCFG_PALETTE_INIT_OWNER(hprot1_state, hprot1)

trunk/src/mess/drivers/pcm.c
r29404	r29405
327	327	MCFG_SCREEN_SIZE(648, 168)
328	328	MCFG_SCREEN_VISIBLE_AREA(0, 648-1, 0, 168-1)
329	329	MCFG_SCREEN_PALETTE("palette")
330
	330
331	331	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pcm)
332	332	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
333	333

trunk/src/mess/drivers/pipbug.c
r29404	r29405
71	71	ADDRESS_MAP_END
72	72
73	73	static ADDRESS_MAP_START(pipbug_io, AS_IO, 8, pipbug_state)
74		// ADDRESS_MAP_UNMAP_HIGH
	74	// ADDRESS_MAP_UNMAP_HIGH
75	75	AM_RANGE(S2650_CTRL_PORT, S2650_CTRL_PORT) AM_WRITE(pipbug_ctrl_w)
76	76	AM_RANGE(S2650_SENSE_PORT, S2650_SENSE_PORT) AM_READNOP // this has to return zero or the parameter to write_sense is ignored
77	77	ADDRESS_MAP_END

trunk/src/mess/drivers/bml3.c
r29404	r29405
153	153	required_device<speaker_sound_device> m_speaker;
154	154	optional_device<ym2203_device> m_ym2203;
155	155	required_device<acia6850_device> m_acia6850;
156		public:
	156	public:
157	157	required_device<palette_device> m_palette;
158	158	};
159	159

trunk/src/mess/drivers/esqasr.c
r29404	r29405
59	59
60	60	virtual void machine_reset();
61	61
62		DECLARE_DRIVER_INIT(asr);
	62	DECLARE_DRIVER_INIT(asr);
63	63	DECLARE_WRITE_LINE_MEMBER(esq5506_otto_irq);
64		DECLARE_READ16_MEMBER(esq5506_read_adc);
	64	DECLARE_READ16_MEMBER(esq5506_read_adc);
65	65	};
66	66
67	67	void esqasr_state::machine_reset()

trunk/src/mess/drivers/pve500.c
r29404	r29405
73	73	static const z80sio_interface external_sio_intf =
74	74	{
75	75	DEVCB_NULL, /* interrupt handler */
76		DEVCB_NULL, /* DTR changed handler */
	76	DEVCB_NULL, /* DTR changed handler */
77	77	DEVCB_NULL, /* RTS changed handler */
78	78	DEVCB_NULL, /* BREAK changed handler */
79	79	DEVCB_NULL, /* transmit handler */
r29404	r29405
151	151	{
152	152	//printf("dualport_ram: Right WRITE\n");
153	153	dualport_7FE_data = data;
154		m_maincpu->ctc_trg1(0); //(INT_Left)
	154	m_maincpu->ctc_trg1(0); //(INT_Left)
155	155	}
156	156
157	157	READ8_MEMBER(pve500_state::io_expander_r)
r29404	r29405
203	203	case 128: output_set_digit_value(8*i + 7, io_LD & 0x7F); break;
204	204	default:
205	205	/*software should not do it.
206		any idea how to emulate that in case it does? */ break;
	206	any idea how to emulate that in case it does? */ break;
207	207	}
208	208	}
209	209	}

trunk/src/mess/drivers/softbox.c
r29404	r29405
413	413	MCFG_COM8116_FT_HANDLER(DEVWRITELINE(I8251_TAG, i8251_device, write_txc))
414	414
415	415	MCFG_CBM_IEEE488_ADD("c8050")
416
	416
417	417	MCFG_DEVICE_ADD(CORVUS_HDC_TAG, CORVUS_HDC, 0)
418	418	MCFG_HARDDISK_CONFIG_ADD("harddisk1", corvus_hdc_t::hd_intf)
419	419	MCFG_HARDDISK_CONFIG_ADD("harddisk2", corvus_hdc_t::hd_intf)

trunk/src/mess/drivers/geniusiq.c
r29404	r29405
811	811	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
812	812	MCFG_SCREEN_UPDATE_DRIVER( geniusiq_state, screen_update )
813	813	MCFG_SCREEN_PALETTE("palette")
814
	814
815	815	MCFG_PALETTE_ADD("palette", 16)
816	816	MCFG_PALETTE_INIT_OWNER(geniusiq_state, geniusiq)
817	817
r29404	r29405
847	847	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
848	848	MCFG_SCREEN_SIZE(512, 256)
849	849	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
850		MCFG_SCREEN_UPDATE_DRIVER( gl8008cx_state, screen_update )
	850	MCFG_SCREEN_UPDATE_DRIVER( gl8008cx_state, screen_update )
851	851	MACHINE_CONFIG_END
852	852
853	853	/* ROM definition */

trunk/src/mess/drivers/smc777.c
r29404	r29405
57	57	m_sn(*this, "sn1"),
58	58	m_beeper(*this, "beeper"),
59	59	m_gfxdecode(*this, "gfxdecode"),
60		m_palette(*this, "palette")
	60	m_palette(*this, "palette")
61	61	{ }
62	62
63	63	required_device<cpu_device> m_maincpu;
r29404	r29405
1095	1095	MCFG_PALETTE_INIT_OWNER(smc777_state, smc777)
1096	1096
1097	1097	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1098
	1098
1099	1099	MCFG_MC6845_ADD("crtc", H46505, "screen", MASTER_CLOCK/2, mc6845_intf) /* unknown clock, hand tuned to get ~60 fps */
1100	1100
1101	1101	MCFG_MB8876_ADD("fdc",smc777_mb8876_interface)

trunk/src/mess/drivers/alphatro.c
r29404	r29405
85	85	private:
86	86	UINT8 m_timer_bit;
87	87	UINT8 m_cass_data[4];
88		bool m_cass_state;
	88	bool m_cass_state;
89	89	emu_timer* m_sys_timer;
90	90	virtual void video_start();
91	91	virtual void machine_start();
r29404	r29405
97	97	required_device<cassette_image_device> m_cass;
98	98	required_device<beep_device> m_beep;
99	99	required_shared_ptr<UINT8> m_p_ram;
100		public:
	100	public:
101	101	required_device<palette_device> m_palette;
102	102	};
103	103

trunk/src/mess/drivers/hp9k.c
r29404	r29405
161	161	DECLARE_WRITE8_MEMBER(kbd_put);
162	162
163	163	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
164
	164
165	165	required_device<gfxdecode_device> m_gfxdecode;
166	166	};
167	167

trunk/src/mess/drivers/fanucs15.c
r29404	r29405
2	2	// copyright-holders:R. Belmont
3	3	/***************************************************************************
4	4
5		Fanuc System 15
	5	Fanuc System 15
6	6
7		2014-01-04 Skeleton driver.
	7	2014-01-04 Skeleton driver.
8	8
9		This is a circa-1990 CNC machine with a very custom GUI, made of a
10		bunch of boards plugged into a passive backplane.
	9	This is a circa-1990 CNC machine with a very custom GUI, made of a
	10	bunch of boards plugged into a passive backplane.
11	11
12		Possible boards include:
13		A16B-2200-0020/04B : Base 2 Board (contains 12 MHz 68020 "CNC CPU" and 1 or 2 MB of DRAM)
14		A16B-2200-0090/07A : Digital Servo 4-Axis Controller Board (no ROMs on this board)
15		A16B-2200-0121/06C : Base 0 Board (1 ROM location but position is empty. -0120 has 6081 001A)
	12	Possible boards include:
	13	A16B-2200-0020/04B : Base 2 Board (contains 12 MHz 68020 "CNC CPU" and 1 or 2 MB of DRAM)
	14	A16B-2200-0090/07A : Digital Servo 4-Axis Controller Board (no ROMs on this board)
	15	A16B-2200-0121/06C : Base 0 Board (1 ROM location but position is empty. -0120 has 6081 001A)
16	16
17		A16B-2200-0131/11B : Base 1 Board (15 ROMs on this board, 4040, 9030, AB02)
18		See detailed layout and description below.
19
20		A16B-2200-0150/03A : Conversational Board (4 ROMs on this board, 5A00, probably for Mill)
21		or
22		A16B-2200-0150/03A : Conversational Board (4 ROMs on this board, 5C30. 5C for 2 axis Lathe)
23		or
24		A16B-2200-0150/03A : Conversational Board (4 ROMs on this board, 5D30. 5D for 4 axis (twin Turret) lathe)
25		Fanuc FBI-A MB605111 (QFP100)
26		MB1422A (DIP42 - DRAM Controller)
27		51256-10 (x18)
28		MB89259A (SOP28)
29		Intel 80286-8
30		Intel 80287-8
31		MBL82288-8 (DIP10)
32		uPB8284 (DIP18)
33		24MHz & 32MHz OSC's
34		4 EPROMs
	17	A16B-2200-0131/11B : Base 1 Board (15 ROMs on this board, 4040, 9030, AB02)
	18	See detailed layout and description below.
35	19
36		A16B-2200-0160/07B : Graphic Board (3 ROMs on this board, 6082 001A, 600B 001D, 600B 002D. 600B is for Mill)
37		or
38		A16B-2200-0160/07B : Graphic Board (3 ROMs on this board, 6082 001A, 600A 001C, 600A 001D. 600A is for Lathe)
39		Fanuc FBI-A MB605111 (QFP100)
40		HD68HC000P10 (68000 @10MHz, PLCC68)
41		HM62256-10 (x2)
42		HM53461-12 (x3)
43		HD63484 (PLCC68)
44		HD6445 (PLCC44)
45		Fanuc GBC MB652147 (PGA135)
46		MB81464-12 (x12)
47		20MHz OSC
48		3 EPROMs. 6082 is common to both mills and lathes.
49		600A is a known EPROM version required for lathes with FAPT conversational graphics.
50		600B is unknown. Possibly for mills with FAPT.
	20	A16B-2200-0150/03A : Conversational Board (4 ROMs on this board, 5A00, probably for Mill)
	21	or
	22	A16B-2200-0150/03A : Conversational Board (4 ROMs on this board, 5C30. 5C for 2 axis Lathe)
	23	or
	24	A16B-2200-0150/03A : Conversational Board (4 ROMs on this board, 5D30. 5D for 4 axis (twin Turret) lathe)
	25	Fanuc FBI-A MB605111 (QFP100)
	26	MB1422A (DIP42 - DRAM Controller)
	27	51256-10 (x18)
	28	MB89259A (SOP28)
	29	Intel 80286-8
	30	Intel 80287-8
	31	MBL82288-8 (DIP10)
	32	uPB8284 (DIP18)
	33	24MHz & 32MHz OSC's
	34	4 EPROMs
51	35
52		A20B-1003-0230/09C : Motherboard (dumb backplane, contains only slots)
53		A20B-1003-0500/01A : Additional Graphic Board for 15TTF only (for TT, connects to A16B-2200-0160 Board. No info on this PCB)
54		A20B-1003-0240/07B : Connector Assembly Unit / IO Board
55		A20B-1003-0580/01A : PMC Cassette C (16000 Step + Pascal 128KB, small PCB in a yellow plastic box, contains just 2 EPROMs)
56
57
58		Fanuc System 15A Base 1 Board A16B-2200-013
	36	A16B-2200-0160/07B : Graphic Board (3 ROMs on this board, 6082 001A, 600B 001D, 600B 002D. 600B is for Mill)
	37	or
	38	A16B-2200-0160/07B : Graphic Board (3 ROMs on this board, 6082 001A, 600A 001C, 600A 001D. 600A is for Lathe)
	39	Fanuc FBI-A MB605111 (QFP100)
	40	HD68HC000P10 (68000 @10MHz, PLCC68)
	41	HM62256-10 (x2)
	42	HM53461-12 (x3)
	43	HD63484 (PLCC68)
	44	HD6445 (PLCC44)
	45	Fanuc GBC MB652147 (PGA135)
	46	MB81464-12 (x12)
	47	20MHz OSC
	48	3 EPROMs. 6082 is common to both mills and lathes.
	49	600A is a known EPROM version required for lathes with FAPT conversational graphics.
	50	600B is unknown. Possibly for mills with FAPT.
59	51
60		PCB Layout
61		----------
	52	A20B-1003-0230/09C : Motherboard (dumb backplane, contains only slots)
	53	A20B-1003-0500/01A : Additional Graphic Board for 15TTF only (for TT, connects to A16B-2200-0160 Board. No info on this PCB)
	54	A20B-1003-0240/07B : Connector Assembly Unit / IO Board
	55	A20B-1003-0580/01A : PMC Cassette C (16000 Step + Pascal 128KB, small PCB in a yellow plastic box, contains just 2 EPROMs)
62	56
63		A16B-2200-0131/03B (note 1 and 03B have been added/printed later)
64		\|--------------\| \|---\|
65		\|------\| CA34 \|-----\|CA4\|-------------------------------------\|
66		\| \|--------------\|75463\|---\| LL LL MB81C79A\|
67		\| (x6) LL LL \|--------\| \|
68		\| HM53461(x5)\|MB605117\| \|
69		\| FA8191 \| \| \|
70		\|4040002E.M27 4040001E.M23 FA8191 \| \| \|
71		\| \|--------\| \|
72		\| \|
73		\| MC-122-41256A9A-12 \|--------\| \|
74		\|AB02142A.K27 AB02141A.K23 MC-122-41256A9A-12 \|MB661128\| \|
75		\| 9030001E.J18 \| \| \|
76		\| \| \| \|
77		\| \|--------\| \|
78		\|AB02102A.H27 AB02101A.H23 \|
79		\| \|
80		\| \|
81		\| \|
82		\|AB020C2A.F27 AB020C1A.F23 24MHz \|
83		\| \|
84		\| \|
85		\| \|--------\| \|
86		\|AB02082A.E27 AB02081A.E23 \|------\| \|MB605111\| \|
87		\| \|68000 \| \| \| \|
88		\| \| \| \| \| \|
89		\| \|---------\| \| \| \|--------\| \|
90		\| \|---------\| \|------\| \|
91		\| CNM1 \|-----------------------\| \|
92		\|------------------------------------------\| CNA \|--\|
93		\|-----------------------\|
94		Notes:
95		MC-122-41256- NEC MC-122-41256A9A-12 256k RAM SIP module (with parity) containing NEC D41256L-12 32k x8 SRAM
96		2 SIP modules populated, 9 chips per module, 18 total RAMs, total 512k
97		68000 - Hitachi HD68HC000-12 68000 CPU. Clock 24/2 (PLCC68)
98		MB661128 - Fujitsu Fanuc SLC01 MB661128 (Serial Data Link Controller, PLCC68)
99		MB605117 - Fujitsu Fanuc BOC MB605117U (DRAM/SRAM Interface Controller, QFP100)
100		MB605111 - Fujitsu Fanuc FBI-A MB605111 (Global/Local Interface Controller, QFP100)
101		HM53461 - Hitachi HM53461-12 64k x4-bit multiport CMOS video RAM (x5, SOJ24)
102		MB81C79A - Fujitsu MB81C79A-35 8k x 9-bit (72k) CMOS Static RAM (SOP28)
103		FA8191 - Fanuc FA8191 RV07 custom ceramic module (contains resistors and transistors, SIL16)
104		75463 - Texas Instruments SN75463 Dual High-Voltage, High-Current Peripheral Driver (DIP8)
105		L - LED
106		CA34 - Connector for PMC Cassette C A02B-0094-C103 (holds 2 EPROMs containing the PMC Ladder)
107		The Ladder is specific and unique to each CNC machine, depending on capability and options.
108		CA4 - Connector for cable joined to Servo Control Board A16B-2200-0090 or 16B-2200-0091
109		CNA - Connector plugs into motherboard slot CNA2 (BASE 1)
110		CNM1 - 40 pin flat cable joined to optional board A16B-1600-0280/02A
111	57
112		Note about EPROMs:
113		Software Series is denoted by the first 4 digits
114		ROM # (possibly relating to the memory location in hex) is the next 3 digits
115		Software Revision is the last letter
116		Both IC locations and ROM # are printed on this board
	58	Fanuc System 15A Base 1 Board A16B-2200-013
117	59
118		ROM IC Memory EPROM Used
119		Label Location Location Type For...
120		-----------------------------------------------------------------------------------------
121		9030001E J18 381 27256 Digital Servo Control Program Version 9030 Revision E
	60	PCB Layout
	61	----------
122	62
123		4040001E M23 001 27C1001 PMC Control Program Version 4040 Revision E
124		4040002E M27 002 27C1001
	63	A16B-2200-0131/03B (note 1 and 03B have been added/printed later)
	64	\|--------------\| \|---\|
	65	\|------\| CA34 \|-----\|CA4\|-------------------------------------\|
	66	\| \|--------------\|75463\|---\| LL LL MB81C79A\|
	67	\| (x6) LL LL \|--------\| \|
	68	\| HM53461(x5)\|MB605117\| \|
	69	\| FA8191 \| \| \|
	70	\|4040002E.M27 4040001E.M23 FA8191 \| \| \|
	71	\| \|--------\| \|
	72	\| \|
	73	\| MC-122-41256A9A-12 \|--------\| \|
	74	\|AB02142A.K27 AB02141A.K23 MC-122-41256A9A-12 \|MB661128\| \|
	75	\| 9030001E.J18 \| \| \|
	76	\| \| \| \|
	77	\| \|--------\| \|
	78	\|AB02102A.H27 AB02101A.H23 \|
	79	\| \|
	80	\| \|
	81	\| \|
	82	\|AB020C2A.F27 AB020C1A.F23 24MHz \|
	83	\| \|
	84	\| \|
	85	\| \|--------\| \|
	86	\|AB02082A.E27 AB02081A.E23 \|------\| \|MB605111\| \|
	87	\| \|68000 \| \| \| \|
	88	\| \| \| \| \| \|
	89	\| \|---------\| \| \| \|--------\| \|
	90	\| \|---------\| \|------\| \|
	91	\| CNM1 \|-----------------------\| \|
	92	\|------------------------------------------\| CNA \|--\|
	93	\|-----------------------\|
	94	Notes:
	95	MC-122-41256- NEC MC-122-41256A9A-12 256k RAM SIP module (with parity) containing NEC D41256L-12 32k x8 SRAM
	96	2 SIP modules populated, 9 chips per module, 18 total RAMs, total 512k
	97	68000 - Hitachi HD68HC000-12 68000 CPU. Clock 24/2 (PLCC68)
	98	MB661128 - Fujitsu Fanuc SLC01 MB661128 (Serial Data Link Controller, PLCC68)
	99	MB605117 - Fujitsu Fanuc BOC MB605117U (DRAM/SRAM Interface Controller, QFP100)
	100	MB605111 - Fujitsu Fanuc FBI-A MB605111 (Global/Local Interface Controller, QFP100)
	101	HM53461 - Hitachi HM53461-12 64k x4-bit multiport CMOS video RAM (x5, SOJ24)
	102	MB81C79A - Fujitsu MB81C79A-35 8k x 9-bit (72k) CMOS Static RAM (SOP28)
	103	FA8191 - Fanuc FA8191 RV07 custom ceramic module (contains resistors and transistors, SIL16)
	104	75463 - Texas Instruments SN75463 Dual High-Voltage, High-Current Peripheral Driver (DIP8)
	105	L - LED
	106	CA34 - Connector for PMC Cassette C A02B-0094-C103 (holds 2 EPROMs containing the PMC Ladder)
	107	The Ladder is specific and unique to each CNC machine, depending on capability and options.
	108	CA4 - Connector for cable joined to Servo Control Board A16B-2200-0090 or 16B-2200-0091
	109	CNA - Connector plugs into motherboard slot CNA2 (BASE 1)
	110	CNM1 - 40 pin flat cable joined to optional board A16B-1600-0280/02A
125	111
126		AB02081A E23 081 27C1001 Boot Software Version AB02 Revision A
127		AB02082A E27 082 27C1001
128		AB020C1A F23 0C1 27C1001
129		AB020C2A F27 0C2 27C1001
130		AB02101A H23 101 27C1001
131		AB02102A H27 102 27C1001
132		AB02141A K23 141 27C1001
133		AB02142A K27 142 27C1001
	112	Note about EPROMs:
	113	Software Series is denoted by the first 4 digits
	114	ROM # (possibly relating to the memory location in hex) is the next 3 digits
	115	Software Revision is the last letter
	116	Both IC locations and ROM # are printed on this board
134	117
	118	ROM IC Memory EPROM Used
	119	Label Location Location Type For...
	120	-----------------------------------------------------------------------------------------
	121	9030001E J18 381 27256 Digital Servo Control Program Version 9030 Revision E
135	122
136		Another identical board from a different machine contains the following EPROMs....
137		9030001F (known revisions exist up to at least rev M)
138		4040001D, 4040002D (known revisions exist up to at least rev I)
139		A202081G, A202082G
140		A2020C1G, A2020C2G
141		A202101G, A202102G
	123	4040001E M23 001 27C1001 PMC Control Program Version 4040 Revision E
	124	4040002E M27 002 27C1001
142	125
143		The complete boot software series is listed below:
	126	AB02081A E23 081 27C1001 Boot Software Version AB02 Revision A
	127	AB02082A E27 082 27C1001
	128	AB020C1A F23 0C1 27C1001
	129	AB020C2A F27 0C2 27C1001
	130	AB02101A H23 101 27C1001
	131	AB02102A H27 102 27C1001
	132	AB02141A K23 141 27C1001
	133	AB02142A K27 142 27C1001
144	134
145		15TA SOFTWARE SERIES (Single Turret 2 Axis Lathe)
146		\|------+----+---------+---+---+---+---\|
147		\|S/W \|STEP\| CRT \|I/O\|SER\|SER\|DNC\|
148		\|SERIES\| \| \| \| \| \| \|
149		\| \|1 2\| 9M 14 9C\|LNK\|SPN\|FB \|1 2\|
150		+------+----+---------+---+---+---+---+
151		\|A201 \|X \| X \| \| \| \| \|
152		\|A202 \|X \| X \| \| \| \| \|
153		\|A211 \| X\| X \| X \| X \| \|X \|
154		\|A212 \| X\| X \| X \| X \| \|X \|
155		\|A219 \| X\| X \| X \| X \| X \| \|
156		\|A220 \| X\| X \| X \| X \| X \| \|
157		\|A215 \| X\| X \| X \| X \| \| X\|
158		\|A216 \| X\| X \| X \| X \| \| X\|
159		\|A217 \| X\| X \| X \| X \| X \| X\|
160		\|A218 \| X\| X \| X \| X \| X \| X\|
161		\|A221 \| X\| X \| X \| X \| ? \| ?\|
162		\|------+----+---------+---+---+---+---\|
163		Notes:
164		9M - 9" Monochrome
165		9C - 9" Color
166		14 - 14" Color
167		SER SPN - Serial Spindle
168		SER FB - Serial FB ?
169		DNC 1/2 - DNC (Direct NC) type 1 or type 2 for Direct PC to CNC program transfer operation
170	135
	136	Another identical board from a different machine contains the following EPROMs....
	137	9030001F (known revisions exist up to at least rev M)
	138	4040001D, 4040002D (known revisions exist up to at least rev I)
	139	A202081G, A202082G
	140	A2020C1G, A2020C2G
	141	A202101G, A202102G
171	142
172		15TTA SOFTWARE SERIES (Twin Turret 4 Axis Lathe)
173		\|------+----+---------+---+---+---+---\|
174		\|S/W \|STEP\| CRT \|I/O\|SER\|SER\|DNC\|
175		\|SERIES\| \| \| \| \| \| \|
176		\| \|1 2\| 9M 14 9C\|LNK\|SPN\|FB \|1 2\|
177		+------+----+---------+---+---+---+---+
178		\|A401 \|X \| X \| \| \| \| \|
179		\|A402 \|X \| X \| \| \| \| \|
180		\|A411 \| X\| X \| X \| X \| \|X \|
181		\|A412 \| X\| X \| X \| X \| \|X \|
182		\|A419 \| X\| X \| X \| X \| X \| \|
183		\|A420 \| X\| X \| X \| X \| X \| \|
184		\|------+----+---------+---+---+---+---\|
	143	The complete boot software series is listed below:
185	144
	145	15TA SOFTWARE SERIES (Single Turret 2 Axis Lathe)
	146	\|------+----+---------+---+---+---+---\|
	147	\|S/W \|STEP\| CRT \|I/O\|SER\|SER\|DNC\|
	148	\|SERIES\| \| \| \| \| \| \|
	149	\| \|1 2\| 9M 14 9C\|LNK\|SPN\|FB \|1 2\|
	150	+------+----+---------+---+---+---+---+
	151	\|A201 \|X \| X \| \| \| \| \|
	152	\|A202 \|X \| X \| \| \| \| \|
	153	\|A211 \| X\| X \| X \| X \| \|X \|
	154	\|A212 \| X\| X \| X \| X \| \|X \|
	155	\|A219 \| X\| X \| X \| X \| X \| \|
	156	\|A220 \| X\| X \| X \| X \| X \| \|
	157	\|A215 \| X\| X \| X \| X \| \| X\|
	158	\|A216 \| X\| X \| X \| X \| \| X\|
	159	\|A217 \| X\| X \| X \| X \| X \| X\|
	160	\|A218 \| X\| X \| X \| X \| X \| X\|
	161	\|A221 \| X\| X \| X \| X \| ? \| ?\|
	162	\|------+----+---------+---+---+---+---\|
	163	Notes:
	164	9M - 9" Monochrome
	165	9C - 9" Color
	166	14 - 14" Color
	167	SER SPN - Serial Spindle
	168	SER FB - Serial FB ?
	169	DNC 1/2 - DNC (Direct NC) type 1 or type 2 for Direct PC to CNC program transfer operation
186	170
187		15TTF SOFTWARE SERIES (Twin Turret 4 Axis Lathe with FAPT)
188		\|------+----+---------+---+---+---+---\|
189		\|S/W \|STEP\| CRT \|I/O\|SER\|SER\|DNC\|
190		\|SERIES\| \| \| \| \| \| \|
191		\| \|1 2\| 9M 14 9C\|LNK\|SPN\|FB \|1 2\|
192		+------+----+---------+---+---+---+---+
193		\|A502 \|X \| X \| \| \| \| \|
194		\|A512 \| X\| X \| X \| X \| \|X \|
195		\|A520 \| X\| X \| X \| X \| X \| \|
196		\|------+----+---------+---+---+---+---\|
197	171
	172	15TTA SOFTWARE SERIES (Twin Turret 4 Axis Lathe)
	173	\|------+----+---------+---+---+---+---\|
	174	\|S/W \|STEP\| CRT \|I/O\|SER\|SER\|DNC\|
	175	\|SERIES\| \| \| \| \| \| \|
	176	\| \|1 2\| 9M 14 9C\|LNK\|SPN\|FB \|1 2\|
	177	+------+----+---------+---+---+---+---+
	178	\|A401 \|X \| X \| \| \| \| \|
	179	\|A402 \|X \| X \| \| \| \| \|
	180	\|A411 \| X\| X \| X \| X \| \|X \|
	181	\|A412 \| X\| X \| X \| X \| \|X \|
	182	\|A419 \| X\| X \| X \| X \| X \| \|
	183	\|A420 \| X\| X \| X \| X \| X \| \|
	184	\|------+----+---------+---+---+---+---\|
198	185
199		15MA SOFTWARE SERIES (Mill With 3 Axes minimum XYZ)
200		\|------+----+---------+---+---+---+---\|---\|
201		\|S/W \|STEP\| CRT \|I/O\|SER\|SER\|DNC\|SUB\|
202		\|SERIES\| \| \| \| \| \| \| \|
203		\| \|1 2\| 9M 14 9C\|LNK\|SPN\|FB \|1 2\|CPU\|
204		+------+----+---------+---+---+---+---+---\|
205		\|A001 \|X \| X \| \| \| \| \| \|
206		\|A002 \|X \| X \| \| \| \| \| \|
207		\|A00A \|X \| X \| \| \| \| \| \|
208		\|A00B \|X \| X \| \| \| \| \| \|
209		\|AA01 \|X \| X \| \| \| \| \| X \|
210		\|AA02 \|X \| X \| \| \| \| \| X \|
211		\|A011 \| X\| X \| X \| X \| \|X \| \|
212		\|A012 \| X\| X \| X \| X \| \|X \| \|
213		\|AA11 \| X\| X \| X \| X \| \|X \| X \|
214		\|AA12 \| X\| X \| X \| X \| \|X \| X \|
215		\|A017 \| X\| X \| X \| X \| X \| X\| \|
216		\|A018 \| X\| X \| X \| X \| X \| X\| \|
217		\|A019 \| X\| X \| X \| X \| X \| \| \|
218		\|A01A \| X\| X \| X \| X \| \|X \| \|
219		\|A01B \| X\| X \| X \| X \| \|X \| \|
220		\|A020 \| X\| X \| X \| X \| X \| \| \|
221		\|A021 \| X\| X\| X \| X \| X \| ?\| \|
222		\|A027 (NEW STANDARD) \| \| \| \| \| \|
223		\|A028 (NEW STANDARD) \| \| \| \| \| \|
224		\|A041 (FOR OSI ONLY) \| \| \| \| \| \|
225		\|A042 (FOR OSI ONLY) \| \| \| \| \| \|
226		\|AA19 \| X\| X \| X \| X \| X \| \| X \|
227		\|AA20 \| X\| X \| X \| X \| X \| \| X \|
228		\|AA13 \| X\| X \| X \| X \| X \| X\| X \|
229		\|AA14 \| X\| X \| X \| X \| X \| X\| X \|
230		\|AA23 \| X\| X \| X \| X \| X \| \| X \|
231		\|AA24 \| X\| X \| X \| X \| X \| \| X \|
232		\|AA26 \| X\| X \| X \| X \| X \| ?\| X \|
233		\|AA27 (NEW STD) \| \| \| \| \| \|
234		\|AA28 (NEW STD) \| \| \| \| \| \|
235		\|AA41 (FOR OSI ONLY) \| \| \| \| \| \|
236		\|AA42 (FOR OSI ONLY) \| \| \| \| \| \|
237		\|---------------------+---+---+---+---+---\|
238	186
	187	15TTF SOFTWARE SERIES (Twin Turret 4 Axis Lathe with FAPT)
	188	\|------+----+---------+---+---+---+---\|
	189	\|S/W \|STEP\| CRT \|I/O\|SER\|SER\|DNC\|
	190	\|SERIES\| \| \| \| \| \| \|
	191	\| \|1 2\| 9M 14 9C\|LNK\|SPN\|FB \|1 2\|
	192	+------+----+---------+---+---+---+---+
	193	\|A502 \|X \| X \| \| \| \| \|
	194	\|A512 \| X\| X \| X \| X \| \|X \|
	195	\|A520 \| X\| X \| X \| X \| X \| \|
	196	\|------+----+---------+---+---+---+---\|
239	197
240		Optional PCB A16B-1600-0280/02A
241		-------------------------------
242	198
243		\|---------------------------\|
244		\| 181 182 \|
245		\| \|
246		\| \|
247		\| \|
248		\| 1C1 1C2 \|
249		\| \|
250		\| \|
251		\| \|
252		\| 201 202 \|
253		\| \|
254		\| \|
255		\| \|
256		\| 241 242 \|
257		\| \|
258		\| \|
259		\| \|
260		\| 281 282 \|
261		\| \|
262		\| \|
263		\| \|
264		\| 2C1 2C2 \|
265		\| \|
266		\| \|
267		\| \|---------\| \|
268		\| \|---------\| \|
269		\| CNM1 \|
270		\|---------------------------\|
271		Notes:
272		The A16B-1600-0280/02A board contains only 12 DIP32 sockets and some logic and
273		bolts to the back of the BASE 1 board. The board extends the boot software memory
274		storage space if additional EPROMS are required. Not all sockets are populated.
275		Connector CNM1 joins with a 40 pin flat cable to the BASE 1 board connector CNM1
276		IC locations are not printed on this board. Only the ROM # is printed at each
277		socket location.
	199	15MA SOFTWARE SERIES (Mill With 3 Axes minimum XYZ)
	200	\|------+----+---------+---+---+---+---\|---\|
	201	\|S/W \|STEP\| CRT \|I/O\|SER\|SER\|DNC\|SUB\|
	202	\|SERIES\| \| \| \| \| \| \| \|
	203	\| \|1 2\| 9M 14 9C\|LNK\|SPN\|FB \|1 2\|CPU\|
	204	+------+----+---------+---+---+---+---+---\|
	205	\|A001 \|X \| X \| \| \| \| \| \|
	206	\|A002 \|X \| X \| \| \| \| \| \|
	207	\|A00A \|X \| X \| \| \| \| \| \|
	208	\|A00B \|X \| X \| \| \| \| \| \|
	209	\|AA01 \|X \| X \| \| \| \| \| X \|
	210	\|AA02 \|X \| X \| \| \| \| \| X \|
	211	\|A011 \| X\| X \| X \| X \| \|X \| \|
	212	\|A012 \| X\| X \| X \| X \| \|X \| \|
	213	\|AA11 \| X\| X \| X \| X \| \|X \| X \|
	214	\|AA12 \| X\| X \| X \| X \| \|X \| X \|
	215	\|A017 \| X\| X \| X \| X \| X \| X\| \|
	216	\|A018 \| X\| X \| X \| X \| X \| X\| \|
	217	\|A019 \| X\| X \| X \| X \| X \| \| \|
	218	\|A01A \| X\| X \| X \| X \| \|X \| \|
	219	\|A01B \| X\| X \| X \| X \| \|X \| \|
	220	\|A020 \| X\| X \| X \| X \| X \| \| \|
	221	\|A021 \| X\| X\| X \| X \| X \| ?\| \|
	222	\|A027 (NEW STANDARD) \| \| \| \| \| \|
	223	\|A028 (NEW STANDARD) \| \| \| \| \| \|
	224	\|A041 (FOR OSI ONLY) \| \| \| \| \| \|
	225	\|A042 (FOR OSI ONLY) \| \| \| \| \| \|
	226	\|AA19 \| X\| X \| X \| X \| X \| \| X \|
	227	\|AA20 \| X\| X \| X \| X \| X \| \| X \|
	228	\|AA13 \| X\| X \| X \| X \| X \| X\| X \|
	229	\|AA14 \| X\| X \| X \| X \| X \| X\| X \|
	230	\|AA23 \| X\| X \| X \| X \| X \| \| X \|
	231	\|AA24 \| X\| X \| X \| X \| X \| \| X \|
	232	\|AA26 \| X\| X \| X \| X \| X \| ?\| X \|
	233	\|AA27 (NEW STD) \| \| \| \| \| \|
	234	\|AA28 (NEW STD) \| \| \| \| \| \|
	235	\|AA41 (FOR OSI ONLY) \| \| \| \| \| \|
	236	\|AA42 (FOR OSI ONLY) \| \| \| \| \| \|
	237	\|---------------------+---+---+---+---+---\|
278	238
279		ROM IC Memory EPROM Used For
280		Label Location Location Type
281		---------------------------------------------------------------------------------
282		AB02281A N/A 281 27C1001 Boot Software Version AB02 Revision A
283		AB02282A N/A 282 27C1001
284		AB022C1A N/A 2C1 27C1001
285		AB022C2A N/A 2C2 27C1001
286	239
	240	Optional PCB A16B-1600-0280/02A
	241	-------------------------------
287	242
288		15A EPROM population and option type
289		----------------+---------+-------------------------------------------
290		PCB NAME \|ROM # \| Option Type (Basic, Option A1/A2/A3 etc)
291		----------------\|---------+-------------------------------------------
292		BASE 1 main \|081, 082 \| B
293		BASE 1 main \|0C1, 0C2 \| B
294		BASE 1 main \|101, 102 \| A1 if step1 software, B if step2 software
295		BASE 1 main \|141, 142 \| A2 (only used for foreign language option)
296		BASE 1 daughter \|181, 182 \| A3 (if used)
297		BASE 1 daughter \|1C1, 1C2 \| not used
298		BASE 1 daughter \|201, 202 \| not used
299		BASE 1 daughter \|241, 242 \| A6 (if used)
300		BASE 1 daughter \|281, 282 \| B when subcpu used
301		BASE 1 daughter \|2C1, 2C2 \| B when subcpu used
302		--------------------------+-------------------------------------------
303		Note: 2 MEG DRAM is required on BASE2 PCB when A3 or A6 is used
304
	243	\|---------------------------\|
	244	\| 181 182 \|
	245	\| \|
	246	\| \|
	247	\| \|
	248	\| 1C1 1C2 \|
	249	\| \|
	250	\| \|
	251	\| \|
	252	\| 201 202 \|
	253	\| \|
	254	\| \|
	255	\| \|
	256	\| 241 242 \|
	257	\| \|
	258	\| \|
	259	\| \|
	260	\| 281 282 \|
	261	\| \|
	262	\| \|
	263	\| \|
	264	\| 2C1 2C2 \|
	265	\| \|
	266	\| \|
	267	\| \|---------\| \|
	268	\| \|---------\| \|
	269	\| CNM1 \|
	270	\|---------------------------\|
	271	Notes:
	272	The A16B-1600-0280/02A board contains only 12 DIP32 sockets and some logic and
	273	bolts to the back of the BASE 1 board. The board extends the boot software memory
	274	storage space if additional EPROMS are required. Not all sockets are populated.
	275	Connector CNM1 joins with a 40 pin flat cable to the BASE 1 board connector CNM1
	276	IC locations are not printed on this board. Only the ROM # is printed at each
	277	socket location.
	278
	279	ROM IC Memory EPROM Used For
	280	Label Location Location Type
	281	---------------------------------------------------------------------------------
	282	AB02281A N/A 281 27C1001 Boot Software Version AB02 Revision A
	283	AB02282A N/A 282 27C1001
	284	AB022C1A N/A 2C1 27C1001
	285	AB022C2A N/A 2C2 27C1001
	286
	287
	288	15A EPROM population and option type
	289	----------------+---------+-------------------------------------------
	290	PCB NAME \|ROM # \| Option Type (Basic, Option A1/A2/A3 etc)
	291	----------------\|---------+-------------------------------------------
	292	BASE 1 main \|081, 082 \| B
	293	BASE 1 main \|0C1, 0C2 \| B
	294	BASE 1 main \|101, 102 \| A1 if step1 software, B if step2 software
	295	BASE 1 main \|141, 142 \| A2 (only used for foreign language option)
	296	BASE 1 daughter \|181, 182 \| A3 (if used)
	297	BASE 1 daughter \|1C1, 1C2 \| not used
	298	BASE 1 daughter \|201, 202 \| not used
	299	BASE 1 daughter \|241, 242 \| A6 (if used)
	300	BASE 1 daughter \|281, 282 \| B when subcpu used
	301	BASE 1 daughter \|2C1, 2C2 \| B when subcpu used
	302	--------------------------+-------------------------------------------
	303	Note: 2 MEG DRAM is required on BASE2 PCB when A3 or A6 is used
	304
305	305	****************************************************************************/
306	306
307	307	#include "emu.h"
r29404	r29405
313	313	public:
314	314	fanucs15_state(const machine_config &mconfig, device_type type, const char *tag)
315	315	: driver_device(mconfig, type, tag)
316		, m_maincpu(*this, "maincpu") // main 68020
317		, m_pmccpu(*this, "pmccpu") // sub 68000-12
318		, m_gfxcpu(*this, "gfxcpu") // gfx 68000-10
319		, m_convcpu(*this, "convcpu") // conversational 80286-8
	316	, m_maincpu(*this, "maincpu") // main 68020
	317	, m_pmccpu(*this, "pmccpu") // sub 68000-12
	318	, m_gfxcpu(*this, "gfxcpu") // gfx 68000-10
	319	, m_convcpu(*this, "convcpu") // conversational 80286-8
320	320	{ }
321	321
322	322	required_device<m68020_device> m_maincpu;
r29404	r29405
330	330
331	331	static ADDRESS_MAP_START(maincpu_mem, AS_PROGRAM, 32, fanucs15_state)
332	332	AM_RANGE(0x00000000, 0x0017ffff) AM_ROM AM_REGION("base1b", 0)
333		AM_RANGE(0x000f8000, 0x000fffff) AM_RAM // filled with 0x96 on boot
334		AM_RANGE(0xffff0000, 0xffffffff) AM_RAM // initial stack
	333	AM_RANGE(0x000f8000, 0x000fffff) AM_RAM // filled with 0x96 on boot
	334	AM_RANGE(0xffff0000, 0xffffffff) AM_RAM // initial stack
335	335	ADDRESS_MAP_END
336	336
337	337	static ADDRESS_MAP_START(pmccpu_mem, AS_PROGRAM, 16, fanucs15_state)
r29404	r29405
369	369	MCFG_CPU_PROGRAM_MAP(pmccpu_mem)
370	370	MCFG_DEVICE_DISABLE()
371	371
372		MCFG_CPU_ADD("gfxcpu", M68000, XTAL_10MHz) // wants bit 15 of 70500 to be set
	372	MCFG_CPU_ADD("gfxcpu", M68000, XTAL_10MHz) // wants bit 15 of 70500 to be set
373	373	MCFG_CPU_PROGRAM_MAP(gfxcpu_mem)
374	374	MCFG_DEVICE_DISABLE()
375	375
376		MCFG_CPU_ADD("convcpu", I80286, XTAL_8MHz) // wants 70500 to return 0x8000 (same as what gfxcpu looks for, basically)
	376	MCFG_CPU_ADD("convcpu", I80286, XTAL_8MHz) // wants 70500 to return 0x8000 (same as what gfxcpu looks for, basically)
377	377	MCFG_CPU_PROGRAM_MAP(convcpu_mem)
378	378	MACHINE_CONFIG_END
379	379
380	380	/* ROM definition */
381		ROM_START( fanucs15 )
382		ROM_REGION16_BE( 0x50000, "base1a", 0 ) // 68000 sub CPU code and data on base 1 board (verified)
383		ROM_LOAD16_BYTE( "4040_001e_001.23m", 0x000001, 0x020000, CRC(2e12109f) SHA1(83ed846d3d59ab0d81b2e2e2231d1a444e462590) )
384		ROM_LOAD16_BYTE( "4040_002e_002.27m", 0x000000, 0x020000, CRC(a5469692) SHA1(31c44edb36fb69d3d418a97e32e4a2769d1ec9e7) )
	381	ROM_START( fanucs15 )
	382	ROM_REGION16_BE( 0x50000, "base1a", 0 ) // 68000 sub CPU code and data on base 1 board (verified)
	383	ROM_LOAD16_BYTE( "4040_001e_001.23m", 0x000001, 0x020000, CRC(2e12109f) SHA1(83ed846d3d59ab0d81b2e2e2231d1a444e462590) )
	384	ROM_LOAD16_BYTE( "4040_002e_002.27m", 0x000000, 0x020000, CRC(a5469692) SHA1(31c44edb36fb69d3d418a97e32e4a2769d1ec9e7) )
385	385	ROM_LOAD16_BYTE( "9030_001e_381.18j", 0x040001, 0x008000, CRC(9f10a022) SHA1(dc4a242f7611143cc2d9564993fd5fa52f0ac13a) )
386	386
387		ROM_REGION32_BE( 0x180000, "base1b", 0 ) // 68020 main CPU code and data on base 1 board (verified)
388		ROM_LOAD16_BYTE( "ab02_081a_081.23e", 0x000001, 0x020000, CRC(5328b023) SHA1(661f2908f3287f7cd2b215cd29962f2789f7d99a) )
389		ROM_LOAD16_BYTE( "ab02_082a_082.27e", 0x000000, 0x020000, CRC(ad37740f) SHA1(e65cc0a8b4e515fcf5fcefde99e95d100d310018) )
390		ROM_LOAD16_BYTE( "ab02_0c1a_0c1.23f", 0x040001, 0x020000, CRC(62566569) SHA1(dd85b6e7875d996759b833552b00e1b3a0e3696b) )
391		ROM_LOAD16_BYTE( "ab02_0c2a_0c2.27f", 0x040000, 0x020000, CRC(a4ade1fe) SHA1(44ef5358b34d3538fb061f235b8a14bac6b5faa8) )
392		ROM_LOAD16_BYTE( "ab02_101a_101.23h", 0x080001, 0x020000, CRC(96f5d00e) SHA1(f5de3621df536435d27a0aac1c9d25e69601bd40) )
393		ROM_LOAD16_BYTE( "ab02_102a_102.27h", 0x080000, 0x020000, CRC(e23a5414) SHA1(f6aff51dfd6d976b7cd33399c7aa3d06c7c06919) )
394		ROM_LOAD16_BYTE( "ab02_141a_141.23k", 0x0c0001, 0x020000, CRC(3ceb6809) SHA1(7e37b18847b35f81c08b7b2ab62e99fa3a737c32) )
	387	ROM_REGION32_BE( 0x180000, "base1b", 0 ) // 68020 main CPU code and data on base 1 board (verified)
	388	ROM_LOAD16_BYTE( "ab02_081a_081.23e", 0x000001, 0x020000, CRC(5328b023) SHA1(661f2908f3287f7cd2b215cd29962f2789f7d99a) )
	389	ROM_LOAD16_BYTE( "ab02_082a_082.27e", 0x000000, 0x020000, CRC(ad37740f) SHA1(e65cc0a8b4e515fcf5fcefde99e95d100d310018) )
	390	ROM_LOAD16_BYTE( "ab02_0c1a_0c1.23f", 0x040001, 0x020000, CRC(62566569) SHA1(dd85b6e7875d996759b833552b00e1b3a0e3696b) )
	391	ROM_LOAD16_BYTE( "ab02_0c2a_0c2.27f", 0x040000, 0x020000, CRC(a4ade1fe) SHA1(44ef5358b34d3538fb061f235b8a14bac6b5faa8) )
	392	ROM_LOAD16_BYTE( "ab02_101a_101.23h", 0x080001, 0x020000, CRC(96f5d00e) SHA1(f5de3621df536435d27a0aac1c9d25e69601bd40) )
	393	ROM_LOAD16_BYTE( "ab02_102a_102.27h", 0x080000, 0x020000, CRC(e23a5414) SHA1(f6aff51dfd6d976b7cd33399c7aa3d06c7c06919) )
	394	ROM_LOAD16_BYTE( "ab02_141a_141.23k", 0x0c0001, 0x020000, CRC(3ceb6809) SHA1(7e37b18847b35f81c08b7b2ab62e99fa3a737c32) )
395	395	ROM_LOAD16_BYTE( "ab02_142a_142.27k", 0x0c0000, 0x020000, CRC(1d8a4d7d) SHA1(580322e2927742bbcbf0bb2757730e2817b320e1) )
396	396	// this appears to be a different version of the 081a/0c1a ROM program. it's definitely for a 68020 (32-bit pointers everywhere)
397	397	ROM_LOAD16_BYTE( "ab02_281a_281.8a", 0x100001, 0x020000, CRC(cec79742) SHA1(1233ff920d607206a80c8d187745e3d657a8635d) )
398		ROM_LOAD16_BYTE( "ab02_282a_282.8d", 0x100000, 0x020000, CRC(63eacc0e) SHA1(1f25b99280112c720d778219b4610f556f33a7f1) )
399		ROM_LOAD16_BYTE( "ab02_2c1a_2c1.10a", 0x140001, 0x020000, CRC(66eb74dd) SHA1(f256763cb15b4524c09bd09b88df46a1498846ef) )
400		ROM_LOAD16_BYTE( "ab02_2c2a_2c2.10d", 0x140000, 0x020000, CRC(6edf4ff3) SHA1(9cbf7c6555cc27def3b580f5a7b0ff580984206d) )
	398	ROM_LOAD16_BYTE( "ab02_282a_282.8d", 0x100000, 0x020000, CRC(63eacc0e) SHA1(1f25b99280112c720d778219b4610f556f33a7f1) )
	399	ROM_LOAD16_BYTE( "ab02_2c1a_2c1.10a", 0x140001, 0x020000, CRC(66eb74dd) SHA1(f256763cb15b4524c09bd09b88df46a1498846ef) )
	400	ROM_LOAD16_BYTE( "ab02_2c2a_2c2.10d", 0x140000, 0x020000, CRC(6edf4ff3) SHA1(9cbf7c6555cc27def3b580f5a7b0ff580984206d) )
401	401
402		ROM_REGION16_LE( 0x80000, "conversational", 0 ) // 80286 ROMs, 5a00 for Mill
403		ROM_LOAD16_BYTE( "5a00_041b.041", 0x000000, 0x020000, CRC(bf22c0a3) SHA1(56ab70bfd5794cb4db1d87c8becf7af522687564) )
404		ROM_LOAD16_BYTE( "5a00_042b.042", 0x000001, 0x020000, CRC(7abc9d6b) SHA1(5cb6ad08ce93aa99391d1ce46ac8db8ba2e0f94a) )
405		ROM_LOAD16_BYTE( "5a00_001b.001", 0x040000, 0x020000, CRC(cd2a2839) SHA1(bc20fd9ae9d071e1df835244aea85648d1bd1dbc) )
406		ROM_LOAD16_BYTE( "5a00_002b.002", 0x040001, 0x020000, CRC(d9ebbb4a) SHA1(9c3d96e9b88848472210beacdf9d300ddd42d16e) )
	402	ROM_REGION16_LE( 0x80000, "conversational", 0 ) // 80286 ROMs, 5a00 for Mill
	403	ROM_LOAD16_BYTE( "5a00_041b.041", 0x000000, 0x020000, CRC(bf22c0a3) SHA1(56ab70bfd5794cb4db1d87c8becf7af522687564) )
	404	ROM_LOAD16_BYTE( "5a00_042b.042", 0x000001, 0x020000, CRC(7abc9d6b) SHA1(5cb6ad08ce93aa99391d1ce46ac8db8ba2e0f94a) )
	405	ROM_LOAD16_BYTE( "5a00_001b.001", 0x040000, 0x020000, CRC(cd2a2839) SHA1(bc20fd9ae9d071e1df835244aea85648d1bd1dbc) )
	406	ROM_LOAD16_BYTE( "5a00_002b.002", 0x040001, 0x020000, CRC(d9ebbb4a) SHA1(9c3d96e9b88848472210beacdf9d300ddd42d16e) )
407	407
408		ROM_REGION16_BE( 0x50000, "gfxboard", 0 ) // graphics board 68000 code/data. 600a for lathe, 600b for mill, 6082 common to both
409		ROM_LOAD16_BYTE( "600b_001d_low.3l", 0x000001, 0x010000, CRC(50566c5c) SHA1(966c8d90d09a9c50c5dedebe9c67f1755846b234) )
410		ROM_LOAD16_BYTE( "600b_002d_high.3j", 0x000000, 0x010000, CRC(304e1ecb) SHA1(1e4b149b306550750fc03bd80bd399f239f68657) )
411		ROM_LOAD16_BYTE( "600a_001c.bin", 0x020001, 0x010000, CRC(63d9fc2f) SHA1(280e825ba7b79e7c38282a4f4b762d2219fd873b) )
412		ROM_LOAD16_BYTE( "600a_002c.bin", 0x020000, 0x010000, CRC(4d78e702) SHA1(a89bd07dc1ae030bdee5a541777825eaadbc2307) )
	408	ROM_REGION16_BE( 0x50000, "gfxboard", 0 ) // graphics board 68000 code/data. 600a for lathe, 600b for mill, 6082 common to both
	409	ROM_LOAD16_BYTE( "600b_001d_low.3l", 0x000001, 0x010000, CRC(50566c5c) SHA1(966c8d90d09a9c50c5dedebe9c67f1755846b234) )
	410	ROM_LOAD16_BYTE( "600b_002d_high.3j", 0x000000, 0x010000, CRC(304e1ecb) SHA1(1e4b149b306550750fc03bd80bd399f239f68657) )
	411	ROM_LOAD16_BYTE( "600a_001c.bin", 0x020001, 0x010000, CRC(63d9fc2f) SHA1(280e825ba7b79e7c38282a4f4b762d2219fd873b) )
	412	ROM_LOAD16_BYTE( "600a_002c.bin", 0x020000, 0x010000, CRC(4d78e702) SHA1(a89bd07dc1ae030bdee5a541777825eaadbc2307) )
413	413	// font or tilemap data?
414		ROM_LOAD( "6082_001a_cg.12b", 0x040000, 0x010000, CRC(f3d10cf9) SHA1(bc5bc88dcb5f347e1442aa4a0897747958a53413) )
	414	ROM_LOAD( "6082_001a_cg.12b", 0x040000, 0x010000, CRC(f3d10cf9) SHA1(bc5bc88dcb5f347e1442aa4a0897747958a53413) )
415	415
416		ROM_REGION16_BE( 0x40000, "cassette", 0 ) // "PMC Cassette C", ROM cartridge that plugs into the Base 1 board
417		ROM_LOAD16_BYTE( "pmc_high.a2", 0x000000, 0x020000, CRC(7b8f9a96) SHA1(08d828b612c45bb3f2f7a56df418cd8e34731bf4) )
418		ROM_LOAD16_BYTE( "pmc_low.a1", 0x000001, 0x020000, CRC(3ab261f8) SHA1(20b7eef96deb91a3a867f9ac4165b0c188fbcff3) )
	416	ROM_REGION16_BE( 0x40000, "cassette", 0 ) // "PMC Cassette C", ROM cartridge that plugs into the Base 1 board
	417	ROM_LOAD16_BYTE( "pmc_high.a2", 0x000000, 0x020000, CRC(7b8f9a96) SHA1(08d828b612c45bb3f2f7a56df418cd8e34731bf4) )
	418	ROM_LOAD16_BYTE( "pmc_low.a1", 0x000001, 0x020000, CRC(3ab261f8) SHA1(20b7eef96deb91a3a867f9ac4165b0c188fbcff3) )
419	419	ROM_END
420	420
421	421	/* Driver */
422	422	/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
423	423	COMP( 1990, fanucs15, 0, 0, fanucs15, fanucs15, driver_device, 0, "Fanuc", "System 15", GAME_NOT_WORKING \| GAME_NO_SOUND)
424
425

trunk/src/mess/drivers/phunsy.c
r29404	r29405
15	15	The tape must already be playing the leader when you press the Enter
16	16	key, or it errors immediately.
17	17
18		Rom banking (in U bank):
	18	Rom banking (in U bank):
19	19	0U: RAM
20	20	1U: MDCR program
21	21	2U: Disassembler
r29404	r29405
110	110	// U-bank
111	111	data >>= 4;
112	112
113		if (data < 4)
	113	if (data < 4)
114	114	membank("bankru")->set_entry(data);
115	115	}
116	116
r29404	r29405
354	354	MCFG_SCREEN_RAW_PARAMS(XTAL_8MHz, 480, 0, 64*6, 313, 0, 256)
355	355	MCFG_SCREEN_UPDATE_DRIVER(phunsy_state, screen_update)
356	356	MCFG_SCREEN_PALETTE("palette")
357
	357
358	358	MCFG_GFXDECODE_ADD("gfxdecode", "palette", phunsy)
359	359	MCFG_PALETTE_ADD("palette", 8)
360	360	MCFG_PALETTE_INIT_OWNER(phunsy_state, phunsy)

trunk/src/mess/drivers/coco12.c
r29404	r29405
301	301	MCFG_MC6847_ADD(VDG_TAG, MC6847_NTSC, XTAL_3_579545MHz, coco12_state::mc6847_config)
302	302	MCFG_MC6847_HSYNC_CALLBACK(WRITELINE(coco12_state, horizontal_sync))
303	303	MCFG_MC6847_FSYNC_CALLBACK(WRITELINE(coco12_state, field_sync))
304
	304
305	305	// sound hardware
306	306	MCFG_FRAGMENT_ADD( coco_sound )
307	307

trunk/src/mess/drivers/esqkt.c
r29404	r29405
18	18	0x280000-0x2801FF ES5510
19	19	0x300000-0x30000F 68681 DUART
20	20	0xFF0000-0xFFFFFF OS RAM
21
	21
22	22	Ensoniq KT-76
23		Ensoniq 1994
	23	Ensoniq 1994
24	24
25		This is a wavetable-based synth keyboard made by Ensoniq in 1994
	25	This is a wavetable-based synth keyboard made by Ensoniq in 1994
26	26
27		PCB Layout
28		----------
	27	PCB Layout
	28	----------
29	29
30		KT-76
31		\|---------------------------------------------\|
32		\|J12 J3 J11 J10 \|
33		\| LM393 LM358\|
34		\| 74HC4051\|
35		\|ADM691 \|
36		\| 62256 \|
37		\| \|
38		\|3V_BATTERY KT76_0590_LO.U5 ROM0 \|
39		\| \|
40		\| 68EC020 62256 OTTOR2 ROM1 \|
41		\| \|
42		\| KT76_690B_HI.U6 ROM2 \|
43		\| PAL1 \|
44		\| HP_6N138 \|
45		\| PAL2 OTTOR2 J6\|
46		\| 7407 \|
47		\| \|
48		\| D41464 D41464 \|
49		\| \|
50		\| SCN2681 D41464 D41464 \|
51		\| 137000402 \|
52		\| \|
53		\| 18.432MHz \|
54		\| ESPR6 16MHz \|
55		\| POT \|
56		\| R1136-11 \|
57		\| \|
58		\| LM339 LM339 \|
59		\| J13 J5 J1 J2 J4 \|
60		\|---------------------------------------------\|
61		Notes:
62		J1 - connector for digital jacks
63		J2 - connector for keyboard
64		J3 - connector for LCD display
65		J4 - connector for keyboard
66		J5 - connector for power input
67		J6 - connector for wave expansion
68		J10 - connector for wheels/pressure
69		J11 - connector for memory card
70		J12 - connector for headphones
71		J13 - connector for analog jacks
72		68EC020 - Motorola MC68EC020FG16 CPU. Clock input 16MHz
73		1370000402 - Unknown PLCC44 IC stamped with the Ensoniq logo. Likely CPLD or gate array.
74		ESPR6 - Ensoniq ESPR6 (ES5510) sound chip
75		OTTOR2 - Ensoniq OTTOR2 (ES5506) sound chip
76		POT - ESP adjustment pot
77		KT76* - 27C2048/27C210 EPROM
78		ROM* - 2M x8-bit SOP44 mask ROM
79		R1136-11 - DIP40 IC manufactured by Rockwell - believed to be some type of MCU.
80		D41464 - NEC D41464 64k x4-bit DRAM
81		62256 - 32k x8-bit SRAM
82		SCN2681 - Philips SCN2681 Dual Universal Asynchronous Receiver/Transmitter (DUART)
83		HP_6N138 - HP/Agilent HP 6N138 Low Input Current High Gain Optocoupler
84		PAL1 - MMI PAL20L8ACN stamped 'KT-76 MMU 6A0A'. Printing is faint so 0 could be a B or a D.
85		PAL2 - MMI PAL20L8ACN stamped 'KT-76 BCU 73D6'
	30	KT-76
	31	\|---------------------------------------------\|
	32	\|J12 J3 J11 J10 \|
	33	\| LM393 LM358\|
	34	\| 74HC4051\|
	35	\|ADM691 \|
	36	\| 62256 \|
	37	\| \|
	38	\|3V_BATTERY KT76_0590_LO.U5 ROM0 \|
	39	\| \|
	40	\| 68EC020 62256 OTTOR2 ROM1 \|
	41	\| \|
	42	\| KT76_690B_HI.U6 ROM2 \|
	43	\| PAL1 \|
	44	\| HP_6N138 \|
	45	\| PAL2 OTTOR2 J6\|
	46	\| 7407 \|
	47	\| \|
	48	\| D41464 D41464 \|
	49	\| \|
	50	\| SCN2681 D41464 D41464 \|
	51	\| 137000402 \|
	52	\| \|
	53	\| 18.432MHz \|
	54	\| ESPR6 16MHz \|
	55	\| POT \|
	56	\| R1136-11 \|
	57	\| \|
	58	\| LM339 LM339 \|
	59	\| J13 J5 J1 J2 J4 \|
	60	\|---------------------------------------------\|
	61	Notes:
	62	J1 - connector for digital jacks
	63	J2 - connector for keyboard
	64	J3 - connector for LCD display
	65	J4 - connector for keyboard
	66	J5 - connector for power input
	67	J6 - connector for wave expansion
	68	J10 - connector for wheels/pressure
	69	J11 - connector for memory card
	70	J12 - connector for headphones
	71	J13 - connector for analog jacks
	72	68EC020 - Motorola MC68EC020FG16 CPU. Clock input 16MHz
	73	1370000402 - Unknown PLCC44 IC stamped with the Ensoniq logo. Likely CPLD or gate array.
	74	ESPR6 - Ensoniq ESPR6 (ES5510) sound chip
	75	OTTOR2 - Ensoniq OTTOR2 (ES5506) sound chip
	76	POT - ESP adjustment pot
	77	KT76* - 27C2048/27C210 EPROM
	78	ROM* - 2M x8-bit SOP44 mask ROM
	79	R1136-11 - DIP40 IC manufactured by Rockwell - believed to be some type of MCU.
	80	D41464 - NEC D41464 64k x4-bit DRAM
	81	62256 - 32k x8-bit SRAM
	82	SCN2681 - Philips SCN2681 Dual Universal Asynchronous Receiver/Transmitter (DUART)
	83	HP_6N138 - HP/Agilent HP 6N138 Low Input Current High Gain Optocoupler
	84	PAL1 - MMI PAL20L8ACN stamped 'KT-76 MMU 6A0A'. Printing is faint so 0 could be a B or a D.
	85	PAL2 - MMI PAL20L8ACN stamped 'KT-76 BCU 73D6'
86	86
87	87	***************************************************************************/
88	88
r29404	r29405
263	263	ROM_LOAD32_WORD( "kt76_162_hi.bin", 0x000002, 0x040000, CRC(de16d236) SHA1(c55fca86453e90e8c34a048bed45817063237370) )
264	264
265	265	ROM_REGION(0x400000, "waverom", ROMREGION_ERASE00)
266		ROM_LOAD16_BYTE( "1351000401_rom0.u103", 0x000001, 0x200000, CRC(425047af) SHA1(9680d1fc222b29ba24f0fbf6136982bee87a60ef) )
	266	ROM_LOAD16_BYTE( "1351000401_rom0.u103", 0x000001, 0x200000, CRC(425047af) SHA1(9680d1fc222b29ba24f0fbf6136982bee87a60ef) )
267	267
268	268	ROM_REGION(0x400000, "waverom2", ROMREGION_ERASE00)
269		ROM_LOAD16_BYTE( "1351000402_rom1.u102", 0x000001, 0x200000, CRC(64459185) SHA1(0fa20b16847fc02a384057fc3d385226eb3e7527) )
	269	ROM_LOAD16_BYTE( "1351000402_rom1.u102", 0x000001, 0x200000, CRC(64459185) SHA1(0fa20b16847fc02a384057fc3d385226eb3e7527) )
270	270
271	271	ROM_REGION(0x400000, "waverom3", ROMREGION_ERASE00)
272		ROM_LOAD16_BYTE( "1351000403_rom2.u104", 0x000001, 0x200000, CRC(c2aacc5d) SHA1(7fab518ba92ddb23cdc4dcb04751b26d25c298c0) )
	272	ROM_LOAD16_BYTE( "1351000403_rom2.u104", 0x000001, 0x200000, CRC(c2aacc5d) SHA1(7fab518ba92ddb23cdc4dcb04751b26d25c298c0) )
273	273
274	274	ROM_REGION(0x200000, "waverom4", ROMREGION_ERASE00)
275	275	ROM_END

trunk/src/mess/drivers/sgi_ip2.c
r29404	r29405
378	378	AM_RANGE(0x30800000, 0x30800003) AM_READWRITE8(sgi_ip2_m_but_r, sgi_ip2_m_but_w, 0xffffffff)
379	379	AM_RANGE(0x31000000, 0x31000003) AM_READWRITE16(sgi_ip2_m_quad_r, sgi_ip2_m_quad_w, 0xffffffff)
380	380	AM_RANGE(0x31800000, 0x31800003) AM_READ16(sgi_ip2_swtch_r, 0xffffffff)
381		AM_RANGE(0x32000000, 0x3200000f) AM_DEVREADWRITE8("duart68681a", mc68681_device, read, write, 0xffffffff)
382		AM_RANGE(0x32800000, 0x3280000f) AM_DEVREADWRITE8("duart68681b", mc68681_device, read, write, 0xffffffff)
	381	AM_RANGE(0x32000000, 0x3200000f) AM_DEVREADWRITE8("duart68681a", mc68681_device, read, write, 0xffffffff)
	382	AM_RANGE(0x32800000, 0x3280000f) AM_DEVREADWRITE8("duart68681b", mc68681_device, read, write, 0xffffffff)
383	383	AM_RANGE(0x33000000, 0x330007ff) AM_RAM
384	384	AM_RANGE(0x34000000, 0x34000003) AM_READWRITE8(sgi_ip2_clock_ctl_r, sgi_ip2_clock_ctl_w, 0xffffffff)
385	385	AM_RANGE(0x35000000, 0x35000003) AM_READWRITE8(sgi_ip2_clock_data_r, sgi_ip2_clock_data_w, 0xffffffff)
r29404	r29405
423	423	MCFG_CPU_PROGRAM_MAP(sgi_ip2_map)
424	424
425	425	MCFG_MC68681_ADD( "duart68681a", XTAL_3_6864MHz ) /* Y3 3.6864MHz Xtal ??? copy-over from dectalk */
426		MCFG_MC68681_IRQ_CALLBACK(WRITELINE(sgi_ip2_state, duarta_irq_handler))
	426	MCFG_MC68681_IRQ_CALLBACK(WRITELINE(sgi_ip2_state, duarta_irq_handler))
427	427	MCFG_MC68681_B_TX_CALLBACK(DEVWRITELINE("rs232", rs232_port_device, write_txd))
428	428
429	429	MCFG_MC68681_ADD( "duart68681b", XTAL_3_6864MHz ) /* Y3 3.6864MHz Xtal ??? copy-over from dectalk */
430		MCFG_MC68681_IRQ_CALLBACK(WRITELINE(sgi_ip2_state, duartb_irq_handler))
	430	MCFG_MC68681_IRQ_CALLBACK(WRITELINE(sgi_ip2_state, duartb_irq_handler))
431	431
432	432	MCFG_MC146818_ADD( "rtc", XTAL_4_194304Mhz )
433	433

trunk/src/mess/drivers/europc.c
r29404	r29405
32	32
33	33	DECLARE_READ8_MEMBER( europc_rtc_r );
34	34	DECLARE_WRITE8_MEMBER( europc_rtc_w );
35
	35
36	36	DECLARE_DRIVER_INIT(europc);
37	37
38	38	void europc_rtc_set_time();
r29404	r29405
47	47
48	48	void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
49	49	emu_timer* m_rtc_timer;
50
	50
51	51	enum
52	52	{
53	53	TIMER_RTC
r29404	r29405
345	345	m_rtc_timer = timer_alloc();
346	346	m_rtc_timer->adjust(attotime::zero, 0, attotime(1,0));
347	347	// europc_rtc_set_time();
348
	348
349	349	machine().device<nvram_device>("nvram")->set_base(m_rtc_data, sizeof(m_rtc_data));
350		m_aga = machine().device<isa8_aga_device>("aga:aga");
	350	m_aga = machine().device<isa8_aga_device>("aga:aga");
351	351
352	352	}
353	353
r29404	r29405
402	402	\ and ~ had to be swapped
403	403	i am not sure if keypad enter delivers the mf2 keycode
404	404	*/
405
	405
406	406	static INPUT_PORTS_START( europc )
407	407	PORT_START("DSW0") /* IN1 */
408	408
r29404	r29405
476	476	ADDRESS_MAP_END
477	477
478	478	static MACHINE_CONFIG_START( europc, europc_pc_state )
479		MCFG_CPU_ADD("maincpu", I8088, 4772720*2)
	479	MCFG_CPU_ADD("maincpu", I8088, 4772720*2)
480	480	MCFG_CPU_PROGRAM_MAP(europc_map)
481	481	MCFG_CPU_IO_MAP(europc_io)
482	482
483	483	MCFG_PCNOPPI_MOTHERBOARD_ADD("mb", "maincpu")
484
	484
485	485	MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", pc_isa8_cards, "aga", false)
486	486	MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", pc_isa8_cards, "lpt", false)
487	487	MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, "com", false)
488	488	MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", pc_isa8_cards, "fdc_xt", false)
489
	489
490	490	MCFG_PC_KEYB_ADD("pc_keyboard", DEVWRITELINE("mb:pic8259", pic8259_device, ir1_w))
491	491
492	492	MCFG_NVRAM_ADD_0FILL("nvram");
493
	493
494	494	/* internal ram */
495	495	MCFG_RAM_ADD(RAM_TAG)
496	496	MCFG_RAM_DEFAULT_SIZE("640K")
r29404	r29405
502	502	ROM_LOAD("50145", 0xf8000, 0x8000, CRC(1775a11d) SHA1(54430d4d0462860860397487c9c109e6f70db8e3)) // V2.07
503	503	ROM_END
504	504
505		COMP( 1988, europc, ibm5150, 0, europc, europc, europc_pc_state, europc, "Schneider Rdf. AG", "EURO PC", GAME_NOT_WORKING)
		No newline at end of file
	505	COMP( 1988, europc, ibm5150, 0, europc, europc, europc_pc_state, europc, "Schneider Rdf. AG", "EURO PC", GAME_NOT_WORKING)

trunk/src/mess/drivers/iq151.c
r29404	r29405
434	434	MCFG_SCREEN_SIZE(648, 328)
435	435	MCFG_SCREEN_VISIBLE_AREA(0, 328-1, 0, 328-1)
436	436	MCFG_SCREEN_PALETTE("palette")
437
	437
438	438	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
439	439
440	440	/* sound hardware */

trunk/src/mess/drivers/mirage.c
r29404	r29405
215	215	MCFG_ES5503_OUTPUT_CHANNELS(2)
216	216	MCFG_ES5503_IRQ_FUNC(WRITELINE(mirage_state, mirage_doc_irq))
217	217	MCFG_ES5503_ADC_FUNC(READ8(mirage_state, mirage_adc_read))
218
	218
219	219	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
220	220	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
221	221

trunk/src/mess/drivers/avigo.c
r29404	r29405
893	893	MCFG_SCREEN_SIZE(AVIGO_SCREEN_WIDTH, AVIGO_SCREEN_HEIGHT + AVIGO_PANEL_HEIGHT)
894	894	MCFG_SCREEN_VISIBLE_AREA(0, AVIGO_SCREEN_WIDTH-1, 0, AVIGO_SCREEN_HEIGHT + AVIGO_PANEL_HEIGHT -1)
895	895	MCFG_SCREEN_PALETTE("palette")
896
	896
897	897	MCFG_DEFAULT_LAYOUT(layout_avigo)
898	898
899	899	MCFG_GFXDECODE_ADD("gfxdecode", "palette", avigo)

trunk/src/mess/drivers/zrt80.c
r29404	r29405
60	60	required_device<mc6845_device> m_crtc;
61	61	required_device<ins8250_device> m_8250;
62	62	required_device<beep_device> m_beep;
63		public:
	63	public:
64	64	required_device<palette_device> m_palette;
65	65	};
66	66

trunk/src/mess/drivers/svmu.c
r29404	r29405
314	314	MCFG_SCREEN_VISIBLE_AREA(0, 48(PIXEL_SIZE + PIXEL_DISTANCE) - 1, 0, 32(PIXEL_SIZE + PIXEL_DISTANCE) - 1)
315	315	MCFG_SCREEN_UPDATE_DEVICE("maincpu", lc8670_cpu_device, screen_update)
316	316	MCFG_SCREEN_PALETTE("palette")
317
	317
318	318	MCFG_DEFAULT_LAYOUT(layout_svmu)
319	319	MCFG_PALETTE_ADD("palette", 2)
320	320	MCFG_PALETTE_INIT_OWNER(svmu_state, svmu)

trunk/src/mess/drivers/mz2500.c
r29404	r29405
71	71	m_pit(*this, "pit"),
72	72	m_beeper(*this, "beeper"),
73	73	m_gfxdecode(*this, "gfxdecode"),
74		m_palette(*this, "palette")
	74	m_palette(*this, "palette")
75	75	{ }
76	76
77	77	required_device<cpu_device> m_maincpu;
r29404	r29405
2127	2127	MCFG_Z80SIO0_ADD( "z80sio", 6000000, mz2500_sio_intf )
2128	2128	MCFG_DEVICE_ADD(RP5C15_TAG, RP5C15, XTAL_32_768kHz)
2129	2129	MCFG_RP5C15_OUT_ALARM_CB(WRITELINE(mz2500_state, mz2500_rtc_alarm_irq))
2130
	2130
2131	2131	MCFG_DEVICE_ADD("pit", PIT8253, 0)
2132	2132	MCFG_PIT8253_CLK0(31250)
2133	2133	MCFG_PIT8253_OUT0_HANDLER(WRITELINE(mz2500_state, pit8253_clk0_irq))

trunk/src/mess/drivers/m20.c
r29404	r29405
65	65	m_floppy0(*this, "fd1797:0:5dd"),
66	66	m_floppy1(*this, "fd1797:1:5dd"),
67	67	m_p_videoram(*this, "p_videoram"),
68		m_palette(*this, "palette")
	68	m_palette(*this, "palette")
69	69	{
70	70	}
71	71
r29404	r29405
163	163	m_kbrecv_data = (m_kbrecv_data >> 1) \| (state ? (1<<10) : 0);
164	164	if (m_kbrecv_bitcount == 11) {
165	165	data = (m_kbrecv_data >> 1) & 0xff;
166		// printf ("0x%02X received by keyboard\n", data);
	166	// printf ("0x%02X received by keyboard\n", data);
167	167	switch (data) {
168	168	case 0x03: m_kbdi8251->receive_character(2); printf ("sending 2 back from kb...\n"); break;
169	169	case 0x0a: break;
r29404	r29405
173	173	m_kbrecv_in_progress = 0;
174	174	}
175	175	}
176		else
	176	else
177	177	{
178	178	if (state == 0)
179	179	{
180		m_kbrecv_in_progress = 1;
	180	m_kbrecv_in_progress = 1;
181	181	m_kbrecv_bitcount = 1;
182	182	m_kbrecv_data = state ? (1<<10) : 0;
183	183	}
r29404	r29405
388	388
389	389	void m20_state::install_memory()
390	390	{
391
392	391	m_memsize = m_ram->size();
393	392	UINT8 *memptr = m_ram->pointer();
394	393	address_space& pspace = m_maincpu->space(AS_PROGRAM);
r29404	r29405
811	810
812	811	void m20_state::machine_start()
813	812	{
814
815	813	install_memory();
816	814	}
817	815
r29404	r29405
937	935
938	936	/* Devices */
939	937	MCFG_FD1797x_ADD("fd1797", 1000000)
940		MCFG_WD_FDC_INTRQ_CALLBACK(DEVWRITELINE("i8259", pic8259_device, ir0_w))
	938	MCFG_WD_FDC_INTRQ_CALLBACK(DEVWRITELINE("i8259", pic8259_device, ir0_w))
941	939	MCFG_FLOPPY_DRIVE_ADD("fd1797:0", m20_floppies, "5dd", m20_state::floppy_formats)
942	940	MCFG_FLOPPY_DRIVE_ADD("fd1797:1", m20_floppies, "5dd", m20_state::floppy_formats)
943	941	MCFG_MC6845_ADD("crtc", MC6845, "screen", PIXEL_CLOCK/8, mc6845_intf) /* hand tuned to get ~50 fps */
r29404	r29405
991	989	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
992	990	COMP( 1981, m20, 0, 0, m20, m20, m20_state, m20, "Olivetti", "Olivetti L1 M20", GAME_NOT_WORKING \| GAME_NO_SOUND)
993	991	COMP( 1981, m40, m20, 0, m20, m20, m20_state, m20, "Olivetti", "Olivetti L1 M40", GAME_NOT_WORKING \| GAME_NO_SOUND)
994

trunk/src/mess/drivers/super80.c
r29404	r29405
697	697	MCFG_CPU_PROGRAM_MAP(super80m_map)
698	698
699	699	MCFG_GFXDECODE_MODIFY("gfxdecode", super80m)
700
	700
701	701	MCFG_PALETTE_MODIFY("palette")
702	702	MCFG_PALETTE_ENTRIES(16)
703	703	MCFG_PALETTE_INIT_OWNER(super80_state,super80m)
r29404	r29405
721	721	MCFG_SCREEN_SIZE(SUPER80V_SCREEN_WIDTH, SUPER80V_SCREEN_HEIGHT)
722	722	MCFG_SCREEN_VISIBLE_AREA(0, SUPER80V_SCREEN_WIDTH-1, 0, SUPER80V_SCREEN_HEIGHT-1)
723	723	MCFG_SCREEN_UPDATE_DRIVER(super80_state, screen_update_super80v)
724		MCFG_SCREEN_VBLANK_DRIVER(super80_state, screen_eof_super80m)
	724	MCFG_SCREEN_VBLANK_DRIVER(super80_state, screen_eof_super80m)
725	725
726	726	MCFG_PALETTE_ADD("palette", 16)
727	727	MCFG_PALETTE_INIT_OWNER(super80_state,super80m)

trunk/src/mess/drivers/tk80bs.c
r29404	r29405
38	38	m_maincpu(*this, "maincpu"),
39	39	m_ppi(*this, "ppi"),
40	40	m_gfxdecode(*this, "gfxdecode"),
41		m_palette(*this, "palette")
	41	m_palette(*this, "palette")
42	42	{
43	43	}
44	44
r29404	r29405
196	196	MCFG_SCREEN_VISIBLE_AREA(0, 256-1, 0, 128-1)
197	197	MCFG_SCREEN_UPDATE_DRIVER(tk80bs_state, screen_update_tk80bs)
198	198	MCFG_SCREEN_PALETTE("palette")
199
	199
200	200	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
201	201	MCFG_GFXDECODE_ADD("gfxdecode", "palette", tk80bs)
202	202

trunk/src/mess/drivers/multi8.c
r29404	r29405
674	674	MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 200-1)
675	675	MCFG_SCREEN_UPDATE_DRIVER(multi8_state, screen_update_multi8)
676	676	MCFG_SCREEN_PALETTE("palette")
677
	677
678	678	MCFG_PALETTE_ADD("palette", 8)
679	679	MCFG_PALETTE_INIT_OWNER(multi8_state, multi8)
680	680	MCFG_GFXDECODE_ADD("gfxdecode", "palette", multi8)

trunk/src/mess/drivers/esqmr.c
r29404	r29405
12	12	Memory map:
13	13
14	14	0x000000-0x0FFFFF OS ROM
15
	15
16	16	MR Rack
17		Ensoniq, 1995
	17	Ensoniq, 1995
18	18
19		This is a 64-voice expandable synth module made by Ensoniq in 1995.
20		It is shipped with 12MB of 16-bit 44.1kHz wave data and can be expanded
21		with up to 3 ENSONIQ EXP Series Wave Expansion Boards containing up to a
22		maximum of 84MB of additional wave data.
	19	This is a 64-voice expandable synth module made by Ensoniq in 1995.
	20	It is shipped with 12MB of 16-bit 44.1kHz wave data and can be expanded
	21	with up to 3 ENSONIQ EXP Series Wave Expansion Boards containing up to a
	22	maximum of 84MB of additional wave data.
23	23
24	24
25		PCB Layout
26		----------
	25	PCB Layout
	26	----------
27	27
28		PN: 4001028501 REV C
29		\|--------------------------------------------------------\|
30		\| J6 J7 J12 J13 J21 J23 J22\|
31		\| J5\|
32		\| 4565 4565 HP_6N138 \|
33		\| \|
34		\| BATTERY 7407 \|
35		\| 4565 \|
36		\| \|
37		\| OTTOR2 OTTOR2 \|
38		\|AD1861 \|
39		\|AD1861 \|
40		\|AD1861 \|
41		\|AD1861 \|--J3-----\| \|
42		\| HC04 \|EXPANSION\| \|
43		\| \|BOARD #3 \| \|
44		\| \| \| \|
45		\| 1370001501 \| \| \|
46		\| \| \| \|
47		\| \|--J8-----\| \|
48		\| ESP2 ROM2 \|
49		\| \|--J2-----\| \|
50		\| \|EXPANSION\| \|
51		\| ROM0 \|BOARD #2 \| \|
52		\| \| \| \|
53		\| D43256 IDT7130 \| \| \|
54		\| D43256 35MHz 16MHz ROM1 \| \| \|
55		\| D43256 J14 \|--J9-----\| \|
56		\| D43256 22.5792MHz ADM691\|
57		\| D43256 MC68340 \|--J1-----\| \|
58		\| D43256 \|EXPANSION\| \|
59		\| 6MHz \|BOARD #1 \| \|
60		\| EPROM_UP \| \| \|
61		\| MC68HC705C4A KM681000 \| \|
62		\|J4 EPROM_LO KM681000 \|J11\|
63		\| J19 J18 \|--J10----\| \|
64		\|--------------------------------------------------------\|
65		Notes:
66		J4/J18/J19 - Connectors to front panel buttons, LCD etc
67		J1/J10 - Connectors for expansion board #1
68		J2/J9 - Connectors for expansion board #2
69		J3/J8 - Connectors for expansion board #3
70		J11 - Memory card connector
71		J14 - JTAG connector
72		J6 - Main left/mono jack
73		J7 - Main right jack
74		J12 - Aux left/mono jack
75		J13 - Aux right jack
76		J21 - MIDI in connector
77		J23 - MIDI out connector
78		J22 - MIDI thru connector
79		J5 - Power input connector
80		1370001501 - Unknown TQFP144 IC stamped with the Ensoniq logo. Possibly CPLD?
81		ESP2 - Ensoniq ESP2 sound chip
82		OTTOR2 - Ensoniq OTTOR2 sound chip
83		ROM* - 4M x8-bit SOP44 mask ROM
84		D43256 - NEC D43256 32k x8-bit Static RAM
85		HP_6N138 - HP/Agilent HP 6N138 Low Input Current High Gain Optocoupler
86		4565 - JRC4565 Dual Operational Amplifier
87		AD1861 - Analog Devices AD1861 16-bit/18-bit PCM Audio DAC
88		MC68HC705C4A - Motorola MC68HC705C4A Microcontroller. Clock input is tied to the TQFP CPLD
89		MC68340 - Motorola MC68340PV16E 68000-compatible 32-bit processor with on-board peripherals. Clock input 6.000MHz
90		EPROM* - 27C4001 EPROM
91		IDT7130 - IDT7130 High Speed 1k x8-bit Dual Port Static RAM
92		KM681000 - Samsung KM681000 128k x8-bit Static RAM
93		ADM691 - Analog Devices ADM691 Microprocessor Supervisory Circuit with Automatic Battery Backup Switching
94
	28	PN: 4001028501 REV C
	29	\|--------------------------------------------------------\|
	30	\| J6 J7 J12 J13 J21 J23 J22\|
	31	\| J5\|
	32	\| 4565 4565 HP_6N138 \|
	33	\| \|
	34	\| BATTERY 7407 \|
	35	\| 4565 \|
	36	\| \|
	37	\| OTTOR2 OTTOR2 \|
	38	\|AD1861 \|
	39	\|AD1861 \|
	40	\|AD1861 \|
	41	\|AD1861 \|--J3-----\| \|
	42	\| HC04 \|EXPANSION\| \|
	43	\| \|BOARD #3 \| \|
	44	\| \| \| \|
	45	\| 1370001501 \| \| \|
	46	\| \| \| \|
	47	\| \|--J8-----\| \|
	48	\| ESP2 ROM2 \|
	49	\| \|--J2-----\| \|
	50	\| \|EXPANSION\| \|
	51	\| ROM0 \|BOARD #2 \| \|
	52	\| \| \| \|
	53	\| D43256 IDT7130 \| \| \|
	54	\| D43256 35MHz 16MHz ROM1 \| \| \|
	55	\| D43256 J14 \|--J9-----\| \|
	56	\| D43256 22.5792MHz ADM691\|
	57	\| D43256 MC68340 \|--J1-----\| \|
	58	\| D43256 \|EXPANSION\| \|
	59	\| 6MHz \|BOARD #1 \| \|
	60	\| EPROM_UP \| \| \|
	61	\| MC68HC705C4A KM681000 \| \|
	62	\|J4 EPROM_LO KM681000 \|J11\|
	63	\| J19 J18 \|--J10----\| \|
	64	\|--------------------------------------------------------\|
	65	Notes:
	66	J4/J18/J19 - Connectors to front panel buttons, LCD etc
	67	J1/J10 - Connectors for expansion board #1
	68	J2/J9 - Connectors for expansion board #2
	69	J3/J8 - Connectors for expansion board #3
	70	J11 - Memory card connector
	71	J14 - JTAG connector
	72	J6 - Main left/mono jack
	73	J7 - Main right jack
	74	J12 - Aux left/mono jack
	75	J13 - Aux right jack
	76	J21 - MIDI in connector
	77	J23 - MIDI out connector
	78	J22 - MIDI thru connector
	79	J5 - Power input connector
	80	1370001501 - Unknown TQFP144 IC stamped with the Ensoniq logo. Possibly CPLD?
	81	ESP2 - Ensoniq ESP2 sound chip
	82	OTTOR2 - Ensoniq OTTOR2 sound chip
	83	ROM* - 4M x8-bit SOP44 mask ROM
	84	D43256 - NEC D43256 32k x8-bit Static RAM
	85	HP_6N138 - HP/Agilent HP 6N138 Low Input Current High Gain Optocoupler
	86	4565 - JRC4565 Dual Operational Amplifier
	87	AD1861 - Analog Devices AD1861 16-bit/18-bit PCM Audio DAC
	88	MC68HC705C4A - Motorola MC68HC705C4A Microcontroller. Clock input is tied to the TQFP CPLD
	89	MC68340 - Motorola MC68340PV16E 68000-compatible 32-bit processor with on-board peripherals. Clock input 6.000MHz
	90	EPROM* - 27C4001 EPROM
	91	IDT7130 - IDT7130 High Speed 1k x8-bit Dual Port Static RAM
	92	KM681000 - Samsung KM681000 128k x8-bit Static RAM
	93	ADM691 - Analog Devices ADM691 Microprocessor Supervisory Circuit with Automatic Battery Backup Switching
95	94
96		Additional notes from the manual:
97		---------------------------------
98	95
99		The MR-Rack can play special demonstration songs to give you an idea of how terrific it sounds.
	96	Additional notes from the manual:
	97	---------------------------------
100	98
101		To Play the MR-Rack Main Demo
102		1. Press the Audition button, and hold it down.
103		2. While still holding Audition, press the Save button.
104		3. Let go of both buttons.
	99	The MR-Rack can play special demonstration songs to give you an idea of how terrific it sounds.
105	100
106		In an unexpanded MR-Rack, the display shows:
	101	To Play the MR-Rack Main Demo
	102	1. Press the Audition button, and hold it down.
	103	2. While still holding Audition, press the Save button.
	104	3. Let go of both buttons.
107	105
108		Hit ENTER to Play:
109		MAINDEMO:MR Internal
	106	In an unexpanded MR-Rack, the display shows:
110	107
111		If you've installed any Expansion boards or a ROM card containing MAINDEMO-type
112		demonstration songs, your display will differ. Turn the Value knob counter-clockwise
113		until the display looks as it does above.
	108	Hit ENTER to Play:
	109	MAINDEMO:MR Internal
114	110
115		Note: When MR-Rack demos are being viewed or playing, MIDI In is disabled.
	111	If you've installed any Expansion boards or a ROM card containing MAINDEMO-type
	112	demonstration songs, your display will differ. Turn the Value knob counter-clockwise
	113	until the display looks as it does above.
116	114
117		4. Press Enter to play the demo.
118		5. Press Enter again to stop the demo.
119		6. When you're done listening to the demo song, press Exit to return to normal MR-Rack
	115	Note: When MR-Rack demos are being viewed or playing, MIDI In is disabled.
120	116
	117	4. Press Enter to play the demo.
	118	5. Press Enter again to stop the demo.
	119	6. When you're done listening to the demo song, press Exit to return to normal MR-Rack
121	120
122		The Version Number of Your MR-Rack Operating System:
123		You can easily find out what operating system (or O.S.) your MR-Rack is currently using.
124		To Find the Operating System:
125		1. Press the Save button and hold it down.
126		2. While still holding the Save button, press the System button.
127		The display briefly shows your current Operating System:
128	121
129		ENSONIQ MR-RACK
130		O.S. Version: #.##
	122	The Version Number of Your MR-Rack Operating System:
	123	You can easily find out what operating system (or O.S.) your MR-Rack is currently using.
	124	To Find the Operating System:
	125	1. Press the Save button and hold it down.
	126	2. While still holding the Save button, press the System button.
	127	The display briefly shows your current Operating System:
131	128
	129	ENSONIQ MR-RACK
	130	O.S. Version: #.##
132	131
133	132
134		ENSONIQ EXP Series Wave Expansion Boards
135		----------------------------------------
136	133
137		These are small plug-in boards containing a 256k x8-bit EPROM (27C020) and from 1 to 6
138		SOP44 mask ROMs. These add additional digital sound waves. These can be used with the MR
139		Rack, the full-size MR Keyboards and a few other models.
	134	ENSONIQ EXP Series Wave Expansion Boards
	135	----------------------------------------
140	136
141		PCB Layout
142		----------
	137	These are small plug-in boards containing a 256k x8-bit EPROM (27C020) and from 1 to 6
	138	SOP44 mask ROMs. These add additional digital sound waves. These can be used with the MR
	139	Rack, the full-size MR Keyboards and a few other models.
143	140
144		PN: 4001033401 REV B
145		\|------------------\|
146		\| \|
147		\| U6 U7 \|
148		\|- \|
149		\|\| \|
150		\|\| U1 \|
151		\|\| U2 -\|
152		\|\| \|\|
153		\|\| \|\|
154		\|\| U3 \|\|
155		\|\| \|\|
156		\|\| U8 \|\|
157		\|\| U4 \|\|
158		\|\| \|\|
159		\|\| \|\|
160		\|\| U5 \|\|
161		\|- -\|
162		\|------------------\|
163		Notes:
164		U1 - AC138 logic chip
165		U2 to U7 - 4M x 8-bit or 2M x 8-bit SOP44 mask ROM
166		U8 - 27C020 EPROM
	141	PCB Layout
	142	----------
167	143
168		The EXP boards dumped so far are....
	144	PN: 4001033401 REV B
	145	\|------------------\|
	146	\| \|
	147	\| U6 U7 \|
	148	\|- \|
	149	\|\| \|
	150	\|\| U1 \|
	151	\|\| U2 -\|
	152	\|\| \|\|
	153	\|\| \|\|
	154	\|\| U3 \|\|
	155	\|\| \|\|
	156	\|\| U8 \|\|
	157	\|\| U4 \|\|
	158	\|\| \|\|
	159	\|\| \|\|
	160	\|\| U5 \|\|
	161	\|- -\|
	162	\|------------------\|
	163	Notes:
	164	U1 - AC138 logic chip
	165	U2 to U7 - 4M x 8-bit or 2M x 8-bit SOP44 mask ROM
	166	U8 - 27C020 EPROM
169	167
170		MROM # of
171		Name Version Size MROMs
172		-----------------------------------
173		Piano V1.00 4M 4 (multisampled pianos, aka "The Perfect Piano")
174		The Real World V1.01 4M 6 (non-Western percusson and other "world music" sounds)
175		Drum V1.00 2M 1 (additional drum kits that are built in to the MR keyboards)
	168	The EXP boards dumped so far are....
176	169
	170	MROM # of
	171	Name Version Size MROMs
	172	-----------------------------------
	173	Piano V1.00 4M 4 (multisampled pianos, aka "The Perfect Piano")
	174	The Real World V1.01 4M 6 (non-Western percusson and other "world music" sounds)
	175	Drum V1.00 2M 1 (additional drum kits that are built in to the MR keyboards)
177	176
178		Additional notes from the manual:
179		---------------------------------
180	177
181		The MR-Rack provides three displays which can identify any EXP Wave Expansion boards
182		you have installed.
	178	Additional notes from the manual:
	179	---------------------------------
183	180
184		To Identify an Installed Expansion Board
185		1. Press the System button.
186		2. Turn the Parameter knob until the display shows:
	181	The MR-Rack provides three displays which can identify any EXP Wave Expansion boards
	182	you have installed.
187	183
188		System parameters:
189		WaveEXP1:xxxxxxxxxxx
	184	To Identify an Installed Expansion Board
	185	1. Press the System button.
	186	2. Turn the Parameter knob until the display shows:
190	187
191		When an Expansion Board is installed, this read-only display will show the name of the
192		Expansion Board located in the first slot.
	188	System parameters:
	189	WaveEXP1:xxxxxxxxxxx
193	190
194		3. Turning the Parameter knob two more times will reveal two more displays which show
195		the names of the Expansion Boards in Wave EXP Slots 2 and 3 (if they're installed).
196		If there are no Expansion Boards installed, the display will show "WaveEXP1= EMPTY."
197
	191	When an Expansion Board is installed, this read-only display will show the name of the
	192	Expansion Board located in the first slot.
	193
	194	3. Turning the Parameter knob two more times will reveal two more displays which show
	195	the names of the Expansion Boards in Wave EXP Slots 2 and 3 (if they're installed).
	196	If there are no Expansion Boards installed, the display will show "WaveEXP1= EMPTY."
	197
198	198	***************************************************************************/
199	199
200	200	#include "emu.h"
r29404	r29405
220	220	public:
221	221	DECLARE_DRIVER_INIT(mr);
222	222	DECLARE_WRITE_LINE_MEMBER(esq5506_otto_irq);
223		DECLARE_READ16_MEMBER(esq5506_read_adc);
	223	DECLARE_READ16_MEMBER(esq5506_read_adc);
224	224	};
225	225
226	226	void esqmr_state::machine_reset()
r29404	r29405
302	302	ROM_START( mrrack )
303	303	// 68340 main MCU
304	304	ROM_REGION(0x100000, "maincpu", 0)
305		ROM_LOAD16_BYTE( "mr_r_ec51_lo_1.50.u36", 0x000001, 0x080000, CRC(b29988a1) SHA1(986c2def11de27fa2b9be55ac32f7fec0c414bca) )
306		ROM_LOAD16_BYTE( "mr_r_9dac_up_1.50.u35", 0x000000, 0x080000, CRC(71511692) SHA1(54744f16f1db1ac5abb2f70b6e04aebf1e0e029d) )
	305	ROM_LOAD16_BYTE( "mr_r_ec51_lo_1.50.u36", 0x000001, 0x080000, CRC(b29988a1) SHA1(986c2def11de27fa2b9be55ac32f7fec0c414bca) )
	306	ROM_LOAD16_BYTE( "mr_r_9dac_up_1.50.u35", 0x000000, 0x080000, CRC(71511692) SHA1(54744f16f1db1ac5abb2f70b6e04aebf1e0e029d) )
307	307
308	308	// 68705 display/front panel MCU
309	309	ROM_REGION(0x2000, "mcu", 0)
310		ROM_LOAD( "68hc705.u40", 0x000000, 0x002000, CRC(7b0291a7) SHA1(c92c19ce9289b7b21dbc915475cdff8930e3c677) )
	310	ROM_LOAD( "68hc705.u40", 0x000000, 0x002000, CRC(7b0291a7) SHA1(c92c19ce9289b7b21dbc915475cdff8930e3c677) )
311	311
312	312	ROM_REGION(0x400000, "waverom", ROMREGION_ERASE00)
313		ROM_LOAD( "1351000901_h-rom0.u5", 0x000000, 0x400000, CRC(89654b42) SHA1(4bdffd8060eb20cdb01f6178222aeb32fdbfd703) )
	313	ROM_LOAD( "1351000901_h-rom0.u5", 0x000000, 0x400000, CRC(89654b42) SHA1(4bdffd8060eb20cdb01f6178222aeb32fdbfd703) )
314	314
315	315	ROM_REGION(0x400000, "waverom2", ROMREGION_ERASE00)
316		ROM_LOAD( "1351000902_h-rom1.u23", 0x000000, 0x400000, CRC(4a19e517) SHA1(e819f1e0b50c4911c4855ad95ed505998a2bbe86) )
	316	ROM_LOAD( "1351000902_h-rom1.u23", 0x000000, 0x400000, CRC(4a19e517) SHA1(e819f1e0b50c4911c4855ad95ed505998a2bbe86) )
317	317
318	318	ROM_REGION(0x400000, "waverom3", ROMREGION_ERASE00)
319		ROM_LOAD( "1351000903_h-rom2.u24", 0x000000, 0x400000, CRC(c9ab1214) SHA1(92f48b068bbe49eacbffd03e428599e3ab21b8ec) )
	319	ROM_LOAD( "1351000903_h-rom2.u24", 0x000000, 0x400000, CRC(c9ab1214) SHA1(92f48b068bbe49eacbffd03e428599e3ab21b8ec) )
320	320
321	321	ROM_REGION(0x200000, "waverom4", ROMREGION_ERASE00)
322	322	ROM_END

trunk/src/mess/drivers/psion.c
r29404	r29405
388	388	m_nvram2->set_base(m_ram, m_ram.bytes());
389	389	if (m_nvram3)
390	390	m_nvram3->set_base(m_paged_ram, m_ram_bank_count * 0x4000);
391
	391
392	392	save_item(NAME(m_kb_counter));
393	393	save_item(NAME(m_enable_nmi));
394	394	save_item(NAME(m_tcsr_value));
r29404	r29405
467	467	MCFG_SCREEN_SIZE(616, 92)
468	468	MCFG_SCREEN_VISIBLE_AREA(0, 616-1, 0, 92-1)
469	469	MCFG_SCREEN_PALETTE("palette")
470
	470
471	471	MCFG_DEFAULT_LAYOUT(layout_lcd)
472	472	MCFG_PALETTE_ADD("palette", 2)
473	473	MCFG_PALETTE_INIT_OWNER(psion_state, psion)
r29404	r29405
481	481	MCFG_SOUND_ADD( "beeper", BEEP, 0 )
482	482	MCFG_SOUND_ROUTE( ALL_OUTPUTS, "mono", 1.00 )
483	483
484		MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram1", psion_state, nvram_init) // sys_regs
	484	MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram1", psion_state, nvram_init) // sys_regs
485	485	MCFG_NVRAM_ADD_0FILL("nvram2") // RAM
486	486
487	487	MCFG_TIMER_DRIVER_ADD_PERIODIC("nmi_timer", psion_state, nmi_timer, attotime::from_seconds(1))

trunk/src/mess/drivers/vtech1.c
r29404	r29405
923	923	static const mc6847_interface vtech1_mc6847_intf =
924	924	{
925	925	"screen",
926		DEVCB_DRIVER_MEMBER(vtech1_state,vtech1_mc6847_videoram_r),
	926	DEVCB_DRIVER_MEMBER(vtech1_state,vtech1_mc6847_videoram_r),
927	927
928	928	DEVCB_NULL, /* AG */
929	929	DEVCB_LINE_GND, /* GM2 */
r29404	r29405
963	963	/* video hardware */
964	964	MCFG_SCREEN_MC6847_PAL_ADD("screen", "mc6847")
965	965	MCFG_MC6847_ADD("mc6847", MC6847_PAL, XTAL_4_433619MHz, vtech1_mc6847_bw_intf)
966		MCFG_MC6847_FSYNC_CALLBACK(INPUTLINE("maincpu", 0))
	966	MCFG_MC6847_FSYNC_CALLBACK(INPUTLINE("maincpu", 0))
967	967
968	968	/* sound hardware */
969	969	MCFG_SPEAKER_STANDARD_MONO("mono")
r29404	r29405
999	999	static MACHINE_CONFIG_DERIVED( laser200, laser110 )
1000	1000	MCFG_DEVICE_REMOVE("mc6847")
1001	1001	MCFG_MC6847_ADD("mc6847", MC6847_PAL, XTAL_4_433619MHz, vtech1_mc6847_intf)
1002		MCFG_MC6847_FSYNC_CALLBACK(INPUTLINE("maincpu", 0))
	1002	MCFG_MC6847_FSYNC_CALLBACK(INPUTLINE("maincpu", 0))
1003	1003	MACHINE_CONFIG_END
1004	1004
1005	1005	static MACHINE_CONFIG_DERIVED( laser210, laser200 )
r29404	r29405
1028	1028	MCFG_CPU_IO_MAP(vtech1_shrg_io)
1029	1029	MCFG_DEVICE_REMOVE("mc6847")
1030	1030	MCFG_MC6847_ADD("mc6847", MC6847_PAL, XTAL_4_433619MHz, vtech1_shrg_mc6847_intf)
1031		MCFG_MC6847_FSYNC_CALLBACK(INPUTLINE("maincpu", 0))
	1031	MCFG_MC6847_FSYNC_CALLBACK(INPUTLINE("maincpu", 0))
1032	1032	MACHINE_CONFIG_END
1033	1033
1034	1034

trunk/src/mess/drivers/pda600.c
r29404	r29405
209	209	MCFG_SCREEN_VISIBLE_AREA(0, 240-1, 0, 320-1)
210	210	MCFG_SCREEN_UPDATE_DRIVER( pda600_state, screen_update )
211	211	MCFG_SCREEN_PALETTE("palette")
212
	212
213	213	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pda600)
214	214	MCFG_DEFAULT_LAYOUT(layout_lcd)
215	215	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")

trunk/src/mess/drivers/apricot.c
r29404	r29405
170	170
171	171	WRITE8_MEMBER( apricot_state::i8255_portc_w )
172	172	{
173		// schematic page 294 says pc4 outputs to centronics pin 13, which is the "select" output from the printer.
	173	// schematic page 294 says pc4 outputs to centronics pin 13, which is the "select" output from the printer.
174	174	m_centronics->write_strobe(BIT(data, 5));
175		// schematic page 294 says pc6 outputs to centronics pin 15, which is unused
	175	// schematic page 294 says pc6 outputs to centronics pin 15, which is unused
176	176	}
177	177
178	178	static const i8255_interface apricot_i8255a_intf =

trunk/src/mess/drivers/vt520.c
r29404	r29405
85	85	MCFG_SCREEN_VISIBLE_AREA(0, 802-1, 0, 480-1)
86	86	MCFG_SCREEN_UPDATE_DRIVER(vt520_state, screen_update_vt520)
87	87	MCFG_SCREEN_PALETTE("palette")
88
	88
89	89	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
90	90
91	91	// On the board there are two M5M44256BJ-7 chips

trunk/src/mess/drivers/sym1.c
r29404	r29405
324	324
325	325	// devices
326	326	MCFG_RIOT6532_ADD("riot", SYM1_CLOCK, sym1_r6532_interface)
327
	327
328	328	MCFG_DEVICE_ADD("ttl74145", TTL74145, 0)
329	329	MCFG_TTL74145_OUTPUT_LINE_0_CB(WRITELINE(sym1_state, sym1_74145_output_0_w))
330	330	MCFG_TTL74145_OUTPUT_LINE_1_CB(WRITELINE(sym1_state, sym1_74145_output_1_w))
r29404	r29405
334	334	MCFG_TTL74145_OUTPUT_LINE_5_CB(WRITELINE(sym1_state, sym1_74145_output_5_w))
335	335	MCFG_TTL74145_OUTPUT_LINE_6_CB(DEVWRITELINE("speaker", speaker_sound_device, level_w))
336	336	// lines 7-9 not connected
337
	337
338	338	MCFG_DEVICE_ADD("via6522_0", VIA6522, 0)
339	339	MCFG_VIA6522_IRQ_HANDLER(DEVWRITELINE("maincpu", m6502_device, irq_line))
340	340

trunk/src/mess/drivers/v6809.c
r29404	r29405
108	108	required_device<speaker_sound_device> m_speaker;
109	109	required_device<acia6850_device> m_acia0;
110	110	required_device<acia6850_device> m_acia1;
111		public:
	111	public:
112	112	required_device<palette_device> m_palette;
113	113	};
114	114

trunk/src/mess/drivers/x68k.c
r29404	r29405
1057	1057	m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
1058	1058	m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
1059	1059	timer_set(m_maincpu->cycles_to_attotime(16), TIMER_X68K_BUS_ERROR); // let rmw cycles complete
1060		logerror("%s: Bus error: Unused RAM access [%08x]\n", machine().describe_context(), address);
	1060	logerror("%s: Bus error: Unused RAM access [%08x]\n", machine().describe_context(), address);
1061	1061	}
1062	1062
1063	1063	READ16_MEMBER(x68k_state::x68k_rom0_r)
r29404	r29405
1873	1873	MCFG_SCREEN_VISIBLE_AREA(0, 767, 0, 511)
1874	1874	MCFG_SCREEN_UPDATE_DRIVER(x68k_state, screen_update_x68000)
1875	1875	MCFG_SCREEN_PALETTE("palette")
1876
	1876
1877	1877	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1878	1878
1879	1879	MCFG_PALETTE_ADD("palette", 65536)

trunk/src/mess/drivers/special.c
r29404	r29405
375	375	MCFG_VIDEO_START_OVERRIDE(special_state,special)
376	376	MCFG_SCREEN_UPDATE_DRIVER(special_state, screen_update_special)
377	377	MCFG_SCREEN_PALETTE("palette")
378
	378
379	379	MCFG_PALETTE_ADD("palette", 2)
380	380
381	381	/* audio hardware */
r29404	r29405
419	419	MCFG_SCREEN_MODIFY("screen")
420	420	MCFG_SCREEN_UPDATE_DRIVER(special_state, screen_update_specimx)
421	421	MCFG_VIDEO_START_OVERRIDE(special_state,specimx)
422
	422
423	423	MCFG_PALETTE_MODIFY("palette")
424	424	MCFG_PALETTE_ENTRIES(16)
425	425	MCFG_PALETTE_INIT_OWNER(special_state, specimx )
r29404	r29405
436	436	MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("custom", specimx_sound_device, set_input_ch1))
437	437	MCFG_PIT8253_CLK2(2000000)
438	438	MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("custom", specimx_sound_device, set_input_ch2))
439
	439
440	440	MCFG_DEVICE_REMOVE("ppi8255")
441	441	MCFG_I8255_ADD( "ppi8255", specimx_ppi8255_interface )
442	442	MCFG_FD1793x_ADD("fd1793", XTAL_8MHz / 8)
r29404	r29405
467	467	MCFG_VIDEO_START_OVERRIDE(special_state,erik)
468	468	MCFG_SCREEN_UPDATE_DRIVER(special_state, screen_update_erik)
469	469	MCFG_SCREEN_PALETTE("palette")
470
	470
471	471	MCFG_PALETTE_ADD("palette", 8)
472	472	MCFG_PALETTE_INIT_OWNER(special_state,erik)
473	473

trunk/src/mess/drivers/jupiter.c
r29404	r29405
290	290	MCFG_SCREEN_SIZE(512, 320)
291	291	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 320-1)
292	292	MCFG_SCREEN_PALETTE("palette")
293
294
	293
	294
295	295	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
296	296
297	297	// devices

trunk/src/mess/drivers/mes.c
r29404	r29405
117	117	MCFG_SCREEN_SIZE(640, 250)
118	118	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 249)
119	119	MCFG_SCREEN_PALETTE("palette")
120
	120
121	121	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
122	122	MACHINE_CONFIG_END
123	123

trunk/src/mess/drivers/sm1800.c
r29404	r29405
189	189	MCFG_PALETTE_ADD("palette", 3)
190	190	MCFG_PALETTE_INIT_OWNER(sm1800_state, sm1800)
191	191
192		MCFG_GFXDECODE_ADD("gfxdecode", "palette", sm1800)
	192	MCFG_GFXDECODE_ADD("gfxdecode", "palette", sm1800)
193	193
194	194	/* Devices */
195	195	MCFG_I8255_ADD ("i8255", sm1800_ppi8255_interface )

trunk/src/mess/drivers/compis.c
r29404	r29405
712	712	MCFG_SCREEN_SIZE(640, 400)
713	713	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 400-1)
714	714	MCFG_SCREEN_UPDATE_DEVICE("upd7220", upd7220_device, screen_update)
715
	715
716	716	MCFG_DEVICE_ADD("upd7220", UPD7220, XTAL_4_433619MHz/2) // unknown clock
717	717	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
718		MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(compis_state, hgdc_display_pixels)
	718	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(compis_state, hgdc_display_pixels)
719	719	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
720
	720
721	721	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
722	722
723	723	// devices

trunk/src/mess/drivers/megadriv.c
r29404	r29405
286	286	{
287	287	MACHINE_START_CALL_MEMBER( md_common );
288	288
289		// the segaCD introduces some kind of DMA 'lag', which we have to compensate for,
	289	// the segaCD introduces some kind of DMA 'lag', which we have to compensate for,
290	290	// at least when reading wordram? we might need to check what mode we're in the DMA...
291	291	m_vdp->set_dma_delay(2);
292	292	}
r29404	r29405
295	295	{
296	296	m_maincpu->reset();
297	297	MACHINE_RESET_CALL_MEMBER( megadriv );
298
	298
299	299	// if the system has a 32x, pause the extra CPUs until they are actually turned on
300	300	if (m_32x)
301	301	m_32x->pause_cpu();
r29404	r29405
306	306	{
307	307	if (m_io_reset->read_safe(0x00) & 0x01)
308	308	m_maincpu->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
309
	309
310	310	// rising edge
311	311	if (state)
312	312	{
r29404	r29405
315	315	bool mode3 = (m_vdp->get_imode() == 3);
316	316	m_vdp->vdp_handle_eof();
317	317	m_vdp->m_megadriv_scanline_timer->adjust(attotime::zero);
318
	318
319	319	if (m_32x)
320	320	{
321	321	m_32x->m_32x_vblank_flag = 0;
r29404	r29405
410	410	m_segacd->set_framerate(60);
411	411	m_segacd->set_total_scanlines(262);
412	412	}
413
414		m_version_hi_nibble = 0x80; // Export NTSC
	413
	414	m_version_hi_nibble = 0x80; // Export NTSC
415	415	if (!m_segacd)
416	416	m_version_hi_nibble \|= 0x20;
417	417	}
r29404	r29405
420	420	{
421	421	DRIVER_INIT_CALL(megadrie);
422	422	DRIVER_INIT_CALL(mess_md_common);
423
	423
424	424	if (m_32x)
425	425	{
426	426	m_32x->set_32x_pal(TRUE);
r29404	r29405
432	432	m_segacd->set_framerate(50);
433	433	m_segacd->set_total_scanlines(313);
434	434	}
435
436		m_version_hi_nibble = 0xc0; // Export PAL
	435
	436	m_version_hi_nibble = 0xc0; // Export PAL
437	437	if (!m_segacd)
438	438	m_version_hi_nibble \|= 0x20;
439	439	}
r29404	r29405
442	442	{
443	443	DRIVER_INIT_CALL(megadrij);
444	444	DRIVER_INIT_CALL(mess_md_common);
445
	445
446	446	if (m_32x)
447	447	{
448	448	m_32x->set_32x_pal(FALSE);
r29404	r29405
454	454	m_segacd->set_framerate(60);
455	455	m_segacd->set_total_scanlines(262);
456	456	}
457
458		m_version_hi_nibble = 0x00; // JPN NTSC
	457
	458	m_version_hi_nibble = 0x00; // JPN NTSC
459	459	if (!m_segacd)
460	460	m_version_hi_nibble \|= 0x20;
461	461	}
r29404	r29405
728	728	MCFG_SCREEN_VBLANK_DRIVER(md_cons_state, screen_eof_console)
729	729
730	730	MCFG_DEVICE_ADD("segacd", SEGA_SEGACD_JAPAN, 0)
731
	731
732	732	MCFG_CDROM_ADD( "cdrom",scd_cdrom )
733	733
734	734	MCFG_SOFTWARE_LIST_ADD("cd_list","megacdj")

trunk/src/mess/drivers/d6800.c
r29404	r29405
392	392	MCFG_SCREEN_UPDATE_DRIVER(d6800_state, screen_update_d6800)
393	393	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(25))
394	394	MCFG_SCREEN_PALETTE("palette")
395
	395
396	396	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
397	397
398	398	/* sound hardware */

trunk/src/mess/drivers/rx78.c
r29404	r29405
57	57	m_maincpu(*this, "maincpu"),
58	58	m_cass(*this, "cassette"),
59	59	m_ram(*this, RAM_TAG),
60		m_palette(*this, "palette")
	60	m_palette(*this, "palette")
61	61	{ }
62	62
63	63	DECLARE_READ8_MEMBER( key_r );
r29404	r29405
472	472	MCFG_SCREEN_SIZE(192, 184)
473	473	MCFG_SCREEN_VISIBLE_AREA(0, 192-1, 0, 184-1)
474	474	MCFG_SCREEN_PALETTE("palette")
475
	475
476	476	MCFG_PALETTE_ADD("palette", 16+1) //+1 for the background color
477	477	MCFG_GFXDECODE_ADD("gfxdecode", "palette", rx78)
478	478

trunk/src/mess/drivers/tim100.c
r29404	r29405
18	18	tim100_state(const machine_config &mconfig, device_type type, const char *tag)
19	19	: driver_device(mconfig, type, tag),
20	20	m_maincpu(*this, "maincpu"),
21		m_palette(*this, "palette")
	21	m_palette(*this, "palette")
22	22	{ }
23	23
24	24	required_device<cpu_device> m_maincpu;

trunk/src/mess/drivers/psx.c
r29404	r29405
623	623	ROM_FILL( 0x0400, 0x0c00, 0xff )
624	624	ROM_LOAD( "scea.ic304", 0x001000, 0x004000, CRC(82729934) SHA1(7d5f52eb9df1243dcdab32cb763a9eb6a22706d7) )
625	625	ROM_FILL( 0x5000, 0xae00, 0xff )
626		ROM_LOAD( "test.ic304", 0x00fe00, 0x000200, CRC(3b2f8041) SHA1(d7127cb4a9b5efe9deffab3b72ab4451cb30675b) )
	626	ROM_LOAD( "test.ic304", 0x00fe00, 0x000200, CRC(3b2f8041) SHA1(d7127cb4a9b5efe9deffab3b72ab4451cb30675b) )
627	627	ROM_END
628	628
629	629	ROM_START( pse )

trunk/src/mess/drivers/pv1000.c
r29404	r29405
470	470
471	471	MCFG_PALETTE_ADD( "palette", 8 )
472	472	MCFG_PALETTE_INIT_OWNER(pv1000_state, pv1000)
473
	473
474	474	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pv1000 )
475	475
476	476	MCFG_SPEAKER_STANDARD_MONO("mono")

trunk/src/mess/drivers/bigbord2.c
r29404	r29405
163	163	required_memory_bank m_bankr;
164	164	required_memory_bank m_bankv;
165	165	required_memory_bank m_banka;
166		public:
	166	public:
167	167	required_device<palette_device> m_palette;
168	168	};
169	169

trunk/src/mess/drivers/applix.c
r29404	r29405
195	195	required_ioport m_io_k3b0;
196	196	required_ioport m_io_k0b;
197	197	required_shared_ptr<UINT16> m_expansion;
198		public:
	198	public:
199	199	required_device<palette_device> m_palette;
200	200	};
201	201

trunk/src/mess/drivers/sitcom.c
r29404	r29405
113	113	MCFG_CPU_IO_MAP(sitcom_io)
114	114	MCFG_I8085A_SID(READLINE(sitcom_state, sid_line))
115	115	MCFG_I8085A_SOD(WRITELINE(sitcom_state, sod_led))
116
	116
117	117	MCFG_DEFAULT_LAYOUT(layout_sitcom)
118	118
119	119	/* video hardware */

trunk/src/mess/drivers/plus4.c
r29404	r29405
690	690	{
691	691	m_acia->write_cts(0);
692	692	}
693
	693
694	694	m_spi_kb->write_p0(1);
695	695	m_spi_kb->write_p1(1);
696	696	m_spi_kb->write_p2(1);

trunk/src/mess/drivers/tim011.c
r29404	r29405
145	145	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
146	146	MCFG_SCREEN_UPDATE_DRIVER(tim011_state, screen_update_tim011)
147	147	MCFG_SCREEN_PALETTE("palette")
148
	148
149	149	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
150	150	MACHINE_CONFIG_END
151	151

trunk/src/mess/drivers/intv.c
r29404	r29405
817	817	MCFG_SCREEN_SIZE((STIC_OVERSCAN_LEFT_WIDTH+STIC_BACKTAB_WIDTHSTIC_CARD_WIDTH-1+STIC_OVERSCAN_RIGHT_WIDTH)STIC_X_SCALEINTV_X_SCALE, (STIC_OVERSCAN_TOP_HEIGHT+STIC_BACKTAB_HEIGHTSTIC_CARD_HEIGHT+STIC_OVERSCAN_BOTTOM_HEIGHT)STIC_Y_SCALEINTV_Y_SCALE)
818	818	MCFG_SCREEN_VISIBLE_AREA(0, (STIC_OVERSCAN_LEFT_WIDTH+STIC_BACKTAB_WIDTHSTIC_CARD_WIDTH-1+STIC_OVERSCAN_RIGHT_WIDTH)STIC_X_SCALEINTV_X_SCALE-1, 0, (STIC_OVERSCAN_TOP_HEIGHT+STIC_BACKTAB_HEIGHTSTIC_CARD_HEIGHT+STIC_OVERSCAN_BOTTOM_HEIGHT)STIC_Y_SCALEINTV_Y_SCALE-1)
819	819	MCFG_SCREEN_PALETTE("palette")
820
	820
821	821	MCFG_PALETTE_ADD("palette", 0x400)
822	822	MCFG_PALETTE_INDIRECT_ENTRIES(32)
823	823	MCFG_PALETTE_INIT_OWNER(intv_state, intv)
r29404	r29405
874	874	MCFG_GFXDECODE_ADD("gfxdecode", "palette", intvkbd)
875	875	MCFG_PALETTE_MODIFY("palette")
876	876	MCFG_PALETTE_INIT_OWNER(intv_state, intv)
877
	877
878	878	MCFG_SCREEN_MODIFY("screen")
879	879	MCFG_SCREEN_SIZE((STIC_OVERSCAN_LEFT_WIDTH+STIC_BACKTAB_WIDTHSTIC_CARD_WIDTH-1+STIC_OVERSCAN_RIGHT_WIDTH)STIC_X_SCALEINTVKBD_X_SCALE, (STIC_OVERSCAN_TOP_HEIGHT+STIC_BACKTAB_HEIGHTSTIC_CARD_HEIGHT+STIC_OVERSCAN_BOTTOM_HEIGHT)STIC_Y_SCALEINTVKBD_Y_SCALE)
880	880	MCFG_SCREEN_VISIBLE_AREA(0, (STIC_OVERSCAN_LEFT_WIDTH+STIC_BACKTAB_WIDTHSTIC_CARD_WIDTH-1+STIC_OVERSCAN_RIGHT_WIDTH)STIC_X_SCALEINTVKBD_X_SCALE-1, 0, (STIC_OVERSCAN_TOP_HEIGHT+STIC_BACKTAB_HEIGHTSTIC_CARD_HEIGHT+STIC_OVERSCAN_BOTTOM_HEIGHT)STIC_Y_SCALEINTVKBD_Y_SCALE-1)

trunk/src/mess/drivers/phc25.c
r29404	r29405
266	266	{
267	267	return m_video_ram[offset];
268	268	}
269		else // text
	269	else // text
270	270	{
271	271	offset &= 0x7ff;
272	272	m_vdg->inv_w(BIT(m_video_ram[offset \| 0x800], 0)); // cursor attribute

trunk/src/mess/drivers/compucolor.c
r29404	r29405
10	10
11	11	/*
12	12
13		TODO:
	13	TODO:
14	14
15		- floppy
16		- interlaced video
17		- add-on ROM
18		- add-on RAM
19		- add-on unit
	15	- floppy
	16	- interlaced video
	17	- add-on ROM
	18	- add-on RAM
	19	- add-on unit
20	20
21	21	*/
22	22
23		#define I8080_TAG "ua2"
24		#define TMS5501_TAG "ud2"
25		#define CRT5027_TAG "uf9"
26		#define RS232_TAG "rs232"
	23	#define I8080_TAG "ua2"
	24	#define TMS5501_TAG "ud2"
	25	#define CRT5027_TAG "uf9"
	26	#define RS232_TAG "rs232"
27	27
28	28	#include "bus/rs232/rs232.h"
29	29	#include "cpu/i8085/i8085.h"
r29404	r29405
37	37	public:
38	38	compucolor2_state(const machine_config &mconfig, device_type type, const char *tag)
39	39	: driver_device(mconfig, type, tag),
40		m_maincpu(*this, I8080_TAG),
41		m_mioc(*this, TMS5501_TAG),
42		m_vtac(*this, CRT5027_TAG),
43		m_rs232(*this, RS232_TAG),
44		m_floppy0(*this, "cd0"),
45		m_floppy1(*this, "cd1"),
46		m_char_rom(*this, "chargen"),
47		m_video_ram(*this, "videoram"),
48		m_y0(*this, "Y0"),
49		m_y1(*this, "Y1"),
50		m_y2(*this, "Y2"),
51		m_y3(*this, "Y3"),
52		m_y4(*this, "Y4"),
53		m_y5(*this, "Y5"),
54		m_y6(*this, "Y6"),
55		m_y7(*this, "Y7"),
56		m_y8(*this, "Y8"),
57		m_y9(*this, "Y9"),
58		m_y10(*this, "Y10"),
59		m_y11(*this, "Y11"),
60		m_y12(*this, "Y12"),
61		m_y13(*this, "Y13"),
62		m_y14(*this, "Y14"),
63		m_y15(*this, "Y15"),
64		m_y128(*this, "Y128")
	40	m_maincpu(*this, I8080_TAG),
	41	m_mioc(*this, TMS5501_TAG),
	42	m_vtac(*this, CRT5027_TAG),
	43	m_rs232(*this, RS232_TAG),
	44	m_floppy0(*this, "cd0"),
	45	m_floppy1(*this, "cd1"),
	46	m_char_rom(*this, "chargen"),
	47	m_video_ram(*this, "videoram"),
	48	m_y0(*this, "Y0"),
	49	m_y1(*this, "Y1"),
	50	m_y2(*this, "Y2"),
	51	m_y3(*this, "Y3"),
	52	m_y4(*this, "Y4"),
	53	m_y5(*this, "Y5"),
	54	m_y6(*this, "Y6"),
	55	m_y7(*this, "Y7"),
	56	m_y8(*this, "Y8"),
	57	m_y9(*this, "Y9"),
	58	m_y10(*this, "Y10"),
	59	m_y11(*this, "Y11"),
	60	m_y12(*this, "Y12"),
	61	m_y13(*this, "Y13"),
	62	m_y14(*this, "Y14"),
	63	m_y15(*this, "Y15"),
	64	m_y128(*this, "Y128")
65	65	{ }
66	66
67	67	required_device<cpu_device> m_maincpu;
r29404	r29405
93	93	virtual void machine_start();
94	94	virtual void machine_reset();
95	95	DECLARE_PALETTE_INIT(compucolor2);
96
	96
97	97	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
98	98
99	99	DECLARE_READ8_MEMBER( xi_r );
r29404	r29405
299	299	{
300	300	UINT8 code = m_video_ram[offset++];
301	301	UINT8 attr = m_video_ram[offset++];
302
	302
303	303	offs_t char_offs = ((code & 0x7f) << 3) \| (y & 0x07);
304	304	if (BIT(code, 7)) char_offs = ((code & 0x7f) << 3) \| ((y >> 1) & 0x07);
305	305
r29404	r29405
458	458
459	459	MCFG_PALETTE_ADD("palette", 8)
460	460	MCFG_PALETTE_INIT_OWNER(compucolor2_state, compucolor2)
461
	461
462	462	// video hardware
463	463	MCFG_SCREEN_ADD("screen", RASTER)
464	464	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mess/drivers/octopus.c
r29404	r29405
178	178	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
179	179	MCFG_SCREEN_UPDATE_DRIVER(octopus_state, screen_update_octopus)
180	180	MCFG_SCREEN_PALETTE("palette")
181
	181
182	182	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
183	183	MACHINE_CONFIG_END
184	184

trunk/src/mess/drivers/mz3500.c
r29404	r29405
50	50	m_fdc(*this, "upd765a"),
51	51	m_video_ram(*this, "video_ram"),
52	52	m_beeper(*this, "beeper"),
53		m_palette(*this, "palette")
	53	m_palette(*this, "palette")
54	54	{ }
55	55
56	56	// devices
r29404	r29405
837	837	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, MAIN_CLOCK/5)
838	838	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
839	839	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(mz3500_state, hgdc_draw_text)
840		MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_gfx", upd7220_device, ext_sync_w))
	840	MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_gfx", upd7220_device, ext_sync_w))
841	841
842	842	MCFG_DEVICE_ADD("upd7220_gfx", UPD7220, MAIN_CLOCK/5)
843	843	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)

trunk/src/mess/drivers/mz80.c
r29404	r29405
290	290	MCFG_SCREEN_VISIBLE_AREA(0, 319, 0, 199)
291	291	MCFG_SCREEN_UPDATE_DRIVER(mz80_state, screen_update_mz80k)
292	292	MCFG_SCREEN_PALETTE("palette")
293
	293
294	294	MCFG_GFXDECODE_ADD("gfxdecode", "palette", mz80k)
295	295	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
296	296

trunk/src/mess/drivers/rainbow.c
r29404	r29405
6	6
7	7	STATE AS OF MARCH 2014
8	8	----------------------
9		Driver is based entirely on the DEC-100 'B' variant (DEC-190 and DEC-100 A models are treated as clones).
10		While this is OK for the compatible -190, it doesn't do justice to ancient '100 A' hardware.
	9	Driver is based entirely on the DEC-100 'B' variant (DEC-190 and DEC-100 A models are treated as clones).
	10	While this is OK for the compatible -190, it doesn't do justice to ancient '100 A' hardware.
11	11
12		Currently, there are 2 showstoppers:
13		(1) IRQ logic for 100-B needs further work (text in RBCONVERT.ZIP has details concerning -A versus -B)
	12	Currently, there are 2 showstoppers:
	13	(1) IRQ logic for 100-B needs further work (text in RBCONVERT.ZIP has details concerning -A versus -B)
14	14	(2) Keyboard emulation incomplete (inhibits the system from booting with ERROR 50 on cold or ERROR 13 on warm boot).
15	15
16	16	- FLOPPY TIMING: 'wd17xx_complete_command' * must * be hard wired to about 13 usecs.
r29404	r29405
35	35	* Extended communication option (same as BUNDLE_OPTION ?)
36	36
37	37	- OTHER HARDWARE UPGRADES:
38		* Suitable Solutions ClikClok (real time clock)
39
	38	* Suitable Solutions ClikClok (real time clock)
	39
40	40	* Suitable Solutions TURBOW286: 12 Mhz, 68-pin, low power AMD N80L286-12 and WAYLAND/EDSUN EL286-88-10-B ( 80286 to 8088 Processor Signal Converter )
41	41	plus DC 7174 or DT 7174 (barely readable). Add-on card, replaces main 8088 cpu (via ribbon cable). Altered BOOT ROM labeled 'TBSS1.3 - 3ED4'.
42	42
r29404	r29405
269	269	private:
270	270	enum
271	271	{
272		IRQ_8088_MAILBOX = 0, // vector 0x27/a7
273		IRQ_8088_VBL, // vector 0x20/a0
274		IRQ_8088_KBD, // vector 0x26/a6
	272	IRQ_8088_MAILBOX = 0, // vector 0x27/a7
	273	IRQ_8088_VBL, // vector 0x20/a0
	274	IRQ_8088_KBD, // vector 0x26/a6
275	275
276	276	IRQ_8088_MAX
277	277	};
r29404	r29405
441	441	// BOOT LOADERS:
442	442	// - the DEC boot loader (and FDISK from DOS 3.10) initially allowed a maximum hard disc size of 20 MB.
443	443	// - the custom boot loader that comes with 'WUTIL 3.2' allows 117 MB and 8 surfaces.
444		// SOFTWARE:
	444	// SOFTWARE:
445	445	// - MS-DOS 2 allows a maximum partition size of 16 MB (sizes > 15 MB are incompatible to DOS 3)
446	446	// - MS-DOS 3 has a global 1024 cylinder limit (32 MB).
447	447	AM_RANGE (0x68, 0x68) AM_READ(hd_status_68_r)
r29404	r29405
528	528	PORT_DIPSETTING( 0x02, DEF_STR( On ) )
529	529	INPUT_PORTS_END
530	530
531		// Native 400K format (80 T * 10 S * 512 bytes) on 'quad density' RX50 drives
	531	// Native 400K format (80 T * 10 S * 512 bytes) on 'quad density' RX50 drives
532	532	// ( 5.25" single sided; 300 rpm; MFM 250 kbps; 96 - 100 tpi ).
533		//
	533	//
534	534	// Additionally, the BIOS can read VT-180 disks and MS-DOS 160 k disks
535	535	// - MS-DOS: FORMAT A: /F:160 and MEDIACHK ON
536	536	// ( 40 tracks; single sided with 9 or 8 sectors per track )
537	537	static LEGACY_FLOPPY_OPTIONS_START( dec100_floppy )
538	538	LEGACY_FLOPPY_OPTION( dec100_floppy, "td0", "Teledisk floppy disk image", td0_dsk_identify, td0_dsk_construct, td0_dsk_destruct, NULL )
539		LEGACY_FLOPPY_OPTION( dec100_floppy, "img", "DEC Rainbow 100", basicdsk_identify_default, basicdsk_construct_default, NULL,
	539	LEGACY_FLOPPY_OPTION( dec100_floppy, "img", "DEC Rainbow 100", basicdsk_identify_default, basicdsk_construct_default, NULL,
540	540	HEADS([1])
541	541	TRACKS(40/[80])
542	542	SECTORS(8/9/[10])
r29404	r29405
578	578	output_set_value("led7", 1);
579	579
580	580	// GREEN KEYBOARD LEDs (1 = on, 0 = off):
581		output_set_value("led_wait", 0); // led8
	581	output_set_value("led_wait", 0); // led8
582	582	output_set_value("led_compose", 0); // led9
583	583	output_set_value("led_lock", 0); // led10
584	584	output_set_value("led_hold", 0); // led11
r29404	r29405
654	654	}
655	655	else
656	656	{
657		m_i8088->set_input_line(INPUT_LINE_INT0, CLEAR_LINE);
	657	m_i8088->set_input_line(INPUT_LINE_INT0, CLEAR_LINE);
658	658	}
659	659	}
660	660
r29404	r29405
1210	1210	MCFG_SCREEN_UPDATE_DRIVER(rainbow_state, screen_update_rainbow)
1211	1211	MCFG_SCREEN_PALETTE("vt100_video:palette")
1212	1212	MCFG_GFXDECODE_ADD("gfxdecode", "vt100_video:palette", rainbow)
1213
	1213
1214	1214	MCFG_RAINBOW_VIDEO_ADD("vt100_video", "screen", video_interface)
1215	1215	MCFG_VT_VIDEO_RAM_CALLBACK(READ8(rainbow_state, read_video_ram_r))
1216	1216	MCFG_VT_VIDEO_CLEAR_VIDEO_INTERRUPT_CALLBACK(WRITELINE(rainbow_state, clear_video_interrupt))
r29404	r29405
1236	1236	MCFG_NVRAM_ADD_0FILL("nvram")
1237	1237	MACHINE_CONFIG_END
1238	1238
1239		// 'Rainbow 100-A' (introduced May 1982) is first-generation hardware with ROM 04.03.11
	1239	// 'Rainbow 100-A' (introduced May 1982) is first-generation hardware with ROM 04.03.11
1240	1240	// - 64 K base RAM on board (instead of 128 K on 'B' model). 832 K RAM max.
1241	1241	// - inability to boot from hard disc (mind the inadequate PSU)
1242	1242	// - cannot control bit 7 of IRQ vector (prevents DOS 2.0x from booting on unmodified hardware)
r29404	r29405
1298	1298	/* Driver */
1299	1299
1300	1300	/* YEAR NAME PARENT COMPAT MACHINE INPUT STATE INIT COMPANY FULLNAME FLAGS */
1301		COMP( 1982, rainbow100 , rainbow, 0, rainbow, rainbow100b_in, driver_device, 0, "Digital Equipment Corporation", "Rainbow 100-A", GAME_IS_SKELETON )
	1301	COMP( 1982, rainbow100 , rainbow, 0, rainbow, rainbow100b_in, driver_device, 0, "Digital Equipment Corporation", "Rainbow 100-A", GAME_IS_SKELETON )
1302	1302	COMP( 1983, rainbow , 0 , 0, rainbow, rainbow100b_in, driver_device, 0, "Digital Equipment Corporation", "Rainbow 100-B", GAME_NOT_WORKING \| GAME_IMPERFECT_COLORS)
1303	1303	COMP( 1985, rainbow190 , rainbow, 0, rainbow, rainbow100b_in, driver_device, 0, "Digital Equipment Corporation", "Rainbow 190-B", GAME_NOT_WORKING \| GAME_IMPERFECT_COLORS)
1304

trunk/src/mess/drivers/pc1500.c
r29404	r29405
277	277	MCFG_SCREEN_SIZE(156, 8)
278	278	MCFG_SCREEN_VISIBLE_AREA(0, 156-1, 0, 7-1)
279	279	MCFG_SCREEN_PALETTE("palette")
280
	280
281	281	MCFG_DEFAULT_LAYOUT(layout_pc1500)
282	282	MCFG_PALETTE_ADD("palette", 2)
283	283	MCFG_PALETTE_INIT_OWNER(pc1500_state, pc1500)

trunk/src/mess/drivers/ut88.c
r29404	r29405
201	201	MCFG_VIDEO_START_OVERRIDE(ut88_state,ut88)
202	202	MCFG_SCREEN_UPDATE_DRIVER(ut88_state, screen_update_ut88)
203	203	MCFG_SCREEN_PALETTE("palette")
204
	204
205	205	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
206	206	MCFG_GFXDECODE_ADD("gfxdecode", "palette", ut88 )
207	207

trunk/src/mess/drivers/unistar.c
r29404	r29405
100	100	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
101	101	MCFG_SCREEN_UPDATE_DRIVER(unistar_state, screen_update_unistar)
102	102	MCFG_SCREEN_PALETTE("palette")
103
	103
104	104	MCFG_GFXDECODE_ADD("gfxdecode", "palette", unistar)
105	105	MCFG_PALETTE_ADD("palette", 3)
106	106	MCFG_PALETTE_INIT_OWNER(unistar_state, unistar)

trunk/src/mess/drivers/rd110.c
r29404	r29405
241	241	MCFG_SCREEN_SIZE(166-1, (166-1)*3/4)
242	242	MCFG_SCREEN_VISIBLE_AREA(0, 166-2, 0, (166-1)*3/4-1)
243	243	MCFG_SCREEN_PALETTE("palette")
244
	244
245	245	MCFG_PALETTE_ADD("palette", 2)
246	246	MCFG_PALETTE_INIT_OWNER(d110_state, d110)
247	247

trunk/src/mess/drivers/casloopy.c
r29404	r29405
497	497	MCFG_SCREEN_PALETTE("palette")
498	498
499	499	MCFG_PALETTE_ADD("palette", 512)
500
	500
501	501	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
502	502
503	503	MCFG_CARTSLOT_ADD("cart")

trunk/src/mess/drivers/replicator.c
r29404	r29405
179	179	UINT8 m_port_k;
180	180	UINT8 m_port_l;
181	181
182		UINT8 shift_register_value;
	182	UINT8 shift_register_value;
183	183
184	184	required_device<avr8_device> m_maincpu;
185	185	required_device<hd44780_device> m_lcdc;
r29404	r29405
201	201	switch( offset )
202	202	{
203	203	case AVR8_IO_PORTA:
204		{
	204	{
205	205	#if LOG_PORTS
206		printf("[%08X] Port A READ (A-axis signals + B-axis STEP&DIR)\n", m_maincpu->m_shifted_pc);
	206	printf("[%08X] Port A READ (A-axis signals + B-axis STEP&DIR)\n", m_maincpu->m_shifted_pc);
207	207	#endif
208		return 0x00;
209		break;
210		}
	208	return 0x00;
	209	break;
	210	}
211	211	case AVR8_IO_PORTB:
212		{
	212	{
213	213	#if LOG_PORTS
214		printf("[%08X] Port B READ (SD-CS; 1280-MISO/MOSI/SCK; EX2-FAN/HEAT/PWR-CHECK; BLINK)\n", m_maincpu->m_shifted_pc);
	214	printf("[%08X] Port B READ (SD-CS; 1280-MISO/MOSI/SCK; EX2-FAN/HEAT/PWR-CHECK; BLINK)\n", m_maincpu->m_shifted_pc);
215	215	#endif
216		return 0x00;
217		break;
218		}
	216	return 0x00;
	217	break;
	218	}
219	219	case AVR8_IO_PORTC:
220		{
	220	{
221	221	#if LOG_PORTS
222		printf("[%08X] Port C READ (1280-EX1/EX2; LCD-signals; R&G-LED; DETECT)\n", m_maincpu->m_shifted_pc);
	222	printf("[%08X] Port C READ (1280-EX1/EX2; LCD-signals; R&G-LED; DETECT)\n", m_maincpu->m_shifted_pc);
223	223	#endif
224		return DETECT; //indicated that the Interface board is present.
225		break;
226		}
	224	return DETECT; //indicated that the Interface board is present.
	225	break;
	226	}
227	227	case AVR8_IO_PORTD:
228		{
	228	{
229	229	#if LOG_PORTS
230		printf("[%08X] Port D READ (SDA/SCL; 1280-EX-TX/RX)\n", m_maincpu->m_shifted_pc);
	230	printf("[%08X] Port D READ (SDA/SCL; 1280-EX-TX/RX)\n", m_maincpu->m_shifted_pc);
231	231	#endif
232		return 0x00;
233		break;
234		}
	232	return 0x00;
	233	break;
	234	}
235	235	case AVR8_IO_PORTE:
236		{
	236	{
237	237	#if LOG_PORTS
238		printf("[%08X] Port E READ (1280-TX/RX; THERMO-signals)\n", m_maincpu->m_shifted_pc);
	238	printf("[%08X] Port E READ (1280-TX/RX; THERMO-signals)\n", m_maincpu->m_shifted_pc);
239	239	#endif
240		return 0x00;
241		break;
242		}
	240	return 0x00;
	241	break;
	242	}
243	243	case AVR8_IO_PORTF:
244		{
	244	{
245	245	#if LOG_PORTS
246		printf("[%08X] Port F READ (X-axis & Y-axis signals)\n", m_maincpu->m_shifted_pc);
	246	printf("[%08X] Port F READ (X-axis & Y-axis signals)\n", m_maincpu->m_shifted_pc);
247	247	#endif
248		return 0x00;
249		break;
250		}
	248	return 0x00;
	249	break;
	250	}
251	251	case AVR8_IO_PORTG:
252		{
	252	{
253	253	#if LOG_PORTS
254		printf("[%08X] Port G READ (BUZZ; Cutoff-sr-check; B-axis EN; 1280-EX3/EX4)\n", m_maincpu->m_shifted_pc);
	254	printf("[%08X] Port G READ (BUZZ; Cutoff-sr-check; B-axis EN; 1280-EX3/EX4)\n", m_maincpu->m_shifted_pc);
255	255	#endif
256		return 0x00;
257		break;
258		}
	256	return 0x00;
	257	break;
	258	}
259	259	case AVR8_IO_PORTH:
260		{
	260	{
261	261	#if LOG_PORTS
262		printf("[%08X] Port H READ (cuttoff-text/reset; EX1-FAN/HEAT/PWR-CHECK; SD-CD/SD-WP)\n", m_maincpu->m_shifted_pc);
	262	printf("[%08X] Port H READ (cuttoff-text/reset; EX1-FAN/HEAT/PWR-CHECK; SD-CD/SD-WP)\n", m_maincpu->m_shifted_pc);
263	263	#endif
264		return 0x00;
265		break;
266		}
	264	return 0x00;
	265	break;
	266	}
267	267	case AVR8_IO_PORTJ:
268		{
	268	{
269	269	#if LOG_PORTS
270		printf("[%08X] Port J READ (Interface buttons; POTS-SCL; B-axis-POT)\n", m_maincpu->m_shifted_pc);
	270	printf("[%08X] Port J READ (Interface buttons; POTS-SCL; B-axis-POT)\n", m_maincpu->m_shifted_pc);
271	271	#endif
272		return ioport("keypad")->read();
273		break;
274		}
	272	return ioport("keypad")->read();
	273	break;
	274	}
275	275	case AVR8_IO_PORTK:
276		{
	276	{
277	277	#if LOG_PORTS
278		printf("[%08X] Port K READ (Z-axis signals; HBP-THERM; 1280-EX5/6/7)\n", m_maincpu->m_shifted_pc);
	278	printf("[%08X] Port K READ (Z-axis signals; HBP-THERM; 1280-EX5/6/7)\n", m_maincpu->m_shifted_pc);
279	279	#endif
280		return 0x00;
281		break;
282		}
	280	return 0x00;
	281	break;
	282	}
283	283	case AVR8_IO_PORTL:
284		{
	284	{
285	285	#if LOG_PORTS
286		printf("[%08X] Port L READ (HBP; EXTRA-FET; X-MIN/MAX; Y-MIN/MAX; Z-MIN/MAX)\n", m_maincpu->m_shifted_pc);
	286	printf("[%08X] Port L READ (HBP; EXTRA-FET; X-MIN/MAX; Y-MIN/MAX; Z-MIN/MAX)\n", m_maincpu->m_shifted_pc);
287	287	#endif
288		return 0x00;
289		break;
290		}
	288	return 0x00;
	289	break;
291	290	}
	291	}
292	292	return 0;
293	293	}
294	294
r29404	r29405
297	297	switch( offset )
298	298	{
299	299	case AVR8_IO_PORTA:
300		{
301		if (data == m_port_a) break;
	300	{
	301	if (data == m_port_a) break;
302	302
303	303	#if LOG_PORTS
304	304	UINT8 old_port_a = m_port_a;
305	305	UINT8 changed = data ^ old_port_a;
306	306
307		printf("[%08X] ", m_maincpu->m_shifted_pc);
	307	printf("[%08X] ", m_maincpu->m_shifted_pc);
308	308	if(changed & A_AXIS_DIR) printf("[A] A_AXIS_DIR: %s\n", data & A_AXIS_DIR ? "HIGH" : "LOW");
309	309	if(changed & A_AXIS_STEP) printf("[A] A_AXIS_STEP: %s\n", data & A_AXIS_STEP ? "HIGH" : "LOW");
310	310	if(changed & A_AXIS_EN) printf("[A] A_AXIS_EN: %s\n", data & A_AXIS_EN ? "HIGH" : "LOW");
r29404	r29405
313	313	if(changed & B_AXIS_STEP) printf("[A] B_AXIS_STEP: %s\n", data & B_AXIS_STEP ? "HIGH" : "LOW");
314	314	#endif
315	315
316		m_port_a = data;
317		break;
318		}
	316	m_port_a = data;
	317	break;
	318	}
319	319	case AVR8_IO_PORTB:
320		{
321		if (data == m_port_b) break;
	320	{
	321	if (data == m_port_b) break;
322	322
323	323	#if LOG_PORTS
324	324	UINT8 old_port_b = m_port_b;
325	325	UINT8 changed = data ^ old_port_b;
326	326
327		printf("[%08X] ", m_maincpu->m_shifted_pc);
	327	printf("[%08X] ", m_maincpu->m_shifted_pc);
328	328	if(changed & SD_CS) printf("[B] SD Card Chip Select: %s\n", data & SD_CS ? "HIGH" : "LOW");
329	329	if(changed & SCK_1280) printf("[B] 1280-SCK: %s\n", data & SCK_1280 ? "HIGH" : "LOW");
330	330	if(changed & MOSI_1280) printf("[B] 1280-MOSI: %s\n", data & MOSI_1280 ? "HIGH" : "LOW");
r29404	r29405
335	335	if(changed & BLINK) printf("[B] BLINK: %s\n", data & BLINK ? "HIGH" : "LOW");
336	336	#endif
337	337
338		m_port_b = data;
339		break;
340		}
	338	m_port_b = data;
	339	break;
	340	}
341	341	case AVR8_IO_PORTC:
342		{
343		if (data == m_port_c) break;
	342	{
	343	if (data == m_port_c) break;
344	344
345	345	UINT8 old_port_c = m_port_c;
346	346	UINT8 changed = data ^ old_port_c;
347	347	#if LOG_PORTS
348		printf("[%08X] ", m_maincpu->m_shifted_pc);
	348	printf("[%08X] ", m_maincpu->m_shifted_pc);
349	349	if(changed & EX2_1280) printf("[C] EX2_1280: %s\n", data & EX2_1280 ? "HIGH" : "LOW");
350	350	if(changed & EX1_1280) printf("[C] EX1_1280: %s\n", data & EX1_1280 ? "HIGH" : "LOW");
351	351	if(changed & LCD_CLK) printf("[C] LCD_CLK: %s\n", data & LCD_CLK ? "HIGH" : "LOW");
r29404	r29405
357	357	#endif
358	358
359	359	if (changed & LCD_CLK){
360		/* The LCD is interfaced by an 8-bit shift register (74HC4094). */
361		if (data & LCD_CLK){//CLK positive edge
362		shift_register_value = (shift_register_value << 1) \| ((data & LCD_DATA) >> 3);
363		//printf("[%08X] ", m_maincpu->m_shifted_pc);
364		//printf("[C] LCD CLK positive edge. shift_register=0x%02X\n", shift_register_value);
365		}
366		}
	360	/* The LCD is interfaced by an 8-bit shift register (74HC4094). */
	361	if (data & LCD_CLK){//CLK positive edge
	362	shift_register_value = (shift_register_value << 1) \| ((data & LCD_DATA) >> 3);
	363	//printf("[%08X] ", m_maincpu->m_shifted_pc);
	364	//printf("[C] LCD CLK positive edge. shift_register=0x%02X\n", shift_register_value);
	365	}
	366	}
367	367
368	368	if(changed & LCD_STROBE){
369		if (data & LCD_STROBE){ //STROBE positive edge
370		bool RS = (shift_register_value >> 1) & 1;
371		bool RW = (shift_register_value >> 2) & 1;
372		bool enable = (shift_register_value >> 3) & 1;
373		UINT8 lcd_data = shift_register_value & 0xF0;
	369	if (data & LCD_STROBE){ //STROBE positive edge
	370	bool RS = (shift_register_value >> 1) & 1;
	371	bool RW = (shift_register_value >> 2) & 1;
	372	bool enable = (shift_register_value >> 3) & 1;
	373	UINT8 lcd_data = shift_register_value & 0xF0;
374	374
375		if (enable && RW==0){
376		if (RS==0){
377		m_lcdc->control_write(space, 0, lcd_data);
378		} else {
379		m_lcdc->data_write(space, 0, lcd_data);
380		}
381		}
382		}
383		}
	375	if (enable && RW==0){
	376	if (RS==0){
	377	m_lcdc->control_write(space, 0, lcd_data);
	378	} else {
	379	m_lcdc->data_write(space, 0, lcd_data);
	380	}
	381	}
	382	}
	383	}
384	384	m_port_c = data;
385	385
386	386	break;
387	387	}
388	388	case AVR8_IO_PORTD:
389		{
390		if (data == m_port_d) break;
	389	{
	390	if (data == m_port_d) break;
391	391
392	392	#if LOG_PORTS
393	393	UINT8 old_port_d = m_port_d;
394	394	UINT8 changed = data ^ old_port_d;
395	395
396		printf("[%08X] ", m_maincpu->m_shifted_pc);
	396	printf("[%08X] ", m_maincpu->m_shifted_pc);
397	397	if(changed & PORTD_SCL) printf("[D] PORTD_SCL: %s\n", data & PORTD_SCL ? "HIGH" : "LOW");
398	398	if(changed & PORTD_SDA) printf("[D] PORTD_SDA: %s\n", data & PORTD_SDA ? "HIGH" : "LOW");
399	399	if(changed & EX_RX_1280) printf("[D] EX_RX_1280: %s\n", data & EX_RX_1280 ? "HIGH" : "LOW");
r29404	r29405
401	401	#endif
402	402
403	403	m_port_d = data;
404		break;
405		}
	404	break;
	405	}
406	406	case AVR8_IO_PORTE:
407		{
408		if (data == m_port_e) break;
	407	{
	408	if (data == m_port_e) break;
409	409
410	410	#if LOG_PORTS
411	411	UINT8 old_port_e = m_port_e;
412	412	UINT8 changed = data ^ old_port_e;
413	413
414		printf("[%08X] ", m_maincpu->m_shifted_pc);
	414	printf("[%08X] ", m_maincpu->m_shifted_pc);
415	415	if(changed & RX_1280) printf("[E] 1280-RX: %s\n", data & RX_1280 ? "HIGH" : "LOW");
416	416	if(changed & TX_1280) printf("[E] 1280-TX: %s\n", data & TX_1280 ? "HIGH" : "LOW");
417	417	if(changed & THERMO_SCK) printf("[E] THERMO-SCK: %s\n", data & THERMO_SCK ? "HIGH" : "LOW");
r29404	r29405
421	421	#endif
422	422
423	423	m_port_e = data;
424		break;
425		}
	424	break;
	425	}
426	426	case AVR8_IO_PORTF:
427		{
428		if (data == m_port_f) break;
	427	{
	428	if (data == m_port_f) break;
429	429
430	430	#if LOG_PORTS
431	431	UINT8 old_port_f = m_port_f;
432	432	UINT8 changed = data ^ old_port_f;
433	433
434		printf("[%08X] ", m_maincpu->m_shifted_pc);
	434	printf("[%08X] ", m_maincpu->m_shifted_pc);
435	435	if(changed & X_AXIS_DIR) printf("[F] X_AXIS_DIR: %s\n", data & X_AXIS_DIR ? "HIGH" : "LOW");
436	436	if(changed & X_AXIS_STEP) printf("[F] X_AXIS_STEP: %s\n", data & X_AXIS_STEP ? "HIGH" : "LOW");
437	437	if(changed & X_AXIS_EN) printf("[F] X_AXIS_EN: %s\n", data & X_AXIS_EN ? "HIGH" : "LOW");
r29404	r29405
443	443	#endif
444	444
445	445	m_port_f = data;
446		break;
447		}
	446	break;
	447	}
448	448	case AVR8_IO_PORTG:
449		{
450		if (data == m_port_g) break;
	449	{
	450	if (data == m_port_g) break;
451	451
452	452	UINT8 old_port_g = m_port_g;
453	453	UINT8 changed = data ^ old_port_g;
454	454
455	455	#if LOG_PORTS
456		printf("[%08X] ", m_maincpu->m_shifted_pc);
	456	printf("[%08X] ", m_maincpu->m_shifted_pc);
457	457	if(changed & EX4_1280) printf("[G] EX4_1280: %s\n", data & EX4_1280 ? "HIGH" : "LOW");
458	458	if(changed & EX3_1280) printf("[G] EX3_1280: %s\n", data & EX3_1280 ? "HIGH" : "LOW");
459	459	if(changed & B_AXIS_EN) printf("[G] B_AXIS_EN: %s\n", data & B_AXIS_EN ? "HIGH" : "LOW");
r29404	r29405
462	462	#endif
463	463
464	464	if(changed & BUZZ){
465		/* FIX-ME: What is the largest sample value allowed?
466		I'm using 0x3F based on what I see in src/mess/drivers/craft.c
467		But as the method is called "write_unsigned8", I guess we could have samples with values up to 0xFF, right?
468		Anyway... With the 0x3F value we'll get a sound that is not so loud, which may be less annoying... :-)
469		*/
470		UINT8 audio_sample = (data & BUZZ) ? 0x3F : 0;
471		m_dac->write_unsigned8(audio_sample << 1);
472		}
	465	/* FIX-ME: What is the largest sample value allowed?
	466	I'm using 0x3F based on what I see in src/mess/drivers/craft.c
	467	But as the method is called "write_unsigned8", I guess we could have samples with values up to 0xFF, right?
	468	Anyway... With the 0x3F value we'll get a sound that is not so loud, which may be less annoying... :-)
	469	*/
	470	UINT8 audio_sample = (data & BUZZ) ? 0x3F : 0;
	471	m_dac->write_unsigned8(audio_sample << 1);
	472	}
473	473
474	474	m_port_g = data;
475		break;
476		}
	475	break;
	476	}
477	477	case AVR8_IO_PORTH:
478		{
479		if (data == m_port_h) break;
	478	{
	479	if (data == m_port_h) break;
480	480
481	481	#if LOG_PORTS
482	482	UINT8 old_port_h = m_port_h;
483	483	UINT8 changed = data ^ old_port_h;
484	484
485		printf("[%08X] ", m_maincpu->m_shifted_pc);
	485	printf("[%08X] ", m_maincpu->m_shifted_pc);
486	486	if(changed & CUTOFF_TEST) printf("[H] CUTOFF_TEST: %s\n", data & CUTOFF_TEST ? "HIGH" : "LOW");
487	487	if(changed & CUTOFF_RESET) printf("[H] CUTOFF_RESET: %s\n", data & CUTOFF_RESET ? "HIGH" : "LOW");
488	488	if(changed & EX1_PWR_CHECK) printf("[H] EX1_PWR_CHECK: %s\n", data & EX1_PWR_CHECK ? "HIGH" : "LOW");
r29404	r29405
492	492	if(changed & SD_CD) printf("[H] SD_CD: %s\n", data & SD_CD ? "HIGH" : "LOW");
493	493	#endif
494	494
495		m_port_h = data;
496		break;
497		}
	495	m_port_h = data;
	496	break;
	497	}
498	498	case AVR8_IO_PORTJ:
499		{
500		if (data == m_port_j) break;
	499	{
	500	if (data == m_port_j) break;
501	501
502	502	#if LOG_PORTS
503	503	UINT8 old_port_j = m_port_j;
504	504	UINT8 changed = data ^ old_port_j;
505	505
506		printf("[%08X] ", m_maincpu->m_shifted_pc);
	506	printf("[%08X] ", m_maincpu->m_shifted_pc);
507	507
508	508	if(changed & BUTTON_CENTER) printf("[J] BUTTON_CENTER: %s\n", data & BUTTON_CENTER ? "HIGH" : "LOW");
509	509	if(changed & BUTTON_RIGHT) printf("[J] BUTTON_RIGHT: %s\n", data & BUTTON_RIGHT ? "HIGH" : "LOW");
r29404	r29405
514	514	if(changed & B_AXIS_POT) printf("[J] B_AXIS_POT: %s\n", data & B_AXIS_POT ? "HIGH" : "LOW");
515	515	#endif
516	516
517		m_port_j = data;
518		break;
519		}
	517	m_port_j = data;
	518	break;
	519	}
520	520	case AVR8_IO_PORTK:
521		{
522		if (data == m_port_k) break;
	521	{
	522	if (data == m_port_k) break;
523	523
524	524	#if LOG_PORTS
525	525	UINT8 old_port_k = m_port_k;
526	526	UINT8 changed = data ^ old_port_k;
527	527
528		printf("[%08X] ", m_maincpu->m_shifted_pc);
	528	printf("[%08X] ", m_maincpu->m_shifted_pc);
529	529
530	530	if(changed & Z_AXIS_DIR) printf("[K] Z_AXIS_DIR: %s\n", data & Z_AXIS_DIR ? "HIGH" : "LOW");
531	531	if(changed & Z_AXIS_STEP) printf("[K] Z_AXIS_STEP: %s\n", data & Z_AXIS_STEP ? "HIGH" : "LOW");
r29404	r29405
537	537	if(changed & HBP_THERM) printf("[K] HBP_THERM: %s\n", data & HBP_THERM ? "HIGH" : "LOW");
538	538	#endif
539	539
540		m_port_k = data;
541		break;
542		}
	540	m_port_k = data;
	541	break;
	542	}
543	543	case AVR8_IO_PORTL:
544		{
545		if (data == m_port_l) break;
	544	{
	545	if (data == m_port_l) break;
546	546
547	547	#if LOG_PORTS
548	548	UINT8 old_port_l = m_port_l;
549	549	UINT8 changed = data ^ old_port_l;
550	550
551		printf("[%08X] ", m_maincpu->m_shifted_pc);
	551	printf("[%08X] ", m_maincpu->m_shifted_pc);
552	552
553	553	if(changed & X_MIN) printf("[L] X_MIN: %s\n", data & X_MIN ? "HIGH" : "LOW");
554	554	if(changed & X_MAX) printf("[L] X_MAX: %s\n", data & X_MAX ? "HIGH" : "LOW");
r29404	r29405
560	560	if(changed & Z_MAX) printf("[L] Z_MAX: %s\n", data & Z_MAX ? "HIGH" : "LOW");
561	561	#endif
562	562
563		m_port_l = data;
564		break;
565		}
	563	m_port_l = data;
	564	break;
566	565	}
	566	}
567	567	}
568	568
569	569	/****************************************************\
r29404	r29405
605	605
606	606	void replicator_state::machine_reset()
607	607	{
608		shift_register_value = 0;
609		m_port_a = 0;
610		m_port_b = 0;
611		m_port_c = 0;
612		m_port_d = 0;
613		m_port_e = 0;
614		m_port_f = 0;
615		m_port_g = 0;
616		m_port_h = 0;
617		m_port_j = 0;
618		m_port_k = 0;
619		m_port_l = 0;
	608	shift_register_value = 0;
	609	m_port_a = 0;
	610	m_port_b = 0;
	611	m_port_c = 0;
	612	m_port_d = 0;
	613	m_port_e = 0;
	614	m_port_f = 0;
	615	m_port_g = 0;
	616	m_port_h = 0;
	617	m_port_j = 0;
	618	m_port_k = 0;
	619	m_port_l = 0;
620	620	}
621	621
622	622	const avr8_config atmega1280_config =
r29404	r29405
659	659	MCFG_CPU_AVR8_EFUSE(0xF4)
660	660	MCFG_CPU_AVR8_LOCK(0x0F)
661	661
662		/TODO: Add an ATMEGA8U2 for USB-Serial communications /
	662	/TODO: Add an ATMEGA8U2 for USB-Serial communications /
663	663
664	664	/* video hardware */
665	665	MCFG_SCREEN_ADD("screen", LCD)
r29404	r29405
679	679	MCFG_HD44780_LCD_SIZE(4, 20)
680	680
681	681	/* sound hardware */
682		/* A piezo is connected to the PORT G bit 5 (OC0B pin driven by Timer/Counter #4) */
	682	/* A piezo is connected to the PORT G bit 5 (OC0B pin driven by Timer/Counter #4) */
683	683	MCFG_SPEAKER_STANDARD_MONO("buzzer")
684	684	MCFG_SOUND_ADD("dac", DAC, 0)
685	685	MCFG_SOUND_ROUTE(0, "buzzer", 1.00)

trunk/src/mess/drivers/amstr_pc.c
r29404	r29405
531	531	MCFG_CPU_ADD("maincpu", V30, 8000000)
532	532	MCFG_CPU_PROGRAM_MAP(ppc512_map)
533	533	MCFG_CPU_IO_MAP(ppc512_io)
534
	534
535	535	MCFG_DEVICE_REMOVE("isa1")
536	536	MCFG_DEVICE_REMOVE("isa2")
537	537

trunk/src/mess/drivers/sapi1.c
r29404	r29405
87	87	required_ioport m_line3;
88	88	required_ioport m_line4;
89	89	required_device<cpu_device> m_maincpu;
90		public:
	90	public:
91	91	optional_device<palette_device> m_palette;
92	92	};
93	93
r29404	r29405
572	572	MCFG_SCREEN_VISIBLE_AREA(0, 406-1, 0, 249-1)
573	573	MCFG_SCREEN_UPDATE_DRIVER(sapi1_state, screen_update_sapi1)
574	574	MCFG_SCREEN_PALETTE("palette")
575
	575
576	576	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
577	577
578	578	/* internal ram */

trunk/src/mess/drivers/pasopia7.c
r29404	r29405
45	45	m_floppy(*this, "fdc:0:525hd"),
46	46	m_sn1(*this, "sn1"),
47	47	m_sn2(*this, "sn2"),
48		m_palette(*this, "palette")
	48	m_palette(*this, "palette")
49	49	{ }
50	50
51	51	required_device<cpu_device> m_maincpu;
r29404	r29405
60	60	required_device<sn76489a_device> m_sn1;
61	61	required_device<sn76489a_device> m_sn2;
62	62	required_device<palette_device> m_palette;
63
	63
64	64	DECLARE_READ8_MEMBER(vram_r);
65	65	DECLARE_WRITE8_MEMBER(vram_w);
66	66	DECLARE_WRITE8_MEMBER(pasopia7_memory_ctrl_w);
r29404	r29405
1017	1017	MCFG_SCREEN_SIZE(640, 480)
1018	1018	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 32-1)
1019	1019	MCFG_SCREEN_PALETTE("palette")
1020
	1020
1021	1021	MCFG_VIDEO_START_OVERRIDE(pasopia7_state,pasopia7)
1022	1022	MCFG_SCREEN_UPDATE_DRIVER(pasopia7_state, screen_update_pasopia7)
1023	1023	MCFG_PALETTE_ADD("palette", 8)
r29404	r29405
1037	1037	MCFG_VIDEO_START_OVERRIDE(pasopia7_state,pasopia7)
1038	1038	MCFG_SCREEN_UPDATE_DRIVER(pasopia7_state, screen_update_pasopia7)
1039	1039	MCFG_SCREEN_PALETTE("palette")
1040
	1040
1041	1041	MCFG_PALETTE_ADD("palette", 8)
1042	1042	MCFG_PALETTE_INIT_OWNER(pasopia7_state,p7_lcd)
1043	1043	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pasopia7 )

trunk/src/mess/drivers/ngp.c
r29404	r29405
841	841
842	842	MCFG_SCREEN_MODIFY("screen")
843	843	MCFG_SCREEN_PALETTE("k1ge:palette")
844
	844
845	845	MCFG_CARTSLOT_ADD("cart")
846	846	MCFG_CARTSLOT_EXTENSION_LIST("bin,ngp,npc,ngc")
847	847	MCFG_CARTSLOT_NOT_MANDATORY
r29404	r29405
860	860
861	861	MCFG_SCREEN_MODIFY("screen")
862	862	MCFG_SCREEN_PALETTE("k1ge:palette")
863
	863
864	864	MCFG_CARTSLOT_ADD("cart")
865	865	MCFG_CARTSLOT_EXTENSION_LIST("bin,ngp,npc,ngc")
866	866	MCFG_CARTSLOT_NOT_MANDATORY

trunk/src/mess/drivers/univac.c
r29404	r29405
149	149	MCFG_SCREEN_SIZE(640, 250)
150	150	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 249)
151	151	MCFG_SCREEN_PALETTE("palette")
152
	152
153	153	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
154	154	MACHINE_CONFIG_END
155	155

trunk/src/mess/drivers/hunter2.c
r29404	r29405
103	103	ADDRESS_MAP_UNMAP_HIGH
104	104	ADDRESS_MAP_GLOBAL_MASK(0xff)
105	105	AM_RANGE(0x00, 0x1f) AM_DEVREADWRITE("iotimer", nsc810_device, read, write) // device not yet emulated
106		// AM_RANGE(0x00, 0x00) AM_READ(port00_r)
107		// AM_RANGE(0x01, 0x01) AM_WRITE(port01_w)
108		// AM_RANGE(0x02, 0x02) AM_READ(port02_r)
109		// AM_RANGE(0x03, 0x1F) AM_WRITENOP
	106	// AM_RANGE(0x00, 0x00) AM_READ(port00_r)
	107	// AM_RANGE(0x01, 0x01) AM_WRITE(port01_w)
	108	// AM_RANGE(0x02, 0x02) AM_READ(port02_r)
	109	// AM_RANGE(0x03, 0x1F) AM_WRITENOP
110	110	AM_RANGE(0x20, 0x20) AM_DEVWRITE("lcdc", hd61830_device, data_w)
111	111	AM_RANGE(0x21, 0x21) AM_DEVREADWRITE("lcdc", hd61830_device, status_r, control_w)
112	112	AM_RANGE(0x3e, 0x3e) AM_DEVREAD("lcdc", hd61830_device, data_r)
r29404	r29405
255	255	WRITE8_MEMBER( hunter2_state::port81_w )
256	256	{
257	257	m_rs232->write_txd(data & 0x01);
258		// logerror("TXD write %02x\n",data);
	258	// logerror("TXD write %02x\n",data);
259	259	}
260	260
261	261	WRITE8_MEMBER( hunter2_state::port82_w )
262	262	{
263	263	m_rs232->write_dtr(data & 0x01);
264		// logerror("DTR write %02x\n",data);
	264	// logerror("DTR write %02x\n",data);
265	265	}
266	266
267	267	WRITE8_MEMBER( hunter2_state::port84_w )
268	268	{
269	269	m_rs232->write_rts(data & 0x01);
270		// logerror("RTS write %02x\n",data);
	270	// logerror("RTS write %02x\n",data);
271	271	}
272	272
273	273	WRITE8_MEMBER( hunter2_state::port86_w )
r29404	r29405
277	277
278	278	/*
279	279	Bit 0 = Enable normal interrupts
280		Bit 1 = Enable RSTC interrupts
	280	Bit 1 = Enable RSTC interrupts
281	281	Bit 2 = Enable RSTB interrupts
282	282	Bit 3 = Enable RSTA interrupts
283	283	*/
r29404	r29405
399	399	MCFG_SCREEN_SIZE(240, 128)
400	400	MCFG_SCREEN_VISIBLE_AREA(0, 239, 0, 63)
401	401	MCFG_SCREEN_PALETTE("palette")
402
	402
403	403	MCFG_DEFAULT_LAYOUT(layout_lcd)
404	404	MCFG_PALETTE_ADD("palette", 2)
405	405	MCFG_PALETTE_INIT_OWNER(hunter2_state, hunter2)

trunk/src/mess/drivers/jonos.c
r29404	r29405
131	131	MCFG_SCREEN_SIZE(640, 300)
132	132	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 299)
133	133	MCFG_SCREEN_PALETTE("palette")
134
	134
135	135	MCFG_GFXDECODE_ADD("gfxdecode", "palette", jonos)
136	136	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
137	137	MACHINE_CONFIG_END

trunk/src/mess/drivers/at.c
r29404	r29405
24	24	ADDRESS_MAP_END
25	25
26	26	static ADDRESS_MAP_START( ps2m30286_map, AS_PROGRAM, 16, at_state)
27		AM_RANGE(0x000000, 0x09ffff) AM_RAMBANK("bank10")
	27	AM_RANGE(0x000000, 0x09ffff) AM_RAMBANK("bank10")
28	28	AM_RANGE(0x0c0000, 0x0c7fff) AM_ROM
29	29	AM_RANGE(0x0c8000, 0x0cffff) AM_ROM
30	30	AM_RANGE(0x0d0000, 0x0dffff) AM_RAM
r29404	r29405
130	130
131	131	READ8_MEMBER( at_state::ps1_kbdc_r )
132	132	{
133		UINT8 ret;
134		if(offset == 0) ret = at_keybc_r(space, offset, mem_mask);
135		else ret = ps2_portb_r(space,offset, mem_mask);
	133	UINT8 ret;
	134	if(offset == 0) ret = at_keybc_r(space, offset, mem_mask);
	135	else ret = ps2_portb_r(space,offset, mem_mask);
136	136	return ret;
137	137	}
138	138
r29404	r29405
461	461
462	462	MCFG_QUANTUM_TIME(attotime::from_hz(60))
463	463	MCFG_FRAGMENT_ADD( pcvideo_vga )
464
	464
465	465	MCFG_FRAGMENT_ADD( at_motherboard )
466	466
467	467	MCFG_ISA16_BUS_ADD("isabus", ":maincpu", isabus_intf)

trunk/src/mess/drivers/ql.c
r29404	r29405
289	289	case 0x0002 : result=m_fdc->read(space, offset); break;
290	290	case 0x0003 : result=m_fdc->read(space, offset); break;
291	291	case 0x000C : if(IS_SANDY_DISK(m_disk_type))
292		result = (m_mouse_int ^ MOUSE_DIRX) \| m_mouseb->read() \| 0x01; break;
	292	result = (m_mouse_int ^ MOUSE_DIRX) \| m_mouseb->read() \| 0x01; break;
293	293	case 0x0010 : if(IS_SANDY_DISK(m_disk_type))
294		m_mouse_int &= ~MOUSE_INT_MASK; break;
	294	m_mouse_int &= ~MOUSE_INT_MASK; break;
295	295	default : logerror("%s DiskIO undefined read : from %08X\n",machine().describe_context(),m_disk_io_base+offset); break;
296	296	}
297	297
r29404	r29405
314	314	case 0x0008 : if(IS_SANDY_DISK(m_disk_type))
315	315	sandy_print_char(data); break;
316	316	case 0x0010 : if(IS_SANDY_DISK(m_disk_type))
317		m_mouse_int &= ~MOUSE_INT_MASK; break;
	317	m_mouse_int &= ~MOUSE_INT_MASK; break;
318	318	case 0x2000 : if(m_disk_type==DISK_TYPE_TRUMP)
319	319	trump_card_set_control(data);break;
320	320	default : logerror("%s DiskIO undefined write : %02X to %08X\n",machine().describe_context(),data,m_disk_io_base+offset); break;
r29404	r29405
382	382	if(data & SANDY_PRINTER_INTMASK)
383	383	m_zx8302->extint_w(ASSERT_LINE);
384	384	}
385
	385
386	386	m_disk_io_byte=data;
387	387	}
388	388
r29404	r29405
390	390	{
391	391	// latch the data until it's strobed out
392	392	m_printer_char=data;
393
394		// m_centronics->write(data);
	393
	394	// m_centronics->write(data);
395	395	}
396	396
397	397	WRITE_LINE_MEMBER( ql_state::sandy_printer_busy )
r29404	r29405
423	423
424	424	void ql_state::mouse_tick()
425	425	{
426		UINT8 x = m_mousex->read();
427		UINT8 y = m_mousey->read();
428		UINT8 do_int = 0;
	426	UINT8 x = m_mousex->read();
	427	UINT8 y = m_mousey->read();
	428	UINT8 do_int = 0;
429	429
430	430	//m_mouse_int = 0;
431	431
432	432	// Set X interupt flag and direction if x has changed
433		if (x > m_ql_mouse_x)
	433	if (x > m_ql_mouse_x)
434	434	{
435	435	m_mouse_int \|= MOUSE_INTX;
436	436	m_mouse_int \|= MOUSE_DIRX;
r29404	r29405
442	442	}
443	443
444	444	// Set Y interupt flag and direction if y has changed
445		if (y > m_ql_mouse_y)
	445	if (y > m_ql_mouse_y)
446	446	{
447	447	m_mouse_int \|= MOUSE_INTY;
448	448	m_mouse_int &= ~MOUSE_DIRY;
r29404	r29405
463	463	do_int = 1;
464	464	else
465	465	do_int = IS_SANDY_DISK(m_disk_type) && (m_disk_io_byte & SANDY_MOUSE_INTMASK);
466
	466
467	467	//logerror("m_mouse_int=%02X, MOUSE_INT_MASK=%02X, m_disk_io_byte=%02X, (m_disk_io_byte & SANDY_MOUSE_INTMASK)=%02x\n",m_mouse_int,MOUSE_INT_MASK,m_disk_io_byte,(m_disk_io_byte & SANDY_MOUSE_INTMASK));
468
	468
469	469	// if mouse moved trigger external int
470	470	if((m_mouse_int & MOUSE_INT_MASK) && do_int)
471	471	{
r29404	r29405
477	477	{
478	478	UINT8 result = 0;
479	479	UINT8 buttons;
480
	480
481	481	switch (offset)
482	482	{
483	483	// 0x1bf9c, button status
484		case 0x00 :
	484	case 0x00 :
485	485	buttons = m_mouseb->read();
486	486	result = ((buttons & MOUSE_RIGHT) << 2) \| ((buttons & MOUSE_LEFT) << 2);
487	487	break;
488
	488
489	489	// 0x1bfbc, direction status
490		case 0x20 :
	490	case 0x20 :
491	491	result = ((m_mouse_int & MOUSE_INTX) >> 5) \| ((m_mouse_int & MOUSE_INTY) >> 1) \|
492		((m_mouse_int & MOUSE_DIRX) >> 1) \| ((m_mouse_int & MOUSE_DIRY) >> 4);
	492	((m_mouse_int & MOUSE_DIRX) >> 1) \| ((m_mouse_int & MOUSE_DIRY) >> 4);
493	493	break;
494		case 0x22 :
	494	case 0x22 :
495	495	m_mouse_int &= ~MOUSE_INT_MASK;
496	496	break;
497	497	}
498
	498
499	499	return result;
500	500	}
501	501
r29404	r29405
664	664	PORT_CONFNAME( QIMI_PORT_MASK, QIMI_NONE, "QIMI enabled")
665	665	PORT_CONFSETTING( QIMI_NONE, "No" )
666	666	PORT_CONFSETTING( QIMI_MOUSE, "Yes" )
667
	667
668	668	PORT_CONFNAME( DISK_TYPE_MASK, DISK_TYPE_NONE, "Disk interface select" )
669	669	PORT_CONFSETTING(DISK_TYPE_NONE, DEF_STR( None ))
670	670	PORT_CONFSETTING(DISK_TYPE_TRUMP, "Miracle Trump card")
671	671	PORT_CONFSETTING(DISK_TYPE_SANDY_SD, "Sandy Superdisk")
672	672	PORT_CONFSETTING(DISK_TYPE_SANDY_SQB,"Sandy SuperQBoard")
673	673
674
	674
675	675	PORT_START(MOUSEX_TAG)
676		PORT_BIT( 0xff, 0x00, IPT_MOUSE_X ) PORT_SENSITIVITY(50) PORT_KEYDELTA(5) PORT_MINMAX(0, 255) PORT_PLAYER(1)
	676	PORT_BIT( 0xff, 0x00, IPT_MOUSE_X ) PORT_SENSITIVITY(50) PORT_KEYDELTA(5) PORT_MINMAX(0, 255) PORT_PLAYER(1)
677	677
678	678	PORT_START(MOUSEY_TAG)
679		PORT_BIT( 0xff, 0x00, IPT_MOUSE_Y ) PORT_SENSITIVITY(50) PORT_KEYDELTA(5) PORT_MINMAX(0, 255) PORT_PLAYER(1)
	679	PORT_BIT( 0xff, 0x00, IPT_MOUSE_Y ) PORT_SENSITIVITY(50) PORT_KEYDELTA(5) PORT_MINMAX(0, 255) PORT_PLAYER(1)
680	680
681	681	PORT_START(MOUSEB_TAG) /* Mouse buttons */
682		PORT_BIT( MOUSE_RIGHT, IP_ACTIVE_LOW, IPT_BUTTON1) PORT_NAME("Mouse Button 1") PORT_CODE(MOUSECODE_BUTTON1)
683		PORT_BIT( MOUSE_LEFT, IP_ACTIVE_LOW, IPT_BUTTON2) PORT_NAME("Mouse Button 2") PORT_CODE(MOUSECODE_BUTTON2)
684		PORT_BIT( MOUSE_MIDDLE, IP_ACTIVE_LOW, IPT_BUTTON3) PORT_NAME("Mouse Button 3") PORT_CODE(MOUSECODE_BUTTON3)
	682	PORT_BIT( MOUSE_RIGHT, IP_ACTIVE_LOW, IPT_BUTTON1) PORT_NAME("Mouse Button 1") PORT_CODE(MOUSECODE_BUTTON1)
	683	PORT_BIT( MOUSE_LEFT, IP_ACTIVE_LOW, IPT_BUTTON2) PORT_NAME("Mouse Button 2") PORT_CODE(MOUSECODE_BUTTON2)
	684	PORT_BIT( MOUSE_MIDDLE, IP_ACTIVE_LOW, IPT_BUTTON3) PORT_NAME("Mouse Button 3") PORT_CODE(MOUSECODE_BUTTON3)
685	685
686	686	INPUT_PORTS_END
687	687
r29404	r29405
1031	1031	m_printer_char=0;
1032	1032	m_disk_io_byte=0;
1033	1033	m_mouse_int = 0;
1034
	1034
1035	1035	logerror("Configuring RAM %d\n",m_ram->size() / 1024);
1036
	1036
1037	1037	// configure RAM
1038	1038	switch (m_ram->size())
1039	1039	{
r29404	r29405
1086	1086	break;
1087	1087	}
1088	1088
1089
	1089
1090	1090	// QIMI QL Internal Mouse Interface
1091	1091	if (m_config->read() & QIMI_MOUSE)
1092		{
	1092	{
1093	1093	logerror("QIMI enabled\n");
1094	1094	program.install_read_handler(QIMI_IO_BASE, QIMI_IO_END, 0, 0, read8_delegate(FUNC(ql_state::qimi_io_r), this));
1095		program.install_write_handler(QIMI_IO_BASE, QIMI_IO_END, 0, 0, write8_delegate(FUNC(ql_state::qimi_io_w), this));
	1095	program.install_write_handler(QIMI_IO_BASE, QIMI_IO_END, 0, 0, write8_delegate(FUNC(ql_state::qimi_io_w), this));
1096	1096	}
1097	1097	}
1098	1098
r29404	r29405
1129	1129	MCFG_DEVICE_ADD(ZX8301_TAG, ZX8301, X1)
1130	1130	MCFG_ZX8301_CPU(M68008_TAG)
1131	1131	MCFG_ZX8301_VSYNC_CALLBACK(DEVWRITELINE(ZX8302_TAG, zx8302_device, vsync_w))
1132
	1132
1133	1133	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
1134
	1134
1135	1135	MCFG_DEVICE_ADD(ZX8302_TAG, ZX8302, X1)
1136	1136	MCFG_ZX8302_RTC_CLOCK(X2)
1137	1137	MCFG_ZX8302_OUT_IPL1L_CB(INPUTLINE(M68008_TAG, M68K_IRQ_2))
r29404	r29405
1149	1149	MCFG_ZX8302_OUT_RAW2_CB(WRITELINE(ql_state, zx8302_raw2_w))
1150	1150	MCFG_ZX8302_IN_RAW2_CB(READLINE(ql_state, zx8302_raw2_r))
1151	1151	MCFG_LEGACY_FLOPPY_2_DRIVES_ADD(ql_floppy_interface)
1152
	1152
1153	1153	MCFG_WD1772_ADD(WD1772_TAG,ql_wd17xx_interface)
1154	1154	MCFG_MICRODRIVE_ADD(MDV_1, mdv1_config)
1155	1155	MCFG_MICRODRIVE_COMMS_OUT_CALLBACK(DEVWRITELINE(MDV_2, microdrive_image_device, comms_in_w))

trunk/src/mess/drivers/saturn.c
r29404	r29405
87	87
88	88	required_device<sat_cart_slot_device> m_exp;
89	89	required_device<nvram_device> m_nvram;
90		required_device<nvram_device> m_smpc_nv; // TODO: move this in the base class saturn_state and add it to stv in MAME
	90	required_device<nvram_device> m_smpc_nv; // TODO: move this in the base class saturn_state and add it to stv in MAME
91	91	};
92	92
93	93
r29404	r29405
548	548	/* TODO: if you change the driver configuration then NVRAM contents gets screwed, needs mods in MAME framework */
549	549	void sat_console_state::nvram_init(nvram_device &nvram, void *data, size_t size)
550	550	{
551		static const UINT8 init[64] = {
	551	static const UINT8 init[64] = {
552	552	'B', 'a', 'c', 'k', 'U', 'p', 'R', 'a', 'm', ' ', 'F', 'o', 'r', 'm', 'a', 't',
553	553	'B', 'a', 'c', 'k', 'U', 'p', 'R', 'a', 'm', ' ', 'F', 'o', 'r', 'm', 'a', 't',
554	554	'B', 'a', 'c', 'k', 'U', 'p', 'R', 'a', 'm', ' ', 'F', 'o', 'r', 'm', 'a', 't',
555	555	'B', 'a', 'c', 'k', 'U', 'p', 'R', 'a', 'm', ' ', 'F', 'o', 'r', 'm', 'a', 't', };
556
	556
557	557	memset(data, 0x00, size);
558	558	memcpy(data, init, sizeof(init));
559	559	}
r29404	r29405
894	894	ROM_START(hisaturn)
895	895	ROM_REGION( 0x480000, "maincpu", ROMREGION_ERASEFF ) /* SH2 code */
896	896	ROM_SYSTEM_BIOS(0, "102", "v1.02 (950519)")
897		ROMX_LOAD( "mpr-18100.bin", 0x000000, 0x080000, CRC(3408dbf4) SHA1(8a22710e09ce75f39625894366cafe503ed1942d), ROM_BIOS(1))
	897	ROMX_LOAD( "mpr-18100.bin", 0x000000, 0x080000, CRC(3408dbf4) SHA1(8a22710e09ce75f39625894366cafe503ed1942d), ROM_BIOS(1))
898	898	ROM_SYSTEM_BIOS(1, "101", "v1.01 (950130)")
899	899	ROMX_LOAD("hisaturn.bin", 0x00000000, 0x00080000, CRC(721e1b60) SHA1(49d8493008fa715ca0c94d99817a5439d6f2c796), ROM_BIOS(2))
900	900	ROM_REGION( 0x080000, "slave", 0 ) /* SH2 code */

trunk/src/mess/drivers/apple2gs.c
r29404	r29405
380	380	MCFG_ES5503_OUTPUT_CHANNELS(2)
381	381	MCFG_ES5503_IRQ_FUNC(WRITELINE(apple2gs_state, apple2gs_doc_irq))
382	382	MCFG_ES5503_ADC_FUNC(READ8(apple2gs_state, apple2gs_adc_read))
383
	383
384	384	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
385	385	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
386	386

trunk/src/mess/drivers/lola8a.c
r29404	r29405
56	56	private:
57	57	UINT8 m_portb;
58	58	required_device<cassette_image_device> m_cass;
59		public:
	59	public:
60	60	required_device<palette_device> m_palette;
61	61	};
62	62

trunk/src/mess/drivers/molecular.c
r29404	r29405
88	88
89	89	UINT8 app_ram_enable;
90	90	UINT8 file_ram_enable;
91
	91
92	92	DECLARE_PALETTE_INIT(molecula);
93	93
94	94	protected:

trunk/src/mess/drivers/hp48.c
r29404	r29405
767	767	keyboard layout for 49 G model
768	768
769	769	-------------------------------------------------
770		\| F1 \| F2 \| F3 \| F4 \| F5 \| F6 \|
	770	\| F1 \| F2 \| F3 \| F4 \| F5 \| F6 \|
771	771	\|-----------------------------------------------\|
772	772	\| APPS \| MODE \| TOOL \| up \|
773	773	\|---------+--------+--------\| left right \|
774	774	\| VAR \| STO \| NXT \| down \|
775	775	\|---------+--------+--------+-------------------\|
776		\| HIST \| CAT \| EQW \| SYMB \| <= \|
	776	\| HIST \| CAT \| EQW \| SYMB \| <= \|
777	777	\|---------+--------+--------+---------+---------\|
778		\| y^x \| sqrt \| SIN \| COS \| TAN \|
	778	\| y^x \| sqrt \| SIN \| COS \| TAN \|
779	779	\|---------+--------+--------+---------+---------\|
780		\| EEX \| +/- \| X \| 1/x \| / \|
	780	\| EEX \| +/- \| X \| 1/x \| / \|
781	781	\|---------+--------+--------+---------+---------\|
782		\| alpha \| 7 \| 8 \| 9 \| * \|
	782	\| alpha \| 7 \| 8 \| 9 \| * \|
783	783	\|---------+--------+--------+---------+---------\|
784		\| blue \| 4 \| 5 \| 6 \| - \|
	784	\| blue \| 4 \| 5 \| 6 \| - \|
785	785	\|---------+--------+--------+---------+---------\|
786		\| red \| 1 \| 2 \| 3 \| + \|
	786	\| red \| 1 \| 2 \| 3 \| + \|
787	787	\|---------+--------+--------+---------+---------\|
788		\| ON \| 0 \| . \| SPC \| ENTER \|
	788	\| ON \| 0 \| . \| SPC \| ENTER \|
789	789	-------------------------------------------------
790	790
791	791	* 51 keys
r29404	r29405
798	798
799	799	static INPUT_PORTS_START( hp49g_kbd )
800	800
801		PORT_START( "LINE0" ) /* OUT = 0x001 */
	801	PORT_START( "LINE0" ) /* OUT = 0x001 */
802	802
803	803	PORT_BIT ( 1, IP_ACTIVE_HIGH, IPT_KEYBOARD )
804	804	PORT_NAME ( "ENTER ANS NUM")
805	805	PORT_CODE ( KEYCODE_ENTER )
806	806
807	807	PORT_BIT ( 2, IP_ACTIVE_HIGH, IPT_KEYBOARD )
808		PORT_NAME ( "+ { } \xC2\xAB \xC2\xBB") /* << >> */
	808	PORT_NAME ( "+ { } \xC2\xAB \xC2\xBB") /* << >> */
809	809	PORT_CODE ( KEYCODE_EQUALS )
810	810	PORT_CODE ( KEYCODE_PLUS_PAD )
811	811
r29404	r29405
826	826	PORT_CODE ( KEYCODE_Z)
827	827
828	828	PORT_BIT ( 32, IP_ACTIVE_HIGH, IPT_KEYBOARD )
829		PORT_NAME ( "TAN ATAN \xE2\x88\xAB U") /* integral */
	829	PORT_NAME ( "TAN ATAN \xE2\x88\xAB U") /* integral */
830	830	PORT_CODE ( KEYCODE_U )
831	831
832	832	PORT_BIT ( 64, IP_ACTIVE_HIGH, IPT_KEYBOARD )
833		PORT_NAME ( "\xE2\x87\x90 DEL CLEAR") /* double left arrow */
	833	PORT_NAME ( "\xE2\x87\x90 DEL CLEAR") /* double left arrow */
834	834	PORT_CODE ( KEYCODE_BACKSPACE )
835	835	PORT_CODE ( KEYCODE_DEL )
836	836	PORT_CODE ( KEYCODE_DEL_PAD )
r29404	r29405
839	839	PORT_NAME ( "NXT PREV PASTE L")
840	840	PORT_CODE ( KEYCODE_L )
841	841
842		PORT_BIT ( 0x7f00, 0, IPT_UNUSED )
	842	PORT_BIT ( 0x7f00, 0, IPT_UNUSED )
843	843
844	844
845		PORT_START( "LINE1" ) /* OUT = 0x002 */
	845	PORT_START( "LINE1" ) /* OUT = 0x002 */
846	846
847	847	PORT_BIT ( 1, IP_ACTIVE_HIGH, IPT_KEYBOARD )
848		PORT_NAME ( "SPC \xCF\x80 ,") /* pi */
	848	PORT_NAME ( "SPC \xCF\x80 ,") /* pi */
849	849	PORT_CODE ( KEYCODE_SPACE )
850	850
851	851	PORT_BIT ( 2, IP_ACTIVE_HIGH, IPT_KEYBOARD )
r29404	r29405
864	864	PORT_CODE ( KEYCODE_9_PAD )
865	865
866	866	PORT_BIT ( 16, IP_ACTIVE_HIGH, IPT_KEYBOARD )
867		PORT_NAME ( "1/x \xE2\x89\xA5 > Y") /* >= */
	867	PORT_NAME ( "1/x \xE2\x89\xA5 > Y") /* >= */
868	868	PORT_CODE ( KEYCODE_Y )
869	869
870	870	PORT_BIT ( 32, IP_ACTIVE_HIGH, IPT_KEYBOARD )
871		PORT_NAME ( "COS ACOS \xE2\x88\x82 T") /* delta */
	871	PORT_NAME ( "COS ACOS \xE2\x88\x82 T") /* delta */
872	872	PORT_CODE ( KEYCODE_T )
873	873
874	874	PORT_BIT ( 64, IP_ACTIVE_HIGH, IPT_KEYBOARD )
r29404	r29405
879	879	PORT_NAME ( "STO\xE2\x8A\xB3 RCL CUT K")
880	880	PORT_CODE ( KEYCODE_K )
881	881
882		PORT_BIT ( 0x7f00, 0, IPT_UNUSED )
	882	PORT_BIT ( 0x7f00, 0, IPT_UNUSED )
883	883
884	884
885		PORT_START( "LINE2" ) /* OUT = 0x004 */
	885	PORT_START( "LINE2" ) /* OUT = 0x004 */
886	886
887	887	PORT_BIT ( 1, IP_ACTIVE_HIGH, IPT_KEYBOARD )
888	888	PORT_NAME ( ". : : \xE2\x86\xb5") /* return arrow */
r29404	r29405
904	904	PORT_CODE ( KEYCODE_8_PAD )
905	905
906	906	PORT_BIT ( 16, IP_ACTIVE_HIGH, IPT_KEYBOARD )
907		PORT_NAME ( "X \xE2\x89\xA4 < X") /* <= */
	907	PORT_NAME ( "X \xE2\x89\xA4 < X") /* <= */
908	908	PORT_CODE ( KEYCODE_X )
909	909
910	910	PORT_BIT ( 32, IP_ACTIVE_HIGH, IPT_KEYBOARD )
r29404	r29405
919	919	PORT_NAME ( "VAR UPDIR COPY J")
920	920	PORT_CODE ( KEYCODE_J )
921	921
922		PORT_BIT ( 0x7f00, 0, IPT_UNUSED )
	922	PORT_BIT ( 0x7f00, 0, IPT_UNUSED )
923	923
924	924
925		PORT_START( "LINE3" ) /* OUT = 0x008 */
	925	PORT_START( "LINE3" ) /* OUT = 0x008 */
926	926
927	927	PORT_BIT ( 1, IP_ACTIVE_HIGH, IPT_KEYBOARD )
928		PORT_NAME ( "0 \xE2\x88\x9E \xE2\x86\x92") /* infinity, right arrow */
	928	PORT_NAME ( "0 \xE2\x88\x9E \xE2\x86\x92") /* infinity, right arrow */
929	929	PORT_CODE ( KEYCODE_0 )
930	930	PORT_CODE ( KEYCODE_0_PAD )
931	931
r29404	r29405
945	945	PORT_CODE ( KEYCODE_7_PAD )
946	946
947	947	PORT_BIT ( 16, IP_ACTIVE_HIGH, IPT_KEYBOARD )
948		PORT_NAME ( "+/- \xE2\x89\xA0 = W") /* =/ */
	948	PORT_NAME ( "+/- \xE2\x89\xA0 = W") /* =/ */
949	949	PORT_CODE ( KEYCODE_W )
950	950
951	951	PORT_BIT ( 32, IP_ACTIVE_HIGH, IPT_KEYBOARD )
952		PORT_NAME ( "\xE2\x88\x9A x^2 sqrt(x,y) R") /* square root */
	952	PORT_NAME ( "\xE2\x88\x9A x^2 sqrt(x,y) R") /* square root */
953	953	PORT_CODE ( KEYCODE_R )
954	954
955	955	PORT_BIT ( 64, IP_ACTIVE_HIGH, IPT_KEYBOARD )
r29404	r29405
960	960	PORT_NAME ( "TOOL i \| I")
961	961	PORT_CODE ( KEYCODE_I )
962	962
963		PORT_BIT ( 0x7f00, 0, IPT_UNUSED )
	963	PORT_BIT ( 0x7f00, 0, IPT_UNUSED )
964	964
965	965
966		PORT_START( "LINE4" ) /* OUT = 0x010 */
	966	PORT_START( "LINE4" ) /* OUT = 0x010 */
967	967
968	968	PORT_BIT ( 16, IP_ACTIVE_HIGH, IPT_KEYBOARD )
969	969	PORT_NAME ( "EEX 10^x LOG V")
r29404	r29405
981	981	PORT_NAME ( "MODE CUSTOM END H")
982	982	PORT_CODE ( KEYCODE_H )
983	983
984		PORT_BIT ( 0x7f0f, 0, IPT_UNUSED )
	984	PORT_BIT ( 0x7f0f, 0, IPT_UNUSED )
985	985
986	986
987		PORT_START( "LINE5" ) /* OUT = 0x020 */
	987	PORT_START( "LINE5" ) /* OUT = 0x020 */
988	988
989	989	PORT_BIT ( 1, IP_ACTIVE_HIGH, IPT_KEYBOARD )
990	990	PORT_NAME ( "F1 Y= A")
r29404	r29405
1020	1020	PORT_NAME ( "APPS FILES BEGIN G")
1021	1021	PORT_CODE ( KEYCODE_G )
1022	1022
1023		PORT_BIT ( 0x7f40, 0, IPT_UNUSED )
	1023	PORT_BIT ( 0x7f40, 0, IPT_UNUSED )
1024	1024
1025	1025
1026		PORT_START( "LINE6" ) /* OUT = 0x040 */
	1026	PORT_START( "LINE6" ) /* OUT = 0x040 */
1027	1027
1028	1028	PORT_BIT ( 1, IP_ACTIVE_HIGH, IPT_KEYBOARD )
1029	1029	PORT_NAME ( "\xE2\x86\x92") /* right arrow */
r29404	r29405
1034	1034	PORT_CODE ( KEYCODE_DOWN )
1035	1035
1036	1036	PORT_BIT ( 4, IP_ACTIVE_HIGH, IPT_KEYBOARD )
1037		PORT_NAME ( "\xE2\x86\x90") /* left arrow */
	1037	PORT_NAME ( "\xE2\x86\x90") /* left arrow */
1038	1038	PORT_CODE ( KEYCODE_LEFT )
1039	1039
1040	1040	PORT_BIT ( 8, IP_ACTIVE_HIGH, IPT_KEYBOARD )
1041	1041	PORT_NAME ( "\xE2\x86\x91") /* up arrow */
1042	1042	PORT_CODE ( KEYCODE_UP )
1043	1043
1044		PORT_BIT ( 0x7ff0, 0, IPT_UNUSED )
	1044	PORT_BIT ( 0x7ff0, 0, IPT_UNUSED )
1045	1045
1046	1046
1047		PORT_START( "LINE7" ) /* OUT = 0x080 */
	1047	PORT_START( "LINE7" ) /* OUT = 0x080 */
1048	1048
1049	1049	PORT_BIT ( 2, IP_ACTIVE_HIGH, IPT_KEYBOARD )
1050	1050	PORT_NAME ( "right shift")
r29404	r29405
1055	1055	PORT_CODE ( KEYCODE_LSHIFT )
1056	1056
1057	1057	PORT_BIT ( 8, IP_ACTIVE_HIGH, IPT_KEYBOARD )
1058		PORT_NAME ( "\xCE\xB1 USER ENTRY") /* alpha */
	1058	PORT_NAME ( "\xCE\xB1 USER ENTRY") /* alpha */
1059	1059	PORT_CODE ( KEYCODE_LALT )
1060	1060
1061		PORT_BIT ( 0x7ff1, 0, IPT_UNUSED )
	1061	PORT_BIT ( 0x7ff1, 0, IPT_UNUSED )
1062	1062
1063	1063
1064		PORT_START( "LINE8" ) /* OUT = 0x100 */
	1064	PORT_START( "LINE8" ) /* OUT = 0x100 */
1065	1065
1066		PORT_BIT ( 0xffff, 0, IPT_UNUSED )
	1066	PORT_BIT ( 0xffff, 0, IPT_UNUSED )
1067	1067
1068	1068
1069		PORT_START( "ON" ) /* ON key, appears on all OUT lines */
	1069	PORT_START( "ON" ) /* ON key, appears on all OUT lines */
1070	1070
1071	1071	PORT_BIT ( 0x8000, IP_ACTIVE_HIGH, IPT_KEYBOARD )
1072	1072	PORT_NAME ( "ON CONT OFF CANCEL" )
1073	1073	PORT_CODE ( KEYCODE_ESC )
1074	1074	PORT_CODE ( KEYCODE_HOME )
1075	1075
1076		PORT_BIT ( 0x7fff, 0, IPT_UNUSED )
	1076	PORT_BIT ( 0x7fff, 0, IPT_UNUSED )
1077	1077
1078	1078	INPUT_PORTS_END
1079	1079
r29404	r29405
1109	1109	INPUT_PORTS_END
1110	1110
1111	1111	static INPUT_PORTS_START( hp49g )
1112		PORT_INCLUDE( hp49g_kbd )
1113		PORT_INCLUDE( hp48_battery )
	1112	PORT_INCLUDE( hp49g_kbd )
	1113	PORT_INCLUDE( hp48_battery )
1114	1114	INPUT_PORTS_END
1115	1115
1116	1116
r29404	r29405
1356	1356	MCFG_DEFAULT_LAYOUT ( layout_hp49g )
1357	1357
1358	1358	/* serial I/O */
1359		//MCFG_XMODEM_ADD( "rs232_x", hp48_xmodem_rs232_conf )
1360		//MCFG_KERMIT_ADD( "rs232_k", hp48_kermit_rs232_conf )
	1359	//MCFG_XMODEM_ADD( "rs232_x", hp48_xmodem_rs232_conf )
	1360	//MCFG_KERMIT_ADD( "rs232_k", hp48_kermit_rs232_conf )
1361	1361	MACHINE_CONFIG_END
1362	1362
1363	1363

trunk/src/mess/drivers/z100.c
r29404	r29405
163	163	m_pics(*this, "pic8259_slave"),
164	164	m_fdc(*this, "z207_fdc"),
165	165	m_crtc(*this, "crtc"),
166		m_palette(*this, "palette")
	166	m_palette(*this, "palette")
167	167	{ }
168	168
169	169	required_device<cpu_device> m_maincpu;
r29404	r29405
174	174	required_device<fd1797_device> m_fdc;
175	175	required_device<mc6845_device> m_crtc;
176	176	required_device<palette_device> m_palette;
177
	177
178	178	DECLARE_READ8_MEMBER(z100_vram_r);
179	179	DECLARE_WRITE8_MEMBER(z100_vram_w);
180	180	DECLARE_READ8_MEMBER(keyb_data_r);
r29404	r29405
737	737	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
738	738	MCFG_SCREEN_UPDATE_DRIVER(z100_state, screen_update_z100)
739	739	MCFG_SCREEN_PALETTE("palette")
740
	740
741	741	MCFG_PALETTE_ADD("palette", 8)
742	742
743	743	/* Devices */

trunk/src/mess/drivers/stratos.c
r29404	r29405
16	16	public:
17	17	stratos_state(const machine_config &mconfig, device_type type, const char *tag)
18	18	: driver_device(mconfig, type, tag),
19		maincpu(*this, "maincpu"),
20		nvram(*this, "nvram"),
21		bank_8000(*this, "bank_8000"),
22		bank_4000(*this, "bank_4000"),
23		nvram_bank(*this, "nvram_bank")
	19	maincpu(*this, "maincpu"),
	20	nvram(*this, "nvram"),
	21	bank_8000(*this, "bank_8000"),
	22	bank_4000(*this, "bank_4000"),
	23	nvram_bank(*this, "nvram_bank")
24	24	{ }
25	25
26	26	required_device<m65c02_device> maincpu;
r29404	r29405
255	255	// 0f08 Bi
256	256	// 1008 Kn
257	257	// 1108 Pa
258		// 0108
259		// 0208
260		// 0308
261		// 0408
	258	// 0108
	259	// 0208
	260	// 0308
	261	// 0408
262	262	// 0617 8
263	263	// 0016 7
264	264	// 0015 6

trunk/src/mess/drivers/adam.c
r29404	r29405
289	289
290	290	TODO:
291	291
292		- spinner INT
	292	- spinner INT
293	293	- printer
294	294	- SPI
295	295
r29404	r29405
443	443	case 5:
444	444	cs2 = 0;
445	445	break;
446
	446
447	447	case 6:
448	448	cs3 = 0;
449	449	break;
450
	450
451	451	case 7:
452	452	cs4 = 0;
453	453	break;

trunk/src/mess/drivers/atarist.c
r29404	r29405
2409	2409	MCFG_MC68901_OUT_IRQ_CB(INPUTLINE(M68000_TAG, M68K_IRQ_6))
2410	2410	MCFG_MC68901_OUT_TDO_CB(WRITELINE(st_state, mfp_tdo_w))
2411	2411	MCFG_MC68901_OUT_SO_CB(DEVWRITELINE(RS232_TAG, rs232_port_device, write_txd))
2412
	2412
2413	2413	MCFG_WD1772x_ADD(WD1772_TAG, U517/2)
2414	2414	MCFG_WD_FDC_INTRQ_CALLBACK(DEVWRITELINE(MC68901_TAG, mc68901_device, i5_w)) MCFG_DEVCB_INVERT
2415	2415	MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(st_state, fdc_drq_w))

trunk/src/mess/drivers/mc80.c
r29404	r29405
174	174	MCFG_VIDEO_START_OVERRIDE(mc80_state,mc8020)
175	175	MCFG_SCREEN_UPDATE_DRIVER(mc80_state, screen_update_mc8020)
176	176	MCFG_SCREEN_PALETTE("palette")
177
	177
178	178	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
179	179
180	180	/* Devices */
r29404	r29405
201	201	MCFG_VIDEO_START_OVERRIDE(mc80_state,mc8030)
202	202	MCFG_SCREEN_UPDATE_DRIVER(mc80_state, screen_update_mc8030)
203	203	MCFG_SCREEN_PALETTE("palette")
204
	204
205	205	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
206	206
207	207	/* Devices */

trunk/src/mess/drivers/px4.c
r29404	r29405
66	66	//**************************************************************************
67	67
68	68	class px4_state : public driver_device,
69		public device_serial_interface
	69	public device_serial_interface
70	70	{
71	71	public:
72	72	px4_state(const machine_config &mconfig, device_type type, const char *tag) :
r29404	r29405
83	83	m_isr(0), m_ier(0), m_str(0), m_sior(0xbf),
84	84	m_artdir(0xff), m_artdor(0xff), m_artsr(0), m_artcr(0),
85	85	m_swr(0),
86		m_one_sec_int_enabled(true), m_alarm_int_enabled(true), m_key_int_enabled(true),
	86	m_one_sec_int_enabled(true), m_alarm_int_enabled(true), m_key_int_enabled(true),
87	87	m_ramdisk_address(0),
88	88	m_ear_last_state(0)
89	89	{ }

trunk/src/mess/drivers/pentagon.c
r29404	r29405
160	160	}
161	161	static ADDRESS_MAP_START (pentagon_io, AS_IO, 8, pentagon_state )
162	162	ADDRESS_MAP_UNMAP_HIGH
163		AM_RANGE(0x0000, 0x0000) AM_WRITE(pentagon_port_7ffd_w) AM_MIRROR(0x7ffd) // (A15 \| A1) == 0
	163	AM_RANGE(0x0000, 0x0000) AM_WRITE(pentagon_port_7ffd_w) AM_MIRROR(0x7ffd) // (A15 \| A1) == 0
164	164	AM_RANGE(0x001f, 0x001f) AM_DEVREADWRITE(BETA_DISK_TAG, beta_disk_device, status_r, command_w) AM_MIRROR(0xff00)
165	165	AM_RANGE(0x003f, 0x003f) AM_DEVREADWRITE(BETA_DISK_TAG, beta_disk_device, track_r, track_w) AM_MIRROR(0xff00)
166	166	AM_RANGE(0x005f, 0x005f) AM_DEVREADWRITE(BETA_DISK_TAG, beta_disk_device, sector_r, sector_w) AM_MIRROR(0xff00)

trunk/src/mess/drivers/k8915.c
r29404	r29405
168	168	MCFG_SCREEN_SIZE(640, 250)
169	169	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 249)
170	170	MCFG_SCREEN_PALETTE("palette")
171
	171
172	172	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
173	173
174	174	MCFG_ASCII_KEYBOARD_ADD(KEYBOARD_TAG, keyboard_intf)

trunk/src/mess/drivers/pc4.c
r29404	r29405
225	225	MCFG_SCREEN_SIZE(240, 36)
226	226	MCFG_SCREEN_VISIBLE_AREA(0, 240-1, 0, 36-1)
227	227	MCFG_SCREEN_PALETTE("palette")
228
	228
229	229	MCFG_DEFAULT_LAYOUT(layout_lcd)
230	230	MCFG_PALETTE_ADD("palette", 2)
231	231	MCFG_PALETTE_INIT_OWNER(pc4_state, pc4)

trunk/src/mess/drivers/palm.c
r29404	r29405
201	201	MCFG_SCREEN_VISIBLE_AREA( 0, 159, 0, 219 )
202	202	MCFG_SCREEN_UPDATE_DEVICE(MC68328_TAG, mc68328_device, screen_update)
203	203	MCFG_SCREEN_PALETTE("palette")
204
	204
205	205	MCFG_PALETTE_ADD( "palette", 2 )
206	206	MCFG_PALETTE_INIT_OWNER(palm_state, palm)
207	207	MCFG_DEFAULT_LAYOUT(layout_lcd)

trunk/src/mess/drivers/rex6000.c
r29404	r29405
652	652	MCFG_SCREEN_SIZE(240, 120)
653	653	MCFG_SCREEN_VISIBLE_AREA(0, 240-1, 0, 120-1)
654	654	MCFG_SCREEN_PALETTE("palette")
655
	655
656	656	MCFG_DEFAULT_LAYOUT(layout_lcd)
657	657	MCFG_PALETTE_ADD("palette", 2)
658	658	MCFG_PALETTE_INIT_OWNER(rex6000_state, rex6000)

trunk/src/mess/drivers/mx2178.c
r29404	r29405
52	52	UINT8 m_term_data;
53	53	required_device<z80_device> m_maincpu;
54	54	required_device<acia6850_device> m_acia;
55		public:
	55	public:
56	56	required_device<palette_device> m_palette;
57	57	};
58	58

trunk/src/mess/drivers/apple2.c
r29404	r29405
358	358
359	359	/*
360	360	Apple IIe & IIc key matrix (from "Sams ComputerFacts: Apple IIe" and "Sams ComputerFacts: Apple IIc")
361
	361
362	362	\| Y0 \| Y1 \| Y2 \| Y3 \| Y4 \| Y5 \| Y6 \| Y7 \| Y8 \| Y9 \|
363	363	\| \| \| \| \| \| \| \| \| \| \|
364	364	----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----\|
r29404	r29405
382	382
383	383	/*
384	384	Apple IIe platinum key matrix
385
	385
386	386	\| Y0 \| Y1 \| Y2 \| Y3 \| Y4 \| Y5 \| Y6 \| Y7 \| Y8 \| Y9 \|
387	387	\| \| \| \| \| \| \| \| \| \| \|
388	388	----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----\|
r29404	r29405
617	617
618	618	PORT_START("X6")
619	619	PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_UNUSED)
620		PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_UNUSED)
621		PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_UNUSED)
622		PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_UNUSED)
623		PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_UNUSED)
624		PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_UNUSED)
	620	PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_UNUSED)
	621	PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_UNUSED)
	622	PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_UNUSED)
	623	PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_UNUSED)
	624	PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_UNUSED)
625	625	PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
626	626	PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(UTF8_UP) PORT_CODE(KEYCODE_UP)
627	627	PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
r29404	r29405
671	671	PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Esc") PORT_CODE(KEYCODE_ESC) PORT_CHAR(27)
672	672	PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
673	673	PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('\"')
674		PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR(0xa3) // a3 is Unicode for the pound sign
	674	PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR(0xa3) // a3 is Unicode for the pound sign
675	675	PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
676	676	PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
677	677	PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
r29404	r29405
741	741
742	742	PORT_START("X6")
743	743	PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_UNUSED)
744		PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_UNUSED)
745		PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_UNUSED)
746		PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_UNUSED)
747		PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_UNUSED)
748		PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_UNUSED)
	744	PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_UNUSED)
	745	PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_UNUSED)
	746	PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_UNUSED)
	747	PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_UNUSED)
	748	PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_UNUSED)
749	749	PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
750	750	PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(UTF8_UP) PORT_CODE(KEYCODE_UP)
751	751	PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
r29404	r29405
862	862
863	863	PORT_START("X6")
864	864	PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ASTERISK) PORT_CHAR(UCHAR_MAMEKEY(ASTERISK))
865		PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_UNUSED)
	865	PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_UNUSED)
866	866	PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8_PAD) PORT_CHAR(UCHAR_MAMEKEY(8_PAD))
867	867	PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9_PAD) PORT_CHAR(UCHAR_MAMEKEY(9_PAD))
868	868	PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL_PAD) PORT_CHAR(UCHAR_MAMEKEY(DEL_PAD))
r29404	r29405
997	997	SLOT_INTERFACE("ultraterm", A2BUS_ULTRATERM) /* Videx UltraTerm (original) */
998	998	SLOT_INTERFACE("ultratermenh", A2BUS_ULTRATERMENH) /* Videx UltraTerm (enhanced //e) */
999	999	SLOT_INTERFACE("aevm80", A2BUS_VTC2) /* Applied Engineering ViewMaster 80 */
1000		SLOT_INTERFACE("parallel", A2BUS_PIC) /* Apple Parallel Interface Card */
1001		SLOT_INTERFACE("corvus", A2BUS_CORVUS) /* Corvus flat-cable HDD interface (must go in slot 6) */
	1000	SLOT_INTERFACE("parallel", A2BUS_PIC) /* Apple Parallel Interface Card */
	1001	SLOT_INTERFACE("corvus", A2BUS_CORVUS) /* Corvus flat-cable HDD interface (must go in slot 6) */
1002	1002	SLOT_INTERFACE_END
1003	1003
1004	1004	static SLOT_INTERFACE_START(apple2eaux_cards)
r29404	r29405
1321	1321
1322	1322	/*
1323	1323	J-Plus ROM numbers confirmed by:
1324		http://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Computers/Apple%20II/Apple%20II%20j-plus/Photos/Apple%20II%20j-plus%20-%20Motherboard.jpg
	1324	http://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Computers/Apple%20II/Apple%20II%20j-plus/Photos/Apple%20II%20j-plus%20-%20Motherboard.jpg
1325	1325	*/
1326	1326
1327	1327	ROM_START(apple2jp)
r29404	r29405
1566	1566	ROM_CONTINUE(0x1000, 0x1000)
1567	1567	ROM_LOAD( "ultra2.bin", 0x3000, 0x1000, CRC(1ac1e17e) SHA1(a5b8adec37da91970c303905b5e2c4d1b715ee4e))
1568	1568
1569		ROM_REGION(0x800, "kbmcu", 0) // 6802 code for keyboard MCU (very unlike real Apples, will require some reverse-engineering)
	1569	ROM_REGION(0x800, "kbmcu", 0) // 6802 code for keyboard MCU (very unlike real Apples, will require some reverse-engineering)
1570	1570	ROM_LOAD( "ultra4.bin", 0x0000, 0x0800, CRC(3dce51ac) SHA1(676b6e775d5159049cae5b6143398ec7b2bf437a) )
1571	1571	ROM_END
1572	1572
r29404	r29405
1627	1627	COMP( 1980, apple2jp, apple2, 0, apple2p, apple2p, driver_device, 0, "Apple Computer", "Apple ][ J-Plus", GAME_SUPPORTS_SAVE )
1628	1628	COMP( 1982, ace100, apple2, 0, apple2, apple2e, driver_device, 0, "Franklin Computer", "Franklin Ace 100", GAME_SUPPORTS_SAVE )
1629	1629	COMP( 1983, apple2e, 0, apple2, apple2e, apple2e, driver_device, 0, "Apple Computer", "Apple //e", GAME_SUPPORTS_SAVE )
1630		COMP( 1983, apple2euk,apple2e, 0, apple2e, apple2euk,driver_device, 0, "Apple Computer", "Apple //e (UK)", GAME_SUPPORTS_SAVE )
	1630	COMP( 1983, apple2euk,apple2e, 0, apple2e, apple2euk,driver_device, 0, "Apple Computer", "Apple //e (UK)", GAME_SUPPORTS_SAVE )
1631	1631	COMP( 1983, mprof3, apple2e, 0, mprof3, apple2e, driver_device, 0, "Multitech", "Microprofessor III", GAME_SUPPORTS_SAVE )
1632	1632	COMP( 1985, apple2ee, apple2e, 0, apple2ee, apple2e, driver_device, 0, "Apple Computer", "Apple //e (enhanced)", GAME_SUPPORTS_SAVE )
1633	1633	COMP( 1985, apple2eeuk,apple2e, 0, apple2ee, apple2euk, driver_device,0, "Apple Computer", "Apple //e (enhanced, UK)", GAME_SUPPORTS_SAVE )

trunk/src/mess/drivers/bcs3.c
r29404	r29405
446	446	MCFG_SCREEN_VISIBLE_AREA(0,288-1,0,1210-1)
447	447	MCFG_SCREEN_UPDATE_DRIVER(bcs3_state, screen_update_bcs3)
448	448	MCFG_SCREEN_PALETTE("palette")
449
	449
450	450	MCFG_GFXDECODE_ADD("gfxdecode", "palette", bcs3)
451	451	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
452	452	MACHINE_CONFIG_END

trunk/src/mess/drivers/fmtowns.c
r29404	r29405
624	624	}
625	625
626	626	READ16_MEMBER(towns_state::towns_fdc_dma_r)
627		{ UINT16 data = m_fdc->data_r(generic_space(), 0);
	627	{ UINT16 data = m_fdc->data_r(generic_space(), 0);
628	628	return data;
629	629	}
630	630

trunk/src/mess/drivers/c128.c
r29404	r29405
1468	1468	MCFG_SCREEN_SIZE(VIC6567_COLUMNS, VIC6567_LINES)
1469	1469	MCFG_SCREEN_VISIBLE_AREA(0, VIC6567_VISIBLECOLUMNS - 1, 0, VIC6567_VISIBLELINES - 1)
1470	1470	MCFG_SCREEN_UPDATE_DEVICE(MOS8564_TAG, mos8564_device, screen_update)
1471
	1471
1472	1472	MCFG_GFXDECODE_ADD("gfxdecode", MOS8563_TAG":palette", c128)
1473	1473
1474	1474	// sound hardware
r29404	r29405
1632	1632	MCFG_SCREEN_SIZE(VIC6569_COLUMNS, VIC6569_LINES)
1633	1633	MCFG_SCREEN_VISIBLE_AREA(0, VIC6569_VISIBLECOLUMNS - 1, 0, VIC6569_VISIBLELINES - 1)
1634	1634	MCFG_SCREEN_UPDATE_DEVICE(MOS8566_TAG, mos8566_device, screen_update)
1635
	1635
1636	1636	MCFG_GFXDECODE_ADD("gfxdecode", MOS8563_TAG":palette", c128)
1637	1637
1638	1638	// sound hardware

trunk/src/mess/drivers/kyocera.c
r29404	r29405
30	30
31	31	TODO:
32	32
33		- bar code reader (!RxDB -> RST5.5, Hewlett-Packard HREDS-3050 interface)
	33	- bar code reader (!RxDB -> RST5.5, Hewlett-Packard HREDS-3050 interface)
34	34	- un-Y2K-hack tandy200
35	35	- keyboard is unresponsive for couple of seconds after boot
36	36	- soft power on/off

trunk/src/mess/drivers/pb1000.c
r29404	r29405
514	514	MCFG_SCREEN_SIZE(192, 32)
515	515	MCFG_SCREEN_VISIBLE_AREA(0, 192-1, 0, 32-1)
516	516	MCFG_SCREEN_PALETTE("palette")
517
	517
518	518	MCFG_DEFAULT_LAYOUT(layout_lcd)
519	519	MCFG_PALETTE_ADD("palette", 2)
520	520	MCFG_PALETTE_INIT_OWNER(pb1000_state, pb1000)

trunk/src/mess/drivers/plan80.c
r29404	r29405
242	242	MCFG_SCREEN_SIZE(486, 328)
243	243	MCFG_SCREEN_VISIBLE_AREA(0, 486-1, 0, 328-1)
244	244	MCFG_SCREEN_PALETTE("palette")
245
	245
246	246	MCFG_GFXDECODE_ADD("gfxdecode", "palette", plan80)
247	247	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
248	248	MACHINE_CONFIG_END

trunk/src/mess/drivers/ssem.c
r29404	r29405
22	22	required_device<ssem_device> m_maincpu;
23	23	required_shared_ptr<UINT8> m_store;
24	24	required_device<screen_device> m_screen;
25
	25
26	26	UINT8 m_store_line;
27	27	virtual void machine_reset();
28	28	UINT32 screen_update_ssem(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);

trunk/src/mess/drivers/rmt32.c
r29404	r29405
360	360	MCFG_SCREEN_SIZE(206-1, (206-1)*3/4)
361	361	MCFG_SCREEN_VISIBLE_AREA(0, 206-2, 0, (206-1)*3/4-1)
362	362	MCFG_SCREEN_PALETTE("palette")
363
	363
364	364	MCFG_PALETTE_ADD("palette", 2)
365	365	MCFG_PALETTE_INIT_OWNER(mt32_state, mt32)
366	366

trunk/src/mess/drivers/vt100.c
r29404	r29405
421	421	MCFG_SCREEN_PALETTE("vt100_video:palette")
422	422
423	423	MCFG_GFXDECODE_ADD("gfxdecode", "vt100_video:palette", vt100)
424		// MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
	424	// MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
425	425
426	426	MCFG_DEFAULT_LAYOUT( layout_vt100 )
427	427

trunk/src/mess/drivers/supracan.c
r29404	r29405
1925	1925	MCFG_SCREEN_RAW_PARAMS(XTAL_10_738635MHz/2, 348, 0, 256, 256, 0, 240 ) /* No idea if this is correct */
1926	1926	MCFG_SCREEN_UPDATE_DRIVER(supracan_state, screen_update_supracan)
1927	1927	MCFG_SCREEN_PALETTE("palette")
1928
	1928
1929	1929	MCFG_PALETTE_ADD( "palette", 32768 )
1930	1930	MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
1931	1931	MCFG_PALETTE_INIT_OWNER(supracan_state, supracan)
1932
	1932
1933	1933	MCFG_GFXDECODE_ADD("gfxdecode", "palette", supracan)
1934	1934
1935	1935	MCFG_CARTSLOT_ADD("cart")

trunk/src/mess/drivers/zorba.c
r29404	r29405
98	98	required_device<fd1793_t> m_fdc;
99	99	required_device<floppy_connector> m_floppy0;
100	100	required_device<floppy_connector> m_floppy1;
101		public:
	101	public:
102	102	required_device<palette_device> m_palette;
103	103	};
104	104
r29404	r29405
361	361	MCFG_SCREEN_SIZE(640, 276)
362	362	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 275)
363	363	MCFG_SCREEN_PALETTE("palette")
364
	364
365	365	MCFG_PALETTE_ADD("palette", 3)
366	366	MCFG_PALETTE_INIT_OWNER(zorba_state, zorba)
367	367

trunk/src/mess/drivers/mz700.c
r29404	r29405
366	366	MCFG_PIT8253_OUT2_HANDLER(WRITELINE(mz_state, pit_irq_2))
367	367
368	368	MCFG_I8255_ADD("ppi8255", mz700_ppi8255_interface)
369
	369
370	370	MCFG_DEVICE_ADD("ls145", TTL74145, 0)
371	371
372	372	MCFG_CASSETTE_ADD( "cassette", mz700_cassette_interface )

trunk/src/mess/drivers/mk90.c
r29404	r29405
79	79	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
80	80	MCFG_SCREEN_UPDATE_DRIVER(mk90_state, screen_update_mk90)
81	81	MCFG_SCREEN_PALETTE("palette")
82
	82
83	83	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
84	84	MACHINE_CONFIG_END
85	85

trunk/src/mess/drivers/apple3.c
r29404	r29405
3	3	drivers/apple3.c
4	4
5	5	Apple ///
6
	6
7	7	driver by Nathan Woods and R. Belmont
8
	8
9	9	Special thanks to Chris Smolinski (author of the Sara emulator)
10	10	for his input about this poorly known system.
11
	11
12	12	Also thanks to Washington Apple Pi for the "Apple III DVD" containing the
13	13	technical manual, schematics, and software.
14	14
r29404	r29405
176	176	*/
177	177
178	178	/*
179		Esc
180		0x00
	179	Esc
	180	0x00
181	181
182		` 1 2 3 4 5 6 7 8 9 0 - = BACKSPACE
183		0x38 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x30 0x31 0x2f 0x104
	182	` 1 2 3 4 5 6 7 8 9 0 - = BACKSPACE
	183	0x38 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x30 0x31 0x2f 0x104
184	184
185		Tab Q W E R T Y U I O P [ ] \
186		0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x3a 0x3b 0x39 0x2e
	185	Tab Q W E R T Y U I O P [ ] \
	186	0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x3a 0x3b 0x39 0x2e
187	187
188		A S D F G H J K L ; ' ENTER
189		0x14 0x15 0x16 0x17 0x19 0x18 0x1a 0x1b 0x1d 0x1c 0x105 0x102
190
191		Z X C V B N M , . /
	188	A S D F G H J K L ; ' ENTER
	189	0x14 0x15 0x16 0x17 0x19 0x18 0x1a 0x1b 0x1d 0x1c 0x105 0x102
	190
	191	Z X C V B N M , . /
192	192	0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
193
194		SPACE UP LT DN RT KP- KP7 KP8 KP9
	193
	194	SPACE UP LT DN RT KP- KP7 KP8 KP9
195	195	0x109 0x103 0x10e 0x10d 0x10c 0x10b 0x2d 0x2b 0x29
196
	196
197	197	KP4 KP5 KP6 KP1 KP2 KP3 KPEN KP0 KP.
198	198	0x37 0x35 0x33 0x101 0x3f 0x3d 0x108 0x100 0x3e
199	199	*/
r29404	r29405
310	310	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Left Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
311	311	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Right Shift") PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
312	312	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Control") PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
313		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Open Apple") PORT_CODE(KEYCODE_LALT)
314		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Solid Apple") PORT_CODE(KEYCODE_RALT)
	313	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Open Apple") PORT_CODE(KEYCODE_LALT)
	314	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Solid Apple") PORT_CODE(KEYCODE_RALT)
315	315	PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("RESET") PORT_CODE(KEYCODE_F12)
316	316	INPUT_PORTS_END
317	317
r29404	r29405
322	322
323	323	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */
324	324	COMP( 1980, apple3, 0, 0, apple3, apple3, apple3_state, apple3, "Apple Computer", "Apple ///", GAME_SUPPORTS_SAVE )
325

trunk/src/mess/drivers/homez80.c
r29404	r29405
293	293	MCFG_SCREEN_SIZE(344, 32*8)
294	294	MCFG_SCREEN_VISIBLE_AREA(0, 344-1, 0, 32*8-1)
295	295	MCFG_SCREEN_PALETTE("palette")
296
	296
297	297	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
298	298	MCFG_GFXDECODE_ADD("gfxdecode", "palette", homez80 )
299	299	MACHINE_CONFIG_END

trunk/src/mess/drivers/abc1600.c
r29404	r29405
936	936	MCFG_FD1797x_ADD(SAB1797_02P_TAG, XTAL_64MHz/64)
937	937	MCFG_WD_FDC_INTRQ_CALLBACK(DEVWRITELINE(Z8536B1_TAG, z8536_device, pb7_w))
938	938	MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(abc1600_state, fdc_drq_w))
939
	939
940	940	MCFG_FLOPPY_DRIVE_ADD(SAB1797_02P_TAG":0", abc1600_floppies, NULL, floppy_image_device::default_floppy_formats)
941	941	MCFG_FLOPPY_DRIVE_ADD(SAB1797_02P_TAG":1", abc1600_floppies, NULL, floppy_image_device::default_floppy_formats)
942	942	MCFG_FLOPPY_DRIVE_ADD(SAB1797_02P_TAG":2", abc1600_floppies, "525qd", floppy_image_device::default_floppy_formats)

trunk/src/mess/drivers/nc.c
r29404	r29405
1417	1417
1418	1418	MCFG_PALETTE_ADD("palette", NC_NUM_COLOURS)
1419	1419	MCFG_PALETTE_INIT_OWNER(nc_state, nc)
1420
	1420
1421	1421	MCFG_DEFAULT_LAYOUT(layout_lcd)
1422	1422
1423	1423	/* sound hardware */
r29404	r29405
1484	1484	MCFG_SCREEN_MODIFY("screen")
1485	1485	MCFG_SCREEN_SIZE(NC200_SCREEN_WIDTH, NC200_SCREEN_HEIGHT)
1486	1486	MCFG_SCREEN_VISIBLE_AREA(0, NC200_SCREEN_WIDTH-1, 0, NC200_SCREEN_HEIGHT-1)
1487
	1487
1488	1488	MCFG_PALETTE_MODIFY("palette")
1489	1489	MCFG_PALETTE_ENTRIES(NC200_NUM_COLOURS)
1490	1490	MCFG_PALETTE_INIT_OWNER(nc_state, nc)

trunk/src/mess/drivers/pt68k4.c
r29404	r29405
8	8	2013-09-30 Connected to a terminal
9	9	2014-01-03 Connect real DUARTs, FDC, and TimeKeeper. Settings now save properly, floppies can be read.
10	10	2014-01-19 ISA bus and compatible cards, PC keyboard support, speaker support
11
	11
12	12	This has the appearance of a PC, including pc power supply, slots, etc
13	13	on a conventional pc-like motherboard and case.
14	14
15	15	Some pics: http://www.wormfood.net/old_computers/
16	16
17		Chips:
	17	Chips:
18	18	68230 Parallel Interface/Timer @ FE0081
19	19	68681 DUART/Timer (x2) @ FE0001 and FE0041
20	20	WD37C65 FDC (PC FDC compatible, even mapped as an ISA device)
21	21	MK48T02 TimeKeeper @ odd bytes from FF0001 to FF0FFF. even bytes in that range are a standard SRAM chip which is not backed up.
22	22	Keyboard at FE01C1 (status/IRQ clear)/FE01C3 (AT scan codes)
23	23	WD1002 HDD controller @ FE0141-FE014F. "Monk" BIOS also supports an 8-bit ISA IDE card.
24
	24
25	25	Video: ISA MDA or CGA/EGA/VGA-style boards
26	26	ISA memory is C00001-DFFFFF odd bytes only. So the MDA B0000 framebuffer becames (B0000*2) + C00001 = D60001.
27	27	ISA I/O is at FA0001-FBFFFF odd bytes only, and the mapping is similar.
28
	28
29	29	HUMBUG BIOS tests MDA and CGA VRAM to determine existence, falls back to serial console if neither exists. If both exist, MDA is used.
30	30	VRAM is every other byte for ISA cards. (Only 8 bit cards are supported).
31
	31
32	32	OP3 on DUART1 drives a speaker.
33	33	IP2 on DUART1 signals if a new keyboard scan code is available.
34
35		IRQs:
	34
	35	IRQs:
36	36	2: 68230 PIT
37	37	4: DUART2
38	38	5: DUART1
39	39	6: PC FDC IRQ
40
	40
41	41	TODO: 68230 device. Better hardware documentation would be nice too, and working OS disks.
42
	42
43	43	****************************************************************************/
44	44
45	45	#include "emu.h"
r29404	r29405
55	55	#include "sound/speaker.h"
56	56
57	57	#define M68K_TAG "maincpu"
58		#define DUART1_TAG "duart1"
59		#define DUART2_TAG "duart2"
60		#define TIMEKEEPER_TAG "timekpr"
	58	#define DUART1_TAG "duart1"
	59	#define DUART2_TAG "duart2"
	60	#define TIMEKEEPER_TAG "timekpr"
61	61	#define ISABUS_TAG "isa"
62	62	#define KBDC_TAG "pc_kbdc"
63	63	#define SPEAKER_TAG "speaker"
r29404	r29405
109	109	// XT keyboard interface - done in TTL instead of an 804x
110	110	WRITE_LINE_MEMBER(pt68k4_state::keyboard_clock_w)
111	111	{
112		// printf("KCLK: %d\n", state ? 1 : 0);
	112	// printf("KCLK: %d\n", state ? 1 : 0);
113	113
114	114	// rising edge?
115	115	if ((state == ASSERT_LINE) && (!m_kclk))
r29404	r29405
123	123	// stop bit?
124	124	if (m_kbit == 9)
125	125	{
126		// printf("scancode %02x\n", m_scancode);
	126	// printf("scancode %02x\n", m_scancode);
127	127	m_kbit = 0;
128	128	m_kbdflag = 0x80;
129	129	m_duart1->ip2_w(CLEAR_LINE);
r29404	r29405
139	139
140	140	WRITE_LINE_MEMBER(pt68k4_state::keyboard_data_w)
141	141	{
142		// printf("KDATA: %d\n", state ? 1 : 0);
	142	// printf("KDATA: %d\n", state ? 1 : 0);
143	143	m_kdata = (state == ASSERT_LINE) ? 0x80 : 0x00;
144	144	}
145	145
r29404	r29405
228	228	SLOT_INTERFACE("mda", ISA8_MDA)
229	229	SLOT_INTERFACE("cga", ISA8_CGA)
230	230	SLOT_INTERFACE("ega", ISA8_EGA) // Monk only
231		SLOT_INTERFACE("vga", ISA8_VGA) // Monk only
	231	SLOT_INTERFACE("vga", ISA8_VGA) // Monk only
232	232	SLOT_INTERFACE("fdc_at", ISA8_FDC_AT)
233	233	SLOT_INTERFACE("wdxt_gen", ISA8_WDXT_GEN)
234	234	SLOT_INTERFACE("lpt", ISA8_LPT)
235		SLOT_INTERFACE("xtide", ISA8_XTIDE) // Monk only
	235	SLOT_INTERFACE("xtide", ISA8_XTIDE) // Monk only
236	236	SLOT_INTERFACE_END
237	237
238	238	static const isa8bus_interface pt68k4_isabus_intf =
r29404	r29405
309	309	/* Driver */
310	310	/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
311	311	COMP( 1990, pt68k4, 0, 0, pt68k4, pt68k4, driver_device, 0, "Peripheral Technology", "PT68K4", GAME_NOT_WORKING )
312

trunk/src/mess/drivers/itt3030.c
r29404	r29405
233	233	, m_keyrow16(*this, "ROW16")
234	234	, m_vram(*this, "vram"),
235	235	m_gfxdecode(*this, "gfxdecode"),
236		m_palette(*this, "palette")
	236	m_palette(*this, "palette")
237	237	{ }
238	238
239	239	// devices

trunk/src/mess/drivers/pc6001.c
r29404	r29405
2367	2367
2368	2368	MCFG_SCREEN_MODIFY("screen")
2369	2369	MCFG_SCREEN_UPDATE_DRIVER(pc6001_state, screen_update_pc6001m2)
2370
	2370
2371	2371	MCFG_PALETTE_MODIFY("palette")
2372	2372	MCFG_PALETTE_ENTRIES(16+16)
2373	2373	MCFG_PALETTE_INIT_OWNER(pc6001_state,pc6001m2)

trunk/src/mess/drivers/tandy2k.c
r29404	r29405
11	11	TODO:
12	12
13	13	- floppy
14		- HDL is also connected to WP/TS input where TS is used to detect motor status
15		- 3 second motor off delay timer
	14	- HDL is also connected to WP/TS input where TS is used to detect motor status
	15	- 3 second motor off delay timer
16	16	- DMA
17		- video (video RAM is at memory top - 0x1400, i.e. 0x1ec00)
	17	- video (video RAM is at memory top - 0x1400, i.e. 0x1ec00)
18	18	- keyboard ROM
19	19	- hires graphics board
20	20	- WD1010
r29404	r29405
187	187	int dme = (drq0 > 2) \|\| (drq1 > 2);
188	188
189	189	m_pic1->ir6_w(dme);
190
	190
191	191	update_drq();
192	192	}
193	193
r29404	r29405
339	339	{
340	340	const pen_t *pen = m_palette->pens();
341	341	address_space &program = m_maincpu->space(AS_PROGRAM);
342
	342
343	343	for (int y = 0; y < 400; y++)
344	344	{
345	345	UINT8 cgra = y % 16;
r29404	r29405
355	355	int color = BIT(data, 7);
356	356	bitmap.pix32(y, (sx * 8) + x) = pen[color];
357	357	data <<= 1;
358		}
	358	}
359	359	}
360	360	}
361	361
r29404	r29405
398	398	WRITE_LINE_MEMBER( tandy2k_state::vpac_sld_w )
399	399	{
400	400	m_sld = state;
401
	401
402	402	m_vac->sld_w(state);
403	403	}
404	404
r29404	r29405
758	758	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 400-1)
759	759	//MCFG_SCREEN_UPDATE_DEVICE(CRT9021B_TAG, crt9021_t, screen_update)
760	760	MCFG_SCREEN_UPDATE_DRIVER(tandy2k_state, screen_update)
761
	761
762	762	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
763	763
764	764	MCFG_DEVICE_ADD(CRT9007_TAG, CRT9007, XTAL_16MHz*28/20/8)
r29404	r29405
816	816	MCFG_PIT8253_OUT2_HANDLER(WRITELINE(tandy2k_state, rfrqpulse_w))
817	817
818	818	MCFG_PIC8259_ADD(I8259A_0_TAG, DEVWRITELINE(I80186_TAG, i80186_cpu_device, int0_w), VCC, NULL)
819
	819
820	820	MCFG_PIC8259_ADD(I8259A_1_TAG, DEVWRITELINE(I80186_TAG, i80186_cpu_device, int1_w), VCC, NULL)
821
	821
822	822	MCFG_I8272A_ADD(I8272A_TAG, true)
823	823	downcast<i8272a_device *>(device)->set_select_lines_connected(true);
824	824	MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE(I8259A_0_TAG, pic8259_device, ir4_w))

trunk/src/mess/drivers/vboy.c
r29404	r29405
106	106	: driver_device(mconfig, type, tag),
107	107	m_maintimer(*this, "timer_main"),
108	108	m_maincpu(*this, "maincpu"),
109		m_palette(*this, "palette")
	109	m_palette(*this, "palette")
110	110	{
111	111	m_vip_regs.INTPND = 0;
112	112	m_vip_regs.INTENB = 0;

trunk/src/mess/drivers/vip.c
r29404	r29405
503	503
504	504	WRITE8_MEMBER( vip_state::sc_w )
505	505	{
506		m_exp->sc_w(data);
	506	m_exp->sc_w(data);
507	507	}
508	508
509	509
r29404	r29405
726	726	MCFG_CPU_ADD(CDP1802_TAG, CDP1802, XTAL_3_52128MHz/2)
727	727	MCFG_CPU_PROGRAM_MAP(vip_mem)
728	728	MCFG_CPU_IO_MAP(vip_io)
729		MCFG_COSMAC_WAIT_CALLBACK(VCC)
730		MCFG_COSMAC_CLEAR_CALLBACK(READLINE(vip_state, clear_r))
731		MCFG_COSMAC_EF1_CALLBACK(READLINE(vip_state, ef1_r))
732		MCFG_COSMAC_EF2_CALLBACK(READLINE(vip_state, ef2_r))
733		MCFG_COSMAC_EF3_CALLBACK(READLINE(vip_state, ef3_r))
734		MCFG_COSMAC_EF4_CALLBACK(READLINE(vip_state, ef4_r))
735		MCFG_COSMAC_Q_CALLBACK(WRITELINE(vip_state, q_w))
736		MCFG_COSMAC_DMAR_CALLBACK(READ8(vip_state, dma_r))
737		MCFG_COSMAC_DMAW_CALLBACK(WRITE8(vip_state, dma_w))
738		MCFG_COSMAC_SC_CALLBACK(WRITE8(vip_state, sc_w))
	729	MCFG_COSMAC_WAIT_CALLBACK(VCC)
	730	MCFG_COSMAC_CLEAR_CALLBACK(READLINE(vip_state, clear_r))
	731	MCFG_COSMAC_EF1_CALLBACK(READLINE(vip_state, ef1_r))
	732	MCFG_COSMAC_EF2_CALLBACK(READLINE(vip_state, ef2_r))
	733	MCFG_COSMAC_EF3_CALLBACK(READLINE(vip_state, ef3_r))
	734	MCFG_COSMAC_EF4_CALLBACK(READLINE(vip_state, ef4_r))
	735	MCFG_COSMAC_Q_CALLBACK(WRITELINE(vip_state, q_w))
	736	MCFG_COSMAC_DMAR_CALLBACK(READ8(vip_state, dma_r))
	737	MCFG_COSMAC_DMAW_CALLBACK(WRITE8(vip_state, dma_w))
	738	MCFG_COSMAC_SC_CALLBACK(WRITE8(vip_state, sc_w))
739	739
740	740	// video hardware
741		MCFG_DEVICE_ADD(CDP1861_TAG, CDP1861, XTAL_3_52128MHz/2)
742		MCFG_CDP1861_IRQ_CALLBACK(WRITELINE(vip_state, vdc_int_w))
743		MCFG_CDP1861_DMA_OUT_CALLBACK(WRITELINE(vip_state, vdc_dma_out_w))
744		MCFG_CDP1861_EFX_CALLBACK(WRITELINE(vip_state, vdc_ef1_w))
745		MCFG_CDP1861_SCREEN_ADD(CDP1861_TAG, SCREEN_TAG, XTAL_3_52128MHz/2)
746		MCFG_SCREEN_UPDATE_DRIVER(vip_state, screen_update)
	741	MCFG_DEVICE_ADD(CDP1861_TAG, CDP1861, XTAL_3_52128MHz/2)
	742	MCFG_CDP1861_IRQ_CALLBACK(WRITELINE(vip_state, vdc_int_w))
	743	MCFG_CDP1861_DMA_OUT_CALLBACK(WRITELINE(vip_state, vdc_dma_out_w))
	744	MCFG_CDP1861_EFX_CALLBACK(WRITELINE(vip_state, vdc_ef1_w))
	745	MCFG_CDP1861_SCREEN_ADD(CDP1861_TAG, SCREEN_TAG, XTAL_3_52128MHz/2)
	746	MCFG_SCREEN_UPDATE_DRIVER(vip_state, screen_update)
747	747
748	748	// sound hardware
749	749	MCFG_SPEAKER_STANDARD_MONO("mono")
r29404	r29405
754	754
755	755	MCFG_VIP_BYTEIO_PORT_ADD(VIP_BYTEIO_PORT_TAG, vip_byteio_cards, NULL, WRITELINE(vip_state, byteio_inst_w))
756	756	MCFG_VIP_EXPANSION_SLOT_ADD(VIP_EXPANSION_SLOT_TAG, XTAL_3_52128MHz/2, vip_expansion_cards, NULL)
757		MCFG_VIP_EXPANSION_SLOT_INT_CALLBACK(WRITELINE(vip_state, exp_int_w))
758		MCFG_VIP_EXPANSION_SLOT_DMA_OUT_CALLBACK(WRITELINE(vip_state, exp_dma_out_w))
759		MCFG_VIP_EXPANSION_SLOT_DMA_IN_CALLBACK(WRITELINE(vip_state, exp_dma_in_w))
	757	MCFG_VIP_EXPANSION_SLOT_INT_CALLBACK(WRITELINE(vip_state, exp_int_w))
	758	MCFG_VIP_EXPANSION_SLOT_DMA_OUT_CALLBACK(WRITELINE(vip_state, exp_dma_out_w))
	759	MCFG_VIP_EXPANSION_SLOT_DMA_IN_CALLBACK(WRITELINE(vip_state, exp_dma_in_w))
760	760
761	761	// devices
762	762	MCFG_QUICKLOAD_ADD("quickload", vip_state, vip, "bin,c8,c8x", 0)

trunk/src/mess/drivers/indiana.c
r29404	r29405
2	2
3	3	Indiana University 68030 board
4	4
5		08/12/2009 Skeleton driver.
6		01/20/2014 Added ISA bus and peripherals
7
8		TODO: Text appears in VGA f/b (0x6B8000), but doesn't display?
9
	5	08/12/2009 Skeleton driver.
	6	01/20/2014 Added ISA bus and peripherals
	7
	8	TODO: Text appears in VGA f/b (0x6B8000), but doesn't display?
	9
10	10	System often reads/writes 6003D4/5, might be a cut-down 6845,
11	11	as it only uses registers C,D,E,F.
12	12
r29404	r29405
120	120	MCFG_MC68901_RX_CLOCK(0)
121	121	MCFG_MC68901_TX_CLOCK(0)
122	122	MCFG_MC68901_OUT_SO_CB(DEVWRITELINE("keyboard", serial_keyboard_device, input_txd))
123
	123
124	124	MCFG_SERIAL_KEYBOARD_ADD("keyboard", keyboard_interface, 1200)
125	125	MACHINE_CONFIG_END
126	126

trunk/src/mess/drivers/grfd2301.c
r29404	r29405
123	123	MCFG_SCREEN_SIZE(640, 240)
124	124	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 239)
125	125	MCFG_SCREEN_PALETTE("palette")
126
	126
127	127	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
128	128	MACHINE_CONFIG_END
129	129

trunk/src/mess/drivers/dms5000.c
r29404	r29405
67	67	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
68	68	MCFG_SCREEN_UPDATE_DRIVER(dms5000_state, screen_update_dms5000)
69	69	MCFG_SCREEN_PALETTE("palette")
70
	70
71	71	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
72	72	MACHINE_CONFIG_END
73	73

trunk/src/mess/drivers/ti85.c
r29404	r29405
552	552
553	553	MCFG_SCREEN_MODIFY("screen")
554	554	MCFG_SCREEN_UPDATE_DEVICE("t6a04", t6a04_device, screen_update)
555
	555
556	556	MCFG_PALETTE_MODIFY("palette")
557	557	MCFG_PALETTE_ENTRIES(2)
558	558	MCFG_PALETTE_INIT_OWNER(ti85_state, ti82 )
r29404	r29405
582	582
583	583	MCFG_SCREEN_MODIFY("screen")
584	584	MCFG_SCREEN_UPDATE_DEVICE("t6a04", t6a04_device, screen_update)
585
	585
586	586	MCFG_PALETTE_MODIFY("palette")
587	587	MCFG_PALETTE_ENTRIES(2)
588	588	MCFG_PALETTE_INIT_OWNER(ti85_state, ti82 )
r29404	r29405
616	616
617	617	MCFG_SCREEN_MODIFY("screen")
618	618	MCFG_SCREEN_UPDATE_DEVICE("t6a04", t6a04_device, screen_update)
619
	619
620	620	MCFG_PALETTE_MODIFY("palette")
621	621	MCFG_PALETTE_ENTRIES(2)
622	622	MCFG_PALETTE_INIT_OWNER(ti85_state, ti82 )

trunk/src/mess/drivers/unior.c
r29404	r29405
83	83	required_device<pit8253_device> m_pit;
84	84	required_device<i8257_device> m_dma;
85	85	required_device<i8251_device> m_uart;
86		public:
	86	public:
87	87	required_device<palette_device> m_palette;
88	88	};
89	89

trunk/src/mess/drivers/xerox820.c
r29404	r29405
692	692	MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
693	693	MCFG_SCREEN_UPDATE_DRIVER(xerox820_state, screen_update)
694	694	MCFG_SCREEN_RAW_PARAMS(XTAL_10_69425MHz, 700, 0, 560, 260, 0, 240)
695
	695
696	696	MCFG_GFXDECODE_ADD("gfxdecode", "palette", xerox820)
697	697	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
698	698
r29404	r29405
747	747	MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
748	748	MCFG_SCREEN_UPDATE_DRIVER(xerox820ii_state, screen_update)
749	749	MCFG_SCREEN_RAW_PARAMS(XTAL_10_69425MHz, 700, 0, 560, 260, 0, 240)
750
	750
751	751	MCFG_GFXDECODE_ADD("gfxdecode", "palette", xerox820ii)
752	752	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
753	753

trunk/src/mess/drivers/micronic.c
r29404	r29405
376	376	MCFG_RAM_ADD(RAM_TAG)
377	377	MCFG_RAM_DEFAULT_SIZE("224K")
378	378
379		MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram1", micronic_state, nvram_init) // base ram
380		MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram2", micronic_state, nvram_init) // additional ram banks
	379	MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram1", micronic_state, nvram_init) // base ram
	380	MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram2", micronic_state, nvram_init) // additional ram banks
381	381
382	382	MCFG_MC146818_ADD( MC146818_TAG, XTAL_32_768kHz )
383	383	MCFG_MC146818_IRQ_HANDLER(WRITELINE(micronic_state, mc146818_irq))

trunk/src/mess/drivers/p2000t.c
r29404	r29405
257	257	MCFG_VIDEO_START_OVERRIDE(p2000t_state,p2000m)
258	258	MCFG_SCREEN_UPDATE_DRIVER(p2000t_state, screen_update_p2000m)
259	259	MCFG_SCREEN_PALETTE("palette")
260
	260
261	261	MCFG_GFXDECODE_ADD("gfxdecode", "palette", p2000m )
262	262	MCFG_PALETTE_ADD("palette", 4)
263	263	MCFG_PALETTE_INIT_OWNER(p2000t_state,p2000m)

trunk/src/mess/drivers/alphasma.c
r29404	r29405
398	398	MCFG_SCREEN_SIZE(640, 94)
399	399	MCFG_SCREEN_VISIBLE_AREA(0, (640)-1, 0, (94)-1)
400	400	MCFG_SCREEN_PALETTE("palette")
401
	401
402	402	MCFG_PALETTE_ADD("palette", 2)
403	403	MCFG_PALETTE_INIT_OWNER(alphasmart_state, alphasmart)
404	404	MCFG_DEFAULT_LAYOUT(layout_lcd)

trunk/src/mess/drivers/esq1.c
r29404	r29405
608	608	MCFG_ES5503_OUTPUT_CHANNELS(8)
609	609	MCFG_ES5503_IRQ_FUNC(WRITELINE(esq1_state, esq1_doc_irq))
610	610	MCFG_ES5503_ADC_FUNC(READ8(esq1_state, esq1_adc_read))
611
	611
612	612	MCFG_SOUND_ROUTE_EX(0, "filters", 1.0, 0)
613	613	MCFG_SOUND_ROUTE_EX(1, "filters", 1.0, 1)
614	614	MCFG_SOUND_ROUTE_EX(2, "filters", 1.0, 2)

trunk/src/mess/drivers/irisha.c
r29404	r29405
407	407	MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 200-1)
408	408	MCFG_SCREEN_UPDATE_DRIVER(irisha_state, screen_update_irisha)
409	409	MCFG_SCREEN_PALETTE("palette")
410
	410
411	411	MCFG_GFXDECODE_ADD("gfxdecode", "palette", irisha)
412	412	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
413	413

trunk/src/mess/drivers/atari400.c
r29404	r29405
325	325	void ms_atari800xl_machine_start(int type, int has_cart);
326	326
327	327	DECLARE_WRITE8_MEMBER(a600xl_pia_pb_w) { a600xl_mmu(data); }
328
	328
329	329	DECLARE_READ8_MEMBER(atari_pia_pa_r);
330	330	DECLARE_READ8_MEMBER(atari_pia_pb_r);
331	331

trunk/src/mess/drivers/nakajies.c
r29404	r29405
745	745	MCFG_SCREEN_SIZE( 80 * 6, 8 * 8 )
746	746	MCFG_SCREEN_VISIBLE_AREA( 0, 6 * 80 - 1, 0, 8 * 8 - 1 )
747	747	MCFG_SCREEN_PALETTE("palette")
748
	748
749	749	MCFG_GFXDECODE_ADD("gfxdecode", "palette", wales210)
750	750	MCFG_PALETTE_ADD( "palette", 2 )
751	751	MCFG_PALETTE_INIT_OWNER(nakajies_state, nakajies)

trunk/src/mess/drivers/ace.c
r29404	r29405
726	726	MCFG_SCREEN_UPDATE_DRIVER(ace_state, screen_update)
727	727	MCFG_SCREEN_RAW_PARAMS(XTAL_6_5MHz, 416, 0, 336, 312, 0, 304)
728	728	MCFG_SCREEN_PALETTE("palette")
729
	729
730	730	MCFG_TIMER_DRIVER_ADD_SCANLINE("set_irq", ace_state, set_irq, SCREEN_TAG, 31*8, 264)
731	731	MCFG_TIMER_DRIVER_ADD_SCANLINE("clear_irq", ace_state, clear_irq, SCREEN_TAG, 32*8, 264)
732	732

trunk/src/mess/drivers/binbug.c
r29404	r29405
301	301	MCFG_SCREEN_SIZE(512, 256)
302	302	MCFG_SCREEN_VISIBLE_AREA(0, 511, 0, 255)
303	303	MCFG_SCREEN_PALETTE("palette")
304
	304
305	305	MCFG_GFXDECODE_ADD("gfxdecode", "palette", dg640)
306	306	MCFG_PALETTE_ADD_MONOCHROME_AMBER("palette")
307	307
r29404	r29405
561	561	MCFG_SCREEN_SIZE(512, 256)
562	562	MCFG_SCREEN_VISIBLE_AREA(0, 511, 0, 255)
563	563	MCFG_SCREEN_PALETTE("palette")
564
	564
565	565	MCFG_GFXDECODE_ADD("gfxdecode", "palette", dg640)
566	566	MCFG_PALETTE_ADD_MONOCHROME_AMBER("palette")
567	567

trunk/src/mess/drivers/cat.c
r29404	r29405
218	218	(vcc ? ? ? ? ? ? gnd) (random guess: txd, rxd, rts, cts, dsr, dtr, and one pin could be cd/ri though the modem circuit may do that separately?)
219	219	J3: Floppy Connector
220	220	(standard DIL 34 pin 2-row rectangular connector for mini-shugart/pc floppy cable; pin 2 IS connected somewhere and ?probably? is used for /DISKCHANGE like on an Amiga, with pin 34 being /TRUEREADY?)
221		(as opposed to normal ibm pc 3.5" drives where pin 2 is unconnected or is /DENSITY input to drive, and pin 34 is /DISKCHANGE)
	221	(as opposed to normal ibm pc 3.5" drives where pin 2 is unconnected or is /DENSITY input to drive, and pin 34 is /DISKCHANGE)
222	222	J4: 18-pin sip header for keyboard ribbon cable
223	223	(needs tracing to see the VIA hookup order)
224	224	J5: locking-tab-type "CONN HEADER VERT 4POS .100 TIN" connector for supplying power
r29404	r29405
282	282	data, though track 0 is just a disk "unique" identifier for the cat
283	283	meaning 404480 usable bytes
284	284	* (Once the floppy is working I'd declare the system working)
285		- WIP: Centronics port (not sure what is wrong right now, ip4 is never reading
	285	- WIP: Centronics port (not sure what is wrong right now, ip4 is never reading
286	286	as high meaning nothing works; does our centronics implementation correctly
287	287	assert BUSY at all?)
288	288	- RS232C port and Modem "port" connected to the DUART's two ports
r29404	r29405
597	597	* sync is active here for 7 cycles; manual claims 10 but is wrong
598	598	* HST (96) is the horizontal count at which the HSYNC pin goes low
599	599	* sync is inactive here for 7 cycles, manual claims 8 but is wrong?, this is the frontporch
600		* HSE (104) is the horizontal count at which the horizontal counter is reset to 0 (so counts 0-103 then back to 0)
	600	* HSE (104) is the horizontal count at which the horizontal counter is reset to 0 (so counts 0-103 then back to 0)
601	601	*
602	602	* VERTICAL:
603	603	* 0 is the first vertical line displayed to screen
r29404	r29405
654	654	m_keyboard_line = data >> 8;
655	655	}
656	656
657		// 0x800004-0x800005 'pr.data' write
	657	// 0x800004-0x800005 'pr.data' write
658	658	// /DSTB (centronics pin 1) is implied by the cat source code to be pulsed
659	659	// low (for some unknown period of time) upon any write to this port.
660	660	WRITE16_MEMBER( cat_state::cat_printer_data_w )
r29404	r29405
764	764	* \|\|\|\|\|\|\|\-- CC line enable (pin 34) (verified from cat source code)
765	765	* \|\|\|\|\|\|\--- LEDE line enable (pin 33) (verified from cat source code)
766	766	* \|\|\|\|\|\---- ?
767		* \|\|\|\|\----- ? may be IPP (pin 2) write (non-standard pin 34 of centronics port) or another watchdog reset bit; may also be /DSTB-enable-on-pr.data-write
	767	* \|\|\|\|\----- ? may be IPP (pin 2) write (non-standard pin 34 of centronics port) or another watchdog reset bit; may also be /DSTB-enable-on-pr.data-write
768	768	* \|\|\|\------ ?
769	769	* \|\|\------- ?
770	770	* \|\-------- ?
r29404	r29405
835	835	*
836	836	* 76543210
837	837	* ??????\\-- Watchdog count? (counts upward? if this reaches <some unknown number greater than 2> the watchdog fires? writing bit 3 set to opr above resets this)
838		*
	838	*
839	839	* FEDCBA98
840	840	* \|\|\|\|\|\|\|\-- PFAIL state (MB3771 comparator: 1: vcc = 5v; 0: vcc != 5v, hence do not write to svram!)
841	841	* \|\|\|\|\|\|\--- (always 0?)
r29404	r29405
847	847	* \--------- (always 0?)
848	848	*/
849	849	READ16_MEMBER( cat_state::cat_wdt_r )
850		{
	850	{
851	851	uint16 Retval = 0x0100; // set pfail to 1; should this be a dipswitch?
852	852	return Retval \| m_wdt_counter;
853	853	}

trunk/src/mess/drivers/konin.c
r29404	r29405
90	90	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
91	91	MCFG_SCREEN_UPDATE_DRIVER(konin_state, screen_update_konin)
92	92	MCFG_SCREEN_PALETTE("palette")
93
	93
94	94	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
95	95	MACHINE_CONFIG_END
96	96

trunk/src/mess/drivers/wangpc.c
r29404	r29405
1133	1133	MCFG_IM6402_TRO_CALLBACK(DEVWRITELINE(WANGPC_KEYBOARD_TAG, wangpc_keyboard_device, write_rxd))
1134	1134	MCFG_IM6402_DR_CALLBACK(WRITELINE(wangpc_state, uart_dr_w))
1135	1135	MCFG_IM6402_TBRE_CALLBACK(WRITELINE(wangpc_state, uart_tbre_w))
1136
	1136
1137	1137	MCFG_DEVICE_ADD(SCN2661_TAG, MC2661, 0)
1138	1138	MCFG_MC2661_TXD_HANDLER(DEVWRITELINE(RS232_TAG, rs232_port_device, write_txd))
1139	1139	MCFG_MC2661_RXRDY_HANDLER(WRITELINE(wangpc_state, epci_irq_w))

trunk/src/mess/drivers/apricotp.c
r29404	r29405
576	576	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
577	577	MCFG_SCREEN_UPDATE_DEVICE(MC6845_TAG, mc6845_device, screen_update)
578	578	MCFG_SCREEN_SIZE(640, 256)
579		MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 256-1)
	579	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 256-1)
580	580
581	581	MCFG_PALETTE_ADD("palette", 16)
582	582	MCFG_GFXDECODE_ADD("gfxdecode", "palette", act_f1)

trunk/src/mess/drivers/ibmpcjr.c
r29404	r29405
78	78	UINT32 m_raw_keyb_data;
79	79	int m_signal_count;
80	80	UINT8 m_nmi_enabled;
81
	81
82	82	void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
83	83	emu_timer *m_pc_int_delay_timer;
84	84	emu_timer *m_pcjr_watchdog;
r29404	r29405
90	90	TIMER_WATCHDOG,
91	91	TIMER_KB_SIGNAL
92	92	};
93
	93
94	94	void machine_reset();
95	95	DECLARE_DRIVER_INIT(pcjr);
96	96	};
r29404	r29405
146	146	else
147	147	m_pic8259->ir6_w(0);
148	148	break;
149
	149
150	150	case TIMER_KB_SIGNAL:
151	151	m_raw_keyb_data = m_raw_keyb_data >> 1;
152	152	m_signal_count--;
r29404	r29405
246	246	WRITE_LINE_MEMBER(pcjr_state::keyb_interrupt)
247	247	{
248	248	int data;
249
	249
250	250	if(state && (data = m_keyboard->read(machine().driver_data()->generic_space(), 0)))
251	251	{
252	252	UINT8 parity = 0;
r29404	r29405
650	650
651	651	/* video hardware */
652	652	MCFG_PCVIDEO_PCJR_ADD("pcvideo_pcjr")
653
	653
654	654	MCFG_GFXDECODE_ADD("gfxdecode", "pcvideo_pcjr:palette", pcjr)
655	655
656	656	/* sound hardware */

trunk/src/mess/drivers/amust.c
r29404	r29405
94	94
95	95	//WRITE8_MEMBER( amust_state::port00_w )
96	96	//{
97		// membank("bankr0")->set_entry(BIT(data, 6));
98		// m_fdc->dden_w(BIT(data, 5));
99		// floppy_image_device *floppy = NULL;
100		// if (BIT(data, 0)) floppy = m_floppy0->get_device();
101		// m_fdc->set_floppy(floppy);
102		// if (floppy)
103		// floppy->ss_w(BIT(data, 4));
	97	// membank("bankr0")->set_entry(BIT(data, 6));
	98	// m_fdc->dden_w(BIT(data, 5));
	99	// floppy_image_device *floppy = NULL;
	100	// if (BIT(data, 0)) floppy = m_floppy0->get_device();
	101	// m_fdc->set_floppy(floppy);
	102	// if (floppy)
	103	// floppy->ss_w(BIT(data, 4));
104	104	//}
105	105
106	106	static ADDRESS_MAP_START(amust_mem, AS_PROGRAM, 8, amust_state)
r29404	r29405
179	179
180	180	//static I8255_INTERFACE( ppi1_intf )
181	181	//{
182		// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pa_r), // Port A read
183		// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pa_w), // Port A write
184		// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pb_r), // Port B read
185		// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pb_w), // Port B write
186		// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pc_r), // Port C read
187		// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pc_w), // Port C write
	182	// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pa_r), // Port A read
	183	// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pa_w), // Port A write
	184	// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pb_r), // Port B read
	185	// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pb_w), // Port B write
	186	// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pc_r), // Port C read
	187	// DEVCB_DRIVER_MEMBER(amust_state, ppi1_pc_w), // Port C write
188	188	//};
189	189
190	190	//static I8255_INTERFACE( ppi2_intf )
191	191	//{
192		// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pa_r), // Port A read
193		// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pa_w), // Port A write
194		// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pb_r), // Port B read
195		// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pb_w), // Port B write
196		// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pc_r), // Port C read
197		// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pc_w), // Port C write
	192	// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pa_r), // Port A read
	193	// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pa_w), // Port A write
	194	// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pb_r), // Port B read
	195	// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pb_w), // Port B write
	196	// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pc_r), // Port C read
	197	// DEVCB_DRIVER_MEMBER(amust_state, ppi2_pc_w), // Port C write
198	198	//};
199	199
200	200	WRITE8_MEMBER( amust_state::kbd_put )

trunk/src/mess/drivers/ng_aes.c
r29404	r29405
1346	1346
1347	1347	PORT_START("JP") // JP1 and JP2 are jumpers or solderpads depending on AES board revision, intended for use on the Development BIOS
1348	1348	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Short JP1 (Debug Monitor)") PORT_CODE(KEYCODE_F1) PORT_CHANGED_MEMBER(DEVICE_SELF, ng_aes_state, aes_jp1, 0)
1349		// PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) // what is JP2 for? somehow related to system reset, disable watchdog?
	1349	// PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) // what is JP2 for? somehow related to system reset, disable watchdog?
1350	1350	INPUT_PORTS_END
1351	1351
1352	1352	INPUT_CHANGED_MEMBER(ng_aes_state::aes_jp1)

trunk/src/mess/drivers/rsc55.c
r29404	r29405
3	3	Roland Sound Canvas SC-55
4	4
5	5	Skeleton by R. Belmont
6
	6
7	7	Reference and LCD photo: http://www.synthman.com/roland/Roland_SC-55.html
8	8	http://en.wikipedia.org/wiki/Roland_SCC-1
9
	9
10	10	The Roland SC55 is an expander (synthesizer without the keyboard)
11	11	from 1991. It has 24 voice polyphony, is 16 part multitimbral, and
12	12	outputs 16-bit stereo samples at 32 kHz. The synthesis engine uses a
13	13	combination of Roland's LA and straight PCM playback.
14
	14
15	15	The front panel includes the power switch, a headphone jack with volume knob,
16	16	a second MIDI IN port, a large LCD, ALL and MUTE buttons, and a group of up/down
17	17	buttons for Part, Level, Reverb, Key Shift, Instrument, Pan, Chorus, and MIDI Channel.
18
	18
19	19	The SCC-1 is an ISA board variant of the SC55 with a MPU-401 frontend added to
20		communicate with the synth.
21
	20	communicate with the synth.
	21
22	22	Main PCB:
23
	23
24	24	20.0 MHz crystal
25	25	Roland R15239147 HG62E11B23FS 1L1 Japan
26	26	Roland R15199778 6435328A97F 1M1 R Japan
r29404	r29405
30	30	HM62256ALFP-12T 32K by 8-bit RAM
31	31	65256BLFP-12T 32K by 8-bit high-speed pseudo-static RAM
32	32	MB89251A - Serial data transceiver
33
	33
34	34	LCD controller (on front panel board) is a Toshiba T7934.
35	35	*/
36	36
r29404	r29405
51	51
52	52	sc55_state::sc55_state(const machine_config &mconfig, device_type type, const char *tag) :
53	53	driver_device(mconfig, type, tag),
54		m_maincpu(*this, "maincpu")
	54	m_maincpu(*this, "maincpu")
55	55	{
56	56	}
57	57
r29404	r29405
63	63	ADDRESS_MAP_END
64	64
65	65	static MACHINE_CONFIG_START( sc55, sc55_state )
66		MCFG_CPU_ADD( "maincpu", P8098, XTAL_20MHz ) // probably not?
	66	MCFG_CPU_ADD( "maincpu", P8098, XTAL_20MHz ) // probably not?
67	67	MCFG_CPU_PROGRAM_MAP( sc55_map )
68	68	MCFG_CPU_IO_MAP( sc55_io )
69	69	MACHINE_CONFIG_END
70	70
71	71	ROM_START( sc55 )
72	72	ROM_REGION( 0x40000, "maincpu", 0 )
73		ROM_LOAD( "roland_r15209363.ic23", 0x000000, 0x040000, CRC(2dc58549) SHA1(9c17f85e784dc1549ac1f98d457b353393331f6b) )
	73	ROM_LOAD( "roland_r15209363.ic23", 0x000000, 0x040000, CRC(2dc58549) SHA1(9c17f85e784dc1549ac1f98d457b353393331f6b) )
74	74
75	75	ROM_REGION( 0x300000, "la", 0 )
76		ROM_LOAD( "roland-gss.a_r15209276.ic28", 0x000000, 0x100000, CRC(1ac774d3) SHA1(8cc3c0d7ec0993df81d4ca1970e01a4b0d8d3775) )
77		ROM_LOAD( "roland-gss.b_r15209277.ic27", 0x100000, 0x100000, CRC(8dcc592a) SHA1(80e6eb130c18c09955551563f78906163c55cc11) )
78		ROM_LOAD( "roland-gss.c_r15209281.ic26", 0x200000, 0x100000, CRC(e21ebc04) SHA1(7454b817778179806f3f9d1985b3a2ef67ace76f) )
	76	ROM_LOAD( "roland-gss.a_r15209276.ic28", 0x000000, 0x100000, CRC(1ac774d3) SHA1(8cc3c0d7ec0993df81d4ca1970e01a4b0d8d3775) )
	77	ROM_LOAD( "roland-gss.b_r15209277.ic27", 0x100000, 0x100000, CRC(8dcc592a) SHA1(80e6eb130c18c09955551563f78906163c55cc11) )
	78	ROM_LOAD( "roland-gss.c_r15209281.ic26", 0x200000, 0x100000, CRC(e21ebc04) SHA1(7454b817778179806f3f9d1985b3a2ef67ace76f) )
79	79	ROM_END
80	80
81	81	CONS( 1991, sc55, 0, 0, sc55, sc55, driver_device, 0, "Roland", "Sound Canvas SC-55", GAME_NOT_WORKING\|GAME_NO_SOUND )

trunk/src/mess/drivers/ie15.c
r29404	r29405
634	634	IE15_HORZ_START+IE15_DISP_HORZ,IE15_TOTAL_VERT,IE15_VERT_START,
635	635	IE15_VERT_START+IE15_DISP_VERT);
636	636	MCFG_SCREEN_PALETTE("palette")
637
638		MCFG_GFXDECODE_ADD("gfxdecode", "palette", ie15)
	637
	638	MCFG_GFXDECODE_ADD("gfxdecode", "palette", ie15)
639	639	MCFG_PALETTE_ADD("palette", 2)
640	640	MCFG_PALETTE_INIT_OWNER(ie15_state, ie15)
641	641

trunk/src/mess/drivers/hx20.c
r29404	r29405
833	833	MCFG_SCREEN_VISIBLE_AREA(0, 120-1, 0, 32-1)
834	834	MCFG_SCREEN_UPDATE_DRIVER(hx20_state, screen_update)
835	835	MCFG_SCREEN_PALETTE("palette")
836
	836
837	837	MCFG_PALETTE_ADD("palette", 2)
838	838	MCFG_PALETTE_INIT_OWNER(hx20_state, hx20)
839
	839
840	840	MCFG_UPD7227_ADD(UPD7227_0_TAG, 0, 0)
841	841	MCFG_UPD7227_ADD(UPD7227_1_TAG, 40, 0)
842	842	MCFG_UPD7227_ADD(UPD7227_2_TAG, 80, 0)

trunk/src/mess/drivers/pc100.c
r29404	r29405
73	73	m_maincpu(*this, "maincpu"),
74	74	m_beeper(*this, "beeper"),
75	75	m_rtc_portc(0),
76		m_palette(*this, "palette")
	76	m_palette(*this, "palette")
77	77	{
78	78	}
79	79
r29404	r29405
534	534	MCFG_SCREEN_RAW_PARAMS(MASTER_CLOCK4, 1024, 0, 768, 2642, 0, 512)
535	535	MCFG_SCREEN_UPDATE_DRIVER(pc100_state, screen_update_pc100)
536	536	MCFG_SCREEN_PALETTE("palette")
537
	537
538	538	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pc100)
539	539	MCFG_PALETTE_ADD("palette", 16)
540	540	// MCFG_PALETTE_INIT(black_and_white)

trunk/src/mess/drivers/hec2hrp.c
r29404	r29405
648	648	MCFG_SCREEN_VISIBLE_AREA(0, 243, 0, 227)
649	649	MCFG_SCREEN_UPDATE_DRIVER(hec2hrp_state, screen_update_hec2hrp)
650	650	MCFG_SCREEN_PALETTE("palette")
651
	651
652	652	MCFG_VIDEO_START_OVERRIDE(hec2hrp_state,hec2hrp)
653	653	MCFG_PALETTE_ADD("palette", 16)
654	654	MCFG_VIDEO_START_OVERRIDE(hec2hrp_state,hec2hrp)

trunk/src/mess/drivers/spectrum.c
r29404	r29405
707	707
708	708	MCFG_PALETTE_ADD("palette", 16)
709	709	MCFG_PALETTE_INIT_OWNER(spectrum_state, spectrum )
710
	710
711	711	MCFG_GFXDECODE_ADD("gfxdecode", "palette", spectrum)
712	712	MCFG_VIDEO_START_OVERRIDE(spectrum_state, spectrum )
713	713

trunk/src/mess/drivers/pc.c
r29404	r29405
246	246
247	247	MCFG_IBM5150_MOTHERBOARD_ADD("mb", "maincpu")
248	248	MCFG_DEVICE_INPUT_DEFAULTS(pccga)
249
	249
250	250	MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", pc_isa8_cards, "cga", false)
251	251	MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", pc_isa8_cards, "fdc_xt", false)
252	252	MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, "lpt", false)

trunk/src/mess/drivers/esq5505.c
r29404	r29405
222	222	DECLARE_INPUT_CHANGED_MEMBER(key_stroke);
223	223	IRQ_CALLBACK_MEMBER(maincpu_irq_acknowledge_callback);
224	224	DECLARE_WRITE_LINE_MEMBER(esq5505_otis_irq);
225
	225
226	226	//dmac
227	227	DECLARE_WRITE8_MEMBER(dma_end);
228	228	DECLARE_WRITE8_MEMBER(dma_error);

trunk/src/mess/drivers/fp6000.c
r29404	r29405
33	33	m_maincpu(*this, "maincpu")
34	34	, m_crtc(*this, "crtc"),
35	35	m_gfxdecode(*this, "gfxdecode"),
36		m_palette(*this, "palette")
	36	m_palette(*this, "palette")
37	37	{ }
38	38
39	39	UINT8 *m_char_rom;

trunk/src/mess/drivers/fk1.c
r29404	r29405
447	447	MCFG_SCREEN_SIZE(512, 256)
448	448	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
449	449	MCFG_SCREEN_PALETTE("palette")
450
	450
451	451	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
452	452
453	453	MCFG_DEVICE_ADD("pit8253", PIT8253, 0)

trunk/src/mess/drivers/mk85.c
r29404	r29405
74	74	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
75	75	MCFG_SCREEN_UPDATE_DRIVER(mk85_state, screen_update_mk85)
76	76	MCFG_SCREEN_PALETTE("palette")
77
	77
78	78	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
79	79	MACHINE_CONFIG_END
80	80

trunk/src/mess/drivers/mycom.c
r29404	r29405
118	118	required_device<floppy_connector> m_floppy1;
119	119	required_device<sn76489_device> m_audio;
120	120	required_device<msm5832_device> m_rtc;
121		public:
122		required_device<palette_device> m_palette;
	121	public:
	122	required_device<palette_device> m_palette;
123	123	};
124	124
125	125

trunk/src/mess/drivers/apc.c
r29404	r29405
83	83	m_pit(*this, "pit8253"),
84	84	m_video_ram_1(*this, "video_ram_1"),
85	85	m_video_ram_2(*this, "video_ram_2"),
86		m_palette(*this, "palette")
	86	m_palette(*this, "palette")
87	87	{ }
88	88
89	89	// devices
r29404	r29405
101	101
102	102	required_shared_ptr<UINT8> m_video_ram_1;
103	103	required_shared_ptr<UINT8> m_video_ram_2;
104
	104
105	105	required_device<palette_device> m_palette;
106	106
107	107	// screen updates
r29404	r29405
151	151	UINT8 m_dma_offset[4];
152	152
153	153	IRQ_CALLBACK_MEMBER(irq_callback);
154
	154
155	155	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
156	156	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
157	157
r29404	r29405
984	984
985	985	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 3579545) // unk clock
986	986	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
987		MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(apc_state, hgdc_draw_text)
	987	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(apc_state, hgdc_draw_text)
988	988
989	989	MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 3579545) // unk clock
990	990	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
991		MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(apc_state, hgdc_display_pixels)
	991	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(apc_state, hgdc_display_pixels)
992	992
993	993	MCFG_PALETTE_ADD("palette", 16)
994	994	MCFG_PALETTE_INIT_OWNER(apc_state,apc)

trunk/src/mess/drivers/vector06.c
r29404	r29405
176	176	MCFG_SCREEN_VISIBLE_AREA(0, 256+64-1, 0, 256+64-1)
177	177	MCFG_SCREEN_UPDATE_DRIVER(vector06_state, screen_update_vector06)
178	178	MCFG_SCREEN_PALETTE("palette")
179
	179
180	180	MCFG_PALETTE_ADD("palette", 16)
181	181	MCFG_PALETTE_INIT_OWNER(vector06_state, vector06)
182	182

trunk/src/mess/drivers/llc.c
r29404	r29405
217	217	MCFG_SCREEN_VISIBLE_AREA(0, 648-1, 0, 168-1)
218	218	MCFG_SCREEN_UPDATE_DRIVER(llc_state, screen_update_llc1)
219	219	MCFG_SCREEN_PALETTE("palette")
220
	220
221	221	MCFG_GFXDECODE_ADD("gfxdecode", "palette", llc1)
222	222	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
223	223	MCFG_DEFAULT_LAYOUT(layout_llc1)
r29404	r29405
245	245	MCFG_SCREEN_VISIBLE_AREA(0, 648-1, 0, 328-1)
246	246	MCFG_SCREEN_UPDATE_DRIVER(llc_state, screen_update_llc2)
247	247	MCFG_SCREEN_PALETTE("palette")
248
	248
249	249	MCFG_GFXDECODE_ADD("gfxdecode", "palette", llc2)
250	250	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
251	251

trunk/src/mess/drivers/atm.c
r29404	r29405
190	190	MCFG_MACHINE_RESET_OVERRIDE(atm_state, atm )
191	191
192	192	MCFG_BETA_DISK_ADD(BETA_DISK_TAG)
193
	193
194	194	MCFG_GFXDECODE_MODIFY("gfxdecode", atm)
195	195	MACHINE_CONFIG_END
196	196

trunk/src/mess/drivers/sorcerer.c
r29404	r29405
434	434	MCFG_SCREEN_VISIBLE_AREA(0, 648-1, 0, 308-1)
435	435	MCFG_SCREEN_UPDATE_DRIVER(sorcerer_state, screen_update)
436	436	MCFG_SCREEN_PALETTE("palette")
437
	437
438	438	MCFG_GFXDECODE_ADD("gfxdecode", "palette", sorcerer)
439	439	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
440	440

trunk/src/mess/drivers/vta2000.c
r29404	r29405
171	171	MCFG_SCREEN_VISIBLE_AREA(0, 808-1, 0, 2512-1)
172	172	MCFG_SCREEN_UPDATE_DRIVER(vta2000_state, screen_update_vta2000)
173	173	MCFG_SCREEN_PALETTE("palette")
174
175		MCFG_PALETTE_ADD("palette", 3)
	174
	175	MCFG_PALETTE_ADD("palette", 3)
176	176	MCFG_PALETTE_INIT_OWNER(vta2000_state, vta2000)
177	177	MCFG_GFXDECODE_ADD("gfxdecode", "palette", vta2000)
178	178	MACHINE_CONFIG_END

trunk/src/mess/drivers/x07.c
r29404	r29405
1481	1481	MCFG_SCREEN_SIZE(120, 32)
1482	1482	MCFG_SCREEN_VISIBLE_AREA(0, 120-1, 0, 32-1)
1483	1483	MCFG_SCREEN_PALETTE("palette")
1484
	1484
1485	1485	MCFG_PALETTE_ADD("palette", 2)
1486	1486	MCFG_PALETTE_INIT_OWNER(x07_state, x07)
1487	1487	MCFG_DEFAULT_LAYOUT(layout_lcd)
r29404	r29405
1499	1499
1500	1500	MCFG_TIMER_DRIVER_ADD_PERIODIC("blink_timer", x07_state, blink_timer, attotime::from_msec(300))
1501	1501
1502		MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram1", x07_state, nvram_init) // t6834 RAM
	1502	MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram1", x07_state, nvram_init) // t6834 RAM
1503	1503	MCFG_NVRAM_ADD_0FILL("nvram2") // RAM banks
1504	1504
1505	1505	/* internal ram */
r29404	r29405
1540	1540	ROM_REGION( 0x0800, "default", ROMREGION_ERASE00 )
1541	1541	ROM_END
1542	1542
1543		DRIVER_INIT_MEMBER(x07_state, x07)
1544		{
	1543	DRIVER_INIT_MEMBER(x07_state, x07)
	1544	{
1545	1545	UINT8 *RAM = memregion("default")->base();
1546	1546	UINT8 *GFX = memregion("gfx1")->base();
1547
	1547
1548	1548	for (int i = 0; i < 12; i++)
1549	1549	strcpy((char *)RAM + udk_offset[i], udk_ini[i]);
1550
	1550
1551	1551	//copy default chars in the UDC
1552	1552	memcpy(RAM + 0x200, GFX + 0x400, 0x100);
1553	1553	memcpy(RAM + 0x300, GFX + 0x700, 0x100);

trunk/src/mess/drivers/modellot.c
r29404	r29405
167	167	MCFG_SCREEN_VISIBLE_AREA(0, 648-1, 0, 1616-1)
168	168	MCFG_SCREEN_UPDATE_DRIVER(modellot_state, screen_update_modellot)
169	169	MCFG_SCREEN_PALETTE("palette")
170
	170
171	171	MCFG_GFXDECODE_ADD("gfxdecode", "palette", modellot )
172	172	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
173
	173
174	174	/* Devices */
175	175	MCFG_ASCII_KEYBOARD_ADD(KEYBOARD_TAG, keyboard_intf)
176	176	MACHINE_CONFIG_END

trunk/src/mess/drivers/myb3k.c
r29404	r29405
286	286	MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 200-1)
287	287	MCFG_SCREEN_UPDATE_DRIVER(myb3k_state, screen_update_myb3k)
288	288	MCFG_SCREEN_PALETTE("palette")
289
	289
290	290	MCFG_GFXDECODE_ADD("gfxdecode", "palette", myb3k)
291	291	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
292	292

trunk/src/mess/drivers/gb.c
r29404	r29405
756	756	MCFG_SCREEN_VBLANK_TIME(0)
757	757	MCFG_SCREEN_UPDATE_DEVICE("lcd", gb_lcd_device, screen_update)
758	758	MCFG_SCREEN_PALETTE("palette")
759
	759
760	760	MCFG_DEFAULT_LAYOUT(layout_lcd)
761	761	// MCFG_SCREEN_SIZE(208, 188)
762	762	MCFG_SCREEN_SIZE( 458, 154 )
r29404	r29405
797	797	MCFG_SCREEN_MODIFY("screen")
798	798	MCFG_SCREEN_SIZE(328, 288)
799	799	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 08, 288-1)
800
	800
801	801	MCFG_PALETTE_MODIFY("palette")
802	802	MCFG_PALETTE_ENTRIES(32768)
803	803	MCFG_PALETTE_INIT_OWNER(gb_state,sgb)
r29404	r29405
814	814
815	815	MCFG_MACHINE_START_OVERRIDE(gb_state, gbpocket)
816	816	MCFG_MACHINE_RESET_OVERRIDE(gb_state, gbpocket)
817
	817
818	818	MCFG_PALETTE_MODIFY("palette")
819	819	MCFG_PALETTE_INIT_OWNER(gb_state,gbp)
820	820
r29404	r29405
860	860	MCFG_SCREEN_REFRESH_RATE(DMG_FRAMES_PER_SECOND)
861	861	MCFG_SCREEN_VBLANK_TIME(0)
862	862	MCFG_SCREEN_PALETTE("palette")
863
	863
864	864	MCFG_QUANTUM_TIME(attotime::from_hz(60))
865	865
866	866	MCFG_MACHINE_START_OVERRIDE(megaduck_state, megaduck )
r29404	r29405
872	872
873	873	MCFG_DEFAULT_LAYOUT(layout_lcd)
874	874	MCFG_GFXDECODE_ADD("gfxdecode", "palette", gb)
875
	875
876	876	MCFG_PALETTE_ADD("palette", 4)
877	877	MCFG_PALETTE_INIT_OWNER(megaduck_state,megaduck)
878	878

trunk/src/mess/drivers/a2600.c
r29404	r29405
1939	1939	MCFG_TIA_READ_INPUT_PORT_CB(READ16(a2600_state, a2600_read_input_port))
1940	1940	MCFG_TIA_DATABUS_CONTENTS_CB(READ8(a2600_state, a2600_get_databus_contents))
1941	1941	MCFG_TIA_VSYNC_CB(WRITE16(a2600_state, a2600_tia_vsync_callback))
1942
	1942
1943	1943	MCFG_SCREEN_ADD("screen", RASTER)
1944	1944	MCFG_SCREEN_RAW_PARAMS( MASTER_CLOCK_NTSC, 228, 26, 26 + 160 + 16, 262, 24 , 24 + 192 + 31 )
1945	1945	MCFG_SCREEN_UPDATE_DEVICE("tia_video", tia_video_device, screen_update)
r29404	r29405
1977	1977	MCFG_TIA_READ_INPUT_PORT_CB(READ16(a2600_state, a2600_read_input_port))
1978	1978	MCFG_TIA_DATABUS_CONTENTS_CB(READ8(a2600_state, a2600_get_databus_contents))
1979	1979	MCFG_TIA_VSYNC_CB(WRITE16(a2600_state, a2600_tia_vsync_callback_pal))
1980
1981	1980
	1981
1982	1982	MCFG_SCREEN_ADD("screen", RASTER)
1983	1983	MCFG_SCREEN_RAW_PARAMS( MASTER_CLOCK_PAL, 228, 26, 26 + 160 + 16, 312, 32, 32 + 228 + 31 )
1984	1984	MCFG_SCREEN_UPDATE_DEVICE("tia_video", tia_video_device, screen_update)

trunk/src/mess/drivers/homelab.c
r29404	r29405
745	745	MCFG_VIDEO_START_OVERRIDE(homelab_state,homelab2)
746	746	MCFG_SCREEN_UPDATE_DRIVER(homelab_state, screen_update_homelab2)
747	747	MCFG_SCREEN_PALETTE("palette")
748
	748
749	749	MCFG_GFXDECODE_ADD("gfxdecode", "palette", homelab)
750	750	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
751	751
r29404	r29405
776	776	MCFG_VIDEO_START_OVERRIDE(homelab_state,homelab3)
777	777	MCFG_SCREEN_UPDATE_DRIVER(homelab_state, screen_update_homelab3)
778	778	MCFG_SCREEN_PALETTE("palette")
779
	779
780	780	MCFG_GFXDECODE_ADD("gfxdecode", "palette", homelab)
781	781	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
782	782
r29404	r29405
807	807	MCFG_VIDEO_START_OVERRIDE(homelab_state,brailab4)
808	808	MCFG_SCREEN_UPDATE_DRIVER(homelab_state, screen_update_homelab3)
809	809	MCFG_SCREEN_PALETTE("palette")
810
	810
811	811	MCFG_GFXDECODE_ADD("gfxdecode", "palette", homelab)
812	812	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
813	813

trunk/src/mess/drivers/vt220.c
r29404	r29405
68	68	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
69	69	MCFG_SCREEN_UPDATE_DRIVER(vt220_state, screen_update_vt220)
70	70	MCFG_SCREEN_PALETTE("palette")
71
	71
72	72	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
73	73
74	74	/* internal ram */

trunk/src/mess/drivers/amiga.c
r29404	r29405
799	799	// MCFG_SCREEN_RAW_PARAMS(AMIGA_68EC020_NTSC_CLOCK,5122,(129-8-8)2,(449+8-1+8)*2,312,44-8,300+8)
800	800	MCFG_SCREEN_RAW_PARAMS(AMIGA_68EC020_NTSC_CLOCK,2284,214,2284,262,34,262)
801	801
802		MCFG_SCREEN_UPDATE_DRIVER(a1200_state, screen_update_amiga_aga)
	802	MCFG_SCREEN_UPDATE_DRIVER(a1200_state, screen_update_amiga_aga)
803	803
804	804	MCFG_VIDEO_START_OVERRIDE(a1200_state,amiga_aga)
805	805

trunk/src/mess/drivers/pp01.c
r29404	r29405
209	209	MCFG_SCREEN_VISIBLE_AREA(0, 256-1, 0, 256-1)
210	210	MCFG_SCREEN_UPDATE_DRIVER(pp01_state, screen_update_pp01)
211	211	MCFG_SCREEN_PALETTE("palette")
212
	212
213	213	MCFG_PALETTE_ADD("palette", 8)
214	214	MCFG_PALETTE_INIT_OWNER(pp01_state, pp01)
215	215

trunk/src/mess/drivers/odyssey2.c
r29404	r29405
867	867	MCFG_SCREEN_UPDATE_DRIVER(odyssey2_state, screen_update_odyssey2)
868	868	MCFG_SCREEN_PALETTE("palette")
869	869
870		MCFG_GFXDECODE_ADD("gfxdecode", "palette", odyssey2 )
	870	MCFG_GFXDECODE_ADD("gfxdecode", "palette", odyssey2 )
871	871	MCFG_PALETTE_ADD("palette", 16)
872	872	MCFG_PALETTE_INIT_OWNER(g7400_state, g7400)
873	873

trunk/src/mess/drivers/apollo.c
r29404	r29405
44	44	#define APOLLO_MAX_NO_OF_LOG_LINES 1000000
45	45
46	46	// ISA/AT Bus notes
47		// I/O space: to get the Apollo address = take the PC I/O address, keep the low 3 bits how they are, and shift the rest left 7, inserting zeros.
	47	// I/O space: to get the Apollo address = take the PC I/O address, keep the low 3 bits how they are, and shift the rest left 7, inserting zeros.
48	48	// then add 0x40000 for the I/O base.
49	49	//
50	50	// example: 3c503 Ethernet is at I/O 300h on PC, which is (%1100000000 -> 1 1000 0000 0000 0000) + 0x40000 = 0x58000
r29404	r29405
719	719	AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
720	720	AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8(cache_status_register_r, cache_control_register_w, 0xffffffff )
721	721	AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8(task_alias_register_r , task_alias_register_w , 0xffffffff )
722		AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
	722	AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
723	723	AM_RANGE(0x010500, 0x0105ff) AM_DEVREADWRITE8(APOLLO_SIO2_TAG, mc68681_device, read, write, 0x00ff00ff )
724		AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8(APOLLO_PTM_TAG, ptm6840_device, read, write, 0x00ff00ff )
	724	AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8(APOLLO_PTM_TAG, ptm6840_device, read, write, 0x00ff00ff )
725	725	AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
726	726	AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8(/"dma1",/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
727	727	AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8(/"dma2",/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
r29404	r29405
751	751	AM_RANGE(0x000000, 0x007fff) AM_WRITE(apollo_rom_w)
752	752	AM_RANGE(0x008000, 0x0080ff) AM_READWRITE16(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
753	753	AM_RANGE(0x008100, 0x0081ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
754		AM_RANGE(0x008400, 0x0087ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
	754	AM_RANGE(0x008400, 0x0087ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
755	755	AM_RANGE(0x008800, 0x0088ff) AM_DEVREADWRITE8(APOLLO_PTM_TAG, ptm6840_device, read, write, 0x00ff00ff )
756	756	AM_RANGE(0x008900, 0x0089ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
757	757	AM_RANGE(0x009000, 0x0090ff) AM_READWRITE8(/"dma1",/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
r29404	r29405
786	786	AM_RANGE(0x000000, 0x007fff) AM_WRITE(apollo_rom_w)
787	787	AM_RANGE(0x008000, 0x0080ff) AM_READWRITE16(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
788	788	AM_RANGE(0x008100, 0x0081ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
789		AM_RANGE(0x008400, 0x0087ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
	789	AM_RANGE(0x008400, 0x0087ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
790	790	AM_RANGE(0x008800, 0x0088ff) AM_DEVREADWRITE8(APOLLO_PTM_TAG, ptm6840_device, read, write, 0x00ff00ff )
791	791	AM_RANGE(0x008900, 0x0089ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
792	792
r29404	r29405
819	819	AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
820	820	AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8(cache_status_register_r, cache_control_register_w, 0xffffffff )
821	821	AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8(task_alias_register_r , task_alias_register_w , 0xffffffff )
822		AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
	822	AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
823	823	AM_RANGE(0x010500, 0x0105ff) AM_DEVREADWRITE8(APOLLO_SIO2_TAG, mc68681_device, read, write, 0x00ff00ff )
824		AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8(APOLLO_PTM_TAG, ptm6840_device, read, write, 0x00ff00ff )
	824	AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8(APOLLO_PTM_TAG, ptm6840_device, read, write, 0x00ff00ff )
825	825	AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
826	826	AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8(/"dma1",/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
827	827	AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8(/"dma2",/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
r29404	r29405
868	868	AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
869	869	AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8(cache_status_register_r, cache_control_register_w, 0xffffffff )
870	870	AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8(task_alias_register_r , task_alias_register_w , 0xffffffff )
871		AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
	871	AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8(APOLLO_SIO_TAG, mc68681_device, read, write, 0x00ff00ff )
872	872	AM_RANGE(0x010500, 0x0105ff) AM_DEVREADWRITE8(APOLLO_SIO2_TAG, mc68681_device, read, write, 0x00ff00ff )
873		AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8(APOLLO_PTM_TAG, ptm6840_device, read, write, 0x00ff00ff )
	873	AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8(APOLLO_PTM_TAG, ptm6840_device, read, write, 0x00ff00ff )
874	874	AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
875	875	AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8(/"dma1",/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
876	876	AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8(/"dma2",/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
r29404	r29405
925	925	// set node_id from UID of logical volume 1 of logical unit 0
926	926	node_id = (((db[0x49] << 8) \| db[0x4a]) << 8) \| db[0x4b];
927	927
928		MLOG2(("machine_reset_dn3500: node ID is %06X (from disk)", node_id));
	928	MLOG2(("machine_reset_dn3500: node ID is %06X (from disk)", node_id));
929	929	}
930	930	}
931	931	#endif
r29404	r29405
1047	1047	PORT_INCLUDE(apollo_config)
1048	1048	INPUT_PORTS_END
1049	1049
1050		READ_LINE_MEMBER( apollo_state::apollo_kbd_is_german )
	1050	READ_LINE_MEMBER( apollo_state::apollo_kbd_is_german )
1051	1051	{
1052	1052	return (apollo_config(APOLLO_CONF_GERMAN_KBD) != 0) ? ASSERT_LINE : CLEAR_LINE;
1053	1053	}
r29404	r29405
1100	1100	/* video hardware 19" monochrome */
1101	1101	MCFG_APOLLO_MONO19I_ADD(APOLLO_SCREEN_TAG)
1102	1102	MCFG_DEVICE_ADD(APOLLO_KBD_TAG, APOLLO_KBD, 0)
1103		MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
1104		MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
	1103	MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
	1104	MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
1105	1105	MACHINE_CONFIG_END
1106	1106
1107	1107	static MACHINE_CONFIG_DERIVED( dn3500_15i, dn3500 )
1108	1108	/* video hardware is 15" monochrome or color */
1109	1109	MCFG_APOLLO_GRAPHICS_ADD(APOLLO_SCREEN_TAG)
1110	1110	MCFG_DEVICE_ADD(APOLLO_KBD_TAG, APOLLO_KBD, 0)
1111		MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
1112		MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
	1111	MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
	1112	MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
1113	1113	MACHINE_CONFIG_END
1114	1114
1115	1115	static MACHINE_CONFIG_DERIVED( dn3000, dn3500 )
r29404	r29405
1149	1149	/* video hardware 19" monochrome */
1150	1150	MCFG_APOLLO_MONO19I_ADD(APOLLO_SCREEN_TAG)
1151	1151	MCFG_DEVICE_ADD(APOLLO_KBD_TAG, APOLLO_KBD, 0)
1152		MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
1153		MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
	1152	MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
	1153	MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
1154	1154	MACHINE_CONFIG_END
1155	1155
1156	1156	static MACHINE_CONFIG_DERIVED( dn3000_15i, dn3000 )
1157	1157	/* video hardware 15" monochrome */
1158	1158	MCFG_APOLLO_GRAPHICS_ADD(APOLLO_SCREEN_TAG)
1159	1159	MCFG_DEVICE_ADD(APOLLO_KBD_TAG, APOLLO_KBD, 0)
1160		MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
1161		MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
	1160	MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
	1161	MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
1162	1162	MACHINE_CONFIG_END
1163	1163
1164	1164	static MACHINE_CONFIG_DERIVED( dn5500, dn3500 )
r29404	r29405
1186	1186	/* video hardware 19" monochrome */
1187	1187	MCFG_APOLLO_MONO19I_ADD(APOLLO_SCREEN_TAG)
1188	1188	MCFG_DEVICE_ADD(APOLLO_KBD_TAG, APOLLO_KBD, 0)
1189		MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
1190		MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
	1189	MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
	1190	MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
1191	1191	MACHINE_CONFIG_END
1192	1192
1193	1193	static MACHINE_CONFIG_DERIVED( dn5500_15i, dn5500 )
1194	1194	/* video hardware 15" monochrome */
1195	1195	MCFG_APOLLO_GRAPHICS_ADD(APOLLO_SCREEN_TAG)
1196	1196	MCFG_DEVICE_ADD(APOLLO_KBD_TAG, APOLLO_KBD, 0)
1197		MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
1198		MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
	1197	MCFG_APOLLO_KBD_TX_CALLBACK(DEVWRITELINE(APOLLO_SIO_TAG, mc68681_device, rx_a_w))
	1198	MCFG_APOLLO_KBD_GERMAN_CALLBACK(READLINE(apollo_state, apollo_kbd_is_german))
1199	1199	MACHINE_CONFIG_END
1200	1200
1201	1201	/***************************************************************************
r29404	r29405
1265	1265	COMP( 1991, dn5500, dn3500, 0, dn5500_15i, dn3500, apollo_state, dn5500, "Apollo", "Apollo DN5500", GAME_NOT_WORKING )
1266	1266	COMP( 1991, dsp5500, dn3500, 0, dsp5500, dsp3500, apollo_state,dsp5500,"Apollo", "Apollo DSP5500", GAME_NOT_WORKING )
1267	1267	COMP( 1991, dn5500_19i, dn3500, 0, dn5500_19i, dn3500, apollo_state, dn5500, "Apollo", "Apollo DN5500 19\" Monochrome", GAME_NOT_WORKING )
1268

trunk/src/mess/drivers/a7000.c
r29404	r29405
27	27	a7000_state(const machine_config &mconfig, device_type type, const char *tag)
28	28	: driver_device(mconfig, type, tag),
29	29	m_maincpu(*this, "maincpu"),
30		m_palette(*this, "palette")
	30	m_palette(*this, "palette")
31	31	{ }
32	32
33	33	required_device<cpu_device> m_maincpu;

trunk/src/mess/drivers/ibm6580.c
r29404	r29405
83	83	MCFG_SCREEN_SIZE(640, 240)
84	84	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 239)
85	85	MCFG_SCREEN_PALETTE("palette")
86
	86
87	87	MCFG_PALETTE_ADD("palette", 3)
88	88	MCFG_PALETTE_INIT_OWNER(ibm6580_state, ibm6580)
89	89	MACHINE_CONFIG_END

trunk/src/mess/drivers/ti89.c
r29404	r29405
529	529	MCFG_SCREEN_SIZE(240, 128)
530	530	MCFG_SCREEN_VISIBLE_AREA(0, 160-1, 0, 100-1)
531	531	MCFG_SCREEN_PALETTE("palette")
532
	532
533	533	MCFG_PALETTE_ADD("palette", 2)
534	534	MCFG_PALETTE_INIT_OWNER(ti68k_state, ti68k)
535	535	MCFG_DEFAULT_LAYOUT(layout_lcd)

trunk/src/mess/drivers/a7800.c
r29404	r29405
74	74
75	75	2014/01/02 Robert Tuccitto Corrected joystick buttons assignment & minor
76	76	palette notes cleanup.
77
	77
78	78	2014/01/09 Robert Tuccitto Positional description for difficulty
79	79	switches added.
80
	80
81	81	2014/02/15 Robert Tuccitto Added more details and clarification
82	82	regarding the potentiometer.
83	83
r29404	r29405
177	177	calibration) on a modern flat panel display, as opposed to 'gold' (~-33
178	178	degrees) on a CRT.
179	179
180		The potentiometer (pot adjustment) for the 7800 modifies the delay line
181		regarding colors it will exhibit and is extremely sensitive. The slightest
182		turn can have a significant impact.
	180	The potentiometer (pot adjustment) for the 7800 modifies the delay line
	181	regarding colors it will exhibit and is extremely sensitive. The slightest
	182	turn can have a significant impact.
183	183
184		A system whose potentiometer is not properly calibrated via
185		'CPS 7800 Diagnostic Test Cartridge' or/and just slightly off from the
186		desired factory settings may exhibit consequences such as too much blue in
187		place of green (Pot adjusted slightly too far left) or washed out reddish
188		tones in place of where most other systems display a darker reddish tones
189		(Pot adjusted slightly too far right).
	184	A system whose potentiometer is not properly calibrated via
	185	'CPS 7800 Diagnostic Test Cartridge' or/and just slightly off from the
	186	desired factory settings may exhibit consequences such as too much blue in
	187	place of green (Pot adjusted slightly too far left) or washed out reddish
	188	tones in place of where most other systems display a darker reddish tones
	189	(Pot adjusted slightly too far right).
190	190
191		This is a result of the phase shifting of lesser degrees (Pot adjusted more
192		to the left) or phase shifting of greater degrees (Pot adjusted more to the
193		right).
	191	This is a result of the phase shifting of lesser degrees (Pot adjusted more
	192	to the left) or phase shifting of greater degrees (Pot adjusted more to the
	193	right).
194	194
195		Turning the pot adjustment to the right, it can be observed that the values
196		of the higher end of the scale will match the lower end of the scale.
197		For example, after some turning to the right, the values of Dx, Ex, Fx,
198		can be set to match 1x, 2x, 3x.
	195	Turning the pot adjustment to the right, it can be observed that the values
	196	of the higher end of the scale will match the lower end of the scale.
	197	For example, after some turning to the right, the values of Dx, Ex, Fx,
	198	can be set to match 1x, 2x, 3x.
199	199
200		After further turning to the right, now the palette can be brought to make
201		Ax, Bx, Cx, Dx, Ex, Fx will match 1x, 2x, 3x, 4x, 5x, 6x.
	200	After further turning to the right, now the palette can be brought to make
	201	Ax, Bx, Cx, Dx, Ex, Fx will match 1x, 2x, 3x, 4x, 5x, 6x.
202	202
203		Ultimately though, too much turning to the right results in all colors being
204		wiped from the scale, excluding the hue begin point 1x (Which remains
	203	Ultimately though, too much turning to the right results in all colors being
	204	wiped from the scale, excluding the hue begin point 1x (Which remains
205	205	unchanged while tweaking the potentiometer either left or right).
206	206
207		Continuously turning the pot adjustment to the left, red and blue become the
208		most dominant two colors encompassing the palette with only a slight
209		influence of green at the highest end of the palette (Fx), once turned all
	207	Continuously turning the pot adjustment to the left, red and blue become the
	208	most dominant two colors encompassing the palette with only a slight
	209	influence of green at the highest end of the palette (Fx), once turned all
210	210	the way leftward.
211	211
212		The degree range for adjustment of the phase shifting on the 7800 appears
213		to be as low as approximately 15 degrees when tuned all the way left, and
214		seems to be able to achieve as high as approximately 45 degrees when turned
	212	The degree range for adjustment of the phase shifting on the 7800 appears
	213	to be as low as approximately 15 degrees when tuned all the way left, and
	214	seems to be able to achieve as high as approximately 45 degrees when turned
215	215	right before losing all color (Excluding 1x) from the palette scale.
216	216
217		For even a properly calibrated system at power on, the system's phase
218		shift appears as low as ~23 degrees and after a considerable consistent
	217	For even a properly calibrated system at power on, the system's phase
	218	shift appears as low as ~23 degrees and after a considerable consistent
219	219	runtime ('warm-up'), can be as high as ~28 degrees.
220	220
221	221	In general, the low end of ~23 degrees lasts for maybe several seconds,
r29404	r29405
224	224	near exact match of Hue 1x and 15x - To the naked eye they appear to be
225	225	the same).
226	226
227		However, consistent system run time causes Hue 15x (F$) to become
	227	However, consistent system run time causes Hue 15x (F$) to become
228	228	stronger/darker gold (More brown then ultimately red-brown); as well
229	229	as leans Hue 14x (E$) more brown than green. Once achieving a phase shift
230	230	of 27.7, Hue 14x (E$) and Hue 15x (F$) near-exact match Hue 1x and 2x
r29404	r29405
265	265	***************************************************************************/
266	266
267	267	#define NTSC_GREY \
268		rgb_t(0x00,0x00,0x00), rgb_t(0x11,0x11,0x11), rgb_t(0x22,0x22,0x22), rgb_t(0x33,0x33,0x33), \
269		rgb_t(0x44,0x44,0x44), rgb_t(0x55,0x55,0x55), rgb_t(0x66,0x66,0x66), rgb_t(0x77,0x77,0x77), \
270		rgb_t(0x88,0x88,0x88), rgb_t(0x99,0x99,0x99), rgb_t(0xAA,0xAA,0xAA), rgb_t(0xBB,0xBB,0xBB), \
271		rgb_t(0xCC,0xCC,0xCC), rgb_t(0xDD,0xDD,0xDD), rgb_t(0xEE,0xEE,0xEE), rgb_t(0xFF,0xFF,0xFF )
	268	rgb_t(0x00,0x00,0x00), rgb_t(0x11,0x11,0x11), rgb_t(0x22,0x22,0x22), rgb_t(0x33,0x33,0x33), \
	269	rgb_t(0x44,0x44,0x44), rgb_t(0x55,0x55,0x55), rgb_t(0x66,0x66,0x66), rgb_t(0x77,0x77,0x77), \
	270	rgb_t(0x88,0x88,0x88), rgb_t(0x99,0x99,0x99), rgb_t(0xAA,0xAA,0xAA), rgb_t(0xBB,0xBB,0xBB), \
	271	rgb_t(0xCC,0xCC,0xCC), rgb_t(0xDD,0xDD,0xDD), rgb_t(0xEE,0xEE,0xEE), rgb_t(0xFF,0xFF,0xFF )
272	272
273	273	#define NTSC_GOLD \
274		rgb_t(0x1A,0x07,0x00), rgb_t(0x2B,0x18,0x00), rgb_t(0x3C,0x29,0x00), rgb_t(0x4D,0x3A,0x00), \
275		rgb_t(0x5E,0x4B,0x00), rgb_t(0x6F,0x5C,0x00), rgb_t(0x80,0x6D,0x00), rgb_t(0x91,0x7E,0x09), \
276		rgb_t(0xA2,0x8F,0x1A), rgb_t(0xB3,0xA0,0x2B), rgb_t(0xC4,0xB1,0x3C), rgb_t(0xD5,0xC2,0x4D), \
277		rgb_t(0xE6,0xD3,0x5E), rgb_t(0xF7,0xE4,0x6F), rgb_t(0xFF,0xF5,0x83), rgb_t(0xFF,0xF7,0x97 )
	274	rgb_t(0x1A,0x07,0x00), rgb_t(0x2B,0x18,0x00), rgb_t(0x3C,0x29,0x00), rgb_t(0x4D,0x3A,0x00), \
	275	rgb_t(0x5E,0x4B,0x00), rgb_t(0x6F,0x5C,0x00), rgb_t(0x80,0x6D,0x00), rgb_t(0x91,0x7E,0x09), \
	276	rgb_t(0xA2,0x8F,0x1A), rgb_t(0xB3,0xA0,0x2B), rgb_t(0xC4,0xB1,0x3C), rgb_t(0xD5,0xC2,0x4D), \
	277	rgb_t(0xE6,0xD3,0x5E), rgb_t(0xF7,0xE4,0x6F), rgb_t(0xFF,0xF5,0x83), rgb_t(0xFF,0xF7,0x97 )
278	278
279	279	#define NTSC_ORANGE \
280		rgb_t(0x31,0x00,0x00), rgb_t(0x42,0x06,0x00), rgb_t(0x53,0x17,0x00), rgb_t(0x64,0x28,0x00), \
281		rgb_t(0x75,0x39,0x00), rgb_t(0x86,0X4A,0x00), rgb_t(0x97,0x5B,0x0A), rgb_t(0xA8,0x6C,0x1B), \
282		rgb_t(0xB9,0x7D,0x2C), rgb_t(0xCA,0x8E,0x3D), rgb_t(0xDB,0x9F,0x4E), rgb_t(0xEC,0xB0,0x5F), \
283		rgb_t(0xFD,0xC1,0x70), rgb_t(0xFF,0xD2,0x85), rgb_t(0xFF,0xE3,0x9C), rgb_t(0xFF,0xF4,0xB2 )
	280	rgb_t(0x31,0x00,0x00), rgb_t(0x42,0x06,0x00), rgb_t(0x53,0x17,0x00), rgb_t(0x64,0x28,0x00), \
	281	rgb_t(0x75,0x39,0x00), rgb_t(0x86,0X4A,0x00), rgb_t(0x97,0x5B,0x0A), rgb_t(0xA8,0x6C,0x1B), \
	282	rgb_t(0xB9,0x7D,0x2C), rgb_t(0xCA,0x8E,0x3D), rgb_t(0xDB,0x9F,0x4E), rgb_t(0xEC,0xB0,0x5F), \
	283	rgb_t(0xFD,0xC1,0x70), rgb_t(0xFF,0xD2,0x85), rgb_t(0xFF,0xE3,0x9C), rgb_t(0xFF,0xF4,0xB2 )
284	284
285	285	#define NTSC_RED_ORANGE \
286		rgb_t(0x3E,0x00,0x00), rgb_t(0x4F,0x00,0x00), rgb_t(0x60,0x08,0x00), rgb_t(0x71,0x19,0x00), \
287		rgb_t(0x82,0x2A,0x0D), rgb_t(0x93,0x3B,0x1E), rgb_t(0xA4,0x4C,0x2F), rgb_t(0xB5,0x5D,0x40), \
288		rgb_t(0xC6,0x6E,0x51), rgb_t(0xD7,0x7F,0x62), rgb_t(0xE8,0x90,0x73), rgb_t(0xF9,0xA1,0x83), \
289		rgb_t(0xFF,0xB2,0x98), rgb_t(0xFF,0xC3,0xAE), rgb_t(0xFF,0xD4,0xC4), rgb_t(0xFF,0xE5,0xDA )
	286	rgb_t(0x3E,0x00,0x00), rgb_t(0x4F,0x00,0x00), rgb_t(0x60,0x08,0x00), rgb_t(0x71,0x19,0x00), \
	287	rgb_t(0x82,0x2A,0x0D), rgb_t(0x93,0x3B,0x1E), rgb_t(0xA4,0x4C,0x2F), rgb_t(0xB5,0x5D,0x40), \
	288	rgb_t(0xC6,0x6E,0x51), rgb_t(0xD7,0x7F,0x62), rgb_t(0xE8,0x90,0x73), rgb_t(0xF9,0xA1,0x83), \
	289	rgb_t(0xFF,0xB2,0x98), rgb_t(0xFF,0xC3,0xAE), rgb_t(0xFF,0xD4,0xC4), rgb_t(0xFF,0xE5,0xDA )
290	290
291	291	#define NTSC_PINK \
292		rgb_t(0x3F,0x00,0x03), rgb_t(0x50,0x00,0x0F), rgb_t(0x61,0x00,0x1B), rgb_t(0x72,0x0F,0x2B), \
293		rgb_t(0x83,0x20,0x3C), rgb_t(0x94,0x31,0x4D), rgb_t(0xA5,0x42,0x5E), rgb_t(0xB6,0x53,0x6F), \
294		rgb_t(0xC7,0x64,0x80), rgb_t(0xD8,0x75,0x91), rgb_t(0xE9,0x86,0xA2), rgb_t(0xFA,0x97,0xB3), \
295		rgb_t(0xFF,0xA8,0xC8), rgb_t(0xFF,0xB9,0xDE), rgb_t(0xFF,0xCA,0xEF), rgb_t(0xFF,0xDB,0xF4 )
	292	rgb_t(0x3F,0x00,0x03), rgb_t(0x50,0x00,0x0F), rgb_t(0x61,0x00,0x1B), rgb_t(0x72,0x0F,0x2B), \
	293	rgb_t(0x83,0x20,0x3C), rgb_t(0x94,0x31,0x4D), rgb_t(0xA5,0x42,0x5E), rgb_t(0xB6,0x53,0x6F), \
	294	rgb_t(0xC7,0x64,0x80), rgb_t(0xD8,0x75,0x91), rgb_t(0xE9,0x86,0xA2), rgb_t(0xFA,0x97,0xB3), \
	295	rgb_t(0xFF,0xA8,0xC8), rgb_t(0xFF,0xB9,0xDE), rgb_t(0xFF,0xCA,0xEF), rgb_t(0xFF,0xDB,0xF4 )
296	296
297	297	#define NTSC_PURPLE \
298		rgb_t(0x33,0x00,0x35), rgb_t(0x44,0x00,0x41), rgb_t(0x55,0x00,0x4C), rgb_t(0x66,0x0C,0x5C), \
299		rgb_t(0x77,0x1D,0x6D), rgb_t(0x88,0x2E,0x7E), rgb_t(0x99,0x3F,0x8F), rgb_t(0xAA,0x50,0xA0), \
300		rgb_t(0xBB,0x61,0xB1), rgb_t(0xCC,0x72,0xC2), rgb_t(0xDD,0x83,0xD3), rgb_t(0xEE,0x94,0xE4), \
301		rgb_t(0xFF,0xA5,0xE4), rgb_t(0xFF,0xB6,0xE9), rgb_t(0xFF,0xC7,0xEE), rgb_t(0xFF,0xD8,0xF3 )
	298	rgb_t(0x33,0x00,0x35), rgb_t(0x44,0x00,0x41), rgb_t(0x55,0x00,0x4C), rgb_t(0x66,0x0C,0x5C), \
	299	rgb_t(0x77,0x1D,0x6D), rgb_t(0x88,0x2E,0x7E), rgb_t(0x99,0x3F,0x8F), rgb_t(0xAA,0x50,0xA0), \
	300	rgb_t(0xBB,0x61,0xB1), rgb_t(0xCC,0x72,0xC2), rgb_t(0xDD,0x83,0xD3), rgb_t(0xEE,0x94,0xE4), \
	301	rgb_t(0xFF,0xA5,0xE4), rgb_t(0xFF,0xB6,0xE9), rgb_t(0xFF,0xC7,0xEE), rgb_t(0xFF,0xD8,0xF3 )
302	302
303	303	#define NTSC_PURPLE_BLUE \
304		rgb_t(0x1D,0x00,0x5C), rgb_t(0x2E,0x00,0x68), rgb_t(0x40,0x00,0x74), rgb_t(0x51,0x10,0x84), \
305		rgb_t(0x62,0x21,0x95), rgb_t(0x73,0x32,0xA6), rgb_t(0x84,0x43,0xB7), rgb_t(0x95,0x54,0xC8), \
306		rgb_t(0xA6,0x65,0xD9), rgb_t(0xB7,0x76,0xEA), rgb_t(0xC8,0x87,0xEB), rgb_t(0xD9,0x98,0xEB), \
307		rgb_t(0xE9,0xA9,0xEC), rgb_t(0xFB,0xBA,0xEB), rgb_t(0xFF,0xCB,0xEF), rgb_t(0xFF,0xDC,0xF4 )
	304	rgb_t(0x1D,0x00,0x5C), rgb_t(0x2E,0x00,0x68), rgb_t(0x40,0x00,0x74), rgb_t(0x51,0x10,0x84), \
	305	rgb_t(0x62,0x21,0x95), rgb_t(0x73,0x32,0xA6), rgb_t(0x84,0x43,0xB7), rgb_t(0x95,0x54,0xC8), \
	306	rgb_t(0xA6,0x65,0xD9), rgb_t(0xB7,0x76,0xEA), rgb_t(0xC8,0x87,0xEB), rgb_t(0xD9,0x98,0xEB), \
	307	rgb_t(0xE9,0xA9,0xEC), rgb_t(0xFB,0xBA,0xEB), rgb_t(0xFF,0xCB,0xEF), rgb_t(0xFF,0xDC,0xF4 )
308	308
309	309	#define NTSC_BLUE1 \
310		rgb_t(0x02,0x00,0x71), rgb_t(0x13,0x00,0x7D), rgb_t(0x24,0x0B,0x8C), rgb_t(0x35,0x1C,0x9D), \
311		rgb_t(0x46,0x2D,0xAE), rgb_t(0x57,0x3E,0xBF), rgb_t(0x68,0x4F,0xD0), rgb_t(0x79,0x60,0xE1), \
312		rgb_t(0x8A,0x71,0xF2), rgb_t(0x9B,0x82,0xF7), rgb_t(0xAC,0x93,0xF7), rgb_t(0xBD,0xA4,0xF7), \
313		rgb_t(0xCE,0xB5,0xF7), rgb_t(0xDF,0xC6,0xF7), rgb_t(0xF0,0xD7,0xF7), rgb_t(0xFF,0xE8,0xF8 )
	310	rgb_t(0x02,0x00,0x71), rgb_t(0x13,0x00,0x7D), rgb_t(0x24,0x0B,0x8C), rgb_t(0x35,0x1C,0x9D), \
	311	rgb_t(0x46,0x2D,0xAE), rgb_t(0x57,0x3E,0xBF), rgb_t(0x68,0x4F,0xD0), rgb_t(0x79,0x60,0xE1), \
	312	rgb_t(0x8A,0x71,0xF2), rgb_t(0x9B,0x82,0xF7), rgb_t(0xAC,0x93,0xF7), rgb_t(0xBD,0xA4,0xF7), \
	313	rgb_t(0xCE,0xB5,0xF7), rgb_t(0xDF,0xC6,0xF7), rgb_t(0xF0,0xD7,0xF7), rgb_t(0xFF,0xE8,0xF8 )
314	314
315	315	#define NTSC_BLUE2 \
316		rgb_t(0x00,0x00,0x68), rgb_t(0x00,0x0A,0x7C), rgb_t(0x08,0x1B,0x90), rgb_t(0x19,0x2C,0xA1), \
317		rgb_t(0x2A,0x3D,0xB2), rgb_t(0x3B,0x4E,0xC3), rgb_t(0x4C,0x5F,0xD4), rgb_t(0x5D,0x70,0xE5), \
318		rgb_t(0x6E,0x81,0xF6), rgb_t(0x7F,0x92,0xFF), rgb_t(0x90,0xA3,0xFF), rgb_t(0xA1,0xB4,0xFF), \
319		rgb_t(0xB2,0xC5,0xFF), rgb_t(0xC3,0xD6,0xFF), rgb_t(0xD4,0xE7,0xFF), rgb_t(0xE5,0xF8,0xFF )
	316	rgb_t(0x00,0x00,0x68), rgb_t(0x00,0x0A,0x7C), rgb_t(0x08,0x1B,0x90), rgb_t(0x19,0x2C,0xA1), \
	317	rgb_t(0x2A,0x3D,0xB2), rgb_t(0x3B,0x4E,0xC3), rgb_t(0x4C,0x5F,0xD4), rgb_t(0x5D,0x70,0xE5), \
	318	rgb_t(0x6E,0x81,0xF6), rgb_t(0x7F,0x92,0xFF), rgb_t(0x90,0xA3,0xFF), rgb_t(0xA1,0xB4,0xFF), \
	319	rgb_t(0xB2,0xC5,0xFF), rgb_t(0xC3,0xD6,0xFF), rgb_t(0xD4,0xE7,0xFF), rgb_t(0xE5,0xF8,0xFF )
320	320
321	321	#define NTSC_LIGHT_BLUE \
322		rgb_t(0x00,0x0A,0x4D), rgb_t(0x00,0x1B,0x63), rgb_t(0x00,0x2C,0x79), rgb_t(0x02,0x3D,0x8F), \
323		rgb_t(0x13,0x4E,0xA0), rgb_t(0x24,0x5F,0xB1), rgb_t(0x35,0x70,0xC2), rgb_t(0x46,0x81,0xD3), \
324		rgb_t(0x57,0x92,0xE4), rgb_t(0x68,0xA3,0xF5), rgb_t(0x79,0xB4,0xFF), rgb_t(0x8A,0xC5,0xFF), \
325		rgb_t(0x9B,0xD6,0xFF), rgb_t(0xAC,0xE7,0xFF), rgb_t(0xBD,0xF8,0xFF), rgb_t(0xCE,0xFF,0xFF )
	322	rgb_t(0x00,0x0A,0x4D), rgb_t(0x00,0x1B,0x63), rgb_t(0x00,0x2C,0x79), rgb_t(0x02,0x3D,0x8F), \
	323	rgb_t(0x13,0x4E,0xA0), rgb_t(0x24,0x5F,0xB1), rgb_t(0x35,0x70,0xC2), rgb_t(0x46,0x81,0xD3), \
	324	rgb_t(0x57,0x92,0xE4), rgb_t(0x68,0xA3,0xF5), rgb_t(0x79,0xB4,0xFF), rgb_t(0x8A,0xC5,0xFF), \
	325	rgb_t(0x9B,0xD6,0xFF), rgb_t(0xAC,0xE7,0xFF), rgb_t(0xBD,0xF8,0xFF), rgb_t(0xCE,0xFF,0xFF )
326	326
327	327	#define NTSC_TURQUOISE \
328		rgb_t(0x00,0x1A,0x26), rgb_t(0x00,0x2B,0x3C), rgb_t(0x00,0x3C,0x52), rgb_t(0x00,0x4D,0x68), \
329		rgb_t(0x06,0x5E,0x7C), rgb_t(0x17,0x6F,0x8D), rgb_t(0x28,0x80,0x9E), rgb_t(0x39,0x91,0xAF), \
330		rgb_t(0x4A,0xA2,0xC0), rgb_t(0x5B,0xB3,0xD1), rgb_t(0x6C,0xC4,0xE2), rgb_t(0x7D,0xD5,0xF3), \
331		rgb_t(0x8E,0xE6,0xFF), rgb_t(0x9F,0xF7,0xFF), rgb_t(0xB0,0xFF,0xFF), rgb_t(0xC1,0xFF,0xFF )
	328	rgb_t(0x00,0x1A,0x26), rgb_t(0x00,0x2B,0x3C), rgb_t(0x00,0x3C,0x52), rgb_t(0x00,0x4D,0x68), \
	329	rgb_t(0x06,0x5E,0x7C), rgb_t(0x17,0x6F,0x8D), rgb_t(0x28,0x80,0x9E), rgb_t(0x39,0x91,0xAF), \
	330	rgb_t(0x4A,0xA2,0xC0), rgb_t(0x5B,0xB3,0xD1), rgb_t(0x6C,0xC4,0xE2), rgb_t(0x7D,0xD5,0xF3), \
	331	rgb_t(0x8E,0xE6,0xFF), rgb_t(0x9F,0xF7,0xFF), rgb_t(0xB0,0xFF,0xFF), rgb_t(0xC1,0xFF,0xFF )
332	332
333	333	#define NTSC_GREEN_BLUE \
334		rgb_t(0x00,0x24,0x0B), rgb_t(0x00,0x35,0x10), rgb_t(0x00,0x46,0x22), rgb_t(0x00,0x57,0x38), \
335		rgb_t(0x05,0x68,0x4D), rgb_t(0x16,0x79,0x5E), rgb_t(0x27,0x8A,0x6F), rgb_t(0x38,0x9B,0x80), \
336		rgb_t(0x49,0xAC,0x91), rgb_t(0x5A,0xBD,0xA2), rgb_t(0x6B,0xCE,0xB3), rgb_t(0x7C,0xDF,0xC4), \
337		rgb_t(0x8D,0xF0,0xD5), rgb_t(0x9E,0xFF,0xE5), rgb_t(0xAF,0xFF,0xF1), rgb_t(0xC0,0xFF,0xFD )
	334	rgb_t(0x00,0x24,0x0B), rgb_t(0x00,0x35,0x10), rgb_t(0x00,0x46,0x22), rgb_t(0x00,0x57,0x38), \
	335	rgb_t(0x05,0x68,0x4D), rgb_t(0x16,0x79,0x5E), rgb_t(0x27,0x8A,0x6F), rgb_t(0x38,0x9B,0x80), \
	336	rgb_t(0x49,0xAC,0x91), rgb_t(0x5A,0xBD,0xA2), rgb_t(0x6B,0xCE,0xB3), rgb_t(0x7C,0xDF,0xC4), \
	337	rgb_t(0x8D,0xF0,0xD5), rgb_t(0x9E,0xFF,0xE5), rgb_t(0xAF,0xFF,0xF1), rgb_t(0xC0,0xFF,0xFD )
338	338
339	339	#define NTSC_GREEN \
340		rgb_t(0x00,0x27,0x0C), rgb_t(0x00,0x38,0x11), rgb_t(0x00,0x49,0x16), rgb_t(0x00,0x5A,0x1B), \
341		rgb_t(0x10,0x6B,0x1B), rgb_t(0x21,0x7C,0x2C), rgb_t(0x32,0x8D,0x3D), rgb_t(0x43,0x9E,0x4E), \
342		rgb_t(0x54,0xAF,0x5F), rgb_t(0x65,0xC0,0x70), rgb_t(0x76,0xD1,0x81), rgb_t(0x87,0xE2,0x92), \
343		rgb_t(0x98,0xF3,0xA3), rgb_t(0xA9,0xFF,0xB3), rgb_t(0xBA,0xFF,0xBF), rgb_t(0xCB,0xFF,0xCB )
	340	rgb_t(0x00,0x27,0x0C), rgb_t(0x00,0x38,0x11), rgb_t(0x00,0x49,0x16), rgb_t(0x00,0x5A,0x1B), \
	341	rgb_t(0x10,0x6B,0x1B), rgb_t(0x21,0x7C,0x2C), rgb_t(0x32,0x8D,0x3D), rgb_t(0x43,0x9E,0x4E), \
	342	rgb_t(0x54,0xAF,0x5F), rgb_t(0x65,0xC0,0x70), rgb_t(0x76,0xD1,0x81), rgb_t(0x87,0xE2,0x92), \
	343	rgb_t(0x98,0xF3,0xA3), rgb_t(0xA9,0xFF,0xB3), rgb_t(0xBA,0xFF,0xBF), rgb_t(0xCB,0xFF,0xCB )
344	344
345	345	#define NTSC_YELLOW_GREEN \
346		rgb_t(0x00,0x23,0x0A), rgb_t(0x00,0x34,0x10), rgb_t(0x04,0x45,0x13), rgb_t(0x15,0x56,0x13), \
347		rgb_t(0x26,0x67,0x13), rgb_t(0x37,0x78,0x13), rgb_t(0x48,0x89,0x14), rgb_t(0x59,0x9A,0x25), \
348		rgb_t(0x6A,0xAB,0x36), rgb_t(0x7B,0xBC,0x47), rgb_t(0x8C,0xCD,0x58), rgb_t(0x9D,0xDE,0x69), \
349		rgb_t(0xAE,0xEF,0x7A), rgb_t(0xBF,0xFF,0x8B), rgb_t(0xD0,0xFF,0x97), rgb_t(0xE1,0xFF,0xA3 )
	346	rgb_t(0x00,0x23,0x0A), rgb_t(0x00,0x34,0x10), rgb_t(0x04,0x45,0x13), rgb_t(0x15,0x56,0x13), \
	347	rgb_t(0x26,0x67,0x13), rgb_t(0x37,0x78,0x13), rgb_t(0x48,0x89,0x14), rgb_t(0x59,0x9A,0x25), \
	348	rgb_t(0x6A,0xAB,0x36), rgb_t(0x7B,0xBC,0x47), rgb_t(0x8C,0xCD,0x58), rgb_t(0x9D,0xDE,0x69), \
	349	rgb_t(0xAE,0xEF,0x7A), rgb_t(0xBF,0xFF,0x8B), rgb_t(0xD0,0xFF,0x97), rgb_t(0xE1,0xFF,0xA3 )
350	350
351	351	#define NTSC_ORANGE_GREEN \
352		rgb_t(0x00,0x17,0x07), rgb_t(0x0E,0x28,0x08), rgb_t(0x1F,0x39,0x08), rgb_t(0x30,0x4A,0x08), \
353		rgb_t(0x41,0x5B,0x08), rgb_t(0x52,0x6C,0x08), rgb_t(0x63,0x7D,0x08), rgb_t(0x74,0x8E,0x0D), \
354		rgb_t(0x85,0x9F,0x1E), rgb_t(0x96,0xB0,0x2F), rgb_t(0xA7,0xC1,0x40), rgb_t(0xB8,0xD2,0x51), \
355		rgb_t(0xC9,0xE3,0x62), rgb_t(0xDA,0xF4,0x73), rgb_t(0xEB,0xFF,0x82), rgb_t(0xFC,0xFF,0x8E )
	352	rgb_t(0x00,0x17,0x07), rgb_t(0x0E,0x28,0x08), rgb_t(0x1F,0x39,0x08), rgb_t(0x30,0x4A,0x08), \
	353	rgb_t(0x41,0x5B,0x08), rgb_t(0x52,0x6C,0x08), rgb_t(0x63,0x7D,0x08), rgb_t(0x74,0x8E,0x0D), \
	354	rgb_t(0x85,0x9F,0x1E), rgb_t(0x96,0xB0,0x2F), rgb_t(0xA7,0xC1,0x40), rgb_t(0xB8,0xD2,0x51), \
	355	rgb_t(0xC9,0xE3,0x62), rgb_t(0xDA,0xF4,0x73), rgb_t(0xEB,0xFF,0x82), rgb_t(0xFC,0xFF,0x8E )
356	356
357	357	#define NTSC_LIGHT_ORANGE \
358		rgb_t(0x19,0x07,0x00), rgb_t(0x2A,0x18,0x00), rgb_t(0x3B,0x29,0x00), rgb_t(0x4C,0x3A,0x00), \
359		rgb_t(0x5D,0x4B,0x00), rgb_t(0x6E,0x5C,0x00), rgb_t(0x7F,0x6D,0x00), rgb_t(0x90,0x7E,0x09), \
360		rgb_t(0xA1,0x8F,0x1A), rgb_t(0xB2,0xA0,0x2B), rgb_t(0xC3,0xB1,0x3C), rgb_t(0xD4,0xC2,0x4D), \
361		rgb_t(0xE5,0xD3,0x5E), rgb_t(0xF6,0xE4,0x6F), rgb_t(0xFF,0xF5,0x82), rgb_t(0xFF,0xFF,0x96 )
	358	rgb_t(0x19,0x07,0x00), rgb_t(0x2A,0x18,0x00), rgb_t(0x3B,0x29,0x00), rgb_t(0x4C,0x3A,0x00), \
	359	rgb_t(0x5D,0x4B,0x00), rgb_t(0x6E,0x5C,0x00), rgb_t(0x7F,0x6D,0x00), rgb_t(0x90,0x7E,0x09), \
	360	rgb_t(0xA1,0x8F,0x1A), rgb_t(0xB2,0xA0,0x2B), rgb_t(0xC3,0xB1,0x3C), rgb_t(0xD4,0xC2,0x4D), \
	361	rgb_t(0xE5,0xD3,0x5E), rgb_t(0xF6,0xE4,0x6F), rgb_t(0xFF,0xF5,0x82), rgb_t(0xFF,0xFF,0x96 )
362	362
363	363	static const rgb_t a7800_palette[256*3] =
364	364	{
r29404	r29405
711	711
712	712
713	713	#define NTSC_GREY \
714		rgb_t(0x00,0x00,0x00), rgb_t(0x11,0x11,0x11), rgb_t(0x22,0x22,0x22), rgb_t(0x33,0x33,0x33), \
715		rgb_t(0x44,0x44,0x44), rgb_t(0x55,0x55,0x55), rgb_t(0x66,0x66,0x66), rgb_t(0x77,0x77,0x77), \
716		rgb_t(0x88,0x88,0x88), rgb_t(0x99,0x99,0x99), rgb_t(0xAA,0xAA,0xAA), rgb_t(0xBB,0xBB,0xBB), \
717		rgb_t(0xCC,0xCC,0xCC), rgb_t(0xDD,0xDD,0xDD), rgb_t(0xEE,0xEE,0xEE), rgb_t(0xFF,0xFF,0xFF )
	714	rgb_t(0x00,0x00,0x00), rgb_t(0x11,0x11,0x11), rgb_t(0x22,0x22,0x22), rgb_t(0x33,0x33,0x33), \
	715	rgb_t(0x44,0x44,0x44), rgb_t(0x55,0x55,0x55), rgb_t(0x66,0x66,0x66), rgb_t(0x77,0x77,0x77), \
	716	rgb_t(0x88,0x88,0x88), rgb_t(0x99,0x99,0x99), rgb_t(0xAA,0xAA,0xAA), rgb_t(0xBB,0xBB,0xBB), \
	717	rgb_t(0xCC,0xCC,0xCC), rgb_t(0xDD,0xDD,0xDD), rgb_t(0xEE,0xEE,0xEE), rgb_t(0xFF,0xFF,0xFF )
718	718
719	719	#define NTSC_GOLD \
720		rgb_t(0x1A,0x07,0x00), rgb_t(0x2B,0x18,0x00), rgb_t(0x3C,0x29,0x00), rgb_t(0x4D,0x3A,0x00), \
721		rgb_t(0x5E,0x4B,0x00), rgb_t(0x6F,0x5C,0x00), rgb_t(0x80,0x6D,0x00), rgb_t(0x91,0x7E,0x09), \
722		rgb_t(0xA2,0x8F,0x1A), rgb_t(0xB3,0xA0,0x2B), rgb_t(0xC4,0xB1,0x3C), rgb_t(0xD5,0xC2,0x4D), \
723		rgb_t(0xE6,0xD3,0x5E), rgb_t(0xF7,0xE4,0x6F), rgb_t(0xFF,0xF5,0x83), rgb_t(0xFF,0xF7,0x97 )
	720	rgb_t(0x1A,0x07,0x00), rgb_t(0x2B,0x18,0x00), rgb_t(0x3C,0x29,0x00), rgb_t(0x4D,0x3A,0x00), \
	721	rgb_t(0x5E,0x4B,0x00), rgb_t(0x6F,0x5C,0x00), rgb_t(0x80,0x6D,0x00), rgb_t(0x91,0x7E,0x09), \
	722	rgb_t(0xA2,0x8F,0x1A), rgb_t(0xB3,0xA0,0x2B), rgb_t(0xC4,0xB1,0x3C), rgb_t(0xD5,0xC2,0x4D), \
	723	rgb_t(0xE6,0xD3,0x5E), rgb_t(0xF7,0xE4,0x6F), rgb_t(0xFF,0xF5,0x83), rgb_t(0xFF,0xF7,0x97 )
724	724
725	725	#define NTSC_ORANGE \
726		rgb_t(0x31,0x00,0x00), rgb_t(0x42,0x06,0x00), rgb_t(0x53,0x17,0x00), rgb_t(0x64,0x28,0x00), \
727		rgb_t(0x75,0x39,0x00), rgb_t(0x86,0X4A,0x00), rgb_t(0x97,0x5B,0x0B), rgb_t(0xA8,0x6C,0x1C), \
728		rgb_t(0xB9,0x7D,0x2D), rgb_t(0xCA,0x8E,0x3E), rgb_t(0xDB,0x9F,0x4F), rgb_t(0xEC,0xB0,0x60), \
729		rgb_t(0xFD,0xC1,0x71), rgb_t(0xFF,0xD2,0x86), rgb_t(0xFF,0xE3,0x9D), rgb_t(0xFF,0xF4,0xB3 )
	726	rgb_t(0x31,0x00,0x00), rgb_t(0x42,0x06,0x00), rgb_t(0x53,0x17,0x00), rgb_t(0x64,0x28,0x00), \
	727	rgb_t(0x75,0x39,0x00), rgb_t(0x86,0X4A,0x00), rgb_t(0x97,0x5B,0x0B), rgb_t(0xA8,0x6C,0x1C), \
	728	rgb_t(0xB9,0x7D,0x2D), rgb_t(0xCA,0x8E,0x3E), rgb_t(0xDB,0x9F,0x4F), rgb_t(0xEC,0xB0,0x60), \
	729	rgb_t(0xFD,0xC1,0x71), rgb_t(0xFF,0xD2,0x86), rgb_t(0xFF,0xE3,0x9D), rgb_t(0xFF,0xF4,0xB3 )
730	730
731	731	#define NTSC_RED_ORANGE \
732		rgb_t(0x3E,0x00,0x00), rgb_t(0x4F,0x00,0x00), rgb_t(0x60,0x08,0x00), rgb_t(0x71,0x19,0x00), \
733		rgb_t(0x82,0x2A,0x0F), rgb_t(0x93,0x3B,0x20), rgb_t(0xA4,0x4C,0x31), rgb_t(0xB5,0x5D,0x42), \
734		rgb_t(0xC6,0x6E,0x53), rgb_t(0xD7,0x7F,0x64), rgb_t(0xE8,0x90,0x75), rgb_t(0xF9,0xA1,0x86), \
735		rgb_t(0xFF,0xB2,0x9A), rgb_t(0xFF,0xC3,0xB0), rgb_t(0xFF,0xD4,0xC6), rgb_t(0xFF,0xE5,0xDC )
	732	rgb_t(0x3E,0x00,0x00), rgb_t(0x4F,0x00,0x00), rgb_t(0x60,0x08,0x00), rgb_t(0x71,0x19,0x00), \
	733	rgb_t(0x82,0x2A,0x0F), rgb_t(0x93,0x3B,0x20), rgb_t(0xA4,0x4C,0x31), rgb_t(0xB5,0x5D,0x42), \
	734	rgb_t(0xC6,0x6E,0x53), rgb_t(0xD7,0x7F,0x64), rgb_t(0xE8,0x90,0x75), rgb_t(0xF9,0xA1,0x86), \
	735	rgb_t(0xFF,0xB2,0x9A), rgb_t(0xFF,0xC3,0xB0), rgb_t(0xFF,0xD4,0xC6), rgb_t(0xFF,0xE5,0xDC )
736	736
737	737	#define NTSC_PINK \
738		rgb_t(0x3E,0x00,0x06), rgb_t(0x4F,0x00,0x12), rgb_t(0x60,0x00,0x1E), rgb_t(0x71,0x0E,0x2E), \
739		rgb_t(0x82,0x1F,0x3F), rgb_t(0x93,0x30,0x50), rgb_t(0xA4,0x41,0x61), rgb_t(0xB5,0x52,0x72), \
740		rgb_t(0xC6,0x63,0x83), rgb_t(0xD7,0x74,0x94), rgb_t(0xE8,0x85,0xA5), rgb_t(0xF9,0x96,0xB6), \
741		rgb_t(0xFF,0xA7,0xCB), rgb_t(0xFF,0xB8,0xE1), rgb_t(0xFF,0xC9,0xEF), rgb_t(0xFF,0xDA,0xF4 )
	738	rgb_t(0x3E,0x00,0x06), rgb_t(0x4F,0x00,0x12), rgb_t(0x60,0x00,0x1E), rgb_t(0x71,0x0E,0x2E), \
	739	rgb_t(0x82,0x1F,0x3F), rgb_t(0x93,0x30,0x50), rgb_t(0xA4,0x41,0x61), rgb_t(0xB5,0x52,0x72), \
	740	rgb_t(0xC6,0x63,0x83), rgb_t(0xD7,0x74,0x94), rgb_t(0xE8,0x85,0xA5), rgb_t(0xF9,0x96,0xB6), \
	741	rgb_t(0xFF,0xA7,0xCB), rgb_t(0xFF,0xB8,0xE1), rgb_t(0xFF,0xC9,0xEF), rgb_t(0xFF,0xDA,0xF4 )
742	742
743	743	#define NTSC_PURPLE \
744		rgb_t(0x32,0x00,0x38), rgb_t(0x43,0x00,0x44), rgb_t(0x54,0x00,0x50), rgb_t(0x65,0x0C,0x5F), \
745		rgb_t(0x76,0x1D,0x70), rgb_t(0x87,0x2E,0x81), rgb_t(0x98,0x3F,0x92), rgb_t(0xA9,0x50,0xA3), \
746		rgb_t(0xBA,0x61,0xB4), rgb_t(0xCB,0x72,0xC5), rgb_t(0xDC,0x83,0xD6), rgb_t(0xED,0x94,0xE4), \
747		rgb_t(0xFE,0xA5,0xE4), rgb_t(0xFF,0xB6,0xE9), rgb_t(0xFF,0xC7,0xEE), rgb_t(0xFF,0xD8,0xF3 )
	744	rgb_t(0x32,0x00,0x38), rgb_t(0x43,0x00,0x44), rgb_t(0x54,0x00,0x50), rgb_t(0x65,0x0C,0x5F), \
	745	rgb_t(0x76,0x1D,0x70), rgb_t(0x87,0x2E,0x81), rgb_t(0x98,0x3F,0x92), rgb_t(0xA9,0x50,0xA3), \
	746	rgb_t(0xBA,0x61,0xB4), rgb_t(0xCB,0x72,0xC5), rgb_t(0xDC,0x83,0xD6), rgb_t(0xED,0x94,0xE4), \
	747	rgb_t(0xFE,0xA5,0xE4), rgb_t(0xFF,0xB6,0xE9), rgb_t(0xFF,0xC7,0xEE), rgb_t(0xFF,0xD8,0xF3 )
748	748
749	749	#define NTSC_PURPLE_BLUE \
750		rgb_t(0x1B,0x00,0x5F), rgb_t(0x2C,0x00,0x6B), rgb_t(0x3D,0x00,0x77), rgb_t(0x4E,0x11,0x88), \
751		rgb_t(0x5F,0x22,0x99), rgb_t(0x70,0x33,0xAA), rgb_t(0x81,0x44,0xBB), rgb_t(0x92,0x55,0xCC), \
752		rgb_t(0xA3,0x66,0xDD), rgb_t(0xB4,0x77,0xED), rgb_t(0xC5,0x88,0xED), rgb_t(0xD6,0x99,0xED), \
753		rgb_t(0xE7,0xAA,0xED), rgb_t(0xF8,0xBB,0xED), rgb_t(0xFF,0xCC,0xF0), rgb_t(0xFF,0xDD,0xF5 )
	750	rgb_t(0x1B,0x00,0x5F), rgb_t(0x2C,0x00,0x6B), rgb_t(0x3D,0x00,0x77), rgb_t(0x4E,0x11,0x88), \
	751	rgb_t(0x5F,0x22,0x99), rgb_t(0x70,0x33,0xAA), rgb_t(0x81,0x44,0xBB), rgb_t(0x92,0x55,0xCC), \
	752	rgb_t(0xA3,0x66,0xDD), rgb_t(0xB4,0x77,0xED), rgb_t(0xC5,0x88,0xED), rgb_t(0xD6,0x99,0xED), \
	753	rgb_t(0xE7,0xAA,0xED), rgb_t(0xF8,0xBB,0xED), rgb_t(0xFF,0xCC,0xF0), rgb_t(0xFF,0xDD,0xF5 )
754	754
755	755	#define NTSC_BLUE1 \
756		rgb_t(0x00,0x00,0x72), rgb_t(0x10,0x00,0x7E), rgb_t(0x21,0x0D,0x8E), rgb_t(0x32,0x1E,0x9F), \
757		rgb_t(0x43,0x2F,0xB0), rgb_t(0x54,0x40,0xC1), rgb_t(0x65,0x51,0xD2), rgb_t(0x76,0x62,0xE3), \
758		rgb_t(0x87,0x73,0xF4), rgb_t(0x98,0x84,0xF9), rgb_t(0xA9,0x95,0xF9), rgb_t(0xBA,0xA6,0xF9), \
759		rgb_t(0xCB,0xB7,0xF9), rgb_t(0xDC,0xC8,0xF9), rgb_t(0xED,0xD9,0xF9), rgb_t(0xFE,0xEA,0xF9 )
	756	rgb_t(0x00,0x00,0x72), rgb_t(0x10,0x00,0x7E), rgb_t(0x21,0x0D,0x8E), rgb_t(0x32,0x1E,0x9F), \
	757	rgb_t(0x43,0x2F,0xB0), rgb_t(0x54,0x40,0xC1), rgb_t(0x65,0x51,0xD2), rgb_t(0x76,0x62,0xE3), \
	758	rgb_t(0x87,0x73,0xF4), rgb_t(0x98,0x84,0xF9), rgb_t(0xA9,0x95,0xF9), rgb_t(0xBA,0xA6,0xF9), \
	759	rgb_t(0xCB,0xB7,0xF9), rgb_t(0xDC,0xC8,0xF9), rgb_t(0xED,0xD9,0xF9), rgb_t(0xFE,0xEA,0xF9 )
760	760
761	761	#define NTSC_BLUE2 \
762		rgb_t(0x00,0x00,0x65), rgb_t(0x00,0x0C,0x7A), rgb_t(0x05,0x1D,0x8E), rgb_t(0x16,0x2E,0x9F), \
763		rgb_t(0x27,0x3F,0xB0), rgb_t(0x38,0x50,0xC1), rgb_t(0x49,0x61,0xD2), rgb_t(0x5A,0x72,0xE3), \
764		rgb_t(0x6B,0x83,0xF4), rgb_t(0x7C,0x94,0xFF), rgb_t(0x8D,0xA5,0xFF), rgb_t(0x9E,0xB6,0xFF), \
765		rgb_t(0xAF,0xC7,0xFF), rgb_t(0xC0,0xD8,0xFF), rgb_t(0xD1,0xE9,0xFF), rgb_t(0xE2,0xFA,0xFF )
	762	rgb_t(0x00,0x00,0x65), rgb_t(0x00,0x0C,0x7A), rgb_t(0x05,0x1D,0x8E), rgb_t(0x16,0x2E,0x9F), \
	763	rgb_t(0x27,0x3F,0xB0), rgb_t(0x38,0x50,0xC1), rgb_t(0x49,0x61,0xD2), rgb_t(0x5A,0x72,0xE3), \
	764	rgb_t(0x6B,0x83,0xF4), rgb_t(0x7C,0x94,0xFF), rgb_t(0x8D,0xA5,0xFF), rgb_t(0x9E,0xB6,0xFF), \
	765	rgb_t(0xAF,0xC7,0xFF), rgb_t(0xC0,0xD8,0xFF), rgb_t(0xD1,0xE9,0xFF), rgb_t(0xE2,0xFA,0xFF )
766	766
767	767	#define NTSC_LIGHT_BLUE \
768		rgb_t(0x00,0x0D,0x48), rgb_t(0x00,0x1E,0x5E), rgb_t(0x00,0x2F,0x74), rgb_t(0x00,0x40,0x8A), \
769		rgb_t(0x11,0x51,0x9B), rgb_t(0x22,0x62,0xAC), rgb_t(0x33,0x73,0xBD), rgb_t(0x44,0x84,0xCE), \
770		rgb_t(0x55,0x95,0xDF), rgb_t(0x66,0xA6,0xF0), rgb_t(0x77,0xB7,0xFF), rgb_t(0x88,0xC8,0xFF), \
771		rgb_t(0x99,0xD9,0xFF), rgb_t(0xAA,0xEA,0xFF), rgb_t(0xBB,0xFB,0xFF), rgb_t(0xCC,0xFF,0xFF )
	768	rgb_t(0x00,0x0D,0x48), rgb_t(0x00,0x1E,0x5E), rgb_t(0x00,0x2F,0x74), rgb_t(0x00,0x40,0x8A), \
	769	rgb_t(0x11,0x51,0x9B), rgb_t(0x22,0x62,0xAC), rgb_t(0x33,0x73,0xBD), rgb_t(0x44,0x84,0xCE), \
	770	rgb_t(0x55,0x95,0xDF), rgb_t(0x66,0xA6,0xF0), rgb_t(0x77,0xB7,0xFF), rgb_t(0x88,0xC8,0xFF), \
	771	rgb_t(0x99,0xD9,0xFF), rgb_t(0xAA,0xEA,0xFF), rgb_t(0xBB,0xFB,0xFF), rgb_t(0xCC,0xFF,0xFF )
772	772
773	773	#define NTSC_TURQUOISE \
774		rgb_t(0x00,0x1C,0x1C), rgb_t(0x00,0x2D,0x32), rgb_t(0x00,0x3E,0x49), rgb_t(0x00,0x4F,0x5F), \
775		rgb_t(0x05,0x60,0x73), rgb_t(0x16,0x71,0x84), rgb_t(0x27,0x82,0x95), rgb_t(0x38,0x93,0xA6), \
776		rgb_t(0x49,0xA4,0xB7), rgb_t(0x5A,0xB5,0xC8), rgb_t(0x6B,0xC6,0xD9), rgb_t(0x7C,0xD7,0xEA), \
777		rgb_t(0x8D,0xE8,0xFB), rgb_t(0x9E,0xF9,0xFF), rgb_t(0xAF,0xFF,0xFF), rgb_t(0xC0,0xFF,0xFF )
	774	rgb_t(0x00,0x1C,0x1C), rgb_t(0x00,0x2D,0x32), rgb_t(0x00,0x3E,0x49), rgb_t(0x00,0x4F,0x5F), \
	775	rgb_t(0x05,0x60,0x73), rgb_t(0x16,0x71,0x84), rgb_t(0x27,0x82,0x95), rgb_t(0x38,0x93,0xA6), \
	776	rgb_t(0x49,0xA4,0xB7), rgb_t(0x5A,0xB5,0xC8), rgb_t(0x6B,0xC6,0xD9), rgb_t(0x7C,0xD7,0xEA), \
	777	rgb_t(0x8D,0xE8,0xFB), rgb_t(0x9E,0xF9,0xFF), rgb_t(0xAF,0xFF,0xFF), rgb_t(0xC0,0xFF,0xFF )
778	778
779	779	#define NTSC_GREEN_BLUE \
780		rgb_t(0x00,0x25,0x0B), rgb_t(0x00,0x36,0x10), rgb_t(0x00,0x47,0x18), rgb_t(0x00,0x58,0x2E), \
781		rgb_t(0x07,0x69,0x42), rgb_t(0x18,0x7A,0x53), rgb_t(0x29,0x8B,0x64), rgb_t(0x3A,0x9C,0x75), \
782		rgb_t(0x4B,0xAD,0x86), rgb_t(0x5C,0xBE,0x97), rgb_t(0x6D,0xCF,0xA8), rgb_t(0x7E,0xE0,0xB9), \
783		rgb_t(0x8F,0xF1,0xCA), rgb_t(0xA0,0xFF,0xDA), rgb_t(0xB1,0xFF,0xE6), rgb_t(0xC2,0xFF,0xF2 )
	780	rgb_t(0x00,0x25,0x0B), rgb_t(0x00,0x36,0x10), rgb_t(0x00,0x47,0x18), rgb_t(0x00,0x58,0x2E), \
	781	rgb_t(0x07,0x69,0x42), rgb_t(0x18,0x7A,0x53), rgb_t(0x29,0x8B,0x64), rgb_t(0x3A,0x9C,0x75), \
	782	rgb_t(0x4B,0xAD,0x86), rgb_t(0x5C,0xBE,0x97), rgb_t(0x6D,0xCF,0xA8), rgb_t(0x7E,0xE0,0xB9), \
	783	rgb_t(0x8F,0xF1,0xCA), rgb_t(0xA0,0xFF,0xDA), rgb_t(0xB1,0xFF,0xE6), rgb_t(0xC2,0xFF,0xF2 )
784	784
785	785	#define NTSC_GREEN \
786		rgb_t(0x00,0x27,0x0C), rgb_t(0x00,0x38,0x11), rgb_t(0x00,0x49,0x16), rgb_t(0x04,0x5A,0x1A), \
787		rgb_t(0x15,0x6B,0x1A), rgb_t(0x26,0x7C,0x22), rgb_t(0x37,0x8D,0x33), rgb_t(0x48,0x9E,0x44), \
788		rgb_t(0x59,0xAF,0x55), rgb_t(0x6A,0xC0,0x66), rgb_t(0x7B,0xD1,0x77), rgb_t(0x8C,0xE2,0x88), \
789		rgb_t(0x9D,0xF3,0x99), rgb_t(0xAE,0xFF,0xA8), rgb_t(0xBF,0xFF,0xB4), rgb_t(0xD0,0xFF,0xC0 )
	786	rgb_t(0x00,0x27,0x0C), rgb_t(0x00,0x38,0x11), rgb_t(0x00,0x49,0x16), rgb_t(0x04,0x5A,0x1A), \
	787	rgb_t(0x15,0x6B,0x1A), rgb_t(0x26,0x7C,0x22), rgb_t(0x37,0x8D,0x33), rgb_t(0x48,0x9E,0x44), \
	788	rgb_t(0x59,0xAF,0x55), rgb_t(0x6A,0xC0,0x66), rgb_t(0x7B,0xD1,0x77), rgb_t(0x8C,0xE2,0x88), \
	789	rgb_t(0x9D,0xF3,0x99), rgb_t(0xAE,0xFF,0xA8), rgb_t(0xBF,0xFF,0xB4), rgb_t(0xD0,0xFF,0xC0 )
790	790
791	791	#define NTSC_YELLOW_GREEN \
792		rgb_t(0x00,0x21,0x0A), rgb_t(0x00,0x32,0x0F), rgb_t(0x0A,0x43,0x11), rgb_t(0x1B,0x54,0x11), \
793		rgb_t(0x2C,0x65,0x11), rgb_t(0x3D,0x76,0x11), rgb_t(0x4E,0x87,0x11), rgb_t(0x5F,0x98,0x1E), \
794		rgb_t(0x70,0xA9,0x2F), rgb_t(0x81,0xBA,0x40), rgb_t(0x92,0xCB,0x51), rgb_t(0xA3,0xDC,0x62), \
795		rgb_t(0xB4,0xED,0x73), rgb_t(0xC5,0xFE,0x84), rgb_t(0xD6,0xFF,0x90), rgb_t(0xE7,0xFF,0x9C )
	792	rgb_t(0x00,0x21,0x0A), rgb_t(0x00,0x32,0x0F), rgb_t(0x0A,0x43,0x11), rgb_t(0x1B,0x54,0x11), \
	793	rgb_t(0x2C,0x65,0x11), rgb_t(0x3D,0x76,0x11), rgb_t(0x4E,0x87,0x11), rgb_t(0x5F,0x98,0x1E), \
	794	rgb_t(0x70,0xA9,0x2F), rgb_t(0x81,0xBA,0x40), rgb_t(0x92,0xCB,0x51), rgb_t(0xA3,0xDC,0x62), \
	795	rgb_t(0xB4,0xED,0x73), rgb_t(0xC5,0xFE,0x84), rgb_t(0xD6,0xFF,0x90), rgb_t(0xE7,0xFF,0x9C )
796	796
797	797	#define NTSC_ORANGE_GREEN \
798		rgb_t(0x05,0x13,0x04), rgb_t(0x16,0x24,0x04), rgb_t(0x27,0x35,0x04), rgb_t(0x38,0x46,0x04), \
799		rgb_t(0x49,0x57,0x04), rgb_t(0x5A,0x68,0x04), rgb_t(0x6B,0x79,0x04), rgb_t(0x7C,0x8A,0x09), \
800		rgb_t(0x8D,0x9B,0x1A), rgb_t(0x9E,0xAC,0x2B), rgb_t(0xAF,0xBD,0x3C), rgb_t(0xC0,0xCE,0x4D), \
801		rgb_t(0xD1,0xDF,0x5E), rgb_t(0xE2,0xF0,0x6F), rgb_t(0xF3,0xFF,0x80), rgb_t(0xFF,0xFF,0x8D )
	798	rgb_t(0x05,0x13,0x04), rgb_t(0x16,0x24,0x04), rgb_t(0x27,0x35,0x04), rgb_t(0x38,0x46,0x04), \
	799	rgb_t(0x49,0x57,0x04), rgb_t(0x5A,0x68,0x04), rgb_t(0x6B,0x79,0x04), rgb_t(0x7C,0x8A,0x09), \
	800	rgb_t(0x8D,0x9B,0x1A), rgb_t(0x9E,0xAC,0x2B), rgb_t(0xAF,0xBD,0x3C), rgb_t(0xC0,0xCE,0x4D), \
	801	rgb_t(0xD1,0xDF,0x5E), rgb_t(0xE2,0xF0,0x6F), rgb_t(0xF3,0xFF,0x80), rgb_t(0xFF,0xFF,0x8D )
802	802
803	803	#define NTSC_LIGHT_ORANGE \
804		rgb_t(0x21,0x02,0x00), rgb_t(0x32,0x13,0x00), rgb_t(0x43,0x24,0x00), rgb_t(0x54,0x35,0x00), \
805		rgb_t(0x65,0x46,0x00), rgb_t(0x76,0x57,0x00), rgb_t(0x87,0x68,0x00), rgb_t(0x98,0x79,0x0C), \
806		rgb_t(0xA9,0x8A,0x1D), rgb_t(0xBA,0x9B,0x2E), rgb_t(0xCB,0xAC,0x3F), rgb_t(0xDC,0xBD,0x50), \
807		rgb_t(0xED,0xCE,0x61), rgb_t(0xFE,0xDF,0x72), rgb_t(0xFF,0xF0,0x87), rgb_t(0xFF,0xFF,0x9D )
	804	rgb_t(0x21,0x02,0x00), rgb_t(0x32,0x13,0x00), rgb_t(0x43,0x24,0x00), rgb_t(0x54,0x35,0x00), \
	805	rgb_t(0x65,0x46,0x00), rgb_t(0x76,0x57,0x00), rgb_t(0x87,0x68,0x00), rgb_t(0x98,0x79,0x0C), \
	806	rgb_t(0xA9,0x8A,0x1D), rgb_t(0xBA,0x9B,0x2E), rgb_t(0xCB,0xAC,0x3F), rgb_t(0xDC,0xBD,0x50), \
	807	rgb_t(0xED,0xCE,0x61), rgb_t(0xFE,0xDF,0x72), rgb_t(0xFF,0xF0,0x87), rgb_t(0xFF,0xFF,0x9D )
808	808	***************************************************************************/
809	809
810	810

trunk/src/mess/drivers/mac.c
r29404	r29405
946	946
947	947	MCFG_DEVICE_ADD("scc", SCC8530, C7M)
948	948	MCFG_Z8530_INTRQ_CALLBACK(WRITELINE(mac_state, set_scc_interrupt))
949
	949
950	950	MCFG_DEVICE_ADD("via6522_0", VIA6522, 1000000)
951	951	MCFG_VIA6522_READPA_HANDLER(READ8(mac_state,mac_via_in_a))
952	952	MCFG_VIA6522_READPB_HANDLER(READ8(mac_state,mac_via_in_b))
r29404	r29405
955	955	MCFG_VIA6522_CB2_HANDLER(WRITELINE(mac_state,mac_via_out_cb2))
956	956	MCFG_VIA6522_IRQ_HANDLER(WRITELINE(mac_state,mac_via_irq))
957	957
958		MCFG_MACKBD_ADD(MACKBD_TAG)
	958	MCFG_MACKBD_ADD(MACKBD_TAG)
959	959	#ifdef MAC_USE_EMULATED_KBD
960	960	MCFG_MACKBD_DATAOUT_HANDLER(DEVWRITELINE("via6522_0", via6522_device, write_cb2))
961	961	MCFG_MACKBD_CLKOUT_HANDLER(WRITELINE(mac_state, mac_kbd_clk_in))
r29404	r29405
1565	1565	MCFG_SCREEN_SIZE(700, 480)
1566	1566	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 399)
1567	1567	MCFG_SCREEN_UPDATE_DRIVER(mac_state, screen_update_macpb160)
1568		MCFG_SCREEN_PALETTE("palette")
	1568	MCFG_SCREEN_PALETTE("palette")
1569	1569
1570	1570	MCFG_PALETTE_ADD("palette", 16)
1571	1571	MCFG_PALETTE_INIT_OWNER(mac_state,macgsc)
r29404	r29405
1697	1697	MCFG_SCREEN_RAW_PARAMS(25175000, 800, 0, 640, 525, 0, 480)
1698	1698	MCFG_SCREEN_SIZE(640, 870)
1699	1699	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
1700		MCFG_SCREEN_UPDATE_DRIVER(mac_state, screen_update_macrbv)
	1700	MCFG_SCREEN_UPDATE_DRIVER(mac_state, screen_update_macrbv)
1701	1701	MCFG_DEFAULT_LAYOUT(layout_mac)
1702	1702
1703	1703	/* internal ram */
r29404	r29405
1825	1825	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(1260))
1826	1826	MCFG_SCREEN_SIZE(1152, 870)
1827	1827	MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 870-1)
1828		MCFG_SCREEN_UPDATE_DRIVER(mac_state, screen_update_macdafb)
	1828	MCFG_SCREEN_UPDATE_DRIVER(mac_state, screen_update_macdafb)
1829	1829
1830	1830	MCFG_VIDEO_START_OVERRIDE(mac_state,macdafb)
1831	1831	MCFG_VIDEO_RESET_OVERRIDE(mac_state,macdafb)

trunk/src/mess/drivers/multi16.c
r29404	r29405
18	18	m_maincpu(*this, "maincpu"),
19	19	m_pic(*this, "pic8259"),
20	20	m_crtc(*this, "crtc"),
21		m_palette(*this, "palette")
	21	m_palette(*this, "palette")
22	22	,
23	23	m_p_vram(*this, "p_vram"){ }
24	24
r29404	r29405
171	171	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
172	172	MCFG_SCREEN_UPDATE_DRIVER(multi16_state, screen_update_multi16)
173	173	MCFG_SCREEN_PALETTE("palette")
174
	174
175	175	MCFG_PALETTE_ADD("palette", 8)
176	176
177	177	/* Devices */

trunk/src/mess/drivers/kaypro.c
r29404	r29405
210	210	MCFG_VIDEO_START_OVERRIDE(kaypro_state, kaypro )
211	211	MCFG_SCREEN_UPDATE_DRIVER(kaypro_state, screen_update_kayproii)
212	212	MCFG_SCREEN_PALETTE("palette")
213
	213
214	214	MCFG_GFXDECODE_ADD("gfxdecode", "palette", kayproii)
215	215	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
216	216
r29404	r29405
266	266	MCFG_SCREEN_SIZE(808, 2516)
267	267	MCFG_SCREEN_VISIBLE_AREA(0,808-1,0,2516-1)
268	268	MCFG_VIDEO_START_OVERRIDE(kaypro_state, kaypro )
269		MCFG_SCREEN_UPDATE_DRIVER(kaypro_state, screen_update_kaypro2x)
270
	269	MCFG_SCREEN_UPDATE_DRIVER(kaypro_state, screen_update_kaypro2x)
	270
271	271	MCFG_GFXDECODE_ADD("gfxdecode", "palette", kaypro2x)
272	272	MCFG_PALETTE_ADD("palette", 3)
273	273	MCFG_PALETTE_INIT_OWNER(kaypro_state,kaypro)

trunk/src/mess/drivers/ip20.c
r29404	r29405
601	601	MCFG_SPEAKER_STANDARD_MONO("mono")
602	602
603	603	MCFG_DEVICE_ADD("scc", SCC8530, 7000000)
604
	604
605	605	MCFG_DEVICE_ADD("sgi_mc", SGI_MC, 0)
606	606
607	607	MCFG_SCSIBUS_ADD("scsi")

trunk/src/mess/drivers/pc8001.c
r29404	r29405
547	547	MCFG_I8255A_ADD(I8255A_TAG, ppi_intf)
548	548	MCFG_I8257_ADD(I8257_TAG, 4000000, dmac_intf)
549	549	MCFG_UPD1990A_ADD(UPD1990A_TAG, XTAL_32_768kHz, NULL, NULL)
550
	550
551	551	MCFG_DEVICE_ADD(UPD3301_TAG, UPD3301, 14318180)
552	552	MCFG_UPD3301_CHARACTER_WIDTH(8)
553	553	MCFG_UPD3301_DRAW_CHARACTER_CALLBACK_OWNER(pc8001_state, pc8001_display_pixels)

trunk/src/mess/drivers/pc8801.c
r29404	r29405
310	310	m_beeper(*this, "beeper"),
311	311	m_opna(*this, "opna"),
312	312	m_opn(*this, "opn"),
313		m_palette(*this, "palette")
	313	m_palette(*this, "palette")
314	314	{ }
315	315
316	316	required_device<cpu_device> m_maincpu;
r29404	r29405
322	322	required_device<ym2608_device> m_opna;
323	323	required_device<ym2203_device> m_opn;
324	324	required_device<palette_device> m_palette;
325
	325
326	326	UINT8 *m_work_ram;
327	327	UINT8 *m_hi_work_ram;
328	328	UINT8 *m_ext_work_ram;
r29404	r29405
2644	2644	MCFG_I8255_ADD( "d8255_slave", slave_fdd_intf )
2645	2645
2646	2646	MCFG_UPD765A_ADD("upd765", true, true)
2647		MCFG_UPD765_INTRQ_CALLBACK(INPUTLINE("fdccpu", INPUT_LINE_IRQ0))
	2647	MCFG_UPD765_INTRQ_CALLBACK(INPUTLINE("fdccpu", INPUT_LINE_IRQ0))
2648	2648
2649	2649	#ifdef USE_PROPER_I8214
2650	2650	MCFG_I8214_ADD(I8214_TAG, MASTER_CLOCK, pic_intf)

trunk/src/mess/drivers/pocketc.c
r29404	r29405
769	769	MCFG_SC61860_READ_B_HANDLER(READ8(pc1251_state,pc1251_inb))
770	770	MCFG_SC61860_WRITE_B_HANDLER(WRITE8(pc1251_state,pc1251_outb))
771	771	MCFG_SC61860_WRITE_C_HANDLER(WRITE8(pc1251_state,pc1251_outc))
772
	772
773	773	/* video hardware */
774	774	MCFG_SCREEN_MODIFY("screen")
775	775	MCFG_SCREEN_SIZE(608, 300)

trunk/src/mess/drivers/argo.c
r29404	r29405
359	359	MCFG_SCREEN_SIZE(640, 250)
360	360	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 249)
361	361	MCFG_SCREEN_PALETTE("palette")
362
	362
363	363	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
364	364	MACHINE_CONFIG_END
365	365

trunk/src/mess/drivers/bmjr.c
r29404	r29405
360	360	MCFG_SCREEN_VISIBLE_AREA(0, 256-1, 0, 192-1)
361	361	MCFG_SCREEN_UPDATE_DRIVER(bmjr_state, screen_update_bmjr)
362	362	MCFG_SCREEN_PALETTE("palette")
363
	363
364	364	MCFG_PALETTE_ADD("palette", 8)
365	365	MCFG_PALETTE_INIT_OWNER(bmjr_state, bmjr)
366	366	MCFG_GFXDECODE_ADD("gfxdecode", "palette", bmjr)

trunk/src/mess/drivers/asst128.c
r29404	r29405
104	104	DEVICE_INPUT_DEFAULTS_END
105	105
106	106	static MACHINE_CONFIG_START( asst128, asst128_state )
107		MCFG_CPU_ADD("maincpu", I8086, 4772720)
	107	MCFG_CPU_ADD("maincpu", I8086, 4772720)
108	108	MCFG_CPU_PROGRAM_MAP(asst128_map)
109	109	MCFG_CPU_IO_MAP(asst128_io)
110	110
r29404	r29405
148	148	ROM_END
149	149
150	150	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */
151		COMP( 198?, asst128, ibm5150, 0, asst128, 0, driver_device, 0, "Schetmash", "Assistent 128", GAME_NOT_WORKING)
		No newline at end of file
	151	COMP( 198?, asst128, ibm5150, 0, asst128, 0, driver_device, 0, "Schetmash", "Assistent 128", GAME_NOT_WORKING)

trunk/src/mess/drivers/dm7000.c
r29404	r29405
256	256	dcr[DCRSTB045_DISP_MODE] = 0x00880000;
257	257	dcr[DCRSTB045_FRAME_BUFR_BASE] = 0x0f000000;
258	258	m_scc0_lsr = UART_LSR_THRE \| UART_LSR_TEMT;
259
	259
260	260	ppc4xx_set_dcr_read_handler(m_maincpu, read32_delegate(FUNC(dm7000_state::dcr_r),this));
261	261	ppc4xx_set_dcr_write_handler(m_maincpu, write32_delegate(FUNC(dm7000_state::dcr_w),this));
262	262	}

trunk/src/mess/drivers/msx.c
r29404	r29405
1029	1029
1030	1030	static const ay8910_interface msx_ay8910_interface =
1031	1031	{
1032		AY8910_SINGLE_OUTPUT,
	1032	AY8910_SINGLE_OUTPUT,
1033	1033	AY8910_DEFAULT_LOADS,
1034	1034	DEVCB_DRIVER_MEMBER(msx_state, msx_psg_port_a_r),
1035	1035	DEVCB_DRIVER_MEMBER(msx_state, msx_psg_port_b_r),
r29404	r29405
1191	1191	MCFG_SCREEN_UPDATE_DEVICE("v9938", v9938_device, screen_update)
1192	1192	MCFG_SCREEN_SIZE(MSX2_TOTAL_XRES_PIXELS, 262*2)
1193	1193	MCFG_SCREEN_VISIBLE_AREA(MSX2_XBORDER_PIXELS - MSX2_VISIBLE_XBORDER_PIXELS, MSX2_TOTAL_XRES_PIXELS - MSX2_XBORDER_PIXELS + MSX2_VISIBLE_XBORDER_PIXELS - 1, MSX2_YBORDER_PIXELS - MSX2_VISIBLE_YBORDER_PIXELS, MSX2_TOTAL_YRES_PIXELS - MSX2_YBORDER_PIXELS + MSX2_VISIBLE_YBORDER_PIXELS - 1)
1194		MCFG_SCREEN_PALETTE("v9938:palette")
	1194	MCFG_SCREEN_PALETTE("v9938:palette")
1195	1195
1196	1196	/* sound hardware */
1197	1197	MCFG_SPEAKER_STANDARD_MONO("mono")

trunk/src/mess/drivers/beehive.c
r29404	r29405
300	300	MCFG_SCREEN_SIZE(640, 250)
301	301	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 249)
302	302	MCFG_SCREEN_PALETTE("palette")
303
	303
304	304	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
305	305	MACHINE_CONFIG_END
306	306

trunk/src/mess/drivers/tavernie.c
r29404	r29405
106	106	optional_device<beep_device> m_beep;
107	107	required_device<cpu_device> m_maincpu;
108	108	required_device<acia6850_device> m_acia;
109		public:
	109	public:
110	110	optional_device<palette_device> m_palette;
111	111	};
112	112

trunk/src/mess/drivers/z1013.c
r29404	r29405
409	409	MCFG_SCREEN_VISIBLE_AREA(0, 328-1, 0, 328-1)
410	410	MCFG_SCREEN_UPDATE_DRIVER(z1013_state, screen_update_z1013)
411	411	MCFG_SCREEN_PALETTE("palette")
412
	412
413	413	MCFG_GFXDECODE_ADD("gfxdecode", "palette", z1013)
414	414	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
415	415

trunk/src/mess/drivers/sbrain.c
r29404	r29405
61	61	m_vs(*this, "VS"),
62	62	m_bankr0(*this, "bankr0"),
63	63	m_bankw0(*this, "bankw0"),
64		m_bank2(*this, "bank2") {}
	64	m_bank2(*this, "bank2") {}
65	65
66	66	public:
67	67	const UINT8 *m_p_chargen;
r29404	r29405
340	340	MCFG_SCREEN_SIZE(640, 240)
341	341	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 239)
342	342	MCFG_SCREEN_PALETTE("palette")
343
	343
344	344	MCFG_PALETTE_ADD_MONOCHROME_AMBER("palette")
345	345
346	346	/* sound hardware */

trunk/src/mess/drivers/trs80.c
r29404	r29405
641	641	MCFG_MACHINE_RESET_OVERRIDE(trs80_state, trs80m4 )
642	642
643	643	MCFG_GFXDECODE_MODIFY("gfxdecode",trs80m4)
644
	644
645	645	MCFG_SCREEN_MODIFY("screen")
646	646	MCFG_SCREEN_UPDATE_DRIVER(trs80_state, screen_update_trs80m4)
647	647	MCFG_SCREEN_SIZE(80*8, 240)
r29404	r29405
676	676	MCFG_MACHINE_RESET_OVERRIDE(trs80_state, lnw80 )
677	677
678	678	MCFG_GFXDECODE_MODIFY("gfxdecode",lnw80)
679
	679
680	680	MCFG_PALETTE_MODIFY("palette")
681	681	MCFG_PALETTE_ENTRIES(8)
682	682	MCFG_PALETTE_INIT_OWNER(trs80_state,lnw80)

trunk/src/mess/drivers/fanucspmg.c
r29404	r29405
400	400	\| /-->\| Graphic memory\|------\| \|
401	401	\| \| \|---------------\| \| \| \|----------------\|
402	402	\| \| \| \|--------\| \|<--->\|RS232C interface\|---CN2
403		\| \| \| \| BOOT \|<-------->\| \|----------------\|
	403	\| \| \| \| BOOT \|<-------->\| \|----------------\|
404	404	\| \| \| \| EPROM \| \|
405	405	\| \| \|----------------\| \| \|--------\| \| \|----------------\|
406	406	\|<-----\|-->\|Character memory\|--\| \| \|<--->\|RS232C interface\|---CN3
407	407	\| \|-->\|----------------\| \| \| \|--------\| \| \|----------------\|
408	408	\| \| \| \| \|Main RAM\|<-------->\|
409	409	\| \| \| \| \|--------\| \| \|----------------\|
410		\| \| \| \| \|<--->\|RS232C interface\|---CN4
	410	\| \| \| \| \|<--->\|RS232C interface\|---CN4
411	411	\| \| \| \| \| \|----------------\|
412	412	\|---------\| \| \| \/ \/ \|
413	413	\|Keyboard \| \/ \---\|---------------------------\| \| \|-----------------\| CN9 \|--------\|
r29404	r29405
421	421	\|---\|----\| \|----\|----\|
422	422	\|Keyboard\| \| Screen \|
423	423	\|--------\| \|---------\|
424
425
	424
	425
426	426	TODO:
427	427	- Is the VRAM hookup anything like correct?
428	428	- Hookup enough keyboard to get it to boot a floppy, the FAPT DOCTOR
r29404	r29405
430	430	- Shared RAM is 8k, but there are 2 6264s on the sub board. Is shared RAM
431	431	banked?
432	432	- I/O is at F00xx:
433		':maincpu' (FC15A): unmapped program memory write to F0012 = 00CE & 00FF
434		':maincpu' (FC15D): unmapped program memory write to F0016 = 00CE & 00FF
435		':maincpu' (FC160): unmapped program memory write to F001A = 00CE & 00FF
436		':maincpu' (FC163): unmapped program memory write to F001E = 00CE & 00FF
437		':maincpu' (FC16D): unmapped program memory write to F000E = 0034 & 00FF
438		':maincpu' (FC172): unmapped program memory write to F0008 = 00D4 & 00FF
439		':maincpu' (FC177): unmapped program memory write to F0008 = 0030 & 00FF
440		':maincpu' (FC17C): unmapped program memory write to F000E = 0056 & 00FF
441		':maincpu' (FC181): unmapped program memory write to F000A = 0010 & 00FF
442		':maincpu' (FC186): unmapped program memory write to F000E = 0096 & 00FF
443		':maincpu' (FC18B): unmapped program memory write to F000C = 0010 & 00FF
444		':maincpu' (FC190): unmapped program memory write to F004E = 0034 & 00FF
445		':maincpu' (FC195): unmapped program memory write to F0048 = 0020 & 00FF
446		':maincpu' (FC19A): unmapped program memory write to F0048 = 004E & 00FF
447		':maincpu' (FC19F): unmapped program memory write to F004E = 0056 & 00FF
448		':maincpu' (FC1A4): unmapped program memory write to F004A = 0010 & 00FF
449		':maincpu' (FC1A9): unmapped program memory write to F004E = 0096 & 00FF
450		':maincpu' (FC1AE): unmapped program memory write to F004C = 0010 & 00FF
451
	433	':maincpu' (FC15A): unmapped program memory write to F0012 = 00CE & 00FF
	434	':maincpu' (FC15D): unmapped program memory write to F0016 = 00CE & 00FF
	435	':maincpu' (FC160): unmapped program memory write to F001A = 00CE & 00FF
	436	':maincpu' (FC163): unmapped program memory write to F001E = 00CE & 00FF
	437	':maincpu' (FC16D): unmapped program memory write to F000E = 0034 & 00FF
	438	':maincpu' (FC172): unmapped program memory write to F0008 = 00D4 & 00FF
	439	':maincpu' (FC177): unmapped program memory write to F0008 = 0030 & 00FF
	440	':maincpu' (FC17C): unmapped program memory write to F000E = 0056 & 00FF
	441	':maincpu' (FC181): unmapped program memory write to F000A = 0010 & 00FF
	442	':maincpu' (FC186): unmapped program memory write to F000E = 0096 & 00FF
	443	':maincpu' (FC18B): unmapped program memory write to F000C = 0010 & 00FF
	444	':maincpu' (FC190): unmapped program memory write to F004E = 0034 & 00FF
	445	':maincpu' (FC195): unmapped program memory write to F0048 = 0020 & 00FF
	446	':maincpu' (FC19A): unmapped program memory write to F0048 = 004E & 00FF
	447	':maincpu' (FC19F): unmapped program memory write to F004E = 0056 & 00FF
	448	':maincpu' (FC1A4): unmapped program memory write to F004A = 0010 & 00FF
	449	':maincpu' (FC1A9): unmapped program memory write to F004E = 0096 & 00FF
	450	':maincpu' (FC1AE): unmapped program memory write to F004C = 0010 & 00FF
	451
452	452	****************************************************************************/
453	453
454	454	#include "emu.h"
r29404	r29405
464	464	#include "video/mc6845.h"
465	465	#include "formats/imd_dsk.h"
466	466
467		#define MAINCPU_TAG "maincpu"
468		#define SUBCPU_TAG "subcpu"
469		#define USART0_TAG "usart0"
470		#define USART1_TAG "usart1"
471		#define USART2_TAG "usart2"
472		#define USART3_TAG "usart3"
473		#define PIT0_TAG "pit0"
474		#define PIT1_TAG "pit1"
475		#define PIC0_TAG "pic0"
476		#define PIC1_TAG "pic1"
477		#define DMAC_TAG "dmac"
478		#define CRTC_TAG "crtc"
479		#define FDC_TAG "fdc"
480		#define SCREEN_TAG "screen"
481		#define SHARED_TAG "shared"
482		#define CHARGEN_TAG "chargen"
	467	#define MAINCPU_TAG "maincpu"
	468	#define SUBCPU_TAG "subcpu"
	469	#define USART0_TAG "usart0"
	470	#define USART1_TAG "usart1"
	471	#define USART2_TAG "usart2"
	472	#define USART3_TAG "usart3"
	473	#define PIT0_TAG "pit0"
	474	#define PIT1_TAG "pit1"
	475	#define PIC0_TAG "pic0"
	476	#define PIC1_TAG "pic1"
	477	#define DMAC_TAG "dmac"
	478	#define CRTC_TAG "crtc"
	479	#define FDC_TAG "fdc"
	480	#define SCREEN_TAG "screen"
	481	#define SHARED_TAG "shared"
	482	#define CHARGEN_TAG "chargen"
483	483
484	484	class fanucspmg_state : public driver_device
485	485	{
r29404	r29405
577	577
578	578	READ8_MEMBER(fanucspmg_state::test_r)
579	579	{
580		return 0x00; // 0x80 to start weird not-sure-what process which may be FDC related
	580	return 0x00; // 0x80 to start weird not-sure-what process which may be FDC related
581	581	}
582	582
583	583	READ8_MEMBER(fanucspmg_state::vbl_r)
r29404	r29405
586	586	}
587	587
588	588	static ADDRESS_MAP_START(maincpu_mem, AS_PROGRAM, 16, fanucspmg_state)
589		AM_RANGE(0x00000, 0x7ffff) AM_RAM // main RAM
	589	AM_RANGE(0x00000, 0x7ffff) AM_RAM // main RAM
590	590
591	591	AM_RANGE(0x88000, 0x88001) AM_READ8(vbl_r, 0xffff)
592	592
593	593	AM_RANGE(0xf0004, 0xf0005) AM_READ8(test_r, 0xffff)
594	594
595	595	AM_RANGE(0xf8000, 0xf9fff) AM_READWRITE8(shared_r, shared_w, 0xffff)
596		AM_RANGE(0xfc000, 0xfffff) AM_ROM AM_REGION(MAINCPU_TAG, 0)
	596	AM_RANGE(0xfc000, 0xfffff) AM_ROM AM_REGION(MAINCPU_TAG, 0)
597	597	ADDRESS_MAP_END
598	598
599	599	static ADDRESS_MAP_START(maincpu_io, AS_IO, 16, fanucspmg_state)
r29404	r29405
603	603	{
604	604	if ((m_vbl_ctrl & 0x08) == 0x08)
605	605	{
606		if (state == ASSERT_LINE)
	606	if (state == ASSERT_LINE)
607	607	{
608	608	m_subcpu->set_input_line(I8085_RST75_LINE, ASSERT_LINE);
609	609	}
r29404	r29405
672	672	AM_RANGE(0x0000, 0x3fff) AM_ROM AM_REGION(SUBCPU_TAG, 0)
673	673
674	674	AM_RANGE(0x4000, 0x45ff) AM_READWRITE(vram1_r, vram1_w)
675		AM_RANGE(0x4800, 0x4dff) AM_READWRITE(vram2_r, vram2_w)
	675	AM_RANGE(0x4800, 0x4dff) AM_READWRITE(vram2_r, vram2_w)
676	676
677	677	AM_RANGE(0x5000, 0x5000) AM_DEVREADWRITE(CRTC_TAG, mc6845_device, status_r, address_w)
678	678	AM_RANGE(0x5001, 0x5001) AM_DEVREADWRITE(CRTC_TAG, mc6845_device, register_r, register_w)
679	679	AM_RANGE(0x5008, 0x5008) AM_WRITE(keyboard_row_w)
680	680	AM_RANGE(0x5009, 0x5009) AM_READ(keyboard_r)
681		AM_RANGE(0x500a, 0x500b) AM_WRITENOP // probably keyboard related, not sure how though
	681	AM_RANGE(0x500a, 0x500b) AM_WRITENOP // probably keyboard related, not sure how though
682	682	AM_RANGE(0x500c, 0x500c) AM_WRITE(vbl_ctrl_w)
683	683	AM_RANGE(0x500d, 0x500d) AM_WRITE(vram_bank_w)
684	684	AM_RANGE(0x500e, 0x500e) AM_READ(vblank_ack_r)
685		AM_RANGE(0x5018, 0x5018) AM_WRITE(video_ctrl_w)
	685	AM_RANGE(0x5018, 0x5018) AM_WRITE(video_ctrl_w)
686	686
687		AM_RANGE(0xe000, 0xffff) AM_RAM AM_SHARE(SHARED_TAG) // shared RAM
	687	AM_RANGE(0xe000, 0xffff) AM_RAM AM_SHARE(SHARED_TAG) // shared RAM
688	688	ADDRESS_MAP_END
689	689
690	690	/* Input ports */
r29404	r29405
752	752	*p++ = ( data & 0x01 ) ? fg : bg;
753	753	*p++ = ( data & 0x02 ) ? fg : bg;
754	754	*p++ = ( data & 0x04 ) ? fg : bg;
755		*p++ = ( data & 0x08 ) ? fg : bg;
756		*p++ = ( data & 0x10 ) ? fg : bg;
	755	*p++ = ( data & 0x08 ) ? fg : bg;
	756	*p++ = ( data & 0x10 ) ? fg : bg;
757	757	*p++ = ( data & 0x20 ) ? fg : bg;
758	758	*p++ = ( data & 0x40 ) ? fg : bg;
759	759	*p++ = ( data & 0x80 ) ? fg : bg;
r29404	r29405
784	784	DEVCB_NULL, /* on_de_changed */
785	785	DEVCB_NULL, /* on_cur_changed */
786	786	DEVCB_NULL, /* on hsync changed */
787		DEVCB_DRIVER_LINE_MEMBER(fanucspmg_state, vsync_w), /* on vsync changed */
	787	DEVCB_DRIVER_LINE_MEMBER(fanucspmg_state, vsync_w), /* on vsync changed */
788	788	NULL
789	789	};
790	790
r29404	r29405
838	838	/* ROM definition */
839	839	ROM_START( fanucspg )
840	840	ROM_REGION(0x4000, MAINCPU_TAG, 0)
841		ROM_LOAD16_BYTE( "a40_001a.13a", 0x000000, 0x002000, CRC(1b8ac8ef) SHA1(309c081d25270e082ebf846b4f73cef76b52d991) )
842		ROM_LOAD16_BYTE( "a40_002a.15a", 0x000001, 0x002000, CRC(587ae652) SHA1(ebc5a4c3d64ab9d6dd4d5355f85bc894e7294e17) )
	841	ROM_LOAD16_BYTE( "a40_001a.13a", 0x000000, 0x002000, CRC(1b8ac8ef) SHA1(309c081d25270e082ebf846b4f73cef76b52d991) )
	842	ROM_LOAD16_BYTE( "a40_002a.15a", 0x000001, 0x002000, CRC(587ae652) SHA1(ebc5a4c3d64ab9d6dd4d5355f85bc894e7294e17) )
843	843
844	844	ROM_REGION(0x4000, SUBCPU_TAG, 0)
845		ROM_LOAD( "a41_010b.28b", 0x000000, 0x004000, CRC(35a9714f) SHA1(5697b6c4db5adb5702dc1290ecc98758d5fab221) )
	845	ROM_LOAD( "a41_010b.28b", 0x000000, 0x004000, CRC(35a9714f) SHA1(5697b6c4db5adb5702dc1290ecc98758d5fab221) )
846	846
847	847	ROM_REGION(0x8000, CHARGEN_TAG, 0)
848		ROM_LOAD( "a42_020a.30b", 0x000000, 0x008000, CRC(33eb5962) SHA1(1157a72089ff77e8db9a9a8fcd0f6c32a1374f56) )
	848	ROM_LOAD( "a42_020a.30b", 0x000000, 0x008000, CRC(33eb5962) SHA1(1157a72089ff77e8db9a9a8fcd0f6c32a1374f56) )
849	849	ROM_END
850	850
851	851	/* Driver */
852	852	/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
853	853	COMP( 1983, fanucspg, 0, 0, fanucspmg, fanucspmg, fanucspmg_state, fanucspmg, "Fanuc", "System P Model G", GAME_NOT_WORKING \| GAME_NO_SOUND)
854
855

trunk/src/mess/drivers/thomson.c
r29404	r29405
566	566
567	567	WRITE_LINE_MEMBER( thomson_state::fdc_index_0_w )
568	568	{
569		thomson_index_callback(machine().device<legacy_floppy_image_device>(FLOPPY_0), state);
	569	thomson_index_callback(machine().device<legacy_floppy_image_device>(FLOPPY_0), state);
570	570	}
571	571
572	572	WRITE_LINE_MEMBER( thomson_state::fdc_index_1_w )
573	573	{
574		thomson_index_callback(machine().device<legacy_floppy_image_device>(FLOPPY_1), state);
	574	thomson_index_callback(machine().device<legacy_floppy_image_device>(FLOPPY_1), state);
575	575	}
576	576
577	577	WRITE_LINE_MEMBER( thomson_state::fdc_index_2_w )
578	578	{
579		thomson_index_callback(machine().device<legacy_floppy_image_device>(FLOPPY_2), state);
	579	thomson_index_callback(machine().device<legacy_floppy_image_device>(FLOPPY_2), state);
580	580	}
581	581
582	582	WRITE_LINE_MEMBER( thomson_state::fdc_index_3_w )
583	583	{
584		thomson_index_callback(machine().device<legacy_floppy_image_device>(FLOPPY_3), state);
	584	thomson_index_callback(machine().device<legacy_floppy_image_device>(FLOPPY_3), state);
585	585	}
586	586
587	587	static const floppy_interface thomson_floppy_interface_0 =
r29404	r29405
956	956
957	957	MCFG_DEVICE_MODIFY("mc6846")
958	958	MCFG_MC6846_OUT_PORT_CB(WRITE8(thomson_state, to770_timer_port_out))
959
	959
960	960	MCFG_CARTSLOT_MODIFY("cart")
961	961	MCFG_CARTSLOT_INTERFACE("to770_cart")
962	962	MCFG_DEVICE_REMOVE("cart_list")
r29404	r29405
1878	1878	MCFG_MC6846_OUT_PORT_CB(WRITE8(thomson_state, to9p_timer_port_out))
1879	1879	MCFG_MC6846_OUT_CP2_CB(WRITE8(thomson_state, to8_timer_cp2_out))
1880	1880	MCFG_MC6846_IN_PORT_CB(READ8(thomson_state, to9p_timer_port_in))
1881
	1881
1882	1882	/* internal ram */
1883	1883	MCFG_RAM_MODIFY(RAM_TAG)
1884	1884	MCFG_RAM_DEFAULT_SIZE("512K")
r29404	r29405
1965	1965	AM_RANGE ( 0xa7f2, 0xa7f3 ) AM_READWRITE(to7_midi_r, to7_midi_w )
1966	1966	AM_RANGE ( 0xa7fe, 0xa7ff ) AM_DEVREADWRITE("mea8000", mea8000_device, read, write)
1967	1967	AM_RANGE ( 0xb000, 0xbfff ) AM_ROMBANK ( MO6_CART_LO )
1968		AM_WRITE ( mo6_cartridge_w )
	1968	AM_WRITE ( mo6_cartridge_w )
1969	1969	AM_RANGE ( 0xc000, 0xefff ) AM_ROMBANK ( MO6_CART_HI )
1970		AM_WRITE ( mo6_cartridge_w )
	1970	AM_WRITE ( mo6_cartridge_w )
1971	1971	AM_RANGE ( 0xf000, 0xffff ) AM_ROMBANK ( TO8_BIOS_BANK )
1972	1972
1973	1973	/* 0x10000 - 0x1ffff: 64 KB external ROM cartridge */
r29404	r29405
2295	2295	AM_RANGE ( 0xa7f8, 0xa7fb ) AM_DEVREADWRITE( "pia_3", pia6821_device, read_alt, write_alt)
2296	2296	AM_RANGE ( 0xa7fe, 0xa7ff ) AM_DEVREADWRITE("mea8000", mea8000_device, read, write)
2297	2297	AM_RANGE ( 0xb000, 0xbfff ) AM_ROMBANK ( MO6_CART_LO )
2298		AM_WRITE ( mo6_cartridge_w )
	2298	AM_WRITE ( mo6_cartridge_w )
2299	2299	AM_RANGE ( 0xc000, 0xefff ) AM_ROMBANK ( MO6_CART_HI )
2300		AM_WRITE ( mo6_cartridge_w )
	2300	AM_WRITE ( mo6_cartridge_w )
2301	2301	AM_RANGE ( 0xf000, 0xffff ) AM_ROMBANK ( TO8_BIOS_BANK )
2302	2302
2303	2303	/* 0x10000 - 0x1ffff: 64 KB external ROM cartridge */

trunk/src/mess/drivers/lcmate2.c
r29404	r29405
235	235	MCFG_SCREEN_SIZE(120, 18)
236	236	MCFG_SCREEN_VISIBLE_AREA(0, 120-1, 0, 18-1)
237	237	MCFG_SCREEN_PALETTE("palette")
238
	238
239	239	MCFG_PALETTE_ADD("palette", 2)
240	240	MCFG_PALETTE_INIT_OWNER(lcmate2_state, lcmate2)
241	241	MCFG_DEFAULT_LAYOUT(layout_lcd)

trunk/src/mess/drivers/mbee.c
r29404	r29405
793	793	MCFG_SCREEN_UPDATE_DRIVER(mbee_state, screen_update_mbee)
794	794
795	795	MCFG_GFXDECODE_ADD("gfxdecode", "palette", mbeeic)
796
	796
797	797	MCFG_PALETTE_ADD("palette", 96)
798	798	MCFG_PALETTE_INIT_OWNER(mbee_state,mbeeic)
799	799

trunk/src/mess/drivers/ymmu100.c
r29404	r29405
79	79	16 7 mode
80	80	15 7 eq
81	81	14 7 exit
82		10 7 value -
	82	10 7 value -
83	83	11 7 value +
84	84	2 led play
85	85	3 led edit
r29404	r29405
452	452
453	453	static MACHINE_CONFIG_DERIVED_CLASS( mu100r, mu100, mu100r_state )
454	454	MACHINE_CONFIG_END
455
	455
456	456	#define ROM_LOAD16_WORD_SWAP_BIOS(bios,name,offset,length,hash) \
457	457	ROMX_LOAD(name, offset, length, hash, ROM_GROUPWORD \| ROM_REVERSE \| ROM_BIOS(bios+1)) /* Note '+1' */
458
	458
459	459	ROM_START( mu100 )
460	460	ROM_REGION( 0x200000, "maincpu", 0 )
461	461	ROM_SYSTEM_BIOS( 0, "bios0", "xu50720 (v1.11, Aug. 3, 1999)" )

trunk/src/mess/drivers/nanos.c
r29404	r29405
570	570	MCFG_SCREEN_SIZE(808, 2510)
571	571	MCFG_SCREEN_VISIBLE_AREA(0,808-1,0,2510-1)
572	572	MCFG_SCREEN_PALETTE("palette")
573
	573
574	574	MCFG_GFXDECODE_ADD("gfxdecode", "palette", nanos)
575	575	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
576	576

trunk/src/mess/drivers/z9001.c
r29404	r29405
251	251	MCFG_SCREEN_VISIBLE_AREA(0, 408-1, 0, 248-1)
252	252	MCFG_SCREEN_UPDATE_DRIVER(z9001_state, screen_update_z9001)
253	253	MCFG_SCREEN_PALETTE("palette")
254
	254
255	255	MCFG_GFXDECODE_ADD("gfxdecode", "palette", z9001)
256	256	MCFG_PALETTE_ADD("palette", 16)
257	257

trunk/src/mess/drivers/wswan.c
r29404	r29405
135	135	MCFG_SCREEN_SIZE( WSWAN_X_PIXELS, WSWAN_Y_PIXELS )
136	136	MCFG_SCREEN_VISIBLE_AREA(0*8, WSWAN_X_PIXELS - 1, 0, WSWAN_Y_PIXELS - 1)
137	137	MCFG_SCREEN_PALETTE("palette")
138
	138
139	139	MCFG_DEFAULT_LAYOUT(layout_wswan)
140	140
141	141	MCFG_QUANTUM_TIME(attotime::from_hz(60))
r29404	r29405
169	169	MCFG_CPU_MODIFY("maincpu")
170	170	MCFG_CPU_PROGRAM_MAP(wscolor_mem)
171	171	MCFG_MACHINE_START_OVERRIDE(wswan_state, wscolor )
172
	172
173	173	MCFG_PALETTE_MODIFY("palette")
174	174	MCFG_PALETTE_ENTRIES(4096)
175	175	MCFG_PALETTE_INIT_OWNER(wswan_state, wscolor )

trunk/src/mess/mess.mak
r29404	r29405
1771	1771	$(MESS_DRIVERS)/svision.o \
1772	1772	$(MESS_AUDIO)/svision.o \
1773	1773
1774		$(MESSOBJ)/swtpc09.a: \
1775		$(MESS_DRIVERS)/swtpc09.o \
	1774	$(MESSOBJ)/swtpc09.a: \
	1775	$(MESS_DRIVERS)/swtpc09.o \
1776	1776	$(MESS_MACHINE)/swtpc09.o \
1777	1777
1778	1778	$(MESSOBJ)/synertec.a: \

199869 Revisions