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r29366 Sunday 6th April, 2014 at 13:37:04 UTC by Angelo Salese
Added proper CGA device to 4enlinea. CPU logic is quite off tho, nw
[src/mame/drivers]4enlinea.c

trunk/src/mame/drivers/4enlinea.c
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137137  8952 (PIN 04) --|02   19|-- GAL (PIN 17)      8952 (PIN 08) --|02   19|-- GAL (PIN 16)
138138  MAIN Z80 (D7) --|03   18|-- MAIN Z80 (D0)     MAIN Z80 (D7) --|03   18|-- MAIN Z80 (D0)
139139  8952 (PIN 03) --|04   17|-- 8952 (PIN 40)     8952 (PIN 07) --|04   17|-- 8952 (PIN 36)
140  MAIN Z80 (D6) --|05   16|-- MAIN Z80 (D1)     MAIN Z80 (D6) --|05   16|-- MAIN Z80 (D1)
140  MAIN Z80 (D6) --|05   16|-- MAIN Z80 (D1)     MAIN Z80 (D6) --|05   16|-- MAIN Z80 (D1)
141141  8952 (PIN 02) --|06   15|-- 8952 (PIN 39)     8952 (PIN 06) --|06   15|-- 8952 (PIN 35)
142142  MAIN Z80 (D5) --|07   14|-- MAIN Z80 (D2)     MAIN Z80 (D5) --|07   14|-- MAIN Z80 (D2)
143143  8952 (PIN 01) --|08   13|-- 8952 (PIN 38)     8952 (PIN 05) --|08   13|-- 8952 (PIN 34)
144  MAIN Z80 (D4) --|09   12|-- MAIN Z80 (D3)     MAIN Z80 (D4) --|09   12|-- MAIN Z80 (D3)
144  MAIN Z80 (D4) --|09   12|-- MAIN Z80 (D3)     MAIN Z80 (D4) --|09   12|-- MAIN Z80 (D3)
145145            GND --|10   11|-- 8952 (PIN 37)               GND --|10   11|-- 8952 (PIN 33)
146146                  '-------'                                     '-------'
147147
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198198#include "cpu/z80/z80.h"
199199#include "video/mc6845.h"
200200#include "sound/ay8910.h"
201#include "bus/isa/isa.h"
202#include "bus/isa/cga.h"
203#include "video/cgapal.h"
201204
202205class _4enlinea_state : public driver_device
203206{
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205208   _4enlinea_state(const machine_config &mconfig, device_type type, const char *tag)
206209      : driver_device(mconfig, type, tag),
207210      m_ay(*this, "aysnd"),
208      m_videoram(*this, "videoram"),
209      m_videoram2(*this, "videoram2"),
210      m_maincpu(*this, "maincpu"),
211      m_gfxdecode(*this, "gfxdecode"),
212      m_screen(*this, "screen"),
213      m_palette(*this, "palette")  { }
211      m_maincpu(*this, "maincpu")
212      { }
214213
215214
216215   required_device<ay8910_device> m_ay;
217   required_shared_ptr<UINT8> m_videoram;
218   required_shared_ptr<UINT8> m_videoram2;
219216
220   DECLARE_WRITE8_MEMBER(crtc_config_w);
221   DECLARE_WRITE8_MEMBER(crtc_mode_ctrl_w);
222   DECLARE_WRITE8_MEMBER(crtc_colormode_w);
223   DECLARE_READ8_MEMBER(crtc_status_r);
224217   DECLARE_READ8_MEMBER(unk_e000_r);
225218   DECLARE_READ8_MEMBER(unk_e001_r);
219   INTERRUPT_GEN_MEMBER(_4enlinea_irq);
220   UINT8 m_irq_count;
226221
227222   virtual void machine_start();
228223   virtual void machine_reset();
229   virtual void video_start();
230   DECLARE_PALETTE_INIT(_4enlinea);
231   UINT32 screen_update_4enlinea(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
232224   required_device<cpu_device> m_maincpu;
233   required_device<gfxdecode_device> m_gfxdecode;
234   required_device<screen_device> m_screen;
235   required_device<palette_device> m_palette;
236
237   DECLARE_WRITE8_MEMBER(vram_w);
238   DECLARE_WRITE8_MEMBER(vram2_w);
239
240225};
241226
242227
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244229*          Video Hardware          *
245230***********************************/
246231
247void _4enlinea_state::video_start()
232class isa8_cga_4enlinea_device : public isa8_cga_device
248233{
249   m_gfxdecode->gfx(0)->set_source(m_videoram);
250}
234public:
235   // construction/destruction
236   isa8_cga_4enlinea_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
251237
252UINT32 _4enlinea_state::screen_update_4enlinea(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
238   virtual void device_start();
239   virtual const rom_entry *device_rom_region() const;
240};
241
242const rom_entry *isa8_cga_4enlinea_device::device_rom_region() const
253243{
254/* note: chars are 16*12 pixels */
244   return NULL;
245}
255246
256   int offset = 0;
257   int offset2 = 0;
247const device_type ISA8_CGA_4ENLINEA = &device_creator<isa8_cga_4enlinea_device>;
258248
259   for (int y = 0; y < 200; y++)
260   {
261      UINT16* dstptr_bitmap = &bitmap.pix16(y);
249isa8_cga_4enlinea_device::isa8_cga_4enlinea_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
250      isa8_cga_device( mconfig, ISA8_CGA_4ENLINEA, "ISA8_CGA_4ENLINEA", tag, owner, clock, "4enlinea_cga", __FILE__)
251{
252}
262253
263      for (int x = 0; x < 320; x += 4)
264      {
265         UINT8 pix;
266254
267         if (y & 1) pix = m_videoram2[offset2++];
268         else pix = m_videoram[offset++];
269255
270         dstptr_bitmap[x + 3] = (pix >> 0) & 0x3;
271         dstptr_bitmap[x + 2] = (pix >> 2) & 0x3;
272         dstptr_bitmap[x + 1] = (pix >> 4) & 0x3;
273         dstptr_bitmap[x + 0] = (pix >> 6) & 0x3;
274      }
275   }
256void isa8_cga_4enlinea_device::device_start()
257{
258   if (m_palette != NULL && !m_palette->started())
259      throw device_missing_dependencies();
276260
277   return 0;
278}
261   set_isa_device();
262   m_vram_size = 0x4000;
263   m_vram.resize(m_vram_size);
279264
265   m_update_row = NULL;
266   m_isa->install_device(0x3d0, 0x3df, 0, 0, read8_delegate( FUNC(isa8_cga_device::io_read), this ), write8_delegate( FUNC(isa8_cga_device::io_write), this ) );
267   m_isa->install_bank(0x8000, 0xbfff, 0, 0, "bank1", m_vram);
280268
281WRITE8_MEMBER(_4enlinea_state::vram_w)
282{
283   m_videoram[offset] = data;
284//   m_gfxdecode->gfx(0)->mark_dirty(offset/16);
285}
269   /* Initialise the cga palette */
270   int i;
286271
287WRITE8_MEMBER(_4enlinea_state::vram2_w)
288{
289   m_videoram2[offset] = data;
290//   m_gfxdecode->gfx(0)->mark_dirty(offset/16);
291}
292
293WRITE8_MEMBER(_4enlinea_state::crtc_config_w)
294{
295/* Bit 6 enables the CGA mode, otherwise is MGA */
296   if(data & 0x40)
272   for ( i = 0; i < CGA_PALETTE_SETS * 16; i++ )
297273   {
298      logerror("CRTC config mode (3BFh): CGA\n");
274      m_palette->set_pen_color( i, cga_palette[i][0], cga_palette[i][1], cga_palette[i][2] );
299275   }
300   else
276
277   i = 0x8000;
278   for ( int r = 0; r < 32; r++ )
301279   {
302      logerror("CRTC config mode (3BFh): MGA\n");
280      for ( int g = 0; g < 32; g++ )
281      {
282         for ( int b = 0; b < 32; b++ )
283         {
284            m_palette->set_pen_color( i, r << 3, g << 3, b << 3 );
285            i++;
286         }
287      }
303288   }
304}
305289
306WRITE8_MEMBER(_4enlinea_state::crtc_mode_ctrl_w)
307{
308/* Bit 3 enables/disables the video (see the notes above) */
309   logerror("CRTC mode control (3D8h): %02x\n", data);
290//   astring tempstring;
291//   m_chr_gen_base = memregion(subtag(tempstring, "gfx1"))->base();
292//   m_chr_gen = m_chr_gen_base + m_chr_gen_offset[1];
310293}
311294
312WRITE8_MEMBER(_4enlinea_state::crtc_colormode_w)
313{
314   logerror("CRTC color mode (3D9h): %02x\n", data);
315}
316295
317READ8_MEMBER(_4enlinea_state::crtc_status_r)
318{
319/*----- bits -----
320  7 6 5 4  3 2 1 0   For CGA Mode.
321  x x x x  - - - -  (bits 4-5-6-7 are unused)
322           | | | |
323           | | | '-- 0: Display active period.
324           | | |     1: Non-display period.
325           | | |
326           | | '---- 0: Light pen reset.
327           | |       1: Light pen set.
328           | |
329           | '------ 0: Light pen switch off.
330           |         1: Light pen switch on.
331           |
332           '-------- 0: Non-vertical sync period.
333                     1: Vertical sync period.
334
335*/
336   return (m_screen->vpos() >= 200) ? 0x80 : 0x00;    // bit 7 is suppossed to be unused in CGA mode
337}
338
339296READ8_MEMBER(_4enlinea_state::unk_e000_r)
340297{
341298   logerror("read e000\n");
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350307//   return (machine().rand() & 0x0f);   // after 30 seconds, random gfx appear on the screen.
351308}
352309
353
354310/***********************************
355311*      Memory Map Information      *
356312***********************************/
357313
358314static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, _4enlinea_state )
359315   AM_RANGE(0x0000, 0x7fff) AM_ROM
360   AM_RANGE(0x8000, 0x9fff) AM_RAM_WRITE(vram_w) AM_SHARE("videoram")      // even lines
361   AM_RANGE(0xa000, 0xbfff) AM_RAM_WRITE(vram2_w) AM_SHARE("videoram2")   // odd lines
316//   AM_RANGE(0x8000, 0xbfff) AM_RAM // CGA VRAM
362317   AM_RANGE(0xc000, 0xdfff) AM_RAM
363318
364319   AM_RANGE(0xe000, 0xe000) AM_READ(unk_e000_r)
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372327static ADDRESS_MAP_START( main_portmap, AS_IO, 8, _4enlinea_state )
373328   ADDRESS_MAP_GLOBAL_MASK(0x3ff)
374329
375   AM_RANGE(0x3d4, 0x3d4) AM_DEVWRITE("crtc", mc6845_device, address_w)
376   AM_RANGE(0x3d5, 0x3d5) AM_DEVWRITE("crtc", mc6845_device, register_w)
377   AM_RANGE(0x3d8, 0x3d8) AM_WRITE(crtc_mode_ctrl_w)
378   AM_RANGE(0x3d9, 0x3d9) AM_WRITE(crtc_colormode_w)
379   AM_RANGE(0x3da, 0x3da) AM_READ(crtc_status_r)
380   AM_RANGE(0x3bf, 0x3bf) AM_WRITE(crtc_config_w)
381
330//   AM_RANGE(0x3d4, 0x3df) CGA regs
382331ADDRESS_MAP_END
383332
384333
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423372   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 )                   PORT_PLAYER(2)
424373   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 )                   PORT_PLAYER(2)
425374   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
375
376
377   PORT_START( "pcvideo_cga_config" )
378   PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED )
426379INPUT_PORTS_END
427380
428381
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430383*         Graphics Layouts         *
431384***********************************/
432385
433static const gfx_layout charlayout =
434{
435   8,8,
436   0x4000/16,
437   2,
438   { 0, 1 },
439   { 0, 2, 4, 6, 8, 10, 12, 14 },
440   { 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16 },
441   8*16
442};
443386
387
444388/****************************************
445389*      Graphics Decode Information      *
446390****************************************/
447391
448392static GFXDECODE_START( 4enlinea )
449   GFXDECODE_ENTRY( NULL, 0, charlayout, 0, 1 )
450393GFXDECODE_END
451394
452395
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469412*         CRTC Interface          *
470413**********************************/
471414
472static MC6845_ON_UPDATE_ADDR_CHANGED(crtc_addr)
473{
474415
475}
476416
477static MC6845_INTERFACE( mc6845_intf )
478{
479   false,           /* show border area */
480   0,0,0,0,         /* visarea adjustment */
481   8,               /* number of pixels per video memory address */
482   NULL,            /* before pixel update callback */
483   NULL,            /* row update callback */
484   NULL,            /* after pixel update callback */
485   DEVCB_NULL,      /* callback for display state changes */
486   DEVCB_NULL,      /* callback for cursor state changes */
487   DEVCB_NULL,      /* HSYNC callback */
488   DEVCB_NULL,      /* VSYNC callback */
489   crtc_addr        /* update address callback */
490};
491
492
493417/***********************************
494418*         Sound Interface          *
495419***********************************/
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509433*         Machine Drivers          *
510434***********************************/
511435
436SLOT_INTERFACE_START( 4enlinea_isa8_cards )
437   SLOT_INTERFACE_INTERNAL("4enlinea",  ISA8_CGA_4ENLINEA)
438SLOT_INTERFACE_END
439
440static const isa8bus_interface _4enlinea_isabus_intf =
441{
442   // interrupts
443   DEVCB_NULL,
444   DEVCB_NULL,
445   DEVCB_NULL,
446   DEVCB_NULL,
447   DEVCB_NULL,
448   DEVCB_NULL,
449
450   // dma request
451   DEVCB_NULL,
452   DEVCB_NULL,
453   DEVCB_NULL
454};
455
456/* TODO: irq sources are unknown */
457INTERRUPT_GEN_MEMBER(_4enlinea_state::_4enlinea_irq)
458{
459   if(m_irq_count == 0)
460      device.execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
461   else
462      device.execute().set_input_line(0, HOLD_LINE);
463
464   m_irq_count++;
465   m_irq_count&=3;
466}
467
512468static MACHINE_CONFIG_START( 4enlinea, _4enlinea_state )
513469
514470   /* basic machine hardware */
515471   MCFG_CPU_ADD("maincpu", Z80, PRG_CPU_CLOCK)
516472   MCFG_CPU_PROGRAM_MAP(main_map)
517473   MCFG_CPU_IO_MAP(main_portmap)
518   MCFG_CPU_VBLANK_INT_DRIVER("screen", _4enlinea_state, nmi_line_pulse)
519   MCFG_CPU_PERIODIC_INT_DRIVER(_4enlinea_state, irq0_line_hold, 4*60)
474   MCFG_CPU_PERIODIC_INT_DRIVER(_4enlinea_state, _4enlinea_irq, 60) //TODO
475//   MCFG_CPU_PERIODIC_INT_DRIVER(_4enlinea_state, irq0_line_hold, 4*35)
520476
521477   MCFG_CPU_ADD("audiocpu", Z80, SND_CPU_CLOCK)
522478   MCFG_CPU_PROGRAM_MAP(audio_map)
523479   MCFG_CPU_IO_MAP(audio_portmap)
524480
525   /* video hardware */
526   MCFG_SCREEN_ADD("screen", RASTER)
527   MCFG_SCREEN_REFRESH_RATE(60)
528   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
529   MCFG_SCREEN_SIZE(320, 200)
530   MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 200-1)
531   MCFG_SCREEN_UPDATE_DRIVER(_4enlinea_state, screen_update_4enlinea)
532   MCFG_SCREEN_PALETTE("palette")
481   MCFG_ISA8_BUS_ADD("isa", ":maincpu", _4enlinea_isabus_intf)
482   MCFG_ISA8_SLOT_ADD("isa", "isa1", 4enlinea_isa8_cards, "4enlinea", true)
533483
534   MCFG_GFXDECODE_ADD("gfxdecode", "palette", 4enlinea)
535   MCFG_PALETTE_ADD("palette", 256)
536484
537485/*  6845 clock is a guess, since it's a UM6845R embedded in the UM487F.
538486    CRTC_CLOCK is 8MHz, entering for pin 1 of UM487F. This clock is used
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542490   CRTC_CLOCK / 4.5 = 59.521093 Hz.
543491    CRTC_CLOCK / 5.0 = 53.569037 Hz.
544492*/
545//   MCFG_MC6845_ADD("crtc", MC6845, "screen", CRTC_CLOCK / 2, mc6845_intf)   // seems that MC6845 doesn't support the game mode
546   MCFG_MC6845_ADD("crtc", R6545_1, "screen", CRTC_CLOCK / 4.5, mc6845_intf)
547493
548494   /* sound hardware */
549495   MCFG_SPEAKER_STANDARD_MONO("mono")

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