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r29310 Saturday 5th April, 2014 at 12:31:38 UTC by Curt Coder
(MESS) tandy2k: WIP. (nw)

[src/emu/video]	crt9021.h crt9212.c crt9212.h
[src/mess/drivers]	tandy2k.c
[src/mess/includes]	tandy2k.h

trunk/src/emu/video/crt9212.c

r29309	r29310
51	51	m_oe(0),
52	52	m_rclk(0),
53	53	m_wclk(0),
	54	m_clrcnt_edge(false),
	55	m_data_latch(0),
	56	m_ren_int(0),
	57	m_wen_int(0),
54	58	m_buffer(0),
55	59	m_rac(0),
56	60	m_wac(0)
r29309	r29310
79	83	save_item(NAME(m_oe));
80	84	save_item(NAME(m_rclk));
81	85	save_item(NAME(m_wclk));
	86	save_item(NAME(m_clrcnt_edge));
	87	save_item(NAME(m_data_latch));
	88	save_item(NAME(m_ren_int));
	89	save_item(NAME(m_wen_int));
82	90	save_item(NAME(m_ram[0]));
83	91	save_item(NAME(m_ram[1]));
84	92	save_item(NAME(m_buffer));
r29309	r29310
88	96
89	97
90	98	//-------------------------------------------------
	99	//  clrcnt_w - clear counter
	100	//-------------------------------------------------
	101
	102	WRITE_LINE_MEMBER( crt9212_t::clrcnt_w )
	103	{
	104	if (m_clrcnt && !state)
	105	{
	106	m_clrcnt_edge = true;
	107	}
	108
	109	m_clrcnt = state;
	110	}
	111
	112
	113	//-------------------------------------------------
91	114	//  rclk_w - read clock
92	115	//-------------------------------------------------
93	116
94	117	WRITE_LINE_MEMBER( crt9212_t::rclk_w )
95	118	{
96		if (m_rclk && !state)
	119	if (!m_rclk && state)
97	120	{
98		if (!m_clrcnt)
	121	if (m_clrcnt_edge)
99	122	{
	123	// reset read address counter
	124	m_rac = 0;
	125
	126	// reset read overflow
	127	m_write_rof(0);
	128
100	129	if (!m_tog)
101	130	{
102		// switch buffer
	131	// switch buffers
103	132	m_buffer = !m_buffer;
104	133
105		// clear write address counter
	134	// reset write address counter
106	135	m_wac = 0;
	136
	137	// reset write overflow
107	138	m_write_wof(0);
108	139	}
109		else
110		{
111		// clear read address counter
112		m_rac = 0;
113		m_write_rof(0);
114		}
	140
	141	m_clrcnt_edge = false;
115	142	}
116		else
	143
	144	if (m_ren_int && (m_rac < CRT9212_RAM_SIZE))
117	145	{
118		if (m_ren && (m_rac < CRT9212_RAM_SIZE))
119		{
120		//
121		m_write_dout(m_ram[m_rac][!m_buffer]);
	146	// output data
	147	m_write_dout(m_ram[m_rac][!m_buffer]);
122	148
123		// increment read address counter
124		m_rac++;
	149	// increment read address counter
	150	m_rac++;
125	151
126		if (m_rac == CRT9212_RAM_SIZE)
127		{
128		// set read overflow
129		m_write_rof(1);
130		}
	152	if (m_rac == CRT9212_RAM_SIZE - 1)
	153	{
	154	// set read overflow
	155	m_write_rof(1);
131	156	}
132	157	}
	158
	159	m_ren_int = m_ren;
133	160	}
134	161
135	162	m_rclk = state;
r29309	r29310
144	171	{
145	172	if (!m_wclk && state)
146	173	{
147		if (m_wen1 && m_wen2 && (m_wac < CRT9212_RAM_SIZE))
	174	if (m_wen_int && (m_wac < CRT9212_RAM_SIZE))
148	175	{
149		//
150		m_ram[m_rac][m_buffer] = m_data;
	176	// input data
	177	m_ram[m_rac][m_buffer] = m_data_latch;
151	178
152		// increment read address counter
	179	// increment write address counter
153	180	m_wac++;
154	181
155		if (m_wac == CRT9212_RAM_SIZE)
	182	if (m_wac == CRT9212_RAM_SIZE - 1)
156	183	{
157	184	// set write overflow
158	185	m_write_wof(1);
159	186	}
160	187	}
	188
	189	if (m_wen1 && m_wen2)
	190	{
	191	m_data_latch = m_data;
	192	}
	193
	194	m_wen_int = m_wen1 && m_wen2;
161	195	}
162	196
163	197	m_wclk = state;

trunk/src/emu/video/crt9212.h

r29309	r29310
47	47	//  INTERFACE CONFIGURATION MACROS
48	48	//**************************************************************************
49	49
	50	#define MCFG_CRT9212_WEN2_VCC() \
	51	crt9212_t::static_set_wen2(*device, 1);
	52
50	53	#define MCFG_CRT9212_DOUT_CALLBACK(_write) \
51	54	devcb = &crt9212_t::set_dout_wr_callback(*device, DEVCB2_##_write);
52	55
r29309	r29310
70	73	// construction/destruction
71	74	crt9212_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
72	75
	76	static void static_set_wen2(device_t &device, int state) { downcast<crt9212_t &>(device).m_wen2 = state; }
	77
73	78	template<class _Object> static devcb2_base &set_dout_wr_callback(device_t &device, _Object object) { return downcast<crt9212_t &>(device).m_write_dout.set_callback(object); }
74	79	template<class _Object> static devcb2_base &set_rof_wr_callback(device_t &device, _Object object) { return downcast<crt9212_t &>(device).m_write_rof.set_callback(object); }
75	80	template<class _Object> static devcb2_base &set_wof_wr_callback(device_t &device, _Object object) { return downcast<crt9212_t &>(device).m_write_wof.set_callback(object); }
76	81
77	82	DECLARE_WRITE8_MEMBER( write ) { m_data = data; }
78		DECLARE_WRITE_LINE_MEMBER( clrcnt_w ) { m_clrcnt = state; }
	83	DECLARE_WRITE_LINE_MEMBER( clrcnt_w );
79	84	DECLARE_WRITE_LINE_MEMBER( tog_w ) { m_tog = state; }
80	85	DECLARE_WRITE_LINE_MEMBER( ren_w ) { m_ren = state; }
81	86	DECLARE_WRITE_LINE_MEMBER( wen1_w ) { m_wen1 = state; }
r29309	r29310
105	110	int m_wclk;
106	111
107	112	// internal state
	113	bool m_clrcnt_edge;
	114	UINT8 m_data_latch;
	115	int m_ren_int;
	116	int m_wen_int;
108	117	UINT8 m_ram[CRT9212_RAM_SIZE][2];
109	118	int m_buffer;
110	119	int m_rac;

trunk/src/emu/video/crt9021.h

r29309	r29310
64	64
65	65	static void static_set_display_callback(device_t &device, crt9021_draw_character_delegate callback) { downcast<crt9021_t &>(device).m_display_cb = callback; }
66	66
67		DECLARE_WRITE8_MEMBER( write ) { m_data = data; }
	67	void write(UINT8 data) { m_data = data; }
	68	DECLARE_WRITE8_MEMBER( write ) { write(data); }
68	69	DECLARE_WRITE_LINE_MEMBER( ms0_w ) { m_ms0 = state; }
69	70	DECLARE_WRITE_LINE_MEMBER( ms1_w ) { m_ms1 = state; }
70	71	DECLARE_WRITE_LINE_MEMBER( revid_w ) { m_revid = state; }

trunk/src/mess/includes/tandy2k.h

r29309	r29310
3	3	#ifndef __TANDY2K__
4	4	#define __TANDY2K__
5	5
6
7	6	#include "emu.h"
	7	#include "bus/centronics/ctronics.h"
	8	#include "bus/rs232/rs232.h"
8	9	#include "cpu/i86/i186.h"
9	10	#include "cpu/mcs48/mcs48.h"
10	11	#include "imagedev/harddriv.h"
11		#include "bus/centronics/ctronics.h"
12	12	#include "machine/i8255.h"
13	13	#include "machine/i8251.h"
14	14	#include "machine/pit8253.h"
r29309	r29310
61	61	m_ram(*this, RAM_TAG),
62	62	m_floppy0(*this, I8272A_TAG ":0:525qd"),
63	63	m_floppy1(*this, I8272A_TAG ":1:525qd"),
	64	m_rs232(*this, RS232_TAG),
64	65	m_kb(*this, TANDY2K_KEYBOARD_TAG),
65	66	m_hires_ram(*this, "hires_ram"),
66	67	m_char_ram(*this, "char_ram"),
67		m_kbdclk(0)
	68	m_dma_mux(0),
	69	m_kbdclk(0),
	70	m_kbddat(0),
	71	m_kbdin(0),
	72	m_extclk(0),
	73	m_rxrdy(0),
	74	m_txrdy(0),
	75	m_pb_sel(0),
	76	m_vram_base(0),
	77	m_vidouts(0),
	78	m_clkspd(0),
	79	m_clkcnt(0),
	80	m_blc(0),
	81	m_bkc(0),
	82	m_cblank(0),
	83	m_dblc(0),
	84	m_dbkc(0),
	85	m_dblank(0),
	86	m_slg(0),
	87	m_sld(0),
	88	m_cgra(0),
	89	m_vidla(0),
	90	m_outspkr(0),
	91	m_spkrdata(0),
	92	m_centronics_ack(0),
	93	m_centronics_fault(0),
	94	m_centronics_select(0),
	95	m_centronics_perror(0),
	96	m_centronics_busy(0)
68	97	{
69	98	}
70	99
r29309	r29310
86	115	required_device<ram_device> m_ram;
87	116	required_device<floppy_image_device> m_floppy0;
88	117	required_device<floppy_image_device> m_floppy1;
	118	required_device<rs232_port_device> m_rs232;
89	119	required_device<tandy2k_keyboard_device> m_kb;
90	120	required_shared_ptr<UINT16> m_hires_ram;
91		required_shared_ptr<UINT16> m_char_ram;
	121	optional_shared_ptr<UINT8> m_char_ram;
92	122
93	123	virtual void machine_start();
94	124
95	125	void speaker_update();
96	126	void dma_request(int line, int state);
97	127
	128	DECLARE_READ8_MEMBER( char_ram_r );
	129	DECLARE_WRITE8_MEMBER( char_ram_w );
98	130	DECLARE_READ8_MEMBER( videoram_r );
99	131	DECLARE_READ8_MEMBER( enable_r );
100	132	DECLARE_WRITE8_MEMBER( enable_w );
r29309	r29310
115	147	DECLARE_WRITE_LINE_MEMBER( vpac_vlt_w );
116	148	DECLARE_WRITE_LINE_MEMBER( vpac_drb_w );
117	149	DECLARE_WRITE_LINE_MEMBER( vpac_wben_w );
	150	DECLARE_WRITE_LINE_MEMBER( vpac_cblank_w );
	151	DECLARE_WRITE_LINE_MEMBER( vpac_slg_w );
	152	DECLARE_WRITE_LINE_MEMBER( vpac_sld_w );
	153	DECLARE_WRITE8_MEMBER( vidla_w );
118	154	DECLARE_WRITE8_MEMBER( drb_attr_w );
119	155	DECLARE_WRITE_LINE_MEMBER( kbdclk_w );
120	156	DECLARE_WRITE_LINE_MEMBER( kbddat_w );
121	157	DECLARE_READ8_MEMBER( irq_callback );
122	158	DECLARE_WRITE_LINE_MEMBER( fdc_drq );
	159	DECLARE_WRITE_LINE_MEMBER(write_centronics_ack);
	160	DECLARE_WRITE_LINE_MEMBER(write_centronics_busy);
	161	DECLARE_WRITE_LINE_MEMBER(write_centronics_perror);
	162	DECLARE_WRITE_LINE_MEMBER(write_centronics_select);
	163	DECLARE_WRITE_LINE_MEMBER(write_centronics_fault);
123	164	CRT9021_DRAW_CHARACTER_MEMBER( vac_draw_character );
124	165	TIMER_DEVICE_CALLBACK_MEMBER( vidldsh_tick );
125	166
	167	enum
	168	{
	169	LPINEN = 0,
	170	KBDINEN,
	171	PORTINEN
	172	};
	173
126	174	/* DMA state */
127	175	UINT8 m_dma_mux;
128	176
r29309	r29310
144	192	int m_vidouts;
145	193	int m_clkspd;
146	194	int m_clkcnt;
	195	int m_blc;
	196	int m_bkc;
	197	int m_cblank;
	198	UINT8 m_dblc;
	199	UINT8 m_dbkc;
	200	UINT8 m_dblank;
	201	int m_slg;
	202	int m_sld;
	203	UINT8 m_cgra;
	204	UINT8 m_vidla;
147	205
148	206	/* sound state */
149	207	int m_outspkr;
r29309	r29310
154	212	int m_centronics_select;
155	213	int m_centronics_perror;
156	214	int m_centronics_busy;
157
158		DECLARE_WRITE_LINE_MEMBER(write_centronics_ack);
159		DECLARE_WRITE_LINE_MEMBER(write_centronics_busy);
160		DECLARE_WRITE_LINE_MEMBER(write_centronics_perror);
161		DECLARE_WRITE_LINE_MEMBER(write_centronics_select);
162		DECLARE_WRITE_LINE_MEMBER(write_centronics_fault);
163	215	};
164	216
165	217	#endif

trunk/src/mess/drivers/tandy2k.c

r29309	r29310
12	12
13	13	TODO:
14	14
15		- CRT9007
16		- CRT9212 Double Row Buffer
17		- CRT9021B Attribute Generator
	15	- video
18	16	- keyboard ROM
19	17	- hires graphics board
20	18	- floppy 720K DSQD
r29309	r29310
26	24	*/
27	25
28	26	#include "includes/tandy2k.h"
29		#include "bus/rs232/rs232.h"
30	27
31		enum
32		{
33		LPINEN = 0,
34		KBDINEN,
35		PORTINEN
36		};
37
38	28	// Read/Write Handlers
39	29
40	30	void tandy2k_state::dma_request(int line, int state)
r29309	r29310
44	34	void tandy2k_state::speaker_update()
45	35	{
46	36	int level = !(m_spkrdata & m_outspkr);
	37
47	38	m_speaker->level_w(level);
48	39	}
49	40
	41	READ8_MEMBER( tandy2k_state::char_ram_r )
	42	{
	43	return m_char_ram[offset];
	44	}
	45
	46	WRITE8_MEMBER( tandy2k_state::char_ram_w )
	47	{
	48	m_char_ram[offset] = data;
	49	}
	50
50	51	READ8_MEMBER( tandy2k_state::videoram_r )
51	52	{
52	53	address_space &program = m_maincpu->space(AS_PROGRAM);
r29309	r29310
80	81
81	82	*/
82	83
83		return 0x80;
	84	UINT8 data = 0x80;
	85
	86	data |= m_rs232->ri_r();
	87	data |= m_rs232->dcd_r() << 1;
	88
	89	return data;
84	90	}
85	91
86	92	WRITE8_MEMBER( tandy2k_state::enable_w )
r29309	r29310
240	246
241	247	m_vpac->set_character_width(clkcnt ? 8 : 10);
242	248	m_vpac->set_unscaled_clock(vidcclk);
243
	249
244	250	m_vac->set_unscaled_clock(busdotclk);
245	251
246	252	m_timer_vidldsh->adjust(attotime::from_hz(vidcclk), 0, attotime::from_hz(vidcclk));
r29309	r29310
261	267	ADDRESS_MAP_UNMAP_HIGH
262	268	//  AM_RANGE(0x00000, 0xdffff) AM_RAM
263	269	AM_RANGE(0xe0000, 0xf7fff) AM_RAM AM_SHARE("hires_ram")
264		AM_RANGE(0xf8000, 0xfbfff) AM_RAM AM_SHARE("char_ram")
	270	AM_RANGE(0xf8000, 0xfbfff) AM_READWRITE8(char_ram_r, char_ram_w, 0x00ff)
265	271	AM_RANGE(0xfc000, 0xfdfff) AM_MIRROR(0x2000) AM_ROM AM_REGION(I80186_TAG, 0)
266	272	ADDRESS_MAP_END
267	273
r29309	r29310
326	332	m_drb1->wen1_w(state);
327	333	}
328	334
	335	WRITE_LINE_MEMBER( tandy2k_state::vpac_cblank_w )
	336	{
	337	m_cblank = state;
	338	}
	339
	340	WRITE_LINE_MEMBER( tandy2k_state::vpac_slg_w )
	341	{
	342	m_slg = state;
	343
	344	m_vac->slg_w(state);
	345	}
	346
	347	WRITE_LINE_MEMBER( tandy2k_state::vpac_sld_w )
	348	{
	349	m_sld = state;
	350
	351	m_vac->sld_w(state);
	352	}
	353
	354	WRITE8_MEMBER( tandy2k_state::vidla_w )
	355	{
	356	m_vidla = data;
	357	}
	358
329	359	WRITE8_MEMBER( tandy2k_state::drb_attr_w )
330	360	{
331	361	/*
332	362
333	363	bit     description
334	364
335		0       BLC -> DBLC
336		1       BKC -> DBKC
	365	0       BLC -> DBLC (delayed 2 CCLKs)
	366	1       BKC -> DBKC (delayed 2 CCLKs)
337	367	2       CHABL
338	368	3       MS0
339	369	4       MS1
r29309	r29310
343	373
344	374	*/
345	375
	376	m_blc = BIT(data, 0);
	377	m_bkc = BIT(data, 1);
346	378	m_vac->chabl_w(BIT(data, 2));
347	379	m_vac->ms0_w(BIT(data, 3));
348	380	m_vac->ms1_w(BIT(data, 4));
r29309	r29310
372	404	m_vac->ld_sh_w(0);
373	405
374	406	// 1 busdotclk later
	407	m_vac->blc_w(BIT(m_dblc, 0));
	408	m_dblc >>= 1;
	409	m_dblc |= m_blc << 2;
	410
	411	m_vac->bkc_w(BIT(m_dbkc, 0));
	412	m_dbkc >>= 1;
	413	m_dbkc |= m_bkc << 2;
	414
	415	m_vac->retbl_w(BIT(m_dblank, 0));
	416	m_dblank >>= 1;
	417	m_dblank |= m_cblank << 2;
	418
	419	if (!m_slg)
	420	{
	421	m_cgra >>= 1;
	422	m_cgra |= m_sld << 3;
	423	}
	424
	425	UINT8 vidd = m_char_ram[(m_vidla << 4) | m_cgra];
	426	m_vac->write(vidd);
	427
375	428	m_drb0->rclk_w(1);
376	429	m_drb0->wclk_w(1);
377	430	m_drb1->rclk_w(1);
r29309	r29310
610	663
611	664	program.install_ram(0x00000, ram_size - 1, ram);
612	665
	666	m_char_ram.allocate(0x1000);
	667
613	668	// register for state saving
614	669	save_item(NAME(m_dma_mux));
615	670	save_item(NAME(m_kbdclk));
r29309	r29310
655	710	MCFG_CRT9007_CURS_CALLBACK(DEVWRITELINE(CRT9021B_TAG, crt9021_t, cursor_w))
656	711	MCFG_CRT9007_DRB_CALLBACK(WRITELINE(tandy2k_state, vpac_drb_w))
657	712	MCFG_CRT9007_WBEN_CALLBACK(WRITELINE(tandy2k_state, vpac_wben_w))
658		MCFG_CRT9007_CBLANK_CALLBACK(DEVWRITELINE(CRT9021B_TAG, crt9021_t, retbl_w))
659		MCFG_CRT9007_SLG_CALLBACK(DEVWRITELINE(CRT9021B_TAG, crt9021_t, slg_w))
660		MCFG_CRT9007_SLD_CALLBACK(DEVWRITELINE(CRT9021B_TAG, crt9021_t, sld_w))
	713	MCFG_CRT9007_CBLANK_CALLBACK(WRITELINE(tandy2k_state, vpac_cblank_w))
	714	MCFG_CRT9007_SLG_CALLBACK(WRITELINE(tandy2k_state, vpac_slg_w))
	715	MCFG_CRT9007_SLD_CALLBACK(WRITELINE(tandy2k_state, vpac_sld_w))
661	716	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
662	717
663	718	MCFG_DEVICE_ADD(CRT9212_0_TAG, CRT9212, 0)
664		MCFG_CRT9212_DOUT_CALLBACK(DEVWRITE8(CRT9021B_TAG, crt9021_t, write))
	719	MCFG_CRT9212_WEN2_VCC()
	720	MCFG_CRT9212_DOUT_CALLBACK(WRITE8(tandy2k_state, vidla_w))
665	721
666	722	MCFG_DEVICE_ADD(CRT9212_1_TAG, CRT9212, 0)
	723	MCFG_CRT9212_WEN2_VCC()
667	724	MCFG_CRT9212_DOUT_CALLBACK(WRITE8(tandy2k_state, drb_attr_w))
668	725
669	726	MCFG_DEVICE_ADD(CRT9021B_TAG, CRT9021, XTAL_16MHz*28/16)

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