trunk/src/emu/cpu/sh2/sh2comn.c
| r29285 | r29286 | |
|---|
| 536 | 536 | |
| 537 | 537 | switch( offset ) |
| 538 | 538 | { |
| 539 | case 0x00: |
| 540 | //if(mem_mask == 0xff) |
| 541 | // printf("%c",data & 0xff); |
| 542 | break; |
| 543 | case 0x01: |
| 544 | //printf("%08x %02x %02x\n",mem_mask,offset,data); |
| 545 | break; |
| 539 | 546 | // Timers |
| 540 | 547 | case 0x04: // TIER, FTCSR, FRC |
| 541 | 548 | if((mem_mask & 0x00ffffff) != 0) |
| r29285 | r29286 | |
|---|
| 747 | 754 | // logerror("sh2_internal_r: Read %08x (%x) @ %08x\n", 0xfffffe00+offset*4, offset, mem_mask); |
| 748 | 755 | switch( offset ) |
| 749 | 756 | { |
| 757 | case 0x00: |
| 758 | break; |
| 759 | case 0x01: |
| 760 | return sh2->m[1] | 0x80000000; // TDRE: Trasmit Data Register Empty. Force it to be '1' for the time being. |
| 761 | |
| 750 | 762 | case 0x04: // TIER, FTCSR, FRC |
| 751 | 763 | if ( mem_mask == 0x00ff0000 ) |
| 752 | 764 | { |
trunk/src/mame/drivers/namcos23.c
| r29285 | r29286 | |
|---|
| 1400 | 1400 | required_device<screen_device> m_screen; |
| 1401 | 1401 | required_device<palette_device> m_palette; |
| 1402 | 1402 | |
| 1403 | | |
| 1403 | |
| 1404 | 1404 | c404_t m_c404; |
| 1405 | 1405 | c361_t m_c361; |
| 1406 | 1406 | c417_t m_c417; |
| r29285 | r29286 | |
|---|
| 2765 | 2765 | static ADDRESS_MAP_START( gmen_mips_map, AS_PROGRAM, 32, namcos23_state ) |
| 2766 | 2766 | AM_IMPORT_FROM(s23_map) |
| 2767 | 2767 | AM_RANGE(0x0e400000, 0x0e400003) AM_READ(gmen_trigger_sh2) |
| 2768 | | AM_RANGE(0x0e700000, 0x0e707fff) AM_READWRITE(sh2_shared_r, sh2_shared_w) |
| 2768 | AM_RANGE(0x0e700000, 0x0e70ffff) AM_READWRITE(sh2_shared_r, sh2_shared_w) |
| 2769 | 2769 | ADDRESS_MAP_END |
| 2770 | 2770 | |
| 2771 | 2771 | |
| 2772 | 2772 | // SH2 memmap |
| 2773 | /* TODO: of course, I believe that area 0x008***** is actually a bank of some sort ... */ |
| 2773 | 2774 | static ADDRESS_MAP_START( gmen_sh2_map, AS_PROGRAM, 32, namcos23_state ) |
| 2774 | | AM_RANGE(0x00000000, 0x00007fff) AM_RAM AM_SHARE("gmen_sh2_shared") |
| 2775 | | AM_RANGE(0x04000000, 0x043fffff) AM_RAM // SH-2 main work RAM |
| 2775 | AM_RANGE(0x00000000, 0x0000ffff) AM_RAM AM_SHARE("gmen_sh2_shared") |
| 2776 | AM_RANGE(0x00800000, 0x008fffff) AM_ROM AM_REGION("data", 0xc00000) //c00000 "data" for final furlong 2. 0x1b6bc0 "user1" for gunmen wars |
| 2777 | AM_RANGE(0x01800000, 0x0183ffff) AM_RAM // ??? |
| 2778 | //AM_RANGE(0x02800000, 0x02800003) AM_RAM // probably transfer status related, reads/writes after each end of flash transfer, TBD |
| 2779 | AM_RANGE(0x04000000, 0x043fffff) AM_RAM // SH-2 main work RAM (SDRAM) |
| 2780 | AM_RANGE(0x06000000, 0x06000003) AM_NOP // serial port for camera? |
| 2776 | 2781 | ADDRESS_MAP_END |
| 2777 | 2782 | |
| 2778 | 2783 | |
| r29285 | r29286 | |
|---|
| 3350 | 3355 | MCFG_LINE_DISPATCH_ADD("clk_dispatch", 2) |
| 3351 | 3356 | MCFG_LINE_DISPATCH_FWD_CB(0, 2, DEVWRITELINE(":rtc", rtc4543_device, clk_w)) MCFG_DEVCB_INVERT |
| 3352 | 3357 | MCFG_LINE_DISPATCH_FWD_CB(1, 2, DEVWRITELINE(":namco_settings", namco_settings_device, clk_w)) |
| 3353 | | |
| 3358 | |
| 3354 | 3359 | MCFG_DEVICE_MODIFY("subcpu:sci1") |
| 3355 | 3360 | MCFG_H8_SCI_TX_CALLBACK(DEVWRITELINE(":namco_settings", namco_settings_device, data_w)) |
| 3356 | 3361 | MCFG_H8_SCI_CLK_CALLBACK(DEVWRITELINE(":clk_dispatch", devcb2_line_dispatch_device<2>, in_w)) |
| r29285 | r29286 | |
|---|
| 3418 | 3423 | MCFG_LINE_DISPATCH_ADD("clk_dispatch", 2) |
| 3419 | 3424 | MCFG_LINE_DISPATCH_FWD_CB(0, 2, DEVWRITELINE(":rtc", rtc4543_device, clk_w)) MCFG_DEVCB_INVERT |
| 3420 | 3425 | MCFG_LINE_DISPATCH_FWD_CB(1, 2, DEVWRITELINE(":namco_settings", namco_settings_device, clk_w)) |
| 3421 | | |
| 3426 | |
| 3422 | 3427 | MCFG_DEVICE_MODIFY("subcpu:sci1") |
| 3423 | 3428 | MCFG_H8_SCI_TX_CALLBACK(DEVWRITELINE(":namco_settings", namco_settings_device, data_w)) |
| 3424 | 3429 | MCFG_H8_SCI_CLK_CALLBACK(DEVWRITELINE(":clk_dispatch", devcb2_line_dispatch_device<2>, in_w)) |
| r29285 | r29286 | |
|---|
| 3497 | 3502 | MCFG_LINE_DISPATCH_ADD("clk_dispatch", 2) |
| 3498 | 3503 | MCFG_LINE_DISPATCH_FWD_CB(0, 2, DEVWRITELINE(":rtc", rtc4543_device, clk_w)) MCFG_DEVCB_INVERT |
| 3499 | 3504 | MCFG_LINE_DISPATCH_FWD_CB(1, 2, DEVWRITELINE(":namco_settings", namco_settings_device, clk_w)) |
| 3500 | | |
| 3505 | |
| 3501 | 3506 | MCFG_DEVICE_MODIFY("subcpu:sci1") |
| 3502 | 3507 | MCFG_H8_SCI_TX_CALLBACK(DEVWRITELINE(":namco_settings", namco_settings_device, data_w)) |
| 3503 | 3508 | MCFG_H8_SCI_CLK_CALLBACK(DEVWRITELINE(":clk_dispatch", devcb2_line_dispatch_device<2>, in_w)) |