trunk/src/mame/includes/mjkjidai.h
| r29217 | r29218 | |
| 1 | #include "machine/nvram.h" |
| 1 | 2 | #include "sound/okiadpcm.h" |
| 2 | 3 | |
| 3 | 4 | class mjkjidai_adpcm_device; |
| r29217 | r29218 | |
| 7 | 8 | public: |
| 8 | 9 | mjkjidai_state(const machine_config &mconfig, device_type type, const char *tag) |
| 9 | 10 | : driver_device(mconfig, type, tag), |
| 10 | | m_nvram(*this, "nvram"), |
| 11 | 11 | m_spriteram1(*this, "spriteram1"), |
| 12 | 12 | m_spriteram2(*this, "spriteram2"), |
| 13 | 13 | m_spriteram3(*this, "spriteram3"), |
| 14 | 14 | m_videoram(*this, "videoram"), |
| 15 | 15 | m_maincpu(*this, "maincpu"), |
| 16 | 16 | m_mjk_adpcm(*this, "adpcm"), |
| 17 | m_nvram(*this, "nvram"), |
| 17 | 18 | m_gfxdecode(*this, "gfxdecode"), |
| 18 | 19 | m_palette(*this, "palette") { } |
| 19 | 20 | |
| 20 | | required_shared_ptr<UINT8> m_nvram; |
| 21 | 21 | required_shared_ptr<UINT8> m_spriteram1; |
| 22 | 22 | required_shared_ptr<UINT8> m_spriteram2; |
| 23 | 23 | required_shared_ptr<UINT8> m_spriteram3; |
| r29217 | r29218 | |
| 25 | 25 | |
| 26 | 26 | required_device<cpu_device> m_maincpu; |
| 27 | 27 | required_device<mjkjidai_adpcm_device> m_mjk_adpcm; |
| 28 | required_device<nvram_device> m_nvram; |
| 28 | 29 | required_device<gfxdecode_device> m_gfxdecode; |
| 29 | 30 | required_device<palette_device> m_palette; |
| 30 | 31 | |
trunk/src/mame/includes/3do.h
| r29217 | r29218 | |
| 7 | 7 | #ifndef _3DO_H_ |
| 8 | 8 | #define _3DO_H_ |
| 9 | 9 | |
| 10 | #include "machine/nvram.h" |
| 11 | |
| 12 | |
| 10 | 13 | struct SLOW2 { |
| 11 | 14 | /* 03180000 - 0318003f - configuration group */ |
| 12 | 15 | /* 03180040 - 0318007f - diagnostic UART */ |
| r29217 | r29218 | |
| 139 | 142 | m_maincpu(*this, "maincpu"), |
| 140 | 143 | m_dram(*this, "dram"), |
| 141 | 144 | m_vram(*this, "vram"), |
| 145 | m_nvram(*this, "nvram"), |
| 142 | 146 | m_bank1(*this, "bank1"), |
| 143 | 147 | m_bank2(*this, "bank2") { } |
| 144 | 148 | |
| 145 | 149 | required_device<cpu_device> m_maincpu; |
| 146 | 150 | required_shared_ptr<UINT32> m_dram; |
| 147 | 151 | required_shared_ptr<UINT32> m_vram; |
| 152 | required_device<nvram_device> m_nvram; |
| 148 | 153 | SLOW2 m_slow2; |
| 149 | 154 | MADAM m_madam; |
| 150 | 155 | CLIO m_clio; |
| 151 | 156 | SVF m_svf; |
| 152 | 157 | DSPP m_dspp; |
| 153 | | UINT8 m_nvram[0x8000]; |
| 158 | UINT8 m_nvmem[0x8000]; |
| 154 | 159 | |
| 155 | 160 | // UINT8 m_video_bits[512]; |
| 156 | 161 | DECLARE_READ8_MEMBER(_3do_nvarea_r); |
| r29217 | r29218 | |
| 165 | 170 | DECLARE_WRITE32_MEMBER(_3do_clio_w); |
| 166 | 171 | virtual void machine_start(); |
| 167 | 172 | virtual void machine_reset(); |
| 173 | DECLARE_MACHINE_START(_3do); |
| 168 | 174 | DECLARE_VIDEO_START(_3do); |
| 169 | 175 | UINT32 screen_update__3do(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); |
| 170 | 176 | |
trunk/src/mame/drivers/mjkjidai.c
| r29217 | r29218 | |
| 25 | 25 | #include "cpu/z80/z80.h" |
| 26 | 26 | #include "sound/sn76496.h" |
| 27 | 27 | #include "includes/mjkjidai.h" |
| 28 | | #include "mcfglgcy.h" |
| 29 | 28 | |
| 30 | 29 | /* Start of ADPCM custom chip code */ |
| 31 | 30 | |
| r29217 | r29218 | |
| 133 | 132 | |
| 134 | 133 | res |= (ioport("IN3")->read() & 0xc0); |
| 135 | 134 | |
| 136 | | if (m_nvram_init_count) |
| 137 | | { |
| 138 | | m_nvram_init_count--; |
| 139 | | res &= 0xbf; |
| 140 | | } |
| 141 | | |
| 142 | 135 | return res; |
| 143 | 136 | } |
| 144 | 137 | |
| r29217 | r29218 | |
| 153 | 146 | } |
| 154 | 147 | } |
| 155 | 148 | |
| 156 | | static NVRAM_HANDLER( mjkjidai ) |
| 157 | | { |
| 158 | | mjkjidai_state *state = machine.driver_data<mjkjidai_state>(); |
| 159 | 149 | |
| 160 | | if (read_or_write) |
| 161 | | file->write(state->m_nvram, state->m_nvram.bytes()); |
| 162 | | else if (file) |
| 163 | | file->read(state->m_nvram, state->m_nvram.bytes()); |
| 164 | | else |
| 165 | | { |
| 166 | | state->m_nvram_init_count = 1; |
| 167 | | } |
| 168 | | } |
| 169 | | |
| 170 | | |
| 171 | | |
| 172 | 150 | static ADDRESS_MAP_START( mjkjidai_map, AS_PROGRAM, 8, mjkjidai_state ) |
| 173 | 151 | AM_RANGE(0x0000, 0x7fff) AM_ROM |
| 174 | 152 | AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1") |
| 175 | 153 | AM_RANGE(0xc000, 0xcfff) AM_RAM |
| 176 | | AM_RANGE(0xd000, 0xdfff) AM_RAM AM_SHARE("nvram") // cleared and initialized on startup if bit 6 if port 00 is 0 |
| 154 | AM_RANGE(0xd000, 0xdfff) AM_RAM AM_SHARE("nvram") // cleared and initialized on startup if bit 6 of port 00 is 0 |
| 177 | 155 | AM_RANGE(0xe000, 0xe01f) AM_RAM AM_SHARE("spriteram1") // shared with tilemap ram |
| 178 | 156 | AM_RANGE(0xe800, 0xe81f) AM_RAM AM_SHARE("spriteram2") // shared with tilemap ram |
| 179 | 157 | AM_RANGE(0xf000, 0xf01f) AM_RAM AM_SHARE("spriteram3") // shared with tilemap ram |
| r29217 | r29218 | |
| 385 | 363 | MCFG_CPU_IO_MAP(mjkjidai_io_map) |
| 386 | 364 | MCFG_CPU_VBLANK_INT_DRIVER("screen", mjkjidai_state, vblank_irq) |
| 387 | 365 | |
| 388 | | MCFG_NVRAM_HANDLER(mjkjidai) |
| 366 | MCFG_NVRAM_ADD_NO_FILL("nvram") |
| 389 | 367 | |
| 390 | 368 | /* video hardware */ |
| 391 | 369 | MCFG_SCREEN_ADD("screen", RASTER) |
| r29217 | r29218 | |
| 442 | 420 | |
| 443 | 421 | ROM_REGION( 0x8000, "adpcm", 0 ) /* ADPCM samples */ |
| 444 | 422 | ROM_LOAD( "mkj-40.14c", 0x00000, 0x8000, CRC(4d8fcc4a) SHA1(24c2b8031367035c89c6649a084bce0714f3e8d4) ) |
| 423 | |
| 424 | ROM_REGION( 0x1000, "nvram", 0 ) /* preformatted NVRAM */ |
| 425 | ROM_LOAD( "default.nv", 0x00000, 0x1000, CRC(eccc0263) SHA1(679010f096536e8bb572551e9d0776cad72145e2) ) |
| 445 | 426 | ROM_END |
| 446 | 427 | |
| 447 | 428 | |
trunk/src/mame/drivers/3do.c
| r29217 | r29218 | |
| 98 | 98 | #include "imagedev/chd_cd.h" |
| 99 | 99 | #include "cpu/arm/arm.h" |
| 100 | 100 | #include "cpu/arm7/arm7.h" |
| 101 | | #include "mcfglgcy.h" |
| 102 | 101 | |
| 103 | 102 | |
| 104 | | |
| 105 | 103 | #define X2_CLOCK_PAL 59000000 |
| 106 | 104 | #define X2_CLOCK_NTSC 49090000 |
| 107 | 105 | #define X601_CLOCK XTAL_16_9344MHz |
| r29217 | r29218 | |
| 135 | 133 | void _3do_state::machine_start() |
| 136 | 134 | { |
| 137 | 135 | m_bank2->set_base(memregion("user1")->base()); |
| 136 | m_nvram->set_base(&m_nvmem, sizeof(m_nvmem)); |
| 138 | 137 | |
| 139 | 138 | /* configure overlay */ |
| 140 | 139 | m_bank1->configure_entry(0, m_dram); |
| r29217 | r29218 | |
| 159 | 158 | NULL |
| 160 | 159 | }; |
| 161 | 160 | |
| 162 | | static NVRAM_HANDLER( _3do ) |
| 163 | | { |
| 164 | | _3do_state *state = machine.driver_data<_3do_state>(); |
| 165 | | UINT8 *nvram = state->m_nvram; |
| 166 | 161 | |
| 167 | | if (read_or_write) |
| 168 | | file->write(nvram,0x8000); |
| 169 | | else |
| 170 | | { |
| 171 | | if (file) |
| 172 | | file->read(nvram,0x8000); |
| 173 | | else |
| 174 | | { |
| 175 | | /* fill in the default values */ |
| 176 | | memset(nvram,0xff,0x8000); |
| 177 | | } |
| 178 | | } |
| 179 | | } |
| 180 | | |
| 181 | 162 | static MACHINE_CONFIG_START( 3do, _3do_state ) |
| 182 | 163 | |
| 183 | 164 | /* Basic machine hardware */ |
| 184 | 165 | MCFG_CPU_ADD( "maincpu", ARM7_BE, XTAL_50MHz/4 ) |
| 185 | 166 | MCFG_CPU_PROGRAM_MAP( 3do_mem) |
| 186 | 167 | |
| 187 | | MCFG_NVRAM_HANDLER(_3do) |
| 168 | MCFG_NVRAM_ADD_1FILL("nvram") |
| 188 | 169 | |
| 189 | 170 | MCFG_TIMER_DRIVER_ADD_PERIODIC("timer_x16", _3do_state, timer_x16_cb, attotime::from_hz(12000)) // TODO: timing |
| 190 | 171 | |
| r29217 | r29218 | |
| 204 | 185 | MCFG_CPU_ADD("maincpu", ARM7_BE, XTAL_50MHz/4 ) |
| 205 | 186 | MCFG_CPU_PROGRAM_MAP( 3do_mem) |
| 206 | 187 | |
| 207 | | MCFG_NVRAM_HANDLER(_3do) |
| 188 | MCFG_NVRAM_ADD_1FILL("nvram") |
| 208 | 189 | |
| 209 | 190 | MCFG_TIMER_DRIVER_ADD_PERIODIC("timer_x16", _3do_state, timer_x16_cb, attotime::from_hz(12000)) // TODO: timing |
| 210 | 191 | |