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r29209 Thursday 3rd April, 2014 at 06:14:04 UTC by Miodrag Milanović
Moved things to driver state, too coupled right now to make a proper device (nw)
[src/mess/includes]swtpc09.h
[src/mess/machine]swtpc09.c

trunk/src/mess/machine/swtpc09.c
r29208r29209
2424#define LOG(x)   do { if (VERBOSE) logerror x; } while (0)
2525
2626
27/* channel_data structure holds info about each 6844 DMA channel */
28typedef struct m6844_channel_data
29{
30   int active;
31   int address;
32   int counter;
33   UINT8 control;
34   int start_address;
35   int start_counter;
36} m6844_channel_data;
37
38/* 6844 description */
39static m6844_channel_data m6844_channel[4];
40static UINT8 m6844_priority;
41static UINT8 m6844_interrupt;
42static UINT8 m6844_chain;
43
4427/******* MC6840 PTM on MPID Board *******/
4528/* 6840 PTM interface */
4629const ptm6840_interface swtpc09_6840_intf =
r29208r29209
206189
207190    offset = (m_fdc_dma_address_reg & 0x0f)<<16;
208191
209   if (m6844_channel[0].active == 1)  //active dma transfer
192   if (m_m6844_channel[0].active == 1)  //active dma transfer
210193   {
211      if (!(m6844_channel[0].control & 0x01))  // dma write to memory
194      if (!(m_m6844_channel[0].control & 0x01))  // dma write to memory
212195      {
213196         UINT8 data = m_fdc->data_r(space, 0);
214197
215         LOG(("swtpc09_dma_write_mem %05X %02X\n", m6844_channel[0].address + offset, data));
216         RAM[m6844_channel[0].address + offset] = data;
198         LOG(("swtpc09_dma_write_mem %05X %02X\n", m_m6844_channel[0].address + offset, data));
199         RAM[m_m6844_channel[0].address + offset] = data;
217200      }
218201      else
219202      {
220         UINT8 data = RAM[m6844_channel[0].address + offset];
203         UINT8 data = RAM[m_m6844_channel[0].address + offset];
221204
222205         m_fdc->data_w(space, 0, data);
223         //LOG(("swtpc09_dma_read_mem %04X %02X\n", m6844_channel[0].address, data));
206         //LOG(("swtpc09_dma_read_mem %04X %02X\n", m_m6844_channel[0].address, data));
224207      }
225208
226      m6844_channel[0].address++;
227      m6844_channel[0].counter--;
209      m_m6844_channel[0].address++;
210      m_m6844_channel[0].counter--;
228211
229      if (m6844_channel[0].counter == 0)    // dma transfer has finished
212      if (m_m6844_channel[0].counter == 0)    // dma transfer has finished
230213      {
231            m6844_channel[0].control |= 0x80; // set dend flag
232            if (m6844_interrupt & 0x01)       // interrupt for channel 0 is enabled?
214            m_m6844_channel[0].control |= 0x80; // set dend flag
215            if (m_m6844_interrupt & 0x01)       // interrupt for channel 0 is enabled?
233216            {
234              m6844_interrupt   |= 0x80;      // set bit 7 to indicate active interrupt
217              m_m6844_interrupt   |= 0x80;      // set bit 7 to indicate active interrupt
235218                swtpc09_irq_handler(DMAC_IRQ, ASSERT_LINE);
236219          }
237220      }
r29208r29209
630613    {
631614        if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2)   // if DMF2 conroller this is the map
632615        {
633            mem.install_legacy_readwrite_handler(logical_address+0x000, logical_address+0x01f, FUNC(m6844_r), FUNC(m6844_w));
616            mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
634617            mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
635618           mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
636619           mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
r29208r29209
640623       }
641624        else if (m_system_type == FLEX_DC4_PIAIDE)   // 2k ram for piaide on s09 board
642625        {
643            //mem.install_legacy_readwrite_handler(logical_address+0x000, logical_address+0x01f, FUNC(m6844_r), FUNC(m6844_w));
644            //mem.install_legacy_readwrite_handler(*fdc, logical_address+0x020, logical_address+0x023, 0, 0, FUNC(wd17xx_r), FUNC(wd17xx_w));
626            //mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
627            //mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
645628           //mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
646629           //mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
647630            mem.install_ram(logical_address+0x000, logical_address+0x7ff, &RAM[0xf000]);
r29208r29209
649632            mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
650633       }
651634       else    // assume DMF3 controller
652        {
653            mem.install_legacy_readwrite_handler(logical_address+0x000, logical_address+0x01f, FUNC(m6844_r), FUNC(m6844_w));
635        {           
636         mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
654637            mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
655638           mem.install_readwrite_handler(logical_address+0x024, logical_address+0x024, read8_delegate(FUNC(swtpc09_state::dmf3_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_control_reg_w),this));
656639           mem.install_readwrite_handler(logical_address+0x025, logical_address+0x025, read8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_w),this));
r29208r29209
688671
689672/*  MC6844 DMA controller I/O */
690673
691READ8_HANDLER( m6844_r )
674READ8_MEMBER( swtpc09_state::m6844_r )
692675{
693676   UINT8 result = 0;
694   swtpc09_state *state = space.machine().driver_data<swtpc09_state>();
695677
696678
697679   /* switch off the offset we were given */
r29208r29209
702684      case 0x04:
703685      case 0x08:
704686      case 0x0c:
705         result = m6844_channel[offset / 4].address >> 8;
687         result = m_m6844_channel[offset / 4].address >> 8;
706688         break;
707689
708690      /* lower byte of address */
r29208r29209
710692      case 0x05:
711693      case 0x09:
712694      case 0x0d:
713         result = m6844_channel[offset / 4].address & 0xff;
695         result = m_m6844_channel[offset / 4].address & 0xff;
714696         break;
715697
716698      /* upper byte of counter */
r29208r29209
718700      case 0x06:
719701      case 0x0a:
720702      case 0x0e:
721         result = m6844_channel[offset / 4].counter >> 8;
703         result = m_m6844_channel[offset / 4].counter >> 8;
722704         break;
723705
724706      /* lower byte of counter */
r29208r29209
726708      case 0x07:
727709      case 0x0b:
728710      case 0x0f:
729         result = m6844_channel[offset / 4].counter & 0xff;
711         result = m_m6844_channel[offset / 4].counter & 0xff;
730712         break;
731713
732714      /* channel control */
r29208r29209
734716      case 0x11:
735717      case 0x12:
736718      case 0x13:
737         result = m6844_channel[offset - 0x10].control;
719         result = m_m6844_channel[offset - 0x10].control;
738720
739721         /* a read here clears the DMA end flag */
740         m6844_channel[offset - 0x10].control &= ~0x80;
741            if (m6844_interrupt && 0x80) // if interrupt is active, then clear
722         m_m6844_channel[offset - 0x10].control &= ~0x80;
723            if (m_m6844_interrupt && 0x80) // if interrupt is active, then clear
742724            {
743                state->swtpc09_irq_handler(0x01, CLEAR_LINE);
744             m6844_interrupt &= 0x7f;  // clear interrupt indication bit 7
725                swtpc09_irq_handler(0x01, CLEAR_LINE);
726             m_m6844_interrupt &= 0x7f;  // clear interrupt indication bit 7
745727             LOG(("swtpc09_6844_r interrupt cleared \n"));
746728         }
747729         break;
748730
749731      /* priority control */
750732      case 0x14:
751         result = m6844_priority;
733         result = m_m6844_priority;
752734         break;
753735
754736      /* interrupt control */
755737      case 0x15:
756         result = m6844_interrupt;
738         result = m_m6844_interrupt;
757739         break;
758740
759741      /* chaining control */
760742      case 0x16:
761         result = m6844_chain;
743         result = m_m6844_chain;
762744         break;
763745
764746      /* 0x17-0x1f not used */
r29208r29209
766748   }
767749    //LOG(("swtpc09_6844_r %02X %02X\n", offset, result & 0xff));
768750
769    if (state->m_system_type == UNIFLEX_DMF2 || state->m_system_type == FLEX_DMF2)   // if DMF2 controller data bus is inverted to 6844
751    if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2)   // if DMF2 controller data bus is inverted to 6844
770752    {
771753        return ~result & 0xff;
772754   }
r29208r29209
777759}
778760
779761
780WRITE8_HANDLER( m6844_w )
762WRITE8_MEMBER( swtpc09_state::m6844_w )
781763{
782764   int i;
783   swtpc09_state *state = space.machine().driver_data<swtpc09_state>();
784765
785    if (state->m_system_type == UNIFLEX_DMF2 || state->m_system_type == FLEX_DMF2)   // if DMF2 controller data bus is inverted to 6844
766    if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2)   // if DMF2 controller data bus is inverted to 6844
786767        data = ~data & 0xff;
787768
788769    LOG(("swtpc09_6844_w %02X %02X\n", offset, data));
r29208r29209
794775      case 0x04:
795776      case 0x08:
796777      case 0x0c:
797         m6844_channel[offset / 4].address = (m6844_channel[offset / 4].address & 0xff) | (data << 8);
778         m_m6844_channel[offset / 4].address = (m_m6844_channel[offset / 4].address & 0xff) | (data << 8);
798779         break;
799780
800781      /* lower byte of address */
r29208r29209
802783      case 0x05:
803784      case 0x09:
804785      case 0x0d:
805         m6844_channel[offset / 4].address = (m6844_channel[offset / 4].address & 0xff00) | (data & 0xff);
786         m_m6844_channel[offset / 4].address = (m_m6844_channel[offset / 4].address & 0xff00) | (data & 0xff);
806787         break;
807788
808789      /* upper byte of counter */
r29208r29209
810791      case 0x06:
811792      case 0x0a:
812793      case 0x0e:
813         m6844_channel[offset / 4].counter = (m6844_channel[offset / 4].counter & 0xff) | (data << 8);
794         m_m6844_channel[offset / 4].counter = (m_m6844_channel[offset / 4].counter & 0xff) | (data << 8);
814795         break;
815796
816797      /* lower byte of counter */
r29208r29209
818799      case 0x07:
819800      case 0x0b:
820801      case 0x0f:
821         m6844_channel[offset / 4].counter = (m6844_channel[offset / 4].counter & 0xff00) | (data & 0xff);
802         m_m6844_channel[offset / 4].counter = (m_m6844_channel[offset / 4].counter & 0xff00) | (data & 0xff);
822803         break;
823804
824805      /* channel control */
r29208r29209
826807      case 0x11:
827808      case 0x12:
828809      case 0x13:
829         m6844_channel[offset - 0x10].control = (m6844_channel[offset - 0x10].control & 0xc0) | (data & 0x3f);
810         m_m6844_channel[offset - 0x10].control = (m_m6844_channel[offset - 0x10].control & 0xc0) | (data & 0x3f);
830811         break;
831812
832813      /* priority control */
833814      case 0x14:
834         m6844_priority = data;
815         m_m6844_priority = data;
835816
836817         /* update each channel */
837818         for (i = 0; i < 4; i++)
838819         {
839820            /* if we're going active... */
840            if (!m6844_channel[i].active && (data & (1 << i)))
821            if (!m_m6844_channel[i].active && (data & (1 << i)))
841822            {
842823               /* mark us active */
843               m6844_channel[i].active = 1;
824               m_m6844_channel[i].active = 1;
844825               LOG(("swtpc09_dma_channel active %02X\n", i));
845826
846827               /* set the DMA busy bit and clear the DMA end bit */
847               m6844_channel[i].control |= 0x40;
848               m6844_channel[i].control &= ~0x80;
828               m_m6844_channel[i].control |= 0x40;
829               m_m6844_channel[i].control &= ~0x80;
849830
850831               /* set the starting address, counter, and time */
851               m6844_channel[i].start_address = m6844_channel[i].address;
852               m6844_channel[i].start_counter = m6844_channel[i].counter;
832               m_m6844_channel[i].start_address = m_m6844_channel[i].address;
833               m_m6844_channel[i].start_counter = m_m6844_channel[i].counter;
853834
854835
855836               /* generate and play the sample */
r29208r29209
857838            }
858839
859840            /* if we're going inactive... */
860            else if (m6844_channel[i].active && !(data & (1 << i)))
841            else if (m_m6844_channel[i].active && !(data & (1 << i)))
861842            {
862843               /* mark us inactive */
863               m6844_channel[i].active = 0;
844               m_m6844_channel[i].active = 0;
864845            }
865846         }
866847         break;
867848
868849      /* interrupt control */
869850      case 0x15:
870         m6844_interrupt = (m6844_interrupt & 0x80) | (data & 0x7f);
871            LOG(("swtpc09_m6844_interrupt_w %02X\n", m6844_interrupt));
851         m_m6844_interrupt = (m_m6844_interrupt & 0x80) | (data & 0x7f);
852            LOG(("swtpc09_m_m6844_interrupt_w %02X\n", m_m6844_interrupt));
872853         break;
873854
874855      /* chaining control */
875856      case 0x16:
876         m6844_chain = data;
857         m_m6844_chain = data;
877858         break;
878859
879860      /* 0x17-0x1f not used */
r29208r29209
895876   /* reset the 6844 */
896877   for (i = 0; i < 4; i++)
897878   {
898      m6844_channel[i].active = 0;
899      m6844_channel[i].control = 0x00;
879      m_m6844_channel[i].active = 0;
880      m_m6844_channel[i].control = 0x00;
900881   }
901   m6844_priority = 0x00;
902   m6844_interrupt = 0x00;
903   m6844_chain = 0x00;
882   m_m6844_priority = 0x00;
883   m_m6844_interrupt = 0x00;
884   m_m6844_chain = 0x00;
904885
905886}
906887
r29208r29209
917898   /* reset the 6844 */
918899   for (i = 0; i < 4; i++)
919900   {
920      m6844_channel[i].active = 0;
921      m6844_channel[i].control = 0x00;
901      m_m6844_channel[i].active = 0;
902      m_m6844_channel[i].control = 0x00;
922903   }
923   m6844_priority = 0x00;
924   m6844_interrupt = 0x00;
925   m6844_chain = 0x00;
904   m_m6844_priority = 0x00;
905   m_m6844_interrupt = 0x00;
906   m_m6844_chain = 0x00;
926907
927908}
928909
r29208r29209
939920   /* reset the 6844 */
940921   for (i = 0; i < 4; i++)
941922   {
942      m6844_channel[i].active = 0;
943      m6844_channel[i].control = 0x00;
923      m_m6844_channel[i].active = 0;
924      m_m6844_channel[i].control = 0x00;
944925   }
945   m6844_priority = 0x00;
946   m6844_interrupt = 0x00;
947   m6844_chain = 0x00;
926   m_m6844_priority = 0x00;
927   m_m6844_interrupt = 0x00;
928   m_m6844_chain = 0x00;
948929
949930}
950931
r29208r29209
963944   /* reset the 6844 */
964945   for (i = 0; i < 4; i++)
965946   {
966      m6844_channel[i].active = 0;
967      m6844_channel[i].control = 0x00;
947      m_m6844_channel[i].active = 0;
948      m_m6844_channel[i].control = 0x00;
968949   }
969   m6844_priority = 0x00;
970   m6844_interrupt = 0x00;
971   m6844_chain = 0x00;
950   m_m6844_priority = 0x00;
951   m_m6844_interrupt = 0x00;
952   m_m6844_chain = 0x00;
972953
973954}
trunk/src/mess/includes/swtpc09.h
r29208r29209
112112   UINT8 m_piaide_portb;
113113   UINT8 m_active_interrupt;
114114   UINT8 m_interrupt;
115   
116   
117   // TODO: move this in proper device
118   
119   /* channel_data structure holds info about each 6844 DMA channel */
120   typedef struct m6844_channel_data
121   {
122      int active;
123      int address;
124      int counter;
125      UINT8 control;
126      int start_address;
127      int start_counter;
128   } m6844_channel_data;
115129
130   /* 6844 description */
131   m6844_channel_data m_m6844_channel[4];
132   UINT8 m_m6844_priority;
133   UINT8 m_m6844_interrupt;
134   UINT8 m_m6844_chain;
135   DECLARE_READ8_MEMBER ( m6844_r );
136   DECLARE_WRITE8_MEMBER ( m6844_w );
137
116138};
117139
118140/*----------- defined in machine/swtpc09.c -----------*/
r29208r29209
120142extern const wd17xx_interface swtpc09_wd17xx_interface;
121143extern const ptm6840_interface swtpc09_6840_intf;
122144
123
124READ8_HANDLER ( m6844_r );
125WRITE8_HANDLER ( m6844_w );
126
127
128145#endif /* swtpc09_H_ */
129146
130147

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