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r29183 Wednesday 2nd April, 2014 at 13:17:56 UTC by Curt Coder
upd7220: devcb2 and delegates. (nw)

[src/emu/bus/wangpc]	tig.c tig.h
[src/emu/video]	upd7220.c upd7220.h
[src/mess/drivers]	a5105.c apc.c compis.c dmv.c if800.c mz3500.c mz6500.c pc9801.c qx10.c vt240.c
[src/mess/includes]	compis.h mikromik.h
[src/mess/video]	mikromik.c

trunk/src/emu/video/upd7220.c

r29182	r29183
182	182	}
183	183
184	184
185		//-------------------------------------------------
186		//  device_config_complete - perform any
187		//  operations now that the configuration is
188		//  complete
189		//-------------------------------------------------
190	185
191		void upd7220_device::device_config_complete()
192		{
193		// inherit a copy of the static data
194		const upd7220_interface *intf = reinterpret_cast<const upd7220_interface *>(static_config());
195		if (intf != NULL)
196		*static_cast<upd7220_interface *>(this) = *intf;
197
198		// or initialize to defaults if none provided
199		else
200		{
201		memset(&m_out_drq_cb, 0, sizeof(m_out_drq_cb));
202		memset(&m_out_hsync_cb, 0, sizeof(m_out_hsync_cb));
203		memset(&m_out_vsync_cb, 0, sizeof(m_out_vsync_cb));
204		memset(&m_out_blank_cb, 0, sizeof(m_out_blank_cb));
205		}
206		}
207
208
209
210	186	//**************************************************************************
211	187	//  INLINE HELPERS
212	188	//**************************************************************************
r29182	r29183
681	657	//  upd7220_device - constructor
682	658	//-------------------------------------------------
683	659
684		upd7220_device::upd7220_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
685		: device_t(mconfig, UPD7220, "uPD7220", tag, owner, clock, "upd7220", __FILE__),
686		device_memory_interface(mconfig, *this),
687		device_video_interface(mconfig, *this),
688		m_mask(0),
689		m_pitch(0),
690		m_ead(0),
691		m_dad(0),
692		m_lad(0),
693		m_ra_addr(0),
694		m_sr(UPD7220_SR_FIFO_EMPTY),
695		m_cr(0),
696		m_param_ptr(0),
697		m_fifo_ptr(-1),
698		m_fifo_dir(0),
699		m_mode(0),
700		m_draw_mode(0),
701		m_de(0),
702		m_m(0),
703		m_aw(0),
704		m_al(0),
705		m_vs(0),
706		m_vfp(0),
707		m_vbp(0),
708		m_hs(0),
709		m_hfp(0),
710		m_hbp(0),
711		m_dc(0),
712		m_sc(0),
713		m_br(0),
714		m_ctop(0),
715		m_cbot(0),
716		m_lr(0),
717		m_disp(0),
718		m_gchr(0),
719		m_bitmap_mod(0),
720		m_space_config("videoram", ENDIANNESS_LITTLE, 8, 18, 0, NULL, *ADDRESS_MAP_NAME(upd7220_vram))
	660	upd7220_device::upd7220_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	661	device_t(mconfig, UPD7220, "uPD7220", tag, owner, clock, "upd7220", __FILE__),
	662	device_memory_interface(mconfig, *this),
	663	device_video_interface(mconfig, *this),
	664	m_write_drq(*this),
	665	m_write_hsync(*this),
	666	m_write_vsync(*this),
	667	m_write_blank(*this),
	668	m_mask(0),
	669	m_pitch(0),
	670	m_ead(0),
	671	m_dad(0),
	672	m_lad(0),
	673	m_ra_addr(0),
	674	m_sr(UPD7220_SR_FIFO_EMPTY),
	675	m_cr(0),
	676	m_param_ptr(0),
	677	m_fifo_ptr(-1),
	678	m_fifo_dir(0),
	679	m_mode(0),
	680	m_draw_mode(0),
	681	m_de(0),
	682	m_m(0),
	683	m_aw(0),
	684	m_al(0),
	685	m_vs(0),
	686	m_vfp(0),
	687	m_vbp(0),
	688	m_hs(0),
	689	m_hfp(0),
	690	m_hbp(0),
	691	m_dc(0),
	692	m_sc(0),
	693	m_br(0),
	694	m_ctop(0),
	695	m_cbot(0),
	696	m_lr(0),
	697	m_disp(0),
	698	m_gchr(0),
	699	m_bitmap_mod(0),
	700	m_space_config("videoram", ENDIANNESS_LITTLE, 8, 18, 0, NULL, *ADDRESS_MAP_NAME(upd7220_vram))
721	701	{
722	702	for (int i = 0; i < 16; i++)
723	703	{
r29182	r29183
748	728
749	729	void upd7220_device::device_start()
750	730	{
	731	// resolve callbacks
	732	m_display_cb.bind_relative_to(*owner());
	733	m_draw_text_cb.bind_relative_to(*owner());
	734
	735	m_write_drq.resolve_safe();
	736	m_write_hsync.resolve_safe();
	737	m_write_vsync.resolve_safe();
	738	m_write_blank.resolve_safe();
	739
751	740	// allocate timers
752	741	m_vsync_timer = timer_alloc(TIMER_VSYNC);
753	742	m_hsync_timer = timer_alloc(TIMER_HSYNC);
754	743	m_blank_timer = timer_alloc(TIMER_BLANK);
755	744
756		// resolve callbacks
757		m_out_drq_func.resolve(m_out_drq_cb, *this);
758		m_out_hsync_func.resolve(m_out_hsync_cb, *this);
759		m_out_vsync_func.resolve(m_out_vsync_cb, *this);
760		m_out_blank_func.resolve(m_out_blank_cb, *this);
761
762	745	// register for state saving
763	746	save_item(NAME(m_ra));
764	747	save_item(NAME(m_sr));
r29182	r29183
795	778
796	779	void upd7220_device::device_reset()
797	780	{
798		m_out_drq_func(CLEAR_LINE);
	781	m_write_drq(CLEAR_LINE);
799	782	}
800	783
801	784
r29182	r29183
817	800	m_sr &= ~UPD7220_SR_HBLANK_ACTIVE;
818	801	}
819	802
820		m_out_hsync_func(param);
	803	m_write_hsync(param);
821	804
822	805	update_hsync_timer(param);
823	806	break;
r29182	r29183
832	815	m_sr &= ~UPD7220_SR_VSYNC_ACTIVE;
833	816	}
834	817
835		m_out_vsync_func(param);
	818	m_write_vsync(param);
836	819
837	820	update_vsync_timer(param);
838	821	break;
r29182	r29183
847	830	m_sr &= ~UPD7220_SR_HBLANK_ACTIVE;
848	831	}
849	832
850		m_out_blank_func(param);
	833	m_write_blank(param);
851	834
852	835	update_blank_timer(param);
853	836	break;
r29182	r29183
1556	1539	{
1557	1540	addr = sad + (y * m_pitch);
1558	1541
1559		if (m_draw_text_cb)
1560		m_draw_text_cb(this, bitmap, addr, y, wd, m_pitch, m_lr, m_dc, m_ead);
	1542	if (!m_draw_text_cb.isnull())
	1543	m_draw_text_cb(bitmap, addr, y, wd, m_pitch, m_lr, m_dc, m_ead);
1561	1544	}
1562	1545
1563	1546	sy = y + 1;
r29182	r29183
1576	1559	for (sx = 0; sx < 80; sx++)
1577	1560	{
1578	1561	if((sx << 3) < m_aw * 16 && y < m_al)
1579		m_display_cb(this, bitmap, y, sx << 3, addr);
	1562	m_display_cb(bitmap, y, sx << 3, addr);
1580	1563
1581	1564	addr+= wd + 1;
1582	1565	}
r29182	r29183
1613	1596	Dragon Buster (PC-98xx) contradicts with Xevious with regards of the pitch tho ... */
1614	1597	addr = ((sad << 1) & 0x3ffff) + (y * m_pitch * 2);
1615	1598
1616		if (m_display_cb)
	1599	if (!m_display_cb.isnull())
1617	1600	draw_graphics_line(bitmap, addr, y + bsy/((m_pitch == 40)+1), wd);
1618	1601	}
1619	1602	}
r29182	r29183
1627	1610	{
1628	1611	addr = (sad & 0x3ffff) + ((y / m_lr) * m_pitch);
1629	1612
1630		if (m_draw_text_cb)
1631		m_draw_text_cb(this, bitmap, addr, (y + tsy) / m_lr, wd, m_pitch, m_lr, m_dc, m_ead);
	1613	if (!m_draw_text_cb.isnull())
	1614	m_draw_text_cb(bitmap, addr, (y + tsy) / m_lr, wd, m_pitch, m_lr, m_dc, m_ead);
1632	1615	}
1633	1616	}
1634	1617	}

trunk/src/emu/video/upd7220.h

r29182	r29183
40	40
41	41
42	42	//**************************************************************************
43		//  MACROS / CONSTANTS
	43	//  INTERFACE CONFIGURATION MACROS
44	44	//**************************************************************************
45	45
	46	#define UPD7220_DISPLAY_PIXELS_MEMBER(_name) void _name(bitmap_rgb32 &bitmap, int y, int x, UINT32 address)
	47	#define UPD7220_DRAW_TEXT_LINE_MEMBER(_name) void _name(bitmap_rgb32 &bitmap, UINT32 addr, int y, int wd, int pitch, int lr, int cursor_on, int cursor_addr)
46	48
47	49
	50	#define MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(_class, _method) \
	51	upd7220_device::static_set_display_pixels_callback(*device, upd7220_display_pixels_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
48	52
49		//**************************************************************************
50		//  INTERFACE CONFIGURATION MACROS
51		//**************************************************************************
	53	#define MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(_class, _method) \
	54	upd7220_device::static_set_draw_text_callback(*device, upd7220_draw_text_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
52	55
53		#define MCFG_UPD7220_ADD(_tag, _clock, _config, _map) \
54		MCFG_DEVICE_ADD(_tag, UPD7220, _clock) \
55		MCFG_DEVICE_CONFIG(_config) \
56		MCFG_DEVICE_ADDRESS_MAP(AS_0, _map)
	56	#define MCFG_UPD7220_DRQ_CALLBACK(_write) \
	57	devcb = &upd7220_device::set_drq_wr_callback(*device, DEVCB2_##_write);
57	58
58		#define UPD7220_INTERFACE(name) \
59		const upd7220_interface (name) =
	59	#define MCFG_UPD7220_HSYNC_CALLBACK(_write) \
	60	devcb = &upd7220_device::set_hsync_wr_callback(*device, DEVCB2_##_write);
60	61
	62	#define MCFG_UPD7220_VSYNC_CALLBACK(_write) \
	63	devcb = &upd7220_device::set_vsync_wr_callback(*device, DEVCB2_##_write);
61	64
	65	#define MCFG_UPD7220_BLANK_CALLBACK(_write) \
	66	devcb = &upd7220_device::set_blank_wr_callback(*device, DEVCB2_##_write);
62	67
	68
	69
63	70	//**************************************************************************
64	71	//  TYPE DEFINITIONS
65	72	//**************************************************************************
66	73
67		typedef void (*upd7220_display_pixels_func)(device_t *device, bitmap_rgb32 &bitmap, int y, int x, UINT32 address);
68		#define UPD7220_DISPLAY_PIXELS(name) void name(device_t *device, bitmap_rgb32 &bitmap, int y, int x, UINT32 address)
	74	typedef device_delegate<void (bitmap_rgb32 &bitmap, int y, int x, UINT32 address)> upd7220_display_pixels_delegate;
	75	typedef device_delegate<void (bitmap_rgb32 &bitmap, UINT32 addr, int y, int wd, int pitch, int lr, int cursor_on, int cursor_addr)> upd7220_draw_text_delegate;
69	76
70		typedef void (*upd7220_draw_text_line)(device_t *device, bitmap_rgb32 &bitmap, UINT32 addr, int y, int wd, int pitch, int lr, int cursor_on, int cursor_addr);
71		#define UPD7220_DRAW_TEXT_LINE(name) void name(device_t *device, bitmap_rgb32 &bitmap, UINT32 addr, int y, int wd, int pitch, int lr, int cursor_on, int cursor_addr)
72	77
73
74		// ======================> upd7220_interface
75
76		struct upd7220_interface
77		{
78		upd7220_display_pixels_func m_display_cb;
79		upd7220_draw_text_line m_draw_text_cb;
80
81		devcb_write_line        m_out_drq_cb;
82		devcb_write_line        m_out_hsync_cb;
83		devcb_write_line        m_out_vsync_cb;
84		devcb_write_line        m_out_blank_cb;
85		};
86
87	78	// ======================> upd7220_device
88	79
89	80	class upd7220_device :  public device_t,
90	81	public device_memory_interface,
91		public device_video_interface,
92		public upd7220_interface
	82	public device_video_interface
93	83	{
94	84	public:
95	85	// construction/destruction
96	86	upd7220_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
97	87
	88	static void static_set_display_pixels_callback(device_t &device, upd7220_display_pixels_delegate callback) { downcast<upd7220_device &>(device).m_display_cb = callback; }
	89	static void static_set_draw_text_callback(device_t &device, upd7220_draw_text_delegate callback) { downcast<upd7220_device &>(device).m_draw_text_cb = callback; }
	90
	91	template<class _Object> static devcb2_base &set_drq_wr_callback(device_t &device, _Object object) { return downcast<upd7220_device &>(device).m_write_drq.set_callback(object); }
	92	template<class _Object> static devcb2_base &set_hsync_wr_callback(device_t &device, _Object object) { return downcast<upd7220_device &>(device).m_write_hsync.set_callback(object); }
	93	template<class _Object> static devcb2_base &set_vsync_wr_callback(device_t &device, _Object object) { return downcast<upd7220_device &>(device).m_write_vsync.set_callback(object); }
	94	template<class _Object> static devcb2_base &set_blank_wr_callback(device_t &device, _Object object) { return downcast<upd7220_device &>(device).m_write_blank.set_callback(object); }
	95
98	96	DECLARE_READ8_MEMBER( read );
99	97	DECLARE_WRITE8_MEMBER( write );
100	98
r29182	r29183
117	115	virtual void device_start();
118	116	virtual void device_reset();
119	117	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
120		virtual void device_config_complete();
121	118
122	119	private:
123		static const device_timer_id TIMER_VSYNC = 0;
124		static const device_timer_id TIMER_HSYNC = 1;
125		static const device_timer_id TIMER_BLANK = 2;
	120	enum
	121	{
	122	TIMER_VSYNC,
	123	TIMER_HSYNC,
	124	TIMER_BLANK
	125	};
126	126
127	127	inline UINT8 readbyte(offs_t address);
128	128	inline void writebyte(offs_t address, UINT8 data);
r29182	r29183
153	153	void draw_graphics_line(bitmap_rgb32 &bitmap, UINT32 addr, int y, int wd);
154	154	void update_graphics(bitmap_rgb32 &bitmap, const rectangle &cliprect, int force_bitmap);
155	155
156		devcb_resolved_write_line   m_out_drq_func;
157		devcb_resolved_write_line   m_out_hsync_func;
158		devcb_resolved_write_line   m_out_vsync_func;
159		devcb_resolved_write_line   m_out_blank_func;
	156	upd7220_display_pixels_delegate      m_display_cb;
	157	upd7220_draw_text_delegate         m_draw_text_cb;
160	158
	159	devcb2_write_line   m_write_drq;
	160	devcb2_write_line   m_write_hsync;
	161	devcb2_write_line   m_write_vsync;
	162	devcb2_write_line   m_write_blank;
	163
161	164	UINT16 m_mask;                  // mask register
162	165	UINT8 m_pitch;                  // number of word addresses in display memory in the horizontal direction
163	166	UINT32 m_ead;                   // execute word address

trunk/src/emu/bus/wangpc/tig.c

r29182	r29183
89	89	AM_RANGE(0x4000, 0x7fff) AM_RAM // font memory
90	90	ADDRESS_MAP_END
91	91
92		static UPD7220_DRAW_TEXT_LINE( hgdc_display_text)
	92	UPD7220_DRAW_TEXT_LINE_MEMBER( wangpc_tig_device::hgdc_draw_text )
93	93	{
94	94	}
95	95
96		static UPD7220_INTERFACE( hgdc0_intf )
97		{
98		NULL,
99		hgdc_display_text,
100		DEVCB_NULL,
101		DEVCB_NULL,
102		DEVCB_NULL
103		};
104	96
105
106	97	//-------------------------------------------------
107	98	//  UPD7220_INTERFACE( hgdc1_intf )
108	99	//-------------------------------------------------
r29182	r29183
112	103	AM_RANGE(0x0000, 0xffff) AM_RAM // graphics memory
113	104	ADDRESS_MAP_END
114	105
115		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	106	UPD7220_DISPLAY_PIXELS_MEMBER( wangpc_tig_device::hgdc_display_pixels )
116	107	{
117	108	}
118	109
119		static UPD7220_INTERFACE( hgdc1_intf )
120		{
121		hgdc_display_pixels,
122		NULL,
123		DEVCB_NULL,
124		DEVCB_NULL,
125		DEVCB_NULL
126		};
127	110
128
129	111	//-------------------------------------------------
130	112	//  MACHINE_CONFIG_FRAGMENT( wangpc_tig )
131	113	//-------------------------------------------------
r29182	r29183
140	122
141	123	MCFG_PALETTE_ADD_MONOCHROME_GREEN_HIGHLIGHT("palette")
142	124
143		MCFG_UPD7220_ADD(UPD7720_0_TAG, XTAL_52_832MHz/28, hgdc0_intf, upd7220_0_map) // was /10?
	125	MCFG_DEVICE_ADD(UPD7720_0_TAG, UPD7220, XTAL_52_832MHz/28)
	126	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_0_map)
	127	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(wangpc_tig_device, hgdc_draw_text)
144	128	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
145		MCFG_UPD7220_ADD(UPD7720_1_TAG, XTAL_52_832MHz/28, hgdc1_intf, upd7220_1_map) // was /16?
	129
	130	MCFG_DEVICE_ADD(UPD7720_1_TAG, UPD7220, XTAL_52_832MHz/28)
	131	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
	132	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(wangpc_tig_device, hgdc_display_pixels)
146	133	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
147	134	MACHINE_CONFIG_END
148	135

trunk/src/emu/bus/wangpc/tig.h

r29182	r29183
38	38	virtual machine_config_constructor device_mconfig_additions() const;
39	39	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
40	40
	41	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
	42	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
	43
41	44	protected:
42	45	// device-level overrides
43	46	virtual void device_start();

trunk/src/mess/drivers/compis.c

r29182	r29183
453	453	//  UPD7220_INTERFACE( hgdc_intf )
454	454	//-------------------------------------------------
455	455
456		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	456	UPD7220_DISPLAY_PIXELS_MEMBER( compis_state::hgdc_display_pixels )
457	457	{
458		compis_state *state = device->machine().driver_data<compis_state>();
459		UINT8 i,gfx = state->m_video_ram[address];
460		const pen_t *pen = state->m_palette->pens();
	458	UINT8 i,gfx = m_video_ram[address];
	459	const pen_t *pen = m_palette->pens();
461	460
462	461	for(i=0; i<8; i++)
463	462	bitmap.pix32(y, x + i) = pen[BIT(gfx, i)];
464	463	}
465	464
466		static UPD7220_INTERFACE( hgdc_intf )
467		{
468		hgdc_display_pixels,
469		NULL,
470		DEVCB_NULL,
471		DEVCB_NULL,
472		DEVCB_NULL
473		};
474	465
475
476	466	//-------------------------------------------------
477	467	//  I80186_INTERFACE( cpu_intf )
478	468	//-------------------------------------------------
r29182	r29183
722	712	MCFG_SCREEN_SIZE(640, 400)
723	713	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 400-1)
724	714	MCFG_SCREEN_UPDATE_DEVICE("upd7220", upd7220_device, screen_update)
725		MCFG_UPD7220_ADD("upd7220", XTAL_4_433619MHz/2, hgdc_intf, upd7220_map) //unknown clock
	715
	716	MCFG_DEVICE_ADD("upd7220", UPD7220, XTAL_4_433619MHz/2) // unknown clock
	717	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
	718	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(compis_state, hgdc_display_pixels)
726	719	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
	720
727	721	MCFG_PALETTE_ADD_MONOCHROME_GREEN("palette")
728	722
729	723	// devices

trunk/src/mess/drivers/mz3500.c

r29182	r29183
97	97	// screen updates
98	98	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
99	99	DECLARE_PALETTE_INIT(mz3500);
	100	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
	101	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
	102
100	103	protected:
101	104	// driver_device overrides
102	105	virtual void machine_start();
r29182	r29183
137	140	(mirror of [5]?)
138	141	*/
139	142
140		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	143	UPD7220_DISPLAY_PIXELS_MEMBER( mz3500_state::hgdc_display_pixels )
141	144	{
142	145	// ...
143	146	}
144	147
145		static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
	148	UPD7220_DRAW_TEXT_LINE_MEMBER( mz3500_state::hgdc_draw_text )
146	149	{
147		mz3500_state *state = device->machine().driver_data<mz3500_state>();
148		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	150	const rgb_t *palette = m_palette->palette()->entry_list_raw();
149	151	int x;
150	152	int xi,yi;
151	153	int tile;
r29182	r29183
156	158	UINT8 hires;
157	159	UINT8 color_mode;
158	160
159		//  popmessage("%02x",state->m_crtc[6]);
	161	//  popmessage("%02x",m_crtc[6]);
160	162
161		color_mode = state->m_crtc[4] & 1;
162		width80 = (state->m_crtc[5] & 2) >> 1;
163		hires = (state->m_crtc[6] & 1);
	163	color_mode = m_crtc[4] & 1;
	164	width80 = (m_crtc[5] & 2) >> 1;
	165	hires = (m_crtc[6] & 1);
164	166	char_size = (hires) ? 16 : 8;
165	167
166	168	for( x = 0; x < pitch; x++ )
167	169	{
168		tile = (state->m_video_ram[((addr+x)*2) & 0x1fff] & 0xff);
169		attr = (state->m_video_ram[((addr+x)*2+1) & 0x3ffff] & 0x0f);
	170	tile = (m_video_ram[((addr+x)*2) & 0x1fff] & 0xff);
	171	attr = (m_video_ram[((addr+x)*2+1) & 0x3ffff] & 0x0f);
170	172
171	173	//if(hires)
172	174	//  tile <<= 1;
173	175
174	176	for( yi = 0; yi < lr; yi++)
175	177	{
176		tile_data = state->m_char_rom[((tile*16+yi) & 0xfff) | (hires*0x1000)];
	178	tile_data = m_char_rom[((tile*16+yi) & 0xfff) | (hires*0x1000)];
177	179
178	180	for( xi = 0; xi < 8; xi++)
179	181	{
r29182	r29183
234	236	return 0;
235	237	}
236	238
237
238
239		static UPD7220_INTERFACE( hgdc_1_intf )
240		{
241		NULL,
242		hgdc_draw_text,
243		DEVCB_NULL,
244		DEVCB_DEVICE_LINE_MEMBER("upd7220_gfx", upd7220_device, ext_sync_w),
245		DEVCB_NULL
246		};
247
248		static UPD7220_INTERFACE( hgdc_2_intf )
249		{
250		hgdc_display_pixels,
251		NULL,
252		DEVCB_NULL,
253		DEVCB_NULL,
254		DEVCB_NULL
255		};
256
257	239	READ8_MEMBER(mz3500_state::mz3500_ipl_r)
258	240	{
259	241	return m_ipl_rom[offset];
r29182	r29183
852	834	MCFG_FLOPPY_DRIVE_ADD("upd765a:2", mz3500_floppies, "525ssdd", floppy_image_device::default_floppy_formats)
853	835	MCFG_FLOPPY_DRIVE_ADD("upd765a:3", mz3500_floppies, "525ssdd", floppy_image_device::default_floppy_formats)
854	836
855		MCFG_UPD7220_ADD("upd7220_chr", MAIN_CLOCK/5, hgdc_1_intf, upd7220_1_map)
856		MCFG_UPD7220_ADD("upd7220_gfx", MAIN_CLOCK/5, hgdc_2_intf, upd7220_2_map)
	837	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, MAIN_CLOCK/5)
	838	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
	839	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(mz3500_state, hgdc_draw_text)
	840	MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_gfx", upd7220_device, ext_sync_w))
857	841
	842	MCFG_DEVICE_ADD("upd7220_gfx", UPD7220, MAIN_CLOCK/5)
	843	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
	844	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(mz3500_state, hgdc_display_pixels)
	845
858	846	/* video hardware */
859	847	MCFG_SCREEN_ADD("screen", RASTER)
860	848	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mess/drivers/if800.c

r29182	r29183
28	28	virtual void machine_reset();
29	29	required_device<cpu_device> m_maincpu;
30	30	required_device<palette_device> m_palette;
	31	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
31	32	};
32	33
33		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	34	UPD7220_DISPLAY_PIXELS_MEMBER( if800_state::hgdc_display_pixels )
34	35	{
35		if800_state *state = device->machine().driver_data<if800_state>();
36		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	36	const rgb_t *palette = m_palette->palette()->entry_list_raw();
37	37
38	38	int xi,gfx;
39	39	UINT8 pen;
40	40
41		gfx = state->m_video_ram[address];
	41	gfx = m_video_ram[address];
42	42
43	43	for(xi=0;xi<8;xi++)
44	44	{
r29182	r29183
73	73	{
74	74	}
75	75
76		static UPD7220_INTERFACE( hgdc_intf )
77		{
78		hgdc_display_pixels,
79		NULL,
80		DEVCB_NULL,
81		DEVCB_NULL,
82		DEVCB_NULL
83		};
84
85	76	static ADDRESS_MAP_START( upd7220_map, AS_0, 8, if800_state )
86	77	AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram")
87	78	ADDRESS_MAP_END
r29182	r29183
94	85
95	86
96	87	//  MCFG_PIC8259_ADD( "pic8259", if800_pic8259_config )
97		MCFG_UPD7220_ADD("upd7220", 8000000/4, hgdc_intf, upd7220_map)
	88	MCFG_DEVICE_ADD("upd7220", UPD7220, 8000000/4)
	89	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
	90	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(if800_state, hgdc_display_pixels)
98	91
99	92	/* video hardware */
100	93	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/mess/drivers/apc.c

r29182	r29183
151	151	UINT8 m_dma_offset[4];
152	152
153	153	IRQ_CALLBACK_MEMBER(irq_callback);
	154
	155	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
	156	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
154	157
155	158	protected:
156	159	// driver_device overrides
r29182	r29183
179	182	}
180	183
181	184
182		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	185	UPD7220_DISPLAY_PIXELS_MEMBER( apc_state::hgdc_display_pixels )
183	186	{
184	187	// ...
185	188	}
186	189
187		static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
	190	UPD7220_DRAW_TEXT_LINE_MEMBER( apc_state::hgdc_draw_text )
188	191	{
189		apc_state *state = device->machine().driver_data<apc_state>();
190		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	192	const rgb_t *palette = m_palette->palette()->entry_list_raw();
191	193	int xi,yi,yi_trans;
192	194	int x;
193	195	UINT8 char_size;
194	196	//  UINT8 interlace_on;
195	197
196		//  if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
	198	//  if(m_video_ff[DISPLAY_REG] == 0) //screen is off
197	199	//      return;
198	200
199		//  interlace_on = state->m_video_reg[2] == 0x10; /* TODO: correct? */
	201	//  interlace_on = m_video_reg[2] == 0x10; /* TODO: correct? */
200	202	char_size = 19;
201	203
202	204	for(x=0;x<pitch;x++)
r29182	r29183
208	210	UINT32 tile_addr;
209	211	UINT8 tile_sel;
210	212
211		//      tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1));
	213	//      tile_addr = addr+(x*(m_video_ff[WIDTH40_REG]+1));
212	214	tile_addr = addr+(x*(1));
213	215
214		tile = state->m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0x00ff;
215		tile_sel = state->m_video_ram_1[(tile_addr*2) & 0x1fff] & 0x00ff;
216		attr = (state->m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0x00ff);
	216	tile = m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0x00ff;
	217	tile_sel = m_video_ram_1[(tile_addr*2) & 0x1fff] & 0x00ff;
	218	attr = (m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0x00ff);
217	219
218	220	u_line = attr & 0x01;
219	221	o_line = attr & 0x02;
r29182	r29183
233	235	res_x = (x*8+xi);
234	236	res_y = y*lr+yi;
235	237
236		if(!device->machine().first_screen()->visible_area().contains(res_x, res_y))
	238	if(!machine().first_screen()->visible_area().contains(res_x, res_y))
237	239	continue;
238	240
239	241	/*
r29182	r29183
257	259	if(yi & 0x10)
258	260	tile_data = 0;
259	261	else
260		tile_data = state->m_aux_pcg[(tile & 0xff)*0x20+yi*2];
	262	tile_data = m_aux_pcg[(tile & 0xff)*0x20+yi*2];
261	263	}
262	264	else
263		tile_data = state->m_char_rom[(tile & 0x7f)+((tile & 0x80)<<4)+((yi_trans & 0xf)*0x80)+((yi_trans & 0x10)<<8)];
	265	tile_data = m_char_rom[(tile & 0x7f)+((tile & 0x80)<<4)+((yi_trans & 0xf)*0x80)+((yi_trans & 0x10)<<8)];
264	266
265	267	if(reverse) { tile_data^=0xff; }
266	268	if(u_line && yi == lr-1) { tile_data = 0xff; }
267	269	if(o_line && yi == 0) { tile_data = 0xff; }
268	270	if(v_line)  { tile_data|=1; }
269		if(blink && device->machine().first_screen()->frame_number() & 0x20) { tile_data = 0; } // TODO: rate & correct behaviour
	271	if(blink && machine().first_screen()->frame_number() & 0x20) { tile_data = 0; } // TODO: rate & correct behaviour
270	272
271		if(cursor_on && cursor_addr == tile_addr && device->machine().first_screen()->frame_number() & 0x10)
	273	if(cursor_on && cursor_addr == tile_addr && machine().first_screen()->frame_number() & 0x10)
272	274	tile_data^=0xff;
273	275
274	276	if(yi >= char_size)
r29182	r29183
758	760	m_keyb.sig = 0;
759	761	}
760	762
761
762		static UPD7220_INTERFACE( hgdc_1_intf )
763		{
764		NULL,
765		hgdc_draw_text,
766		DEVCB_NULL,
767		DEVCB_NULL,
768		DEVCB_NULL
769		};
770
771
772		static UPD7220_INTERFACE( hgdc_2_intf )
773		{
774		hgdc_display_pixels,
775		NULL,
776		DEVCB_NULL,
777		DEVCB_NULL,
778		DEVCB_NULL
779		};
780
781	763	static const gfx_layout charset_8x16 =
782	764	{
783	765	8, 16,
r29182	r29183
1000	982
1001	983	MCFG_GFXDECODE_ADD("gfxdecode", "palette", apc)
1002	984
1003		MCFG_UPD7220_ADD("upd7220_chr", XTAL_3_579545MHz, hgdc_1_intf, upd7220_1_map) // unk clock
1004		MCFG_UPD7220_ADD("upd7220_btm", XTAL_3_579545MHz, hgdc_2_intf, upd7220_2_map) // unk clock
	985	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 3579545) // unk clock
	986	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
	987	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(apc_state, hgdc_draw_text)
1005	988
	989	MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 3579545) // unk clock
	990	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
	991	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(apc_state, hgdc_display_pixels)
	992
1006	993	MCFG_PALETTE_ADD("palette", 16)
1007	994	MCFG_PALETTE_INIT_OWNER(apc_state,apc)
1008	995

trunk/src/mess/drivers/mz6500.c

r29182	r29183
33	33	virtual void video_start();
34	34	required_device<cpu_device> m_maincpu;
35	35	required_device<palette_device> m_palette;
	36	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
36	37	};
37	38
38		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	39	UPD7220_DISPLAY_PIXELS_MEMBER( mz6500_state::hgdc_display_pixels )
39	40	{
40		mz6500_state *state = device->machine().driver_data<mz6500_state>();
41		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	41	const rgb_t *palette = m_palette->palette()->entry_list_raw();
42	42	int gfx[3];
43	43	UINT8 i,pen;
44	44
45		gfx[0] = state->m_video_ram[address + 0x00000];
46		gfx[1] = state->m_video_ram[address + 0x10000];
47		gfx[2] = state->m_video_ram[address + 0x20000];
	45	gfx[0] = m_video_ram[address + 0x00000];
	46	gfx[1] = m_video_ram[address + 0x10000];
	47	gfx[2] = m_video_ram[address + 0x20000];
48	48
49	49	for(i=0; i<8; i++)
50	50	{
r29182	r29183
126	126	SLOT_INTERFACE( "525hd", FLOPPY_525_HD )
127	127	SLOT_INTERFACE_END
128	128
129		static UPD7220_INTERFACE( hgdc_intf )
130		{
131		hgdc_display_pixels,
132		NULL,
133		DEVCB_NULL,
134		DEVCB_NULL,
135		DEVCB_NULL
136		};
137
138	129	static ADDRESS_MAP_START( upd7220_map, AS_0, 8, mz6500_state )
139	130	AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram")
140	131	ADDRESS_MAP_END
r29182	r29183
157	148	MCFG_PALETTE_ADD("palette", 8)
158	149
159	150	/* Devices */
160		MCFG_UPD7220_ADD("upd7220", 8000000/6, hgdc_intf, upd7220_map) // unk clock
	151	MCFG_DEVICE_ADD("upd7220", UPD7220, 8000000/6) // unk clock
	152	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
	153	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(mz6500_state, hgdc_display_pixels)
	154
161	155	MCFG_UPD765A_ADD("upd765", true, true)
162	156	MCFG_FLOPPY_DRIVE_ADD("upd765:0", mz6500_floppies, "525hd", floppy_image_device::default_floppy_formats)
163	157	MCFG_FLOPPY_DRIVE_ADD("upd765:1", mz6500_floppies, "525hd", floppy_image_device::default_floppy_formats)

trunk/src/mess/drivers/a5105.c

r29182	r29183
88	88	required_device<ram_device> m_ram;
89	89	required_device<gfxdecode_device> m_gfxdecode;
90	90	required_device<palette_device> m_palette;
	91	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
	92	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
91	93	};
92	94
93	95	/* TODO */
94		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	96	UPD7220_DISPLAY_PIXELS_MEMBER( a5105_state::hgdc_display_pixels )
95	97	{
96		a5105_state *state = device->machine().driver_data<a5105_state>();
97		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	98	const rgb_t *palette = m_palette->palette()->entry_list_raw();
98	99
99	100	int xi,gfx;
100	101	UINT8 pen;
101	102
102		gfx = state->m_video_ram[address & 0x1ffff];
	103	gfx = m_video_ram[address & 0x1ffff];
103	104
104	105	for(xi=0;xi<8;xi++)
105	106	{
r29182	r29183
109	110	}
110	111	}
111	112
112		static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
	113	UPD7220_DRAW_TEXT_LINE_MEMBER( a5105_state::hgdc_draw_text )
113	114	{
114		a5105_state *state = device->machine().driver_data<a5105_state>();
115		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	115	const rgb_t *palette = m_palette->palette()->entry_list_raw();
116	116	int x;
117	117	int xi,yi;
118	118	int tile,color;
r29182	r29183
120	120
121	121	for( x = 0; x < pitch; x++ )
122	122	{
123		tile = (state->m_video_ram[((addr+x)*2) & 0x1ffff] & 0xff);
124		color = (state->m_video_ram[((addr+x)*2+1) & 0x1ffff] & 0x0f);
	123	tile = (m_video_ram[((addr+x)*2) & 0x1ffff] & 0xff);
	124	color = (m_video_ram[((addr+x)*2+1) & 0x1ffff] & 0x0f);
125	125
126	126	for( yi = 0; yi < lr; yi++)
127	127	{
128		tile_data = state->m_char_ram[(tile*8+yi) & 0x7ff];
	128	tile_data = m_char_ram[(tile*8+yi) & 0x7ff];
129	129
130		if(cursor_on && cursor_addr == addr+x && device->machine().first_screen()->frame_number() & 0x10)
	130	if(cursor_on && cursor_addr == addr+x && machine().first_screen()->frame_number() & 0x10)
131	131	tile_data^=0xff;
132	132
133	133	for( xi = 0; xi < 8; xi++)
r29182	r29183
141	141	if(yi >= 8) { pen = 0; }
142	142
143	143	/* TODO: pitch is currently 40, this should actually go in the upd7220 device */
144		if(!device->machine().first_screen()->visible_area().contains(res_x*2+0, res_y))
	144	if(!machine().first_screen()->visible_area().contains(res_x*2+0, res_y))
145	145	continue;
146	146
147	147	bitmap.pix32(res_y, res_x*2+0) = palette[pen];
148	148
149		if(!device->machine().first_screen()->visible_area().contains(res_x*2+1, res_y))
	149	if(!machine().first_screen()->visible_area().contains(res_x*2+1, res_y))
150	150	continue;
151	151
152	152	bitmap.pix32(res_y, res_x*2+1) = palette[pen];
r29182	r29183
539	539	m_char_ram = memregion("pcg")->base();
540	540	}
541	541
542		static UPD7220_INTERFACE( hgdc_intf )
543		{
544		hgdc_display_pixels,
545		hgdc_draw_text,
546		DEVCB_NULL,
547		DEVCB_NULL,
548		DEVCB_NULL
549		};
550
551	542	static ADDRESS_MAP_START( upd7220_map, AS_0, 8, a5105_state)
552	543	ADDRESS_MAP_GLOBAL_MASK(0x1ffff)
553	544	AM_RANGE(0x00000, 0x1ffff) AM_RAM AM_SHARE("video_ram")
r29182	r29183
613	604	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
614	605
615	606	/* Devices */
616		MCFG_UPD7220_ADD("upd7220", XTAL_15MHz / 16, hgdc_intf, upd7220_map) // unk clock
	607	MCFG_DEVICE_ADD("upd7220", UPD7220, XTAL_15MHz / 16) // unk clock
	608	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
	609	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(a5105_state, hgdc_display_pixels)
	610	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(a5105_state, hgdc_draw_text)
	611
617	612	MCFG_Z80CTC_ADD( "z80ctc", XTAL_15MHz / 4, a5105_ctc_intf )
618	613	MCFG_Z80PIO_ADD( "z80pio", XTAL_15MHz / 4, a5105_pio_intf )
619	614

trunk/src/mess/drivers/vt240.c

r29182	r29183
30	30	vt240_state(const machine_config &mconfig, device_type type, const char *tag)
31	31	: driver_device(mconfig, type, tag),
32	32	m_maincpu(*this, "maincpu"),
33		m_hgdc(*this, "upd7220")
34		,
	33	m_hgdc(*this, "upd7220"),
35	34	m_video_ram(*this, "video_ram"){ }
36	35
37	36	required_device<cpu_device> m_maincpu;
r29182	r29183
48	47	DECLARE_DRIVER_INIT(vt240);
49	48	virtual void machine_reset();
50	49	INTERRUPT_GEN_MEMBER(vt240_irq);
	50	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
51	51	};
52	52
53	53	/* TODO */
54		static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
	54	UPD7220_DRAW_TEXT_LINE_MEMBER( vt240_state::hgdc_draw_text )
55	55	{
56		//vt240_state *state = device->machine().driver_data<a5105_state>();
57	56	//int x;
58	57	//int xi,yi;
59	58	//int tile,color;
r29182	r29183
67	66
68	67	for( yi = 0; yi < lr; yi++)
69	68	{
70		tile_data = state->m_char_rom[(tile*8+yi) & 0x7ff];
	69	tile_data = m_char_rom[(tile*8+yi) & 0x7ff];
71	70
72	71	if(cursor_on && cursor_addr == addr+x) //TODO
73	72	tile_data^=0xff;
r29182	r29183
131	130	{
132	131	}
133	132
134		static UPD7220_INTERFACE( hgdc_intf )
135		{
136		NULL,
137		hgdc_draw_text,
138		DEVCB_NULL,
139		DEVCB_NULL,
140		DEVCB_NULL
141		};
142
143	133	INTERRUPT_GEN_MEMBER(vt240_state::vt240_irq)
144	134	{
145	135	//device.execute().set_input_line(I8085_RST65_LINE, ASSERT_LINE);
r29182	r29183
179	169	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
180	170	MCFG_GFXDECODE_ADD("gfxdecode", "palette", vt240)
181	171
182		MCFG_UPD7220_ADD("upd7220", XTAL_4MHz / 4, hgdc_intf, upd7220_map) //unknown clock
	172	MCFG_DEVICE_ADD("upd7220", UPD7220, XTAL_4MHz / 4)
	173	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
	174	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(vt240_state, hgdc_draw_text)
183	175	MACHINE_CONFIG_END
184	176
185	177	/* ROM definition */

trunk/src/mess/drivers/pc9801.c

r29182	r29183
683	683	DECLARE_WRITE8_MEMBER(pc9821_ext2_video_ff_w);
684	684
685	685	DECLARE_FLOPPY_FORMATS( floppy_formats );
	686	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
	687	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
686	688
687	689	private:
688	690	UINT8 m_sdip_read(UINT16 port, UINT8 sdip_offset);
r29182	r29183
781	783	return 0;
782	784	}
783	785
784		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	786	UPD7220_DISPLAY_PIXELS_MEMBER( pc9801_state::hgdc_display_pixels )
785	787	{
786		pc9801_state *state = device->machine().driver_data<pc9801_state>();
787		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	788	const rgb_t *palette = m_palette->palette()->entry_list_raw();
788	789	int xi;
789	790	int res_x,res_y;
790	791	UINT8 pen;
791	792	UINT8 interlace_on;
792	793	UINT8 colors16_mode;
793	794
794		if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
	795	if(m_video_ff[DISPLAY_REG] == 0) //screen is off
795	796	return;
796	797
797		//  popmessage("%02x %d",state->m_video_ff[INTERLACE_REG],device->machine().first_screen()->visible_area().max_y + 1);
798		//  interlace_on = ((device->machine().first_screen()->visible_area().max_y + 1) >= 400) ? 1 : 0;
799		interlace_on = state->m_video_ff[INTERLACE_REG];
800		colors16_mode = (state->m_ex_video_ff[ANALOG_16_MODE]) ? 16 : 8;
	798	//  popmessage("%02x %d",m_video_ff[INTERLACE_REG],machine().first_screen()->visible_area().max_y + 1);
	799	//  interlace_on = ((machine().first_screen()->visible_area().max_y + 1) >= 400) ? 1 : 0;
	800	interlace_on = m_video_ff[INTERLACE_REG];
	801	colors16_mode = (m_ex_video_ff[ANALOG_16_MODE]) ? 16 : 8;
801	802
802		if(state->m_ex_video_ff[ANALOG_256_MODE])
	803	if(m_ex_video_ff[ANALOG_256_MODE])
803	804	{
804	805	for(xi=0;xi<8;xi++)
805	806	{
806	807	res_x = x + xi;
807	808	res_y = y;
808	809
809		if(!device->machine().first_screen()->visible_area().contains(res_x, res_y*2+0))
	810	if(!machine().first_screen()->visible_area().contains(res_x, res_y*2+0))
810	811	return;
811	812
812		pen = state->m_ext_gvram[(address*8+xi)+(state->m_vram_disp*0x40000)];
	813	pen = m_ext_gvram[(address*8+xi)+(m_vram_disp*0x40000)];
813	814
814	815	bitmap.pix32(res_y*2+0, res_x) = palette[pen + 0x20];
815		if(device->machine().first_screen()->visible_area().contains(res_x, res_y*2+1))
	816	if(machine().first_screen()->visible_area().contains(res_x, res_y*2+1))
816	817	bitmap.pix32(res_y*2+1, res_x) = palette[pen + 0x20];
817	818	}
818	819	}
r29182	r29183
823	824	res_x = x + xi;
824	825	res_y = y;
825	826
826		pen = ((state->m_video_ram_2[(address & 0x7fff) + (0x08000) + (state->m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 1 : 0;
827		pen|= ((state->m_video_ram_2[(address & 0x7fff) + (0x10000) + (state->m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 2 : 0;
828		pen|= ((state->m_video_ram_2[(address & 0x7fff) + (0x18000) + (state->m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 4 : 0;
829		if(state->m_ex_video_ff[ANALOG_16_MODE])
830		pen|= ((state->m_video_ram_2[(address & 0x7fff) + (0) + (state->m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 8 : 0;
	827	pen = ((m_video_ram_2[(address & 0x7fff) + (0x08000) + (m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 1 : 0;
	828	pen|= ((m_video_ram_2[(address & 0x7fff) + (0x10000) + (m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 2 : 0;
	829	pen|= ((m_video_ram_2[(address & 0x7fff) + (0x18000) + (m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 4 : 0;
	830	if(m_ex_video_ff[ANALOG_16_MODE])
	831	pen|= ((m_video_ram_2[(address & 0x7fff) + (0) + (m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 8 : 0;
831	832
832	833	if(interlace_on)
833	834	{
834		if(device->machine().first_screen()->visible_area().contains(res_x, res_y*2+0))
	835	if(machine().first_screen()->visible_area().contains(res_x, res_y*2+0))
835	836	bitmap.pix32(res_y*2+0, res_x) = palette[pen + colors16_mode];
836	837	/* TODO: it looks like that PC-98xx can only display even lines ... */
837		if(device->machine().first_screen()->visible_area().contains(res_x, res_y*2+1))
	838	if(machine().first_screen()->visible_area().contains(res_x, res_y*2+1))
838	839	bitmap.pix32(res_y*2+1, res_x) = palette[pen + colors16_mode];
839	840	}
840	841	else
r29182	r29183
843	844	}
844	845	}
845	846
846		static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
	847	UPD7220_DRAW_TEXT_LINE_MEMBER( pc9801_state::hgdc_draw_text )
847	848	{
848		pc9801_state *state = device->machine().driver_data<pc9801_state>();
849		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	849	const rgb_t *palette = m_palette->palette()->entry_list_raw();
850	850	int xi,yi;
851	851	int x;
852	852	UINT8 char_size;
r29182	r29183
856	856	UINT8 kanji_sel;
857	857	UINT8 x_step;
858	858
859		if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
	859	if(m_video_ff[DISPLAY_REG] == 0) //screen is off
860	860	return;
861	861
862		//  interlace_on = state->m_video_ff[INTERLACE_REG];
863		char_size = state->m_video_ff[FONTSEL_REG] ? 16 : 8;
	862	//  interlace_on = m_video_ff[INTERLACE_REG];
	863	char_size = m_video_ff[FONTSEL_REG] ? 16 : 8;
864	864	tile = 0;
865	865
866	866	for(x=0;x<pitch;x+=x_step)
r29182	r29183
873	873	UINT8 knj_tile;
874	874	UINT8 gfx_mode;
875	875
876		tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1));
	876	tile_addr = addr+(x*(m_video_ff[WIDTH40_REG]+1));
877	877
878	878	kanji_sel = 0;
879	879	kanji_lr = 0;
880	880
881		tile = state->m_video_ram_1[(tile_addr*2) & 0x1fff] & 0xff;
882		knj_tile = state->m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0xff;
	881	tile = m_video_ram_1[(tile_addr*2) & 0x1fff] & 0xff;
	882	knj_tile = m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0xff;
883	883	if(knj_tile)
884	884	{
885	885	/* Note: bit 7 doesn't really count, if a kanji is enabled then the successive tile is always the second part of it.
r29182	r29183
900	900	else
901	901	x_step = 1;
902	902
903		attr = (state->m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0xff);
	903	attr = (m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0xff);
904	904
905	905	secret = (attr & 1) ^ 1;
906	906	blink = attr & 2;
907	907	reverse = attr & 4;
908	908	u_line = attr & 8;
909		v_line = (state->m_video_ff[ATTRSEL_REG]) ? 0 : attr & 0x10;
910		gfx_mode = (state->m_video_ff[ATTRSEL_REG]) ? attr & 0x10 : 0;
	909	v_line = (m_video_ff[ATTRSEL_REG]) ? 0 : attr & 0x10;
	910	gfx_mode = (m_video_ff[ATTRSEL_REG]) ? attr & 0x10 : 0;
911	911	color = (attr & 0xe0) >> 5;
912	912
913	913	for(kanji_lr=0;kanji_lr<x_step;kanji_lr++)
r29182	r29183
918	918	{
919	919	int res_x,res_y;
920	920
921		res_x = ((x+kanji_lr)*8+xi) * (state->m_video_ff[WIDTH40_REG]+1);
922		res_y = y*lr+yi - (state->m_txt_scroll_reg[3] & 0xf);
	921	res_x = ((x+kanji_lr)*8+xi) * (m_video_ff[WIDTH40_REG]+1);
	922	res_y = y*lr+yi - (m_txt_scroll_reg[3] & 0xf);
923	923
924		if(!device->machine().first_screen()->visible_area().contains(res_x, res_y))
	924	if(!machine().first_screen()->visible_area().contains(res_x, res_y))
925	925	continue;
926	926
927	927	tile_data = 0;
r29182	r29183
952	952	tile_data = ((tile >> gfx_bit) & 1) ? 0xff : 0x00;
953	953	}
954	954	else if(kanji_sel)
955		tile_data = (state->m_kanji_rom[tile*0x20+yi*2+kanji_lr]);
	955	tile_data = (m_kanji_rom[tile*0x20+yi*2+kanji_lr]);
956	956	else
957		tile_data = (state->m_char_rom[tile*char_size+state->m_video_ff[FONTSEL_REG]*0x800+yi]);
	957	tile_data = (m_char_rom[tile*char_size+m_video_ff[FONTSEL_REG]*0x800+yi]);
958	958	}
959	959
960	960	if(reverse) { tile_data^=0xff; }
r29182	r29183
962	962	if(v_line)  { tile_data|=8; }
963	963
964	964	/* TODO: proper blink rate for these two */
965		if(cursor_on && cursor_addr == tile_addr && device->machine().first_screen()->frame_number() & 0x10)
	965	if(cursor_on && cursor_addr == tile_addr && machine().first_screen()->frame_number() & 0x10)
966	966	tile_data^=0xff;
967	967
968		if(blink && device->machine().first_screen()->frame_number() & 0x10)
	968	if(blink && machine().first_screen()->frame_number() & 0x10)
969	969	tile_data^=0xff;
970	970
971	971	if(yi >= char_size)
r29182	r29183
976	976	if(pen != -1)
977	977	bitmap.pix32(res_y, res_x) = palette[pen];
978	978
979		if(state->m_video_ff[WIDTH40_REG])
	979	if(m_video_ff[WIDTH40_REG])
980	980	{
981		if(!device->machine().first_screen()->visible_area().contains(res_x+1, res_y))
	981	if(!machine().first_screen()->visible_area().contains(res_x+1, res_y))
982	982	continue;
983	983
984	984	if(pen != -1)
r29182	r29183
990	990	}
991	991	}
992	992
993		static UPD7220_INTERFACE( hgdc_1_intf )
994		{
995		NULL,
996		hgdc_draw_text,
997		DEVCB_NULL,
998		DEVCB_DEVICE_LINE_MEMBER("upd7220_btm", upd7220_device, ext_sync_w),
999		DEVCB_NULL
1000		};
1001	993
1002		static UPD7220_INTERFACE( hgdc_2_intf )
1003		{
1004		hgdc_display_pixels,
1005		NULL,
1006		DEVCB_NULL,
1007		DEVCB_NULL,
1008		DEVCB_NULL
1009		};
1010
1011
1012	994	#if 0
1013	995	READ8_MEMBER(pc9801_state::pc9801_xx_r)
1014	996	{
r29182	r29183
3672	3654	MCFG_SCREEN_SIZE(640, 480)
3673	3655	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
3674	3656
3675		MCFG_UPD7220_ADD("upd7220_chr", 5000000/2, hgdc_1_intf, upd7220_1_map)
3676		MCFG_UPD7220_ADD("upd7220_btm", 5000000/2, hgdc_2_intf, upd7220_2_map)
	3657	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
	3658	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
	3659	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
	3660	MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
3677	3661
	3662	MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
	3663	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
	3664	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
	3665
3678	3666	MCFG_PALETTE_ADD("palette", 16)
3679	3667	MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)
3680	3668	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pc9801)
r29182	r29183
3744	3732	MCFG_SCREEN_SIZE(640, 480)
3745	3733	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
3746	3734
3747		MCFG_UPD7220_ADD("upd7220_chr", 5000000/2, hgdc_1_intf, upd7220_1_map)
3748		MCFG_UPD7220_ADD("upd7220_btm", 5000000/2, hgdc_2_intf, upd7220_2_map)
	3735	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
	3736	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
	3737	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
	3738	MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
3749	3739
	3740	MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
	3741	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
	3742	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
	3743
3750	3744	MCFG_PALETTE_ADD("palette", 16+16)
3751	3745	MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)
3752	3746	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pc9801)
r29182	r29183
3830	3824	MCFG_SCREEN_SIZE(640, 480)
3831	3825	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
3832	3826
3833		MCFG_UPD7220_ADD("upd7220_chr", 5000000/2, hgdc_1_intf, upd7220_1_map)
3834		MCFG_UPD7220_ADD("upd7220_btm", 5000000/2, hgdc_2_intf, upd7220_2_map)
	3827	MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
	3828	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
	3829	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
	3830	MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
3835	3831
	3832	MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
	3833	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
	3834	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
	3835
3836	3836	MCFG_PALETTE_ADD("palette", 16+16+256)
3837	3837	MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)
3838	3838	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pc9801)

trunk/src/mess/drivers/qx10.c

r29182	r29183
148	148	required_device<cpu_device> m_maincpu;
149	149	required_device<ram_device> m_ram;
150	150	required_device<palette_device> m_palette;
	151	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
	152	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
151	153	};
152	154
153		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	155	UPD7220_DISPLAY_PIXELS_MEMBER( qx10_state::hgdc_display_pixels )
154	156	{
155		qx10_state *state = device->machine().driver_data<qx10_state>();
156		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	157	const rgb_t *palette = m_palette->palette()->entry_list_raw();
157	158	int xi,gfx[3];
158	159	UINT8 pen;
159	160
160		if(state->m_color_mode)
	161	if(m_color_mode)
161	162	{
162		gfx[0] = state->m_video_ram[(address) + 0x00000];
163		gfx[1] = state->m_video_ram[(address) + 0x20000];
164		gfx[2] = state->m_video_ram[(address) + 0x40000];
	163	gfx[0] = m_video_ram[(address) + 0x00000];
	164	gfx[1] = m_video_ram[(address) + 0x20000];
	165	gfx[2] = m_video_ram[(address) + 0x40000];
165	166	}
166	167	else
167	168	{
168		gfx[0] = state->m_video_ram[address];
	169	gfx[0] = m_video_ram[address];
169	170	gfx[1] = 0;
170	171	gfx[2] = 0;
171	172	}
r29182	r29183
180	181	}
181	182	}
182	183
183		static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
	184	UPD7220_DRAW_TEXT_LINE_MEMBER( qx10_state::hgdc_draw_text )
184	185	{
185		qx10_state *state = device->machine().driver_data<qx10_state>();
186		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
	186	const rgb_t *palette = m_palette->palette()->entry_list_raw();
187	187	int x;
188	188	int xi,yi;
189	189	int tile;
r29182	r29183
194	194
195	195	for( x = 0; x < pitch; x++ )
196	196	{
197		tile = state->m_video_ram[(addr+x)*2];
198		attr = state->m_video_ram[(addr+x)*2+1];
	197	tile = m_video_ram[(addr+x)*2];
	198	attr = m_video_ram[(addr+x)*2+1];
199	199
200		color = (state->m_color_mode) ? 1 : (attr & 4) ? 2 : 1; /* TODO: color mode */
	200	color = (m_color_mode) ? 1 : (attr & 4) ? 2 : 1; /* TODO: color mode */
201	201
202	202	for( yi = 0; yi < lr; yi++)
203	203	{
204		tile_data = (state->m_char_rom[tile*16+yi]);
	204	tile_data = (m_char_rom[tile*16+yi]);
205	205
206	206	if(attr & 8)
207	207	tile_data^=0xff;
r29182	r29183
209	209	if(cursor_on && cursor_addr == addr+x) //TODO
210	210	tile_data^=0xff;
211	211
212		if(attr & 0x80 && device->machine().first_screen()->frame_number() & 0x10) //TODO: check for blinking interval
	212	if(attr & 0x80 && machine().first_screen()->frame_number() & 0x10) //TODO: check for blinking interval
213	213	tile_data=0;
214	214
215	215	for( xi = 0; xi < 8; xi++)
r29182	r29183
219	219	res_x = x * 8 + xi;
220	220	res_y = y * lr + yi;
221	221
222		if(!device->machine().first_screen()->visible_area().contains(res_x, res_y))
	222	if(!machine().first_screen()->visible_area().contains(res_x, res_y))
223	223	continue;
224	224
225	225	if(yi >= 16)
r29182	r29183
766	766	m_char_rom = memregion("chargen")->base();
767	767	}
768	768
769		static UPD7220_INTERFACE( hgdc_intf )
770		{
771		hgdc_display_pixels,
772		hgdc_draw_text,
773		DEVCB_NULL,
774		DEVCB_NULL,
775		DEVCB_NULL
776		};
777
778	769	PALETTE_INIT_MEMBER(qx10_state, qx10)
779	770	{
780	771	// ...
r29182	r29183
858	849	MCFG_I8255_ADD("i8255", qx10_i8255_interface)
859	850	MCFG_I8237_ADD("8237dma_1", MAIN_CLK/4, qx10_dma8237_1_interface)
860	851	MCFG_I8237_ADD("8237dma_2", MAIN_CLK/4, qx10_dma8237_2_interface)
861		MCFG_UPD7220_ADD("upd7220", MAIN_CLK/6, hgdc_intf, upd7220_map) // unk clock
	852
	853	MCFG_DEVICE_ADD("upd7220", UPD7220, MAIN_CLK/6) // unk clock
	854	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
	855	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(qx10_state, hgdc_display_pixels)
	856	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(qx10_state, hgdc_draw_text)
862	857	MCFG_VIDEO_SET_SCREEN("screen")
	858
863	859	MCFG_MC146818_ADD( "rtc", XTAL_32_768kHz )
864	860	MCFG_MC146818_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir2_w))
865	861	MCFG_UPD765A_ADD("upd765", true, true)

trunk/src/mess/drivers/dmv.c

r29182	r29183
56	56
57	57	required_shared_ptr<UINT8> m_video_ram;
58	58	required_device<palette_device> m_palette;
	59
	60	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
	61	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
59	62	};
60	63
61	64
r29182	r29183
131	134	machine().device<upi41_cpu_device>("kb_ctrl_mcu")->upi41_master_w(space, offset, data);
132	135	}
133	136
134		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	137	UPD7220_DISPLAY_PIXELS_MEMBER( dmv_state::hgdc_display_pixels )
135	138	{
136	139	//TODO
137	140	}
138	141
139		static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
	142	UPD7220_DRAW_TEXT_LINE_MEMBER( dmv_state::hgdc_draw_text )
140	143	{
141		dmv_state *state = device->machine().driver_data<dmv_state>();
142		const rgb_t *palette = state->m_palette->palette()->entry_list_raw();
143		UINT8 * chargen = state->memregion("maincpu")->base() + 0x1000;
	144	const rgb_t *palette = m_palette->palette()->entry_list_raw();
	145	UINT8 * chargen = memregion("maincpu")->base() + 0x1000;
144	146
145	147	for( int x = 0; x < pitch; x++ )
146	148	{
147		UINT8 tile = state->m_video_ram[((addr+x)*2) & 0x1ffff] & 0xff;
	149	UINT8 tile = m_video_ram[((addr+x)*2) & 0x1ffff] & 0xff;
148	150
149	151	for( int yi = 0; yi < lr; yi++)
150	152	{
r29182	r29183
161	163	res_x = x * 8 + xi;
162	164	res_y = y * lr + yi;
163	165
164		if(!device->machine().first_screen()->visible_area().contains(res_x, res_y))
	166	if(!machine().first_screen()->visible_area().contains(res_x, res_y))
165	167	continue;
166	168
167	169	if(yi >= 16) { pen = 0; }
r29182	r29183
250	252	GFXDECODE_END
251	253
252	254
253		static UPD7220_INTERFACE( hgdc_intf )
254		{
255		hgdc_display_pixels,
256		hgdc_draw_text,
257		DEVCB_NULL,
258		DEVCB_NULL,
259		DEVCB_NULL
260		};
261
262
263	255	//------------------------------------------------------------------------------------
264	256	//   I8237_INTERFACE
265	257	//------------------------------------------------------------------------------------
r29182	r29183
322	314	MCFG_DEFAULT_LAYOUT(layout_dmv)
323	315
324	316	// devices
325		MCFG_UPD7220_ADD( "upd7220", XTAL_5MHz/2, hgdc_intf, upd7220_map ) // unk clock
	317	MCFG_DEVICE_ADD("upd7220", UPD7220, XTAL_5MHz/2) // unk clock
	318	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
	319	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(dmv_state, hgdc_display_pixels)
	320	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(dmv_state, hgdc_draw_text)
	321
326	322	MCFG_I8237_ADD( "dma8237", XTAL_4MHz, dmv_dma8237_config )
327	323	MCFG_UPD765A_ADD( "upd765", true, true )
328	324	MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("dma8237", am9517a_device, dreq3_w))

trunk/src/mess/includes/mikromik.h

r29182	r29183
125	125	int m_fdc_tc;
126	126
127	127	DECLARE_FLOPPY_FORMATS( floppy_formats );
	128	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
128	129	};
129	130
130	131

trunk/src/mess/includes/compis.h

r29182	r29183
125	125	DECLARE_WRITE_LINE_MEMBER(write_centronics_select);
126	126
127	127	int m_tmr0;
	128
	129	UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
128	130	};
129	131
130	132

trunk/src/mess/video/mikromik.c

r29182	r29183
50	50	//  UPD7220_INTERFACE( hgdc_intf )
51	51	//-------------------------------------------------
52	52
53		static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
	53	UPD7220_DISPLAY_PIXELS_MEMBER( mm1_state::hgdc_display_pixels )
54	54	{
55		mm1_state *state = device->machine().driver_data<mm1_state>();
	55	UINT8 data = m_video_ram[address];
56	56
57		UINT8 data = state->m_video_ram[address];
58
59	57	for (int i = 0; i < 8; i++)
60	58	{
61		if (BIT(data, 7-i)) bitmap.pix32(y, x + i) = state->m_palette->pen(1);
	59	if (BIT(data, 7 - i)) bitmap.pix32(y, x + i) = m_palette->pen(1);
62	60	}
63	61	}
64	62
65		static UPD7220_INTERFACE( hgdc_intf )
66		{
67		hgdc_display_pixels,
68		NULL,
69		DEVCB_NULL,
70		DEVCB_NULL,
71		DEVCB_NULL
72		};
73	63
74
75	64	UINT32 mm1_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
76	65	{
77	66	/* text */
r29182	r29183
127	116
128	117	MCFG_I8275_ADD(I8275_TAG, XTAL_18_720MHz/8, 8, crtc_display_pixels, DEVWRITELINE(I8237_TAG, am9517a_device, dreq0_w))
129	118	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
130		MCFG_UPD7220_ADD(UPD7220_TAG, XTAL_18_720MHz/8, hgdc_intf, mm1_upd7220_map)
	119
	120	MCFG_DEVICE_ADD(UPD7220_TAG, UPD7220, XTAL_18_720MHz/8)
	121	MCFG_DEVICE_ADDRESS_MAP(AS_0, mm1_upd7220_map)
	122	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(mm1_state, hgdc_display_pixels)
131	123	MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
132	124	MACHINE_CONFIG_END

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