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r28745 Wednesday 19th March, 2014 at 23:53:59 UTC by Michael Zapf
(MESS) devcb2 migration. (nw)

[src/emu/machine]	tms9901.c tms9901.h
[src/mess/drivers]	geneve.c ti99_4p.c ti99_4x.c ti99_8.c tm990189.c

trunk/src/emu/machine/tms9901.c

r28744	r28745
4	4
5	5	TMS9901 Programmable System Interface
6	6
	7	+--------------+
	8	RST1*| 1   |  |   40| Vcc
	9	CRUOUT | 2   +--+   39| S0
	10	CRUCLK | 3          38| P0
	11	CRUIN | 4          37| P1
	12	CE*| 5          36| S1
	13	INT6*| 6          35| S2
	14	INT5*| 7          34| INT7*  / P15
	15	INT4*| 8          33| INT8*  / P14
	16	INT3*| 9          32| INT9*  / P13
	17	Phi*|10          31| INT10* / P12
	18	INTREQ*|11          30| INT11* / P11
	19	IC3 |12          29| INT12* / P10
	20	IC2 |13          28| INT13* / P9
	21	IC1 |14          27| INT14* / P8
	22	IC0 |15          26| P2
	23	Vss |16          25| S3
	24	INT1*|17          24| S4
	25	INT2*|18          23| INT15* / P7
	26	P6 |19          22| P3
	27	P5 |20          21| P4
	28	+--------------+
	29
7	30	Overview:
8	31	TMS9901 is a support chip for TMS9900.  It handles interrupts, provides
9	32	several I/O pins, and a timer (a.k.a. clock: it is merely a register which
r28744	r28745
101	124
102	125	#include "tms9901.h"
103	126
104		#define VERBOSE 1
105		#define LOG logerror
	127	/*
	128	Debugging flags.
	129	*/
	130	#define TRACE_PINS 0
	131	#define TRACE_CLOCK 0
	132	#define TRACE_MODE 0
106	133
107	134	/*
108	135	Constructor
109	136	*/
110	137	tms9901_device::tms9901_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
111		: device_t(mconfig, TMS9901, "TMS9901 Programmable System Interface", tag, owner, clock, "tms9901", __FILE__)
	138	: device_t(mconfig, TMS9901, "TMS9901 Programmable System Interface", tag, owner, clock, "tms9901", __FILE__),
	139	m_read_block(*this),
	140	m_write_p0(*this),
	141	m_write_p1(*this),
	142	m_write_p2(*this),
	143	m_write_p3(*this),
	144	m_write_p4(*this),
	145	m_write_p5(*this),
	146	m_write_p6(*this),
	147	m_write_p7(*this),
	148	m_write_p8(*this),
	149	m_write_p9(*this),
	150	m_write_p10(*this),
	151	m_write_p11(*this),
	152	m_write_p12(*this),
	153	m_write_p13(*this),
	154	m_write_p14(*this),
	155	m_write_p15(*this),
	156	m_interrupt(*this)
112	157	{
113	158	}
114	159
r28744	r28745
119	164	{
120	165	int current_ints;
121	166
122		/* int_state: state of lines int1-int15 */
	167	// m_int_state: inverted state of lines INT1*-INT15*. Bits are set by set_single_int only.
123	168	current_ints = m_int_state;
124	169	if (m_clock_register != 0)
125		{   /* if timer is enabled, INT3 pin is overriden by timer */
	170	{
	171	// if timer is enabled, INT3 pin is overridden by timer
126	172	if (m_timer_int_pending)
127	173	{
128		if (VERBOSE>8) LOG("tms9901: timer fires\n");
	174	if (TRACE_CLOCK) logerror("%s: timer fires\n", tag());
129	175	current_ints |= TMS9901_INT3;
130	176	}
131	177	else
132	178	{
133		if (VERBOSE>8) LOG("tms9901: timer clear\n");
	179	if (TRACE_CLOCK) logerror("%s: timer clear\n", tag());
134	180	current_ints &= ~TMS9901_INT3;
135	181	}
136	182	}
137	183
138		/* enabled_ints: enabled interrupts */
139		/* mask out all int pins currently set as output */
	184	// enabled_ints: enabled interrupts
	185	// Remove all settings from pins that are set as outputs (INT7*-INT15* share the same pins as P15-P7)
140	186	current_ints &= m_enabled_ints & (~m_pio_direction_mirror);
141	187
142	188	// Check whether we have a new state. For systems that use level-triggered
r28744	r28745
147	193
148	194	m_old_int_state = current_ints;
149	195
150		if (current_ints)
	196	if (current_ints != 0)
151	197	{
152	198	// find which interrupt tripped us:
153	199	// the number of the first (i.e. least significant) non-zero bit among
154	200	// the 16 first bits
155		// we simply look for the first bit set to 1 in current_ints... */
	201	// we simply look for the first bit set to 1 in current_ints...
156	202	int level = 0;
157	203
158	204	while ((current_ints & 1)==0)
r28744	r28745
162	208	}
163	209	m_int_pending = true;
164	210	if (!m_interrupt.isnull())
165		m_interrupt(level, 1);  // the offset carries the IC0-3 level
	211	m_interrupt(level, 1, 0xff);  // the offset carries the IC0-3 level
166	212	}
167	213	else
168	214	{
169	215	m_int_pending = false;
170	216	if (!m_interrupt.isnull())
171		m_interrupt(0xf, 0);  //Spec: INTREQ*=1 <=> IC0,1,2,3 = 1111
	217	m_interrupt(0xf, 0, 0xff);  //Spec: INTREQ*=1 <=> IC0,1,2,3 = 1111
172	218	}
173	219	}
174	220
r28744	r28745
176	222	function which should be called by the driver when the state of an INTn*
177	223	pin changes (only required if the pin is set up as an interrupt pin)
178	224
179		state == 0: INTn* is inactive (high)
180		state != 0: INTn* is active (low)
	225	state == CLEAR_LINE: INTn* is inactive (high)
	226	state == ASSERT_LINE: INTn* is active (low)
181	227
182	228	0<=pin_number<=15
183	229	*/
r28744	r28745
189	235	else
190	236	m_int_state &= ~(1 << pin_number);
191	237
192		/* we do not need to always call this function - time for an optimization */
193	238	field_interrupts();
194	239	}
195	240
r28744	r28745
236	281	{
237	282	case 0:
238	283	if (m_clock_mode)
239		{   /* clock mode */
	284	{
	285	// Clock mode. The LSB reflects the CB bit which is set to 1 for clock mode.
240	286	answer = ((m_clock_read_register & 0x7F) << 1) | 0x01;
241	287	}
242	288	else
243		{   /* interrupt mode */
244		// m_int_state stores the INTx values, which are inverted to the pin levels (INTx*)
245		answer = ((~m_int_state) & m_supported_int_mask) & 0xFF;
246
	289	{
	290	// Interrupt mode
	291	// Note that we rely on the read function to deliver the same
	292	// INTx levels that have been signaled via the set_single_int method.
	293	// This may mean that those levels must be latched by the callee.
247	294	if (!m_read_block.isnull())
248	295	answer |= m_read_block(TMS9901_CB_INT7);
249	296
250		answer &= ~ m_pio_direction_mirror;
	297	// Remove the bits that are set as outputs (can only be INT7*)
	298	answer &= ~m_pio_direction_mirror;
	299
	300	// Set those bits here
251	301	answer |= (m_pio_output_mirror & m_pio_direction_mirror) & 0xFF;
252	302	}
	303	if (TRACE_PINS) logerror("%s: input on lines INT7..CB = %02x\n", tag(), answer);
253	304	break;
254	305	case 1:
255	306	if (m_clock_mode)
256		{   /* clock mode */
	307	{
	308	// clock mode
257	309	answer = (m_clock_read_register & 0x3F80) >> 7;
258	310	if (!m_int_pending)
259	311	answer |= 0x80;
260	312	}
261	313	else
262		{   /* interrupt mode */
263		answer = ((~m_int_state) & m_supported_int_mask) >> 8;
264
	314	{
	315	// See above concerning the INT levels.
265	316	if (!m_read_block.isnull())
266	317	answer |= m_read_block(TMS9901_INT8_INT15);
267	318
268		answer &= ~ (m_pio_direction_mirror >> 8);
	319	// Remove the bits that are set as outputs (can be any line)
	320	answer &= ~(m_pio_direction_mirror >> 8);
269	321	answer |= (m_pio_output_mirror & m_pio_direction_mirror) >> 8;
270	322	}
	323	if (TRACE_PINS) logerror("%s: input on lines INT15..INT8 = %02x\n", tag(), answer);
271	324	break;
272	325	case 2:
273	326	/* exit timer mode */
274		// MZ: See comments at the beginning. I'm pretty sure this is not correct.
	327	// MZ: See comments at the beginning. I'm sure that we do not quit clock mode.
275	328	// m_clock_mode = false;
276	329
277	330	if (!m_read_block.isnull())
r28744	r28745
279	332	else
280	333	answer = 0;
281	334
282		answer &= ~ m_pio_direction;
	335	answer &= ~m_pio_direction;
283	336	answer |= (m_pio_output & m_pio_direction) & 0xFF;
	337	if (TRACE_PINS) logerror("%s: input on lines P7..P0 = %02x\n", tag(), answer);
284	338
285	339	break;
286	340	case 3:
287	341	// MZ: see above
288		// m_clock_mode = false;        // exit timer mode
	342	// m_clock_mode = false;
289	343	if (!m_read_block.isnull())
290	344	answer = m_read_block(TMS9901_P8_P15);
291	345	else
292	346	answer = 0;
293	347
294		answer &= ~ (m_pio_direction >> 8);
	348	answer &= ~(m_pio_direction >> 8);
295	349	answer |= (m_pio_output & m_pio_direction) >> 8;
	350	if (TRACE_PINS) logerror("%s: input on lines P15..P8 = %02x\n", tag(), answer);
296	351
297	352	break;
298	353	}
r28744	r28745
317	372	{
318	373	data &= 1;  /* clear extra bits */
319	374	offset &= 0x01F;
320		switch (offset)
	375
	376	if (offset >= 0x10)
321	377	{
322		case 0x00:  /* write to mode bit */
	378	int pin = offset & 0x0F;
	379	if (TRACE_PINS) logerror("%s: output on P%d = %d\n", tag(), pin, data);
	380
	381	int bit = (1 << pin);
	382
	383	// MZ: see above - I think this is wrong
	384	// m_clock_mode = false; // exit timer mode
	385
	386	// Once a value is written to a pin, the pin remains in output mode
	387	// until the chip is reset
	388	m_pio_direction |= bit;
	389
	390	// Latch the value
	391	if (data)
	392	m_pio_output |= bit;
	393	else
	394	m_pio_output &= ~bit;
	395
	396	if (pin >= 7)
	397	{
	398	// pins P7-P15 are mirrored as INT15*-INT7*,
	399	// also using the same pins in the package
	400	int mirror_bit = (1 << (22 - pin));
	401
	402	// See above
	403	m_pio_direction_mirror |= mirror_bit;
	404
	405	if (data)
	406	m_pio_output_mirror |= mirror_bit;
	407	else
	408	m_pio_output_mirror &= ~mirror_bit;
	409	}
	410
	411	switch (offset)
	412	{
	413	case 0x10:
	414	if (!m_write_p0.isnull()) m_write_p0(data); break;
	415	case 0x11:
	416	if (!m_write_p1.isnull()) m_write_p1(data); break;
	417	case 0x12:
	418	if (!m_write_p2.isnull()) m_write_p2(data); break;
	419	case 0x13:
	420	if (!m_write_p3.isnull()) m_write_p3(data); break;
	421	case 0x14:
	422	if (!m_write_p4.isnull()) m_write_p4(data); break;
	423	case 0x15:
	424	if (!m_write_p5.isnull()) m_write_p5(data); break;
	425	case 0x16:
	426	if (!m_write_p6.isnull()) m_write_p6(data); break;
	427	case 0x17:
	428	if (!m_write_p7.isnull()) m_write_p7(data); break;
	429	case 0x18:
	430	if (!m_write_p8.isnull()) m_write_p8(data); break;
	431	case 0x19:
	432	if (!m_write_p9.isnull()) m_write_p9(data); break;
	433	case 0x1A:
	434	if (!m_write_p10.isnull()) m_write_p10(data); break;
	435	case 0x1B:
	436	if (!m_write_p11.isnull()) m_write_p11(data); break;
	437	case 0x1C:
	438	if (!m_write_p12.isnull()) m_write_p12(data); break;
	439	case 0x1D:
	440	if (!m_write_p13.isnull()) m_write_p13(data); break;
	441	case 0x1E:
	442	if (!m_write_p14.isnull()) m_write_p14(data); break;
	443	case 0x1F:
	444	if (!m_write_p15.isnull()) m_write_p15(data); break;
	445
	446	}
	447	return;
	448	}
	449
	450	if (offset == 0)
	451	{
	452	// Write to control bit (CB)
323	453	if (data == 0)
324	454	{
325		/* we are quitting clock mode */
	455	// Switch to interrupt mode; quit clock mode
326	456	m_clock_mode = false;
327		if (VERBOSE>5) LOG("tms9901: int mode\n");
	457	if (TRACE_MODE) logerror("%s: int mode\n", tag());
328	458	}
329	459	else
330	460	{
331	461	m_clock_mode = true;
332		if (VERBOSE>5) LOG("tms9901: clock mode\n");
	462	if (TRACE_MODE) logerror("%s: clock mode\n", tag());
333	463	// we are switching to clock mode: latch the current value of
334	464	// the decrementer register
335	465	if (m_clock_register != 0)
r28744	r28745
337	467	else
338	468	m_clock_read_register = 0;      /* timer inactive... */
339	469	}
340		break;
341		case 0x01:
342		case 0x02:
343		case 0x03:
344		case 0x04:
345		case 0x05:
346		case 0x06:
347		case 0x07:
348		case 0x08:
349		case 0x09:
350		case 0x0A:
351		case 0x0B:
352		case 0x0C:
353		case 0x0D:
354		case 0x0E:
355		// write one bit to 9901 (bits 1-14)
356		//
357		// m_clock_mode==false ?  Disable/Enable an interrupt
358		// :  Bit in clock interval
359		//
360		// offset is the index of the modified bit of register (-> interrupt number -1)
361		if (m_clock_mode)
362		{   /* modify clock interval */
363		int mask = 1 << ((offset & 0x0F) - 1);  /* corresponding mask */
	470	}
	471	else
	472	{
	473	if (offset == 0x0f)
	474	{
	475	if (m_clock_mode)
	476	{   /* in clock mode this is the soft reset bit */
	477	if (!data)
	478	{   // TMS9901 soft reset (RST2*)
	479	// Spec: "Writing a 0 to bit 15 while in the clock mode executes a soft reset on the I/O pins.
	480	// [...] RST2* will program all ports to the input mode"
	481	m_pio_direction = 0;
	482	m_pio_direction_mirror = 0;
364	483
365		if (data)
366		m_clock_register |= mask;       /* set bit */
	484	// "RST1* (power-up reset) will reset all mask bits low."
	485	// Spec is not clear on whether the mask bits are also reset by RST2*
	486	// TODO: Check on a real machine. (I'd guess from the text they are not touched)
	487	m_enabled_ints = 0;
	488	if (TRACE_MODE) logerror("%s: Soft reset (RST2*)\n", tag());
	489	}
	490	}
367	491	else
368		m_clock_register &= ~mask;      /* clear bit */
	492	{   /* modify interrupt enable mask */
	493	if (data)
	494	m_enabled_ints |= 0x4000;       /* set bit */
	495	else
	496	m_enabled_ints &= ~0x4000;      /* unset bit */
369	497
370		/* reset clock timer (page 8) */
371		if (VERBOSE>6) LOG("tms9901: clock register = %04x\n", m_clock_register);
372		timer_reload();
	498	if (TRACE_PINS) logerror("%s: interrupts = %04x\n", tag(), m_enabled_ints);
	499	field_interrupts();     /* changed interrupt state */
	500	}
373	501	}
374	502	else
375		{   /* modify interrupt enable mask */
376		int mask = 1 << (offset & 0x0F);    /* corresponding mask */
	503	{
	504	// write one bit to 9901 (bits 1-14)
	505	//
	506	// m_clock_mode==false ?  Disable/Enable an interrupt
	507	// :  Bit in clock interval
	508	//
	509	// offset is the index of the modified bit of register (-> interrupt number -1)
	510	if (m_clock_mode)
	511	{   /* modify clock interval */
	512	int bit = 1 << ((offset & 0x0F) - 1);  /* corresponding mask */
377	513
378		if (data)
379		m_enabled_ints |= mask;     /* set bit */
380		else
381		m_enabled_ints &= ~mask;        /* unset bit */
	514	if (data)
	515	m_clock_register |= bit;       /* set bit */
	516	else
	517	m_clock_register &= ~bit;      /* clear bit */
382	518
383		if (offset == 3)
384		m_timer_int_pending = false;    /* SBO 3 clears pending timer interrupt (??) */
385
386		if (VERBOSE>6) LOG("tms9901: interrupts = %04x\n", m_enabled_ints);
387		field_interrupts();     /* changed interrupt state */
388		}
389		break;
390		case 0x0F:
391		if (m_clock_mode)
392		{   /* in clock mode this is the soft reset bit */
393		if (!data)
394		{   // TMS9901 soft reset (RST2*)
395		// Spec: "Writing a 0 to bit 15 while in the clock mode executes a soft reset on the I/O pins.
396		// [...] RST2* will program all ports to the input mode"
397		m_pio_direction = 0;
398		m_pio_direction_mirror = 0;
399
400		// "RST1* (power-up reset) will reset all mask bits low."
401		// Spec is not clear on whether the mask bits are also reset by RST2*
402		// TODO: Check on a real machine. (I'd guess from the text they are not touched)
403		m_enabled_ints = 0;
404		if (VERBOSE>5) LOG("tms9901: Soft reset (RST2*)\n");
	519	/* reset clock timer (page 8) */
	520	if (TRACE_CLOCK) logerror("%s: clock register = %04x\n", tag(), m_clock_register);
	521	timer_reload();
405	522	}
406		}
407		else
408		{   /* modify interrupt enable mask */
409		if (data)
410		m_enabled_ints |= 0x4000;       /* set bit */
411	523	else
412		m_enabled_ints &= ~0x4000;      /* unset bit */
	524	{   /* modify interrupt enable mask */
	525	int bit = 1 << (offset & 0x0F);    /* corresponding mask */
413	526
414		if (VERBOSE>6) LOG("tms9901: interrupts = %04x\n", m_enabled_ints);
415		field_interrupts();     /* changed interrupt state */
416		}
417		break;
418		case 0x10:
419		case 0x11:
420		case 0x12:
421		case 0x13:
422		case 0x14:
423		case 0x15:
424		case 0x16:
425		case 0x17:
426		case 0x18:
427		case 0x19:
428		case 0x1A:
429		case 0x1B:
430		case 0x1C:
431		case 0x1D:
432		case 0x1E:
433		case 0x1F:
434		int pin = offset & 0x0F;
435		if (VERBOSE>6) LOG("tms9901: output on P%d = %d\n", pin, data);
436		int mask = (1 << pin);
	527	if (data)
	528	m_enabled_ints |= bit;     /* set bit */
	529	else
	530	m_enabled_ints &= ~bit;        /* unset bit */
437	531
438		// MZ: see above - I think this is wrong
439		// m_clock_mode = false; // exit timer mode
	532	if (offset == 3)
	533	m_timer_int_pending = false;    /* SBO 3 clears pending timer interrupt (??) */
440	534
441		m_pio_direction |= mask;            /* set up as output pin */
442
443		if (data)
444		m_pio_output |= mask;
445		else
446		m_pio_output &= ~mask;
447
448		if (pin >= 7)
449		{   /* pins P7-P15 are mirrored as INT15*-INT7* */
450		int pin2 = 22 - pin;
451		int mask2 = (1 << pin2);
452
453		m_pio_direction_mirror |= mask2;    /* set up as output pin */
454
455		if (data)
456		m_pio_output_mirror |= mask2;
457		else
458		m_pio_output_mirror &= ~ mask2;
	535	if (TRACE_MODE) logerror("%s: enabled interrupts = %04x\n", tag(), m_enabled_ints);
	536	field_interrupts();     /* changed interrupt state */
	537	}
459	538	}
460
461		if (!m_write_line[pin].isnull())
462		(m_write_line[pin])(data);
463
464		break;
465	539	}
466	540	}
467	541
r28744	r28745
476	550	if (id==DECREMENTER) // we have only that one
477	551	{
478	552	m_decrementer_value--;
479		if (VERBOSE>6) LOG("tms9901: decrementer = %d\n", m_decrementer_value);
	553	if (TRACE_CLOCK) logerror("%s: decrementer = %d\n", tag(), m_decrementer_value);
480	554	if (m_decrementer_value<=0)
481	555	{
482	556	m_timer_int_pending = true;         // decrementer interrupt requested
r28744	r28745
507	581	m_pio_direction_mirror = 0;
508	582	m_pio_output = m_pio_output_mirror = 0;
509	583
	584	// This is an interrupt level latch, positive logic (bit 0 = no int)
	585	// The inputs are negative logic (INTx*)
510	586	m_int_state = 0;
	587
511	588	m_old_int_state = -1;
512	589	field_interrupts();
513	590
r28744	r28745
524	601
525	602	void tms9901_device::device_start(void)
526	603	{
527		const tms9901_interface *intf = reinterpret_cast<const tms9901_interface *>(static_config());
528		m_supported_int_mask = intf->interrupt_mask;
529
530	604	m_decrementer = timer_alloc(DECREMENTER);
531	605	m_decrementer->adjust(attotime::from_hz(clock() / 64.), 0, attotime::from_hz(clock() / 64.));
532	606	m_decrementer->enable(false);
533	607
534		m_read_block.resolve(intf->read_handler, *this);
	608	m_read_block.resolve();
	609	m_write_p0.resolve();
	610	m_write_p1.resolve();
	611	m_write_p2.resolve();
	612	m_write_p3.resolve();
	613	m_write_p4.resolve();
	614	m_write_p5.resolve();
	615	m_write_p6.resolve();
	616	m_write_p7.resolve();
	617	m_write_p8.resolve();
	618	m_write_p9.resolve();
	619	m_write_p10.resolve();
	620	m_write_p11.resolve();
	621	m_write_p12.resolve();
	622	m_write_p13.resolve();
	623	m_write_p14.resolve();
	624	m_write_p15.resolve();
	625	m_interrupt.resolve();
535	626
536		for (int i=0; i < 16; i++)
537		{
538		m_write_line[i].resolve(intf->write_handler[i], *this);
539		}
540
541		m_interrupt.resolve(intf->interrupt_callback, *this);
542
543	627	m_clock_register = 0;
544	628	}
545	629

trunk/src/emu/machine/tms9901.h

r28744	r28745
23	23	MACROS
24	24	***************************************************************************/
25	25
26		/* Masks for the interrupts levels available on TMS9901 */
	26	// Masks for the interrupts levels available on TMS9901
	27
27	28	#define TMS9901_INT1 0x0002
28	29	#define TMS9901_INT2 0x0004
29		#define TMS9901_INT3 0x0008     // overriden by the timer interrupt
	30	#define TMS9901_INT3 0x0008     // overridden by the timer interrupt
30	31	#define TMS9901_INT4 0x0010
31	32	#define TMS9901_INT5 0x0020
32	33	#define TMS9901_INT6 0x0040
r28744	r28745
52	53	CLASS DEFINITION
53	54	***************************************************************************/
54	55
55		struct tms9901_interface
56		{
57		int                 interrupt_mask;         // a bit for each input pin whose state is always notified to the TMS9901 core
58		devcb_read8         read_handler;           // 4*8 bits, to be selected using the offset (0-3)
59		devcb_write_line    write_handler[16];      // 16 Pn outputs
60		devcb_write8        interrupt_callback;     // called when interrupt bus state changes
61		};
62
63	56	class tms9901_device : public device_t
64	57	{
65	58	public:
r28744	r28745
70	63	DECLARE_READ8_MEMBER( read );
71	64	DECLARE_WRITE8_MEMBER( write );
72	65
	66	template<class _Object> static devcb2_base &static_set_readblock_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_read_block.set_callback(object); }
	67
	68	template<class _Object> static devcb2_base &static_set_p0_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p0.set_callback(object); }
	69	template<class _Object> static devcb2_base &static_set_p1_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p1.set_callback(object); }
	70	template<class _Object> static devcb2_base &static_set_p2_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p2.set_callback(object); }
	71	template<class _Object> static devcb2_base &static_set_p3_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p3.set_callback(object); }
	72	template<class _Object> static devcb2_base &static_set_p4_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p4.set_callback(object); }
	73	template<class _Object> static devcb2_base &static_set_p5_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p5.set_callback(object); }
	74	template<class _Object> static devcb2_base &static_set_p6_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p6.set_callback(object); }
	75	template<class _Object> static devcb2_base &static_set_p7_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p7.set_callback(object); }
	76	template<class _Object> static devcb2_base &static_set_p8_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p8.set_callback(object); }
	77	template<class _Object> static devcb2_base &static_set_p9_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p9.set_callback(object); }
	78	template<class _Object> static devcb2_base &static_set_p10_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p10.set_callback(object); }
	79	template<class _Object> static devcb2_base &static_set_p11_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p11.set_callback(object); }
	80	template<class _Object> static devcb2_base &static_set_p12_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p12.set_callback(object); }
	81	template<class _Object> static devcb2_base &static_set_p13_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p13.set_callback(object); }
	82	template<class _Object> static devcb2_base &static_set_p14_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p14.set_callback(object); }
	83	template<class _Object> static devcb2_base &static_set_p15_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_write_p15.set_callback(object); }
	84
	85	template<class _Object> static devcb2_base &static_set_intlevel_callback(device_t &device, _Object object)  { return downcast<tms9901_device &>(device).m_interrupt.set_callback(object); }
	86
73	87	private:
74	88	static const device_timer_id DECREMENTER = 0;
75	89
r28744	r28745
77	91	void timer_reload(void);
78	92	void field_interrupts(void);
79	93
80		virtual void device_start(void);
81		virtual void device_stop(void);
82		virtual void device_reset(void);
	94	void device_start(void);
	95	void device_stop(void);
	96	void device_reset(void);
83	97
84		/* interrupt registers */
85		// mask:  bit #n is set if pin #n is supported as an interrupt pin,
86		// i.e. the driver sends a notification whenever the pin state changes
87		// setting these bits is not required, but it saves you the trouble of
88		// saving the state of interrupt pins and feeding it to the port read
89		// handlers again
90		int m_supported_int_mask;
91		int m_int_state;            // state of the int1-int15 lines (must be inverted when queried)
	98	// State of the INT1-INT15 lines (must be inverted when queried)
	99	// Note that the levels must also be delivered when reading the pins, which
	100	// may require to latch the int levels.
	101	int m_int_state;
92	102	int m_old_int_state;        // stores the previous value to avoid useless INT line assertions
93	103	int m_enabled_ints;         // interrupt enable mask
94	104
r28744	r28745
127	137
128	138	// =======================================================================
129	139
130		// Callbacks
131		devcb_resolved_read8        m_read_block;
132		devcb_resolved_write_line   m_write_line[16];
133		devcb_resolved_write8       m_interrupt;  // also delivers the interrupt level
	140	// Read callback.
	141	devcb2_read8        m_read_block;
	142
	143	// I/O lines, used for output. When used as inputs, the levels are delivered via the m_read_block
	144	devcb2_write_line   m_write_p0;
	145	devcb2_write_line   m_write_p1;
	146	devcb2_write_line   m_write_p2;
	147	devcb2_write_line   m_write_p3;
	148	devcb2_write_line   m_write_p4;
	149	devcb2_write_line   m_write_p5;
	150	devcb2_write_line   m_write_p6;
	151	devcb2_write_line   m_write_p7;
	152	devcb2_write_line   m_write_p8;
	153	devcb2_write_line   m_write_p9;
	154	devcb2_write_line   m_write_p10;
	155	devcb2_write_line   m_write_p11;
	156	devcb2_write_line   m_write_p12;
	157	devcb2_write_line   m_write_p13;
	158	devcb2_write_line   m_write_p14;
	159	devcb2_write_line   m_write_p15;
	160
	161	// The invocation corresponds to the INTREQ signal (with the level passed as data)
	162	// and the address delivers the interrupt level (0-15)
	163	devcb2_write8       m_interrupt;
134	164	};
135	165
136	166	/***************************************************************************
137	167	DEVICE CONFIGURATION MACROS
138	168	***************************************************************************/
139	169
140		#define MCFG_TMS9901_ADD(_tag, _intrf, _rate) \
141		MCFG_DEVICE_ADD(_tag, TMS9901, _rate) \
142		MCFG_DEVICE_CONFIG(_intrf)
	170	#define MCFG_TMS9901_READBLOCK_HANDLER( _read ) \
	171	devcb = &tms9901_device::static_set_readblock_callback( *device, DEVCB2_##_read );
143	172
	173	#define MCFG_TMS9901_P0_HANDLER( _write ) \
	174	devcb = &tms9901_device::static_set_p0_callback( *device, DEVCB2_##_write );
	175
	176	#define MCFG_TMS9901_P1_HANDLER( _write ) \
	177	devcb = &tms9901_device::static_set_p1_callback( *device, DEVCB2_##_write );
	178
	179	#define MCFG_TMS9901_P2_HANDLER( _write ) \
	180	devcb = &tms9901_device::static_set_p2_callback( *device, DEVCB2_##_write );
	181
	182	#define MCFG_TMS9901_P3_HANDLER( _write ) \
	183	devcb = &tms9901_device::static_set_p3_callback( *device, DEVCB2_##_write );
	184
	185	#define MCFG_TMS9901_P4_HANDLER( _write ) \
	186	devcb = &tms9901_device::static_set_p4_callback( *device, DEVCB2_##_write );
	187
	188	#define MCFG_TMS9901_P5_HANDLER( _write ) \
	189	devcb = &tms9901_device::static_set_p5_callback( *device, DEVCB2_##_write );
	190
	191	#define MCFG_TMS9901_P6_HANDLER( _write ) \
	192	devcb = &tms9901_device::static_set_p6_callback( *device, DEVCB2_##_write );
	193
	194	#define MCFG_TMS9901_P7_HANDLER( _write ) \
	195	devcb = &tms9901_device::static_set_p7_callback( *device, DEVCB2_##_write );
	196
	197	#define MCFG_TMS9901_P8_HANDLER( _write ) \
	198	devcb = &tms9901_device::static_set_p8_callback( *device, DEVCB2_##_write );
	199
	200	#define MCFG_TMS9901_P9_HANDLER( _write ) \
	201	devcb = &tms9901_device::static_set_p9_callback( *device, DEVCB2_##_write );
	202
	203	#define MCFG_TMS9901_P10_HANDLER( _write ) \
	204	devcb = &tms9901_device::static_set_p10_callback( *device, DEVCB2_##_write );
	205
	206	#define MCFG_TMS9901_P11_HANDLER( _write ) \
	207	devcb = &tms9901_device::static_set_p11_callback( *device, DEVCB2_##_write );
	208
	209	#define MCFG_TMS9901_P12_HANDLER( _write ) \
	210	devcb = &tms9901_device::static_set_p12_callback( *device, DEVCB2_##_write );
	211
	212	#define MCFG_TMS9901_P13_HANDLER( _write ) \
	213	devcb = &tms9901_device::static_set_p13_callback( *device, DEVCB2_##_write );
	214
	215	#define MCFG_TMS9901_P14_HANDLER( _write ) \
	216	devcb = &tms9901_device::static_set_p14_callback( *device, DEVCB2_##_write );
	217
	218	#define MCFG_TMS9901_P15_HANDLER( _write ) \
	219	devcb = &tms9901_device::static_set_p15_callback( *device, DEVCB2_##_write );
	220
	221	#define MCFG_TMS9901_INTLEVEL_HANDLER( _intlevel ) \
	222	devcb = &tms9901_device::static_set_intlevel_callback( *device, DEVCB2_##_intlevel );
	223
144	224	#endif /* __TMS9901_H__ */

trunk/src/mess/drivers/ti99_4x.c

r28744	r28745
137	137	void    console_ready_join(int id, int state);
138	138
139	139	// Console type
140		int    m_console;
	140	int    m_console;
141	141
	142	// Latch for 9901 INT2, INT1 lines
	143	int     m_9901_int;
	144	void    set_9901_int(int line, line_state state);
	145
142	146	// Connected devices
143	147	required_device<tms9900_device>     m_cpu;
144	148	required_device<tms9901_device>     m_tms9901;
r28744	r28745
443	447	case TMS9901_CB_INT7:
444	448	//
445	449	// Read pins INT3*-INT7* of TI99's 9901.
446		// bit 1: INT1 status (interrupt; not set at this place)
447		// bit 2: INT2 status (interrupt; not set at this place)
	450	// bit 1: INT1 status
	451	// bit 2: INT2 status
448	452	// bit 3-7: keyboard status bits 0 to 4
449	453	//
450	454	// |K|K|K|K|K|I2|I1|C|
r28744	r28745
470	474	{
471	475	answer &= ~(ioport("ALPHA")->read());
472	476	}
473		answer = (answer << 3) & 0xf8;
	477	answer = (answer << 3) | m_9901_int;
474	478
475	479	break;
476	480
r28744	r28745
631	635
632	636	/*****************************************************************************/
633	637
	638	void ti99_4x_state::set_9901_int( int line, line_state state)
	639	{
	640	m_tms9901->set_single_int(line, state);
	641	// We latch the value for the read operation. Mind the negative logic.
	642	if (state==CLEAR_LINE) m_9901_int |= (1<<line);
	643	else m_9901_int &= ~(1<<line);
	644	}
	645
634	646	/*
635	647	set the state of TMS9901's INT2 (called by the tms9928 core)
636	648	*/
637	649	WRITE_LINE_MEMBER( ti99_4x_state::set_tms9901_INT2 )
638	650	{
639	651	if (TRACE_INTERRUPTS) LOG("ti99_4x: VDP int 2 on tms9901, level=%d\n", state);
640		m_tms9901->set_single_int(2, state);
	652	set_9901_int(2, (line_state)state);
641	653	}
642	654
643	655	WRITE_LINE_MEMBER(ti99_4x_state::set_tms9901_INT2_from_v9938)
644	656	{
645	657	if (TRACE_INTERRUPTS) LOG("ti99_4x: VDP int 2 on tms9901, level=%d\n", state);
646		m_tms9901->set_single_int(2, state);
	658	set_9901_int(2, (line_state)state);
647	659	}
648	660
649	661	/*
r28744	r28745
652	664	WRITE_LINE_MEMBER( ti99_4x_state::set_tms9901_INT12)
653	665	{
654	666	if (TRACE_INTERRUPTS) LOG("ti99_4x: joyport INT 12 on tms9901, level=%d\n", state);
655		m_tms9901->set_single_int(12, state);
	667	set_9901_int(12, (line_state)state);
656	668	}
657	669
658	670	/*
r28744	r28745
736	748	WRITE_LINE_MEMBER( ti99_4x_state::extint )
737	749	{
738	750	if (TRACE_INTERRUPTS) LOG("ti99_4x: EXTINT level = %02x\n", state);
739		if (m_tms9901 != NULL)
740		m_tms9901->set_single_int(1, state);
	751	set_9901_int(1, (line_state)state);
741	752	}
742	753
743	754	WRITE_LINE_MEMBER( ti99_4x_state::notconnected )
r28744	r28745
753	764	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, set_tms9901_INT2)
754	765	};
755	766
756		/* TMS9901 setup. */
	767	/* TMS9901 setup.
757	768	const tms9901_interface tms9901_wiring_ti99_4 =
758	769	{
759		TMS9901_INT1 | TMS9901_INT2 | TMS9901_INTC, /* only input pins whose state is always known */
	770	TMS9901_INT1 | TMS9901_INT2 | TMS9901_INTC, // only input pins whose state is always known
760	771
761		// read handler
762		DEVCB_DRIVER_MEMBER(ti99_4x_state, read_by_9901),
	772	// read handler
	773	DEVCB_DRIVER_MEMBER(ti99_4x_state, read_by_9901),
763	774
764		// write handlers
765		{
766		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, handset_ack),
767		DEVCB_NULL,
768		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC0),
769		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC1),
770		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC2),
771		DEVCB_NULL,
772		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cs1_motor),
773		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cs2_motor),
774		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, audio_gate),
775		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cassette_output),
776		DEVCB_NULL,
777		DEVCB_NULL,
778		DEVCB_NULL,
779		DEVCB_NULL,
780		DEVCB_NULL,
781		DEVCB_NULL
782		},
	775	// write handlers
	776	{
	777	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, handset_ack),
	778	DEVCB_NULL,
	779	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC0),
	780	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC1),
	781	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC2),
	782	DEVCB_NULL,
	783	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cs1_motor),
	784	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cs2_motor),
	785	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, audio_gate),
	786	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cassette_output),
	787	DEVCB_NULL,
	788	DEVCB_NULL,
	789	DEVCB_NULL,
	790	DEVCB_NULL,
	791	DEVCB_NULL,
	792	DEVCB_NULL
	793	},
783	794
784		// interrupt handler
785		DEVCB_DRIVER_MEMBER(ti99_4x_state, tms9901_interrupt)
	795	// interrupt handler
	796	DEVCB_DRIVER_MEMBER(ti99_4x_state, tms9901_interrupt)
786	797	};
	798	*/
787	799
	800	/*
788	801	const tms9901_interface tms9901_wiring_ti99_4a =
789	802	{
790		TMS9901_INT1 | TMS9901_INT2 | TMS9901_INTC,
	803	TMS9901_INT1 | TMS9901_INT2 | TMS9901_INTC,
791	804
792		// read handler
793		DEVCB_DRIVER_MEMBER(ti99_4x_state, read_by_9901),
	805	// read handler
	806	DEVCB_DRIVER_MEMBER(ti99_4x_state, read_by_9901),
794	807
795		// write handlers
796		{
797		DEVCB_NULL,
798		DEVCB_NULL,
799		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC0),
800		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC1),
801		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC2),
802		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, alphaW),
803		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cs1_motor),
804		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cs2_motor),
805		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, audio_gate),
806		DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cassette_output),
807		DEVCB_NULL,
808		DEVCB_NULL,
809		DEVCB_NULL,
810		DEVCB_NULL,
811		DEVCB_NULL,
812		DEVCB_NULL
813		},
	808	// write handlers
	809	{
	810	DEVCB_NULL,
	811	DEVCB_NULL,
	812	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC0),
	813	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC1),
	814	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, keyC2),
	815	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, alphaW),
	816	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cs1_motor),
	817	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cs2_motor),
	818	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, audio_gate),
	819	DEVCB_DRIVER_LINE_MEMBER(ti99_4x_state, cassette_output),
	820	DEVCB_NULL,
	821	DEVCB_NULL,
	822	DEVCB_NULL,
	823	DEVCB_NULL,
	824	DEVCB_NULL,
	825	DEVCB_NULL
	826	},
814	827
815		DEVCB_DRIVER_MEMBER(ti99_4x_state, tms9901_interrupt)
	828	DEVCB_DRIVER_MEMBER(ti99_4x_state, tms9901_interrupt)
816	829	};
	830	*/
817	831
818	832	/*
819	833	Devices attached to the databus multiplexer. We cannot solve this with
r28744	r28745
886	900	{
887	901	m_cpu->set_ready(ASSERT_LINE);
888	902	m_cpu->set_hold(CLEAR_LINE);
	903	m_9901_int = 0x03; // INT2* and INT1* set to 1, i.e. inactive
889	904	}
890	905
891	906	/*
r28744	r28745
901	916	MCFG_TI_TMS991x_ADD_NTSC(VIDEO_SYSTEM_TAG, TMS9918, ti99_4_tms9928a_interface)
902	917
903	918	/* Main board */
904		MCFG_TMS9901_ADD(TMS9901_TAG, tms9901_wiring_ti99_4, 3000000)
	919	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, 3000000)
	920	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_4x_state, read_by_9901) )
	921	MCFG_TMS9901_P0_HANDLER( WRITELINE( ti99_4x_state, handset_ack) )
	922	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_4x_state, keyC0) )
	923	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_4x_state, keyC1) )
	924	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_4x_state, keyC2) )
	925	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_4x_state, cs1_motor) )
	926	MCFG_TMS9901_P7_HANDLER( WRITELINE( ti99_4x_state, cs2_motor) )
	927	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_4x_state, audio_gate) )
	928	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_4x_state, cassette_output) )
	929	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_4x_state, tms9901_interrupt) )
	930
905	931	MCFG_DMUX_ADD( DATAMUX_TAG, datamux_conf )
906	932	MCFG_DMUX_READY_HANDLER( WRITELINE(ti99_4x_state, console_ready_dmux) )
907	933	MCFG_TI99_GROMPORT_ADD( GROMPORT_TAG )
r28744	r28745
953	979	/* video hardware */
954	980	MCFG_TI_TMS991x_ADD_PAL(VIDEO_SYSTEM_TAG, TMS9929, ti99_4_tms9928a_interface)
955	981
956		/* main board */
957		MCFG_TMS9901_ADD(TMS9901_TAG, tms9901_wiring_ti99_4, 3000000)
	982	/* Main board */
	983	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, 3000000)
	984	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_4x_state, read_by_9901) )
	985	MCFG_TMS9901_P0_HANDLER( WRITELINE( ti99_4x_state, handset_ack) )
	986	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_4x_state, keyC0) )
	987	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_4x_state, keyC1) )
	988	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_4x_state, keyC2) )
	989	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_4x_state, cs1_motor) )
	990	MCFG_TMS9901_P7_HANDLER( WRITELINE( ti99_4x_state, cs2_motor) )
	991	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_4x_state, audio_gate) )
	992	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_4x_state, cassette_output) )
	993	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_4x_state, tms9901_interrupt) )
	994
958	995	MCFG_DMUX_ADD( DATAMUX_TAG, datamux_conf )
959	996	MCFG_DMUX_READY_HANDLER( WRITELINE(ti99_4x_state, console_ready_dmux) )
960	997
r28744	r28745
1026	1063	MCFG_TI_TMS991x_ADD_NTSC(VIDEO_SYSTEM_TAG, TMS9918A, ti99_4_tms9928a_interface)
1027	1064
1028	1065	/* Main board */
1029		MCFG_TMS9901_ADD(TMS9901_TAG, tms9901_wiring_ti99_4a, 3000000)
	1066	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, 3000000)
	1067	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_4x_state, read_by_9901) )
	1068	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_4x_state, keyC0) )
	1069	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_4x_state, keyC1) )
	1070	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_4x_state, keyC2) )
	1071	MCFG_TMS9901_P5_HANDLER( WRITELINE( ti99_4x_state, alphaW) )
	1072	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_4x_state, cs1_motor) )
	1073	MCFG_TMS9901_P7_HANDLER( WRITELINE( ti99_4x_state, cs2_motor) )
	1074	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_4x_state, audio_gate) )
	1075	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_4x_state, cassette_output) )
	1076	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_4x_state, tms9901_interrupt) )
	1077
1030	1078	MCFG_DMUX_ADD( DATAMUX_TAG, datamux_conf )
1031	1079	MCFG_DMUX_READY_HANDLER( WRITELINE(ti99_4x_state, console_ready_dmux) )
1032	1080	MCFG_TI99_GROMPORT_ADD( GROMPORT_TAG )
r28744	r28745
1078	1126	MCFG_TI_TMS991x_ADD_PAL(VIDEO_SYSTEM_TAG, TMS9929A, ti99_4_tms9928a_interface)
1079	1127
1080	1128	/* Main board */
1081		MCFG_TMS9901_ADD(TMS9901_TAG, tms9901_wiring_ti99_4a, 3000000)
	1129	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, 3000000)
	1130	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_4x_state, read_by_9901) )
	1131	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_4x_state, keyC0) )
	1132	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_4x_state, keyC1) )
	1133	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_4x_state, keyC2) )
	1134	MCFG_TMS9901_P5_HANDLER( WRITELINE( ti99_4x_state, alphaW) )
	1135	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_4x_state, cs1_motor) )
	1136	MCFG_TMS9901_P7_HANDLER( WRITELINE( ti99_4x_state, cs2_motor) )
	1137	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_4x_state, audio_gate) )
	1138	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_4x_state, cassette_output) )
	1139	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_4x_state, tms9901_interrupt) )
	1140
1082	1141	MCFG_DMUX_ADD( DATAMUX_TAG, datamux_conf )
1083	1142	MCFG_DMUX_READY_HANDLER( WRITELINE(ti99_4x_state, console_ready_dmux) )
1084	1143	MCFG_TI99_GROMPORT_ADD( GROMPORT_TAG )
r28744	r28745
1147	1206	MCFG_TI_TMS991x_ADD_NTSC(VIDEO_SYSTEM_TAG, TMS9918A, ti99_4_tms9928a_interface)
1148	1207
1149	1208	/* Main board */
1150		MCFG_TMS9901_ADD(TMS9901_TAG, tms9901_wiring_ti99_4a, 3000000)
	1209	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, 3000000)
	1210	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_4x_state, read_by_9901) )
	1211	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_4x_state, keyC0) )
	1212	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_4x_state, keyC1) )
	1213	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_4x_state, keyC2) )
	1214	MCFG_TMS9901_P5_HANDLER( WRITELINE( ti99_4x_state, alphaW) )
	1215	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_4x_state, cs1_motor) )
	1216	MCFG_TMS9901_P7_HANDLER( WRITELINE( ti99_4x_state, cs2_motor) )
	1217	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_4x_state, audio_gate) )
	1218	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_4x_state, cassette_output) )
	1219	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_4x_state, tms9901_interrupt) )
	1220
1151	1221	MCFG_DMUX_ADD( DATAMUX_TAG, datamux_conf )
1152	1222	MCFG_DMUX_READY_HANDLER( WRITELINE(ti99_4x_state, console_ready_dmux) )
1153	1223	MCFG_TI99_GROMPORT_ADD( GROMPORT_TAG )
r28744	r28745
1199	1269	MCFG_TI_TMS991x_ADD_PAL(VIDEO_SYSTEM_TAG, TMS9929A, ti99_4_tms9928a_interface)
1200	1270
1201	1271	/* Main board */
1202		MCFG_TMS9901_ADD(TMS9901_TAG, tms9901_wiring_ti99_4a, 3000000)
	1272	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, 3000000)
	1273	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_4x_state, read_by_9901) )
	1274	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_4x_state, keyC0) )
	1275	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_4x_state, keyC1) )
	1276	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_4x_state, keyC2) )
	1277	MCFG_TMS9901_P5_HANDLER( WRITELINE( ti99_4x_state, alphaW) )
	1278	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_4x_state, cs1_motor) )
	1279	MCFG_TMS9901_P7_HANDLER( WRITELINE( ti99_4x_state, cs2_motor) )
	1280	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_4x_state, audio_gate) )
	1281	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_4x_state, cassette_output) )
	1282	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_4x_state, tms9901_interrupt) )
	1283
1203	1284	MCFG_DMUX_ADD( DATAMUX_TAG, datamux_conf )
1204	1285	MCFG_DMUX_READY_HANDLER( WRITELINE(ti99_4x_state, console_ready_dmux) )
1205	1286	MCFG_TI99_GROMPORT_ADD( GROMPORT_TAG )
r28744	r28745
1267	1348	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", ti99_4x_state, ti99_4ev_hblank_interrupt, SCREEN_TAG, 0, 1)
1268	1349
1269	1350	/* Main board */
1270		MCFG_TMS9901_ADD(TMS9901_TAG, tms9901_wiring_ti99_4a, 3000000)
	1351	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, 3000000)
	1352	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_4x_state, read_by_9901) )
	1353	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_4x_state, keyC0) )
	1354	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_4x_state, keyC1) )
	1355	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_4x_state, keyC2) )
	1356	MCFG_TMS9901_P5_HANDLER( WRITELINE( ti99_4x_state, alphaW) )
	1357	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_4x_state, cs1_motor) )
	1358	MCFG_TMS9901_P7_HANDLER( WRITELINE( ti99_4x_state, cs2_motor) )
	1359	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_4x_state, audio_gate) )
	1360	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_4x_state, cassette_output) )
	1361	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_4x_state, tms9901_interrupt) )
	1362
1271	1363	MCFG_DMUX_ADD( DATAMUX_TAG, datamux_conf_ev )
1272	1364	MCFG_DMUX_READY_HANDLER( WRITELINE(ti99_4x_state, console_ready_dmux) )
1273	1365	MCFG_TI99_GROMPORT_ADD( GROMPORT_TAG )

trunk/src/mess/drivers/tm990189.c

r28744	r28745
70	70	#include "tm990189.lh"
71	71	#include "tm990189v.lh"
72	72
	73	#define TMS9901_0_TAG "tms9901_usr"
	74	#define TMS9901_1_TAG "tms9901_sys"
73	75
74	76	class tm990189_state : public driver_device
75	77	{
r28744	r28745
81	83	m_cass(*this, "cassette"),
82	84	m_tms9918(*this, "tms9918" ),
83	85	m_maincpu(*this, "maincpu"),
84		m_cassette(*this, "cassette") { }
	86	m_cassette(*this, "cassette"),
	87	m_tms9901_usr(*this, TMS9901_0_TAG),
	88	m_tms9901_sys(*this, TMS9901_1_TAG) { }
85	89
86	90	required_device<tms9980a_device> m_tms9980a;
87	91	required_device<speaker_sound_device> m_speaker;
r28744	r28745
158	162	void digitsel(int offset, bool state);
159	163	required_device<cpu_device> m_maincpu;
160	164	required_device<cassette_image_device> m_cassette;
	165	required_device<tms9901_device>     m_tms9901_usr;
	166	required_device<tms9901_device>     m_tms9901_sys;
161	167	};
162	168
163	169
r28744	r28745
304	310
305	311	WRITE8_MEMBER( tm990189_state::sys9901_interrupt_callback )
306	312	{
307		machine().device<tms9901_device>("tms9901_0")->set_single_int(5, (data!=0)? ASSERT_LINE:CLEAR_LINE);
	313	// machine().device<tms9901_device>("tms9901_0")->set_single_int(5, (data!=0)? ASSERT_LINE:CLEAR_LINE);
	314	// TODO: Check this
	315	m_tms9901_usr->set_single_int(5, (data!=0)? ASSERT_LINE:CLEAR_LINE);
308	316	}
309	317
310	318	READ8_MEMBER( tm990189_state::sys9901_r )
r28744	r28745
624	632	m_joy2y_timer->reset(attotime::from_usec(ioport("JOY2_Y")->read()*28+28));
625	633	}
626	634
627		/* user tms9901 setup */
	635	/*
	636	// user tms9901 setup
628	637	static const tms9901_interface usr9901reset_param =
629	638	{
630		TMS9901_INT1 | TMS9901_INT2 | TMS9901_INT3 | TMS9901_INT4 | TMS9901_INT5 | TMS9901_INT6,    /* only input pins whose state is always known */
	639	TMS9901_INT1 | TMS9901_INT2 | TMS9901_INT3 | TMS9901_INT4 | TMS9901_INT5 | TMS9901_INT6,    // only input pins whose state is always known
631	640
632		/* Read handler. Covers all input lines (see tms9901.h) */
633		DEVCB_NULL,
	641	// Read handler. Covers all input lines (see tms9901.h)
	642	DEVCB_NULL,
634	643
635		/* write handlers */
636		{
637		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, usr9901_led0_w),
638		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, usr9901_led1_w),
639		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, usr9901_led2_w),
640		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, usr9901_led3_w),
641		DEVCB_NULL,
642		DEVCB_NULL,
643		DEVCB_NULL,
644		DEVCB_NULL,
645		DEVCB_NULL,
646		DEVCB_NULL,
647		DEVCB_NULL,
648		DEVCB_NULL,
649		DEVCB_NULL,
650		DEVCB_NULL,
651		DEVCB_NULL,
652		DEVCB_NULL
653		},
	644	// write handlers
	645	{
	646	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, usr9901_led0_w),
	647	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, usr9901_led1_w),
	648	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, usr9901_led2_w),
	649	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, usr9901_led3_w),
	650	DEVCB_NULL,
	651	DEVCB_NULL,
	652	DEVCB_NULL,
	653	DEVCB_NULL,
	654	DEVCB_NULL,
	655	DEVCB_NULL,
	656	DEVCB_NULL,
	657	DEVCB_NULL,
	658	DEVCB_NULL,
	659	DEVCB_NULL,
	660	DEVCB_NULL,
	661	DEVCB_NULL
	662	},
654	663
655		/* interrupt handler */
656		DEVCB_DRIVER_MEMBER(tm990189_state, usr9901_interrupt_callback)
	664	// interrupt handler
	665	DEVCB_DRIVER_MEMBER(tm990189_state, usr9901_interrupt_callback)
657	666	};
	667	*/
658	668
659		/* system tms9901 setup */
	669	/*
	670	// system tms9901 setup
660	671	static const tms9901_interface sys9901reset_param =
661	672	{
662		0,  /* only input pins whose state is always known */
	673	0,  // only input pins whose state is always known
663	674
664		/* Read handler. Covers all input lines (see tms9901.h) */
665		DEVCB_DRIVER_MEMBER(tm990189_state, sys9901_r),
	675	// Read handler. Covers all input lines (see tms9901.h)
	676	DEVCB_DRIVER_MEMBER(tm990189_state, sys9901_r),
666	677
667		/* write handlers */
668		{
669		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_digitsel0_w),
670		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_digitsel1_w),
671		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_digitsel2_w),
672		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_digitsel3_w),
673		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment0_w),
674		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment1_w),
675		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment2_w),
676		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment3_w),
677		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment4_w),
678		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment5_w),
679		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment6_w),
680		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment7_w),
681		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_dsplytrgr_w),
682		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_shiftlight_w),
683		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_spkrdrive_w),
684		DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_tapewdata_w)
685		},
	678	// write handlers
	679	{
	680	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_digitsel0_w),
	681	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_digitsel1_w),
	682	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_digitsel2_w),
	683	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_digitsel3_w),
	684	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment0_w),
	685	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment1_w),
	686	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment2_w),
	687	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment3_w),
	688	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment4_w),
	689	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment5_w),
	690	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment6_w),
	691	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_segment7_w),
	692	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_dsplytrgr_w),
	693	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_shiftlight_w),
	694	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_spkrdrive_w),
	695	DEVCB_DRIVER_LINE_MEMBER(tm990189_state, sys9901_tapewdata_w)
	696	},
686	697
687		/* interrupt handler */
688		DEVCB_DRIVER_MEMBER(tm990189_state, sys9901_interrupt_callback)
	698	// interrupt handler
	699	DEVCB_DRIVER_MEMBER(tm990189_state, sys9901_interrupt_callback)
689	700	};
690	701
	702	*/
	703
691	704	/*
692	705	Memory map:
693	706
r28744	r28745
800	813	*/
801	814
802	815	static ADDRESS_MAP_START( tm990_189_cru_map, AS_IO, 8, tm990189_state )
803		AM_RANGE(0x0000, 0x003f) AM_DEVREAD("tms9901_0", tms9901_device, read)      /* user I/O tms9901 */
804		AM_RANGE(0x0040, 0x006f) AM_DEVREAD("tms9901_1", tms9901_device, read)      /* system I/O tms9901 */
	816	AM_RANGE(0x0000, 0x003f) AM_DEVREAD(TMS9901_0_TAG, tms9901_device, read)      /* user I/O tms9901 */
	817	AM_RANGE(0x0040, 0x006f) AM_DEVREAD(TMS9901_1_TAG, tms9901_device, read)      /* system I/O tms9901 */
805	818	AM_RANGE(0x0080, 0x00cf) AM_DEVREAD("tms9902", tms9902_device, cruread)     /* optional tms9902 */
806	819
807		AM_RANGE(0x0000, 0x01ff) AM_DEVWRITE("tms9901_0", tms9901_device, write)    /* user I/O tms9901 */
808		AM_RANGE(0x0200, 0x03ff) AM_DEVWRITE("tms9901_1", tms9901_device, write)    /* system I/O tms9901 */
	820	AM_RANGE(0x0000, 0x01ff) AM_DEVWRITE(TMS9901_0_TAG, tms9901_device, write)    /* user I/O tms9901 */
	821	AM_RANGE(0x0200, 0x03ff) AM_DEVWRITE(TMS9901_1_TAG, tms9901_device, write)    /* system I/O tms9901 */
809	822	AM_RANGE(0x0400, 0x05ff) AM_DEVWRITE("tms9902", tms9902_device, cruwrite)   /* optional tms9902 */
810	823	ADDRESS_MAP_END
811	824
r28744	r28745
837	850
838	851	/* Devices */
839	852	MCFG_CASSETTE_ADD( "cassette", default_cassette_interface )
840		MCFG_TMS9901_ADD("tms9901_0", usr9901reset_param, 2000000)
841		MCFG_TMS9901_ADD("tms9901_1", sys9901reset_param, 2000000)
	853
	854	MCFG_DEVICE_ADD(TMS9901_0_TAG, TMS9901, 2000000)
	855	MCFG_TMS9901_P0_HANDLER( WRITELINE( tm990189_state, usr9901_led0_w) )
	856	MCFG_TMS9901_P1_HANDLER( WRITELINE( tm990189_state, usr9901_led1_w) )
	857	MCFG_TMS9901_P2_HANDLER( WRITELINE( tm990189_state, usr9901_led2_w) )
	858	MCFG_TMS9901_P3_HANDLER( WRITELINE( tm990189_state, usr9901_led3_w) )
	859	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( tm990189_state, usr9901_interrupt_callback) )
	860
	861	MCFG_DEVICE_ADD(TMS9901_1_TAG, TMS9901, 2000000)
	862	MCFG_TMS9901_READBLOCK_HANDLER( READ8(tm990189_state, sys9901_r) )
	863	MCFG_TMS9901_P0_HANDLER( WRITELINE( tm990189_state, sys9901_digitsel0_w) )
	864	MCFG_TMS9901_P1_HANDLER( WRITELINE( tm990189_state, sys9901_digitsel1_w) )
	865	MCFG_TMS9901_P2_HANDLER( WRITELINE( tm990189_state, sys9901_digitsel2_w) )
	866	MCFG_TMS9901_P3_HANDLER( WRITELINE( tm990189_state, sys9901_digitsel3_w) )
	867	MCFG_TMS9901_P4_HANDLER( WRITELINE( tm990189_state, sys9901_segment0_w) )
	868	MCFG_TMS9901_P5_HANDLER( WRITELINE( tm990189_state, sys9901_segment1_w) )
	869	MCFG_TMS9901_P6_HANDLER( WRITELINE( tm990189_state, sys9901_segment2_w) )
	870	MCFG_TMS9901_P7_HANDLER( WRITELINE( tm990189_state, sys9901_segment3_w) )
	871	MCFG_TMS9901_P8_HANDLER( WRITELINE( tm990189_state, sys9901_segment4_w) )
	872	MCFG_TMS9901_P9_HANDLER( WRITELINE( tm990189_state, sys9901_segment5_w) )
	873	MCFG_TMS9901_P10_HANDLER( WRITELINE( tm990189_state, sys9901_segment6_w) )
	874	MCFG_TMS9901_P11_HANDLER( WRITELINE( tm990189_state, sys9901_segment7_w) )
	875	MCFG_TMS9901_P12_HANDLER( WRITELINE( tm990189_state, sys9901_dsplytrgr_w) )
	876	MCFG_TMS9901_P13_HANDLER( WRITELINE( tm990189_state, sys9901_shiftlight_w) )
	877	MCFG_TMS9901_P14_HANDLER( WRITELINE( tm990189_state, sys9901_spkrdrive_w) )
	878	MCFG_TMS9901_P15_HANDLER( WRITELINE( tm990189_state, sys9901_tapewdata_w) )
	879	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( tm990189_state, sys9901_interrupt_callback) )
	880
842	881	MCFG_TMS9902_ADD("tms9902", tms9902_params, 2000000)
843	882	MCFG_TM990_189_RS232_ADD("rs232")
844	883	MCFG_TIMER_DRIVER_ADD_PERIODIC("display_timer", tm990189_state, display_callback, attotime::from_hz(30))
r28744	r28745
869	908
870	909	/* Devices */
871	910	MCFG_CASSETTE_ADD( "cassette", default_cassette_interface )
872		MCFG_TMS9901_ADD("tms9901_0", usr9901reset_param, 2000000)
873		MCFG_TMS9901_ADD("tms9901_1", sys9901reset_param, 2000000)
	911	MCFG_DEVICE_ADD(TMS9901_0_TAG, TMS9901, 2000000)
	912	MCFG_TMS9901_P0_HANDLER( WRITELINE( tm990189_state, usr9901_led0_w) )
	913	MCFG_TMS9901_P1_HANDLER( WRITELINE( tm990189_state, usr9901_led1_w) )
	914	MCFG_TMS9901_P2_HANDLER( WRITELINE( tm990189_state, usr9901_led2_w) )
	915	MCFG_TMS9901_P3_HANDLER( WRITELINE( tm990189_state, usr9901_led3_w) )
	916	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( tm990189_state, usr9901_interrupt_callback) )
	917
	918	MCFG_DEVICE_ADD(TMS9901_1_TAG, TMS9901, 2000000)
	919	MCFG_TMS9901_READBLOCK_HANDLER( READ8(tm990189_state, sys9901_r) )
	920	MCFG_TMS9901_P0_HANDLER( WRITELINE( tm990189_state, sys9901_digitsel0_w) )
	921	MCFG_TMS9901_P1_HANDLER( WRITELINE( tm990189_state, sys9901_digitsel1_w) )
	922	MCFG_TMS9901_P2_HANDLER( WRITELINE( tm990189_state, sys9901_digitsel2_w) )
	923	MCFG_TMS9901_P3_HANDLER( WRITELINE( tm990189_state, sys9901_digitsel3_w) )
	924	MCFG_TMS9901_P4_HANDLER( WRITELINE( tm990189_state, sys9901_segment0_w) )
	925	MCFG_TMS9901_P5_HANDLER( WRITELINE( tm990189_state, sys9901_segment1_w) )
	926	MCFG_TMS9901_P6_HANDLER( WRITELINE( tm990189_state, sys9901_segment2_w) )
	927	MCFG_TMS9901_P7_HANDLER( WRITELINE( tm990189_state, sys9901_segment3_w) )
	928	MCFG_TMS9901_P8_HANDLER( WRITELINE( tm990189_state, sys9901_segment4_w) )
	929	MCFG_TMS9901_P9_HANDLER( WRITELINE( tm990189_state, sys9901_segment5_w) )
	930	MCFG_TMS9901_P10_HANDLER( WRITELINE( tm990189_state, sys9901_segment6_w) )
	931	MCFG_TMS9901_P11_HANDLER( WRITELINE( tm990189_state, sys9901_segment7_w) )
	932	MCFG_TMS9901_P12_HANDLER( WRITELINE( tm990189_state, sys9901_dsplytrgr_w) )
	933	MCFG_TMS9901_P13_HANDLER( WRITELINE( tm990189_state, sys9901_shiftlight_w) )
	934	MCFG_TMS9901_P14_HANDLER( WRITELINE( tm990189_state, sys9901_spkrdrive_w) )
	935	MCFG_TMS9901_P15_HANDLER( WRITELINE( tm990189_state, sys9901_tapewdata_w) )
	936	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( tm990189_state, sys9901_interrupt_callback) )
	937
874	938	MCFG_TMS9902_ADD("tms9902", tms9902_params, 2000000)
875	939	MCFG_TM990_189_RS232_ADD("rs232")
876	940	MCFG_TIMER_DRIVER_ADD_PERIODIC("display_timer", tm990189_state, display_callback, attotime::from_hz(30))

trunk/src/mess/drivers/ti99_8.c

r28744	r28745
297	297	int     m_nready_prev;
298	298	void    console_ready_join(int id, int state);
299	299
	300	// Latch for 9901 INT2, INT1 lines
	301	int     m_9901_int;
	302	void    set_9901_int(int line, line_state state);
	303
300	304	// Connected devices
301	305	required_device<tms9995_device>     m_cpu;
302	306	required_device<tms9901_device>     m_tms9901;
r28744	r28745
563	567	case TMS9901_CB_INT7:
564	568	// Read pins INT3*-INT7* of TI99's 9901.
565	569	//
566		// (bit 1: INT1 status)
567		// (bit 2: INT2 status)
	570	// bit 1: INT1 status
	571	// bit 2: INT2 status
568	572	// bits 3-4: unused?
569	573	// bit 5: ???
570	574	// bit 6-7: keyboard status bits 0 through 1
r28744	r28745
580	584	{
581	585	answer = ioport(column[m_keyboard_column])->read();
582	586	}
583		answer = (answer << 6) & 0xc0;
	587	answer = (answer << 6) | m_9901_int;
584	588
585	589	break;
586	590
r28744	r28745
714	718	m_cpu->set_input_line(INT_9995_INT1, data);
715	719	}
716	720
	721	/*
717	722	const tms9901_interface tms9901_wiring_ti99_8 =
718	723	{
719		TMS9901_INT1 | TMS9901_INT2 | TMS9901_INTC,
	724	TMS9901_INT1 | TMS9901_INT2 | TMS9901_INTC,
720	725
721		// read handler
722		DEVCB_DRIVER_MEMBER(ti99_8_state, read_by_9901),
	726	// read handler
	727	DEVCB_DRIVER_MEMBER(ti99_8_state, read_by_9901),
723	728
724		// write handlers
725		{
726		DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, keyC0),
727		DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, keyC1),
728		DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, keyC2),
729		DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, keyC3),
730		DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, CRUS),
731		DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, PTGEN),
732		DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, cassette_motor),
733		DEVCB_NULL,
734		DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, audio_gate),
735		DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, cassette_output),
736		DEVCB_NULL,
737		DEVCB_NULL,
738		DEVCB_NULL,
739		DEVCB_NULL,
740		DEVCB_NULL,
741		DEVCB_NULL
742		},
	729	// write handlers
	730	{
	731	DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, keyC0),
	732	DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, keyC1),
	733	DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, keyC2),
	734	DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, keyC3),
	735	DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, CRUS),
	736	DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, PTGEN),
	737	DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, cassette_motor),
	738	DEVCB_NULL,
	739	DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, audio_gate),
	740	DEVCB_DRIVER_LINE_MEMBER(ti99_8_state, cassette_output),
	741	DEVCB_NULL,
	742	DEVCB_NULL,
	743	DEVCB_NULL,
	744	DEVCB_NULL,
	745	DEVCB_NULL,
	746	DEVCB_NULL
	747	},
743	748
744		DEVCB_DRIVER_MEMBER(ti99_8_state, tms9901_interrupt)
	749	DEVCB_DRIVER_MEMBER(ti99_8_state, tms9901_interrupt)
745	750	};
	751	*/
746	752
747	753	/*****************************************************************************/
748	754
	755	void ti99_8_state::set_9901_int( int line, line_state state)
	756	{
	757	m_tms9901->set_single_int(line, state);
	758	// We latch the value for the read operation. Mind the negative logic.
	759	if (state==CLEAR_LINE) m_9901_int |= (1<<line);
	760	else m_9901_int &= ~(1<<line);
	761	}
	762
749	763	/*
750	764	set the state of TMS9901's INT2 (called by the tms9928 core)
751	765	*/
752	766	WRITE_LINE_MEMBER( ti99_8_state::set_tms9901_INT2 )
753	767	{
754	768	if (TRACE_INTERRUPTS) LOG("ti99_8: VDP int 2 on tms9901, level=%02x\n", state);
755		m_tms9901->set_single_int(2, state);
	769	set_9901_int(2, (line_state)state);
756	770	}
757	771
758	772	/***********************************************************
r28744	r28745
829	843	WRITE_LINE_MEMBER( ti99_8_state::extint )
830	844	{
831	845	if (TRACE_READY) LOG("ti99_8: EXTINT level = %02x\n", state);
832		if (m_tms9901 != NULL)
833		m_tms9901->set_single_int(1, state);
	846	set_9901_int(1, (line_state)state);
834	847	}
835	848
836	849	WRITE_LINE_MEMBER( ti99_8_state::notconnected )
r28744	r28745
1004	1017	// But we assert the line here so that the system starts running
1005	1018	m_nready_combined = 0;
1006	1019	m_gromport->set_grom_base(0x9800, 0xfff1);
	1020
	1021	// Clear INT1 and INT2 latch (negative logic)
	1022	m_9901_int = 0x03;
1007	1023	}
1008	1024
1009	1025	static MACHINE_CONFIG_START( ti99_8_60hz, ti99_8_state )
r28744	r28745
1017	1033	MCFG_TI998_ADD_NTSC(VIDEO_SYSTEM_TAG, TMS9118, ti99_8_tms9118a_interface)
1018	1034
1019	1035	/* Main board */
1020		MCFG_TMS9901_ADD( TMS9901_TAG, tms9901_wiring_ti99_8, XTAL_10_738635MHz/4.0)
	1036	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, XTAL_10_738635MHz/4.0)
	1037	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_8_state, read_by_9901) )
	1038	MCFG_TMS9901_P0_HANDLER( WRITELINE( ti99_8_state, keyC0) )
	1039	MCFG_TMS9901_P1_HANDLER( WRITELINE( ti99_8_state, keyC1) )
	1040	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_8_state, keyC2) )
	1041	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_8_state, keyC3) )
	1042	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_8_state, CRUS) )
	1043	MCFG_TMS9901_P5_HANDLER( WRITELINE( ti99_8_state, PTGEN) )
	1044	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_8_state, cassette_motor) )
	1045	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_8_state, audio_gate) )
	1046	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_8_state, cassette_output) )
	1047	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_8_state, tms9901_interrupt) )
	1048
1021	1049	MCFG_MAINBOARD8_ADD( MAINBOARD8_TAG, mapper_conf )
1022	1050	MCFG_MAINBOARD8_READY_CALLBACK(WRITELINE(ti99_8_state, console_ready_mapper))
1023	1051	MCFG_TI99_GROMPORT_ADD( GROMPORT_TAG )
r28744	r28745
1073	1101	MCFG_TI998_ADD_PAL(VIDEO_SYSTEM_TAG, TMS9129, ti99_8_tms9118a_interface)
1074	1102
1075	1103	/* Main board */
1076		MCFG_TMS9901_ADD( TMS9901_TAG, tms9901_wiring_ti99_8, XTAL_10_738635MHz/4.0 )
	1104	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, XTAL_10_738635MHz/4.0)
	1105	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_8_state, read_by_9901) )
	1106	MCFG_TMS9901_P0_HANDLER( WRITELINE( ti99_8_state, keyC0) )
	1107	MCFG_TMS9901_P1_HANDLER( WRITELINE( ti99_8_state, keyC1) )
	1108	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_8_state, keyC2) )
	1109	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_8_state, keyC3) )
	1110	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_8_state, CRUS) )
	1111	MCFG_TMS9901_P5_HANDLER( WRITELINE( ti99_8_state, PTGEN) )
	1112	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_8_state, cassette_motor) )
	1113	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_8_state, audio_gate) )
	1114	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_8_state, cassette_output) )
	1115	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_8_state, tms9901_interrupt) )
	1116
1077	1117	MCFG_MAINBOARD8_ADD( MAINBOARD8_TAG, mapper_conf )
1078	1118	MCFG_TI99_GROMPORT_ADD( GROMPORT_TAG )
1079	1119	MCFG_GROMPORT_READY_HANDLER( WRITELINE(ti99_8_state, console_ready_cart) )

trunk/src/mess/drivers/geneve.c

r28744	r28745
275	275	line_state  m_video_wait; // reflects the line to the mapper for CRU query
276	276
277	277	int m_ready_line, m_ready_line1;
278
279		private:
280		//int     m_joystick_select;
281		// Some values to keep. Rest is on the geneve_mapper.
282	278	};
283	279
284	280	/*
r28744	r28745
551	547	m_cpu->set_input_line(INT_9995_INT1, data);
552	548	}
553	549
554		/* tms9901 setup */
	550	/*
	551	// tms9901 setup
555	552	const tms9901_interface tms9901_wiring_geneve =
556	553	{
557		TMS9901_INT1 | TMS9901_INT2 | TMS9901_INT8 | TMS9901_INTB | TMS9901_INTC,   /* only input pins whose state is always known */
	554	TMS9901_INT1 | TMS9901_INT2 | TMS9901_INT8 | TMS9901_INTB | TMS9901_INTC,
558	555
559		// read handler
560		DEVCB_DRIVER_MEMBER(geneve_state, read_by_9901),
	556	// read handler
	557	DEVCB_DRIVER_MEMBER(geneve_state, read_by_9901),
561	558
562		{   /* write handlers */
563		DEVCB_DRIVER_LINE_MEMBER(geneve_state, peripheral_bus_reset),
564		DEVCB_DRIVER_LINE_MEMBER(geneve_state, VDP_reset),
565		DEVCB_DRIVER_LINE_MEMBER(geneve_state, joystick_select),
566		DEVCB_NULL,
567		DEVCB_NULL,
568		DEVCB_NULL,
569		DEVCB_DEVICE_LINE_MEMBER(GKEYBOARD_TAG, geneve_keyboard_device, reset_line),
570		DEVCB_DRIVER_LINE_MEMBER(geneve_state, extbus_wait_states),
571		DEVCB_NULL,
572		DEVCB_DRIVER_LINE_MEMBER(geneve_state, video_wait_states),
573		DEVCB_NULL,
574		DEVCB_NULL,
575		DEVCB_NULL,
576		DEVCB_NULL,
577		DEVCB_NULL,
578		DEVCB_NULL
579		},
	559	{   // write handlers
	560	DEVCB_DRIVER_LINE_MEMBER(geneve_state, peripheral_bus_reset),
	561	DEVCB_DRIVER_LINE_MEMBER(geneve_state, VDP_reset),
	562	DEVCB_DRIVER_LINE_MEMBER(geneve_state, joystick_select),
	563	DEVCB_NULL,
	564	DEVCB_NULL,
	565	DEVCB_NULL,
	566	DEVCB_DEVICE_LINE_MEMBER(GKEYBOARD_TAG, geneve_keyboard_device, reset_line),
	567	DEVCB_DRIVER_LINE_MEMBER(geneve_state, extbus_wait_states),
	568	DEVCB_NULL,
	569	DEVCB_DRIVER_LINE_MEMBER(geneve_state, video_wait_states),
	570	DEVCB_NULL,
	571	DEVCB_NULL,
	572	DEVCB_NULL,
	573	DEVCB_NULL,
	574	DEVCB_NULL,
	575	DEVCB_NULL
	576	},
580	577
581		/* interrupt handler */
582		DEVCB_DRIVER_MEMBER(geneve_state, tms9901_interrupt)
	578	// interrupt handler
	579	DEVCB_DRIVER_MEMBER(geneve_state, tms9901_interrupt)
583	580	};
	581	*/
584	582
585	583	/*******************************************************************
586	584	Signal lines
587	585	*******************************************************************/
	586
588	587	/*
589	588	inta is connected to both tms9901 IRQ1 line and to tms9995 INT4/EC line.
590	589	*/
r28744	r28745
748	747	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", geneve_state, geneve_hblank_interrupt, SCREEN_TAG, 0, 1) /* 262.5 in 60Hz, 312.5 in 50Hz */
749	748
750	749	// Main board components
751		MCFG_TMS9901_ADD(TMS9901_TAG, tms9901_wiring_geneve, 3000000)
	750	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, 3000000)
	751	MCFG_TMS9901_READBLOCK_HANDLER( READ8(geneve_state, read_by_9901) )
	752	MCFG_TMS9901_P0_HANDLER( WRITELINE( geneve_state, peripheral_bus_reset) )
	753	MCFG_TMS9901_P1_HANDLER( WRITELINE( geneve_state, VDP_reset) )
	754	MCFG_TMS9901_P2_HANDLER( WRITELINE( geneve_state, joystick_select) )
	755	MCFG_TMS9901_P6_HANDLER( DEVWRITELINE( GKEYBOARD_TAG, geneve_keyboard_device, reset_line) )
	756	MCFG_TMS9901_P7_HANDLER( WRITELINE( geneve_state, extbus_wait_states) )
	757	MCFG_TMS9901_P9_HANDLER( WRITELINE( geneve_state, video_wait_states) )
	758	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( geneve_state, tms9901_interrupt) )
752	759
753	760	// Mapper
754	761	MCFG_DEVICE_ADD(GMAPPER_TAG, GENEVE_MAPPER, 0)

trunk/src/mess/drivers/ti99_4p.c

r28744	r28745
167	167	// Mapper registers
168	168	UINT8 m_mapper[16];
169	169
	170	// Latch for 9901 INT2, INT1 lines
	171	int     m_9901_int;
	172	void    set_9901_int(int line, line_state state);
	173
170	174	int     m_ready_prev;       // for debugging purposes only
171	175
172	176	};
r28744	r28745
566	570	{
567	571	case TMS9901_CB_INT7:
568	572	// Read pins INT3*-INT7* of TI99's 9901.
569		// bit 1: INT1 status (interrupt; not set at this place)
570		// bit 2: INT2 status (interrupt; not set at this place)
	573	// bit 1: INT1 status
	574	// bit 2: INT2 status
571	575	// bit 3-7: keyboard status bits 0 to 4
572	576	//
573	577	// |K|K|K|K|K|I2|I1|C|
r28744	r28745
584	588	{
585	589	answer &= ~(ioport("ALPHA")->read());
586	590	}
587		answer = (answer << 3) & 0xf8;
	591	answer = (answer << 3) | m_9901_int;
588	592	break;
589	593
590	594	case TMS9901_INT8_INT15:
r28744	r28745
679	683	m_cassette->output((state!=0)? +1 : -1);
680	684	}
681	685
682		/* TMS9901 setup. The callback functions pass a reference to the TMS9901 as device. */
	686	/*
	687	// TMS9901 setup. The callback functions pass a reference to the TMS9901 as device.
683	688	const tms9901_interface tms9901_wiring_sgcpu =
684	689	{
685		TMS9901_INT1 | TMS9901_INT2 | TMS9901_INTC, /* only input pins whose state is always known */
	690	TMS9901_INT1 | TMS9901_INT2 | TMS9901_INTC, // only input pins whose state is always known
686	691
687		// read handler
688		DEVCB_DRIVER_MEMBER(ti99_4p_state, read_by_9901),
	692	// read handler
	693	DEVCB_DRIVER_MEMBER(ti99_4p_state, read_by_9901),
689	694
690		{   // write handlers
691		DEVCB_NULL,
692		DEVCB_NULL,
693		DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, keyC0),
694		DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, keyC1),
695		DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, keyC2),
696		DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, alphaW),
697		DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, cs_motor),
698		DEVCB_NULL,
699		DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, audio_gate),
700		DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, cassette_output),
701		DEVCB_NULL,
702		DEVCB_NULL,
703		DEVCB_NULL,
704		DEVCB_NULL,
705		DEVCB_NULL,
706		DEVCB_NULL
707		},
	695	{   // write handlers
	696	DEVCB_NULL,
	697	DEVCB_NULL,
	698	DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, keyC0),
	699	DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, keyC1),
	700	DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, keyC2),
	701	DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, alphaW),
	702	DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, cs_motor),
	703	DEVCB_NULL,
	704	DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, audio_gate),
	705	DEVCB_DRIVER_LINE_MEMBER(ti99_4p_state, cassette_output),
	706	DEVCB_NULL,
	707	DEVCB_NULL,
	708	DEVCB_NULL,
	709	DEVCB_NULL,
	710	DEVCB_NULL,
	711	DEVCB_NULL
	712	},
708	713
709		/* interrupt handler */
710		DEVCB_DRIVER_MEMBER(ti99_4p_state, tms9901_interrupt)
	714	// interrupt handler
	715	DEVCB_DRIVER_MEMBER(ti99_4p_state, tms9901_interrupt)
711	716	};
712	717
	718	*/
	719
713	720	/***************************************************************************
714	721	Control lines
715	722	****************************************************************************/
r28744	r28745
751	758	m_cpu->set_ready(combined);
752	759	}
753	760
	761	void ti99_4p_state::set_9901_int( int line, line_state state)
	762	{
	763	m_tms9901->set_single_int(line, state);
	764	// We latch the value for the read operation. Mind the negative logic.
	765	if (state==CLEAR_LINE) m_9901_int |= (1<<line);
	766	else m_9901_int &= ~(1<<line);
	767	}
754	768
755	769	WRITE_LINE_MEMBER( ti99_4p_state::extint )
756	770	{
757	771	if (VERBOSE>6) LOG("ti99_4p: EXTINT level = %02x\n", state);
758		if (m_tms9901 != NULL)
759		m_tms9901->set_single_int(1, state);
	772	set_9901_int(1, (line_state)state);
760	773	}
761	774
762	775	WRITE_LINE_MEMBER( ti99_4p_state::notconnected )
r28744	r28745
836	849	*/
837	850	WRITE_LINE_MEMBER(ti99_4p_state::set_tms9901_INT2_from_v9938)
838	851	{
839		m_tms9901->set_single_int(2, state);
	852	set_9901_int(2, (line_state)state);
840	853	}
841	854
842	855	/*
r28744	r28745
844	857	*/
845	858	MACHINE_RESET_MEMBER(ti99_4p_state,ti99_4p)
846	859	{
847		m_tms9901->set_single_int(12, 0);
	860	set_9901_int(12, CLEAR_LINE);
848	861
849	862	m_cpu->set_ready(ASSERT_LINE);
850	863	m_cpu->set_hold(CLEAR_LINE);
	864	m_9901_int = 0x03; // INT2* and INT1* set to 1, i.e. inactive
851	865	}
852	866
853	867	TIMER_DEVICE_CALLBACK_MEMBER(ti99_4p_state::sgcpu_hblank_interrupt)
r28744	r28745
873	887	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", ti99_4p_state, sgcpu_hblank_interrupt, SCREEN_TAG, 0, 1)
874	888
875	889	// tms9901
876		MCFG_TMS9901_ADD(TMS9901_TAG, tms9901_wiring_sgcpu, 3000000)
	890	MCFG_DEVICE_ADD(TMS9901_TAG, TMS9901, 3000000)
	891	MCFG_TMS9901_READBLOCK_HANDLER( READ8(ti99_4p_state, read_by_9901) )
	892	MCFG_TMS9901_P2_HANDLER( WRITELINE( ti99_4p_state, keyC0) )
	893	MCFG_TMS9901_P3_HANDLER( WRITELINE( ti99_4p_state, keyC1) )
	894	MCFG_TMS9901_P4_HANDLER( WRITELINE( ti99_4p_state, keyC2) )
	895	MCFG_TMS9901_P6_HANDLER( WRITELINE( ti99_4p_state, cs_motor) )
	896	MCFG_TMS9901_P8_HANDLER( WRITELINE( ti99_4p_state, audio_gate) )
	897	MCFG_TMS9901_P9_HANDLER( WRITELINE( ti99_4p_state, cassette_output) )
	898	MCFG_TMS9901_INTLEVEL_HANDLER( WRITE8( ti99_4p_state, tms9901_interrupt) )
877	899
878	900	// Peripheral expansion box (SGCPU composition)
879	901	MCFG_DEVICE_ADD( PERIBOX_TAG, PERIBOX_SG, 0)

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