trunk/src/mame/drivers/rollerg.c
| r28732 | r28733 | |
| 239 | 239 | m_maincpu->set_input_line(0, CLEAR_LINE); |
| 240 | 240 | } |
| 241 | 241 | |
| 242 | | static const k053252_interface rollerg_k053252_intf = |
| 243 | | { |
| 244 | | DEVCB_NULL, |
| 245 | | DEVCB_NULL, |
| 246 | | DEVCB_DRIVER_LINE_MEMBER(rollerg_state,rollerg_irq_ack_w), |
| 247 | | DEVCB_NULL, |
| 248 | | 14*8, 2*8 |
| 249 | | }; |
| 250 | | |
| 251 | 242 | void rollerg_state::machine_start() |
| 252 | 243 | { |
| 253 | 244 | UINT8 *ROM = memregion("maincpu")->base(); |
| r28732 | r28733 | |
| 300 | 291 | MCFG_K051316_GFXDECODE("gfxdecode") |
| 301 | 292 | MCFG_K051316_PALETTE("palette") |
| 302 | 293 | |
| 303 | | MCFG_K053252_ADD("k053252", 3000000*2, rollerg_k053252_intf) |
| 294 | MCFG_DEVICE_ADD("k053252", K053252, 3000000*2) |
| 295 | MCFG_K053252_INT1_ACK_CB(WRITELINE(rollerg_state,rollerg_irq_ack_w)) |
| 296 | MCFG_K053252_OFFSETS(14*8, 2*8) |
| 304 | 297 | |
| 305 | 298 | /* sound hardware */ |
| 306 | 299 | MCFG_SPEAKER_STANDARD_MONO("mono") |
trunk/src/mame/drivers/hexion.c
| r28732 | r28733 | |
| 208 | 208 | m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE); |
| 209 | 209 | } |
| 210 | 210 | |
| 211 | | static const k053252_interface hexion_k053252_intf = |
| 212 | | { |
| 213 | | DEVCB_NULL, |
| 214 | | DEVCB_NULL, |
| 215 | | DEVCB_DRIVER_LINE_MEMBER(hexion_state,hexion_irq_ack_w), |
| 216 | | DEVCB_DRIVER_LINE_MEMBER(hexion_state,hexion_nmi_ack_w), |
| 217 | | 0, 0 |
| 218 | | }; |
| 219 | 211 | |
| 220 | 212 | static MACHINE_CONFIG_START( hexion, hexion_state ) |
| 221 | 213 | |
| r28732 | r28733 | |
| 224 | 216 | MCFG_CPU_PROGRAM_MAP(hexion_map) |
| 225 | 217 | MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", hexion_state, hexion_scanline, "screen", 0, 1) |
| 226 | 218 | |
| 227 | | MCFG_K053252_ADD("k053252", 24000000/2, hexion_k053252_intf) |
| 219 | MCFG_DEVICE_ADD("k053252", K053252, 24000000/2) |
| 220 | MCFG_K053252_INT1_ACK_CB(WRITELINE(hexion_state, hexion_irq_ack_w)) |
| 221 | MCFG_K053252_INT2_ACK_CB(WRITELINE(hexion_state, hexion_nmi_ack_w)) |
| 228 | 222 | |
| 229 | 223 | /* video hardware */ |
| 230 | 224 | MCFG_SCREEN_ADD("screen", RASTER) |
trunk/src/mame/drivers/dbz.c
| r28732 | r28733 | |
| 318 | 318 | m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE); |
| 319 | 319 | } |
| 320 | 320 | |
| 321 | | |
| 322 | | static const k053252_interface dbz_k053252_intf = |
| 323 | | { |
| 324 | | DEVCB_NULL, |
| 325 | | DEVCB_NULL, |
| 326 | | DEVCB_DRIVER_LINE_MEMBER(dbz_state,dbz_irq2_ack_w), |
| 327 | | DEVCB_NULL, |
| 328 | | 0, 0 |
| 329 | | }; |
| 330 | | |
| 331 | 321 | void dbz_state::machine_start() |
| 332 | 322 | { |
| 333 | 323 | save_item(NAME(m_control)); |
| r28732 | r28733 | |
| 386 | 376 | MCFG_K053251_ADD("k053251") |
| 387 | 377 | MCFG_K053936_ADD("k053936_1", dbz_k053936_intf) |
| 388 | 378 | MCFG_K053936_ADD("k053936_2", dbz_k053936_intf) |
| 389 | | MCFG_K053252_ADD("k053252", 16000000/2, dbz_k053252_intf) |
| 379 | MCFG_DEVICE_ADD("k053252", K053252, 16000000/2) |
| 380 | MCFG_K053252_INT1_ACK_CB(WRITELINE(dbz_state, dbz_irq2_ack_w)) |
| 390 | 381 | |
| 391 | 382 | /* sound hardware */ |
| 392 | 383 | MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") |
trunk/src/mame/drivers/qdrmfgp.c
| r28732 | r28733 | |
| 565 | 565 | qdrmfgp2_tile_callback, "none" |
| 566 | 566 | }; |
| 567 | 567 | |
| 568 | | static const k053252_interface qdrmfgp_k053252_intf = |
| 569 | | { |
| 570 | | DEVCB_NULL, |
| 571 | | DEVCB_NULL, |
| 572 | | DEVCB_NULL, |
| 573 | | DEVCB_NULL, |
| 574 | | 40, 16 |
| 575 | | }; |
| 576 | | |
| 577 | | static const k053252_interface qdrmfgp2_k053252_intf = |
| 578 | | { |
| 579 | | DEVCB_NULL, |
| 580 | | DEVCB_NULL, |
| 581 | | DEVCB_NULL, |
| 582 | | DEVCB_NULL, |
| 583 | | 40, 16 |
| 584 | | }; |
| 585 | | |
| 586 | 568 | MACHINE_START_MEMBER(qdrmfgp_state,qdrmfgp) |
| 587 | 569 | { |
| 588 | 570 | save_item(NAME(m_control)); |
| r28732 | r28733 | |
| 643 | 625 | MCFG_K056832_ADD("k056832", qdrmfgp_k056832_intf) |
| 644 | 626 | MCFG_K056832_GFXDECODE("gfxdecode") |
| 645 | 627 | MCFG_K056832_PALETTE("palette") |
| 646 | | MCFG_K053252_ADD("k053252", XTAL_32MHz/4, qdrmfgp_k053252_intf) |
| 628 | |
| 629 | MCFG_DEVICE_ADD("k053252", K053252, XTAL_32MHz/4) |
| 630 | MCFG_K053252_OFFSETS(40, 16) |
| 647 | 631 | |
| 648 | 632 | /* sound hardware */ |
| 649 | 633 | MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") |
| r28732 | r28733 | |
| 685 | 669 | MCFG_K056832_ADD("k056832", qdrmfgp2_k056832_intf) |
| 686 | 670 | MCFG_K056832_GFXDECODE("gfxdecode") |
| 687 | 671 | MCFG_K056832_PALETTE("palette") |
| 688 | | MCFG_K053252_ADD("k053252", XTAL_32MHz/4, qdrmfgp2_k053252_intf) |
| 672 | |
| 673 | MCFG_DEVICE_ADD("k053252", K053252, XTAL_32MHz/4) |
| 674 | MCFG_K053252_OFFSETS(40, 16) |
| 689 | 675 | |
| 690 | 676 | /* sound hardware */ |
| 691 | 677 | MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") |
trunk/src/mame/drivers/overdriv.c
| r28732 | r28733 | |
| 312 | 312 | m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); |
| 313 | 313 | } |
| 314 | 314 | |
| 315 | | static const k053252_interface overdriv_k053252_intf = |
| 316 | | { |
| 317 | | DEVCB_NULL, |
| 318 | | DEVCB_NULL, |
| 319 | | DEVCB_NULL, |
| 320 | | DEVCB_NULL, |
| 321 | | 13*8, 2*8 |
| 322 | | }; |
| 323 | 315 | |
| 324 | | |
| 325 | 316 | static MACHINE_CONFIG_START( overdriv, overdriv_state ) |
| 326 | 317 | |
| 327 | 318 | /* basic machine hardware */ |
| r28732 | r28733 | |
| 372 | 363 | MCFG_K053251_ADD("k053251") |
| 373 | 364 | MCFG_K053250_ADD("k053250_1", "palette", "screen", 0, 0) |
| 374 | 365 | MCFG_K053250_ADD("k053250_2", "palette", "screen", 0, 0) |
| 375 | | MCFG_K053252_ADD("k053252", 24000000/4, overdriv_k053252_intf) |
| 366 | |
| 367 | MCFG_DEVICE_ADD("k053252", K053252, 24000000/4) |
| 368 | MCFG_K053252_OFFSETS(13*8, 2*8) |
| 376 | 369 | |
| 377 | 370 | /* sound hardware */ |
| 378 | 371 | MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") |
trunk/src/mame/drivers/mystwarr.c
| r28732 | r28733 | |
| 973 | 973 | for (i=5; i<=7; i++) m_k054539_1->set_gain(i, 2.0); |
| 974 | 974 | } |
| 975 | 975 | |
| 976 | | static const k053252_interface mystwarr_k053252_intf = |
| 977 | | { |
| 978 | | DEVCB_NULL, |
| 979 | | DEVCB_NULL, |
| 980 | | DEVCB_NULL, |
| 981 | | DEVCB_NULL, |
| 982 | | 24, 16 |
| 983 | | }; |
| 984 | 976 | |
| 985 | | static const k053252_interface viostorm_k053252_intf = |
| 986 | | { |
| 987 | | DEVCB_NULL, |
| 988 | | DEVCB_NULL, |
| 989 | | DEVCB_NULL, |
| 990 | | DEVCB_NULL, |
| 991 | | 40, 16 |
| 992 | | }; |
| 993 | | |
| 994 | | static const k053252_interface metamrph_k053252_intf = |
| 995 | | { |
| 996 | | DEVCB_NULL, |
| 997 | | DEVCB_NULL, |
| 998 | | DEVCB_NULL, |
| 999 | | DEVCB_NULL, |
| 1000 | | 24, 24 |
| 1001 | | }; |
| 1002 | | |
| 1003 | | static const k053252_interface martchmp_k053252_intf = |
| 1004 | | { |
| 1005 | | DEVCB_NULL, |
| 1006 | | DEVCB_NULL, |
| 1007 | | DEVCB_NULL, |
| 1008 | | DEVCB_NULL, |
| 1009 | | 32, 24-1 |
| 1010 | | }; |
| 1011 | | |
| 1012 | | static const k053252_interface dadandrm_k053252_intf = |
| 1013 | | { |
| 1014 | | DEVCB_NULL, |
| 1015 | | DEVCB_NULL, |
| 1016 | | DEVCB_NULL, |
| 1017 | | DEVCB_NULL, |
| 1018 | | 24, 16+1 |
| 1019 | | }; |
| 1020 | | |
| 1021 | | static const k053252_interface gaiapols_k053252_intf = |
| 1022 | | { |
| 1023 | | DEVCB_NULL, |
| 1024 | | DEVCB_NULL, |
| 1025 | | DEVCB_NULL, |
| 1026 | | DEVCB_NULL, |
| 1027 | | 40, 16 |
| 1028 | | }; |
| 1029 | | |
| 1030 | 977 | static MACHINE_CONFIG_START( mystwarr, mystwarr_state ) |
| 1031 | 978 | |
| 1032 | 979 | /* basic machine hardware */ |
| r28732 | r28733 | |
| 1040 | 987 | MCFG_QUANTUM_TIME(attotime::from_hz(1920)) |
| 1041 | 988 | |
| 1042 | 989 | MCFG_EEPROM_SERIAL_ER5911_8BIT_ADD("eeprom") |
| 1043 | | MCFG_K053252_ADD("k053252", 6000000, mystwarr_k053252_intf) // 6 MHz? |
| 1044 | | |
| 990 | |
| 991 | MCFG_DEVICE_ADD("k053252", K053252, 6000000) // 6 MHz? |
| 992 | MCFG_K053252_OFFSETS(24, 16) |
| 993 | |
| 1045 | 994 | MCFG_MACHINE_START_OVERRIDE(mystwarr_state,mystwarr) |
| 1046 | 995 | MCFG_MACHINE_RESET_OVERRIDE(mystwarr_state,mystwarr) |
| 1047 | 996 | |
| r28732 | r28733 | |
| 1089 | 1038 | |
| 1090 | 1039 | MCFG_MACHINE_RESET_OVERRIDE(mystwarr_state,viostorm) |
| 1091 | 1040 | |
| 1092 | | MCFG_DEVICE_REMOVE("k053252") |
| 1093 | | MCFG_K053252_ADD("k053252", 16000000/2, viostorm_k053252_intf) |
| 1094 | | |
| 1041 | MCFG_DEVICE_REPLACE("k053252", K053252, 16000000/2) |
| 1042 | MCFG_K053252_OFFSETS(40, 16) |
| 1043 | |
| 1095 | 1044 | /* basic machine hardware */ |
| 1096 | 1045 | MCFG_CPU_MODIFY("maincpu") |
| 1097 | 1046 | MCFG_CPU_PROGRAM_MAP(viostorm_map) |
| r28732 | r28733 | |
| 1119 | 1068 | MCFG_TIMER_MODIFY("scantimer") |
| 1120 | 1069 | MCFG_TIMER_DRIVER_CALLBACK(mystwarr_state, metamrph_interrupt) |
| 1121 | 1070 | |
| 1122 | | MCFG_DEVICE_REMOVE("k053252") |
| 1123 | | MCFG_K053252_ADD("k053252", 6000000, metamrph_k053252_intf) // 6 MHz? |
| 1071 | MCFG_DEVICE_MODIFY("k053252") |
| 1072 | MCFG_K053252_OFFSETS(24, 24) |
| 1073 | |
| 1124 | 1074 | MCFG_K053250_ADD("k053250_1", "palette", "screen", -7, 0) |
| 1125 | 1075 | |
| 1126 | 1076 | /* video hardware */ |
| r28732 | r28733 | |
| 1144 | 1094 | MCFG_CPU_VBLANK_INT_DRIVER("screen", mystwarr_state, ddd_interrupt) |
| 1145 | 1095 | MCFG_DEVICE_REMOVE("scantimer") |
| 1146 | 1096 | |
| 1147 | | MCFG_DEVICE_REMOVE("k053252") |
| 1148 | | MCFG_K053252_ADD("k053252", 6000000, dadandrm_k053252_intf) // 6 MHz? |
| 1097 | MCFG_DEVICE_MODIFY("k053252") |
| 1098 | MCFG_K053252_OFFSETS(24, 16+1) |
| 1149 | 1099 | |
| 1150 | 1100 | MCFG_GFXDECODE_MODIFY("gfxdecode", dadandrn) |
| 1151 | 1101 | |
| r28732 | r28733 | |
| 1170 | 1120 | MCFG_CPU_VBLANK_INT_DRIVER("screen", mystwarr_state, ddd_interrupt) |
| 1171 | 1121 | MCFG_DEVICE_REMOVE("scantimer") |
| 1172 | 1122 | |
| 1173 | | MCFG_DEVICE_REMOVE("k053252") |
| 1174 | | MCFG_K053252_ADD("k053252", 6000000, gaiapols_k053252_intf) // 6 MHz? |
| 1123 | MCFG_DEVICE_MODIFY("k053252") |
| 1124 | MCFG_K053252_OFFSETS(40, 16) |
| 1175 | 1125 | |
| 1176 | 1126 | MCFG_K054000_ADD("k054000") |
| 1177 | 1127 | |
| r28732 | r28733 | |
| 1199 | 1149 | MCFG_TIMER_MODIFY("scantimer") |
| 1200 | 1150 | MCFG_TIMER_DRIVER_CALLBACK(mystwarr_state, mchamp_interrupt) |
| 1201 | 1151 | |
| 1202 | | MCFG_DEVICE_REMOVE("k053252") |
| 1203 | | MCFG_K053252_ADD("k053252", 16000000/2, martchmp_k053252_intf) |
| 1152 | MCFG_DEVICE_REPLACE("k053252", K053252, 16000000/2) |
| 1153 | MCFG_K053252_OFFSETS(32, 24-1) |
| 1204 | 1154 | |
| 1205 | 1155 | MCFG_PALETTE_MODIFY("palette") |
| 1206 | 1156 | MCFG_PALETTE_FORMAT(XRGB) |
trunk/src/emu/machine/k053252.c
| r28732 | r28733 | |
| 65 | 65 | |
| 66 | 66 | k053252_device::k053252_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
| 67 | 67 | : device_t(mconfig, K053252, "Konami 053252", tag, owner, clock, "k053252", __FILE__), |
| 68 | | device_video_interface(mconfig, *this) |
| 68 | device_video_interface(mconfig, *this), |
| 69 | m_int1_en_cb(*this), |
| 70 | m_int2_en_cb(*this), |
| 71 | m_int1_ack_cb(*this), |
| 72 | m_int2_ack_cb(*this), |
| 73 | //m_int_time_cb(*this), |
| 74 | m_offsx(0), |
| 75 | m_offsy(0) |
| 69 | 76 | { |
| 70 | 77 | } |
| 71 | 78 | |
| 72 | | //------------------------------------------------- |
| 73 | | // device_config_complete - perform any |
| 74 | | // operations now that the configuration is |
| 75 | | // complete |
| 76 | | //------------------------------------------------- |
| 77 | 79 | |
| 78 | | void k053252_device::device_config_complete() |
| 79 | | { |
| 80 | | // inherit a copy of the static data |
| 81 | | const k053252_interface *intf = reinterpret_cast<const k053252_interface *>(static_config()); |
| 82 | | if (intf != NULL) |
| 83 | | *static_cast<k053252_interface *>(this) = *intf; |
| 84 | | |
| 85 | | // or initialize to defaults if none provided |
| 86 | | else |
| 87 | | { |
| 88 | | memset(&m_int1_en, 0, sizeof(m_int1_en)); |
| 89 | | memset(&m_int2_en, 0, sizeof(m_int2_en)); |
| 90 | | memset(&m_int1_ack, 0, sizeof(m_int1_ack)); |
| 91 | | memset(&m_int2_ack, 0, sizeof(m_int2_ack)); |
| 92 | | //memset(&m_int_time, 0, sizeof(m_int_time)); |
| 93 | | } |
| 94 | | } |
| 95 | | |
| 96 | 80 | //------------------------------------------------- |
| 97 | 81 | // device_start - device-specific startup |
| 98 | 82 | //------------------------------------------------- |
| r28732 | r28733 | |
| 100 | 84 | void k053252_device::device_start() |
| 101 | 85 | { |
| 102 | 86 | save_item(NAME(m_regs)); |
| 103 | | m_int1_en_func.resolve(m_int1_en, *this); |
| 104 | | m_int2_en_func.resolve(m_int2_en, *this); |
| 105 | | m_int1_ack_func.resolve(m_int1_ack, *this); |
| 106 | | m_int2_ack_func.resolve(m_int2_ack, *this); |
| 107 | | //m_int_time_func.resolve(m_int_time, *this); |
| 87 | m_int1_en_cb.resolve_safe(); |
| 88 | m_int2_en_cb.resolve_safe(); |
| 89 | m_int1_ack_cb.resolve_safe(); |
| 90 | m_int2_ack_cb.resolve_safe(); |
| 91 | //m_int_time_cb.resolve_safe(); |
| 108 | 92 | } |
| 109 | 93 | |
| 110 | 94 | //------------------------------------------------- |
| r28732 | r28733 | |
| 205 | 189 | logerror("%d (%04x) HBP set\n",m_hbp,m_hbp); |
| 206 | 190 | res_change(); |
| 207 | 191 | break; |
| 208 | | case 0x06: m_int1_en_func(data); break; |
| 209 | | case 0x07: m_int2_en_func(data); break; |
| 192 | case 0x06: m_int1_en_cb(data); break; |
| 193 | case 0x07: m_int2_en_cb(data); break; |
| 210 | 194 | case 0x08: |
| 211 | 195 | case 0x09: |
| 212 | 196 | m_vc = (m_regs[9]&0xff); |
| r28732 | r28733 | |
| 231 | 215 | res_change(); |
| 232 | 216 | break; |
| 233 | 217 | //case 0x0d: m_int_time(data); break; |
| 234 | | case 0x0e: m_int1_ack_func(1); break; |
| 235 | | case 0x0f: m_int2_ack_func(1); break; |
| 218 | case 0x0e: m_int1_ack_cb(1); break; |
| 219 | case 0x0f: m_int2_ack_cb(1); break; |
| 236 | 220 | } |
| 237 | 221 | } |
trunk/src/emu/machine/k053252.h
| r28732 | r28733 | |
| 6 | 6 | #define __K053252_H__ |
| 7 | 7 | |
| 8 | 8 | |
| 9 | | struct k053252_interface |
| 10 | | { |
| 11 | | devcb_write_line m_int1_en; |
| 12 | | devcb_write_line m_int2_en; |
| 13 | | devcb_write_line m_int1_ack; |
| 14 | | devcb_write_line m_int2_ack; |
| 15 | | // devcb_write8 m_int_time; |
| 16 | | int m_offsx; |
| 17 | | int m_offsy; |
| 18 | | }; |
| 9 | #define MCFG_K053252_INT1_EN_CB(_devcb) \ |
| 10 | devcb = &k053252_device::set_int1_en_callback(*device, DEVCB2_##_devcb); |
| 19 | 11 | |
| 12 | #define MCFG_K053252_INT2_EN_CB(_devcb) \ |
| 13 | devcb = &k053252_device::set_int2_en_callback(*device, DEVCB2_##_devcb); |
| 14 | |
| 15 | #define MCFG_K053252_INT1_ACK_CB(_devcb) \ |
| 16 | devcb = &k053252_device::set_int1_ack_callback(*device, DEVCB2_##_devcb); |
| 17 | |
| 18 | #define MCFG_K053252_INT2_ACK_CB(_devcb) \ |
| 19 | devcb = &k053252_device::set_int2_ack_callback(*device, DEVCB2_##_devcb); |
| 20 | |
| 21 | /*#define MCFG_K053252_INT_TIME_CB(_devcb) \ |
| 22 | devcb = &k053252_device::set_int_time_callback(*device, DEVCB2_##_devcb); */ |
| 23 | |
| 24 | #define MCFG_K053252_OFFSETS(_offsx, _offsy) \ |
| 25 | k053252_device::set_offsets(*device, _offsx, _offsy); |
| 26 | |
| 27 | |
| 20 | 28 | class k053252_device : public device_t, |
| 21 | | public device_video_interface, |
| 22 | | public k053252_interface |
| 29 | public device_video_interface |
| 23 | 30 | { |
| 24 | 31 | public: |
| 25 | 32 | k053252_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
| 26 | 33 | ~k053252_device() {} |
| 27 | 34 | |
| 35 | template<class _Object> static devcb2_base &set_int1_en_callback(device_t &device, _Object object) { return downcast<k053252_device &>(device).m_int1_en_cb.set_callback(object); } |
| 36 | template<class _Object> static devcb2_base &set_int2_en_callback(device_t &device, _Object object) { return downcast<k053252_device &>(device).m_int2_en_cb.set_callback(object); } |
| 37 | template<class _Object> static devcb2_base &set_int1_ack_callback(device_t &device, _Object object) { return downcast<k053252_device &>(device).m_int1_ack_cb.set_callback(object); } |
| 38 | template<class _Object> static devcb2_base &set_int2_ack_callback(device_t &device, _Object object) { return downcast<k053252_device &>(device).m_int2_ack_cb.set_callback(object); } |
| 39 | //template<class _Object> static devcb2_base &set_int_time_callback(device_t &device, _Object object) { return downcast<k053252_device &>(device).m_int_time_cb.set_callback(object); } |
| 40 | static void set_offsets(device_t &device, int offsx, int offsy) { downcast<k053252_device &>(device).m_offsx = offsx; downcast<k053252_device &>(device).m_offsy = offsy;} |
| 41 | |
| 28 | 42 | DECLARE_READ8_MEMBER( read ); // CCU registers |
| 29 | 43 | DECLARE_WRITE8_MEMBER( write ); |
| 30 | 44 | |
| r28732 | r28733 | |
| 32 | 46 | |
| 33 | 47 | protected: |
| 34 | 48 | // device-level overrides |
| 35 | | virtual void device_config_complete(); |
| 36 | 49 | virtual void device_start(); |
| 37 | 50 | virtual void device_reset(); |
| 38 | 51 | |
| r28732 | r28733 | |
| 43 | 56 | UINT16 m_vc,m_vfp,m_vbp; |
| 44 | 57 | UINT8 m_vsw,m_hsw; |
| 45 | 58 | |
| 46 | | devcb_resolved_write_line m_int1_en_func; |
| 47 | | devcb_resolved_write_line m_int2_en_func; |
| 48 | | devcb_resolved_write_line m_int1_ack_func; |
| 49 | | devcb_resolved_write_line m_int2_ack_func; |
| 50 | | //devcb_resolved_write8 m_int_time_func; |
| 59 | devcb2_write_line m_int1_en_cb; |
| 60 | devcb2_write_line m_int2_en_cb; |
| 61 | devcb2_write_line m_int1_ack_cb; |
| 62 | devcb2_write_line m_int2_ack_cb; |
| 63 | // devcb2_write8 m_int_time_cb; |
| 64 | int m_offsx; |
| 65 | int m_offsy; |
| 51 | 66 | }; |
| 52 | 67 | |
| 53 | 68 | extern const device_type K053252; |
| 54 | 69 | |
| 55 | | #define MCFG_K053252_ADD(_tag, _clock, _interface) \ |
| 56 | | MCFG_DEVICE_ADD(_tag, K053252, _clock) \ |
| 57 | | MCFG_DEVICE_CONFIG(_interface) |
| 58 | 70 | |
| 59 | | |
| 60 | 71 | #endif /* __K033906_H__ */ |