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r28723 Wednesday 19th March, 2014 at 14:25:25 UTC by Curt Coder
(MESS) cirrus: Moved to emu/bus/pci. (nw)
[src/emu/bus]bus.mak
[src/emu/bus/pci]cirrus.c* cirrus.h*
[src/mess]mess.mak
[src/mess/video]cirrus.c cirrus.h

trunk/src/emu/bus/pci/cirrus.c
r0r28723
1/***************************************************************************
2
3    video/cirrus.c
4
5    Cirrus SVGA card emulation (preliminary)
6
7    Cirrus has the following additional registers that are not present in
8    conventional VGA:
9
10    SEQ 06h:        Unlock Cirrus registers; write 12h to unlock registers,
11                    and read 12h back to confirm Cirrus presence.
12    SEQ 07h
13        bit 3-1:    Pixel depth
14                        0x00    8 bpp
15                        0x02    16 bpp (double vert clock)
16                        0x04    24 bpp
17                        0x06    16 bpp
18                        0x08    32 bpp
19        bit 0:      VGA/SVGA (0=VGA, 1=SVGA)
20    SEQ 0Fh
21        bit 7:      Bankswitch enable
22        bits 4-3:   Memory size
23                        0x00    256K
24                        0x08    512K
25                        0x10    1M
26                        0x18    2M
27    SEQ 12h:        Hardware Cursor
28
29
30
31
32    GC 09h:         Set 64k bank (bits 3-0 only)
33    GC 20h:         Blit Width (bits 7-0)
34    GC 21h:         Blit Width (bits 12-8)
35    GC 22h:         Blit Height (bits 7-0)
36    GC 23h:         Blit Height (bits 12-8)
37    GC 24h:         Blit Destination Pitch (bits 7-0)
38    GC 25h:         Blit Destination Pitch (bits 12-8)
39    GC 26h:         Blit Source Pitch (bits 7-0)
40    GC 27h:         Blit Source Pitch (bits 12-8)
41    GC 28h:         Blit Destination Address (bits 7-0)
42    GC 29h:         Blit Destination Address (bits 15-8)
43    GC 2Ah:         Blit Destination Address (bits 21-16)
44    GC 2Ch:         Blit Source Address (bits 7-0)
45    GC 2Dh:         Blit Source Address (bits 15-8)
46    GC 2Eh:         Blit Source Address (bits 21-16)
47    GC 2Fh:         Blit Write Mask
48    GC 30h:         Blit Mode
49    GC 31h:         Blit Status
50                        bit 7 - Autostart
51                        bit 4 - FIFO Used
52                        bit 2 - Blit Reset
53                        bit 1 - Blit Started
54                        bit 0 - Blit Busy
55    GC 32h:         Raster Operation
56    GC 33h:         Blit Mode Extension
57    GC 34h:         Blit Transparent Color (bits 7-0)
58    GC 35h:         Blit Transparent Color (bits 15-8)
59    GC 38h:         Blit Transparent Color Mask (bits 7-0)
60    GC 39h:         Blit Transparent Color Mask (bits 15-8)
61
62***************************************************************************/
63
64#include "emu.h"
65#include "cirrus.h"
66#include "video/pc_vga.h"
67
68#define LOG_PCIACCESS   0
69
70//**************************************************************************
71//  DEVICE DEFINITIONS
72//**************************************************************************
73
74const device_type CIRRUS = &device_creator<cirrus_device>;
75
76//**************************************************************************
77//  LIVE DEVICE
78//**************************************************************************
79
80//-------------------------------------------------
81//  cirrus_device - constructor
82//-------------------------------------------------
83
84cirrus_device::cirrus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
85      : device_t(mconfig, CIRRUS, "CIRRUS", tag, owner, clock, "cirrus", __FILE__),
86      pci_device_interface( mconfig, *this )
87{
88}
89
90//-------------------------------------------------
91//  device_start - device-specific startup
92//-------------------------------------------------
93
94void cirrus_device::device_start()
95{
96}
97
98//-------------------------------------------------
99//  device_reset - device-specific reset
100//-------------------------------------------------
101
102void cirrus_device::device_reset()
103{
104}
105
106//-------------------------------------------------
107//  pci_read - implementation of PCI read
108//-------------------------------------------------
109
110UINT32 cirrus_device::pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask)
111{
112   UINT32 result = 0;
113
114   if (function == 0)
115   {
116      switch(offset)
117      {
118         case 0x00:  /* vendor/device ID */
119            result = 0x00A01013;
120            break;
121
122         case 0x08:
123            result = 0x03000000;
124            break;
125
126         case 0x10:
127            result = 0xD0000000;
128            break;
129
130         default:
131            result = 0;
132            break;
133      }
134   }
135
136   if (LOG_PCIACCESS)
137      logerror("cirrus5430_pci_read(): function=%d offset=0x%02X result=0x%04X\n", function, offset, result);
138   return result;
139}
140
141
142//-------------------------------------------------
143//  pci_write - implementation of PCI write
144//-------------------------------------------------
145
146void cirrus_device::pci_write(pci_bus_device *pcibus, int function, int offset, UINT32 data, UINT32 mem_mask)
147{
148   if (LOG_PCIACCESS)
149      logerror("cirrus5430_pci_write(): function=%d offset=0x%02X data=0x%04X\n", function, offset, data);
150}
151
152/*************************************
153 *
154 *  Ports
155 *
156 *************************************/
157
158WRITE8_MEMBER( cirrus_device::cirrus_42E8_w )
159{
160   if (data & 0x80)
161      machine().device("vga")->reset();
162}
Property changes on: trunk/src/emu/bus/pci/cirrus.c
Added: svn:eol-style
   + native
Added: svn:mime-type
   + text/plain
trunk/src/emu/bus/pci/cirrus.h
r0r28723
1/***************************************************************************
2
3    video/cirrus.h
4
5    Cirrus SVGA card emulation (preliminary)
6
7***************************************************************************/
8
9#ifndef CIRRUS_H
10#define CIRRUS_H
11
12#include "bus/pci/pci.h"
13
14// ======================> cirrus_device
15
16class cirrus_device : public device_t,
17                  public pci_device_interface
18{
19public:
20      // construction/destruction
21   cirrus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
22
23   virtual UINT32 pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask);
24   virtual void pci_write(pci_bus_device *pcibus, int function, int offset, UINT32 data, UINT32 mem_mask);
25
26   DECLARE_WRITE8_MEMBER( cirrus_42E8_w );
27
28protected:
29   // device-level overrides
30   virtual void device_start();
31   virtual void device_reset();
32private:
33};
34
35
36// device type definition
37extern const device_type CIRRUS;
38
39#endif /* CIRRUS_H */
Property changes on: trunk/src/emu/bus/pci/cirrus.h
Added: svn:mime-type
   + text/plain
Added: svn:eol-style
   + native
trunk/src/emu/bus/bus.mak
r28722r28723
729729ifneq ($(filter PCI,$(BUSES)),)
730730OBJDIRS += $(BUSOBJ)/pci
731731BUSOBJS += $(BUSOBJ)/pci/pci.o
732BUSOBJS += $(BUSOBJ)/pci/cirrus.o
732733BUSOBJS += $(BUSOBJ)/pci/i82371ab.o
733734BUSOBJS += $(BUSOBJ)/pci/i82371sb.o
734735BUSOBJS += $(BUSOBJ)/pci/i82439tx.o
trunk/src/mess/mess.mak
r28722r28723
10111011$(MESSOBJ)/be.a:                \
10121012   $(MESS_DRIVERS)/bebox.o     \
10131013   $(MESS_MACHINE)/bebox.o     \
1014   $(MESS_VIDEO)/cirrus.o      \
10151014
10161015$(MESSOBJ)/bnpo.a:              \
10171016   $(MESS_DRIVERS)/b2m.o       \
trunk/src/mess/video/cirrus.c
r28722r28723
1/***************************************************************************
2
3    video/cirrus.c
4
5    Cirrus SVGA card emulation (preliminary)
6
7    Cirrus has the following additional registers that are not present in
8    conventional VGA:
9
10    SEQ 06h:        Unlock Cirrus registers; write 12h to unlock registers,
11                    and read 12h back to confirm Cirrus presence.
12    SEQ 07h
13        bit 3-1:    Pixel depth
14                        0x00    8 bpp
15                        0x02    16 bpp (double vert clock)
16                        0x04    24 bpp
17                        0x06    16 bpp
18                        0x08    32 bpp
19        bit 0:      VGA/SVGA (0=VGA, 1=SVGA)
20    SEQ 0Fh
21        bit 7:      Bankswitch enable
22        bits 4-3:   Memory size
23                        0x00    256K
24                        0x08    512K
25                        0x10    1M
26                        0x18    2M
27    SEQ 12h:        Hardware Cursor
28
29
30
31
32    GC 09h:         Set 64k bank (bits 3-0 only)
33    GC 20h:         Blit Width (bits 7-0)
34    GC 21h:         Blit Width (bits 12-8)
35    GC 22h:         Blit Height (bits 7-0)
36    GC 23h:         Blit Height (bits 12-8)
37    GC 24h:         Blit Destination Pitch (bits 7-0)
38    GC 25h:         Blit Destination Pitch (bits 12-8)
39    GC 26h:         Blit Source Pitch (bits 7-0)
40    GC 27h:         Blit Source Pitch (bits 12-8)
41    GC 28h:         Blit Destination Address (bits 7-0)
42    GC 29h:         Blit Destination Address (bits 15-8)
43    GC 2Ah:         Blit Destination Address (bits 21-16)
44    GC 2Ch:         Blit Source Address (bits 7-0)
45    GC 2Dh:         Blit Source Address (bits 15-8)
46    GC 2Eh:         Blit Source Address (bits 21-16)
47    GC 2Fh:         Blit Write Mask
48    GC 30h:         Blit Mode
49    GC 31h:         Blit Status
50                        bit 7 - Autostart
51                        bit 4 - FIFO Used
52                        bit 2 - Blit Reset
53                        bit 1 - Blit Started
54                        bit 0 - Blit Busy
55    GC 32h:         Raster Operation
56    GC 33h:         Blit Mode Extension
57    GC 34h:         Blit Transparent Color (bits 7-0)
58    GC 35h:         Blit Transparent Color (bits 15-8)
59    GC 38h:         Blit Transparent Color Mask (bits 7-0)
60    GC 39h:         Blit Transparent Color Mask (bits 15-8)
61
62***************************************************************************/
63
64#include "emu.h"
65#include "cirrus.h"
66#include "video/pc_vga.h"
67
68#define LOG_PCIACCESS   0
69
70//**************************************************************************
71//  DEVICE DEFINITIONS
72//**************************************************************************
73
74const device_type CIRRUS = &device_creator<cirrus_device>;
75
76//**************************************************************************
77//  LIVE DEVICE
78//**************************************************************************
79
80//-------------------------------------------------
81//  cirrus_device - constructor
82//-------------------------------------------------
83
84cirrus_device::cirrus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
85      : device_t(mconfig, CIRRUS, "CIRRUS", tag, owner, clock, "cirrus", __FILE__),
86      pci_device_interface( mconfig, *this )
87{
88}
89
90//-------------------------------------------------
91//  device_start - device-specific startup
92//-------------------------------------------------
93
94void cirrus_device::device_start()
95{
96}
97
98//-------------------------------------------------
99//  device_reset - device-specific reset
100//-------------------------------------------------
101
102void cirrus_device::device_reset()
103{
104}
105
106//-------------------------------------------------
107//  pci_read - implementation of PCI read
108//-------------------------------------------------
109
110UINT32 cirrus_device::pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask)
111{
112   UINT32 result = 0;
113
114   if (function == 0)
115   {
116      switch(offset)
117      {
118         case 0x00:  /* vendor/device ID */
119            result = 0x00A01013;
120            break;
121
122         case 0x08:
123            result = 0x03000000;
124            break;
125
126         case 0x10:
127            result = 0xD0000000;
128            break;
129
130         default:
131            result = 0;
132            break;
133      }
134   }
135
136   if (LOG_PCIACCESS)
137      logerror("cirrus5430_pci_read(): function=%d offset=0x%02X result=0x%04X\n", function, offset, result);
138   return result;
139}
140
141
142//-------------------------------------------------
143//  pci_write - implementation of PCI write
144//-------------------------------------------------
145
146void cirrus_device::pci_write(pci_bus_device *pcibus, int function, int offset, UINT32 data, UINT32 mem_mask)
147{
148   if (LOG_PCIACCESS)
149      logerror("cirrus5430_pci_write(): function=%d offset=0x%02X data=0x%04X\n", function, offset, data);
150}
151
152/*************************************
153 *
154 *  Ports
155 *
156 *************************************/
157
158WRITE8_MEMBER( cirrus_device::cirrus_42E8_w )
159{
160   if (data & 0x80)
161      machine().device("vga")->reset();
162}
trunk/src/mess/video/cirrus.h
r28722r28723
1/***************************************************************************
2
3    video/cirrus.h
4
5    Cirrus SVGA card emulation (preliminary)
6
7***************************************************************************/
8
9#ifndef CIRRUS_H
10#define CIRRUS_H
11
12#include "bus/pci/pci.h"
13
14// ======================> cirrus_device
15
16class cirrus_device : public device_t,
17                  public pci_device_interface
18{
19public:
20      // construction/destruction
21   cirrus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
22
23   virtual UINT32 pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask);
24   virtual void pci_write(pci_bus_device *pcibus, int function, int offset, UINT32 data, UINT32 mem_mask);
25
26   DECLARE_WRITE8_MEMBER( cirrus_42E8_w );
27
28protected:
29   // device-level overrides
30   virtual void device_start();
31   virtual void device_reset();
32private:
33};
34
35
36// device type definition
37extern const device_type CIRRUS;
38
39#endif /* CIRRUS_H */

Previous 199869 Revisions Next

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