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r28717 Wednesday 19th March, 2014 at 13:17:46 UTC by Curt Coder
(MESS) smc92x4: devcb2. (nw)
[src/mess/machine]smc92x4.c smc92x4.h
[src/mess/machine/ti99]hfdc.c

trunk/src/mess/machine/smc92x4.c
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188188#define LOG logerror
189189
190190smc92x4_device::smc92x4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
191: device_t(mconfig, SMC92X4, "SMC 9224/9234 Hard/Floppy Disk Controller", tag, owner, clock, "smc92x4", __FILE__)
191: device_t(mconfig, SMC92X4, "SMC 9224/9234 Hard/Floppy Disk Controller", tag, owner, clock, "smc92x4", __FILE__),
192  m_out_intrq(*this),
193  m_out_dip(*this),
194  m_out_auxbus(*this),
195  m_in_auxbus(*this),
196  m_in_dma(*this),
197  m_out_dma(*this)
192198{
193199}
194200
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272278*/
273279void smc92x4_device::set_dma_address(int pos2316, int pos1508, int pos0700)
274280{
275   m_out_auxbus(OUTPUT_DMA_ADDR, m_register_r[pos2316]);
276   m_out_auxbus(OUTPUT_DMA_ADDR, m_register_r[pos1508]);
277   m_out_auxbus(OUTPUT_DMA_ADDR, m_register_r[pos0700]);
281   m_out_auxbus((offs_t)OUTPUT_DMA_ADDR, m_register_r[pos2316]);
282   m_out_auxbus((offs_t)OUTPUT_DMA_ADDR, m_register_r[pos1508]);
283   m_out_auxbus((offs_t)OUTPUT_DMA_ADDR, m_register_r[pos0700]);
278284}
279285
280286void smc92x4_device::dma_add_offset(int offset)
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314320void smc92x4_device::sync_latches_out()
315321{
316322   m_output1 = (m_output1 & 0xf0) | (m_register_w[RETRY_COUNT]&0x0f);
317   m_out_auxbus(OUTPUT_OUTPUT1, m_output1);
318   m_out_auxbus(OUTPUT_OUTPUT2, m_output2);
323   m_out_auxbus((offs_t)OUTPUT_OUTPUT1, m_output1);
324   m_out_auxbus((offs_t)OUTPUT_OUTPUT2, m_output2);
319325}
320326
321327/*************************************************************
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792798      m_out_dip(ASSERT_LINE);
793799      for (i=0; i < sector_len; i++)
794800      {
795         m_out_dma(0, buf[i]);
801         m_out_dma((offs_t)0, buf[i]);
796802      }
797803      m_out_dip(CLEAR_LINE);
798804   }
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16471653   m_out_dip(ASSERT_LINE);
16481654   for (i=0; i < data_count; i++)
16491655   {
1650      m_out_dma(0, buffer[i]);
1656      m_out_dma((offs_t)0, buffer[i]);
16511657   }
16521658   m_out_dip(CLEAR_LINE);
16531659
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16881694   m_out_dip(ASSERT_LINE);
16891695   for (i=0; i < data_count; i++)
16901696   {
1691      m_out_dma(0, buffer[i]);
1697      m_out_dma((offs_t)0, buffer[i]);
16921698   }
16931699   m_out_dip(CLEAR_LINE);
16941700
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19661972{
19671973   const smc92x4_interface *intf = reinterpret_cast<const smc92x4_interface *>(static_config());
19681974
1969   m_out_intrq.resolve(intf->out_intrq, *this);
1970   m_out_dip.resolve(intf->out_dip, *this);
1971   m_out_auxbus.resolve(intf->out_auxbus, *this);
1972   m_in_auxbus.resolve(intf->in_auxbus, *this);
1973   m_out_dma.resolve(intf->dma_write, *this);
1974   m_in_dma.resolve(intf->dma_read, *this);
1975   m_out_intrq.resolve_safe();
1976   m_out_dip.resolve_safe();
1977   m_out_auxbus.resolve_safe();
1978   m_in_auxbus.resolve_safe(0);
1979   m_out_dma.resolve_safe();
1980   m_in_dma.resolve_safe(0);
19751981
19761982   m_full_track_layout = intf->full_track_layout;
19771983
trunk/src/mess/machine/smc92x4.h
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3636#define DS_READY    0x02        /* drive ready bit */
3737#define DS_WRFAULT  0x01        /* write fault */
3838
39// Interrupt line. To be connected with the controller PCB.
40#define MCFG_SMC92X4_INTRQ_CALLBACK(_write) \
41   devcb = &smc92x4_device::set_intrq_wr_callback(*device, DEVCB2_##_write);
42
43// DMA in progress line. To be connected with the controller PCB.
44#define MCFG_SMC92X4_DIP_CALLBACK(_write) \
45   devcb = &smc92x4_device::set_dip_wr_callback(*device, DEVCB2_##_write);
46
47// Auxiliary Bus. These 8 lines need to be connected to external latches
48// and to a counter circuitry which works together with the external RAM.
49// We use the S0/S1 lines as address lines.
50#define MCFG_SMC92X4_AUXBUS_OUT_CALLBACK(_write) \
51   devcb = &smc92x4_device::set_auxbus_wr_callback(*device, DEVCB2_##_write);
52
53// Auxiliary Bus. This is only used for S0=S1=0.
54#define MCFG_SMC92X4_AUXBUS_IN_CALLBACK(_read) \
55   devcb = &smc92x4_device::set_auxbus_rd_callback(*device, DEVCB2_##_read);
56
57// Callback to read the contents of the external RAM via the data bus.
58// Note that the address must be set and automatically increased
59// by external circuitry.
60#define MCFG_SMC92X4_DMA_IN_CALLBACK(_read) \
61   devcb = &smc92x4_device::set_dma_rd_callback(*device, DEVCB2_##_read);
62
63// Callback to write the contents of the external RAM via the data bus.
64// Note that the address must be set and automatically increased
65// by external circuitry. */
66#define MCFG_SMC92X4_DMA_OUT_CALLBACK(_write) \
67   devcb = &smc92x4_device::set_dma_wr_callback(*device, DEVCB2_##_write);
68
3969struct smc92x4_interface
4070{
4171   // Disk format support. This flag allows to choose between the full
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4575   // simple without too much case checking. Should be removed as soon as
4676   // the respective disk formats support the full format.
4777   int full_track_layout;
48
49   // Interrupt line. To be connected with the controller PCB.
50   devcb_write_line out_intrq;
51
52   // DMA in progress line. To be connected with the controller PCB.
53   devcb_write_line out_dip;
54
55   // Auxiliary Bus. These 8 lines need to be connected to external latches
56   // and to a counter circuitry which works together with the external RAM.
57   // We use the S0/S1 lines as address lines.
58   devcb_write8    out_auxbus;
59
60   // Auxiliary Bus. This is only used for S0=S1=0.
61   devcb_read8     in_auxbus;
62
63   // Callback to read the contents of the external RAM via the data bus.
64   // Note that the address must be set and automatically increased
65   // by external circuitry.
66   devcb_read8     dma_read;
67
68   // Callback to write the contents of the external RAM via the data bus.
69   // Note that the address must be set and automatically increased
70   // by external circuitry. */
71   devcb_write8    dma_write;
72
7378};
7479
7580
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7883public:
7984   smc92x4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
8085
86   template<class _Object> static devcb2_base &set_intrq_wr_callback(device_t &device, _Object object) { return downcast<smc92x4_device &>(device).m_out_intrq.set_callback(object); }
87   template<class _Object> static devcb2_base &set_dip_wr_callback(device_t &device, _Object object) { return downcast<smc92x4_device &>(device).m_out_dip.set_callback(object); }
88   template<class _Object> static devcb2_base &set_auxbus_wr_callback(device_t &device, _Object object) { return downcast<smc92x4_device &>(device).m_out_auxbus.set_callback(object); }
89   template<class _Object> static devcb2_base &set_auxbus_rd_callback(device_t &device, _Object object) { return downcast<smc92x4_device &>(device).m_in_auxbus.set_callback(object); }
90   template<class _Object> static devcb2_base &set_dma_rd_callback(device_t &device, _Object object) { return downcast<smc92x4_device &>(device).m_in_dma.set_callback(object); }
91   template<class _Object> static devcb2_base &set_dma_wr_callback(device_t &device, _Object object) { return downcast<smc92x4_device &>(device).m_out_dma.set_callback(object); }
92
8193   DECLARE_READ8_MEMBER( read );
8294   DECLARE_WRITE8_MEMBER( write );
8395
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95107   virtual void device_reset(void);
96108
97109private:
98   devcb_resolved_write_line   m_out_intrq;    // INT line
99   devcb_resolved_write_line   m_out_dip;      // DMA in progress line
100   devcb_resolved_write8       m_out_auxbus;   // AB0-7 lines (using S0,S1 as address)
101   devcb_resolved_read8        m_in_auxbus;    // AB0-7 lines (S0=S1=0)
102   devcb_resolved_read8        m_in_dma;       // DMA read access to the cache buffer
103   devcb_resolved_write8       m_out_dma;      // DMA write access to the cache buffer
110   devcb2_write_line   m_out_intrq;    // INT line
111   devcb2_write_line   m_out_dip;      // DMA in progress line
112   devcb2_write8       m_out_auxbus;   // AB0-7 lines (using S0,S1 as address)
113   devcb2_read8        m_in_auxbus;    // AB0-7 lines (S0=S1=0)
114   devcb2_read8        m_in_dma;       // DMA read access to the cache buffer
115   devcb2_write8       m_out_dma;      // DMA write access to the cache buffer
104116
105117   UINT8 m_output1;        // internal register "output1"
106118   UINT8 m_output2;        // internal register "output2"
trunk/src/mess/machine/ti99/hfdc.c
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436436const smc92x4_interface ti99_smc92x4_interface =
437437{
438438   FALSE,      /* do not use the full track layout */
439   DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, myarc_hfdc_device, intrq_w),
440   DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, myarc_hfdc_device, dip_w),
441   DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, myarc_hfdc_device, auxbus_out),
442   DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, myarc_hfdc_device, auxbus_in),
443   DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, myarc_hfdc_device, read_buffer),
444   DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, myarc_hfdc_device, write_buffer)
445439};
446440
447441static const mm58274c_interface floppy_mm58274c_interface =
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452446
453447MACHINE_CONFIG_FRAGMENT( ti99_hfdc )
454448   MCFG_SMC92X4_ADD(FDC_TAG, ti99_smc92x4_interface )
449   MCFG_SMC92X4_INTRQ_CALLBACK(WRITELINE(myarc_hfdc_device, intrq_w))
450   MCFG_SMC92X4_DIP_CALLBACK(WRITELINE(myarc_hfdc_device, dip_w))
451   MCFG_SMC92X4_AUXBUS_OUT_CALLBACK(WRITE8(myarc_hfdc_device, auxbus_out))
452   MCFG_SMC92X4_AUXBUS_IN_CALLBACK(READ8(myarc_hfdc_device, auxbus_in))
453   MCFG_SMC92X4_DMA_IN_CALLBACK(READ8(myarc_hfdc_device, read_buffer))
454   MCFG_SMC92X4_DMA_OUT_CALLBACK(WRITE8(myarc_hfdc_device, write_buffer))
455455   MCFG_MM58274C_ADD(CLOCK_TAG, floppy_mm58274c_interface)
456456MACHINE_CONFIG_END
457457

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