trunk/src/mess/drivers/wicat.c
| r26911 | r26912 | |
|---|
| 434 | 434 | { |
| 435 | 435 | switch(offset) |
| 436 | 436 | { |
| 437 | case 0x00: // Write precomp / Error register |
| 438 | logerror("HDC: Write precomp %02x\n",data); |
| 439 | break; |
| 437 | 440 | case 0x01: // Data register |
| 438 | 441 | logerror("HDC: Data %02x\n",data); |
| 439 | 442 | break; |
| 443 | case 0x02: // Sector Number |
| 444 | logerror("HDC: Sector Number %02x\n",data); |
| 445 | break; |
| 446 | case 0x03: // Sector Count |
| 447 | logerror("HDC: Sector Count %02x\n",data); |
| 448 | break; |
| 449 | case 0x04: // Cylinder High |
| 450 | logerror("HDC: Cylinder High %02x\n",data); |
| 451 | break; |
| 452 | case 0x05: // Cylinder Low |
| 453 | logerror("HDC: Cylinder Low %02x\n",data); |
| 454 | break; |
| 440 | 455 | case 0x06: // Command register |
| 441 | 456 | logerror("HDC: Command %1x\n",(data & 0xf0) >> 4); |
| 442 | 457 | m_maincpu->set_input_line(M68K_IRQ_5,HOLD_LINE); |
| 443 | 458 | break; |
| 459 | case 0x07: // Size / Drive / Head |
| 460 | logerror("HDC: Size / Drive / Head %02x\n",data); |
| 461 | break; |
| 462 | case 0x0c: // DMA mid |
| 463 | logerror("HDC: DMA address mid %02x\n",data); |
| 464 | break; |
| 465 | case 0x0d: // DMA low |
| 466 | logerror("HDC: DMA address low %02x\n",data); |
| 467 | break; |
| 468 | case 0x0e: // DMA R/W |
| 469 | logerror("HDC: DMA R/W %02x\n",data); |
| 470 | break; |
| 471 | case 0x0f: // DMA high |
| 472 | logerror("HDC: DMA address high %02x\n",data); |
| 473 | break; |
| 474 | default: |
| 475 | logerror("HDC: Write to unknown register %02x\n",data); |
| 444 | 476 | } |
| 445 | 477 | } |
| 446 | 478 | |
| r26911 | r26912 | |
|---|
| 881 | 913 | |
| 882 | 914 | MCFG_MM58274C_ADD("rtc",wicat_rtc_intf) // actually an MM58174AN, but should be compatible |
| 883 | 915 | |
| 884 | | MCFG_MC2661_ADD("uart0", XTAL_5_0688MHz, wicat_uart0_intf) // connected to terminal board (TODO) |
| 916 | MCFG_MC2661_ADD("uart0", XTAL_5_0688MHz, wicat_uart0_intf) // connected to terminal board |
| 885 | 917 | MCFG_MC2661_ADD("uart1", XTAL_5_0688MHz, wicat_uart1_intf) |
| 886 | 918 | MCFG_MC2661_ADD("uart2", XTAL_5_0688MHz, wicat_uart2_intf) |
| 887 | 919 | MCFG_MC2661_ADD("uart3", XTAL_5_0688MHz, wicat_uart3_intf) |
| r26911 | r26912 | |
|---|
| 943 | 975 | MCFG_DEFAULT_LAYOUT(layout_wicat) |
| 944 | 976 | |
| 945 | 977 | /* Winchester Disk Controller (WD1000 + FD1795) */ |
| 946 | | MCFG_CPU_ADD("floppycpu",N8X300,XTAL_8MHz) |
| 978 | MCFG_CPU_ADD("wd1kcpu",N8X300,XTAL_8MHz) |
| 947 | 979 | MCFG_CPU_PROGRAM_MAP(wicat_wd1000_mem) |
| 948 | 980 | MCFG_CPU_IO_MAP(wicat_wd1000_io) |
| 949 | 981 | MCFG_FD1795x_ADD("fdc",XTAL_8MHz) |