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r26889 Thursday 2nd January, 2014 at 09:54:29 UTC by Miodrag Milanović

-AVR8 cpu changes [Felipe Sanches] - timers wip - Add TIMSK* reads - Refactor timer_tick calls - Remove all redundant register init statements.   We simply set all 0x200 registers to zero. - debugging timers - better syntax for disassembly of RJMP destination address - use register names in disasm of CBI, SBI, SBIC, SBIS instructions - use register bit names in disasm of instructions SBI,    SBIS, SBIC, CBI - wip on avr8 EEPROM read/write support

[src/emu/cpu/avr8]	avr8.c avr8.h avr8dasm.c
[src/mess/drivers]	replicator.c

trunk/src/mess/drivers/replicator.c

r26888	r26889
22	22
23	23	// TODO:
24	24	// * figure out what's wrong with the keypad inputs (interface seems to be blocked in the first screen)
25		// * fix avr8 timer/counter #4 so that we get the buzzer to work
	25	// * fix avr8 timer/counter #0 (toggle OC0B) and #5 (overflow interrupt "Microsecond timer") so that we get the buzzer to work
26	26	// * figure-out correct size of internal EEPROM
27	27	// * emulate an SD Card
28	28	// * implement avr8 WDR (watchdog reset) opcode
29	29
	30	#include "emu.h"
	31	#include "cpu/avr8/avr8.h"
	32	#include "video/hd44780.h"
	33	#include "rendlay.h"
	34	#include "debugger.h"
	35	#include "sound/dac.h"
	36
	37	#define MASTER_CLOCK    16000000
	38
30	39	#define LOG_PORTS 0
31	40
32	41	//Port A bits:
r26888	r26889
139	148	#define Z_MIN (1 << 6)
140	149	#define Z_MAX (1 << 7)
141	150
142
143		#include "emu.h"
144		#include "cpu/avr8/avr8.h"
145		#include "video/hd44780.h"
146		#include "rendlay.h"
147		#include "debugger.h"
148
149		#define MASTER_CLOCK    16000000
150
151	151	/****************************************************\
152	152	* I/O devices                                        *
153	153	\****************************************************/
r26888	r26889
158	158	replicator_state(const machine_config &mconfig, device_type type, const char *tag)
159	159	: driver_device(mconfig, type, tag),
160	160	m_maincpu(*this, "maincpu"),
161		m_lcdc(*this, "hd44780")
	161	m_lcdc(*this, "hd44780"),
	162	m_dac(*this, "dac")
162	163	{
163	164	}
164	165
r26888	r26889
180	181
181	182	required_device<avr8_device> m_maincpu;
182	183	required_device<hd44780_device> m_lcdc;
	184	required_device<dac_device> m_dac;
183	185
184	186	DECLARE_READ8_MEMBER(port_r);
185	187	DECLARE_WRITE8_MEMBER(port_w);
r26888	r26889
445	447	{
446	448	if (data == m_port_g) break;
447	449
448		#if LOG_PORTS
449	450	UINT8 old_port_g = m_port_g;
450	451	UINT8 changed = data ^ old_port_g;
451	452
	453	#if LOG_PORTS
452	454	printf("[%08X] ", m_maincpu->m_shifted_pc);
453	455	if(changed & EX4_1280) printf("[G] EX4_1280: %s\n", data & EX4_1280 ? "HIGH" : "LOW");
454	456	if(changed & EX3_1280) printf("[G] EX3_1280: %s\n", data & EX3_1280 ? "HIGH" : "LOW");
r26888	r26889
457	459	if(changed & BUZZ) printf("[G] BUZZ: %s\n", data & BUZZ ? "HIGH" : "LOW");
458	460	#endif
459	461
	462	if(changed & BUZZ){
	463	/* FIX-ME: What is the largest sample value allowed?
	464	I'm using 0x3F based on what I see in src/mess/drivers/craft.c
	465	But as the method is called "write_unsigned8", I guess we could have samples with values up to 0xFF, right?
	466	Anyway... With the 0x3F value we'll get a sound that is not so loud, which may be less annoying... :-)
	467	*/
	468	UINT8 audio_sample = (data & BUZZ) ? 0x3F : 0;
	469	m_dac->write_unsigned8(audio_sample << 1);
	470	}
	471
460	472	m_port_g = data;
461	473	break;
462	474	}
r26888	r26889
662	674	MCFG_HD44780_ADD("hd44780")
663	675	MCFG_HD44780_LCD_SIZE(4, 20)
664	676
665		/*TODO:
666		Add sound config:
667		- A buzzer connected to the PG5 pin that is driven by Timer/Counter #4
668		*/
	677	/* sound hardware */
	678	/* A piezo is connected to the PORT G bit 5 (OC0B pin driven by Timer/Counter #4) */
	679	MCFG_SPEAKER_STANDARD_MONO("buzzer")
	680	MCFG_SOUND_ADD("dac", DAC, 0)
	681	MCFG_SOUND_ROUTE(0, "buzzer", 1.00)
669	682
670	683	MACHINE_CONFIG_END
671	684
r26888	r26889
679	692	ROM_END
680	693
681	694	/*   YEAR  NAME      PARENT    COMPAT    MACHINE   INPUT     INIT      COMPANY          FULLNAME */
682		CONS(2012, replica1,    0,        0,        replicator,    replicator, replicator_state,    replicator,    "Makerbot", "Replicator 1 desktop 3d printer", GAME_NOT_WORKING|GAME_NO_SOUND)
	695	CONS(2012, replica1,    0,        0,        replicator,    replicator, replicator_state,    replicator,    "Makerbot", "Replicator 1 desktop 3d printer", GAME_NOT_WORKING)

trunk/src/emu/cpu/avr8/avr8.h

r26888	r26889
162	162	UINT8 m_r[0x200];
163	163
164	164	// internal timers
165		UINT8 m_timer0_top;
166		INT32 m_timer0_increment;
167		UINT16 m_timer0_prescale;
168		UINT16 m_timer0_prescale_count;
	165	UINT16 m_timer_top[6];
	166	INT32 m_timer_increment[6];
	167	UINT16 m_timer_prescale[6];
	168	UINT16 m_timer_prescale_count[6];
169	169
170		UINT16 m_timer1_top;
171		INT32 m_timer1_increment;
172		UINT16 m_timer1_prescale;
173		UINT16 m_timer1_prescale_count;
174
175		UINT8 m_timer2_top;
176		INT32 m_timer2_increment;
177		UINT16 m_timer2_prescale;
178		UINT16 m_timer2_prescale_count;
179
180		UINT16 m_timer4_top;
181		INT32 m_timer4_increment;
182		UINT16 m_timer4_prescale;
183		UINT16 m_timer4_prescale_count;
184
185	170	// SPI
186	171	bool m_spi_active;
187	172	UINT8 m_spi_prescale;
r26888	r26889
226	211
227	212	// timers
228	213	void timer_tick(int cycles);
	214	void update_timer_clock_source(UINT8 timer, UINT8 selection);
	215	void update_timer_waveform_gen_mode(UINT8 timer, UINT8 mode);
229	216
230	217	// timer 0
231	218	void timer0_tick();
232	219	void changed_tccr0a(UINT8 data);
233	220	void changed_tccr0b(UINT8 data);
234		void update_timer0_waveform_gen_mode();
235		void update_timer0_clock_source();
236	221	void update_ocr0(UINT8 newval, UINT8 reg);
237	222	void timer0_force_output_compare(int reg);
238	223
r26888	r26889
240	225	void timer1_tick();
241	226	void changed_tccr1a(UINT8 data);
242	227	void changed_tccr1b(UINT8 data);
243		void update_timer1_waveform_gen_mode();
244		void update_timer1_clock_source();
245	228	void update_timer1_input_noise_canceler();
246	229	void update_timer1_input_edge_select();
247	230	void update_ocr1(UINT16 newval, UINT8 reg);
r26888	r26889
250	233	void timer2_tick();
251	234	void changed_tccr2a(UINT8 data);
252	235	void changed_tccr2b(UINT8 data);
253		void update_timer2_waveform_gen_mode();
254		void update_timer2_clock_source();
255	236	void update_ocr2(UINT8 newval, UINT8 reg);
256	237	void timer2_force_output_compare(int reg);
257	238
258	239	// timer 3
259		/*
260	240	void timer3_tick();
261	241	void changed_tccr3a(UINT8 data);
262	242	void changed_tccr3b(UINT8 data);
263		void update_timer3_waveform_gen_mode();
264		void update_timer3_clock_source();
265		void update_ocr3(UINT8 newval, UINT8 reg);
266		void timer3_force_output_compare(int reg);
267		*/
	243	void changed_tccr3c(UINT8 data);
	244	//   void update_ocr3(UINT8 newval, UINT8 reg);
	245	//   void timer3_force_output_compare(int reg);
268	246
269	247	// timer 4
270	248	void timer4_tick();
271	249	void changed_tccr4a(UINT8 data);
272	250	void changed_tccr4b(UINT8 data);
273		void update_timer4_waveform_gen_mode();
274		void update_timer4_clock_source();
	251	void changed_tccr4c(UINT8 data);
275	252	//void update_ocr4(UINT8 newval, UINT8 reg);
276	253	//void timer4_force_output_compare(int reg);
277	254
	255	// timer 5
	256	void timer5_tick();
	257	void changed_tccr5a(UINT8 data);
	258	void changed_tccr5b(UINT8 data);
	259	//   void update_ocr5(UINT8 newval, UINT8 reg);
	260	//   void timer5_force_output_compare(int reg);
	261
278	262	// address spaces
279	263	address_space *m_program;
280	264	address_space *m_data;
r26888	r26889
707	691	AVR8_REGIDX_PORTK,
708	692	AVR8_REGIDX_PINL,
709	693	AVR8_REGIDX_DDRL,
710		AVR8_REGIDX_PORTL
	694	AVR8_REGIDX_PORTL,
	695	//0x10C: Reserved
	696	//0x10D: Reserved
	697	//0x10E: Reserved
	698	//0x10F: Reserved
	699	//0x110: Reserved
	700	//0x111: Reserved
	701	//0x112: Reserved
	702	//0x113: Reserved
	703	//0x114: Reserved
	704	//0x115: Reserved
	705	//0x116: Reserved
	706	//0x117: Reserved
	707	//0x118: Reserved
	708	//0x119: Reserved
	709	//0x11A: Reserved
	710	//0x11B: Reserved
	711	//0x11C: Reserved
	712	//0x11D: Reserved
	713	//0x11E: Reserved
	714	//0x11F: Reserved
	715	AVR8_REGIDX_TCCR5A,
	716	AVR8_REGIDX_TCCR5B,
	717	AVR8_REGIDX_TCCR5C,
	718	//0x123: Reserved
	719	AVR8_REGIDX_TCNT5L,
	720	AVR8_REGIDX_TCNT5H,
	721	AVR8_REGIDX_ICR5L,
	722	AVR8_REGIDX_ICR5H,
	723	AVR8_REGIDX_OCR5AL,
	724	AVR8_REGIDX_OCR5AH,
	725	AVR8_REGIDX_OCR5BL,
	726	AVR8_REGIDX_OCR5BH,
	727	AVR8_REGIDX_OCR5CL,
	728	AVR8_REGIDX_OCR5CH,
	729	//0x12E: Reserved
	730	//0x12F: Reserved
	731	AVR8_REGIDX_UCSR3A,
	732	AVR8_REGIDX_UCSR3B,
	733	AVR8_REGIDX_UCSR3C,
	734	//0x133: Reserved
	735	AVR8_REGIDX_UBRR3L,
	736	AVR8_REGIDX_UBRR3H,
	737	AVR8_REGIDX_UDR3,
	738	//0x137: Reserved
	739	//  .
	740	//  . up to
	741	//  .
	742	//0x1FF: Reserved
711	743	};
712	744
713	745	enum {
r26888	r26889
820	852	CKDIV8 = (1 << 7),
821	853	};
822	854
823		#define AVR8_EECR_EERE          0x01
824
825	855	#define AVR8_EEARH_MASK         0x01
826	856
827	857	#define AVR8_SPSR_SPIF_MASK     0x80

trunk/src/emu/cpu/avr8/avr8dasm.c

r26888	r26889
32	32	UINT32 addr = 0;
33	33	const char* register_names[0x40] = {"PINA", "DDRA", "PORTA", "PINB", "DDRB", "PORTB", "PINC", "DDRC", "PORTC", "PIND", "DDRD", "PORTD", "PINE", "DDRE", "PORTE", "PINF", "DDRF", "PORTF", "PING", "DDRG", "PORTG", "TIFR0", "TIFR1", "TIFR2","TIFR3", "TIFR4", "TIFR5", "PCIFR", "EIFR", "EIMSK", "GPIOR0", "EECR", "EEDR", "EEARL", "EEARH", "GTCCR", "TCCR0A", "TCCR0B", "TCNT0", "OCR0A", "OCR0B", "0x29", "GPIOR1", "GPIOR2", "SPCR", "SPSR", "SPDR", "0x2F", "ACSR", "OCDR", "0x32", "SMCR", "MCUSR", "MCUCR", "0x36", "SPMCSR", "0x38", "0x39", "0x3A", "RAMPZ", "EIND", "SPL", "SPH", "SREG"};
34	34
	35	const char* register_bit_names[0x40][8] = {
	36	/* PINA   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	37	/* DDRA   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	38	/* PORTA  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	39	/* PINB   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	40	/* DDRB   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	41	/* PORTB  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	42	/* PINC   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	43	/* DDRC   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	44	/* PORTC  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	45	/* PIND   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	46	/* DDRD   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	47	/* PORTD  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	48	/* PINE   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	49	/* DDRE   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	50	/* PORTE  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	51	/* PINF   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	52	/* DDRF   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	53	/* PORTF  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	54	/* PING   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	55	/* DDRG   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	56	/* PORTG  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	57	/* TIFR0  */ { "TOV0", "OCF0A", "OCF0B",     "3",     "4",     "5",     "6",     "7"},
	58	/* TIFR1  */ { "TOV1", "OCF1A", "OCF1B", "OCF1C",     "4",  "ICF1",     "6",     "7"},
	59	/* TIFR2  */ { "TOV2", "OCF2A", "OCF2B",     "3",     "4",     "5",     "6",     "7"},
	60	/* TIFR3  */ { "TOV3", "OCF3A", "OCF3B", "OCF3C",     "4",  "ICF3",     "6",     "7"},
	61	/* TIFR4  */ { "TOV4", "OCF4A", "OCF4B", "OCF4C",     "4",  "ICF4",     "6",     "7"},
	62	/* TIFR5  */ { "TOV5", "OCF5A", "OCF5B", "OCF5C",     "4",  "ICF5",     "6",     "7"},
	63	/* PCIFR  */ {"PCIF0", "PCIF1", "PCIF2",     "3",     "4",     "5",     "6",     "7"},
	64	/* EIFR   */ {"INTF0", "INTF1", "INTF2", "INTF3", "INTF4", "INTF5", "INTF6", "INTF7"},
	65	/* EIMSK  */ { "INT0",  "INT1",  "INT2",  "INT3",  "INT4",  "INT5",  "INT6",  "INT7"},
	66	/* GPIOR0 */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	67	/* EECR   */ { "EERE",  "EEPE", "EEMPE", "EERIE", "EEPM0", "EEPM1",     "6",     "7"},
	68	/* EEDR   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	69	/* EEARL  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	70	/* EEARH  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	71	/* GTCCR  */ {"PSRSYNC", "PSRASY",  "2",     "3",     "4",     "5",     "6",   "TSM"},
	72	/* TCCR0A */ {"WGM00", "WGM01",     "2",     "3","COM0B0","COM0B1","COM0A0","COM0A1"},
	73	/* TCCR0B */ {  "CS0",   "CS1",   "CS2", "WGM02",     "4",     "5", "FOC0B", "FOC0A"},
	74	/* TCNT0  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	75	/* OCR0A  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	76	/* OCR0B  */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	77	/* 0x29   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	78	/* GPIOR1 */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	79	/* GPIOR2 */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	80	/* SPCR   */ { "SPR0",  "SPR1",  "CPHA",  "CPOL",  "MSTR",  "DORD",   "SPE",  "SPIE"},
	81	/* SPSR   */ {"SPI2X",     "1",     "2",     "3",     "4",     "5",  "WCOL",  "SPIF"},
	82	/* SPDR   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	83	/* 0x2F   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	84	/* ACSR   */ {"ACIS0", "ACIS1",  "ACIC",  "ACIE",   "ACI",   "ACO",  "ACBG",   "ACD"},
	85	/* OCDR   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	86	/* 0x32   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	87	/* SMCR   */ {   "SE",   "SM0",   "SM1",   "SM2",     "4",     "5",     "6",     "7"},
	88	/* MCUSR  */ { "PORF", "EXTRF",  "BORF",  "WDRF",  "JTRF",     "5",     "6",     "7"},
	89	/* MCUCR  */ { "IVCE", "IVSEL",     "2",     "3",   "PUD",     "5",     "6",   "JTD"},
	90	/* 0x36   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	91	/* SPMCSR */ {"SPMEN", "PGERS", "PGWRT","BLBSET","RWWSRE", "SIGRD", "RWWSB", "SPMIE"},
	92	/* 0x38   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	93	/* 0x39   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	94	/* 0x3A   */ {    "0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	95	/* RAMPZ  */ {"RAMPZ0","RAMPZ1",     "2",     "3",     "4",     "5",     "6",     "7"},
	96	/* EIND   */ {"EIND0",     "1",     "2",     "3",     "4",     "5",     "6",     "7"},
	97	/* SPL    */ {  "SP0",   "SP1",   "SP2",   "SP3",   "SP4",   "SP5",   "SP6",   "SP7"},
	98	/* SPH    */ {  "SP8",   "SP9",  "SP10",  "SP11",  "SP12",  "SP13",  "SP14",  "SP15"},
	99	/* SREG   */ {    "C",     "Z",     "N",     "V",     "S",     "H",     "T",     "I"}};
	100
35	101	switch(op & 0xf000)
36	102	{
37	103	case 0x0000:
r26888	r26889
458	524	output += sprintf( output, "SBIW    R%d:R%d, 0x%02x", 24+(RD2(op) << 1)+1, 24+(RD2(op) << 1), KCONST6(op) );
459	525	break;
460	526	case 0x0800:
461		output += sprintf( output, "CBI     0x%02x, %d", ACONST5(op), RR3(op) );
	527	if (ACONST5(op) < 0x20)
	528	output += sprintf( output, "CBI     %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
	529	else
	530	output += sprintf( output, "CBI     0x%02x, %d", ACONST5(op), RR3(op) );
462	531	break;
463	532	case 0x0900:
464		output += sprintf( output, "SBIC    0x%02x, %d", ACONST5(op), RR3(op) );
	533	if (ACONST5(op) < 0x20)
	534	output += sprintf( output, "SBIC    %s, %s", register_names[ACONST5(op)],  register_bit_names[ACONST5(op)][RR3(op)] );
	535	else
	536	output += sprintf( output, "SBIC    0x%02x, %d", ACONST5(op), RR3(op) );
465	537	break;
466	538	case 0x0a00:
467		output += sprintf( output, "SBI     0x%02x, %d", ACONST5(op), RR3(op) );
	539	if (ACONST5(op) < 0x20)
	540	output += sprintf( output, "SBI     %s, %s", register_names[ACONST5(op)],  register_bit_names[ACONST5(op)][RR3(op)] );
	541	else
	542	output += sprintf( output, "SBI     0x%02x, %d", ACONST5(op), RR3(op) );
468	543	break;
469	544	case 0x0b00:
470		output += sprintf( output, "SBIS    0x%02x, %d", ACONST5(op), RR3(op) );
	545	if (ACONST5(op) < 0x20)
	546	output += sprintf( output, "SBIS    %s, %s", register_names[ACONST5(op)],  register_bit_names[ACONST5(op)][RR3(op)] );
	547	else
	548	output += sprintf( output, "SBIS    0x%02x, %d", ACONST5(op), RR3(op) );
471	549	break;
472	550	case 0x0c00:
473	551	case 0x0d00:
r26888	r26889
481	559	if(op & 0x0800)
482	560	{
483	561	if (ACONST6(op) < 0x40 ) {
484		output += sprintf( output, "OUT     %s, R%d", register_names[ACONST6(op)], RD5(op) );
	562	output += sprintf( output, "OUT     %s, R%d", register_names[ACONST6(op)], RD5(op) );
485	563	} else {
486		output += sprintf( output, "OUT     0x%02x, R%d", ACONST6(op), RD5(op) );
	564	output += sprintf( output, "OUT     0x%02x, R%d", ACONST6(op), RD5(op) );
487	565	}
488	566	}
489	567	else
490	568	{
491	569	if (ACONST6(op) < 0x40 ) {
492		output += sprintf( output, "IN      R%d, %s", RD5(op), register_names[ACONST6(op)] );
	570	output += sprintf( output, "IN      R%d, %s", RD5(op), register_names[ACONST6(op)] );
493	571	} else {
494		output += sprintf( output, "IN      R%d, 0x%02x", RD5(op), ACONST6(op) );
	572	output += sprintf( output, "IN      R%d, 0x%02x", RD5(op), ACONST6(op) );
495	573	}
496	574	}
497	575	break;
498	576	case 0xc000:
499		output += sprintf( output, "RJMP    %08x", (((op & 0x0800) ? ((op & 0x0fff) | 0xfffff000) : (op & 0x0fff)) << 1) );
	577	//I'm not sure if this is correct. why pc + ... : pc + 8 + ... ?
	578	output += sprintf( output, "RJMP    %08x", (((op & 0x0800) ? pc + ((op & 0x0fff) | 0xfffff000) : pc + 8 + (op & 0x0fff)) << 0) );
500	579	break;
501	580	case 0xd000:
502	581	output += sprintf( output, "RCALL   %08x", (((op & 0x0800) ? ((op & 0x0fff) | 0xfffff000) : (op & 0x0fff)) << 1) );

trunk/src/emu/cpu/avr8/avr8.c

r26888	r26889
145	145	WGM4_FAST_PWM_OCR
146	146	};
147	147
	148	enum
	149	{
	150	WGM5_NORMAL = 0,
	151	WGM5_PWM_8_PC,
	152	WGM5_PWM_9_PC,
	153	WGM5_PWM_10_PC,
	154	WGM5_CTC_OCR,
	155	WGM5_FAST_PWM_8,
	156	WGM5_FAST_PWM_9,
	157	WGM5_FAST_PWM_10,
	158	WGM5_PWM_PFC_ICR,
	159	WGM5_PWM_PFC_OCR,
	160	WGM5_PWM_PC_ICR,
	161	WGM5_PWM_PC_OCR,
	162	WGM5_CTC_ICR,
	163	WGM5_RESERVED,
	164	WGM5_FAST_PWM_ICR,
	165	WGM5_FAST_PWM_OCR
	166	};
	167
148	168	static const char avr8_reg_name[4] = { 'A', 'B', 'C', 'D' };
149	169
150	170	#define SREG_R(b) ((m_r[AVR8_REGIDX_SREG] & (1 << (b))) >> (b))
r26888	r26889
187	207	#define AVR8_TCNT1H             (m_r[AVR8_REGIDX_TCNT1H])
188	208	#define AVR8_TCNT1L             (m_r[AVR8_REGIDX_TCNT1L])
189	209
	210	#define AVR8_OCR3CH             (m_r[AVR8_REGIDX_OCR3CH])
	211	#define AVR8_OCR3CL             (m_r[AVR8_REGIDX_OCR3CL])
	212	#define AVR8_OCR3BH             (m_r[AVR8_REGIDX_OCR3BH])
	213	#define AVR8_OCR3BL             (m_r[AVR8_REGIDX_OCR3BL])
	214	#define AVR8_OCR3AH             (m_r[AVR8_REGIDX_OCR3AH])
	215	#define AVR8_OCR3AL             (m_r[AVR8_REGIDX_OCR3AL])
	216	#define AVR8_ICR3H              (m_r[AVR8_REGIDX_ICR3H])
	217	#define AVR8_ICR3L              (m_r[AVR8_REGIDX_ICR3L])
	218	#define AVR8_TCNT3H             (m_r[AVR8_REGIDX_TCNT3H])
	219	#define AVR8_TCNT3L             (m_r[AVR8_REGIDX_TCNT3L])
	220
	221	#define AVR8_OCR4CH             (m_r[AVR8_REGIDX_OCR4CH])
	222	#define AVR8_OCR4CL             (m_r[AVR8_REGIDX_OCR4CL])
	223	#define AVR8_OCR4BH             (m_r[AVR8_REGIDX_OCR4BH])
	224	#define AVR8_OCR4BL             (m_r[AVR8_REGIDX_OCR4BL])
	225	#define AVR8_OCR4AH             (m_r[AVR8_REGIDX_OCR4AH])
	226	#define AVR8_OCR4AL             (m_r[AVR8_REGIDX_OCR4AL])
	227	#define AVR8_ICR4H              (m_r[AVR8_REGIDX_ICR4H])
	228	#define AVR8_ICR4L              (m_r[AVR8_REGIDX_ICR4L])
	229	#define AVR8_TCNT4H             (m_r[AVR8_REGIDX_TCNT4H])
	230	#define AVR8_TCNT4L             (m_r[AVR8_REGIDX_TCNT4L])
	231
	232	#define AVR8_OCR5CH             (m_r[AVR8_REGIDX_OCR5CH])
	233	#define AVR8_OCR5CL             (m_r[AVR8_REGIDX_OCR5CL])
	234	#define AVR8_OCR5BH             (m_r[AVR8_REGIDX_OCR5BH])
	235	#define AVR8_OCR5BL             (m_r[AVR8_REGIDX_OCR5BL])
	236	#define AVR8_OCR5AH             (m_r[AVR8_REGIDX_OCR5AH])
	237	#define AVR8_OCR5AL             (m_r[AVR8_REGIDX_OCR5AL])
	238	#define AVR8_ICR5H              (m_r[AVR8_REGIDX_ICR5H])
	239	#define AVR8_ICR5L              (m_r[AVR8_REGIDX_ICR5L])
	240	#define AVR8_TCNT5H             (m_r[AVR8_REGIDX_TCNT5H])
	241	#define AVR8_TCNT5L             (m_r[AVR8_REGIDX_TCNT5L])
	242
190	243	#define AVR8_TCCR0B                 (m_r[AVR8_REGIDX_TCCR0B])
191	244	#define AVR8_TCCR0B_FOC0A_MASK      0x80
192	245	#define AVR8_TCCR0B_FOC0A_SHIFT     7
r26888	r26889
309	362	#define AVR8_TIFR2_TOV2_SHIFT   0
310	363	#define AVR8_TIFR2_MASK         (AVR8_TIFR2_TOV2_MASK | AVR8_TIFR2_OCF2B_MASK | AVR8_TIFR2_OCF2A_MASK)
311	364
	365	#define AVR8_TIMSK3             (m_r[AVR8_REGIDX_TIMSK3])
	366	#define AVR8_TIMSK3_OCIE3C_MASK 0x08
	367	#define AVR8_TIMSK3_OCIE3B_MASK 0x04
	368	#define AVR8_TIMSK3_OCIE3A_MASK 0x02
	369	#define AVR8_TIMSK3_TOIE3_MASK  0x01
	370	#define AVR8_TIMSK3_OCIE3C      ((AVR8_TIMSK3 & AVR8_TIMSK3_OCIE3C_MASK) >> 3)
	371	#define AVR8_TIMSK3_OCIE3B      ((AVR8_TIMSK3 & AVR8_TIMSK3_OCIE3B_MASK) >> 2)
	372	#define AVR8_TIMSK3_OCIE3A      ((AVR8_TIMSK3 & AVR8_TIMSK3_OCIE3A_MASK) >> 1)
	373	#define AVR8_TIMSK3_TOIE3       ((AVR8_TIMSK3 &  AVR8_TIMSK3_TOIE3_MASK) >> 0)
	374
	375	#define AVR8_TCCR4C                 (m_r[AVR8_REGIDX_TCCR4C])
	376
312	377	#define AVR8_TCCR4B                 (m_r[AVR8_REGIDX_TCCR4B])
313	378	#define AVR8_TCCR4B_FOC4A_MASK      0x80
314	379	#define AVR8_TCCR4B_FOC4A_SHIFT     7
r26888	r26889
327	392	#define AVR8_TCCR4A_COM4A_SHIFT     6
328	393	#define AVR8_TCCR4A_COM4B_MASK      0x30
329	394	#define AVR8_TCCR4A_COM4B_SHIFT     4
	395	#define AVR8_TCCR4A_COM4C_MASK      0x0c
	396	#define AVR8_TCCR4A_COM4C_SHIFT     2
330	397	#define AVR8_TCCR4A_WGM4_10_MASK    0x03
331	398	#define AVR8_TCCR4A_WGM4_10_SHIFT   0
332	399	#define AVR8_TCCR4A_COM4A           ((AVR8_TCCR4A & AVR8_TCCR4A_COM4A_MASK) >> AVR8_TCCR4A_COM4A_SHIFT)
333	400	#define AVR8_TCCR4A_COM4B           ((AVR8_TCCR4A & AVR8_TCCR4A_COM4B_MASK) >> AVR8_TCCR4A_COM4B_SHIFT)
	401	#define AVR8_TCCR4A_COM4C           ((AVR8_TCCR4A & AVR8_TCCR4A_COM4C_MASK) >> AVR8_TCCR4A_COM4C_SHIFT)
334	402	#define AVR8_TCCR4A_WGM2_10         (AVR8_TCCR4A & AVR8_TCCR4A_WGM2_10_MASK)
335	403
336	404	#define AVR8_WGM4_32 ((AVR8_TCCR4B & AVR8_TCCR4B_WGM4_32_MASK) >> AVR8_TCCR4B_WGM4_32_SHIFT)
r26888	r26889
354	422	#define AVR8_TIFR4_TOV4_SHIFT   0
355	423	#define AVR8_TIFR4_MASK         (AVR8_TIFR4_TOV4_MASK | AVR8_TIFR4_OCF4B_MASK | AVR8_TIFR4_OCF4A_MASK)
356	424
	425	//---------------------------------------------------------------
	426	#define AVR8_TCCR5C                 (m_r[AVR8_REGIDX_TCCR5C])
	427	#define AVR8_TCCR5C_FOC5A_MASK      0x80
	428	#define AVR8_TCCR5C_FOC5A_SHIFT     7
	429	#define AVR8_TCCR5C_FOC5B_MASK      0x40
	430	#define AVR8_TCCR5C_FOC5B_SHIFT     6
	431	#define AVR8_TCCR5C_FOC5C_MASK      0x20
	432	#define AVR8_TCCR5C_FOC5C_SHIFT     5
	433
	434	#define AVR8_TCCR5B                 (m_r[AVR8_REGIDX_TCCR5B])
	435	#define AVR8_TCCR5B_ICNC5_MASK      0x80
	436	#define AVR8_TCCR5B_ICNC5_SHIFT     7
	437	#define AVR8_TCCR5B_ICES5_MASK      0x40
	438	#define AVR8_TCCR5B_ICES5_SHIFT     6
	439	#define AVR8_TCCR5B_WGM5_32_MASK    0x18
	440	#define AVR8_TCCR5B_WGM5_32_SHIFT   3
	441	#define AVR8_TCCR5B_CS_MASK         0x07
	442	#define AVR8_TCCR5B_CS_SHIFT        0
	443	#define AVR8_TIMER5_CLOCK_SELECT    ((AVR8_TCCR5B & AVR8_TCCR5B_CS_MASK) >> AVR8_TCCR5B_CS_SHIFT)
	444
	445	#define AVR8_TCCR5A                 (m_r[AVR8_REGIDX_TCCR4A])
	446	#define AVR8_TCCR5A_COM5A_MASK      0xc0
	447	#define AVR8_TCCR5A_COM5A_SHIFT     6
	448	#define AVR8_TCCR5A_COM5B_MASK      0x30
	449	#define AVR8_TCCR5A_COM5B_SHIFT     4
	450	#define AVR8_TCCR5A_COM5C_MASK      0x0c
	451	#define AVR8_TCCR5A_COM5C_SHIFT     2
	452	#define AVR8_TCCR5A_WGM5_10_MASK    0x03
	453	#define AVR8_TCCR5A_WGM5_10_SHIFT   0
	454	#define AVR8_TCCR5A_COM5A           ((AVR8_TCCR5A & AVR8_TCCR5A_COM5A_MASK) >> AVR8_TCCR5A_COM5A_SHIFT)
	455	#define AVR8_TCCR5A_COM5B           ((AVR8_TCCR5A & AVR8_TCCR5A_COM5B_MASK) >> AVR8_TCCR5A_COM5B_SHIFT)
	456	#define AVR8_TCCR5A_COM5C           ((AVR8_TCCR5A & AVR8_TCCR5A_COM5C_MASK) >> AVR8_TCCR5A_COM5C_SHIFT)
	457	#define AVR8_TCCR5A_WGM5_10         (AVR8_TCCR5A & AVR8_TCCR5A_WGM5_10_MASK)
	458
	459	#define AVR8_WGM5_32 ((AVR8_TCCR5B & AVR8_TCCR5B_WGM5_32_MASK) >> AVR8_TCCR5B_WGM5_32_SHIFT)
	460	#define AVR8_WGM5_10 ((AVR8_TCCR5A & AVR8_TCCR5A_WGM5_10_MASK) >> AVR8_TCCR5A_WGM5_10_SHIFT)
	461	#define AVR8_WGM5 ((AVR8_WGM5_32 << 2) | AVR8_WGM5_10)
	462
	463	#define AVR8_TIMSK5             (m_r[AVR8_REGIDX_TIMSK5])
	464	#define AVR8_TIMSK5_ICIE5_MASK  0x20
	465	#define AVR8_TIMSK5_OCIE5C_MASK 0x08
	466	#define AVR8_TIMSK5_OCIE5B_MASK 0x04
	467	#define AVR8_TIMSK5_OCIE5A_MASK 0x02
	468	#define AVR8_TIMSK5_TOIE5_MASK  0x01
	469
	470	#define AVR8_TIMSK5_ICIE5C      ((AVR8_TIMSK5 & AVR8_TIMSK5_ICIE5C_MASK) >> 5)
	471	#define AVR8_TIMSK5_OCIE5C      ((AVR8_TIMSK5 & AVR8_TIMSK5_OCIE5C_MASK) >> 3)
	472	#define AVR8_TIMSK5_OCIE5B      ((AVR8_TIMSK5 & AVR8_TIMSK5_OCIE5B_MASK) >> 2)
	473	#define AVR8_TIMSK5_OCIE5A      ((AVR8_TIMSK5 & AVR8_TIMSK5_OCIE5A_MASK) >> 1)
	474	#define AVR8_TIMSK5_TOIE5       (AVR8_TIMSK5 & AVR8_TIMSK5_TOIE5_MASK)
	475
	476	#define AVR8_TIFR5              (m_r[AVR8_REGIDX_TIFR5])
	477	#define AVR8_TIFR5_ICF5_MASK   0x20
	478	#define AVR8_TIFR5_ICF5_SHIFT  5
	479	#define AVR8_TIFR5_OCF5C_MASK   0x08
	480	#define AVR8_TIFR5_OCF5C_SHIFT  3
	481	#define AVR8_TIFR5_OCF5B_MASK   0x04
	482	#define AVR8_TIFR5_OCF5B_SHIFT  2
	483	#define AVR8_TIFR5_OCF5A_MASK   0x02
	484	#define AVR8_TIFR5_OCF5A_SHIFT  1
	485	#define AVR8_TIFR5_TOV5_MASK    0x01
	486	#define AVR8_TIFR5_TOV5_SHIFT   0
	487	#define AVR8_TIFR5_MASK         (AVR8_TIFR5_ICF5_MASK | AVR8_TIFR5_OCF5C_MASK | AVR8_TIFR5_OCF5B_MASK | AVR8_TIFR5_OCF5A_MASK | AVR8_TIFR5_TOV5_MASK)
	488
	489
	490	#define AVR8_TIFR5_ICF5 ((AVR8_TIFR5 & AVR8_TIFR5_ICF5_MASK) >> AVR8_TIFR5_ICF5_SHIFT)
	491	#define AVR8_TIFR5_OCF5C ((AVR8_TIFR5 & AVR8_TIFR5_OCF5C_MASK) >> AVR8_TIFR5_OCF5C_SHIFT)
	492	#define AVR8_TIFR5_OCF5B ((AVR8_TIFR5 & AVR8_TIFR5_OCF5B_MASK) >> AVR8_TIFR5_OCF5B_SHIFT)
	493	#define AVR8_TIFR5_OCF5A ((AVR8_TIFR5 & AVR8_TIFR5_OCF5A_MASK) >> AVR8_TIFR5_OCF5A_SHIFT)
	494	#define AVR8_TIFR5_TOV5 ((AVR8_TIFR5 & AVR8_TIFR5_TOV5_MASK) >> AVR8_TIFR5_TOV5_SHIFT)
	495
	496	//---------------------------------------------------------------
	497
357	498	#define AVR8_OCR0A              m_r[AVR8_REGIDX_OCR0A]
358	499	#define AVR8_OCR0B              m_r[AVR8_REGIDX_OCR0B]
359	500	#define AVR8_TCNT0              m_r[AVR8_REGIDX_TCNT0]
r26888	r26889
372	513	#define AVR8_TCNT2              m_r[AVR8_REGIDX_TCNT2]
373	514	#define AVR8_WGM2               (((AVR8_TCCR2B & 0x08) >> 1) | (AVR8_TCCR2A & 0x03))
374	515
375		#define AVR8_TCNT3L             m_r[AVR8_REGIDX_TCNT3L]
376		#define AVR8_TCNT3H             m_r[AVR8_REGIDX_TCNT3H]
	516	#define AVR8_ICR3               ((AVR8_ICR3H  << 8) | AVR8_ICR3L)
	517	#define AVR8_OCR3A              ((AVR8_OCR3AH << 8) | AVR8_OCR3AL)
377	518
378	519	#define AVR8_ICR4               ((AVR8_ICR4H  << 8) | AVR8_ICR4L)
379	520	#define AVR8_ICR4H              (m_r[AVR8_REGIDX_ICR4H])
380	521	#define AVR8_ICR4L              (m_r[AVR8_REGIDX_ICR4L])
381		#define AVR8_OCR4AH              m_r[AVR8_REGIDX_OCR4AH]
382		#define AVR8_OCR4AL              m_r[AVR8_REGIDX_OCR4AL]
383	522	#define AVR8_OCR4A              ((AVR8_OCR4AH << 8) | AVR8_OCR4AL)
384	523	#define AVR8_OCR4B              m_r[AVR8_REGIDX_OCR4B]
385	524	#define AVR8_TCNT4              m_r[AVR8_REGIDX_TCNT4]
386	525
387		#define AVR8_TCNT4L             m_r[AVR8_REGIDX_TCNT4L]
388		#define AVR8_TCNT4H             m_r[AVR8_REGIDX_TCNT4H]
	526	#define AVR8_ICR5               ((AVR8_ICR5H  << 8) | AVR8_ICR5L)
	527	#define AVR8_OCR5A              ((AVR8_OCR5AH << 8) | AVR8_OCR5AL)
389	528
390	529	#define AVR8_GTCCR_PSRASY_MASK  0x02
391	530	#define AVR8_GTCCR_PSRASY_SHIFT 1
r26888	r26889
406	545
407	546	#define AVR8_PORTB_MOSI         0x08
408	547
	548	#define AVR8_EECR               m_r[AVR8_REGIDX_EECR] & 0x3F; //bits 6 and 7 are reserved and will always read as zero
	549	#define AVR8_EECR_EEPM_MASK     0x30
	550	#define AVR8_EECR_EERIE_MASK    0x08
	551	#define AVR8_EECR_EEMPE_MASK    0x04
	552	#define AVR8_EECR_EEPE_MASK     0x02
	553	#define AVR8_EECR_EERE_MASK     0x01
	554	#define AVR8_EECR_EEPM          ((AVR8_EECR & AVR8_EECR_EEPM_MASK) >> 4)
	555	#define AVR8_EECR_EERIE         ((AVR8_EECR & AVR8_EECR_EERIE_MASK) >> 3)
	556	#define AVR8_EECR_EEMPE         ((AVR8_EECR & AVR8_EECR_EEMPE_MASK) >> 2)
	557	#define AVR8_EECR_EEPE          ((AVR8_EECR & AVR8_EECR_EEPE_MASK) >> 1)
	558	#define AVR8_EECR_EERE          ((AVR8_EECR & AVR8_EECR_EERE_MASK) >> 0)
	559
409	560	//**************************************************************************
410	561	//  DEVICE INTERFACE
411	562	//**************************************************************************
r26888	r26889
488	639	m_efuses(0xFF),
489	640	m_lock_bits(0xFF),
490	641	m_pc(0),
491		m_timer0_top(0),
492		m_timer0_increment(1),
493		m_timer0_prescale(0),
494		m_timer0_prescale_count(0),
495		m_timer1_top(0),
496		m_timer1_increment(1),
497		m_timer1_prescale(0),
498		m_timer1_prescale_count(0),
499		m_timer2_top(0),
500		m_timer2_increment(1),
501		m_timer2_prescale(0),
502		m_timer2_prescale_count(0),
503		m_timer4_top(0),
504		m_timer4_increment(1),
505		m_timer4_prescale(0),
506		m_timer4_prescale_count(0),
507	642	m_spi_active(false),
508	643	m_spi_prescale(0),
509	644	m_spi_prescale_count(0),
r26888	r26889
513	648	m_elapsed_cycles(0)
514	649	{
515	650	// Allocate & setup
	651
	652	for (int t=0; t<=5; t++){
	653	m_timer_top[t] = 0;
	654	m_timer_increment[t] = 1;
	655	m_timer_prescale[t] = 0;
	656	m_timer_prescale_count[t] = 0;
	657	}
516	658	}
517	659
518	660
r26888	r26889
658	800	// register our state for saving
659	801	save_item(NAME(m_pc));
660	802	save_item(NAME(m_r));
661		save_item(NAME(m_timer0_top));
662		save_item(NAME(m_timer0_increment));
663		save_item(NAME(m_timer0_prescale));
664		save_item(NAME(m_timer0_prescale_count));
665		save_item(NAME(m_timer1_top));
666		save_item(NAME(m_timer1_increment));
667		save_item(NAME(m_timer1_prescale));
668		save_item(NAME(m_timer1_prescale_count));
669		save_item(NAME(m_timer2_top));
670		save_item(NAME(m_timer2_increment));
671		save_item(NAME(m_timer2_prescale));
672		save_item(NAME(m_timer2_prescale_count));
673		save_item(NAME(m_timer4_top));
674		save_item(NAME(m_timer4_increment));
675		save_item(NAME(m_timer4_prescale));
676		save_item(NAME(m_timer4_prescale_count));
	803	save_item(NAME(m_timer_top[0]));
	804	save_item(NAME(m_timer_increment[0]));
	805	save_item(NAME(m_timer_prescale[0]));
	806	save_item(NAME(m_timer_prescale_count[0]));
	807	save_item(NAME(m_timer_top[1]));
	808	save_item(NAME(m_timer_increment[1]));
	809	save_item(NAME(m_timer_prescale[1]));
	810	save_item(NAME(m_timer_prescale_count[1]));
	811	save_item(NAME(m_timer_top[2]));
	812	save_item(NAME(m_timer_increment[2]));
	813	save_item(NAME(m_timer_prescale[2]));
	814	save_item(NAME(m_timer_prescale_count[2]));
	815	save_item(NAME(m_timer_top[3]));
	816	save_item(NAME(m_timer_increment[3]));
	817	save_item(NAME(m_timer_prescale[3]));
	818	save_item(NAME(m_timer_prescale_count[3]));
	819	save_item(NAME(m_timer_top[4]));
	820	save_item(NAME(m_timer_increment[4]));
	821	save_item(NAME(m_timer_prescale[4]));
	822	save_item(NAME(m_timer_prescale_count[4]));
	823	save_item(NAME(m_timer_top[5]));
	824	save_item(NAME(m_timer_increment[5]));
	825	save_item(NAME(m_timer_prescale[5]));
	826	save_item(NAME(m_timer_prescale_count[5]));
677	827	save_item(NAME(m_addr_mask));
678	828	save_item(NAME(m_interrupt_pending));
679	829	save_item(NAME(m_icount));
r26888	r26889
712	862	logerror("AVR Boot loader section size: %d words\n", m_boot_size);
713	863	}
714	864
715		m_r[AVR8_REGIDX_SPL] = 0;
716		m_r[AVR8_REGIDX_SPH] = 0;
717
718	865	for (int i = 0; i < 0x200; i++)
719	866	{
720	867	m_r[i] = 0;
r26888	r26889
724	871	m_spi_prescale = 0;
725	872	m_spi_prescale_count = 0;
726	873
727		m_timer0_top = 0;
728		m_timer0_increment = 1;
729		m_timer0_prescale = 0;
730		m_timer0_prescale_count = 0;
	874	for (int t=0; t<=5; t++){
	875	m_timer_top[t] = 0;
	876	m_timer_increment[t] = 1;
	877	m_timer_prescale[t] = 0;
	878	m_timer_prescale_count[t] = 0;
	879	}
731	880
732		m_timer1_top = 0;
733		m_timer1_increment = 1;
734		m_timer1_prescale = 0;
735		m_timer1_prescale_count = 0;
736
737		m_timer2_top = 0;
738		m_timer2_increment = 1;
739		m_timer2_prescale = 0;
740		m_timer2_prescale_count = 0;
741
742		m_timer4_top = 0;
743		m_timer4_increment = 1;
744		m_timer4_prescale = 0;
745		m_timer4_prescale_count = 0;
746
747		AVR8_TIMSK1 = 0;
748		AVR8_OCR1AH = 0;
749		AVR8_OCR1AL = 0;
750		AVR8_OCR1BH = 0;
751		AVR8_OCR1BL = 0;
752		AVR8_OCR1CH = 0;
753		AVR8_OCR1CL = 0;
754		AVR8_ICR1H = 0;
755		AVR8_ICR1L = 0;
756		AVR8_TCNT1H = 0;
757		AVR8_TCNT1L = 0;
758		AVR8_TCNT2 = 0;
759
760		AVR8_TIMSK4 = 0;
761		AVR8_TCNT4H = 0;
762		AVR8_ICR4H = 0;
763		AVR8_ICR4L = 0;
764		AVR8_TCNT4L = 0;
765
766	881	m_interrupt_pending = false;
767
768	882	m_elapsed_cycles = 0;
769	883	}
770	884
r26888	r26889
1022	1136	}
1023	1137	}
1024	1138
1025		if (m_timer0_prescale != 0)
1026		{
1027		m_timer0_prescale_count++;
1028		if (m_timer0_prescale_count >= m_timer0_prescale)
1029		{
1030		timer0_tick();
1031		m_timer0_prescale_count -= m_timer0_prescale;
1032		}
1033		}
	1139	for (int t=0; t<=5; t++){
	1140	if (m_timer_prescale[t] != 0)
	1141	{
	1142	m_timer_prescale_count[t]++;
	1143	if (m_timer_prescale_count[t] >= m_timer_prescale[t])
	1144	{
	1145	switch (t){
	1146	case 0: timer0_tick(); break;
	1147	case 1: timer1_tick(); break;
	1148	case 2: timer2_tick(); break;
	1149	case 3: timer3_tick(); break;
	1150	case 4: timer4_tick(); break;
	1151	case 5: timer5_tick(); break;
	1152	}
	1153	m_timer_prescale_count[t] -= m_timer_prescale[t];
	1154	}
	1155	}
	1156	}
1034	1157
1035		if (m_timer1_prescale != 0)
1036		{
1037		m_timer1_prescale_count++;
1038		if (m_timer1_prescale_count >= m_timer1_prescale)
1039		{
1040		timer1_tick();
1041		m_timer1_prescale_count -= m_timer1_prescale;
1042		}
1043		}
1044
1045		if (m_timer2_prescale != 0)
1046		{
1047		m_timer2_prescale_count++;
1048		if (m_timer2_prescale_count == m_timer2_prescale)
1049		{
1050		timer2_tick();
1051		m_timer2_prescale_count -= m_timer2_prescale;
1052		}
1053		}
1054
1055		if (m_timer4_prescale != 0)
1056		{
1057		m_timer4_prescale_count++;
1058		if (m_timer4_prescale_count == m_timer4_prescale)
1059		{
1060		timer4_tick();
1061		m_timer4_prescale_count -= m_timer4_prescale;
1062		}
1063		}
1064
1065	1158	}
1066	1159	}
1067	1160
	1161	//   UINT8 ocr0[2] = { m_r[AVR8_REGIDX_OCR0A], m_r[AVR8_REGIDX_OCR0B] };
	1162	//TODO   UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR4_OCF0B_SHIFT) };
	1163	//TODO   UINT8 int0[2] = { AVR8_INTIDX_OCF0A, AVR8_INTIDX_OCF0B };
	1164
	1165	#define LOG_TIMER_0 0
	1166	#define LOG_TIMER_5 1
1068	1167	// Timer 0 Handling
1069	1168	void avr8_device::timer0_tick()
1070	1169	{
1071		/*
1072		UINT16 count = m_r[AVR8_REGIDX_TCNT0];
1073		INT32 wgm0 = ((m_r[AVR8_REGIDX_TCCR0B] & AVR8_TCCR0B_WGM0_2_MASK) >> 1) |
1074		(m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_WGM0_10_MASK);
	1170	#if LOG_TIMER_0
	1171	printf("AVR8_WGM0: %d\n", AVR8_WGM0);
	1172	printf("AVR8_TCCR0A_COM0B: %d\n", AVR8_TCCR0A_COM0B);
	1173	#endif
1075	1174
1076		// Cache things in array form to avoid a compare+branch inside a potentially high-frequency timer
1077		//UINT8 compare_mode[2] = { (m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0A_MASK) >> AVR8_TCCR0A_COM0A_SHIFT,
1078		//(m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0B_MASK) >> AVR8_TCCR0A_COM0B_SHIFT };
1079		UINT8 ocr0[2] = { m_r[AVR8_REGIDX_OCR0A], m_r[AVR8_REGIDX_OCR0B] };
1080		UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR0_OCF0B_SHIFT) };
1081		INT32 increment = m_timer0_increment;
	1175	UINT8 count = m_r[AVR8_REGIDX_TCNT0];
	1176	INT32 increment = m_timer_increment[0];
1082	1177
1083		for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
	1178	switch(AVR8_WGM0)
1084	1179	{
1085		switch(wgm0)
1086		{
1087		case WGM02_FAST_PWM:
1088		if(count == ocr0[reg])
1089		{
1090		if (reg == 0)
1091		{
1092		m_r[AVR8_REGIDX_TIFR0] |= AVR8_TIFR0_TOV0_MASK;
1093		count = 0;
1094		increment = 0;
1095		}
	1180	case WGM02_NORMAL:
	1181	printf("WGM02_NORMAL: Unimplemented timer#0 waveform generation mode\n");
	1182	break;
1096	1183
1097		m_r[AVR8_REGIDX_TIFR0] |= ocf0[reg];
1098		}
1099		else if(count == 0)
1100		{
1101		if (reg == 0)
1102		{
1103		m_r[AVR8_REGIDX_TIFR0] &= ~AVR8_TIFR0_TOV0_MASK;
1104		}
1105		}
1106		break;
	1184	case WGM02_PWM_PC:
	1185	printf("WGM02_PWM_PC: Unimplemented timer#0 waveform generation mode\n");
	1186	break;
1107	1187
1108		case WGM02_FAST_PWM_CMP:
1109		if(count == ocr0[reg])
1110		{
1111		if (reg == 0)
1112		{
1113		m_r[AVR8_REGIDX_TIFR0] |= AVR8_TIFR0_TOV0_MASK;
1114		count = 0;
1115		increment = 0;
1116		}
	1188	case WGM02_CTC_CMP:
	1189	switch(AVR8_TCCR0A_COM0B){
	1190	case 0: /* Normal Operation */
	1191	if (count == m_timer_top[0]){
	1192	m_timer_top[0] = 0;
	1193	}
	1194	break;
	1195	case 1: /* Toggle OC0B on compare match */
	1196	if (count == m_timer_top[0]){
	1197	m_timer_top[0] = 0;
	1198	#if LOG_TIMER_0
	1199	printf("[0] Toggle OC0B\n");
	1200	#endif
	1201	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) ^ (1 << 5));
	1202	}
	1203	break;
	1204	case 2: /* Clear OC0B on compare match */
	1205	if (count == m_timer_top[0]){
	1206	m_timer_top[0] = 0;
	1207	//Clear OC0B
	1208	#if LOG_TIMER_0
	1209	printf("[0] Clear OC0B\n");
	1210	#endif
	1211	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) & ~(1 << 5));
	1212	}
	1213	break;
	1214	case 3: /* Set OC0B on compare match */
	1215	if (count == m_timer_top[0]){
	1216	m_timer_top[0] = 0;
	1217	#if LOG_TIMER_0
	1218	printf("[0] Set OC0B\n");
	1219	#endif
	1220	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) | (1 << 5));
	1221	}
	1222	break;
	1223	}
	1224	break;
1117	1225
1118		m_r[AVR8_REGIDX_TIFR0] |= ocf0[reg];
1119		}
1120		else if(count == 0)
1121		{
1122		if (reg == 0)
1123		{
1124		m_r[AVR8_REGIDX_TIFR0] &= ~AVR8_TIFR0_TOV0_MASK;
1125		}
1126		}
1127		break;
1128
1129		default:
1130		// TODO
1131		break;
1132		}
1133		switch(compare_mode[reg])
1134		{
1135		case 0:
1136		//verboselog(m_pc, 0, "update_timer0_compare_mode: Normal port operation (OC0 disconnected)\n");
1137		break;
1138
1139		case 1:
1140		case 2:
1141		// TODO
1142		break;
1143
1144		case 3:
1145		break;
1146		}
1147		}
1148
1149		m_r[AVR8_REGIDX_TCNT0] = count + increment;
1150
1151		update_interrupt(AVR8_INTIDX_OCF0A);
1152		update_interrupt(AVR8_INTIDX_OCF0B);
1153		update_interrupt(AVR8_INTIDX_TOV0);
1154		*/
1155		}
1156
1157		void avr8_device::update_timer0_waveform_gen_mode()
1158		{
1159		m_timer0_top = 0;
1160		switch(AVR8_WGM0)
1161		{
1162		case WGM02_NORMAL:
1163		case WGM02_PWM_PC:
1164	1226	case WGM02_FAST_PWM:
1165		m_timer0_top = 0x00ff;
1166		break;
	1227	printf("WGM02_FAST_PWM: Unimplemented timer#0 waveform generation mode\n");
	1228	break;
1167	1229
1168		case WGM02_CTC_CMP:
1169	1230	case WGM02_PWM_PC_CMP:
	1231	printf("WGM02_PWM_PC_CMP: Unimplemented timer#0 waveform generation mode\n");
	1232	break;
	1233
1170	1234	case WGM02_FAST_PWM_CMP:
1171		m_timer0_top = AVR8_OCR0A;
1172		break;
	1235	printf("WGM02_FAST_PWM_CMP: Unimplemented timer#0 waveform generation mode\n");
	1236	break;
1173	1237
1174	1238	default:
1175		verboselog(m_pc, 0, "update_timer0_waveform_gen_mode: Unsupported waveform generation type: %d\n", AVR8_WGM0);
	1239	verboselog(m_pc, 0, "update_timer0_compare_mode: Unknown waveform generation mode: %02x\n", AVR8_WGM0);
1176	1240	break;
1177	1241	}
	1242
	1243	count = count & 0xff;
	1244
	1245	count += increment;
	1246	m_r[AVR8_REGIDX_TCNT0] = count & 0xff;
1178	1247	}
1179	1248
1180	1249	void avr8_device::changed_tccr0a(UINT8 data)
r26888	r26889
1187	1256
1188	1257	if(changed & AVR8_TCCR0A_WGM0_10_MASK)
1189	1258	{
1190		// TODO
1191		update_timer0_waveform_gen_mode();
	1259	update_timer_waveform_gen_mode(0, AVR8_WGM0);
1192	1260	}
1193	1261	}
1194	1262
r26888	r26889
1200	1268
1201	1269	void avr8_device::changed_tccr0b(UINT8 data)
1202	1270	{
	1271	printf("changed_tccr0b: data=0x%02X\n", data);
	1272
1203	1273	UINT8 oldtccr = AVR8_TCCR0B;
1204	1274	UINT8 newtccr = data;
1205	1275	UINT8 changed = newtccr ^ oldtccr;
r26888	r26889
1220	1290
1221	1291	if(changed & AVR8_TCCR0B_WGM0_2_MASK)
1222	1292	{
1223		// TODO
1224		update_timer0_waveform_gen_mode();
	1293	update_timer_waveform_gen_mode(0, AVR8_WGM0);
1225	1294	}
1226	1295
1227	1296	if(changed & AVR8_TCCR0B_CS_MASK)
1228	1297	{
1229		update_timer0_clock_source();
	1298	update_timer_clock_source(0, AVR8_TIMER0_CLOCK_SELECT);
1230	1299	}
1231	1300	}
1232	1301
1233		void avr8_device::update_timer0_clock_source()
1234		{
1235		switch(AVR8_TIMER0_CLOCK_SELECT)
1236		{
1237		case 0: // Counter stopped
1238		m_timer0_prescale = 0;
1239		break;
1240		case 1: // Clk/1; no prescaling
1241		m_timer0_prescale = 1;
1242		break;
1243		case 2: // Clk/8
1244		m_timer0_prescale = 8;
1245		break;
1246		case 3: // Clk/64
1247		m_timer0_prescale = 64;
1248		break;
1249		case 4: // Clk/256
1250		m_timer0_prescale = 256;
1251		break;
1252		case 5: // Clk/1024
1253		m_timer0_prescale = 1024;
1254		break;
1255		case 6: // T0 trigger, falling edge
1256		case 7: // T0 trigger, rising edge
1257		m_timer0_prescale = 0;
1258		verboselog(m_pc, 0, "update_timer0_clock_source: T0 Trigger mode not implemented yet\n");
1259		break;
1260		}
1261
1262		if (m_timer0_prescale_count > m_timer0_prescale)
1263		{
1264		m_timer0_prescale_count = m_timer0_prescale - 1;
1265		}
1266		}
1267
1268	1302	void avr8_device::update_ocr0(UINT8 newval, UINT8 reg)
1269	1303	{
1270	1304	m_r[(reg == AVR8_REG_A) ? AVR8_REGIDX_OCR0A : AVR8_REGIDX_OCR0B] = newval;
r26888	r26889
1287	1321	(m_r[AVR8_REGIDX_OCR1BH] << 8) | m_r[AVR8_REGIDX_OCR1BL] };
1288	1322	UINT8 ocf1[2] = { (1 << AVR8_TIFR1_OCF1A_SHIFT), (1 << AVR8_TIFR1_OCF1B_SHIFT) };
1289	1323	UINT8 int1[2] = { AVR8_INTIDX_OCF1A, AVR8_INTIDX_OCF1B };
1290		INT32 increment = m_timer1_increment;
	1324	INT32 increment = m_timer_increment[1];
1291	1325
1292	1326	for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
1293	1327	{
r26888	r26889
1379	1413	m_r[AVR8_REGIDX_TCNT1L] = count & 0xff;
1380	1414	}
1381	1415
1382		void avr8_device::update_timer1_waveform_gen_mode()
	1416	void avr8_device::update_timer_waveform_gen_mode(UINT8 t, UINT8 mode)
1383	1417	{
1384		// TODO
1385		m_timer1_top = 0;
1386		switch(AVR8_WGM1)
1387		{
1388		case WGM1_NORMAL:
1389		m_timer1_top = 0xffff;
1390		break;
	1418	INT32 oc_val = -1, ic_val = -1;
1391	1419
1392		case WGM1_PWM_8_PC:
1393		case WGM1_FAST_PWM_8:
1394		m_timer1_top = 0x00ff;
1395		break;
	1420	switch (t){
	1421	case 0:
	1422	oc_val = AVR8_OCR0A;
	1423	ic_val = -1;
	1424	break;
	1425	case 1:
	1426	oc_val = AVR8_OCR1A;
	1427	ic_val = AVR8_ICR1;
	1428	break;
	1429	case 2:
	1430	oc_val = AVR8_OCR2A;
	1431	ic_val = -1;
	1432	break;
	1433	case 3:
	1434	oc_val = AVR8_OCR3A;
	1435	ic_val = AVR8_ICR3;
	1436	break;
	1437	case 4:
	1438	oc_val = AVR8_OCR4A;
	1439	ic_val = AVR8_ICR4;
	1440	break;
	1441	case 5:
	1442	oc_val = AVR8_OCR5A;
	1443	ic_val = AVR8_ICR5;
	1444	break;
	1445	}
1396	1446
1397		case WGM1_PWM_9_PC:
1398		case WGM1_FAST_PWM_9:
1399		m_timer1_top = 0x01ff;
1400		break;
	1447	INT32 top_values_02[8] = {0xFF, 0xFF, oc_val, 0xFF, -1, oc_val, -1, oc_val}; //table 20-8
1401	1448
1402		case WGM1_PWM_10_PC:
1403		case WGM1_FAST_PWM_10:
1404		m_timer1_top = 0x03ff;
1405		break;
	1449	INT32 top_values_1345[16] = {0xFFFF, 0x00FF, 0x01FF, 0x03FF,
	1450	oc_val, 0x00FF, 0x01FF, 0x03FF,
	1451	ic_val, oc_val, ic_val, oc_val,
	1452	ic_val, -1,     ic_val, oc_val}; //table 17-2
1406	1453
1407		case WGM1_PWM_PFC_ICR:
1408		case WGM1_PWM_PC_ICR:
1409		case WGM1_CTC_ICR:
1410		case WGM1_FAST_PWM_ICR:
1411		m_timer1_top = AVR8_ICR1;
1412		break;
	1454	switch(t){
	1455	case 0:
	1456	case 2:
	1457	m_timer_top[t] = top_values_02[mode];
	1458	break;
	1459	case 1:
	1460	case 3:
	1461	case 4:
	1462	case 5:
	1463	m_timer_top[t] = top_values_1345[mode];
	1464	break;
	1465	}
1413	1466
1414		case WGM1_PWM_PFC_OCR:
1415		case WGM1_PWM_PC_OCR:
1416		case WGM1_CTC_OCR:
1417		case WGM1_FAST_PWM_OCR:
1418		m_timer1_top = AVR8_OCR1A;
1419		break;
1420
1421		default:
1422		verboselog(m_pc, 0, "update_timer1_waveform_gen_mode: Unsupported waveform generation type: %d\n", AVR8_WGM1);
1423		break;
	1467	if (m_timer_top[t] == -1){
	1468	m_timer_top[t] = 0;
	1469	printf("update_timer_waveform_gen_mode: Timer #%d - Unsupported waveform generation type: %d\n", t, mode);
1424	1470	}
1425	1471	}
1426	1472
r26888	r26889
1434	1480
1435	1481	if(changed & AVR8_TCCR1A_WGM1_10_MASK)
1436	1482	{
1437		// TODO
1438		update_timer1_waveform_gen_mode();
	1483	update_timer_waveform_gen_mode(1, AVR8_WGM1);
1439	1484	}
1440	1485	}
1441	1486
r26888	r26889
1450	1495	//verboselog(m_pc, 0, "update_timer1_input_edge_select: TODO; Clocking edge is %s\n", "test");
1451	1496	}
1452	1497
1453		void avr8_device::update_timer1_clock_source()
	1498	void avr8_device::changed_tccr1b(UINT8 data)
1454	1499	{
1455		switch(AVR8_TIMER1_CLOCK_SELECT)
1456		{
1457		case 0: // Counter stopped
1458		m_timer1_prescale = 0;
1459		break;
1460		case 1: // Clk/1; no prescaling
1461		m_timer1_prescale = 1;
1462		break;
1463		case 2: // Clk/8
1464		m_timer1_prescale = 8;
1465		break;
1466		case 3: // Clk/32
1467		m_timer1_prescale = 32;
1468		break;
1469		case 4: // Clk/64
1470		m_timer1_prescale = 64;
1471		break;
1472		case 5: // Clk/128
1473		m_timer1_prescale = 128;
1474		break;
1475		case 6: // T1 trigger, falling edge
1476		case 7: // T1 trigger, rising edge
1477		m_timer1_prescale = 0;
1478		verboselog(m_pc, 0, "update_timer1_clock_source: T1 Trigger mode not implemented yet\n");
1479		break;
1480		}
	1500	printf("changed_tccr1b: data=0x%02X\n", data);
1481	1501
1482		if (m_timer1_prescale_count > m_timer1_prescale)
1483		{
1484		m_timer1_prescale_count = m_timer1_prescale - 1;
1485		}
1486		}
1487
1488		void avr8_device::changed_tccr1b(UINT8 data)
1489		{
1490	1502	UINT8 oldtccr = AVR8_TCCR1B;
1491	1503	UINT8 newtccr = data;
1492	1504	UINT8 changed = newtccr ^ oldtccr;
r26888	r26889
1507	1519
1508	1520	if(changed & AVR8_TCCR1B_WGM1_32_MASK)
1509	1521	{
1510		update_timer1_waveform_gen_mode();
	1522	update_timer_waveform_gen_mode(1, AVR8_WGM1);
1511	1523	}
1512	1524
1513	1525	if(changed & AVR8_TCCR1B_CS_MASK)
1514	1526	{
1515		update_timer1_clock_source();
	1527	update_timer_clock_source(1, AVR8_TIMER1_CLOCK_SELECT);
1516	1528	}
1517	1529	}
1518	1530
r26888	r26889
1539	1551	//(m_r[AVR8_REGIDX_TCCR2A] & AVR8_TCCR2A_COM2B_MASK) >> AVR8_TCCR2A_COM2B_SHIFT };
1540	1552	UINT8 ocr2[2] = { m_r[AVR8_REGIDX_OCR2A], m_r[AVR8_REGIDX_OCR2B] };
1541	1553	UINT8 ocf2[2] = { (1 << AVR8_TIFR2_OCF2A_SHIFT), (1 << AVR8_TIFR2_OCF2B_SHIFT) };
1542		INT32 increment = m_timer2_increment;
	1554	INT32 increment = m_timer_increment[2];
1543	1555
1544	1556	for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
1545	1557	{
r26888	r26889
1616	1628	update_interrupt(AVR8_INTIDX_TOV2);
1617	1629	}
1618	1630
1619		void avr8_device::update_timer2_waveform_gen_mode()
1620		{
1621		m_timer2_top = 0;
1622		switch(AVR8_WGM2)
1623		{
1624		case WGM02_NORMAL:
1625		case WGM02_PWM_PC:
1626		case WGM02_FAST_PWM:
1627		m_timer2_top = 0x00ff;
1628		break;
1629
1630		case WGM02_CTC_CMP:
1631		case WGM02_PWM_PC_CMP:
1632		case WGM02_FAST_PWM_CMP:
1633		m_timer2_top = AVR8_OCR2A;
1634		break;
1635
1636		default:
1637		verboselog(m_pc, 0, "update_timer2_waveform_gen_mode: Unsupported waveform generation type: %d\n", AVR8_WGM2);
1638		break;
1639		}
1640		}
1641
1642	1631	void avr8_device::changed_tccr2a(UINT8 data)
1643	1632	{
1644	1633	UINT8 oldtccr = AVR8_TCCR2A;
r26888	r26889
1650	1639	if(changed & AVR8_TCCR2A_WGM2_10_MASK)
1651	1640	{
1652	1641	// TODO
1653		update_timer2_waveform_gen_mode();
	1642	update_timer_waveform_gen_mode(2, AVR8_WGM2);
1654	1643	}
1655	1644	}
1656	1645
1657		void avr8_device::update_timer2_clock_source()
1658		{
1659		switch(AVR8_TIMER2_CLOCK_SELECT)
1660		{
1661		case 0: // Counter stopped
1662		m_timer2_prescale = 0;
1663		break;
1664		case 1: // Clk/1; no prescaling
1665		m_timer2_prescale = 1;
1666		break;
1667		case 2: // Clk/8
1668		m_timer2_prescale = 8;
1669		break;
1670		case 3: // Clk/32
1671		m_timer2_prescale = 32;
1672		break;
1673		case 4: // Clk/64
1674		m_timer2_prescale = 64;
1675		break;
1676		case 5: // Clk/128
1677		m_timer2_prescale = 128;
1678		break;
1679		case 6: // Clk/256
1680		m_timer2_prescale = 256;
1681		break;
1682		case 7: // Clk/1024
1683		m_timer2_prescale = 1024;
1684		break;
1685		}
1686
1687		if (m_timer2_prescale_count > m_timer2_prescale)
1688		{
1689		m_timer2_prescale_count = m_timer2_prescale - 1;
1690		}
1691		}
1692
1693	1646	void avr8_device::timer2_force_output_compare(int reg)
1694	1647	{
1695	1648	// TODO
r26888	r26889
1698	1651
1699	1652	void avr8_device::changed_tccr2b(UINT8 data)
1700	1653	{
	1654	printf("changed_tccr2b: data=0x%02X\n", data);
	1655
1701	1656	UINT8 oldtccr = AVR8_TCCR2B;
1702	1657	UINT8 newtccr = data;
1703	1658	UINT8 changed = newtccr ^ oldtccr;
r26888	r26889
1718	1673
1719	1674	if(changed & AVR8_TCCR2B_WGM2_2_MASK)
1720	1675	{
1721		// TODO
1722		update_timer2_waveform_gen_mode();
	1676	update_timer_waveform_gen_mode(2, AVR8_WGM2);
1723	1677	}
1724	1678
1725	1679	if(changed & AVR8_TCCR2B_CS_MASK)
1726	1680	{
1727		update_timer2_clock_source();
	1681	update_timer_clock_source(2, AVR8_TIMER2_CLOCK_SELECT);
1728	1682	}
1729	1683	}
1730	1684
r26888	r26889
1737	1691
1738	1692	/************************************************************************************************/
1739	1693
	1694	// Timer 3 Handling
	1695	void avr8_device::timer3_tick()
	1696	{
	1697	}
	1698
	1699	/************************************************************************************************/
	1700
1740	1701	void avr8_device::timer4_tick()
1741	1702	{
1742	1703	/* TODO: Handle comparison, setting OC1x pins, detection of BOTTOM and TOP */
	1704	//  printf("AVR8_WGM4: %d\n", AVR8_WGM4);
	1705	//  printf("AVR8_TCCR4A_COM4B: %d\n", AVR8_TCCR4A_COM4B);
1743	1706
1744	1707	UINT16 count = (m_r[AVR8_REGIDX_TCNT4H] << 8) | m_r[AVR8_REGIDX_TCNT4L];
1745	1708
r26888	r26889
1750	1713	(m_r[AVR8_REGIDX_OCR4BH] << 8) | m_r[AVR8_REGIDX_OCR4BL] };
1751	1714	//TODO   UINT8 ocf4[2] = { (1 << AVR8_TIFR4_OCF4A_SHIFT), (1 << AVR8_TIFR4_OCF4B_SHIFT) };
1752	1715	//TODO   UINT8 int4[2] = { AVR8_INTIDX_OCF4A, AVR8_INTIDX_OCF4B };
1753		INT32 increment = m_timer4_increment;
	1716	INT32 increment = m_timer_increment[4];
1754	1717
1755		for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
	1718	switch(AVR8_WGM4)
1756	1719	{
1757		switch(AVR8_WGM4)
1758		{
1759		case WGM4_FAST_PWM_8:
1760		case WGM4_FAST_PWM_9:
1761		case WGM4_FAST_PWM_10:
1762		if (count == m_timer4_top){
1763		//printf("[T4] tick WGM4_FAST_PWM_8: %d\n", count);
1764		count=0;
1765		}
1766		break;
	1720	case WGM4_FAST_PWM_8:
	1721	case WGM4_FAST_PWM_9:
	1722	case WGM4_FAST_PWM_10:
	1723	switch(AVR8_TCCR4A_COM4B){
	1724	case 0: /* Normal Operation */
	1725	break;
	1726	case 1: /* TODO */
	1727	break;
	1728	case 2: /* Non-inverting mode */
	1729	if (count == m_timer_top[4]){
	1730	//Clear OC0B
	1731	printf("[2] Clear OC0B\n");
	1732	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) & ~(1 << 5));
	1733	} else if (count == 0){
	1734	//Set OC0B
	1735	printf("[2] Set OC0B\n");
	1736	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) | (1 << 5));
	1737	}
	1738	break;
	1739	case 3: /* Inverting mode */
	1740	if (count == m_timer_top[4]){
	1741	//Set OC0B
	1742	printf("[3] Set OC0B\n");
	1743	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) | (1 << 5));
	1744	} else if (count == 0){
	1745	//Clear OC0B
	1746	printf("[3] Clear OC0B\n");
	1747	m_io->write_byte(AVR8_IO_PORTG, m_io->read_byte(AVR8_IO_PORTG) & ~(1 << 5));
	1748	}
	1749	break;
	1750	}
	1751	break;
1767	1752
1768		case WGM4_CTC_OCR:
1769		//printf("[T4] tick WGM4_CTC_OCR: %d\n", count);
1770		if (count == 0xffff)
1771		{
1772		m_r[AVR8_REGIDX_TIFR4] |= AVR8_TIFR4_TOV4_MASK;
1773		update_interrupt(AVR8_INTIDX_TOV4);
1774		count = 0;
1775		increment = 0;
1776		}
	1753	case WGM4_CTC_OCR:
	1754	//printf("[T4] tick WGM4_CTC_OCR: %d\n", count);
	1755	if (count == 0xffff)
	1756	{
	1757	m_r[AVR8_REGIDX_TIFR4] |= AVR8_TIFR4_TOV4_MASK;
	1758	update_interrupt(AVR8_INTIDX_TOV4);
	1759	count = 0;
	1760	increment = 0;
	1761	}
1777	1762
1778		if (count == ocr4[reg])
1779		{
1780		if (reg == 0)
1781		{
1782		count = 0;
1783		increment = 0;
1784		}
1785		//TODO               m_r[AVR8_REGIDX_TIFR4] |= ocf4[reg];
1786		//TODO               update_interrupt(int4[reg]);
1787		}
1788		else if (count == 0)
1789		{
1790		if (reg == 0)
1791		{
1792		//TODO                  m_r[AVR8_REGIDX_TIFR4] &= ~AVR8_TIFR4_TOV4_MASK;
1793		//TODO                  update_interrupt(AVR8_INTIDX_TOV4);
1794		}
	1763	if (count == ocr4[0]) /*TODO: test for all 3 register*/
	1764	{}
	1765	else if (count == 0)
	1766	{}
	1767	break;
1795	1768
1796		//TODO               m_r[AVR8_REGIDX_TIFR4] &= ~ocf4[reg];
1797		//TODO               update_interrupt(int4[reg]);
1798		}
1799		break;
	1769	case WGM1_FAST_PWM_OCR:
	1770	if(count == ocr4[0]) /*TODO: test for all 3 register*/
	1771	{}
	1772	else if(count == 0)
	1773	{}
	1774	break;
1800	1775
1801		case WGM1_FAST_PWM_OCR:
1802		if(count == ocr4[reg])
1803		{
1804		if (reg == 0)
1805		{
1806		//TODO                  m_r[AVR8_REGIDX_TIFR4] |= AVR8_TIFR4_TOV4_MASK;
1807		//TODO                  update_interrupt(AVR8_INTIDX_TOV4);
1808		count = 0;
1809		increment = 0;
1810		}
1811
1812		//TODO               m_r[AVR8_REGIDX_TIFR4] |= ocf4[reg];
1813		//TODO               update_interrupt(int4[reg]);
1814		}
1815		else if(count == 0)
1816		{
1817		if (reg == 0)
1818		{
1819		//TODO                  m_r[AVR8_REGIDX_TIFR4] &= ~AVR8_TIFR4_TOV4_MASK;
1820		//TODO                  update_interrupt(AVR8_INTIDX_TOV4);
1821		}
1822
1823		//TODO               m_r[AVR8_REGIDX_TIFR4] &= ~ocf4[reg];
1824		//TODO               update_interrupt(int4[reg]);
1825		}
1826		break;
1827
1828		default:
1829		//        printf("[T4] tick Unknown waveform generation mode: %d\n", count);
1830
1831		verboselog(m_pc, 0, "update_timer4_compare_mode: Unknown waveform generation mode: %02x\n", wgm4);
1832		break;
1833		}
1834		/*
1835		switch(compare_mode[reg])
1836		{
1837		case 0:
1838		//verboselog(m_pc, 0, "update_timer4_compare_mode: Normal port operation (OC1 disconnected)\n");
1839		break;
1840
1841		case 1:
1842		case 2:
1843		// TODO
1844		break;
1845
1846		case 3:
1847		break;
1848		}
1849		*/
	1776	default:
	1777	verboselog(m_pc, 0, "update_timer4_compare_mode: Unknown waveform generation mode: %02x\n", wgm4);
	1778	break;
1850	1779	}
1851	1780
1852	1781	count += increment;
r26888	r26889
1854	1783	m_r[AVR8_REGIDX_TCNT4L] = count & 0xff;
1855	1784	}
1856	1785
1857		void avr8_device::update_timer4_clock_source()
	1786	void avr8_device::update_timer_clock_source(UINT8 t, UINT8 clock_select)
1858	1787	{
1859		debugger_break(machine());
1860		switch(AVR8_TIMER4_CLOCK_SELECT)
1861		{
1862		case 0: // Counter stopped
1863		m_timer4_prescale = 0;
1864		//printf("[T4]: Counter stopped\n");
1865		break;
1866		case 1: // Clk/1; no prescaling
1867		m_timer4_prescale = 1;
1868		//printf("[T4]: prescale = 1\n");
1869		break;
1870		case 2: // Clk/8
1871		m_timer4_prescale = 8;
1872		//printf("[T4]: prescale = 8\n");
1873		break;
1874		case 3: // Clk/64
1875		m_timer4_prescale = 64;
1876		//printf("[T4]: prescale = 64\n");
1877		break;
1878		case 4: // Clk/256
1879		m_timer4_prescale = 256;
1880		//printf("[T4]: prescale = 256\n");
1881		break;
1882		case 5: // Clk/1024
1883		m_timer4_prescale = 1024;
1884		//printf("[T4]: prescale = 1024\n");
1885		break;
1886		case 6: // T0 trigger, falling edge
1887		case 7: // T0 trigger, rising edge
1888		//printf("[T4]: update_timer4_clock_source: T0 Trigger mode not implemented yet\n");
1889		m_timer4_prescale = 0;
1890		verboselog(m_pc, 0, "update_timer4_clock_source: T0 Trigger mode not implemented yet\n");
1891		break;
1892		}
	1788	int prescale_values[8] = {0, 1, 8, 64, 256, 1024, -1, -1};
	1789	m_timer_prescale[t] = prescale_values[clock_select];
1893	1790
1894		if (m_timer4_prescale_count > m_timer4_prescale)
1895		{
1896		m_timer4_prescale_count = m_timer4_prescale - 1;
1897		}
	1791	printf("update_timer_clock_source: t=%d cs=%d\n", t, clock_select);
	1792
	1793	if (m_timer_prescale[t] == -1){
	1794	printf("[Timer #%d]: update_timer_clock_source: External trigger mode not implemented yet\n", t);
	1795	m_timer_prescale[t] = 0;
	1796	}
	1797
	1798	if (m_timer_prescale_count[t] > m_timer_prescale[t])
	1799	m_timer_prescale_count[t] = m_timer_prescale[t] - 1;
1898	1800	}
1899	1801
1900		void avr8_device::update_timer4_waveform_gen_mode()
	1802	void avr8_device::changed_tccr3a(UINT8 data)
1901	1803	{
1902		//printf("[T4] AVR8_WGM4 = %d\n", AVR8_WGM4);
	1804	//TODO: Implement-me
	1805	//   AVR8_TCCR3A = data;
	1806	}
1903	1807
1904		switch(AVR8_WGM4)
1905		{
1906		case WGM4_NORMAL:
1907		m_timer4_top = 0xffff;
1908		break;
	1808	void avr8_device::changed_tccr3b(UINT8 data)
	1809	{
	1810	printf("IMPLEMENT-ME: changed_tccr4b: data=0x%02X\n", data);
	1811	}
1909	1812
1910		case WGM4_PWM_8_PC:
1911		case WGM4_FAST_PWM_8:
1912		m_timer4_top = 0x00ff;
1913		break;
	1813	void avr8_device::changed_tccr3c(UINT8 data)
	1814	{
	1815	//   UINT8 oldtccr = AVR8_TCCR3C;
	1816	//   UINT8 newtccr = data;
	1817	//   UINT8 changed = newtccr ^ oldtccr;
	1818	printf("IMPLEMENT-ME: changed_tccr3c: data=0x%02X\n", data);
1914	1819
1915		case WGM4_PWM_9_PC:
1916		case WGM4_FAST_PWM_9:
1917		m_timer4_top = 0x01ff;
1918		break;
	1820	//   AVR8_TCCR3C = data;
1919	1821
1920		case WGM4_PWM_10_PC:
1921		case WGM4_FAST_PWM_10:
1922		m_timer4_top = 0x03ff;
1923		break;
1924
1925		case WGM4_PWM_PFC_ICR:
1926		case WGM4_PWM_PC_ICR:
1927		case WGM4_CTC_ICR:
1928		case WGM4_FAST_PWM_ICR:
1929		m_timer4_top = AVR8_ICR4;
1930		break;
1931
1932		case WGM4_PWM_PFC_OCR:
1933		case WGM4_PWM_PC_OCR:
1934		case WGM4_CTC_OCR:
1935		case WGM4_FAST_PWM_OCR:
1936		m_timer4_top = AVR8_OCR4A;
1937		break;
1938
1939		default:
1940		m_timer4_top = 0;
1941		verboselog(m_pc, 0, "update_timer4_waveform_gen_mode: Unsupported waveform generation type: %d\n", AVR8_WGM4);
1942		break;
1943		}
	1822	//TODO: Implement-me
1944	1823	}
1945	1824
1946
1947	1825	void avr8_device::changed_tccr4a(UINT8 data)
1948	1826	{
1949	1827	UINT8 oldtccr = AVR8_TCCR4A;
r26888	r26889
1954	1832
1955	1833	if(changed & AVR8_TCCR4A_WGM4_10_MASK)
1956	1834	{
1957		// TODO
1958		update_timer4_waveform_gen_mode();
	1835	update_timer_waveform_gen_mode(4, AVR8_WGM4);
1959	1836	}
1960	1837	}
1961	1838
1962	1839	void avr8_device::changed_tccr4b(UINT8 data)
1963	1840	{
	1841	printf("changed_tccr4b: data=0x%02X\n", data);
	1842
1964	1843	UINT8 oldtccr = AVR8_TCCR4B;
1965	1844	UINT8 newtccr = data;
1966	1845	UINT8 changed = newtccr ^ oldtccr;
r26888	r26889
1981	1860
1982	1861	if(changed & AVR8_TCCR4B_WGM4_32_MASK)
1983	1862	{
1984		update_timer4_waveform_gen_mode();
	1863	update_timer_waveform_gen_mode(4, AVR8_WGM4);
1985	1864	}
1986	1865
1987	1866	if(changed & AVR8_TCCR4B_CS_MASK)
1988	1867	{
1989		update_timer4_clock_source();
	1868	update_timer_clock_source(4, AVR8_TIMER4_CLOCK_SELECT);
1990	1869	}
1991	1870	}
1992	1871
	1872	void avr8_device::changed_tccr4c(UINT8 data)
	1873	{
	1874	//   UINT8 oldtccr = AVR8_TCCR4C;
	1875	//   UINT8 newtccr = data;
	1876	//   UINT8 changed = newtccr ^ oldtccr;
	1877
	1878	AVR8_TCCR4C = data;
	1879
	1880	//TODO: Implement-me
	1881	}
	1882
1993	1883	/************************************************************************************************/
1994	1884
	1885	// Timer 5 Handling
	1886	void avr8_device::timer5_tick()
	1887	{
	1888	#if LOG_TIMER_5
	1889	printf("AVR8_WGM5: %d\n", AVR8_WGM5);
	1890	printf("AVR8_TCCR5A_COM5B: %d\n", AVR8_TCCR5A_COM5B);
	1891	#endif
1995	1892
	1893	UINT16 count = (AVR8_TCNT5H << 8) + AVR8_TCNT5L;
	1894	INT32 increment = m_timer_increment[5];
	1895
	1896	switch(AVR8_WGM5)
	1897	{
	1898	case WGM5_NORMAL:
	1899	case WGM5_PWM_8_PC:
	1900	case WGM5_PWM_9_PC:
	1901	case WGM5_PWM_10_PC:
	1902	//    case WGM5_CTC_OCR:
	1903	case WGM5_FAST_PWM_8:
	1904	case WGM5_FAST_PWM_9:
	1905	case WGM5_FAST_PWM_10:
	1906	case WGM5_PWM_PFC_ICR:
	1907	case WGM5_PWM_PFC_OCR:
	1908	case WGM5_PWM_PC_ICR:
	1909	case WGM5_PWM_PC_OCR:
	1910	case WGM5_CTC_ICR:
	1911	case WGM5_FAST_PWM_ICR:
	1912	case WGM5_FAST_PWM_OCR:
	1913	printf("Unimplemented timer#5 waveform generation mode: WGMM5=0x%02X\n", AVR8_WGM5);
	1914	break;
	1915
	1916	case WGM5_CTC_OCR:
	1917	//TODO: verify this! Can be very wrong!!!
	1918	switch(AVR8_TCCR5A_COM5B){
	1919	case 0: /* Normal Operation */
	1920	if (count == m_timer_top[5]){
	1921	m_timer_top[5] = 0;
	1922	}
	1923	break;
	1924	case 1: /* Toggle OC5B on compare match */
	1925	if (count == m_timer_top[5]){
	1926	m_timer_top[5] = 0;
	1927	#if LOG_TIMER_5
	1928	printf("[5] Toggle OC5B\n");
	1929	#endif
	1930	m_io->write_byte(AVR8_IO_PORTL, m_io->read_byte(AVR8_IO_PORTL) ^ (1 << 4));
	1931	}
	1932	break;
	1933	case 2: /* Clear OC5B on compare match */
	1934	if (count == m_timer_top[5]){
	1935	m_timer_top[5] = 0;
	1936	//Clear OC5B
	1937	#if LOG_TIMER_5
	1938	printf("[5] Clear OC5B\n");
	1939	#endif
	1940	m_io->write_byte(AVR8_IO_PORTL, m_io->read_byte(AVR8_IO_PORTL) & ~(1 << 4));
	1941	}
	1942	break;
	1943	case 3: /* Set OC5B on compare match */
	1944	if (count == m_timer_top[5]){
	1945	m_timer_top[5] = 0;
	1946	#if LOG_TIMER_5
	1947	printf("[5] Set OC5B\n");
	1948	#endif
	1949	m_io->write_byte(AVR8_IO_PORTL, m_io->read_byte(AVR8_IO_PORTL) | (1 << 4));
	1950	}
	1951	break;
	1952	}
	1953	break;
	1954
	1955	default:
	1956	printf("Timer #5: Unknown waveform generation mode: %02x\n", AVR8_WGM5);
	1957	break;
	1958	}
	1959
	1960	count += increment;
	1961	m_r[AVR8_REGIDX_TCNT5H] = (count >> 8) & 0xff;
	1962	m_r[AVR8_REGIDX_TCNT5L] = count & 0xff;
	1963	}
	1964
	1965	void avr8_device::changed_tccr5a(UINT8 data)
	1966	{
	1967	UINT8 oldtccr = AVR8_TCCR5A;
	1968	UINT8 newtccr = data;
	1969	UINT8 changed = newtccr ^ oldtccr;
	1970
	1971	AVR8_TCCR5A = data;
	1972
	1973	if(changed & AVR8_TCCR5A_WGM5_10_MASK)
	1974	{
	1975	update_timer_waveform_gen_mode(5, AVR8_WGM5);
	1976	}
	1977	}
	1978
	1979	void avr8_device::changed_tccr5b(UINT8 data)
	1980	{
	1981	printf("changed_tccr5b: data=0x%02X\n", data);
	1982
	1983	UINT8 oldtccr = AVR8_TCCR5B;
	1984	UINT8 newtccr = data;
	1985	UINT8 changed = newtccr ^ oldtccr;
	1986
	1987	AVR8_TCCR5B = data;
	1988
	1989	if(changed & AVR8_TCCR5C_FOC5A_MASK)
	1990	{
	1991	// TODO
	1992	//      timer5_force_output_compare(AVR8_REG_A);
	1993	}
	1994
	1995	if(changed & AVR8_TCCR5C_FOC5B_MASK)
	1996	{
	1997	// TODO
	1998	//      timer5_force_output_compare(AVR8_REG_B);
	1999	}
	2000
	2001	if(changed & AVR8_TCCR5C_FOC5C_MASK)
	2002	{
	2003	// TODO
	2004	//      timer5_force_output_compare(AVR8_REG_C);
	2005	}
	2006
	2007	if(changed & AVR8_TCCR5B_WGM5_32_MASK)
	2008	{
	2009	update_timer_waveform_gen_mode(5, AVR8_WGM5);
	2010	}
	2011
	2012	if(changed & AVR8_TCCR5B_CS_MASK)
	2013	{
	2014	update_timer_clock_source(5, AVR8_TIMER5_CLOCK_SELECT);
	2015	}
	2016	}
	2017
	2018	/************************************************************************************************/
	2019
	2020
1996	2021	/****************/
1997	2022	/* SPI Handling */
1998	2023	/****************/
r26888	r26889
2193	2218	case AVR8_REGIDX_DDRB:
2194	2219	case AVR8_REGIDX_DDRC:
2195	2220	case AVR8_REGIDX_DDRD:
2196		case AVR8_REGIDX_EEARL:
2197		case AVR8_REGIDX_EEARH:
2198	2221	case AVR8_REGIDX_SREG:
2199	2222	case AVR8_REGIDX_RAMPZ:
2200	2223	case AVR8_REGIDX_SPH:
r26888	r26889
2255	2278	if (data & AVR8_GTCCR_PSRASY_MASK)
2256	2279	{
2257	2280	data &= ~AVR8_GTCCR_PSRASY_MASK;
2258		m_timer2_prescale_count = 0;
	2281	m_timer_prescale_count[2] = 0;
2259	2282	}
2260	2283	break;
2261	2284
	2285	// EEPROM registers:
	2286	case AVR8_REGIDX_EEARL:
	2287	case AVR8_REGIDX_EEARH:
	2288	case AVR8_REGIDX_EEDR:
	2289	m_r[offset] = data;
	2290	break;
	2291
2262	2292	case AVR8_REGIDX_EECR:
2263		if (data & AVR8_EECR_EERE)
	2293	m_r[offset] = data;
	2294
	2295	if (data & AVR8_EECR_EERE_MASK)
2264	2296	{
2265	2297	UINT16 addr = (m_r[AVR8_REGIDX_EEARH] & AVR8_EEARH_MASK) << 8;
2266	2298	addr |= m_r[AVR8_REGIDX_EEARL];
2267	2299	m_r[AVR8_REGIDX_EEDR] = m_eeprom[addr];
	2300	printf("EEPROM read @ 0x%04x data = 0x%02x\n", addr, m_eeprom[addr]);
2268	2301	}
	2302	if ((data & AVR8_EECR_EEPE_MASK) && (data & AVR8_EECR_EEMPE_MASK))
	2303	{
	2304	UINT16 addr = (m_r[AVR8_REGIDX_EEARH] & AVR8_EEARH_MASK) << 8;
	2305	addr |= m_r[AVR8_REGIDX_EEARL];
	2306	m_eeprom[addr] = m_r[AVR8_REGIDX_EEDR];
	2307	printf("EEPROM write @ 0x%04x data = 0x%02x ('%c')\n", addr, m_eeprom[addr], m_eeprom[addr]);
	2308
	2309	m_r[offset] = data & ~AVR8_EECR_EEPE_MASK; //indicates that we've finished writing a value to the EEPROM.
	2310	//TODO: shouldn't this happen only after a certain dalay?
	2311	}
2269	2312	break;
2270	2313
2271	2314	case AVR8_REGIDX_GPIOR0:
r26888	r26889
2473	2516	break;
2474	2517
2475	2518	case AVR8_REGIDX_ICR1L:
2476		//TODO: ICR1L
	2519	AVR8_ICR1L = data;
2477	2520	break;
2478	2521
2479	2522	case AVR8_REGIDX_ICR1H:
2480		//TODO: ICR1H
	2523	AVR8_ICR1H = data;
2481	2524	break;
2482	2525
2483	2526	case AVR8_REGIDX_OCR1AL:
r26888	r26889
2510	2553	update_ocr1((AVR8_OCR1C & 0x00ff) | (data << 8), AVR8_REG_C);
2511	2554	break;
2512	2555
	2556	case AVR8_REGIDX_TCCR2A:
	2557	verboselog(m_pc, 0, "AVR8: TCCR2A = %02x\n", data );
	2558	changed_tccr2a(data);
	2559	break;
	2560
	2561	case AVR8_REGIDX_TCCR2B:
	2562	verboselog(m_pc, 0, "AVR8: TCCR2B = %02x\n", data );
	2563	changed_tccr2b(data);
	2564	break;
	2565
	2566	case AVR8_REGIDX_TCNT2:
	2567	AVR8_TCNT2 = data;
	2568	break;
	2569
	2570	case AVR8_REGIDX_OCR2A:
	2571	update_ocr2(data, AVR8_REG_A);
	2572	break;
	2573
	2574	case AVR8_REGIDX_OCR2B:
	2575	update_ocr2(data, AVR8_REG_B);
	2576	break;
	2577
2513	2578	case AVR8_REGIDX_TCCR3A:
2514	2579	verboselog(m_pc, 0, "AVR8: TCCR3A = %02x\n", data );
2515		//TODO:         changed_tccr3a(data);
	2580	changed_tccr3a(data);
2516	2581	break;
2517	2582
2518	2583	case AVR8_REGIDX_TCCR3B:
2519	2584	verboselog(m_pc, 0, "AVR8: TCCR3B = %02x\n", data );
2520		//TODO:         changed_tccr3b(data);
	2585	changed_tccr3b(data);
2521	2586	break;
2522	2587
2523	2588	case AVR8_REGIDX_TCCR3C:
2524	2589	verboselog(m_pc, 0, "AVR8: TCCR3C = %02x\n", data );
2525		//TODO:         changed_tccr3c(data);
	2590	changed_tccr3c(data);
2526	2591	break;
2527	2592
2528	2593	case AVR8_REGIDX_TCNT3L:
r26888	r26889
2534	2599	break;
2535	2600
2536	2601	case AVR8_REGIDX_ICR3L:
2537		//TODO: ICR3L
	2602	AVR8_ICR3L = data;
2538	2603	break;
2539	2604
2540	2605	case AVR8_REGIDX_ICR3H:
2541		//TODO: ICR3H
	2606	AVR8_ICR3H = data;
2542	2607	break;
2543	2608
2544	2609	case AVR8_REGIDX_OCR3AL:
2545		verboselog(m_pc, 0, "AVR8: OCR3AL = %02x\n", data );
2546		//TODO:         update_ocr3((AVR8_OCR3A & 0xff00) | data, AVR8_REG_A);
	2610	AVR8_OCR3AL = data;
2547	2611	break;
2548	2612
2549	2613	case AVR8_REGIDX_OCR3AH:
2550		verboselog(m_pc, 0, "AVR8: OCR3AH = %02x\n", data );
2551		//TODO:         update_ocr3((AVR8_OCR3A & 0x00ff) | (data << 8), AVR8_REG_A);
	2614	AVR8_OCR3AH = data;
2552	2615	break;
2553	2616
2554	2617	case AVR8_REGIDX_OCR3BL:
2555		verboselog(m_pc, 0, "AVR8: OCR3BL = %02x\n", data );
2556		//TODO:         update_ocr3((AVR8_OCR3B & 0xff00) | data, AVR8_REG_B);
	2618	AVR8_OCR3BL = data;
2557	2619	break;
2558	2620
2559	2621	case AVR8_REGIDX_OCR3BH:
2560		verboselog(m_pc, 0, "AVR8: OCR3BH = %02x\n", data );
2561		//TODO:         update_ocr3((AVR8_OCR3B & 0x00ff) | (data << 8), AVR8_REG_B);
	2622	AVR8_OCR3BH = data;
2562	2623	break;
2563	2624
2564	2625	case AVR8_REGIDX_OCR3CL:
2565		verboselog(m_pc, 0, "AVR8: OCR3CL = %02x\n", data );
2566		//TODO:         update_ocr3((AVR8_OCR3C & 0xff00) | data, AVR8_REG_C);
	2626	AVR8_OCR3CL = data;
2567	2627	break;
2568	2628
2569	2629	case AVR8_REGIDX_OCR3CH:
2570		verboselog(m_pc, 0, "AVR8: OCR3CH = %02x\n", data );
2571		//TODO:         update_ocr3((AVR8_OCR3C & 0x00ff) | (data << 8), AVR8_REG_C);
	2630	AVR8_OCR3CH = data;
2572	2631	break;
2573	2632
2574	2633	case AVR8_REGIDX_TCCR4A:
r26888	r26889
2583	2642
2584	2643	case AVR8_REGIDX_TCCR4C:
2585	2644	verboselog(m_pc, 0, "AVR8: TCCR4C = %02x\n", data );
2586		//TODO:         changed_tccr4c(data);
	2645	changed_tccr4c(data);
2587	2646	break;
2588	2647
2589	2648	case AVR8_REGIDX_TCNT4L:
r26888	r26889
2595	2654	break;
2596	2655
2597	2656	case AVR8_REGIDX_ICR4L:
2598		//TODO: ICR4L
	2657	AVR8_ICR4L = data;
2599	2658	break;
2600	2659
2601	2660	case AVR8_REGIDX_ICR4H:
2602		//TODO: ICR4H
	2661	AVR8_ICR4H = data;
2603	2662	break;
2604	2663
2605	2664	case AVR8_REGIDX_OCR4AL:
2606		verboselog(m_pc, 0, "AVR8: OCR4AL = %02x\n", data );
2607		//TODO:         update_ocr4((AVR8_OCR4A & 0xff00) | data, AVR8_REG_A);
	2665	AVR8_OCR4AL = data;
2608	2666	break;
2609	2667
2610	2668	case AVR8_REGIDX_OCR4AH:
2611		verboselog(m_pc, 0, "AVR8: OCR4AH = %02x\n", data );
2612		//TODO:         update_ocr4((AVR8_OCR4A & 0x00ff) | (data << 8), AVR8_REG_A);
	2669	AVR8_OCR4AH = data;
2613	2670	break;
2614	2671
2615	2672	case AVR8_REGIDX_OCR4BL:
2616		verboselog(m_pc, 0, "AVR8: OCR4BL = %02x\n", data );
2617		//TODO:         update_ocr4((AVR8_OCR4B & 0xff00) | data, AVR8_REG_B);
	2673	AVR8_OCR4BL = data;
2618	2674	break;
2619	2675
2620	2676	case AVR8_REGIDX_OCR4BH:
2621		verboselog(m_pc, 0, "AVR8: OCR4BH = %02x\n", data );
2622		//TODO:         update_ocr4((AVR8_OCR4B & 0x00ff) | (data << 8), AVR8_REG_B);
	2677	AVR8_OCR4BH = data;
2623	2678	break;
2624	2679
2625	2680	case AVR8_REGIDX_OCR4CL:
2626		verboselog(m_pc, 0, "AVR8: OCR4CL = %02x\n", data );
2627		//TODO:         update_ocr4((AVR8_OCR4C & 0xff00) | data, AVR8_REG_C);
	2681	AVR8_OCR4CL = data;
2628	2682	break;
2629	2683
2630	2684	case AVR8_REGIDX_OCR4CH:
2631		verboselog(m_pc, 0, "AVR8: OCR4CH = %02x\n", data );
2632		//TODO:         update_ocr4((AVR8_OCR4C & 0x00ff) | (data << 8), AVR8_REG_C);
	2685	AVR8_OCR4CH = data;
2633	2686	break;
2634	2687
2635		case AVR8_REGIDX_TCCR2A:
2636		verboselog(m_pc, 0, "AVR8: TCCR2A = %02x\n", data );
2637		changed_tccr2a(data);
	2688	case AVR8_REGIDX_TCCR5A:
	2689	verboselog(m_pc, 0, "AVR8: TCCR5A = %02x\n", data );
	2690	changed_tccr5a(data);
2638	2691	break;
2639	2692
2640		case AVR8_REGIDX_TCCR2B:
2641		verboselog(m_pc, 0, "AVR8: TCCR2B = %02x\n", data );
2642		changed_tccr2b(data);
	2693	case AVR8_REGIDX_TCCR5B:
	2694	verboselog(m_pc, 0, "AVR8: TCCR5B = %02x\n", data );
	2695	changed_tccr5b(data);
2643	2696	break;
2644	2697
2645		case AVR8_REGIDX_TCNT2:
2646		AVR8_TCNT2 = data;
2647		break;
2648
2649		case AVR8_REGIDX_OCR2A:
2650		update_ocr2(data, AVR8_REG_A);
2651		break;
2652
2653		case AVR8_REGIDX_OCR2B:
2654		update_ocr2(data, AVR8_REG_B);
2655		break;
2656
2657	2698	case AVR8_REGIDX_ASSR:
2658	2699	verboselog(m_pc, 0, "AVR8: ASSR = %02x\n", data );
2659	2700	//TODO: changed_assr(data);
r26888	r26889
2756	2797	case AVR8_REGIDX_R31:
2757	2798	return m_r[offset];
2758	2799
	2800	case AVR8_REGIDX_PINA:
	2801	// TODO: consider the DDRA
	2802	return m_io->read_byte(AVR8_REG_A);
	2803
	2804	case AVR8_REGIDX_PINB:
	2805	// TODO: consider the DDRB
	2806	return m_io->read_byte(AVR8_REG_B);
	2807
	2808	case AVR8_REGIDX_PINC:
	2809	// TODO: consider the DDRC
	2810	return m_io->read_byte(AVR8_REG_C);
	2811
	2812	case AVR8_REGIDX_PIND:
	2813	// TODO: consider the DDRD
	2814	return m_io->read_byte(AVR8_REG_D);
	2815
	2816	case AVR8_REGIDX_PINE:
	2817	// TODO: consider the DDRE
	2818	return m_io->read_byte(AVR8_REG_E);
	2819
	2820	case AVR8_REGIDX_PINF:
	2821	// TODO: consider the DDRF
	2822	return m_io->read_byte(AVR8_REG_F);
	2823
	2824	case AVR8_REGIDX_PING:
	2825	// TODO: consider the DDRG
	2826	return m_io->read_byte(AVR8_REG_G);
	2827
	2828	case AVR8_REGIDX_PINH:
	2829	// TODO: consider the DDRH
	2830	return m_io->read_byte(AVR8_REG_H);
	2831
	2832	case AVR8_REGIDX_PINJ:
	2833	// TODO: consider the DDRJ
	2834	return m_io->read_byte(AVR8_REG_J);
	2835
	2836	case AVR8_REGIDX_PINK:
	2837	// TODO: consider the DDRK
	2838	return m_io->read_byte(AVR8_REG_K);
	2839
	2840	case AVR8_REGIDX_PINL:
	2841	// TODO: consider the DDRL
	2842	return m_io->read_byte(AVR8_REG_L);
	2843
2759	2844	case AVR8_REGIDX_PORTA:
2760	2845	case AVR8_REGIDX_PORTB:
2761	2846	case AVR8_REGIDX_PORTC:
r26888	r26889
2767	2852	case AVR8_REGIDX_PORTJ:
2768	2853	case AVR8_REGIDX_PORTK:
2769	2854	case AVR8_REGIDX_PORTL:
	2855	return m_r[offset];
	2856
2770	2857	case AVR8_REGIDX_DDRA:
2771	2858	case AVR8_REGIDX_DDRB:
2772	2859	case AVR8_REGIDX_DDRC:
r26888	r26889
2778	2865	case AVR8_REGIDX_DDRJ:
2779	2866	case AVR8_REGIDX_DDRK:
2780	2867	case AVR8_REGIDX_DDRL:
2781		case AVR8_REGIDX_TWCR:/*TODO: needed for Replicator 1 <------- BLOQUEIA PROGRESSO DA EXECUÇÃO DO FIRMWARE no endereço 105EC*/
2782		case AVR8_REGIDX_UCSR0B:/*TODO: needed for Replicator 1 */
2783		case AVR8_REGIDX_SPDR:  /*TODO: needed for Replicator 1 */
2784		case AVR8_REGIDX_SPSR:  /*TODO: needed for Replicator 1 */
2785		case AVR8_REGIDX_ADCSRA:   /*TODO: needed for Replicator 1 */
2786		case AVR8_REGIDX_ADCSRB:   /*TODO: needed for Replicator 1 */
	2868	return m_r[offset];
	2869
	2870	// EEPROM registers:
	2871	case AVR8_REGIDX_EECR:
	2872	case AVR8_REGIDX_EEDR:
	2873	return m_r[offset];
	2874
	2875	/* Misc. registers.
	2876	TODO: implement all registers reads */
	2877
2787	2878	case AVR8_REGIDX_GPIOR0:
2788	2879	case AVR8_REGIDX_GPIOR1:
2789	2880	case AVR8_REGIDX_GPIOR2:
2790		case AVR8_REGIDX_EEDR:
	2881	//      case AVR8_REGIDX_UCSR0B:/*TODO: needed for Replicator 1 */
	2882	case AVR8_REGIDX_SPDR:  /*TODO: needed for Replicator 1 */
	2883	case AVR8_REGIDX_SPSR:  /*TODO: needed for Replicator 1 */
	2884	//    case AVR8_REGIDX_ADCSRA:   /*TODO: needed for Replicator 1 */
	2885	//    case AVR8_REGIDX_ADCSRB:   /*TODO: needed for Replicator 1 */
2791	2886	case AVR8_REGIDX_SPL:
2792	2887	case AVR8_REGIDX_SPH:
2793	2888	case AVR8_REGIDX_SREG:
2794		case AVR8_REGIDX_EECR: /*TODO: needed for Replicator 1 */
	2889	case AVR8_REGIDX_TIMSK0:
	2890	case AVR8_REGIDX_TIMSK1:
	2891	case AVR8_REGIDX_TIMSK2:
	2892	//    case AVR8_REGIDX_TIMSK3:  /*TODO: needed for Replicator 1 */
	2893	case AVR8_REGIDX_TIMSK4:
	2894	case AVR8_REGIDX_TIMSK5:
2795	2895	return m_r[offset];
2796	2896
	2897	/* Two-wire registers: */
	2898	case AVR8_REGIDX_TWCR:
	2899	/*TODO: needed for Replicator 1
	2900	BLOQUEIA PROGRESSO DA EXECUÇÃO DO FIRMWARE no endereço 105EC*/
	2901	return m_r[offset];
	2902
2797	2903	case AVR8_REGIDX_TWSR:
2798	2904	//quick hack: by returning a value != 0x08 we induce an error state that makes the object code jump out of the wait loop and continue execution failing the 2-wire write operation.
2799	2905	//TODO: implement-me!
2800	2906	return 0x00; /*TODO: needed for Replicator 1 */
2801	2907
2802		// TODO: consider the DDRx
2803		case AVR8_REGIDX_PINA:
2804		return m_io->read_byte(AVR8_REG_A);
2805	2908
2806		case AVR8_REGIDX_PINB:
2807		return m_io->read_byte(AVR8_REG_B);
2808
2809		case AVR8_REGIDX_PINC:
2810		return m_io->read_byte(AVR8_REG_C);
2811
2812		case AVR8_REGIDX_PIND:
2813		return m_io->read_byte(AVR8_REG_D);
2814
2815		case AVR8_REGIDX_PINE:
2816		return m_io->read_byte(AVR8_REG_E);
2817
2818		case AVR8_REGIDX_PINF:
2819		return m_io->read_byte(AVR8_REG_F);
2820
2821		case AVR8_REGIDX_PING:
2822		return m_io->read_byte(AVR8_REG_G);
2823
2824		case AVR8_REGIDX_PINH:
2825		return m_io->read_byte(AVR8_REG_H);
2826
2827		case AVR8_REGIDX_PINJ:
2828		return m_io->read_byte(AVR8_REG_J);
2829
2830		case AVR8_REGIDX_PINK:
2831		return m_io->read_byte(AVR8_REG_K);
2832
2833		case AVR8_REGIDX_PINL:
2834		return m_io->read_byte(AVR8_REG_L);
2835
2836	2909	case AVR8_REGIDX_TCNT1L:
2837	2910	case AVR8_REGIDX_TCNT1H:
2838	2911	case AVR8_REGIDX_TCNT2:
r26888	r26889
2841	2914
2842	2915	default:
2843	2916	printf("[%08X] AVR8: Unknown Register Read: 0x%03X\n", m_shifted_pc, offset);
	2917	//      debugger_break(machine());
2844	2918	return 0;
2845	2919	}
2846	2920	}

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