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r26879 Wednesday 1st January, 2014 at 21:58:00 UTC by Wilbert Pol
tms7000.c: Modernized cpu core.  [Wilbert Pol]

[src/emu/cpu/tms7000]

tms7000.c tms7000.h tms70op.c tms70tb.c

trunk/src/emu/cpu/tms7000/tms7000.h

r26878	r26879
1	1	/*****************************************************************************
2	2	*
3		*   cpustate->h (c header file)
	3	*   tms7000.h (c header file)
4	4	*   Portable TMS7000 emulator (Texas Instruments 7000)
5	5	*
6	6	*   Copyright tim lindner, all rights reserved.
r26878	r26879
45	45	TMS7000_PORTD
46	46	};
47	47
48		/* PUBLIC FUNCTIONS */
49		extern void tms7000_A6EC1( device_t *device ); /* External event counter */
50	48
51		DECLARE_LEGACY_CPU_DEVICE(TMS7000, tms7000);
52		DECLARE_LEGACY_CPU_DEVICE(TMS7000_EXL, tms7000_exl);
	49	class tms7000_device : public cpu_device
	50	{
	51	public:
	52	// construction/destruction
	53	tms7000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	54	tms7000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
53	55
54		extern CPU_DISASSEMBLE( tms7000 );
	56	DECLARE_WRITE8_MEMBER( tms70x0_pf_w );
	57	DECLARE_READ8_MEMBER( tms70x0_pf_r );
	58	DECLARE_WRITE8_MEMBER( tms7000_internal_w );
	59	DECLARE_READ8_MEMBER( tms7000_internal_r );
55	60
	61	void tms7000_A6EC1();
	62
	63	protected:
	64	// device-level overrides
	65	virtual void device_start();
	66	virtual void device_reset();
	67
	68	// device_execute_interface overrides
	69	virtual UINT32 execute_min_cycles() const { return 1; }
	70	virtual UINT32 execute_max_cycles() const { return 48; }
	71	virtual UINT32 execute_input_lines() const { return 3; }
	72	virtual void execute_run();
	73	virtual void execute_set_input(int inputnum, int state);
	74
	75	// device_memory_interface overrides
	76	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); }
	77
	78	// device_state_interface overrides
	79	void state_string_export(const device_state_entry &entry, astring &string);
	80
	81	// device_disasm_interface overrides
	82	virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
	83	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
	84	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	85
	86	private:
	87	address_space_config m_program_config;
	88	address_space_config m_io_config;
	89
	90	typedef void ( tms7000_device::*opcode_func ) ();
	91	static const opcode_func s_opfn[0x100];
	92	static const opcode_func s_opfn_exl[0x100];
	93	const opcode_func *m_opcode;
	94
	95	static UINT16 bcd_add( UINT16 a, UINT16 b );
	96	static UINT16 bcd_tencomp( UINT16 a );
	97	static UINT16 bcd_sub( UINT16 a, UINT16 b);
	98
	99	PAIR        m_pc;         /* Program counter */
	100	UINT8       m_sp;     /* Stack Pointer */
	101	UINT8       m_sr;     /* Status Register */
	102	UINT8       m_irq_state[3];   /* State of the three IRQs */
	103	UINT8       m_rf[0x80];   /* Register file (SJE) */
	104	UINT8       m_pf[0x100];  /* Perpherial file */
	105	address_space *m_program;
	106	direct_read_data *m_direct;
	107	address_space *m_io;
	108	int         m_icount;
	109	int         m_div_by_16_trigger;
	110	int         m_cycles_per_INT2;
	111	UINT8       m_t1_capture_latch; /* Timer 1 capture latch */
	112	INT8        m_t1_prescaler;   /* Timer 1 prescaler (5 bits) */
	113	INT16       m_t1_decrementer; /* Timer 1 decrementer (8 bits) */
	114	UINT8       m_idle_state; /* Set after the execution of an idle instruction */
	115
	116	inline UINT16 RM16( UINT32 mAddr );
	117	inline UINT16 RRF16( UINT32 mAddr );
	118	inline void WRF16( UINT32 mAddr, PAIR p );
	119	void tms7000_check_IRQ_lines();
	120	void tms7000_do_interrupt( UINT16 address, UINT8 line );
	121	void illegal();
	122	void adc_b2a();
	123	void adc_r2a();
	124	void adc_r2b();
	125	void adc_r2r();
	126	void adc_i2a();
	127	void adc_i2b();
	128	void adc_i2r();
	129	void add_b2a();
	130	void add_r2a();
	131	void add_r2b();
	132	void add_r2r();
	133	void add_i2a();
	134	void add_i2b();
	135	void add_i2r();
	136	void and_b2a();
	137	void and_r2a();
	138	void and_r2b();
	139	void and_r2r();
	140	void and_i2a();
	141	void and_i2b();
	142	void and_i2r();
	143	void andp_a2p();
	144	void andp_b2p();
	145	void movp_i2p();
	146	void andp_i2p();
	147	void br_dir();
	148	void br_ind();
	149	void br_inx();
	150	void btjo_b2a();
	151	void btjo_r2a();
	152	void btjo_r2b();
	153	void btjo_r2r();
	154	void btjo_i2a();
	155	void btjo_i2b();
	156	void btjo_i2r();
	157	void btjop_ap();
	158	void btjop_bp();
	159	void btjop_ip();
	160	void btjz_b2a();
	161	void btjz_r2a();
	162	void btjz_r2b();
	163	void btjz_r2r();
	164	void btjz_i2a();
	165	void btjz_i2b();
	166	void btjz_i2r();
	167	void btjzp_ap();
	168	void btjzp_bp();
	169	void btjzp_ip();
	170	void call_dir();
	171	void call_ind();
	172	void call_inx();
	173	void clr_a();
	174	void clr_b();
	175	void clr_r();
	176	void clrc();
	177	void cmp_ba();
	178	void cmp_ra();
	179	void cmp_rb();
	180	void cmp_rr();
	181	void cmp_ia();
	182	void cmp_ib();
	183	void cmp_ir();
	184	void cmpa_dir();
	185	void cmpa_ind();
	186	void cmpa_inx();
	187	void dac_b2a();
	188	void dac_r2a();
	189	void dac_r2b();
	190	void dac_r2r();
	191	void dac_i2a();
	192	void dac_i2b();
	193	void dac_i2r();
	194	void dec_a();
	195	void dec_b();
	196	void dec_r();
	197	void decd_a();
	198	void decd_b();
	199	void decd_r();
	200	void dint();
	201	void djnz_a();
	202	void djnz_b();
	203	void djnz_r();
	204	void dsb_b2a();
	205	void dsb_r2a();
	206	void dsb_r2b();
	207	void dsb_r2r();
	208	void dsb_i2a();
	209	void dsb_i2b();
	210	void dsb_i2r();
	211	void eint();
	212	void idle();
	213	void inc_a();
	214	void inc_b();
	215	void inc_r();
	216	void inv_a();
	217	void inv_b();
	218	void inv_r();
	219	void jc();
	220	void jeq();
	221	void jl();
	222	void jmp();
	223	void j_jn();
	224	void jne();
	225	void jp();
	226	void jpz();
	227	void lda_dir();
	228	void lda_ind();
	229	void lda_inx();
	230	void ldsp();
	231	void mov_a2b();
	232	void mov_b2a();
	233	void mov_a2r();
	234	void mov_b2r();
	235	void mov_r2a();
	236	void mov_r2b();
	237	void mov_r2r();
	238	void mov_i2a();
	239	void mov_i2b();
	240	void mov_i2r();
	241	void movd_imm();
	242	void movd_r();
	243	void movd_inx();
	244	void movp_a2p();
	245	void movp_b2p();
	246	void movp_r2p();
	247	void movp_p2a();
	248	void movp_p2b();
	249	void mpy_ba();
	250	void mpy_ra();
	251	void mpy_rb();
	252	void mpy_rr();
	253	void mpy_ia();
	254	void mpy_ib();
	255	void mpy_ir();
	256	void nop();
	257	void or_b2a();
	258	void or_r2a();
	259	void or_r2b();
	260	void or_r2r();
	261	void or_i2a();
	262	void or_i2b();
	263	void or_i2r();
	264	void orp_a2p();
	265	void orp_b2p();
	266	void orp_i2p();
	267	void pop_a();
	268	void pop_b();
	269	void pop_r();
	270	void pop_st();
	271	void push_a();
	272	void push_b();
	273	void push_r();
	274	void push_st();
	275	void reti();
	276	void rets();
	277	void rl_a();
	278	void rl_b();
	279	void rl_r();
	280	void rlc_a();
	281	void rlc_b();
	282	void rlc_r();
	283	void rr_a();
	284	void rr_b();
	285	void rr_r();
	286	void rrc_a();
	287	void rrc_b();
	288	void rrc_r();
	289	void sbb_ba();
	290	void sbb_ra();
	291	void sbb_rb();
	292	void sbb_rr();
	293	void sbb_ia();
	294	void sbb_ib();
	295	void sbb_ir();
	296	void setc();
	297	void sta_dir();
	298	void sta_ind();
	299	void sta_inx();
	300	void stsp();
	301	void sub_ba();
	302	void sub_ra();
	303	void sub_rb();
	304	void sub_rr();
	305	void sub_ia();
	306	void sub_ib();
	307	void sub_ir();
	308	void trap_0();
	309	void trap_1();
	310	void trap_2();
	311	void trap_3();
	312	void trap_4();
	313	void trap_5();
	314	void trap_6();
	315	void trap_7();
	316	void trap_8();
	317	void trap_9();
	318	void trap_10();
	319	void trap_11();
	320	void trap_12();
	321	void trap_13();
	322	void trap_14();
	323	void trap_15();
	324	void trap_16();
	325	void trap_17();
	326	void trap_18();
	327	void trap_19();
	328	void trap_20();
	329	void trap_21();
	330	void trap_22();
	331	void trap_23();
	332	void swap_a();
	333	void swap_b();
	334	void swap_r();
	335	void swap_r_exl();
	336	void tstb();
	337	void xchb_a();
	338	void xchb_b();
	339	void xchb_r();
	340	void xor_b2a();
	341	void xor_r2a();
	342	void xor_r2b();
	343	void xor_r2r();
	344	void xor_i2a();
	345	void xor_i2b();
	346	void xor_i2r();
	347	void xorp_a2p();
	348	void xorp_b2p();
	349	void xorp_i2p();
	350	void tms7000_service_timer1();
	351
	352	};
	353
	354
	355	class tms7000_exl_device : public tms7000_device
	356	{
	357	public:
	358	// construction/destruction
	359	tms7000_exl_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	360	};
	361
	362
	363	extern const device_type TMS7000;
	364	extern const device_type TMS7000_EXL;
	365
	366
56	367	#endif /* __TMS7000_H__ */

trunk/src/emu/cpu/tms7000/tms70tb.c

r26878	r26879
17	17	*
18	18	*****************************************************************************/
19	19
20		static void (*const opfn[0x100])(tms7000_state *cpustate) = {
	20	const tms7000_device::opcode_func tms7000_device::s_opfn[0x100] = {
21	21	/*          0xX0,   0xX1,     0xX2,    0xX3,    0xX4,    0xX5,    0xX6,    0xX7,
22	22	0xX8,   0xX9,     0xXA,    0xXB,    0xXC,    0xXD,    0xXE,    0xXF   */
23	23
24		/* 0x0X */  nop,     idle,    illegal, illegal, illegal, eint,    dint,    setc,
25		pop_st,  stsp,    rets,    reti,    illegal, ldsp,    push_st, illegal,
	24	/* 0x0X */  &tms7000_device::nop,     &tms7000_device::idle,    &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::eint,    &tms7000_device::dint,    &tms7000_device::setc,
	25	&tms7000_device::pop_st,  &tms7000_device::stsp,    &tms7000_device::rets,    &tms7000_device::reti,    &tms7000_device::illegal, &tms7000_device::ldsp,    &tms7000_device::push_st, &tms7000_device::illegal,
26	26
27		/* 0x1X */  illegal, illegal, mov_r2a, and_r2a, or_r2a,  xor_r2a, btjo_r2a,btjz_r2a,
28		add_r2a, adc_r2a, sub_ra,  sbb_ra,  mpy_ra,  cmp_ra,  dac_r2a, dsb_r2a,
	27	/* 0x1X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2a, &tms7000_device::and_r2a, &tms7000_device::or_r2a,  &tms7000_device::xor_r2a, &tms7000_device::btjo_r2a,&tms7000_device::btjz_r2a,
	28	&tms7000_device::add_r2a, &tms7000_device::adc_r2a, &tms7000_device::sub_ra,  &tms7000_device::sbb_ra,  &tms7000_device::mpy_ra,  &tms7000_device::cmp_ra,  &tms7000_device::dac_r2a, &tms7000_device::dsb_r2a,
29	29
30		/* 0x2X */  illegal, illegal, mov_i2a, and_i2a, or_i2a,  xor_i2a, btjo_i2a,btjz_i2a,
31		add_i2a, adc_i2a, sub_ia,  sbb_ia,  mpy_ia,  cmp_ia,  dac_i2a, dsb_i2a,
	30	/* 0x2X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2a, &tms7000_device::and_i2a, &tms7000_device::or_i2a,  &tms7000_device::xor_i2a, &tms7000_device::btjo_i2a,&tms7000_device::btjz_i2a,
	31	&tms7000_device::add_i2a, &tms7000_device::adc_i2a, &tms7000_device::sub_ia,  &tms7000_device::sbb_ia,  &tms7000_device::mpy_ia,  &tms7000_device::cmp_ia,  &tms7000_device::dac_i2a, &tms7000_device::dsb_i2a,
32	32
33		/* 0x3X */  illegal, illegal, mov_r2b, and_r2b, or_r2b,  xor_r2b, btjo_r2b,btjz_r2b,
34		add_r2b, adc_r2b, sub_rb,  sbb_rb,  mpy_rb,  cmp_rb,  dac_r2b, dsb_r2b,
	33	/* 0x3X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2b, &tms7000_device::and_r2b, &tms7000_device::or_r2b,  &tms7000_device::xor_r2b, &tms7000_device::btjo_r2b,&tms7000_device::btjz_r2b,
	34	&tms7000_device::add_r2b, &tms7000_device::adc_r2b, &tms7000_device::sub_rb,  &tms7000_device::sbb_rb,  &tms7000_device::mpy_rb,  &tms7000_device::cmp_rb,  &tms7000_device::dac_r2b, &tms7000_device::dsb_r2b,
35	35
36		/* 0x4X */  illegal, illegal, mov_r2r, and_r2r, or_r2r,  xor_r2r, btjo_r2r,btjz_r2r,
37		add_r2r, adc_r2r, sub_rr,  sbb_rr,  mpy_rr,  cmp_rr,  dac_r2r, dsb_r2r,
	36	/* 0x4X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2r, &tms7000_device::and_r2r, &tms7000_device::or_r2r,  &tms7000_device::xor_r2r, &tms7000_device::btjo_r2r,&tms7000_device::btjz_r2r,
	37	&tms7000_device::add_r2r, &tms7000_device::adc_r2r, &tms7000_device::sub_rr,  &tms7000_device::sbb_rr,  &tms7000_device::mpy_rr,  &tms7000_device::cmp_rr,  &tms7000_device::dac_r2r, &tms7000_device::dsb_r2r,
38	38
39		/* 0x5X */  illegal, illegal, mov_i2b, and_i2b, or_i2b,  xor_i2b, btjo_i2b,btjz_i2b,
40		add_i2b, adc_i2b, sub_ib,  sbb_ib,  mpy_ib,  cmp_ib,  dac_i2b, dsb_i2b,
	39	/* 0x5X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2b, &tms7000_device::and_i2b, &tms7000_device::or_i2b,  &tms7000_device::xor_i2b, &tms7000_device::btjo_i2b,&tms7000_device::btjz_i2b,
	40	&tms7000_device::add_i2b, &tms7000_device::adc_i2b, &tms7000_device::sub_ib,  &tms7000_device::sbb_ib,  &tms7000_device::mpy_ib,  &tms7000_device::cmp_ib,  &tms7000_device::dac_i2b, &tms7000_device::dsb_i2b,
41	41
42		/* 0x6X */  illegal, illegal, mov_b2a, and_b2a, or_b2a,  xor_b2a, btjo_b2a,btjz_b2a,
43		add_b2a, adc_b2a, sub_ba,  sbb_ba,  mpy_ba,  cmp_ba,  dac_b2a, dsb_b2a,
	42	/* 0x6X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_b2a, &tms7000_device::and_b2a, &tms7000_device::or_b2a,  &tms7000_device::xor_b2a, &tms7000_device::btjo_b2a,&tms7000_device::btjz_b2a,
	43	&tms7000_device::add_b2a, &tms7000_device::adc_b2a, &tms7000_device::sub_ba,  &tms7000_device::sbb_ba,  &tms7000_device::mpy_ba,  &tms7000_device::cmp_ba,  &tms7000_device::dac_b2a, &tms7000_device::dsb_b2a,
44	44
45		/* 0x7X */  illegal, illegal, mov_i2r, and_i2r, or_i2r,  xor_i2r, btjo_i2r,btjz_i2r,
46		add_i2r, adc_i2r, sub_ir,  sbb_ir,  mpy_ir,  cmp_ir,  dac_i2r, dsb_i2r,
	45	/* 0x7X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2r, &tms7000_device::and_i2r, &tms7000_device::or_i2r,  &tms7000_device::xor_i2r, &tms7000_device::btjo_i2r,&tms7000_device::btjz_i2r,
	46	&tms7000_device::add_i2r, &tms7000_device::adc_i2r, &tms7000_device::sub_ir,  &tms7000_device::sbb_ir,  &tms7000_device::mpy_ir,  &tms7000_device::cmp_ir,  &tms7000_device::dac_i2r, &tms7000_device::dsb_i2r,
47	47
48		/* 0x8X */  movp_p2a,illegal, movp_a2p,andp_a2p,orp_a2p, xorp_a2p,btjop_ap,btjzp_ap,
49		movd_imm,illegal, lda_dir, sta_dir, br_dir,  cmpa_dir,call_dir,illegal,
	48	/* 0x8X */  &tms7000_device::movp_p2a,&tms7000_device::illegal, &tms7000_device::movp_a2p,&tms7000_device::andp_a2p,&tms7000_device::orp_a2p, &tms7000_device::xorp_a2p,&tms7000_device::btjop_ap,&tms7000_device::btjzp_ap,
	49	&tms7000_device::movd_imm,&tms7000_device::illegal, &tms7000_device::lda_dir, &tms7000_device::sta_dir, &tms7000_device::br_dir,  &tms7000_device::cmpa_dir,&tms7000_device::call_dir,&tms7000_device::illegal,
50	50
51		/* 0x9X */  illegal, movp_p2b,movp_b2p,andp_b2p,orp_b2p, xorp_b2p,btjop_bp,btjzp_bp,
52		movd_r,  illegal, lda_ind, sta_ind, br_ind,  cmpa_ind,call_ind,illegal,
	51	/* 0x9X */  &tms7000_device::illegal, &tms7000_device::movp_p2b,&tms7000_device::movp_b2p,&tms7000_device::andp_b2p,&tms7000_device::orp_b2p, &tms7000_device::xorp_b2p,&tms7000_device::btjop_bp,&tms7000_device::btjzp_bp,
	52	&tms7000_device::movd_r,  &tms7000_device::illegal, &tms7000_device::lda_ind, &tms7000_device::sta_ind, &tms7000_device::br_ind,  &tms7000_device::cmpa_ind,&tms7000_device::call_ind,&tms7000_device::illegal,
53	53
54		/* 0xAX */  illegal, illegal, movp_i2p,andp_i2p,orp_i2p, xorp_i2p,btjop_ip,btjzp_ip,
55		movd_inx,illegal, lda_inx, sta_inx, br_inx,  cmpa_inx,call_inx,illegal,
	54	/* 0xAX */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::movp_i2p,&tms7000_device::andp_i2p,&tms7000_device::orp_i2p, &tms7000_device::xorp_i2p,&tms7000_device::btjop_ip,&tms7000_device::btjzp_ip,
	55	&tms7000_device::movd_inx,&tms7000_device::illegal, &tms7000_device::lda_inx, &tms7000_device::sta_inx, &tms7000_device::br_inx,  &tms7000_device::cmpa_inx,&tms7000_device::call_inx,&tms7000_device::illegal,
56	56
57		/* 0xBX */  clrc,    illegal, dec_a,   inc_a,   inv_a,   clr_a,   xchb_a,  swap_a,
58		push_a,  pop_a,   djnz_a,  decd_a,  rr_a,    rrc_a,   rl_a,    rlc_a,
	57	/* 0xBX */  &tms7000_device::clrc,    &tms7000_device::illegal, &tms7000_device::dec_a,   &tms7000_device::inc_a,   &tms7000_device::inv_a,   &tms7000_device::clr_a,   &tms7000_device::xchb_a,  &tms7000_device::swap_a,
	58	&tms7000_device::push_a,  &tms7000_device::pop_a,   &tms7000_device::djnz_a,  &tms7000_device::decd_a,  &tms7000_device::rr_a,    &tms7000_device::rrc_a,   &tms7000_device::rl_a,    &tms7000_device::rlc_a,
59	59
60		/* 0xCX */  mov_a2b, tstb,    dec_b,   inc_b,   inv_b,   clr_b,   xchb_b,  swap_b,
61		push_b,  pop_b,   djnz_b,  decd_b,  rr_b,    rrc_b,   rl_b,    rlc_b,
	60	/* 0xCX */  &tms7000_device::mov_a2b, &tms7000_device::tstb,    &tms7000_device::dec_b,   &tms7000_device::inc_b,   &tms7000_device::inv_b,   &tms7000_device::clr_b,   &tms7000_device::xchb_b,  &tms7000_device::swap_b,
	61	&tms7000_device::push_b,  &tms7000_device::pop_b,   &tms7000_device::djnz_b,  &tms7000_device::decd_b,  &tms7000_device::rr_b,    &tms7000_device::rrc_b,   &tms7000_device::rl_b,    &tms7000_device::rlc_b,
62	62
63		/* 0xDX */  mov_a2r, mov_b2r, dec_r,   inc_r,   inv_r,   clr_r,   xchb_r,  swap_r,
64		push_r,  pop_r,   djnz_r,  decd_r,  rr_r,    rrc_r,   rl_r,    rlc_r,
	63	/* 0xDX */  &tms7000_device::mov_a2r, &tms7000_device::mov_b2r, &tms7000_device::dec_r,   &tms7000_device::inc_r,   &tms7000_device::inv_r,   &tms7000_device::clr_r,   &tms7000_device::xchb_r,  &tms7000_device::swap_r,
	64	&tms7000_device::push_r,  &tms7000_device::pop_r,   &tms7000_device::djnz_r,  &tms7000_device::decd_r,  &tms7000_device::rr_r,    &tms7000_device::rrc_r,   &tms7000_device::rl_r,    &tms7000_device::rlc_r,
65	65
66		/* 0xEX */  jmp,     j_jn,    jeq,     jc,      jp,      jpz,     jne,     jl,
67		trap_23, trap_22, trap_21, trap_20, trap_19, trap_18, trap_17, trap_16,
	66	/* 0xEX */  &tms7000_device::jmp,     &tms7000_device::j_jn,    &tms7000_device::jeq,     &tms7000_device::jc,      &tms7000_device::jp,      &tms7000_device::jpz,     &tms7000_device::jne,     &tms7000_device::jl,
	67	&tms7000_device::trap_23, &tms7000_device::trap_22, &tms7000_device::trap_21, &tms7000_device::trap_20, &tms7000_device::trap_19, &tms7000_device::trap_18, &tms7000_device::trap_17, &tms7000_device::trap_16,
68	68
69		/* 0xFX */  trap_15, trap_14, trap_13, trap_12, trap_11, trap_10, trap_9,  trap_8,
70		trap_7,  trap_6,  trap_5,  trap_4,  trap_3,  trap_2,  trap_1,  trap_0
	69	/* 0xFX */  &tms7000_device::trap_15, &tms7000_device::trap_14, &tms7000_device::trap_13, &tms7000_device::trap_12, &tms7000_device::trap_11, &tms7000_device::trap_10, &tms7000_device::trap_9,  &tms7000_device::trap_8,
	70	&tms7000_device::trap_7,  &tms7000_device::trap_6,  &tms7000_device::trap_5,  &tms7000_device::trap_4,  &tms7000_device::trap_3,  &tms7000_device::trap_2,  &tms7000_device::trap_1,  &tms7000_device::trap_0
71	71	};
72	72
73		static void (*const opfn_exl[0x100])(tms7000_state *cpustate) = {
	73	const tms7000_device::opcode_func tms7000_device::s_opfn_exl[0x100] = {
74	74	/*          0xX0,   0xX1,     0xX2,    0xX3,    0xX4,    0xX5,    0xX6,    0xX7,
75	75	0xX8,   0xX9,     0xXA,    0xXB,    0xXC,    0xXD,    0xXE,    0xXF   */
76	76
77		/* 0x0X */  nop,     idle,    illegal, illegal, illegal, eint,    dint,    setc,
78		pop_st,  stsp,    rets,    reti,    illegal, ldsp,    push_st, illegal,
	77	/* 0x0X */  &tms7000_device::nop,     &tms7000_device::idle,    &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::eint,    &tms7000_device::dint,    &tms7000_device::setc,
	78	&tms7000_device::pop_st,  &tms7000_device::stsp,    &tms7000_device::rets,    &tms7000_device::reti,    &tms7000_device::illegal, &tms7000_device::ldsp,    &tms7000_device::push_st, &tms7000_device::illegal,
79	79
80		/* 0x1X */  illegal, illegal, mov_r2a, and_r2a, or_r2a,  xor_r2a, btjo_r2a,btjz_r2a,
81		add_r2a, adc_r2a, sub_ra,  sbb_ra,  mpy_ra,  cmp_ra,  dac_r2a, dsb_r2a,
	80	/* 0x1X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2a, &tms7000_device::and_r2a, &tms7000_device::or_r2a,  &tms7000_device::xor_r2a, &tms7000_device::btjo_r2a,&tms7000_device::btjz_r2a,
	81	&tms7000_device::add_r2a, &tms7000_device::adc_r2a, &tms7000_device::sub_ra,  &tms7000_device::sbb_ra,  &tms7000_device::mpy_ra,  &tms7000_device::cmp_ra,  &tms7000_device::dac_r2a, &tms7000_device::dsb_r2a,
82	82
83		/* 0x2X */  illegal, illegal, mov_i2a, and_i2a, or_i2a,  xor_i2a, btjo_i2a,btjz_i2a,
84		add_i2a, adc_i2a, sub_ia,  sbb_ia,  mpy_ia,  cmp_ia,  dac_i2a, dsb_i2a,
	83	/* 0x2X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2a, &tms7000_device::and_i2a, &tms7000_device::or_i2a,  &tms7000_device::xor_i2a, &tms7000_device::btjo_i2a,&tms7000_device::btjz_i2a,
	84	&tms7000_device::add_i2a, &tms7000_device::adc_i2a, &tms7000_device::sub_ia,  &tms7000_device::sbb_ia,  &tms7000_device::mpy_ia,  &tms7000_device::cmp_ia,  &tms7000_device::dac_i2a, &tms7000_device::dsb_i2a,
85	85
86		/* 0x3X */  illegal, illegal, mov_r2b, and_r2b, or_r2b,  xor_r2b, btjo_r2b,btjz_r2b,
87		add_r2b, adc_r2b, sub_rb,  sbb_rb,  mpy_rb,  cmp_rb,  dac_r2b, dsb_r2b,
	86	/* 0x3X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2b, &tms7000_device::and_r2b, &tms7000_device::or_r2b,  &tms7000_device::xor_r2b, &tms7000_device::btjo_r2b,&tms7000_device::btjz_r2b,
	87	&tms7000_device::add_r2b, &tms7000_device::adc_r2b, &tms7000_device::sub_rb,  &tms7000_device::sbb_rb,  &tms7000_device::mpy_rb,  &tms7000_device::cmp_rb,  &tms7000_device::dac_r2b, &tms7000_device::dsb_r2b,
88	88
89		/* 0x4X */  illegal, illegal, mov_r2r, and_r2r, or_r2r,  xor_r2r, btjo_r2r,btjz_r2r,
90		add_r2r, adc_r2r, sub_rr,  sbb_rr,  mpy_rr,  cmp_rr,  dac_r2r, dsb_r2r,
	89	/* 0x4X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2r, &tms7000_device::and_r2r, &tms7000_device::or_r2r,  &tms7000_device::xor_r2r, &tms7000_device::btjo_r2r,&tms7000_device::btjz_r2r,
	90	&tms7000_device::add_r2r, &tms7000_device::adc_r2r, &tms7000_device::sub_rr,  &tms7000_device::sbb_rr,  &tms7000_device::mpy_rr,  &tms7000_device::cmp_rr,  &tms7000_device::dac_r2r, &tms7000_device::dsb_r2r,
91	91
92		/* 0x5X */  illegal, illegal, mov_i2b, and_i2b, or_i2b,  xor_i2b, btjo_i2b,btjz_i2b,
93		add_i2b, adc_i2b, sub_ib,  sbb_ib,  mpy_ib,  cmp_ib,  dac_i2b, dsb_i2b,
	92	/* 0x5X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2b, &tms7000_device::and_i2b, &tms7000_device::or_i2b,  &tms7000_device::xor_i2b, &tms7000_device::btjo_i2b,&tms7000_device::btjz_i2b,
	93	&tms7000_device::add_i2b, &tms7000_device::adc_i2b, &tms7000_device::sub_ib,  &tms7000_device::sbb_ib,  &tms7000_device::mpy_ib,  &tms7000_device::cmp_ib,  &tms7000_device::dac_i2b, &tms7000_device::dsb_i2b,
94	94
95		/* 0x6X */  illegal, illegal, mov_b2a, and_b2a, or_b2a,  xor_b2a, btjo_b2a,btjz_b2a,
96		add_b2a, adc_b2a, sub_ba,  sbb_ba,  mpy_ba,  cmp_ba,  dac_b2a, dsb_b2a,
	95	/* 0x6X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_b2a, &tms7000_device::and_b2a, &tms7000_device::or_b2a,  &tms7000_device::xor_b2a, &tms7000_device::btjo_b2a,&tms7000_device::btjz_b2a,
	96	&tms7000_device::add_b2a, &tms7000_device::adc_b2a, &tms7000_device::sub_ba,  &tms7000_device::sbb_ba,  &tms7000_device::mpy_ba,  &tms7000_device::cmp_ba,  &tms7000_device::dac_b2a, &tms7000_device::dsb_b2a,
97	97
98		/* 0x7X */  illegal, illegal, mov_i2r, and_i2r, or_i2r,  xor_i2r, btjo_i2r,btjz_i2r,
99		add_i2r, adc_i2r, sub_ir,  sbb_ir,  mpy_ir,  cmp_ir,  dac_i2r, dsb_i2r,
	98	/* 0x7X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2r, &tms7000_device::and_i2r, &tms7000_device::or_i2r,  &tms7000_device::xor_i2r, &tms7000_device::btjo_i2r,&tms7000_device::btjz_i2r,
	99	&tms7000_device::add_i2r, &tms7000_device::adc_i2r, &tms7000_device::sub_ir,  &tms7000_device::sbb_ir,  &tms7000_device::mpy_ir,  &tms7000_device::cmp_ir,  &tms7000_device::dac_i2r, &tms7000_device::dsb_i2r,
100	100
101		/* 0x8X */  movp_p2a,illegal, movp_a2p,andp_a2p,orp_a2p, xorp_a2p,btjop_ap,btjzp_ap,
102		movd_imm,illegal, lda_dir, sta_dir, br_dir,  cmpa_dir,call_dir,illegal,
	101	/* 0x8X */  &tms7000_device::movp_p2a,&tms7000_device::illegal, &tms7000_device::movp_a2p,&tms7000_device::andp_a2p,&tms7000_device::orp_a2p, &tms7000_device::xorp_a2p,&tms7000_device::btjop_ap,&tms7000_device::btjzp_ap,
	102	&tms7000_device::movd_imm,&tms7000_device::illegal, &tms7000_device::lda_dir, &tms7000_device::sta_dir, &tms7000_device::br_dir,  &tms7000_device::cmpa_dir,&tms7000_device::call_dir,&tms7000_device::illegal,
103	103
104		/* 0x9X */  illegal, movp_p2b,movp_b2p,andp_b2p,orp_b2p, xorp_b2p,btjop_bp,btjzp_bp,
105		movd_r,  illegal, lda_ind, sta_ind, br_ind,  cmpa_ind,call_ind,illegal,
	104	/* 0x9X */  &tms7000_device::illegal, &tms7000_device::movp_p2b,&tms7000_device::movp_b2p,&tms7000_device::andp_b2p,&tms7000_device::orp_b2p, &tms7000_device::xorp_b2p,&tms7000_device::btjop_bp,&tms7000_device::btjzp_bp,
	105	&tms7000_device::movd_r,  &tms7000_device::illegal, &tms7000_device::lda_ind, &tms7000_device::sta_ind, &tms7000_device::br_ind,  &tms7000_device::cmpa_ind,&tms7000_device::call_ind,&tms7000_device::illegal,
106	106
107		/* 0xAX */  illegal, illegal, movp_i2p,andp_i2p,orp_i2p, xorp_i2p,btjop_ip,btjzp_ip,
108		movd_inx,illegal, lda_inx, sta_inx, br_inx,  cmpa_inx,call_inx,illegal,
	107	/* 0xAX */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::movp_i2p,&tms7000_device::andp_i2p,&tms7000_device::orp_i2p, &tms7000_device::xorp_i2p,&tms7000_device::btjop_ip,&tms7000_device::btjzp_ip,
	108	&tms7000_device::movd_inx,&tms7000_device::illegal, &tms7000_device::lda_inx, &tms7000_device::sta_inx, &tms7000_device::br_inx,  &tms7000_device::cmpa_inx,&tms7000_device::call_inx,&tms7000_device::illegal,
109	109
110		/* 0xBX */  clrc,    illegal, dec_a,   inc_a,   inv_a,   clr_a,   xchb_a,  swap_a,
111		push_a,  pop_a,   djnz_a,  decd_a,  rr_a,    rrc_a,   rl_a,    rlc_a,
	110	/* 0xBX */  &tms7000_device::clrc,    &tms7000_device::illegal, &tms7000_device::dec_a,   &tms7000_device::inc_a,   &tms7000_device::inv_a,   &tms7000_device::clr_a,   &tms7000_device::xchb_a,  &tms7000_device::swap_a,
	111	&tms7000_device::push_a,  &tms7000_device::pop_a,   &tms7000_device::djnz_a,  &tms7000_device::decd_a,  &tms7000_device::rr_a,    &tms7000_device::rrc_a,   &tms7000_device::rl_a,    &tms7000_device::rlc_a,
112	112
113		/* 0xCX */  mov_a2b, tstb,    dec_b,   inc_b,   inv_b,   clr_b,   xchb_b,  swap_b,
114		push_b,  pop_b,   djnz_b,  decd_b,  rr_b,    rrc_b,   rl_b,    rlc_b,
	113	/* 0xCX */  &tms7000_device::mov_a2b, &tms7000_device::tstb,    &tms7000_device::dec_b,   &tms7000_device::inc_b,   &tms7000_device::inv_b,   &tms7000_device::clr_b,   &tms7000_device::xchb_b,  &tms7000_device::swap_b,
	114	&tms7000_device::push_b,  &tms7000_device::pop_b,   &tms7000_device::djnz_b,  &tms7000_device::decd_b,  &tms7000_device::rr_b,    &tms7000_device::rrc_b,   &tms7000_device::rl_b,    &tms7000_device::rlc_b,
115	115
116		/* 0xDX */  mov_a2r, mov_b2r, dec_r,   inc_r,   inv_r,   clr_r,   xchb_r,  swap_r_exl,
117		push_r,  pop_r,   djnz_r,  decd_r,  rr_r,    rrc_r,   rl_r,    rlc_r,
	116	/* 0xDX */  &tms7000_device::mov_a2r, &tms7000_device::mov_b2r, &tms7000_device::dec_r,   &tms7000_device::inc_r,   &tms7000_device::inv_r,   &tms7000_device::clr_r,   &tms7000_device::xchb_r,  &tms7000_device::swap_r_exl,
	117	&tms7000_device::push_r,  &tms7000_device::pop_r,   &tms7000_device::djnz_r,  &tms7000_device::decd_r,  &tms7000_device::rr_r,    &tms7000_device::rrc_r,   &tms7000_device::rl_r,    &tms7000_device::rlc_r,
118	118
119		/* 0xEX */  jmp,     j_jn,    jeq,     jc,      jp,      jpz,     jne,     jl,
120		trap_23, trap_22, trap_21, trap_20, trap_19, trap_18, trap_17, trap_16,
	119	/* 0xEX */  &tms7000_device::jmp,     &tms7000_device::j_jn,    &tms7000_device::jeq,     &tms7000_device::jc,      &tms7000_device::jp,      &tms7000_device::jpz,     &tms7000_device::jne,     &tms7000_device::jl,
	120	&tms7000_device::trap_23, &tms7000_device::trap_22, &tms7000_device::trap_21, &tms7000_device::trap_20, &tms7000_device::trap_19, &tms7000_device::trap_18, &tms7000_device::trap_17, &tms7000_device::trap_16,
121	121
122		/* 0xFX */  trap_15, trap_14, trap_13, trap_12, trap_11, trap_10, trap_9,  trap_8,
123		trap_7,  trap_6,  trap_5,  trap_4,  trap_3,  trap_2,  trap_1,  trap_0
	122	/* 0xFX */  &tms7000_device::trap_15, &tms7000_device::trap_14, &tms7000_device::trap_13, &tms7000_device::trap_12, &tms7000_device::trap_11, &tms7000_device::trap_10, &tms7000_device::trap_9,  &tms7000_device::trap_8,
	123	&tms7000_device::trap_7,  &tms7000_device::trap_6,  &tms7000_device::trap_5,  &tms7000_device::trap_4,  &tms7000_device::trap_3,  &tms7000_device::trap_2,  &tms7000_device::trap_1,  &tms7000_device::trap_0
124	124	};

trunk/src/emu/cpu/tms7000/tms70op.c

r26878	r26879
25	25
26	26	#include "emu.h"
27	27
28		static void illegal(tms7000_state *cpustate)
	28	void tms7000_device::illegal()
29	29	{
30	30	/* This is a guess */
31		cpustate->icount -= 4;
	31	m_icount -= 4;
32	32	}
33	33
34		static void adc_b2a(tms7000_state *cpustate)
	34	void tms7000_device::adc_b2a()
35	35	{
36	36	UINT16  t;
37	37
r26878	r26879
43	43	SET_N8(t);
44	44	SET_Z8(t);
45	45
46		cpustate->icount -= 5;
	46	m_icount -= 5;
47	47	}
48	48
49		static void adc_r2a(tms7000_state *cpustate)
	49	void tms7000_device::adc_r2a()
50	50	{
51	51	UINT16  t;
52	52	UINT8   v;
r26878	r26879
61	61	SET_N8(t);
62	62	SET_Z8(t);
63	63
64		cpustate->icount -= 8;
	64	m_icount -= 8;
65	65	}
66	66
67		static void adc_r2b(tms7000_state *cpustate)
	67	void tms7000_device::adc_r2b()
68	68	{
69	69	UINT16  t;
70	70	UINT8   v;
r26878	r26879
79	79	SET_N8(t);
80	80	SET_Z8(t);
81	81
82		cpustate->icount -= 8;
	82	m_icount -= 8;
83	83	}
84	84
85		static void adc_r2r(tms7000_state *cpustate)
	85	void tms7000_device::adc_r2r()
86	86	{
87	87	UINT16  t;
88	88	UINT8   i,j;
r26878	r26879
98	98	SET_N8(t);
99	99	SET_Z8(t);
100	100
101		cpustate->icount -= 10;
	101	m_icount -= 10;
102	102	}
103	103
104		static void adc_i2a(tms7000_state *cpustate)
	104	void tms7000_device::adc_i2a()
105	105	{
106	106	UINT16  t;
107	107	UINT8   v;
r26878	r26879
116	116	SET_N8(t);
117	117	SET_Z8(t);
118	118
119		cpustate->icount -= 7;
	119	m_icount -= 7;
120	120	}
121	121
122		static void adc_i2b(tms7000_state *cpustate)
	122	void tms7000_device::adc_i2b()
123	123	{
124	124	UINT16  t;
125	125	UINT8   v;
r26878	r26879
134	134	SET_N8(t);
135	135	SET_Z8(t);
136	136
137		cpustate->icount -= 7;
	137	m_icount -= 7;
138	138	}
139	139
140		static void adc_i2r(tms7000_state *cpustate)
	140	void tms7000_device::adc_i2r()
141	141	{
142	142	UINT16  t;
143	143	UINT8   i,j;
r26878	r26879
153	153	SET_N8(t);
154	154	SET_Z8(t);
155	155
156		cpustate->icount -= 9;
	156	m_icount -= 9;
157	157	}
158	158
159		static void add_b2a(tms7000_state *cpustate)
	159	void tms7000_device::add_b2a()
160	160	{
161	161	UINT16  t;
162	162
r26878	r26879
168	168	SET_N8(t);
169	169	SET_Z8(t);
170	170
171		cpustate->icount -= 5;
	171	m_icount -= 5;
172	172	}
173	173
174		static void add_r2a(tms7000_state *cpustate)
	174	void tms7000_device::add_r2a()
175	175	{
176	176	UINT16  t;
177	177	UINT8   v;
r26878	r26879
186	186	SET_N8(t);
187	187	SET_Z8(t);
188	188
189		cpustate->icount -= 8;
	189	m_icount -= 8;
190	190	}
191	191
192		static void add_r2b(tms7000_state *cpustate)
	192	void tms7000_device::add_r2b()
193	193	{
194	194	UINT16  t;
195	195	UINT8   v;
r26878	r26879
204	204	SET_N8(t);
205	205	SET_Z8(t);
206	206
207		cpustate->icount -= 8;
	207	m_icount -= 8;
208	208	}
209	209
210		static void add_r2r(tms7000_state *cpustate)
	210	void tms7000_device::add_r2r()
211	211	{
212	212	UINT16  t;
213	213	UINT8   i,j;
r26878	r26879
223	223	SET_N8(t);
224	224	SET_Z8(t);
225	225
226		cpustate->icount -= 10;
	226	m_icount -= 10;
227	227	}
228	228
229		static void add_i2a(tms7000_state *cpustate)
	229	void tms7000_device::add_i2a()
230	230	{
231	231	UINT16  t;
232	232	UINT8   v;
r26878	r26879
241	241	SET_N8(t);
242	242	SET_Z8(t);
243	243
244		cpustate->icount -= 7;
	244	m_icount -= 7;
245	245	}
246	246
247		static void add_i2b(tms7000_state *cpustate)
	247	void tms7000_device::add_i2b()
248	248	{
249	249	UINT16  t;
250	250	UINT8   v;
r26878	r26879
259	259	SET_N8(t);
260	260	SET_Z8(t);
261	261
262		cpustate->icount -= 7;
	262	m_icount -= 7;
263	263	}
264	264
265		static void add_i2r(tms7000_state *cpustate)
	265	void tms7000_device::add_i2r()
266	266	{
267	267	UINT16  t;
268	268	UINT8   i,j;
r26878	r26879
278	278	SET_N8(t);
279	279	SET_Z8(t);
280	280
281		cpustate->icount -= 9;
	281	m_icount -= 9;
282	282	}
283	283
284		static void and_b2a(tms7000_state *cpustate)
	284	void tms7000_device::and_b2a()
285	285	{
286	286	UINT8   t;
287	287
r26878	r26879
292	292	SET_N8(t);
293	293	SET_Z8(t);
294	294
295		cpustate->icount -= 5;
	295	m_icount -= 5;
296	296	}
297	297
298		static void and_r2a(tms7000_state *cpustate)
	298	void tms7000_device::and_r2a()
299	299	{
300	300	UINT8   t;
301	301	UINT8   v;
r26878	r26879
309	309	SET_N8(t);
310	310	SET_Z8(t);
311	311
312		cpustate->icount -= 8;
	312	m_icount -= 8;
313	313	}
314	314
315		static void and_r2b(tms7000_state *cpustate)
	315	void tms7000_device::and_r2b()
316	316	{
317	317	UINT8   t;
318	318	UINT8   v;
r26878	r26879
326	326	SET_N8(t);
327	327	SET_Z8(t);
328	328
329		cpustate->icount -= 8;
	329	m_icount -= 8;
330	330	}
331	331
332		static void and_r2r(tms7000_state *cpustate)
	332	void tms7000_device::and_r2r()
333	333	{
334	334	UINT8   t;
335	335	UINT8   i,j;
r26878	r26879
344	344	SET_N8(t);
345	345	SET_Z8(t);
346	346
347		cpustate->icount -= 10;
	347	m_icount -= 10;
348	348	}
349	349
350		static void and_i2a(tms7000_state *cpustate)
	350	void tms7000_device::and_i2a()
351	351	{
352	352	UINT8   t;
353	353	UINT8   v;
r26878	r26879
361	361	SET_N8(t);
362	362	SET_Z8(t);
363	363
364		cpustate->icount -= 7;
	364	m_icount -= 7;
365	365	}
366	366
367		static void and_i2b(tms7000_state *cpustate)
	367	void tms7000_device::and_i2b()
368	368	{
369	369	UINT8   t;
370	370	UINT8   v;
r26878	r26879
378	378	SET_N8(t);
379	379	SET_Z8(t);
380	380
381		cpustate->icount -= 7;
	381	m_icount -= 7;
382	382	}
383	383
384		static void and_i2r(tms7000_state *cpustate)
	384	void tms7000_device::and_i2r()
385	385	{
386	386	UINT8   t;
387	387	UINT8   i,j;
r26878	r26879
396	396	SET_N8(t);
397	397	SET_Z8(t);
398	398
399		cpustate->icount -= 9;
	399	m_icount -= 9;
400	400	}
401	401
402		static void andp_a2p(tms7000_state *cpustate)
	402	void tms7000_device::andp_a2p()
403	403	{
404	404	UINT8   t;
405	405	UINT8   v;
r26878	r26879
412	412	SET_N8(t);
413	413	SET_Z8(t);
414	414
415		cpustate->icount -= 10;
	415	m_icount -= 10;
416	416	}
417	417
418		static void andp_b2p(tms7000_state *cpustate)
	418	void tms7000_device::andp_b2p()
419	419	{
420	420	UINT8   t;
421	421	UINT8   v;
r26878	r26879
428	428	SET_N8(t);
429	429	SET_Z8(t);
430	430
431		cpustate->icount -= 9;
	431	m_icount -= 9;
432	432	}
433	433
434	434
435		static void movp_i2p(tms7000_state *cpustate)
	435	void tms7000_device::movp_i2p()
436	436	{
437	437	UINT8   i,v;
438	438
r26878	r26879
444	444	SET_N8(i);
445	445	SET_Z8(i);
446	446
447		cpustate->icount -= 11;
	447	m_icount -= 11;
448	448	}
449	449
450		static void andp_i2p(tms7000_state *cpustate)
	450	void tms7000_device::andp_i2p()
451	451	{
452	452	UINT8   t;
453	453	UINT8   i,v;
r26878	r26879
461	461	SET_N8(t);
462	462	SET_Z8(t);
463	463
464		cpustate->icount -= 11;
	464	m_icount -= 11;
465	465	}
466	466
467		static void br_dir(tms7000_state *cpustate)
	467	void tms7000_device::br_dir()
468	468	{
469	469	PAIR p;
470	470
471	471	IMMWORD( p );
472	472	pPC = p.d;
473		cpustate->icount -= 10;
	473	m_icount -= 10;
474	474	}
475	475
476		static void br_ind(tms7000_state *cpustate)
	476	void tms7000_device::br_ind()
477	477	{
478	478	UINT8   v;
479	479
480	480	IMMBYTE( v );
481		PC.w.l = RRF16(cpustate,v);
	481	PC.w.l = RRF16(v);
482	482
483		cpustate->icount -= 9;
	483	m_icount -= 9;
484	484	}
485	485
486		static void br_inx(tms7000_state *cpustate)
	486	void tms7000_device::br_inx()
487	487	{
488	488	PAIR p;
489	489
490	490	IMMWORD( p );
491	491	pPC = p.w.l + RDB;
492		cpustate->icount -= 12;
	492	m_icount -= 12;
493	493	}
494	494
495		static void btjo_b2a(tms7000_state *cpustate)
	495	void tms7000_device::btjo_b2a()
496	496	{
497	497	UINT8   t;
498	498
r26878	r26879
508	508
509	509	SIMMBYTE( j );
510	510	pPC += j;
511		cpustate->icount -= 9;
	511	m_icount -= 9;
512	512	}
513	513	else
514	514	{
515	515	pPC++;
516		cpustate->icount -= 7;
	516	m_icount -= 7;
517	517	}
518	518	}
519	519
520		static void btjo_r2a(tms7000_state *cpustate)
	520	void tms7000_device::btjo_r2a()
521	521	{
522	522	UINT8   t,r;
523	523
r26878	r26879
534	534
535	535	SIMMBYTE( j );
536	536	pPC += j;
537		cpustate->icount -= 9;
	537	m_icount -= 9;
538	538	}
539	539	else
540	540	{
541	541	pPC++;
542		cpustate->icount -= 7;
	542	m_icount -= 7;
543	543	}
544	544	}
545	545
546		static void btjo_r2b(tms7000_state *cpustate)
	546	void tms7000_device::btjo_r2b()
547	547	{
548	548	UINT8   t,r;
549	549
r26878	r26879
560	560
561	561	SIMMBYTE(j);
562	562	pPC += j;
563		cpustate->icount -= 12;
	563	m_icount -= 12;
564	564	}
565	565	else
566	566	{
567	567	pPC++;
568		cpustate->icount -= 10;
	568	m_icount -= 10;
569	569	}
570	570	}
571	571
572		static void btjo_r2r(tms7000_state *cpustate)
	572	void tms7000_device::btjo_r2r()
573	573	{
574	574	UINT8   t,r,s;
575	575
r26878	r26879
587	587
588	588	SIMMBYTE(j);
589	589	pPC += j;
590		cpustate->icount -= 14;
	590	m_icount -= 14;
591	591	}
592	592	else
593	593	{
594	594	pPC++;
595		cpustate->icount -= 12;
	595	m_icount -= 12;
596	596	}
597	597	}
598	598
599		static void btjo_i2a(tms7000_state *cpustate)
	599	void tms7000_device::btjo_i2a()
600	600	{
601	601	UINT8   t,r;
602	602
r26878	r26879
613	613
614	614	SIMMBYTE(j);
615	615	pPC += j;
616		cpustate->icount -= 11;
	616	m_icount -= 11;
617	617	}
618	618	else
619	619	{
620	620	pPC++;
621		cpustate->icount -= 9;
	621	m_icount -= 9;
622	622	}
623	623	}
624	624
625		static void btjo_i2b(tms7000_state *cpustate)
	625	void tms7000_device::btjo_i2b()
626	626	{
627	627	UINT8   t,i;
628	628
r26878	r26879
639	639
640	640	SIMMBYTE(j);
641	641	pPC += j;
642		cpustate->icount -= 11;
	642	m_icount -= 11;
643	643	}
644	644	else
645	645	{
646	646	pPC++;
647		cpustate->icount -= 9;
	647	m_icount -= 9;
648	648	}
649	649	}
650	650
651		static void btjo_i2r(tms7000_state *cpustate)
	651	void tms7000_device::btjo_i2r()
652	652	{
653	653	UINT8   t,i,r;
654	654
r26878	r26879
666	666
667	667	SIMMBYTE(j);
668	668	pPC += j;
669		cpustate->icount -= 13;
	669	m_icount -= 13;
670	670	}
671	671	else
672	672	{
673	673	pPC++;
674		cpustate->icount -= 11;
	674	m_icount -= 11;
675	675	}
676	676	}
677	677
678		static void btjop_ap(tms7000_state *cpustate)
	678	void tms7000_device::btjop_ap()
679	679	{
680	680	UINT8   t,p;
681	681
r26878	r26879
693	693
694	694	SIMMBYTE(j);
695	695	pPC += j;
696		cpustate->icount -= 13;
	696	m_icount -= 13;
697	697	}
698	698	else
699	699	{
700	700	pPC++;
701		cpustate->icount -= 11;
	701	m_icount -= 11;
702	702	}
703	703	}
704	704
705		static void btjop_bp(tms7000_state *cpustate)
	705	void tms7000_device::btjop_bp()
706	706	{
707	707	UINT8   t,p;
708	708
r26878	r26879
720	720
721	721	SIMMBYTE(j);
722	722	pPC += j;
723		cpustate->icount -= 12;
	723	m_icount -= 12;
724	724	}
725	725	else
726	726	{
727	727	pPC++;
728		cpustate->icount -= 10;
	728	m_icount -= 10;
729	729	}
730	730	}
731	731
732		static void btjop_ip(tms7000_state *cpustate)
	732	void tms7000_device::btjop_ip()
733	733	{
734	734	UINT8   t,p,i;
735	735
r26878	r26879
748	748
749	749	SIMMBYTE(j);
750	750	pPC += j;
751		cpustate->icount -= 14;
	751	m_icount -= 14;
752	752	}
753	753	else
754	754	{
755	755	pPC++;
756		cpustate->icount -= 12;
	756	m_icount -= 12;
757	757	}
758	758	}
759	759
760		static void btjz_b2a(tms7000_state *cpustate)
	760	void tms7000_device::btjz_b2a()
761	761	{
762	762	UINT8   t;
763	763
r26878	r26879
773	773
774	774	SIMMBYTE( j );
775	775	pPC += j;
776		cpustate->icount -= 9;
	776	m_icount -= 9;
777	777	}
778	778	else
779	779	{
780	780	pPC++;
781		cpustate->icount -= 7;
	781	m_icount -= 7;
782	782	}
783	783	}
784	784
785		static void btjz_r2a(tms7000_state *cpustate)
	785	void tms7000_device::btjz_r2a()
786	786	{
787	787	UINT8   t,r;
788	788
r26878	r26879
799	799
800	800	SIMMBYTE( j );
801	801	pPC += j;
802		cpustate->icount -= 9;
	802	m_icount -= 9;
803	803	}
804	804	else
805	805	{
806	806	pPC++;
807		cpustate->icount -= 7;
	807	m_icount -= 7;
808	808	}
809	809	}
810	810
811		static void btjz_r2b(tms7000_state *cpustate)
	811	void tms7000_device::btjz_r2b()
812	812	{
813	813	UINT8   t,r;
814	814
r26878	r26879
825	825
826	826	SIMMBYTE(j);
827	827	pPC += j;
828		cpustate->icount -= 12;
	828	m_icount -= 12;
829	829	}
830	830	else
831	831	{
832	832	pPC++;
833		cpustate->icount -= 10;
	833	m_icount -= 10;
834	834	}
835	835	}
836	836
837		static void btjz_r2r(tms7000_state *cpustate)
	837	void tms7000_device::btjz_r2r()
838	838	{
839	839	UINT8   t,r,s;
840	840
r26878	r26879
852	852
853	853	SIMMBYTE(j);
854	854	pPC += j;
855		cpustate->icount -= 14;
	855	m_icount -= 14;
856	856	}
857	857	else
858	858	{
859	859	pPC++;
860		cpustate->icount -= 12;
	860	m_icount -= 12;
861	861	}
862	862	}
863	863
864		static void btjz_i2a(tms7000_state *cpustate)
	864	void tms7000_device::btjz_i2a()
865	865	{
866	866	UINT8   t,r;
867	867
r26878	r26879
878	878
879	879	SIMMBYTE(j);
880	880	pPC += j;
881		cpustate->icount -= 11;
	881	m_icount -= 11;
882	882	}
883	883	else
884	884	{
885	885	pPC++;
886		cpustate->icount -= 9;
	886	m_icount -= 9;
887	887	}
888	888	}
889	889
890		static void btjz_i2b(tms7000_state *cpustate)
	890	void tms7000_device::btjz_i2b()
891	891	{
892	892	UINT8   t,i;
893	893
r26878	r26879
904	904
905	905	SIMMBYTE(j);
906	906	pPC += j;
907		cpustate->icount -= 11;
	907	m_icount -= 11;
908	908	}
909	909	else
910	910	{
911	911	pPC++;
912		cpustate->icount -= 9;
	912	m_icount -= 9;
913	913	}
914	914	}
915	915
916		static void btjz_i2r(tms7000_state *cpustate)
	916	void tms7000_device::btjz_i2r()
917	917	{
918	918	UINT8   t,i,r;
919	919
r26878	r26879
931	931
932	932	SIMMBYTE(j);
933	933	pPC += j;
934		cpustate->icount -= 13;
	934	m_icount -= 13;
935	935	}
936	936	else
937	937	{
938	938	pPC++;
939		cpustate->icount -= 11;
	939	m_icount -= 11;
940	940	}
941	941	}
942	942
943		static void btjzp_ap(tms7000_state *cpustate)
	943	void tms7000_device::btjzp_ap()
944	944	{
945	945	UINT8   t,p;
946	946
r26878	r26879
958	958
959	959	SIMMBYTE(j);
960	960	pPC += j;
961		cpustate->icount -= 13;
	961	m_icount -= 13;
962	962	}
963	963	else
964	964	{
965	965	pPC++;
966		cpustate->icount -= 11;
	966	m_icount -= 11;
967	967	}
968	968	}
969	969
970		static void btjzp_bp(tms7000_state *cpustate)
	970	void tms7000_device::btjzp_bp()
971	971	{
972	972	UINT8   t,p;
973	973
r26878	r26879
985	985
986	986	SIMMBYTE(j);
987	987	pPC += j;
988		cpustate->icount -= 12;
	988	m_icount -= 12;
989	989	}
990	990	else
991	991	{
992	992	pPC++;
993		cpustate->icount -= 10;
	993	m_icount -= 10;
994	994	}
995	995	}
996	996
997		static void btjzp_ip(tms7000_state *cpustate)
	997	void tms7000_device::btjzp_ip()
998	998	{
999	999	UINT8   t,p,i;
1000	1000
r26878	r26879
1013	1013
1014	1014	SIMMBYTE(j);
1015	1015	pPC += j;
1016		cpustate->icount -= 14;
	1016	m_icount -= 14;
1017	1017	}
1018	1018	else
1019	1019	{
1020	1020	pPC++;
1021		cpustate->icount -= 12;
	1021	m_icount -= 12;
1022	1022	}
1023	1023	}
1024	1024
1025		static void call_dir(tms7000_state *cpustate)
	1025	void tms7000_device::call_dir()
1026	1026	{
1027	1027	PAIR    tPC;
1028	1028
r26878	r26879
1030	1030	PUSHWORD( PC );
1031	1031	pPC = tPC.d;
1032	1032
1033		cpustate->icount -= 14;
	1033	m_icount -= 14;
1034	1034	}
1035	1035
1036		static void call_ind(tms7000_state *cpustate)
	1036	void tms7000_device::call_ind()
1037	1037	{
1038	1038	UINT8   v;
1039	1039
1040	1040	IMMBYTE( v );
1041	1041	PUSHWORD( PC );
1042		PC.w.l = RRF16(cpustate,v);
	1042	PC.w.l = RRF16(v);
1043	1043
1044		cpustate->icount -= 13;
	1044	m_icount -= 13;
1045	1045	}
1046	1046
1047		static void call_inx(tms7000_state *cpustate)
	1047	void tms7000_device::call_inx()
1048	1048	{
1049	1049	PAIR    tPC;
1050	1050
1051	1051	IMMWORD( tPC );
1052	1052	PUSHWORD( PC );
1053	1053	pPC = tPC.w.l + RDB;
1054		cpustate->icount -= 16;
	1054	m_icount -= 16;
1055	1055	}
1056	1056
1057		static void clr_a(tms7000_state *cpustate)
	1057	void tms7000_device::clr_a()
1058	1058	{
1059	1059	WRA(0);
1060		cpustate->icount -= 5;
	1060	m_icount -= 5;
1061	1061	}
1062	1062
1063		static void clr_b(tms7000_state *cpustate)
	1063	void tms7000_device::clr_b()
1064	1064	{
1065	1065	WRB(0);
1066		cpustate->icount -= 5;
	1066	m_icount -= 5;
1067	1067	}
1068	1068
1069		static void clr_r(tms7000_state *cpustate)
	1069	void tms7000_device::clr_r()
1070	1070	{
1071	1071	UINT8   r;
1072	1072
1073	1073	IMMBYTE(r);
1074	1074	WM(r,0);
1075		cpustate->icount -= 7;
	1075	m_icount -= 7;
1076	1076	}
1077	1077
1078		static void clrc(tms7000_state *cpustate)
	1078	void tms7000_device::clrc()
1079	1079	{
1080	1080	UINT8   a;
1081	1081
r26878	r26879
1085	1085	SET_N8(a);
1086	1086	SET_Z8(a);
1087	1087
1088		cpustate->icount -= 6;
	1088	m_icount -= 6;
1089	1089	}
1090	1090
1091		static void cmp_ba(tms7000_state *cpustate)
	1091	void tms7000_device::cmp_ba()
1092	1092	{
1093	1093	UINT16 t;
1094	1094
r26878	r26879
1103	1103	else
1104	1104	SET_C8( ~t );
1105	1105
1106		cpustate->icount -= 5;
	1106	m_icount -= 5;
1107	1107	}
1108	1108
1109		static void cmp_ra(tms7000_state *cpustate)
	1109	void tms7000_device::cmp_ra()
1110	1110	{
1111	1111	UINT16  t;
1112	1112	UINT8   r;
r26878	r26879
1123	1123	else
1124	1124	SET_C8( ~t );
1125	1125
1126		cpustate->icount -= 8;
	1126	m_icount -= 8;
1127	1127	}
1128	1128
1129		static void cmp_rb(tms7000_state *cpustate)
	1129	void tms7000_device::cmp_rb()
1130	1130	{
1131	1131	UINT16  t;
1132	1132	UINT8   r;
r26878	r26879
1143	1143	else
1144	1144	SET_C8( ~t );
1145	1145
1146		cpustate->icount -= 8;
	1146	m_icount -= 8;
1147	1147	}
1148	1148
1149		static void cmp_rr(tms7000_state *cpustate)
	1149	void tms7000_device::cmp_rr()
1150	1150	{
1151	1151	UINT16  t;
1152	1152	UINT8   r,s;
r26878	r26879
1164	1164	else
1165	1165	SET_C8( ~t );
1166	1166
1167		cpustate->icount -= 10;
	1167	m_icount -= 10;
1168	1168	}
1169	1169
1170		static void cmp_ia(tms7000_state *cpustate)
	1170	void tms7000_device::cmp_ia()
1171	1171	{
1172	1172	UINT16  t;
1173	1173	UINT8   i;
r26878	r26879
1184	1184	else
1185	1185	SET_C8( ~t );
1186	1186
1187		cpustate->icount -= 7;
	1187	m_icount -= 7;
1188	1188	}
1189	1189
1190		static void cmp_ib(tms7000_state *cpustate)
	1190	void tms7000_device::cmp_ib()
1191	1191	{
1192	1192	UINT16  t;
1193	1193	UINT8   i;
r26878	r26879
1204	1204	else
1205	1205	SET_C8( ~t );
1206	1206
1207		cpustate->icount -= 7;
	1207	m_icount -= 7;
1208	1208	}
1209	1209
1210		static void cmp_ir(tms7000_state *cpustate)
	1210	void tms7000_device::cmp_ir()
1211	1211	{
1212	1212	UINT16  t;
1213	1213	UINT8   i,r;
r26878	r26879
1225	1225	else
1226	1226	SET_C8( ~t );
1227	1227
1228		cpustate->icount -= 9;
	1228	m_icount -= 9;
1229	1229	}
1230	1230
1231		static void cmpa_dir(tms7000_state *cpustate)
	1231	void tms7000_device::cmpa_dir()
1232	1232	{
1233	1233	UINT16  t;
1234	1234	PAIR    i;
r26878	r26879
1245	1245	else
1246	1246	SET_C8( ~t );
1247	1247
1248		cpustate->icount -= 12;
	1248	m_icount -= 12;
1249	1249	}
1250	1250
1251		static void cmpa_ind(tms7000_state *cpustate)
	1251	void tms7000_device::cmpa_ind()
1252	1252	{
1253	1253	UINT16  t;
1254	1254	PAIR    p;
1255	1255	INT8    i;
1256	1256
1257	1257	IMMBYTE(i);
1258		p.w.l = RRF16(cpustate,i);
	1258	p.w.l = RRF16(i);
1259	1259	t = RDA - RM(p.w.l);
1260	1260
1261	1261	CLR_NZC;
r26878	r26879
1267	1267	else
1268	1268	SET_C8( ~t );
1269	1269
1270		cpustate->icount -= 11;
	1270	m_icount -= 11;
1271	1271	}
1272	1272
1273		static void cmpa_inx(tms7000_state *cpustate)
	1273	void tms7000_device::cmpa_inx()
1274	1274	{
1275	1275	UINT16  t;
1276	1276	PAIR    i;
r26878	r26879
1287	1287	else
1288	1288	SET_C8( ~t );
1289	1289
1290		cpustate->icount -= 14;
	1290	m_icount -= 14;
1291	1291	}
1292	1292
1293		static void dac_b2a(tms7000_state *cpustate)
	1293	void tms7000_device::dac_b2a()
1294	1294	{
1295	1295	UINT16  t;
1296	1296
r26878	r26879
1306	1306	SET_N8(t);
1307	1307	SET_Z8(t);
1308	1308
1309		cpustate->icount -= 7;
	1309	m_icount -= 7;
1310	1310	}
1311	1311
1312		static void dac_r2a(tms7000_state *cpustate)
	1312	void tms7000_device::dac_r2a()
1313	1313	{
1314	1314	UINT8   r;
1315	1315	UINT16  t;
r26878	r26879
1328	1328	SET_N8(t);
1329	1329	SET_Z8(t);
1330	1330
1331		cpustate->icount -= 10;
	1331	m_icount -= 10;
1332	1332	}
1333	1333
1334		static void dac_r2b(tms7000_state *cpustate)
	1334	void tms7000_device::dac_r2b()
1335	1335	{
1336	1336	UINT8   r;
1337	1337	UINT16  t;
r26878	r26879
1350	1350	SET_N8(t);
1351	1351	SET_Z8(t);
1352	1352
1353		cpustate->icount -= 10;
	1353	m_icount -= 10;
1354	1354	}
1355	1355
1356		static void dac_r2r(tms7000_state *cpustate)
	1356	void tms7000_device::dac_r2r()
1357	1357	{
1358	1358	UINT8   r,s;
1359	1359	UINT16  t;
r26878	r26879
1373	1373	SET_N8(t);
1374	1374	SET_Z8(t);
1375	1375
1376		cpustate->icount -= 12;
	1376	m_icount -= 12;
1377	1377	}
1378	1378
1379		static void dac_i2a(tms7000_state *cpustate)
	1379	void tms7000_device::dac_i2a()
1380	1380	{
1381	1381	UINT8   i;
1382	1382	UINT16  t;
r26878	r26879
1395	1395	SET_N8(t);
1396	1396	SET_Z8(t);
1397	1397
1398		cpustate->icount -= 9;
	1398	m_icount -= 9;
1399	1399	}
1400	1400
1401		static void dac_i2b(tms7000_state *cpustate)
	1401	void tms7000_device::dac_i2b()
1402	1402	{
1403	1403	UINT8   i;
1404	1404	UINT16  t;
r26878	r26879
1417	1417	SET_N8(t);
1418	1418	SET_Z8(t);
1419	1419
1420		cpustate->icount -= 9;
	1420	m_icount -= 9;
1421	1421	}
1422	1422
1423		static void dac_i2r(tms7000_state *cpustate)
	1423	void tms7000_device::dac_i2r()
1424	1424	{
1425	1425	UINT8   i,r;
1426	1426	UINT16  t;
r26878	r26879
1440	1440	SET_N8(t);
1441	1441	SET_Z8(t);
1442	1442
1443		cpustate->icount -= 11;
	1443	m_icount -= 11;
1444	1444	}
1445	1445
1446		static void dec_a(tms7000_state *cpustate)
	1446	void tms7000_device::dec_a()
1447	1447	{
1448	1448	UINT16 t;
1449	1449
r26878	r26879
1456	1456	SET_Z8(t);
1457	1457	SET_C8(~t);
1458	1458
1459		cpustate->icount -= 5;
	1459	m_icount -= 5;
1460	1460	}
1461	1461
1462		static void dec_b(tms7000_state *cpustate)
	1462	void tms7000_device::dec_b()
1463	1463	{
1464	1464	UINT16 t;
1465	1465
r26878	r26879
1472	1472	SET_Z8(t);
1473	1473	SET_C8(~t);
1474	1474
1475		cpustate->icount -= 5;
	1475	m_icount -= 5;
1476	1476	}
1477	1477
1478		static void dec_r(tms7000_state *cpustate)
	1478	void tms7000_device::dec_r()
1479	1479	{
1480	1480	UINT16  t;
1481	1481	UINT8   r;
r26878	r26879
1491	1491	SET_Z8(t);
1492	1492	SET_C8(~t);
1493	1493
1494		cpustate->icount -= 7;
	1494	m_icount -= 7;
1495	1495	}
1496	1496
1497		static void decd_a(tms7000_state *cpustate)
	1497	void tms7000_device::decd_a()
1498	1498	{
1499	1499	PAIR    t;
1500	1500
1501	1501	t.w.h = 0;
1502		t.w.l = RRF16(cpustate,0);
	1502	t.w.l = RRF16(0);
1503	1503	t.d -= 1;
1504		WRF16(cpustate,0,t);
	1504	WRF16(0,t);
1505	1505
1506	1506	CLR_NZC;
1507	1507	SET_N8(t.b.h);
r26878	r26879
1509	1509
1510	1510	SET_C16(~(t.d));
1511	1511
1512		cpustate->icount -= 9;
	1512	m_icount -= 9;
1513	1513	}
1514	1514
1515		static void decd_b(tms7000_state *cpustate)
	1515	void tms7000_device::decd_b()
1516	1516	{
1517	1517	PAIR    t;
1518	1518
1519	1519	t.w.h = 0;
1520		t.w.l = RRF16(cpustate,1);
	1520	t.w.l = RRF16(1);
1521	1521	t.d -= 1;
1522		WRF16(cpustate,1,t);
	1522	WRF16(1,t);
1523	1523
1524	1524	CLR_NZC;
1525	1525	SET_N8(t.b.h);
r26878	r26879
1527	1527
1528	1528	SET_C16(~(t.d));
1529	1529
1530		cpustate->icount -= 9;
	1530	m_icount -= 9;
1531	1531	}
1532	1532
1533		static void decd_r(tms7000_state *cpustate)
	1533	void tms7000_device::decd_r()
1534	1534	{
1535	1535	UINT8   r;
1536	1536	PAIR    t;
1537	1537
1538	1538	IMMBYTE(r);
1539	1539	t.w.h = 0;
1540		t.w.l = RRF16(cpustate,r);
	1540	t.w.l = RRF16(r);
1541	1541	t.d -= 1;
1542		WRF16(cpustate,r,t);
	1542	WRF16(r,t);
1543	1543
1544	1544	CLR_NZC;
1545	1545	SET_N8(t.b.h);
r26878	r26879
1547	1547
1548	1548	SET_C16(~(t.d));
1549	1549
1550		cpustate->icount -= 11;
	1550	m_icount -= 11;
1551	1551	}
1552	1552
1553		static void dint(tms7000_state *cpustate)
	1553	void tms7000_device::dint()
1554	1554	{
1555	1555	CLR_NZCI;
1556		cpustate->icount -= 5;
	1556	m_icount -= 5;
1557	1557	}
1558	1558
1559		static void djnz_a(tms7000_state *cpustate)
	1559	void tms7000_device::djnz_a()
1560	1560	{
1561	1561	UINT16 t;
1562	1562
r26878	r26879
1574	1574
1575	1575	SIMMBYTE(s);
1576	1576	pPC += s;
1577		cpustate->icount -= 7;
	1577	m_icount -= 7;
1578	1578	}
1579	1579	else
1580	1580	{
1581	1581	pPC++;
1582		cpustate->icount -= 2;
	1582	m_icount -= 2;
1583	1583	}
1584	1584	}
1585	1585
1586		static void djnz_b(tms7000_state *cpustate)
	1586	void tms7000_device::djnz_b()
1587	1587	{
1588	1588	UINT16 t;
1589	1589
r26878	r26879
1601	1601
1602	1602	SIMMBYTE(s);
1603	1603	pPC += s;
1604		cpustate->icount -= 7;
	1604	m_icount -= 7;
1605	1605	}
1606	1606	else
1607	1607	{
1608	1608	pPC++;
1609		cpustate->icount -= 2;
	1609	m_icount -= 2;
1610	1610	}
1611	1611	}
1612	1612
1613		static void djnz_r(tms7000_state *cpustate)
	1613	void tms7000_device::djnz_r()
1614	1614	{
1615	1615	UINT16  t;
1616	1616	UINT8   r;
r26878	r26879
1631	1631
1632	1632	SIMMBYTE(s);
1633	1633	pPC += s;
1634		cpustate->icount -= 9;
	1634	m_icount -= 9;
1635	1635	}
1636	1636	else
1637	1637	{
1638	1638	pPC++;
1639		cpustate->icount -= 3;
	1639	m_icount -= 3;
1640	1640	}
1641	1641	}
1642	1642
1643		static void dsb_b2a(tms7000_state *cpustate)
	1643	void tms7000_device::dsb_b2a()
1644	1644	{
1645	1645	UINT16  t;
1646	1646
r26878	r26879
1656	1656	SET_N8(t);
1657	1657	SET_Z8(t);
1658	1658
1659		cpustate->icount -= 7;
	1659	m_icount -= 7;
1660	1660	}
1661	1661
1662		static void dsb_r2a(tms7000_state *cpustate)
	1662	void tms7000_device::dsb_r2a()
1663	1663	{
1664	1664	UINT8   r;
1665	1665	UINT16  t;
r26878	r26879
1678	1678	SET_N8(t);
1679	1679	SET_Z8(t);
1680	1680
1681		cpustate->icount -= 10;
	1681	m_icount -= 10;
1682	1682	}
1683	1683
1684		static void dsb_r2b(tms7000_state *cpustate)
	1684	void tms7000_device::dsb_r2b()
1685	1685	{
1686	1686	UINT8   r;
1687	1687	UINT16  t;
r26878	r26879
1700	1700	SET_N8(t);
1701	1701	SET_Z8(t);
1702	1702
1703		cpustate->icount -= 10;
	1703	m_icount -= 10;
1704	1704	}
1705	1705
1706		static void dsb_r2r(tms7000_state *cpustate)
	1706	void tms7000_device::dsb_r2r()
1707	1707	{
1708	1708	UINT8   r,s;
1709	1709	UINT16  t;
r26878	r26879
1723	1723	SET_N8(t);
1724	1724	SET_Z8(t);
1725	1725
1726		cpustate->icount -= 12;
	1726	m_icount -= 12;
1727	1727	}
1728	1728
1729		static void dsb_i2a(tms7000_state *cpustate)
	1729	void tms7000_device::dsb_i2a()
1730	1730	{
1731	1731	UINT8   i;
1732	1732	UINT16  t;
r26878	r26879
1745	1745	SET_N8(t);
1746	1746	SET_Z8(t);
1747	1747
1748		cpustate->icount -= 9;
	1748	m_icount -= 9;
1749	1749	}
1750	1750
1751		static void dsb_i2b(tms7000_state *cpustate)
	1751	void tms7000_device::dsb_i2b()
1752	1752	{
1753	1753	UINT8   i;
1754	1754	UINT16  t;
r26878	r26879
1767	1767	SET_N8(t);
1768	1768	SET_Z8(t);
1769	1769
1770		cpustate->icount -= 9;
	1770	m_icount -= 9;
1771	1771	}
1772	1772
1773		static void dsb_i2r(tms7000_state *cpustate)
	1773	void tms7000_device::dsb_i2r()
1774	1774	{
1775	1775	UINT8   r,i;
1776	1776	UINT16  t;
r26878	r26879
1790	1790	SET_N8(t);
1791	1791	SET_Z8(t);
1792	1792
1793		cpustate->icount -= 11;
	1793	m_icount -= 11;
1794	1794	}
1795	1795
1796		static void eint(tms7000_state *cpustate)
	1796	void tms7000_device::eint()
1797	1797	{
1798	1798	pSR |= (SR_N|SR_Z|SR_C|SR_I);
1799		cpustate->icount -= 5;
1800		tms7000_check_IRQ_lines(cpustate);
	1799	m_icount -= 5;
	1800	tms7000_check_IRQ_lines();
1801	1801	}
1802	1802
1803		static void idle(tms7000_state *cpustate)
	1803	void tms7000_device::idle()
1804	1804	{
1805		cpustate->idle_state = 1;
1806		cpustate->icount -= 6;
	1805	m_idle_state = 1;
	1806	m_icount -= 6;
1807	1807	}
1808	1808
1809		static void inc_a(tms7000_state *cpustate)
	1809	void tms7000_device::inc_a()
1810	1810	{
1811	1811	UINT16  t;
1812	1812
r26878	r26879
1819	1819	SET_N8(t);
1820	1820	SET_Z8(t);
1821	1821
1822		cpustate->icount -= 5;
	1822	m_icount -= 5;
1823	1823	}
1824	1824
1825		static void inc_b(tms7000_state *cpustate)
	1825	void tms7000_device::inc_b()
1826	1826	{
1827	1827	UINT16  t;
1828	1828
r26878	r26879
1835	1835	SET_N8(t);
1836	1836	SET_Z8(t);
1837	1837
1838		cpustate->icount -= 5;
	1838	m_icount -= 5;
1839	1839	}
1840	1840
1841		static void inc_r(tms7000_state *cpustate)
	1841	void tms7000_device::inc_r()
1842	1842	{
1843	1843	UINT16  t;
1844	1844	UINT8   r;
r26878	r26879
1854	1854	SET_Z8(t);
1855	1855	SET_C8(t);
1856	1856
1857		cpustate->icount -= 7;
	1857	m_icount -= 7;
1858	1858	}
1859	1859
1860		static void inv_a(tms7000_state *cpustate)
	1860	void tms7000_device::inv_a()
1861	1861	{
1862	1862	UINT16 t;
1863	1863
r26878	r26879
1868	1868	SET_N8(t);
1869	1869	SET_Z8(t);
1870	1870
1871		cpustate->icount -= 5;
	1871	m_icount -= 5;
1872	1872	}
1873	1873
1874		static void inv_b(tms7000_state *cpustate)
	1874	void tms7000_device::inv_b()
1875	1875	{
1876	1876	UINT16 t;
1877	1877
r26878	r26879
1882	1882	SET_N8(t);
1883	1883	SET_Z8(t);
1884	1884
1885		cpustate->icount -= 5;
	1885	m_icount -= 5;
1886	1886	}
1887	1887
1888		static void inv_r(tms7000_state *cpustate)
	1888	void tms7000_device::inv_r()
1889	1889	{
1890	1890	UINT16  t;
1891	1891	UINT8   r;
r26878	r26879
1900	1900	SET_N8(t);
1901	1901	SET_Z8(t);
1902	1902
1903		cpustate->icount -= 7;
	1903	m_icount -= 7;
1904	1904	}
1905	1905
1906		static void jc(tms7000_state *cpustate)
	1906	void tms7000_device::jc()
1907	1907	{
1908	1908	if( pSR & SR_C )
1909	1909	{
r26878	r26879
1911	1911
1912	1912	SIMMBYTE( s );
1913	1913	pPC += s;
1914		cpustate->icount -= 7;
	1914	m_icount -= 7;
1915	1915	}
1916	1916	else
1917	1917	{
1918	1918	pPC++;
1919		cpustate->icount -= 5;
	1919	m_icount -= 5;
1920	1920	}
1921	1921	}
1922	1922
1923		static void jeq(tms7000_state *cpustate)
	1923	void tms7000_device::jeq()
1924	1924	{
1925	1925	if( pSR & SR_Z )
1926	1926	{
r26878	r26879
1928	1928
1929	1929	SIMMBYTE( s );
1930	1930	pPC += s;
1931		cpustate->icount -= 7;
	1931	m_icount -= 7;
1932	1932	}
1933	1933	else
1934	1934	{
1935	1935	pPC++;
1936		cpustate->icount -= 5;
	1936	m_icount -= 5;
1937	1937	}
1938	1938	}
1939	1939
1940		static void jl(tms7000_state *cpustate)
	1940	void tms7000_device::jl()
1941	1941	{
1942	1942	if( pSR & SR_C )
1943	1943	{
1944	1944	pPC++;
1945		cpustate->icount -= 5;
	1945	m_icount -= 5;
1946	1946	}
1947	1947	else
1948	1948	{
r26878	r26879
1950	1950
1951	1951	SIMMBYTE( s );
1952	1952	pPC += s;
1953		cpustate->icount -= 7;
	1953	m_icount -= 7;
1954	1954	}
1955	1955	}
1956	1956
1957		static void jmp(tms7000_state *cpustate)
	1957	void tms7000_device::jmp()
1958	1958	{
1959	1959	INT8 s;
1960	1960
1961	1961	SIMMBYTE( s );
1962	1962	pPC += s;
1963		cpustate->icount -= 7;
	1963	m_icount -= 7;
1964	1964	}
1965	1965
1966		static void j_jn(tms7000_state *cpustate)
	1966	void tms7000_device::j_jn()
1967	1967	{
1968	1968	if( pSR & SR_N )
1969	1969	{
r26878	r26879
1971	1971
1972	1972	SIMMBYTE( s );
1973	1973	pPC += s;
1974		cpustate->icount -= 7;
	1974	m_icount -= 7;
1975	1975	}
1976	1976	else
1977	1977	{
1978	1978	pPC++;
1979		cpustate->icount -= 5;
	1979	m_icount -= 5;
1980	1980	}
1981	1981
1982	1982	}
1983	1983
1984		static void jne(tms7000_state *cpustate)
	1984	void tms7000_device::jne()
1985	1985	{
1986	1986	if( pSR & SR_Z )
1987	1987	{
1988	1988	pPC++;
1989		cpustate->icount -= 5;
	1989	m_icount -= 5;
1990	1990	}
1991	1991	else
1992	1992	{
r26878	r26879
1994	1994
1995	1995	SIMMBYTE( s );
1996	1996	pPC += s;
1997		cpustate->icount -= 7;
	1997	m_icount -= 7;
1998	1998	}
1999	1999	}
2000	2000
2001		static void jp(tms7000_state *cpustate)
	2001	void tms7000_device::jp()
2002	2002	{
2003	2003	if( pSR & (SR_Z|SR_N) )
2004	2004	{
2005	2005	pPC++;
2006		cpustate->icount -= 5;
	2006	m_icount -= 5;
2007	2007	}
2008	2008	else
2009	2009	{
r26878	r26879
2011	2011
2012	2012	SIMMBYTE( s );
2013	2013	pPC += s;
2014		cpustate->icount -= 7;
	2014	m_icount -= 7;
2015	2015	}
2016	2016	}
2017	2017
2018		static void jpz(tms7000_state *cpustate)
	2018	void tms7000_device::jpz()
2019	2019	{
2020	2020	if ((pSR & SR_N) == 0)
2021	2021	{
r26878	r26879
2023	2023
2024	2024	SIMMBYTE( s );
2025	2025	pPC += s;
2026		cpustate->icount -= 7;
	2026	m_icount -= 7;
2027	2027	}
2028	2028	else
2029	2029	{
2030	2030	pPC++;
2031		cpustate->icount -= 5;
	2031	m_icount -= 5;
2032	2032	}
2033	2033	}
2034	2034
2035		static void lda_dir(tms7000_state *cpustate)
	2035	void tms7000_device::lda_dir()
2036	2036	{
2037	2037	UINT16  t;
2038	2038	PAIR    i;
r26878	r26879
2045	2045	SET_N8(t);
2046	2046	SET_Z8(t);
2047	2047
2048		cpustate->icount -= 11;
	2048	m_icount -= 11;
2049	2049	}
2050	2050
2051		static void lda_ind(tms7000_state *cpustate)
	2051	void tms7000_device::lda_ind()
2052	2052	{
2053	2053	UINT16  t;
2054	2054	PAIR    p;
2055	2055	INT8    i;
2056	2056
2057	2057	IMMBYTE(i);
2058		p.w.l=RRF16(cpustate,i);
	2058	p.w.l=RRF16(i);
2059	2059	t = RM(p.w.l);
2060	2060	WRA(t);
2061	2061
r26878	r26879
2063	2063	SET_N8(t);
2064	2064	SET_Z8(t);
2065	2065
2066		cpustate->icount -= 10;
	2066	m_icount -= 10;
2067	2067	}
2068	2068
2069		static void lda_inx(tms7000_state *cpustate)
	2069	void tms7000_device::lda_inx()
2070	2070	{
2071	2071	UINT16  t;
2072	2072	PAIR    i;
r26878	r26879
2079	2079	SET_N8(t);
2080	2080	SET_Z8(t);
2081	2081
2082		cpustate->icount -= 13;
	2082	m_icount -= 13;
2083	2083	}
2084	2084
2085		static void ldsp(tms7000_state *cpustate)
	2085	void tms7000_device::ldsp()
2086	2086	{
2087	2087	pSP = RDB;
2088		cpustate->icount -= 5;
	2088	m_icount -= 5;
2089	2089	}
2090	2090
2091		static void mov_a2b(tms7000_state *cpustate)
	2091	void tms7000_device::mov_a2b()
2092	2092	{
2093	2093	UINT16  t;
2094	2094
r26878	r26879
2099	2099	SET_N8(t);
2100	2100	SET_Z8(t);
2101	2101
2102		cpustate->icount -= 6;
	2102	m_icount -= 6;
2103	2103	}
2104	2104
2105		static void mov_b2a(tms7000_state *cpustate)
	2105	void tms7000_device::mov_b2a()
2106	2106	{
2107	2107	UINT16  t;
2108	2108
r26878	r26879
2113	2113	SET_N8(t);
2114	2114	SET_Z8(t);
2115	2115
2116		cpustate->icount -= 5;
	2116	m_icount -= 5;
2117	2117	}
2118	2118
2119	2119
2120		static void mov_a2r(tms7000_state *cpustate)
	2120	void tms7000_device::mov_a2r()
2121	2121	{
2122	2122	UINT8   r;
2123	2123	UINT16  t;
r26878	r26879
2131	2131	SET_N8(t);
2132	2132	SET_Z8(t);
2133	2133
2134		cpustate->icount -= 8;
	2134	m_icount -= 8;
2135	2135	}
2136	2136
2137		static void mov_b2r(tms7000_state *cpustate)
	2137	void tms7000_device::mov_b2r()
2138	2138	{
2139	2139	UINT8   r;
2140	2140	UINT16  t;
r26878	r26879
2148	2148	SET_N8(t);
2149	2149	SET_Z8(t);
2150	2150
2151		cpustate->icount -= 7;
	2151	m_icount -= 7;
2152	2152	}
2153	2153
2154		static void mov_r2a(tms7000_state *cpustate)
	2154	void tms7000_device::mov_r2a()
2155	2155	{
2156	2156	UINT8   r;
2157	2157	UINT16  t;
r26878	r26879
2164	2164	SET_N8(t);
2165	2165	SET_Z8(t);
2166	2166
2167		cpustate->icount -= 8;
	2167	m_icount -= 8;
2168	2168	}
2169	2169
2170		static void mov_r2b(tms7000_state *cpustate)
	2170	void tms7000_device::mov_r2b()
2171	2171	{
2172	2172	UINT8   r;
2173	2173	UINT16  t;
r26878	r26879
2180	2180	SET_N8(t);
2181	2181	SET_Z8(t);
2182	2182
2183		cpustate->icount -= 8;
	2183	m_icount -= 8;
2184	2184	}
2185	2185
2186		static void mov_r2r(tms7000_state *cpustate)
	2186	void tms7000_device::mov_r2r()
2187	2187	{
2188	2188	UINT8   r,s;
2189	2189	UINT16  t;
r26878	r26879
2197	2197	SET_N8(t);
2198	2198	SET_Z8(t);
2199	2199
2200		cpustate->icount -= 10;
	2200	m_icount -= 10;
2201	2201	}
2202	2202
2203		static void mov_i2a(tms7000_state *cpustate)
	2203	void tms7000_device::mov_i2a()
2204	2204	{
2205	2205	UINT16  t;
2206	2206
r26878	r26879
2211	2211	SET_N8(t);
2212	2212	SET_Z8(t);
2213	2213
2214		cpustate->icount -= 7;
	2214	m_icount -= 7;
2215	2215	}
2216	2216
2217		static void mov_i2b(tms7000_state *cpustate)
	2217	void tms7000_device::mov_i2b()
2218	2218	{
2219	2219	UINT16  t;
2220	2220
r26878	r26879
2225	2225	SET_N8(t);
2226	2226	SET_Z8(t);
2227	2227
2228		cpustate->icount -= 7;
	2228	m_icount -= 7;
2229	2229	}
2230	2230
2231		static void mov_i2r(tms7000_state *cpustate)
	2231	void tms7000_device::mov_i2r()
2232	2232	{
2233	2233	UINT16  t;
2234	2234	UINT8   r;
r26878	r26879
2241	2241	SET_N8(t);
2242	2242	SET_Z8(t);
2243	2243
2244		cpustate->icount -= 9;
	2244	m_icount -= 9;
2245	2245	}
2246	2246
2247		static void movd_imm(tms7000_state *cpustate)
	2247	void tms7000_device::movd_imm()
2248	2248	{
2249	2249	PAIR    t;
2250	2250	UINT8   r;
2251	2251
2252	2252	IMMWORD(t);
2253	2253	IMMBYTE(r);
2254		WRF16(cpustate,r,t);
	2254	WRF16(r,t);
2255	2255
2256	2256	CLR_NZC;
2257	2257	SET_N8(t.b.h);
2258	2258	SET_Z8(t.b.h);
2259	2259
2260		cpustate->icount -= 15;
	2260	m_icount -= 15;
2261	2261
2262	2262	}
2263	2263
2264		static void movd_r(tms7000_state *cpustate)
	2264	void tms7000_device::movd_r()
2265	2265	{
2266	2266	PAIR    t;
2267	2267	UINT8   r,s;
2268	2268
2269	2269	IMMBYTE(r);
2270	2270	IMMBYTE(s);
2271		t.w.l = RRF16(cpustate,r);
2272		WRF16(cpustate,s,t);
	2271	t.w.l = RRF16(r);
	2272	WRF16(s,t);
2273	2273
2274	2274	CLR_NZC;
2275	2275	SET_N8(t.b.h);
2276	2276	SET_Z8(t.b.h);
2277	2277
2278		cpustate->icount -= 14;
	2278	m_icount -= 14;
2279	2279
2280	2280	}
2281	2281
2282		static void movd_inx(tms7000_state *cpustate)
	2282	void tms7000_device::movd_inx()
2283	2283	{
2284	2284	PAIR    t;
2285	2285	UINT8   r;
r26878	r26879
2287	2287	IMMWORD(t);
2288	2288	t.w.l += RDB;
2289	2289	IMMBYTE(r);
2290		WRF16(cpustate,r,t);
	2290	WRF16(r,t);
2291	2291
2292	2292	CLR_NZC;
2293	2293	SET_N8(t.b.h);
2294	2294	SET_Z8(t.b.h);
2295	2295
2296		cpustate->icount -= 17;
	2296	m_icount -= 17;
2297	2297	}
2298	2298
2299		static void movp_a2p(tms7000_state *cpustate)
	2299	void tms7000_device::movp_a2p()
2300	2300	{
2301	2301	UINT8   p;
2302	2302	UINT16  t;
r26878	r26879
2309	2309	SET_N8(t);
2310	2310	SET_Z8(t);
2311	2311
2312		cpustate->icount -= 10;
	2312	m_icount -= 10;
2313	2313	}
2314	2314
2315		static void movp_b2p(tms7000_state *cpustate)
	2315	void tms7000_device::movp_b2p()
2316	2316	{
2317	2317	UINT8   p;
2318	2318	UINT16  t;
r26878	r26879
2325	2325	SET_N8(t);
2326	2326	SET_Z8(t);
2327	2327
2328		cpustate->icount -= 10;
	2328	m_icount -= 10;
2329	2329	}
2330	2330
2331	2331	#if 0
2332	2332	/* this appears to be unused */
2333		static void movp_r2p(tms7000_state *cpustate)
	2333	void tms7000_device::movp_r2p()
2334	2334	{
2335	2335	UINT8   p,r;
2336	2336	UINT16  t;
r26878	r26879
2344	2344	SET_N8(t);
2345	2345	SET_Z8(t);
2346	2346
2347		cpustate->icount -= 11;
	2347	m_icount -= 11;
2348	2348	}
2349	2349	#endif
2350	2350
2351		static void movp_p2a(tms7000_state *cpustate)
	2351	void tms7000_device::movp_p2a()
2352	2352	{
2353	2353	UINT8   p;
2354	2354	UINT16  t;
r26878	r26879
2361	2361	SET_N8(t);
2362	2362	SET_Z8(t);
2363	2363
2364		cpustate->icount -= 9;
	2364	m_icount -= 9;
2365	2365	}
2366	2366
2367		static void movp_p2b(tms7000_state *cpustate)
	2367	void tms7000_device::movp_p2b()
2368	2368	{
2369	2369	UINT8   p;
2370	2370	UINT16  t;
r26878	r26879
2377	2377	SET_N8(t);
2378	2378	SET_Z8(t);
2379	2379
2380		cpustate->icount -= 8;
	2380	m_icount -= 8;
2381	2381	}
2382	2382
2383		static void mpy_ba(tms7000_state *cpustate)
	2383	void tms7000_device::mpy_ba()
2384	2384	{
2385	2385	PAIR t;
2386	2386
2387	2387	t.w.l = RDA * RDB;
2388	2388
2389		WRF16(cpustate,0x01,t);
	2389	WRF16(0x01,t);
2390	2390
2391	2391	CLR_NZC;
2392	2392	SET_N8(t.b.h);
2393	2393	SET_Z8(t.b.h);
2394	2394
2395		cpustate->icount -= 43;
	2395	m_icount -= 43;
2396	2396
2397	2397	}
2398	2398
2399		static void mpy_ra(tms7000_state *cpustate)
	2399	void tms7000_device::mpy_ra()
2400	2400	{
2401	2401	PAIR    t;
2402	2402	UINT8   r;
r26878	r26879
2405	2405
2406	2406	t.w.l = RDA * RM(r);
2407	2407
2408		WRF16(cpustate,0x01,t);
	2408	WRF16(0x01,t);
2409	2409
2410	2410	CLR_NZC;
2411	2411	SET_N8(t.b.h);
2412	2412	SET_Z8(t.b.h);
2413	2413
2414		cpustate->icount -= 46;
	2414	m_icount -= 46;
2415	2415
2416	2416	}
2417	2417
2418		static void mpy_rb(tms7000_state *cpustate)
	2418	void tms7000_device::mpy_rb()
2419	2419	{
2420	2420	PAIR    t;
2421	2421	UINT8   r;
r26878	r26879
2424	2424
2425	2425	t.w.l = RDB * RM(r);
2426	2426
2427		WRF16(cpustate,0x01,t);
	2427	WRF16(0x01,t);
2428	2428
2429	2429	CLR_NZC;
2430	2430	SET_N8(t.b.h);
2431	2431	SET_Z8(t.b.h);
2432	2432
2433		cpustate->icount -= 46;
	2433	m_icount -= 46;
2434	2434
2435	2435	}
2436	2436
2437		static void mpy_rr(tms7000_state *cpustate)
	2437	void tms7000_device::mpy_rr()
2438	2438	{
2439	2439	PAIR    t;
2440	2440	UINT8   r,s;
r26878	r26879
2444	2444
2445	2445	t.w.l = RM(s) * RM(r);
2446	2446
2447		WRF16(cpustate,0x01,t);
	2447	WRF16(0x01,t);
2448	2448
2449	2449	CLR_NZC;
2450	2450	SET_N8(t.b.h);
2451	2451	SET_Z8(t.b.h);
2452	2452
2453		cpustate->icount -= 48;
	2453	m_icount -= 48;
2454	2454
2455	2455	}
2456	2456
2457		static void mpy_ia(tms7000_state *cpustate)
	2457	void tms7000_device::mpy_ia()
2458	2458	{
2459	2459	PAIR    t;
2460	2460	UINT8   i;
r26878	r26879
2463	2463
2464	2464	t.w.l = RDA * i;
2465	2465
2466		WRF16(cpustate,0x01,t);
	2466	WRF16(0x01,t);
2467	2467
2468	2468	CLR_NZC;
2469	2469	SET_N8(t.b.h);
2470	2470	SET_Z8(t.b.h);
2471	2471
2472		cpustate->icount -= 45;
	2472	m_icount -= 45;
2473	2473
2474	2474	}
2475	2475
2476		static void mpy_ib(tms7000_state *cpustate)
	2476	void tms7000_device::mpy_ib()
2477	2477	{
2478	2478	PAIR    t;
2479	2479	UINT8   i;
r26878	r26879
2482	2482
2483	2483	t.w.l = RDB * i;
2484	2484
2485		WRF16(cpustate,0x01,t);
	2485	WRF16(0x01,t);
2486	2486
2487	2487	CLR_NZC;
2488	2488	SET_N8(t.b.h);
2489	2489	SET_Z8(t.b.h);
2490	2490
2491		cpustate->icount -= 45;
	2491	m_icount -= 45;
2492	2492
2493	2493	}
2494	2494
2495		static void mpy_ir(tms7000_state *cpustate)
	2495	void tms7000_device::mpy_ir()
2496	2496	{
2497	2497	PAIR    t;
2498	2498	UINT8   i,r;
r26878	r26879
2502	2502
2503	2503	t.w.l = RM(r) * i;
2504	2504
2505		WRF16(cpustate,0x01,t);
	2505	WRF16(0x01,t);
2506	2506
2507	2507	CLR_NZC;
2508	2508	SET_N8(t.b.h);
2509	2509	SET_Z8(t.b.h);
2510	2510
2511		cpustate->icount -= 47;
	2511	m_icount -= 47;
2512	2512
2513	2513	}
2514	2514
2515		static void nop(tms7000_state *cpustate)
	2515	void tms7000_device::nop()
2516	2516	{
2517		cpustate->icount -= 4;
	2517	m_icount -= 4;
2518	2518	}
2519	2519
2520		static void or_b2a(tms7000_state *cpustate)
	2520	void tms7000_device::or_b2a()
2521	2521	{
2522	2522	UINT8   t;
2523	2523
r26878	r26879
2528	2528	SET_N8(t);
2529	2529	SET_Z8(t);
2530	2530
2531		cpustate->icount -= 5;
	2531	m_icount -= 5;
2532	2532	}
2533	2533
2534		static void or_r2a(tms7000_state *cpustate)
	2534	void tms7000_device::or_r2a()
2535	2535	{
2536	2536	UINT8   t;
2537	2537	UINT8   v;
r26878	r26879
2545	2545	SET_N8(t);
2546	2546	SET_Z8(t);
2547	2547
2548		cpustate->icount -= 8;
	2548	m_icount -= 8;
2549	2549	}
2550	2550
2551		static void or_r2b(tms7000_state *cpustate)
	2551	void tms7000_device::or_r2b()
2552	2552	{
2553	2553	UINT8   t;
2554	2554	UINT8   v;
r26878	r26879
2562	2562	SET_N8(t);
2563	2563	SET_Z8(t);
2564	2564
2565		cpustate->icount -= 8;
	2565	m_icount -= 8;
2566	2566	}
2567	2567
2568		static void or_r2r(tms7000_state *cpustate)
	2568	void tms7000_device::or_r2r()
2569	2569	{
2570	2570	UINT8   t;
2571	2571	UINT8   i,j;
r26878	r26879
2580	2580	SET_N8(t);
2581	2581	SET_Z8(t);
2582	2582
2583		cpustate->icount -= 10;
	2583	m_icount -= 10;
2584	2584	}
2585	2585
2586		static void or_i2a(tms7000_state *cpustate)
	2586	void tms7000_device::or_i2a()
2587	2587	{
2588	2588	UINT8   t;
2589	2589	UINT8   v;
r26878	r26879
2597	2597	SET_N8(t);
2598	2598	SET_Z8(t);
2599	2599
2600		cpustate->icount -= 7;
	2600	m_icount -= 7;
2601	2601	}
2602	2602
2603		static void or_i2b(tms7000_state *cpustate)
	2603	void tms7000_device::or_i2b()
2604	2604	{
2605	2605	UINT8   t;
2606	2606	UINT8   v;
r26878	r26879
2614	2614	SET_N8(t);
2615	2615	SET_Z8(t);
2616	2616
2617		cpustate->icount -= 7;
	2617	m_icount -= 7;
2618	2618	}
2619	2619
2620		static void or_i2r(tms7000_state *cpustate)
	2620	void tms7000_device::or_i2r()
2621	2621	{
2622	2622	UINT8   t;
2623	2623	UINT8   i,j;
r26878	r26879
2632	2632	SET_N8(t);
2633	2633	SET_Z8(t);
2634	2634
2635		cpustate->icount -= 9;
	2635	m_icount -= 9;
2636	2636	}
2637	2637
2638		static void orp_a2p(tms7000_state *cpustate)
	2638	void tms7000_device::orp_a2p()
2639	2639	{
2640	2640	UINT8   t;
2641	2641	UINT8   v;
r26878	r26879
2648	2648	SET_N8(t);
2649	2649	SET_Z8(t);
2650	2650
2651		cpustate->icount -= 10;
	2651	m_icount -= 10;
2652	2652	}
2653	2653
2654		static void orp_b2p(tms7000_state *cpustate)
	2654	void tms7000_device::orp_b2p()
2655	2655	{
2656	2656	UINT8   t;
2657	2657	UINT8   v;
r26878	r26879
2664	2664	SET_N8(t);
2665	2665	SET_Z8(t);
2666	2666
2667		cpustate->icount -= 9;
	2667	m_icount -= 9;
2668	2668	}
2669	2669
2670		static void orp_i2p(tms7000_state *cpustate)
	2670	void tms7000_device::orp_i2p()
2671	2671	{
2672	2672	UINT8   t;
2673	2673	UINT8   i,v;
r26878	r26879
2681	2681	SET_N8(t);
2682	2682	SET_Z8(t);
2683	2683
2684		cpustate->icount -= 11;
	2684	m_icount -= 11;
2685	2685	}
2686	2686
2687		static void pop_a(tms7000_state *cpustate)
	2687	void tms7000_device::pop_a()
2688	2688	{
2689	2689	UINT16  t;
2690	2690
r26878	r26879
2695	2695	SET_N8(t);
2696	2696	SET_Z8(t);
2697	2697
2698		cpustate->icount -= 6;
	2698	m_icount -= 6;
2699	2699	}
2700	2700
2701		static void pop_b(tms7000_state *cpustate)
	2701	void tms7000_device::pop_b()
2702	2702	{
2703	2703	UINT16  t;
2704	2704
r26878	r26879
2709	2709	SET_N8(t);
2710	2710	SET_Z8(t);
2711	2711
2712		cpustate->icount -= 6;
	2712	m_icount -= 6;
2713	2713	}
2714	2714
2715		static void pop_r(tms7000_state *cpustate)
	2715	void tms7000_device::pop_r()
2716	2716	{
2717	2717	UINT16  t;
2718	2718	UINT8   r;
r26878	r26879
2725	2725	SET_N8(t);
2726	2726	SET_Z8(t);
2727	2727
2728		cpustate->icount -= 8;
	2728	m_icount -= 8;
2729	2729	}
2730	2730
2731		static void pop_st(tms7000_state *cpustate)
	2731	void tms7000_device::pop_st()
2732	2732	{
2733	2733	UINT16  t;
2734	2734
2735	2735	PULLBYTE(t);
2736	2736	pSR = t;
2737	2737
2738		cpustate->icount -= 6;
	2738	m_icount -= 6;
2739	2739	}
2740	2740
2741		static void push_a(tms7000_state *cpustate)
	2741	void tms7000_device::push_a()
2742	2742	{
2743	2743	UINT16  t;
2744	2744
r26878	r26879
2749	2749	SET_N8(t);
2750	2750	SET_Z8(t);
2751	2751
2752		cpustate->icount -= 6;
	2752	m_icount -= 6;
2753	2753	}
2754	2754
2755		static void push_b(tms7000_state *cpustate)
	2755	void tms7000_device::push_b()
2756	2756	{
2757	2757	UINT16  t;
2758	2758
r26878	r26879
2763	2763	SET_N8(t);
2764	2764	SET_Z8(t);
2765	2765
2766		cpustate->icount -= 6;
	2766	m_icount -= 6;
2767	2767	}
2768	2768
2769		static void push_r(tms7000_state *cpustate)
	2769	void tms7000_device::push_r()
2770	2770	{
2771	2771	UINT16  t;
2772	2772	INT8    r;
r26878	r26879
2779	2779	SET_N8(t);
2780	2780	SET_Z8(t);
2781	2781
2782		cpustate->icount -= 8;
	2782	m_icount -= 8;
2783	2783	}
2784	2784
2785		static void push_st(tms7000_state *cpustate)
	2785	void tms7000_device::push_st()
2786	2786	{
2787	2787	UINT16  t;
2788	2788	t = pSR;
2789	2789	PUSHBYTE(t);
2790	2790
2791		cpustate->icount -= 6;
	2791	m_icount -= 6;
2792	2792	}
2793	2793
2794		static void reti(tms7000_state *cpustate)
	2794	void tms7000_device::reti()
2795	2795	{
2796	2796	PULLWORD( PC );
2797	2797	PULLBYTE( pSR );
2798	2798
2799		cpustate->icount -= 9;
2800		tms7000_check_IRQ_lines(cpustate);
	2799	m_icount -= 9;
	2800	tms7000_check_IRQ_lines();
2801	2801	}
2802	2802
2803		static void rets(tms7000_state *cpustate)
	2803	void tms7000_device::rets()
2804	2804	{
2805	2805	PULLWORD( PC );
2806		cpustate->icount -= 7;
	2806	m_icount -= 7;
2807	2807	}
2808	2808
2809		static void rl_a(tms7000_state *cpustate)
	2809	void tms7000_device::rl_a()
2810	2810	{
2811	2811	UINT16  t;
2812	2812
r26878	r26879
2822	2822	SET_Z8(t);
2823	2823	WRA(t);
2824	2824
2825		cpustate->icount -= 5;
	2825	m_icount -= 5;
2826	2826	}
2827	2827
2828		static void rl_b(tms7000_state *cpustate)
	2828	void tms7000_device::rl_b()
2829	2829	{
2830	2830	UINT16  t;
2831	2831
r26878	r26879
2841	2841	SET_Z8(t);
2842	2842	WRB(t);
2843	2843
2844		cpustate->icount -= 5;
	2844	m_icount -= 5;
2845	2845	}
2846	2846
2847		static void rl_r(tms7000_state *cpustate)
	2847	void tms7000_device::rl_r()
2848	2848	{
2849	2849	UINT16  t;
2850	2850	UINT8   r;
r26878	r26879
2862	2862	SET_Z8(t);
2863	2863	WM(r,t);
2864	2864
2865		cpustate->icount -= 7;
	2865	m_icount -= 7;
2866	2866	}
2867	2867
2868		static void rlc_a(tms7000_state *cpustate)
	2868	void tms7000_device::rlc_a()
2869	2869	{
2870	2870	UINT16  t;
2871	2871	int     old_carry;
r26878	r26879
2884	2884	SET_Z8(t);
2885	2885	WRA(t);
2886	2886
2887		cpustate->icount -= 5;
	2887	m_icount -= 5;
2888	2888	}
2889	2889
2890		static void rlc_b(tms7000_state *cpustate)
	2890	void tms7000_device::rlc_b()
2891	2891	{
2892	2892	UINT16  t;
2893	2893	int     old_carry;
r26878	r26879
2906	2906	SET_Z8(t);
2907	2907	WRB(t);
2908	2908
2909		cpustate->icount -= 5;
	2909	m_icount -= 5;
2910	2910	}
2911	2911
2912		static void rlc_r(tms7000_state *cpustate)
	2912	void tms7000_device::rlc_r()
2913	2913	{
2914	2914	UINT16  t;
2915	2915	UINT8   r;
r26878	r26879
2930	2930	SET_Z8(t);
2931	2931	WM(r,t);
2932	2932
2933		cpustate->icount -= 7;
	2933	m_icount -= 7;
2934	2934	}
2935	2935
2936		static void rr_a(tms7000_state *cpustate)
	2936	void tms7000_device::rr_a()
2937	2937	{
2938	2938	UINT16  t;
2939	2939	int     old_bit0;
r26878	r26879
2956	2956
2957	2957	WRA(t);
2958	2958
2959		cpustate->icount -= 5;
	2959	m_icount -= 5;
2960	2960	}
2961	2961
2962		static void rr_b(tms7000_state *cpustate)
	2962	void tms7000_device::rr_b()
2963	2963	{
2964	2964	UINT16  t;
2965	2965	int     old_bit0;
r26878	r26879
2982	2982
2983	2983	WRB(t);
2984	2984
2985		cpustate->icount -= 5;
	2985	m_icount -= 5;
2986	2986	}
2987	2987
2988		static void rr_r(tms7000_state *cpustate)
	2988	void tms7000_device::rr_r()
2989	2989	{
2990	2990	UINT16  t;
2991	2991	UINT8   r;
r26878	r26879
3011	3011
3012	3012	WM(r,t);
3013	3013
3014		cpustate->icount -= 7;
	3014	m_icount -= 7;
3015	3015	}
3016	3016
3017		static void rrc_a(tms7000_state *cpustate)
	3017	void tms7000_device::rrc_a()
3018	3018	{
3019	3019	UINT16  t;
3020	3020	int     old_bit0;
r26878	r26879
3035	3035
3036	3036	WRA(t);
3037	3037
3038		cpustate->icount -= 5;
	3038	m_icount -= 5;
3039	3039	}
3040	3040
3041		static void rrc_b(tms7000_state *cpustate)
	3041	void tms7000_device::rrc_b()
3042	3042	{
3043	3043	UINT16  t;
3044	3044	int     old_bit0;
r26878	r26879
3059	3059
3060	3060	WRB(t);
3061	3061
3062		cpustate->icount -= 5;
	3062	m_icount -= 5;
3063	3063	}
3064	3064
3065		static void rrc_r(tms7000_state *cpustate)
	3065	void tms7000_device::rrc_r()
3066	3066	{
3067	3067	UINT16  t;
3068	3068	UINT8   r;
r26878	r26879
3085	3085
3086	3086	WM(r,t);
3087	3087
3088		cpustate->icount -= 7;
	3088	m_icount -= 7;
3089	3089	}
3090	3090
3091		static void sbb_ba(tms7000_state *cpustate)
	3091	void tms7000_device::sbb_ba()
3092	3092	{
3093	3093	UINT16  t;
3094	3094
r26878	r26879
3100	3100	SET_N8(t);
3101	3101	SET_Z8(t);
3102	3102
3103		cpustate->icount -= 5;
	3103	m_icount -= 5;
3104	3104	}
3105	3105
3106		static void sbb_ra(tms7000_state *cpustate)
	3106	void tms7000_device::sbb_ra()
3107	3107	{
3108	3108	UINT16  t;
3109	3109	UINT8   r;
r26878	r26879
3117	3117	SET_N8(t);
3118	3118	SET_Z8(t);
3119	3119
3120		cpustate->icount -= 8;
	3120	m_icount -= 8;
3121	3121	}
3122	3122
3123		static void sbb_rb(tms7000_state *cpustate)
	3123	void tms7000_device::sbb_rb()
3124	3124	{
3125	3125	UINT16  t;
3126	3126	UINT8   r;
r26878	r26879
3134	3134	SET_N8(t);
3135	3135	SET_Z8(t);
3136	3136
3137		cpustate->icount -= 8;
	3137	m_icount -= 8;
3138	3138	}
3139	3139
3140		static void sbb_rr(tms7000_state *cpustate)
	3140	void tms7000_device::sbb_rr()
3141	3141	{
3142	3142	UINT16  t;
3143	3143	UINT8   r,s;
r26878	r26879
3152	3152	SET_N8(t);
3153	3153	SET_Z8(t);
3154	3154
3155		cpustate->icount -= 10;
	3155	m_icount -= 10;
3156	3156	}
3157	3157
3158		static void sbb_ia(tms7000_state *cpustate)
	3158	void tms7000_device::sbb_ia()
3159	3159	{
3160	3160	UINT16  t;
3161	3161	UINT8   i;
r26878	r26879
3169	3169	SET_N8(t);
3170	3170	SET_Z8(t);
3171	3171
3172		cpustate->icount -= 7;
	3172	m_icount -= 7;
3173	3173	}
3174	3174
3175		static void sbb_ib(tms7000_state *cpustate)
	3175	void tms7000_device::sbb_ib()
3176	3176	{
3177	3177	UINT16  t;
3178	3178	UINT8   i;
r26878	r26879
3186	3186	SET_N8(t);
3187	3187	SET_Z8(t);
3188	3188
3189		cpustate->icount -= 7;
	3189	m_icount -= 7;
3190	3190	}
3191	3191
3192		static void sbb_ir(tms7000_state *cpustate)
	3192	void tms7000_device::sbb_ir()
3193	3193	{
3194	3194	UINT16  t;
3195	3195	UINT8   r,i;
r26878	r26879
3204	3204	SET_N8(t);
3205	3205	SET_Z8(t);
3206	3206
3207		cpustate->icount -= 9;
	3207	m_icount -= 9;
3208	3208	}
3209	3209
3210		static void setc(tms7000_state *cpustate)
	3210	void tms7000_device::setc()
3211	3211	{
3212	3212	CLR_NZC;
3213	3213	pSR |= (SR_C|SR_Z);
3214	3214
3215		cpustate->icount -= 5;
	3215	m_icount -= 5;
3216	3216	}
3217	3217
3218		static void sta_dir(tms7000_state *cpustate)
	3218	void tms7000_device::sta_dir()
3219	3219	{
3220	3220	UINT16  t;
3221	3221	PAIR    i;
r26878	r26879
3229	3229	SET_N8(t);
3230	3230	SET_Z8(t);
3231	3231
3232		cpustate->icount -= 11;
	3232	m_icount -= 11;
3233	3233	}
3234	3234
3235		static void sta_ind(tms7000_state *cpustate)
	3235	void tms7000_device::sta_ind()
3236	3236	{
3237	3237	UINT16  t;
3238	3238	PAIR    p;
3239	3239	INT8    r;
3240	3240
3241	3241	IMMBYTE(r);
3242		p.w.l = RRF16(cpustate,r);
	3242	p.w.l = RRF16(r);
3243	3243	t = RDA;
3244	3244	WM(p.w.l,t);
3245	3245
r26878	r26879
3247	3247	SET_N8(t);
3248	3248	SET_Z8(t);
3249	3249
3250		cpustate->icount -= 10;
	3250	m_icount -= 10;
3251	3251	}
3252	3252
3253		static void sta_inx(tms7000_state *cpustate)
	3253	void tms7000_device::sta_inx()
3254	3254	{
3255	3255	UINT16  t;
3256	3256	PAIR    i;
r26878	r26879
3263	3263	SET_N8(t);
3264	3264	SET_Z8(t);
3265	3265
3266		cpustate->icount -= 13;
	3266	m_icount -= 13;
3267	3267	}
3268	3268
3269		static void stsp(tms7000_state *cpustate)
	3269	void tms7000_device::stsp()
3270	3270	{
3271	3271	WRB(pSP);
3272	3272
3273		cpustate->icount -= 6;
	3273	m_icount -= 6;
3274	3274	}
3275	3275
3276		static void sub_ba(tms7000_state *cpustate)
	3276	void tms7000_device::sub_ba()
3277	3277	{
3278	3278	UINT16  t;
3279	3279
r26878	r26879
3285	3285	SET_N8(t);
3286	3286	SET_Z8(t);
3287	3287
3288		cpustate->icount -= 5;
	3288	m_icount -= 5;
3289	3289	}
3290	3290
3291		static void sub_ra(tms7000_state *cpustate)
	3291	void tms7000_device::sub_ra()
3292	3292	{
3293	3293	UINT16  t;
3294	3294	UINT8   r;
r26878	r26879
3302	3302	SET_N8(t);
3303	3303	SET_Z8(t);
3304	3304
3305		cpustate->icount -= 8;
	3305	m_icount -= 8;
3306	3306	}
3307	3307
3308		static void sub_rb(tms7000_state *cpustate)
	3308	void tms7000_device::sub_rb()
3309	3309	{
3310	3310	UINT16  t;
3311	3311	UINT8   r;
r26878	r26879
3319	3319	SET_N8(t);
3320	3320	SET_Z8(t);
3321	3321
3322		cpustate->icount -= 8;
	3322	m_icount -= 8;
3323	3323	}
3324	3324
3325		static void sub_rr(tms7000_state *cpustate)
	3325	void tms7000_device::sub_rr()
3326	3326	{
3327	3327	UINT16  t;
3328	3328	UINT8   r,s;
r26878	r26879
3337	3337	SET_N8(t);
3338	3338	SET_Z8(t);
3339	3339
3340		cpustate->icount -= 10;
	3340	m_icount -= 10;
3341	3341	}
3342	3342
3343		static void sub_ia(tms7000_state *cpustate)
	3343	void tms7000_device::sub_ia()
3344	3344	{
3345	3345	UINT16  t;
3346	3346	UINT8   i;
r26878	r26879
3354	3354	SET_N8(t);
3355	3355	SET_Z8(t);
3356	3356
3357		cpustate->icount -= 7;
	3357	m_icount -= 7;
3358	3358	}
3359	3359
3360		static void sub_ib(tms7000_state *cpustate)
	3360	void tms7000_device::sub_ib()
3361	3361	{
3362	3362	UINT16  t;
3363	3363	UINT8   i;
r26878	r26879
3371	3371	SET_N8(t);
3372	3372	SET_Z8(t);
3373	3373
3374		cpustate->icount -= 7;
	3374	m_icount -= 7;
3375	3375	}
3376	3376
3377		static void sub_ir(tms7000_state *cpustate)
	3377	void tms7000_device::sub_ir()
3378	3378	{
3379	3379	UINT16  t;
3380	3380	UINT8   r,i;
r26878	r26879
3389	3389	SET_N8(t);
3390	3390	SET_Z8(t);
3391	3391
3392		cpustate->icount -= 9;
	3392	m_icount -= 9;
3393	3393	}
3394	3394
3395		static void trap_0(tms7000_state *cpustate)
	3395	void tms7000_device::trap_0()
3396	3396	{
3397	3397	PUSHWORD( PC );
3398		pPC = RM16(cpustate, 0xfffe);
3399		cpustate->icount -= 14;
	3398	pPC = RM16(0xfffe);
	3399	m_icount -= 14;
3400	3400	}
3401	3401
3402		static void trap_1(tms7000_state *cpustate)
	3402	void tms7000_device::trap_1()
3403	3403	{
3404	3404	PUSHWORD( PC );
3405		pPC = RM16(cpustate, 0xfffc);
3406		cpustate->icount -= 14;
	3405	pPC = RM16(0xfffc);
	3406	m_icount -= 14;
3407	3407	}
3408	3408
3409		static void trap_2(tms7000_state *cpustate)
	3409	void tms7000_device::trap_2()
3410	3410	{
3411	3411	PUSHWORD( PC );
3412		pPC = RM16(cpustate, 0xfffa);
3413		cpustate->icount -= 14;
	3412	pPC = RM16(0xfffa);
	3413	m_icount -= 14;
3414	3414	}
3415	3415
3416		static void trap_3(tms7000_state *cpustate)
	3416	void tms7000_device::trap_3()
3417	3417	{
3418	3418	PUSHWORD( PC );
3419		pPC = RM16(cpustate, 0xfff8);
3420		cpustate->icount -= 14;
	3419	pPC = RM16(0xfff8);
	3420	m_icount -= 14;
3421	3421	}
3422	3422
3423		static void trap_4(tms7000_state *cpustate)
	3423	void tms7000_device::trap_4()
3424	3424	{
3425	3425	PUSHWORD( PC );
3426		pPC = RM16(cpustate, 0xfff6);
3427		cpustate->icount -= 14;
	3426	pPC = RM16(0xfff6);
	3427	m_icount -= 14;
3428	3428	}
3429	3429
3430		static void trap_5(tms7000_state *cpustate)
	3430	void tms7000_device::trap_5()
3431	3431	{
3432	3432	PUSHWORD( PC );
3433		pPC = RM16(cpustate, 0xfff4);
3434		cpustate->icount -= 14;
	3433	pPC = RM16(0xfff4);
	3434	m_icount -= 14;
3435	3435	}
3436	3436
3437		static void trap_6(tms7000_state *cpustate)
	3437	void tms7000_device::trap_6()
3438	3438	{
3439	3439	PUSHWORD( PC );
3440		pPC = RM16(cpustate, 0xfff2);
3441		cpustate->icount -= 14;
	3440	pPC = RM16(0xfff2);
	3441	m_icount -= 14;
3442	3442	}
3443	3443
3444		static void trap_7(tms7000_state *cpustate)
	3444	void tms7000_device::trap_7()
3445	3445	{
3446	3446	PUSHWORD( PC );
3447		pPC = RM16(cpustate, 0xfff0);
3448		cpustate->icount -= 14;
	3447	pPC = RM16(0xfff0);
	3448	m_icount -= 14;
3449	3449	}
3450	3450
3451		static void trap_8(tms7000_state *cpustate)
	3451	void tms7000_device::trap_8()
3452	3452	{
3453	3453	PUSHWORD( PC );
3454		pPC = RM16(cpustate, 0xffee);
3455		cpustate->icount -= 14;
	3454	pPC = RM16(0xffee);
	3455	m_icount -= 14;
3456	3456	}
3457	3457
3458		static void trap_9(tms7000_state *cpustate)
	3458	void tms7000_device::trap_9()
3459	3459	{
3460	3460	PUSHWORD( PC );
3461		pPC = RM16(cpustate, 0xffec);
3462		cpustate->icount -= 14;
	3461	pPC = RM16(0xffec);
	3462	m_icount -= 14;
3463	3463	}
3464	3464
3465		static void trap_10(tms7000_state *cpustate)
	3465	void tms7000_device::trap_10()
3466	3466	{
3467	3467	PUSHWORD( PC );
3468		pPC = RM16(cpustate, 0xffea);
3469		cpustate->icount -= 14;
	3468	pPC = RM16(0xffea);
	3469	m_icount -= 14;
3470	3470	}
3471	3471
3472		static void trap_11(tms7000_state *cpustate)
	3472	void tms7000_device::trap_11()
3473	3473	{
3474	3474	PUSHWORD( PC );
3475		pPC = RM16(cpustate, 0xffe8);
3476		cpustate->icount -= 14;
	3475	pPC = RM16(0xffe8);
	3476	m_icount -= 14;
3477	3477	}
3478	3478
3479		static void trap_12(tms7000_state *cpustate)
	3479	void tms7000_device::trap_12()
3480	3480	{
3481	3481	PUSHWORD( PC );
3482		pPC = RM16(cpustate, 0xffe6);
3483		cpustate->icount -= 14;
	3482	pPC = RM16(0xffe6);
	3483	m_icount -= 14;
3484	3484	}
3485	3485
3486		static void trap_13(tms7000_state *cpustate)
	3486	void tms7000_device::trap_13()
3487	3487	{
3488	3488	PUSHWORD( PC );
3489		pPC = RM16(cpustate, 0xffe4);
3490		cpustate->icount -= 14;
	3489	pPC = RM16(0xffe4);
	3490	m_icount -= 14;
3491	3491	}
3492	3492
3493		static void trap_14(tms7000_state *cpustate)
	3493	void tms7000_device::trap_14()
3494	3494	{
3495	3495	PUSHWORD( PC );
3496		pPC = RM16(cpustate, 0xffe2);
3497		cpustate->icount -= 14;
	3496	pPC = RM16(0xffe2);
	3497	m_icount -= 14;
3498	3498	}
3499	3499
3500		static void trap_15(tms7000_state *cpustate)
	3500	void tms7000_device::trap_15()
3501	3501	{
3502	3502	PUSHWORD( PC );
3503		pPC = RM16(cpustate, 0xffe0);
3504		cpustate->icount -= 14;
	3503	pPC = RM16(0xffe0);
	3504	m_icount -= 14;
3505	3505	}
3506	3506
3507		static void trap_16(tms7000_state *cpustate)
	3507	void tms7000_device::trap_16()
3508	3508	{
3509	3509	PUSHWORD( PC );
3510		pPC = RM16(cpustate, 0xffde);
3511		cpustate->icount -= 14;
	3510	pPC = RM16(0xffde);
	3511	m_icount -= 14;
3512	3512	}
3513	3513
3514		static void trap_17(tms7000_state *cpustate)
	3514	void tms7000_device::trap_17()
3515	3515	{
3516	3516	PUSHWORD( PC );
3517		pPC = RM16(cpustate, 0xffdc);
3518		cpustate->icount -= 14;
	3517	pPC = RM16(0xffdc);
	3518	m_icount -= 14;
3519	3519	}
3520	3520
3521		static void trap_18(tms7000_state *cpustate)
	3521	void tms7000_device::trap_18()
3522	3522	{
3523	3523	PUSHWORD( PC );
3524		pPC = RM16(cpustate, 0xffda);
3525		cpustate->icount -= 14;
	3524	pPC = RM16(0xffda);
	3525	m_icount -= 14;
3526	3526	}
3527	3527
3528		static void trap_19(tms7000_state *cpustate)
	3528	void tms7000_device::trap_19()
3529	3529	{
3530	3530	PUSHWORD( PC );
3531		pPC = RM16(cpustate, 0xffd8);
3532		cpustate->icount -= 14;
	3531	pPC = RM16(0xffd8);
	3532	m_icount -= 14;
3533	3533	}
3534	3534
3535		static void trap_20(tms7000_state *cpustate)
	3535	void tms7000_device::trap_20()
3536	3536	{
3537	3537	PUSHWORD( PC );
3538		pPC = RM16(cpustate, 0xffd6);
3539		cpustate->icount -= 14;
	3538	pPC = RM16(0xffd6);
	3539	m_icount -= 14;
3540	3540	}
3541	3541
3542		static void trap_21(tms7000_state *cpustate)
	3542	void tms7000_device::trap_21()
3543	3543	{
3544	3544	PUSHWORD( PC );
3545		pPC = RM16(cpustate, 0xffd4);
3546		cpustate->icount -= 14;
	3545	pPC = RM16(0xffd4);
	3546	m_icount -= 14;
3547	3547	}
3548	3548
3549		static void trap_22(tms7000_state *cpustate)
	3549	void tms7000_device::trap_22()
3550	3550	{
3551	3551	PUSHWORD( PC );
3552		pPC = RM16(cpustate, 0xffd2);
3553		cpustate->icount -= 14;
	3552	pPC = RM16(0xffd2);
	3553	m_icount -= 14;
3554	3554	}
3555	3555
3556		static void trap_23(tms7000_state *cpustate)
	3556	void tms7000_device::trap_23()
3557	3557	{
3558	3558	PUSHWORD( PC );
3559		pPC = RM16(cpustate, 0xffd0);
3560		cpustate->icount -= 14;
	3559	pPC = RM16(0xffd0);
	3560	m_icount -= 14;
3561	3561	}
3562	3562
3563		static void swap_a(tms7000_state *cpustate)
	3563	void tms7000_device::swap_a()
3564	3564	{
3565	3565	UINT8   a,b;
3566	3566	UINT16  t;
r26878	r26879
3579	3579	SET_N8(t);
3580	3580	SET_Z8(t);
3581	3581
3582		cpustate->icount -=8;
	3582	m_icount -=8;
3583	3583	}
3584	3584
3585		static void swap_b(tms7000_state *cpustate)
	3585	void tms7000_device::swap_b()
3586	3586	{
3587	3587	UINT8   a,b;
3588	3588	UINT16  t;
r26878	r26879
3601	3601	SET_N8(t);
3602	3602	SET_Z8(t);
3603	3603
3604		cpustate->icount -=8;
	3604	m_icount -=8;
3605	3605	}
3606	3606
3607		static void swap_r(tms7000_state *cpustate)
	3607	void tms7000_device::swap_r()
3608	3608	{
3609	3609	UINT8   a,b,r;
3610	3610	UINT16  t;
r26878	r26879
3624	3624	SET_N8(t);
3625	3625	SET_Z8(t);
3626	3626
3627		cpustate->icount -=8;
	3627	m_icount -=8;
3628	3628	}
3629	3629
3630		static void swap_r_exl(tms7000_state *cpustate)
	3630	void tms7000_device::swap_r_exl()
3631	3631	{
3632	3632	UINT8   a,b,r;
3633	3633	UINT16  t;
r26878	r26879
3645	3645	SET_N8(t);
3646	3646	SET_Z8(t);
3647	3647
3648		cpustate->icount -= 9;  /* ?????? */
	3648	m_icount -= 9;  /* ?????? */
3649	3649	}
3650	3650	else
3651	3651	{   /* stright swap Rn instruction */
r26878	r26879
3663	3663	SET_N8(t);
3664	3664	SET_Z8(t);
3665	3665
3666		cpustate->icount -=8;
	3666	m_icount -=8;
3667	3667	}
3668	3668	}
3669	3669
3670		static void tstb(tms7000_state *cpustate)
	3670	void tms7000_device::tstb()
3671	3671	{
3672	3672	UINT16  t;
3673	3673
r26878	r26879
3677	3677	SET_N8(t);
3678	3678	SET_Z8(t);
3679	3679
3680		cpustate->icount -= 6;
	3680	m_icount -= 6;
3681	3681	}
3682	3682
3683		static void xchb_a(tms7000_state *cpustate)
	3683	void tms7000_device::xchb_a()
3684	3684	{
3685	3685	UINT16  t,u;
3686	3686
r26878	r26879
3694	3694	SET_N8(t);
3695	3695	SET_Z8(t);
3696	3696
3697		cpustate->icount -= 6;
	3697	m_icount -= 6;
3698	3698	}
3699	3699
3700		static void xchb_b(tms7000_state *cpustate)
	3700	void tms7000_device::xchb_b()
3701	3701	{
3702	3702	UINT16  t;
3703	3703	/*  UINT16  u;  */
r26878	r26879
3712	3712	SET_N8(t);
3713	3713	SET_Z8(t);
3714	3714
3715		cpustate->icount -= 6;
	3715	m_icount -= 6;
3716	3716	}
3717	3717
3718		static void xchb_r(tms7000_state *cpustate)
	3718	void tms7000_device::xchb_r()
3719	3719	{
3720	3720	UINT16  t,u;
3721	3721	UINT8   r;
r26878	r26879
3732	3732	SET_N8(t);
3733	3733	SET_Z8(t);
3734	3734
3735		cpustate->icount -= 8;
	3735	m_icount -= 8;
3736	3736	}
3737	3737
3738		static void xor_b2a(tms7000_state *cpustate)
	3738	void tms7000_device::xor_b2a()
3739	3739	{
3740	3740	UINT8   t;
3741	3741
r26878	r26879
3746	3746	SET_N8(t);
3747	3747	SET_Z8(t);
3748	3748
3749		cpustate->icount -= 5;
	3749	m_icount -= 5;
3750	3750	}
3751	3751
3752		static void xor_r2a(tms7000_state *cpustate)
	3752	void tms7000_device::xor_r2a()
3753	3753	{
3754	3754	UINT8   t;
3755	3755	UINT8   v;
r26878	r26879
3763	3763	SET_N8(t);
3764	3764	SET_Z8(t);
3765	3765
3766		cpustate->icount -= 8;
	3766	m_icount -= 8;
3767	3767	}
3768	3768
3769		static void xor_r2b(tms7000_state *cpustate)
	3769	void tms7000_device::xor_r2b()
3770	3770	{
3771	3771	UINT8   t;
3772	3772	UINT8   v;
r26878	r26879
3780	3780	SET_N8(t);
3781	3781	SET_Z8(t);
3782	3782
3783		cpustate->icount -= 8;
	3783	m_icount -= 8;
3784	3784	}
3785	3785
3786		static void xor_r2r(tms7000_state *cpustate)
	3786	void tms7000_device::xor_r2r()
3787	3787	{
3788	3788	UINT8   t;
3789	3789	UINT8   i,j;
r26878	r26879
3798	3798	SET_N8(t);
3799	3799	SET_Z8(t);
3800	3800
3801		cpustate->icount -= 10;
	3801	m_icount -= 10;
3802	3802	}
3803	3803
3804		static void xor_i2a(tms7000_state *cpustate)
	3804	void tms7000_device::xor_i2a()
3805	3805	{
3806	3806	UINT8   t;
3807	3807	UINT8   v;
r26878	r26879
3815	3815	SET_N8(t);
3816	3816	SET_Z8(t);
3817	3817
3818		cpustate->icount -= 7;
	3818	m_icount -= 7;
3819	3819	}
3820	3820
3821		static void xor_i2b(tms7000_state *cpustate)
	3821	void tms7000_device::xor_i2b()
3822	3822	{
3823	3823	UINT8   t;
3824	3824	UINT8   v;
r26878	r26879
3832	3832	SET_N8(t);
3833	3833	SET_Z8(t);
3834	3834
3835		cpustate->icount -= 7;
	3835	m_icount -= 7;
3836	3836	}
3837	3837
3838		static void xor_i2r(tms7000_state *cpustate)
	3838	void tms7000_device::xor_i2r()
3839	3839	{
3840	3840	UINT8   t;
3841	3841	UINT8   i,j;
r26878	r26879
3850	3850	SET_N8(t);
3851	3851	SET_Z8(t);
3852	3852
3853		cpustate->icount -= 9;
	3853	m_icount -= 9;
3854	3854	}
3855	3855
3856		static void xorp_a2p(tms7000_state *cpustate)
	3856	void tms7000_device::xorp_a2p()
3857	3857	{
3858	3858	UINT8   t;
3859	3859	UINT8   v;
r26878	r26879
3866	3866	SET_N8(t);
3867	3867	SET_Z8(t);
3868	3868
3869		cpustate->icount -= 10;
	3869	m_icount -= 10;
3870	3870	}
3871	3871
3872		static void xorp_b2p(tms7000_state *cpustate)
	3872	void tms7000_device::xorp_b2p()
3873	3873	{
3874	3874	UINT8   t;
3875	3875	UINT8   v;
r26878	r26879
3882	3882	SET_N8(t);
3883	3883	SET_Z8(t);
3884	3884
3885		cpustate->icount -= 9;
	3885	m_icount -= 9;
3886	3886	}
3887	3887
3888		static void xorp_i2p(tms7000_state *cpustate)
	3888	void tms7000_device::xorp_i2p()
3889	3889	{
3890	3890	UINT8   t;
3891	3891	UINT8   i,v;
r26878	r26879
3899	3899	SET_N8(t);
3900	3900	SET_Z8(t);
3901	3901
3902		cpustate->icount -= 11;
	3902	m_icount -= 11;
3903	3903	}

trunk/src/emu/cpu/tms7000/tms7000.c

r26878	r26879
36	36
37	37	#define LOG(x)  do { if (VERBOSE) logerror x; } while (0)
38	38
39		struct tms7000_state;
40	39
41		/* Private prototypes */
42
43		static void tms7000_set_irq_line(tms7000_state *cpustate, int irqline, int state);
44		static void tms7000_check_IRQ_lines(tms7000_state *cpustate);
45		static void tms7000_do_interrupt( tms7000_state *cpustate, UINT16 address, UINT8 line );
46		static CPU_EXECUTE( tms7000 );
47		static CPU_EXECUTE( tms7000_exl );
48		static void tms7000_service_timer1( device_t *device );
49		static UINT16 bcd_add( UINT16 a, UINT16 b );
50		static UINT16 bcd_tencomp( UINT16 a );
51		static UINT16 bcd_sub( UINT16 a, UINT16 b);
52
53	40	/* Static variables */
54	41
55		#define RM(Addr) ((unsigned)cpustate->program->read_byte(Addr))
56		#define WM(Addr,Value) (cpustate->program->write_byte(Addr, Value))
	42	#define RM(Addr) ((unsigned)m_program->read_byte(Addr))
	43	#define WM(Addr,Value) (m_program->write_byte(Addr, Value))
57	44
58		#define IMMBYTE(b)  b = ((unsigned)cpustate->direct->read_raw_byte(pPC)); pPC++
59		#define SIMMBYTE(b) b = ((signed)cpustate->direct->read_raw_byte(pPC)); pPC++
60		#define IMMWORD(w)  w.b.h = (unsigned)cpustate->direct->read_raw_byte(pPC++); w.b.l = (unsigned)cpustate->direct->read_raw_byte(pPC++)
	45	#define IMMBYTE(b)  b = ((unsigned)m_direct->read_raw_byte(pPC)); pPC++
	46	#define SIMMBYTE(b) b = ((signed)m_direct->read_raw_byte(pPC)); pPC++
	47	#define IMMWORD(w)  w.b.h = (unsigned)m_direct->read_raw_byte(pPC++); w.b.l = (unsigned)m_direct->read_raw_byte(pPC++)
61	48
62	49	#define PUSHBYTE(b) pSP++; WM(pSP,b)
63	50	#define PUSHWORD(w) pSP++; WM(pSP,w.b.h); pSP++; WM(pSP,w.b.l)
64	51	#define PULLBYTE(b) b = RM(pSP); pSP--
65	52	#define PULLWORD(w) w.b.l = RM(pSP); pSP--; w.b.h = RM(pSP); pSP--
66	53
67		struct tms7000_state
	54
	55	const device_type TMS7000 = &device_creator<tms7000_device>;
	56	const device_type TMS7000_EXL = &device_creator<tms7000_exl_device>;
	57
	58
	59	static ADDRESS_MAP_START(tms7000_mem, AS_PROGRAM, 8, tms7000_device )
	60	AM_RANGE(0x0000, 0x007f)    AM_READWRITE(tms7000_internal_r, tms7000_internal_w) /* tms7000 internal RAM */
	61	AM_RANGE(0x0080, 0x00ff)    AM_NOP                      /* reserved */
	62	AM_RANGE(0x0100, 0x01ff)    AM_READWRITE(tms70x0_pf_r, tms70x0_pf_w)             /* tms7000 internal I/O ports */
	63	ADDRESS_MAP_END
	64
	65
	66	tms7000_device::tms7000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	67	: cpu_device(mconfig, TMS7000, "TMS7000", tag, owner, clock, "tms7000", __FILE__)
	68	, m_program_config("program", ENDIANNESS_BIG, 8, 16, 0, ADDRESS_MAP_NAME(tms7000_mem))
	69	, m_io_config("io", ENDIANNESS_BIG, 8, 8, 0)
	70	, m_opcode(s_opfn)
68	71	{
69		PAIR        pc;         /* Program counter */
70		UINT8       sp;     /* Stack Pointer */
71		UINT8       sr;     /* Status Register */
72		UINT8       irq_state[3];   /* State of the three IRQs */
73		UINT8       rf[0x80];   /* Register file (SJE) */
74		UINT8       pf[0x100];  /* Perpherial file */
75		device_irq_acknowledge_callback irq_callback;
76		legacy_cpu_device *device;
77		address_space *program;
78		direct_read_data *direct;
79		address_space *io;
80		int         icount;
81		int         div_by_16_trigger;
82		int         cycles_per_INT2;
83		UINT8       t1_capture_latch; /* Timer 1 capture latch */
84		INT8        t1_prescaler;   /* Timer 1 prescaler (5 bits) */
85		INT16       t1_decrementer; /* Timer 1 decrementer (8 bits) */
86		UINT8       idle_state; /* Set after the execution of an idle instruction */
87		};
	72	}
88	73
89		INLINE tms7000_state *get_safe_token(device_t *device)
	74
	75	tms7000_device::tms7000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
	76	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
	77	, m_program_config("program", ENDIANNESS_BIG, 8, 16, 0, ADDRESS_MAP_NAME(tms7000_mem))
	78	, m_io_config("io", ENDIANNESS_BIG, 8, 8, 0)
	79	, m_opcode(s_opfn_exl)
90	80	{
91		assert(device != NULL);
92		assert(device->type() == TMS7000 ||
93		device->type() == TMS7000_EXL);
94		return (tms7000_state *)downcast<legacy_cpu_device *>(device)->token();
95	81	}
96	82
97		#define pPC     cpustate->pc.w.l
98		#define PC      cpustate->pc
99		#define pSP     cpustate->sp
100		#define pSR     cpustate->sr
101	83
	84	tms7000_exl_device::tms7000_exl_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	85	: tms7000_device(mconfig, TMS7000_EXL, "TMS7000_EXL", tag, owner, clock, "tms7000_exl", __FILE__)
	86	{
	87	}
	88
	89
	90	offs_t tms7000_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
	91	{
	92	extern CPU_DISASSEMBLE( tms7000 );
	93	return CPU_DISASSEMBLE_NAME(tms7000)(this, buffer, pc, oprom, opram, options);
	94	}
	95
	96
	97	#define pPC     m_pc.w.l
	98	#define PC      m_pc
	99	#define pSP     m_sp
	100	#define pSR     m_sr
	101
102	102	#define RDA     RM(0x0000)
103	103	#define RDB     RM(0x0001)
104	104
r26878	r26879
126	126	#define SETZ        pSR |= SR_Z
127	127	#define SETN        pSR |= SR_N
128	128
129		static DECLARE_READ8_HANDLER( tms7000_internal_r );
130		static DECLARE_WRITE8_HANDLER( tms7000_internal_w );
131		static DECLARE_READ8_HANDLER( tms70x0_pf_r );
132		static DECLARE_WRITE8_HANDLER( tms70x0_pf_w );
133	129
134		static ADDRESS_MAP_START(tms7000_mem, AS_PROGRAM, 8, legacy_cpu_device )
135		AM_RANGE(0x0000, 0x007f)    AM_READWRITE_LEGACY(tms7000_internal_r, tms7000_internal_w) /* tms7000 internal RAM */
136		AM_RANGE(0x0080, 0x00ff)    AM_NOP                      /* reserved */
137		AM_RANGE(0x0100, 0x01ff)    AM_READWRITE_LEGACY(tms70x0_pf_r, tms70x0_pf_w)             /* tms7000 internal I/O ports */
138		ADDRESS_MAP_END
139
140
141		INLINE UINT16 RM16( tms7000_state *cpustate, UINT32 mAddr ) /* Read memory (16-bit) */
	130	UINT16 tms7000_device::RM16( UINT32 mAddr ) /* Read memory (16-bit) */
142	131	{
143	132	UINT32 result = RM(mAddr) << 8;
144	133	return result | RM((mAddr+1)&0xffff);
145	134	}
146	135
147		INLINE UINT16 RRF16( tms7000_state *cpustate, UINT32 mAddr )    /*Read register file (16 bit) */
	136	UINT16 tms7000_device::RRF16( UINT32 mAddr )    /*Read register file (16 bit) */
148	137	{
149	138	PAIR result;
150	139	result.b.h = RM((mAddr-1)&0xffff);
r26878	r26879
152	141	return result.w.l;
153	142	}
154	143
155		INLINE void WRF16( tms7000_state *cpustate, UINT32 mAddr, PAIR p )  /*Write register file (16 bit) */
	144	void tms7000_device::WRF16( UINT32 mAddr, PAIR p )  /*Write register file (16 bit) */
156	145	{
157	146	WM( (mAddr-1)&0xffff, p.b.h );
158	147	WM( mAddr, p.b.l );
159	148	}
160	149
161	150
162		static CPU_INIT( tms7000 )
	151	void tms7000_device::device_start()
163	152	{
164		tms7000_state *cpustate = get_safe_token(device);
	153	m_program = &space(AS_PROGRAM);
	154	m_direct = &m_program->direct();
	155	m_io = &space(AS_IO);
165	156
166		cpustate->irq_callback = irqcallback;
167		cpustate->device = device;
168		cpustate->program = &device->space(AS_PROGRAM);
169		cpustate->direct = &cpustate->program->direct();
170		cpustate->io = &device->space(AS_IO);
	157	memset(m_pf, 0, 0x100);
	158	memset(m_rf, 0, 0x80);
	159	m_cycles_per_INT2 = 0;
	160	m_t1_capture_latch = 0;
	161	m_t1_prescaler = 0;
	162	m_t1_decrementer = 0;
171	163
172		memset(cpustate->pf, 0, 0x100);
173		memset(cpustate->rf, 0, 0x80);
174
175	164	/* Save register state */
176		device->save_item(NAME(pPC));
177		device->save_item(NAME(pSP));
178		device->save_item(NAME(pSR));
	165	save_item(NAME(pPC));
	166	save_item(NAME(pSP));
	167	save_item(NAME(pSR));
179	168
180	169	/* Save Interrupt state */
181		device->save_item(NAME(cpustate->irq_state));
	170	save_item(NAME(m_irq_state));
182	171
183	172	/* Save register and perpherial file state */
184		device->save_item(NAME(cpustate->rf));
185		device->save_item(NAME(cpustate->pf));
	173	save_item(NAME(m_rf));
	174	save_item(NAME(m_pf));
186	175
187	176	/* Save timer state */
188		device->save_item(NAME(cpustate->t1_prescaler));
189		device->save_item(NAME(cpustate->t1_capture_latch));
190		device->save_item(NAME(cpustate->t1_decrementer));
	177	save_item(NAME(m_t1_prescaler));
	178	save_item(NAME(m_t1_capture_latch));
	179	save_item(NAME(m_t1_decrementer));
191	180
192		device->save_item(NAME(cpustate->idle_state));
	181	save_item(NAME(m_idle_state));
	182
	183	state_add( TMS7000_PC,     "PC",    m_pc.w.l).formatstr("%04X");
	184	state_add( TMS7000_SP,     "S",     m_sp).formatstr("%02X");
	185	state_add( TMS7000_ST,     "ST",    m_sr).formatstr("%02X");
	186	state_add( TMS7000_IDLE,   "Idle",  m_idle_state).formatstr("%02X");
	187	state_add( TMS7000_T1_CL,  "T1CL",  m_t1_capture_latch).formatstr("%02X");
	188	state_add( TMS7000_T1_PS,  "T1PS",  m_t1_prescaler).mask(0x1f).formatstr("%02X");
	189	state_add( TMS7000_T1_DEC, "T1DEC", m_t1_decrementer).mask(0xff).formatstr("%02X");
	190
	191	state_add(STATE_GENPC, "GENPC", m_pc.w.l).formatstr("%04X").noshow();
	192	state_add(STATE_GENSP, "GENSP", m_sp).formatstr("%02X").noshow();
	193	state_add(STATE_GENFLAGS, "GENFLAGS",  m_sr).formatstr("%8s").noshow();
	194
	195	m_icountptr = &m_icount;
193	196	}
194	197
195		static CPU_RESET( tms7000 )
	198	void tms7000_device::state_string_export(const device_state_entry &entry, astring &string)
196	199	{
197		tms7000_state *cpustate = get_safe_token(device);
	200	switch (entry.index())
	201	{
	202	case STATE_GENFLAGS:
	203	string.printf("%c%c%c%c%c%c%c%c",
	204	m_sr & 0x80 ? 'C':'c',
	205	m_sr & 0x40 ? 'N':'n',
	206	m_sr & 0x20 ? 'Z':'z',
	207	m_sr & 0x10 ? 'I':'i',
	208	m_sr & 0x08 ? '?':'.',
	209	m_sr & 0x04 ? '?':'.',
	210	m_sr & 0x02 ? '?':'.',
	211	m_sr & 0x01 ? '?':'.'
	212	);
	213	break;
	214	}
	215	}
198	216
199		//  cpustate->architecture = (int)param;
	217	void tms7000_device::device_reset()
	218	{
	219	//  m_architecture = (int)param;
200	220
201		cpustate->idle_state = 0;
202		cpustate->irq_state[ TMS7000_IRQ1_LINE ] = CLEAR_LINE;
203		cpustate->irq_state[ TMS7000_IRQ2_LINE ] = CLEAR_LINE;
204		cpustate->irq_state[ TMS7000_IRQ3_LINE ] = CLEAR_LINE;
	221	m_idle_state = 0;
	222	m_irq_state[ TMS7000_IRQ1_LINE ] = CLEAR_LINE;
	223	m_irq_state[ TMS7000_IRQ2_LINE ] = CLEAR_LINE;
	224	m_irq_state[ TMS7000_IRQ3_LINE ] = CLEAR_LINE;
205	225
206	226	WM( 0x100 + 9, 0 );     /* Data direction regs are cleared */
207	227	WM( 0x100 + 11, 0 );
208	228
209		//  if( cpustate->architecture == TMS7000_NMOS )
	229	//  if( m_architecture == TMS7000_NMOS )
210	230	//  {
211	231	WM( 0x100 + 4, 0xff );      /* Output 0xff on port A */
212	232	WM( 0x100 + 8, 0xff );      /* Output 0xff on port C */
r26878	r26879
223	243
224	244	/* On TMS70x2 and TMS70Cx2 IOCNT1 is zero */
225	245
226		WRA( cpustate->pc.b.h );    /* Write previous PC to A:B */
227		WRB( cpustate->pc.b.l );
228		pPC = RM16(cpustate, 0xfffe);       /* Load reset vector */
	246	WRA( m_pc.b.h );    /* Write previous PC to A:B */
	247	WRB( m_pc.b.l );
	248	pPC = RM16(0xfffe);       /* Load reset vector */
229	249
230		cpustate->div_by_16_trigger = -16;
	250	m_div_by_16_trigger = -16;
231	251	}
232	252
233
234
235		/**************************************************************************
236		* Generic set_info
237		**************************************************************************/
238
239		static CPU_SET_INFO( tms7000 )
	253	void tms7000_device::execute_set_input(int irqline, int state)
240	254	{
241		tms7000_state *cpustate = get_safe_token(device);
242
243		switch (state)
244		{
245		/* --- the following bits of info are set as 64-bit signed integers --- */
246		case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE:   tms7000_set_irq_line(cpustate, TMS7000_IRQ1_LINE, info->i); break;
247		case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE:   tms7000_set_irq_line(cpustate, TMS7000_IRQ2_LINE, info->i); break;
248		case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE:   tms7000_set_irq_line(cpustate, TMS7000_IRQ3_LINE, info->i); break;
249
250		case CPUINFO_INT_PC:
251		case CPUINFO_INT_REGISTER + TMS7000_PC: pPC = info->i; break;
252		case CPUINFO_INT_SP:
253		case CPUINFO_INT_REGISTER + TMS7000_SP: pSP = info->i;  break;
254		case CPUINFO_INT_REGISTER + TMS7000_ST: pSR = info->i;  tms7000_check_IRQ_lines(cpustate);  break;
255		case CPUINFO_INT_REGISTER + TMS7000_IDLE: cpustate->idle_state = info->i;   break;
256		case CPUINFO_INT_REGISTER + TMS7000_T1_CL: cpustate->t1_capture_latch = info->i;    break;
257		case CPUINFO_INT_REGISTER + TMS7000_T1_PS: cpustate->t1_prescaler = info->i;    break;
258		case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: cpustate->t1_decrementer = info->i; break;
259		}
260		}
261
262		/**************************************************************************
263		* Generic get_info
264		**************************************************************************/
265
266		CPU_GET_INFO( tms7000 )
267		{
268		tms7000_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
269
270		switch( state )
271		{
272		/* --- the following bits of info are returned as 64-bit signed integers --- */
273		case CPUINFO_INT_CONTEXT_SIZE:  info->i = sizeof(tms7000_state);    break;
274		case CPUINFO_INT_INPUT_LINES:   info->i = 3;    break;
275		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:    info->i = 0;    break;
276		case CPUINFO_INT_ENDIANNESS:    info->i = ENDIANNESS_BIG;   break;
277		case CPUINFO_INT_CLOCK_MULTIPLIER:  info->i = 1;    break;
278		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1;    break;
279		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1;    break;
280		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4;    break;
281		case CPUINFO_INT_MIN_CYCLES:    info->i = 1;    break;
282		case CPUINFO_INT_MAX_CYCLES:    info->i = 48;   break; /* 48 represents the multiply instruction, the next highest is 17 */
283
284		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 8;    break;
285		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM:    info->i = 16;   break;
286		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM:    info->i = 0;    break;
287		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;    break;
288		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;    break;
289		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;    break;
290		case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8;    break;
291		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8;    break;
292		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0;    break;
293
294		case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE:   info->i = cpustate->irq_state[TMS7000_IRQ1_LINE]; break;
295		case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE:   info->i = cpustate->irq_state[TMS7000_IRQ2_LINE]; break;
296		case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE:   info->i = cpustate->irq_state[TMS7000_IRQ3_LINE]; break;
297
298		case CPUINFO_INT_PREVIOUSPC:    info->i = 0; /* Not supported */    break;
299
300		case CPUINFO_INT_PC:
301		case CPUINFO_INT_REGISTER + TMS7000_PC: info->i = pPC;  break;
302		case CPUINFO_INT_SP:
303		case CPUINFO_INT_REGISTER + TMS7000_SP: info->i = pSP;  break;
304		case CPUINFO_INT_REGISTER + TMS7000_ST: info->i = pSR;  break;
305		case CPUINFO_INT_REGISTER + TMS7000_IDLE: info->i = cpustate->idle_state; break;
306		case CPUINFO_INT_REGISTER + TMS7000_T1_CL: info->i = cpustate->t1_capture_latch; break;
307		case CPUINFO_INT_REGISTER + TMS7000_T1_PS: info->i = cpustate->t1_prescaler; break;
308		case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: info->i = cpustate->t1_decrementer; break;
309
310		/* --- the following bits of info are returned as pointers to data or functions --- */
311		case CPUINFO_FCT_SET_INFO:  info->setinfo = CPU_SET_INFO_NAME(tms7000); break;
312		case CPUINFO_FCT_INIT:  info->init = CPU_INIT_NAME(tms7000);    break;
313		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms7000);  break;
314		case CPUINFO_FCT_EXECUTE:   info->execute = CPU_EXECUTE_NAME(tms7000);  break;
315		case CPUINFO_FCT_BURN:  info->burn = NULL;  /* Not supported */break;
316		case CPUINFO_FCT_DISASSEMBLE:   info->disassemble = CPU_DISASSEMBLE_NAME(tms7000);  break;
317		case CPUINFO_PTR_INSTRUCTION_COUNTER:   info->icount = &cpustate->icount;   break;
318		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM:  info->internal_map8 = ADDRESS_MAP_NAME(tms7000_mem); break;
319
320		/* --- the following bits of info are returned as NULL-terminated strings --- */
321		case CPUINFO_STR_NAME:  strcpy(info->s, "TMS7000"); break;
322		case CPUINFO_STR_SHORTNAME:  strcpy(info->s, "tms7000"); break;
323		case CPUINFO_STR_FAMILY:    strcpy(info->s, "Texas Instriuments TMS7000"); break;
324		case CPUINFO_STR_VERSION:   strcpy(info->s, "1.0"); break;
325		case CPUINFO_STR_SOURCE_FILE:   strcpy(info->s, __FILE__); break;
326		case CPUINFO_STR_CREDITS:   strcpy(info->s, "Copyright tim lindner"); break;
327
328		case CPUINFO_STR_FLAGS:
329		sprintf(info->s,  "%c%c%c%c%c%c%c%c",
330		cpustate->sr & 0x80 ? 'C':'c',
331		cpustate->sr & 0x40 ? 'N':'n',
332		cpustate->sr & 0x20 ? 'Z':'z',
333		cpustate->sr & 0x10 ? 'I':'i',
334		cpustate->sr & 0x08 ? '?':'.',
335		cpustate->sr & 0x04 ? '?':'.',
336		cpustate->sr & 0x02 ? '?':'.',
337		cpustate->sr & 0x01 ? '?':'.' );
338		break;
339
340		case CPUINFO_STR_REGISTER + TMS7000_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break;
341		case CPUINFO_STR_REGISTER + TMS7000_SP: sprintf(info->s, "S:%02X", cpustate->sp); break;
342		case CPUINFO_STR_REGISTER + TMS7000_ST: sprintf(info->s, "ST:%02X", cpustate->sr); break;
343		case CPUINFO_STR_REGISTER + TMS7000_IDLE: sprintf(info->s, "Idle:%02X", cpustate->idle_state); break;
344		case CPUINFO_STR_REGISTER + TMS7000_T1_CL: sprintf(info->s, "T1CL:%02X", cpustate->t1_capture_latch); break;
345		case CPUINFO_STR_REGISTER + TMS7000_T1_PS: sprintf(info->s, "T1PS:%02X", cpustate->t1_prescaler & 0x1f); break;
346		case CPUINFO_STR_REGISTER + TMS7000_T1_DEC: sprintf(info->s, "T1DEC:%02X", cpustate->t1_decrementer & 0xff); break;
347
348		}
349		}
350
351		CPU_GET_INFO( tms7000_exl )
352		{
353		switch( state )
354		{
355		case CPUINFO_FCT_EXECUTE:
356		info->execute = CPU_EXECUTE_NAME(tms7000_exl);
357		break;
358		default:
359		CPU_GET_INFO_CALL(tms7000);
360		break;
361		}
362		}
363
364		void tms7000_set_irq_line(tms7000_state *cpustate, int irqline, int state)
365		{
366		if (cpustate->irq_state[irqline] != state)
	255	if (m_irq_state[irqline] != state)
367	256	{   /* check for transition */
368		cpustate->irq_state[irqline] = state;
	257	m_irq_state[irqline] = state;
369	258
370		LOG(("tms7000: (cpu '%s') set_irq_line (INT%d, state %d)\n", cpustate->device->tag(), irqline+1, state));
	259	LOG(("tms7000: (cpu '%s') set_irq_line (INT%d, state %d)\n", tag(), irqline+1, state));
371	260
372	261	if (state == CLEAR_LINE)
373	262	{
374	263	return;
375	264	}
376	265
377		cpustate->pf[0] |= (0x02 << (irqline * 2)); /* Set INTx iocntl0 flag */
	266	m_pf[0] |= (0x02 << (irqline * 2)); /* Set INTx iocntl0 flag */
378	267
379	268	if( irqline == TMS7000_IRQ3_LINE )
380	269	{
381	270	/* Latch the value in perpherial file register 3 */
382		cpustate->t1_capture_latch = cpustate->t1_decrementer & 0x00ff;
	271	m_t1_capture_latch = m_t1_decrementer & 0x00ff;
383	272	}
384	273
385		tms7000_check_IRQ_lines(cpustate);
	274	tms7000_check_IRQ_lines();
386	275	}
387	276	}
388	277
389		static void tms7000_check_IRQ_lines(tms7000_state *cpustate)
	278	void tms7000_device::tms7000_check_IRQ_lines()
390	279	{
391	280	if( pSR & SR_I ) /* Check Global Interrupt bit: Status register, bit 4 */
392	281	{
393		if ((cpustate->irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE) || (cpustate->pf[0] & 0x02))
	282	if ((m_irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE) || (m_pf[0] & 0x02))
394	283	{
395		if( cpustate->pf[0] & 0x01 ) /* INT1 Enable bit */
	284	if( m_pf[0] & 0x01 ) /* INT1 Enable bit */
396	285	{
397		tms7000_do_interrupt( cpustate, 0xfffc, TMS7000_IRQ1_LINE );
398		cpustate->pf[0] &= ~0x02; /* Data Manual, page: 9-41 */
	286	tms7000_do_interrupt( 0xfffc, TMS7000_IRQ1_LINE );
	287	m_pf[0] &= ~0x02; /* Data Manual, page: 9-41 */
399	288	return;
400	289	}
401	290	}
402	291
403		if( cpustate->irq_state[ TMS7000_IRQ2_LINE ] == ASSERT_LINE )
	292	if( m_irq_state[ TMS7000_IRQ2_LINE ] == ASSERT_LINE )
404	293	{
405		if( cpustate->pf[0] & 0x04 ) /* INT2 Enable bit */
	294	if( m_pf[0] & 0x04 ) /* INT2 Enable bit */
406	295	{
407		tms7000_do_interrupt( cpustate, 0xfffa, TMS7000_IRQ2_LINE );
	296	tms7000_do_interrupt( 0xfffa, TMS7000_IRQ2_LINE );
408	297	return;
409	298	}
410	299	}
411	300
412		if ((cpustate->irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE) || (cpustate->pf[0] & 0x20))
	301	if ((m_irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE) || (m_pf[0] & 0x20))
413	302	{
414		if( cpustate->pf[0] & 0x10 ) /* INT3 Enable bit */
	303	if( m_pf[0] & 0x10 ) /* INT3 Enable bit */
415	304	{
416		tms7000_do_interrupt( cpustate, 0xfff8, TMS7000_IRQ3_LINE );
417		cpustate->pf[0] &= ~0x20; /* Data Manual, page: 9-41 */
	305	tms7000_do_interrupt( 0xfff8, TMS7000_IRQ3_LINE );
	306	m_pf[0] &= ~0x20; /* Data Manual, page: 9-41 */
418	307	return;
419	308	}
420	309	}
421	310	}
422	311	}
423	312
424		static void tms7000_do_interrupt( tms7000_state *cpustate, UINT16 address, UINT8 line )
	313	void tms7000_device::tms7000_do_interrupt( UINT16 address, UINT8 line )
425	314	{
426	315	PUSHBYTE( pSR );        /* Push Status register */
427	316	PUSHWORD( PC );         /* Push Program Counter */
428	317	pSR = 0;                /* Clear Status register */
429		pPC = RM16(cpustate, address);  /* Load PC with interrupt vector */
	318	pPC = RM16(address);  /* Load PC with interrupt vector */
430	319
431		if( cpustate->idle_state == 0 )
432		cpustate->icount -= 19;     /* 19 cycles used */
	320	if( m_idle_state == 0 )
	321	m_icount -= 19;     /* 19 cycles used */
433	322	else
434	323	{
435		cpustate->icount -= 17;     /* 17 if idled */
436		cpustate->idle_state = 0;
	324	m_icount -= 17;     /* 17 if idled */
	325	m_idle_state = 0;
437	326	}
438	327
439		(void)(*cpustate->irq_callback)(cpustate->device, line);
	328	standard_irq_callback(line);
440	329	}
441	330
442	331	#include "tms70op.c"
443	332	#include "tms70tb.c"
444	333
445		static CPU_EXECUTE( tms7000 )
	334	void tms7000_device::execute_run()
446	335	{
447		tms7000_state *cpustate = get_safe_token(device);
448	336	int op;
449	337
450		cpustate->div_by_16_trigger += cpustate->icount;
	338	m_div_by_16_trigger += m_icount;
451	339
452		tms7000_check_IRQ_lines(cpustate);
	340	tms7000_check_IRQ_lines();
453	341
454	342	do
455	343	{
456		debugger_instruction_hook(device, pPC);
	344	debugger_instruction_hook(this, pPC);
457	345
458		if( cpustate->idle_state == 0 )
	346	if( m_idle_state == 0 )
459	347	{
460		op = cpustate->direct->read_decrypted_byte(pPC++);
	348	op = m_direct->read_decrypted_byte(pPC++);
461	349
462		opfn[op](cpustate);
	350	(this->*m_opcode[op])();
463	351	}
464	352	else
465		cpustate->icount -= 16;
	353	m_icount -= 16;
466	354
467	355	/* Internal timer system */
468	356
469		while( cpustate->icount < cpustate->div_by_16_trigger )
	357	while( m_icount < m_div_by_16_trigger )
470	358	{
471		cpustate->div_by_16_trigger -= 16;
	359	m_div_by_16_trigger -= 16;
472	360
473		if( (cpustate->pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
	361	if( (m_pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
474	362	{
475		if( (cpustate->pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
476		tms7000_service_timer1(device);
	363	if( (m_pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
	364	tms7000_service_timer1();
477	365	}
478	366	}
479	367
480		} while( cpustate->icount > 0 );
	368	} while( m_icount > 0 );
481	369
482		cpustate->div_by_16_trigger -= cpustate->icount;
	370	m_div_by_16_trigger -= m_icount;
483	371	}
484	372
485		static CPU_EXECUTE( tms7000_exl )
486		{
487		tms7000_state *cpustate = get_safe_token(device);
488		int op;
489	373
490		cpustate->div_by_16_trigger += cpustate->icount;
491
492		tms7000_check_IRQ_lines(cpustate);
493
494		do
495		{
496		debugger_instruction_hook(device, pPC);
497
498		if( cpustate->idle_state == 0 )
499		{
500		op = cpustate->direct->read_decrypted_byte(pPC++);
501
502		opfn_exl[op](cpustate);
503		}
504		else
505		cpustate->icount -= 16;
506
507		/* Internal timer system */
508
509		while( cpustate->icount < cpustate->div_by_16_trigger )
510		{
511		cpustate->div_by_16_trigger -= 16;
512
513		if( (cpustate->pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
514		{
515		if( (cpustate->pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
516		tms7000_service_timer1(device);
517		}
518		}
519
520		} while( cpustate->icount > 0 );
521
522		cpustate->div_by_16_trigger -= cpustate->icount;
523		}
524
525	374	/****************************************************************************
526	375	* Trigger the event counter
527	376	****************************************************************************/
528		void tms7000_A6EC1( device_t *device )
	377	void tms7000_device::tms7000_A6EC1()
529	378	{
530		tms7000_state *cpustate = get_safe_token(device);
531		if( (cpustate->pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
	379	if( (m_pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
532	380	{
533		if( (cpustate->pf[0x03] & 0x40) == 0x40) /* Is event counter the timer source? */
534		tms7000_service_timer1(device);
	381	if( (m_pf[0x03] & 0x40) == 0x40) /* Is event counter the timer source? */
	382	tms7000_service_timer1();
535	383	}
536	384	}
537	385
538		static void tms7000_service_timer1( device_t *device )
	386	void tms7000_device::tms7000_service_timer1()
539	387	{
540		tms7000_state *cpustate = get_safe_token(device);
541		if( --cpustate->t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */
	388	if( --m_t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */
542	389	{
543		cpustate->t1_prescaler = cpustate->pf[3] & 0x1f; /* Reload prescaler (5 bit) */
	390	m_t1_prescaler = m_pf[3] & 0x1f; /* Reload prescaler (5 bit) */
544	391
545		if( --cpustate->t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */
	392	if( --m_t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */
546	393	{
547		cpustate->t1_decrementer = cpustate->pf[2]; /* Reload decrementer (8 bit) */
548		device->execute().set_input_line(TMS7000_IRQ2_LINE, HOLD_LINE);
549		//LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", cpustate->device->total_cycles(), cpustate->device->total_cycles() - tick, cpustate->cycles_per_INT2-(cpustate->device->total_cycles() - tick) );
550		//tick = cpustate->device->total_cycles() );
	394	m_t1_decrementer = m_pf[2]; /* Reload decrementer (8 bit) */
	395	set_input_line(TMS7000_IRQ2_LINE, HOLD_LINE);
	396	//LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", total_cycles(), total_cycles() - tick, m_cycles_per_INT2-(total_cycles() - tick) );
	397	//tick = total_cycles() );
551	398	/* Also, cascade out to timer 2 - timer 2 unimplemented */
552	399	}
553	400	}
554		//  LOG( ( "tms7000: service timer1. 0x%2.2x 0x%2.2x (cycles %d)\t%d\t\n", cpustate->t1_prescaler, cpustate->t1_decrementer, cpustate->device->total_cycles(), cpustate->device->total_cycles() - tick2 ) );
555		//  tick2 = cpustate->device->total_cycles();
	401	//  LOG( ( "tms7000: service timer1. 0x%2.2x 0x%2.2x (cycles %d)\t%d\t\n", m_t1_prescaler, m_t1_decrementer, total_cycles(), total_cycles() - tick2 ) );
	402	//  tick2 = total_cycles();
556	403	}
557	404
558		static WRITE8_HANDLER( tms70x0_pf_w )   /* Perpherial file write */
	405	WRITE8_MEMBER( tms7000_device::tms70x0_pf_w )   /* Perpherial file write */
559	406	{
560		tms7000_state *cpustate = get_safe_token(&space.device());
561	407	UINT8   temp1, temp2, temp3;
562	408
563	409	switch( offset )
564	410	{
565	411	case 0x00:  /* IOCNT0, Input/Ouput control */
566	412	temp1 = data & 0x2a;                            /* Record which bits to clear */
567		temp2 = cpustate->pf[0x00] & 0x2a;              /* Get copy of current bits */
	413	temp2 = m_pf[0x00] & 0x2a;              /* Get copy of current bits */
568	414	temp3 = (~temp1) & temp2;                       /* Clear the requested bits */
569		cpustate->pf[0x00] = temp3 | (data & (~0x2a) ); /* OR in the remaining data */
	415	m_pf[0x00] = temp3 | (data & (~0x2a) ); /* OR in the remaining data */
570	416	break;
571	417	case 0x02:
572		cpustate->t1_decrementer = cpustate->pf[0x02] = data;
573		cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
574		LOG( ( "tms7000: Timer adjusted. Decrementer: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->t1_decrementer, cpustate->cycles_per_INT2 ) );
	418	m_t1_decrementer = m_pf[0x02] = data;
	419	m_cycles_per_INT2 = 0x10*((m_pf[3] & 0x1f)+1)*(m_pf[0x02]+1);
	420	LOG( ( "tms7000: Timer adjusted. Decrementer: 0x%2.2x (Cycles per interrupt: %d)\n", m_t1_decrementer, m_cycles_per_INT2 ) );
575	421	break;
576	422	case 0x03:  /* T1CTL, timer 1 control */
577		if( ((cpustate->pf[0x03] & 0x80) == 0) && ((data & 0x80) == 0x80 ) )   /* Start timer? */
	423	if( ((m_pf[0x03] & 0x80) == 0) && ((data & 0x80) == 0x80 ) )   /* Start timer? */
578	424	{
579		cpustate->pf[0x03] = data;
580		cpustate->t1_prescaler = cpustate->pf[3] & 0x1f; /* Reload prescaler (5 bit) */
581		cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
582		LOG( ( "tms7000: Timer started. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->pf[3] & 0x1f, cpustate->cycles_per_INT2 ) );
	425	m_pf[0x03] = data;
	426	m_t1_prescaler = m_pf[3] & 0x1f; /* Reload prescaler (5 bit) */
	427	m_cycles_per_INT2 = 0x10*((m_pf[3] & 0x1f)+1)*(m_pf[0x02]+1);
	428	LOG( ( "tms7000: Timer started. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", m_pf[3] & 0x1f, m_cycles_per_INT2 ) );
583	429	}
584		else if( ((data & 0x80) == 0x80 ) && ((cpustate->pf[0x03] & 0x80) == 0) )   /* Timer Stopped? */
	430	else if( ((data & 0x80) == 0x80 ) && ((m_pf[0x03] & 0x80) == 0) )   /* Timer Stopped? */
585	431	{
586		cpustate->pf[0x03] = data;
587		cpustate->t1_prescaler = cpustate->pf[3] & 0x1f; /* Reload prescaler (5 bit) */
588		cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
589		LOG( ( "tms7000: Timer stopped. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->pf[3] & 0x1f, cpustate->cycles_per_INT2 ) );
	432	m_pf[0x03] = data;
	433	m_t1_prescaler = m_pf[3] & 0x1f; /* Reload prescaler (5 bit) */
	434	m_cycles_per_INT2 = 0x10*((m_pf[3] & 0x1f)+1)*(m_pf[0x02]+1);
	435	LOG( ( "tms7000: Timer stopped. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", m_pf[3] & 0x1f, m_cycles_per_INT2 ) );
590	436	}
591	437	else /* Don't modify timer state, but still store data */
592	438	{
593		cpustate->pf[0x03] = data;
594		cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
595		LOG( ( "tms7000: Timer adjusted. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->pf[3] & 0x1f, cpustate->cycles_per_INT2 ) );
	439	m_pf[0x03] = data;
	440	m_cycles_per_INT2 = 0x10*((m_pf[3] & 0x1f)+1)*(m_pf[0x02]+1);
	441	LOG( ( "tms7000: Timer adjusted. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", m_pf[3] & 0x1f, m_cycles_per_INT2 ) );
596	442	}
597	443	break;
598	444
r26878	r26879
601	447	break;
602	448
603	449	case 0x06: /* Port B write */
604		cpustate->io->write_byte( TMS7000_PORTB, data );
605		cpustate->pf[ 0x06 ] = data;
	450	m_io->write_byte( TMS7000_PORTB, data );
	451	m_pf[ 0x06 ] = data;
606	452	break;
607	453
608	454	case 0x08: /* Port C write */
609		temp1 = data & cpustate->pf[ 0x09 ];    /* Mask off input bits */
610		cpustate->io->write_byte( TMS7000_PORTC, temp1 );
611		cpustate->pf[ 0x08 ] = temp1;
	455	temp1 = data & m_pf[ 0x09 ];    /* Mask off input bits */
	456	m_io->write_byte( TMS7000_PORTC, temp1 );
	457	m_pf[ 0x08 ] = temp1;
612	458	break;
613	459
614	460	case 0x0a: /* Port D write */
615		temp1 = data & cpustate->pf[ 0x0b ];    /* Mask off input bits */
616		cpustate->io->write_byte( TMS7000_PORTD, temp1 );
617		cpustate->pf[ 0x0a ] = temp1;
	461	temp1 = data & m_pf[ 0x0b ];    /* Mask off input bits */
	462	m_io->write_byte( TMS7000_PORTD, temp1 );
	463	m_pf[ 0x0a ] = temp1;
618	464	break;
619	465
620	466	default:
621	467	/* Just stuff the other registers */
622		cpustate->pf[ offset ] = data;
	468	m_pf[ offset ] = data;
623	469	break;
624	470	}
625	471	}
626	472
627		static READ8_HANDLER( tms70x0_pf_r )    /* Perpherial file read */
	473	READ8_MEMBER( tms7000_device::tms70x0_pf_r )    /* Perpherial file read */
628	474	{
629		tms7000_state *cpustate = get_safe_token(&space.device());
630	475	UINT8 result;
631	476	UINT8   temp1, temp2, temp3;
632	477
633	478	switch( offset )
634	479	{
635	480	case 0x00:  /* IOCNT0, Input/Ouput control */
636		result = cpustate->pf[0x00];
637		if (cpustate->irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE)
	481	result = m_pf[0x00];
	482	if (m_irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE)
638	483	result |= 0x02;
639		if (cpustate->irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE)
	484	if (m_irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE)
640	485	result |= 0x20;
641	486	break;
642	487
643	488	case 0x02:  /* T1DATA, timer 1 8-bit decrementer */
644		result = (cpustate->t1_decrementer & 0x00ff);
	489	result = (m_t1_decrementer & 0x00ff);
645	490	break;
646	491
647	492	case 0x03:  /* T1CTL, timer 1 capture (latched by INT3) */
648		result = cpustate->t1_capture_latch;
	493	result = m_t1_capture_latch;
649	494	break;
650	495
651	496	case 0x04: /* Port A read */
652		result = cpustate->io->read_byte( TMS7000_PORTA );
	497	result = m_io->read_byte( TMS7000_PORTA );
653	498	break;
654	499
655	500
656	501	case 0x06: /* Port B read */
657	502	/* Port B is write only, return a previous written value */
658		result = cpustate->pf[ 0x06 ];
	503	result = m_pf[ 0x06 ];
659	504	break;
660	505
661	506	case 0x08: /* Port C read */
662		temp1 = cpustate->pf[ 0x08 ] & cpustate->pf[ 0x09 ];    /* Get previous output bits */
663		temp2 = cpustate->io->read_byte( TMS7000_PORTC );           /* Read port */
664		temp3 = temp2 & (~cpustate->pf[ 0x09 ]);                /* Mask off output bits */
	507	temp1 = m_pf[ 0x08 ] & m_pf[ 0x09 ];    /* Get previous output bits */
	508	temp2 = m_io->read_byte( TMS7000_PORTC );           /* Read port */
	509	temp3 = temp2 & (~m_pf[ 0x09 ]);                /* Mask off output bits */
665	510	result = temp1 | temp3;                             /* OR together */
666	511	break;
667	512
668	513	case 0x0a: /* Port D read */
669		temp1 = cpustate->pf[ 0x0a ] & cpustate->pf[ 0x0b ];    /* Get previous output bits */
670		temp2 = cpustate->io->read_byte( TMS7000_PORTD );           /* Read port */
671		temp3 = temp2 & (~cpustate->pf[ 0x0b ]);                /* Mask off output bits */
	514	temp1 = m_pf[ 0x0a ] & m_pf[ 0x0b ];    /* Get previous output bits */
	515	temp2 = m_io->read_byte( TMS7000_PORTD );           /* Read port */
	516	temp3 = temp2 & (~m_pf[ 0x0b ]);                /* Mask off output bits */
672	517	result = temp1 | temp3;                             /* OR together */
673	518	break;
674	519
675	520	default:
676	521	/* Just unstuff the other registers */
677		result = cpustate->pf[ offset ];
	522	result = m_pf[ offset ];
678	523	break;
679	524	}
680	525
r26878	r26879
682	527	}
683	528
684	529	// BCD arthrimetic handling
685		static UINT16 bcd_add( UINT16 a, UINT16 b )
	530	UINT16 tms7000_device::bcd_add( UINT16 a, UINT16 b )
686	531	{
687	532	UINT16  t1,t2,t3,t4,t5,t6;
688	533
r26878	r26879
696	541	return t2-t6;
697	542	}
698	543
699		static UINT16 bcd_tencomp( UINT16 a )
	544	UINT16 tms7000_device::bcd_tencomp( UINT16 a )
700	545	{
701	546	UINT16  t1,t2,t3,t4,t5,t6;
702	547
r26878	r26879
712	557	/*
713	558	Compute difference a-b???
714	559	*/
715		static UINT16 bcd_sub( UINT16 a, UINT16 b)
	560	UINT16 tms7000_device::bcd_sub( UINT16 a, UINT16 b)
716	561	{
717	562	//return bcd_tencomp(b) - bcd_tencomp(a);
718	563	return bcd_add(a, bcd_tencomp(b) & 0xff);
719	564	}
720	565
721		static WRITE8_HANDLER( tms7000_internal_w ) {
722		tms7000_state *cpustate = get_safe_token(&space.device());
723		cpustate->rf[ offset ] = data;
	566	WRITE8_MEMBER( tms7000_device::tms7000_internal_w )
	567	{
	568	m_rf[ offset ] = data;
724	569	}
725	570
726		static READ8_HANDLER( tms7000_internal_r ) {
727		tms7000_state *cpustate = get_safe_token(&space.device());
728		return cpustate->rf[ offset ];
	571	READ8_MEMBER( tms7000_device::tms7000_internal_r )
	572	{
	573	return m_rf[ offset ];
729	574	}
730	575
731		DEFINE_LEGACY_CPU_DEVICE(TMS7000, tms7000);
732		DEFINE_LEGACY_CPU_DEVICE(TMS7000_EXL, tms7000_exl);

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