trunk/src/mess/drivers/cat.c
| r26859 | r26860 | |
| 460 | 460 | DECLARE_WRITE8_MEMBER(swyft_via0_w); |
| 461 | 461 | DECLARE_READ8_MEMBER(via0_pa_r); |
| 462 | 462 | DECLARE_WRITE8_MEMBER(via0_pa_w); |
| 463 | | DECLARE_READ_LINE_MEMBER(via0_ca1_r); |
| 464 | 463 | DECLARE_WRITE_LINE_MEMBER(via0_ca1_w); |
| 465 | | DECLARE_READ_LINE_MEMBER(via0_ca2_r); |
| 466 | 464 | DECLARE_WRITE_LINE_MEMBER(via0_ca2_w); |
| 467 | 465 | DECLARE_READ8_MEMBER(via0_pb_r); |
| 468 | 466 | DECLARE_WRITE8_MEMBER(via0_pb_w); |
| 469 | | DECLARE_READ_LINE_MEMBER(via0_cb1_r); |
| 470 | 467 | DECLARE_WRITE_LINE_MEMBER(via0_cb1_w); |
| 471 | | DECLARE_READ_LINE_MEMBER(via0_cb2_r); |
| 472 | 468 | DECLARE_WRITE_LINE_MEMBER(via0_cb2_w); |
| 473 | 469 | DECLARE_WRITE_LINE_MEMBER(via0_int_w); |
| 474 | 470 | |
| r26859 | r26860 | |
| 476 | 472 | DECLARE_WRITE8_MEMBER(swyft_via1_w); |
| 477 | 473 | DECLARE_READ8_MEMBER(via1_pa_r); |
| 478 | 474 | DECLARE_WRITE8_MEMBER(via1_pa_w); |
| 479 | | DECLARE_READ_LINE_MEMBER(via1_ca1_r); |
| 480 | 475 | DECLARE_WRITE_LINE_MEMBER(via1_ca1_w); |
| 481 | | DECLARE_READ_LINE_MEMBER(via1_ca2_r); |
| 482 | 476 | DECLARE_WRITE_LINE_MEMBER(via1_ca2_w); |
| 483 | 477 | DECLARE_READ8_MEMBER(via1_pb_r); |
| 484 | 478 | DECLARE_WRITE8_MEMBER(via1_pb_w); |
| 485 | | DECLARE_READ_LINE_MEMBER(via1_cb1_r); |
| 486 | 479 | DECLARE_WRITE_LINE_MEMBER(via1_cb1_w); |
| 487 | | DECLARE_READ_LINE_MEMBER(via1_cb2_r); |
| 488 | 480 | DECLARE_WRITE_LINE_MEMBER(via1_cb2_w); |
| 489 | 481 | DECLARE_WRITE_LINE_MEMBER(via1_int_w); |
| 490 | 482 | |
| r26859 | r26860 | |
| 1269 | 1261 | MACHINE_START_MEMBER(cat_state,swyft) |
| 1270 | 1262 | { |
| 1271 | 1263 | //m_6ms_timer = timer_alloc(TIMER_COUNTER_6MS); // CRUDE HACK |
| 1264 | |
| 1265 | m_via0->write_ca1(1); |
| 1266 | m_via0->write_ca2(1); |
| 1267 | m_via0->write_cb1(1); |
| 1268 | m_via0->write_cb2(1); |
| 1269 | |
| 1270 | m_via1->write_ca1(1); |
| 1271 | m_via1->write_ca2(1); |
| 1272 | m_via1->write_cb1(1); |
| 1273 | m_via1->write_cb2(1); |
| 1272 | 1274 | } |
| 1273 | 1275 | |
| 1274 | 1276 | MACHINE_RESET_MEMBER(cat_state,swyft) |
| r26859 | r26860 | |
| 1378 | 1380 | logerror("VIA0: Port A written with data of 0x%02x!\n", data); |
| 1379 | 1381 | } |
| 1380 | 1382 | |
| 1381 | | READ_LINE_MEMBER ( cat_state::via0_ca1_r ) |
| 1382 | | { |
| 1383 | | logerror("VIA0: CA1 read!\n"); |
| 1384 | | return 1; |
| 1385 | | } |
| 1386 | | |
| 1387 | 1383 | WRITE_LINE_MEMBER ( cat_state::via0_ca1_w ) |
| 1388 | 1384 | { |
| 1389 | 1385 | logerror("VIA0: CA1 written with %d!\n", state); |
| 1390 | 1386 | } |
| 1391 | 1387 | |
| 1392 | | READ_LINE_MEMBER ( cat_state::via0_ca2_r ) |
| 1393 | | { |
| 1394 | | logerror("VIA0: CA2 read!\n"); |
| 1395 | | return 1; |
| 1396 | | } |
| 1397 | | |
| 1398 | 1388 | WRITE_LINE_MEMBER ( cat_state::via0_ca2_w ) |
| 1399 | 1389 | { |
| 1400 | 1390 | logerror("VIA0: CA2 written with %d!\n", state); |
| r26859 | r26860 | |
| 1411 | 1401 | logerror("VIA0: Port B written with data of 0x%02x!\n", data); |
| 1412 | 1402 | } |
| 1413 | 1403 | |
| 1414 | | READ_LINE_MEMBER ( cat_state::via0_cb1_r ) |
| 1415 | | { |
| 1416 | | logerror("VIA0: CB1 read!\n"); |
| 1417 | | return 1; |
| 1418 | | } |
| 1419 | | |
| 1420 | 1404 | WRITE_LINE_MEMBER ( cat_state::via0_cb1_w ) |
| 1421 | 1405 | { |
| 1422 | 1406 | logerror("VIA0: CB1 written with %d!\n", state); |
| 1423 | 1407 | } |
| 1424 | 1408 | |
| 1425 | | READ_LINE_MEMBER ( cat_state::via0_cb2_r ) |
| 1426 | | { |
| 1427 | | logerror("VIA0: CB2 read!\n"); |
| 1428 | | return 1; |
| 1429 | | } |
| 1430 | | |
| 1431 | 1409 | WRITE_LINE_MEMBER ( cat_state::via0_cb2_w ) |
| 1432 | 1410 | { |
| 1433 | 1411 | logerror("VIA0: CB2 written with %d!\n", state); |
| r26859 | r26860 | |
| 1450 | 1428 | logerror(" VIA1: Port A written with data of 0x%02x!\n", data); |
| 1451 | 1429 | } |
| 1452 | 1430 | |
| 1453 | | READ_LINE_MEMBER ( cat_state::via1_ca1_r ) |
| 1454 | | { |
| 1455 | | logerror(" VIA1: CA1 read!\n"); |
| 1456 | | return 1; |
| 1457 | | } |
| 1458 | | |
| 1459 | 1431 | WRITE_LINE_MEMBER ( cat_state::via1_ca1_w ) |
| 1460 | 1432 | { |
| 1461 | 1433 | logerror(" VIA1: CA1 written with %d!\n", state); |
| 1462 | 1434 | } |
| 1463 | 1435 | |
| 1464 | | READ_LINE_MEMBER ( cat_state::via1_ca2_r ) |
| 1465 | | { |
| 1466 | | logerror(" VIA1: CA2 read!\n"); |
| 1467 | | return 1; |
| 1468 | | } |
| 1469 | | |
| 1470 | 1436 | WRITE_LINE_MEMBER ( cat_state::via1_ca2_w ) |
| 1471 | 1437 | { |
| 1472 | 1438 | logerror(" VIA1: CA2 written with %d!\n", state); |
| r26859 | r26860 | |
| 1483 | 1449 | logerror(" VIA1: Port B written with data of 0x%02x!\n", data); |
| 1484 | 1450 | } |
| 1485 | 1451 | |
| 1486 | | READ_LINE_MEMBER ( cat_state::via1_cb1_r ) |
| 1487 | | { |
| 1488 | | logerror(" VIA1: CB1 read!\n"); |
| 1489 | | return 1; |
| 1490 | | } |
| 1491 | | |
| 1492 | 1452 | WRITE_LINE_MEMBER ( cat_state::via1_cb1_w ) |
| 1493 | 1453 | { |
| 1494 | 1454 | logerror(" VIA1: CB1 written with %d!\n", state); |
| 1495 | 1455 | } |
| 1496 | 1456 | |
| 1497 | | READ_LINE_MEMBER ( cat_state::via1_cb2_r ) |
| 1498 | | { |
| 1499 | | logerror(" VIA1: CB2 read!\n"); |
| 1500 | | return 1; |
| 1501 | | } |
| 1502 | | |
| 1503 | 1457 | WRITE_LINE_MEMBER ( cat_state::via1_cb2_w ) |
| 1504 | 1458 | { |
| 1505 | 1459 | logerror(" VIA1: CB2 written with %d!\n", state); |
| r26859 | r26860 | |
| 1536 | 1490 | MCFG_DEVICE_ADD("via6522_0", VIA6522, XTAL_15_8976MHz/16) // unknown clock, GUESSED |
| 1537 | 1491 | MCFG_VIA6522_READPA_HANDLER(READ8(cat_state, via0_pa_r)) |
| 1538 | 1492 | MCFG_VIA6522_READPB_HANDLER(READ8(cat_state, via0_pb_r)) |
| 1539 | | MCFG_VIA6522_READCA1_HANDLER(READLINE(cat_state, via0_ca1_r)) |
| 1540 | | MCFG_VIA6522_READCB1_HANDLER(READLINE(cat_state, via0_cb1_r)) |
| 1541 | | MCFG_VIA6522_READCA2_HANDLER(READLINE(cat_state, via0_ca2_r)) |
| 1542 | | MCFG_VIA6522_READCB2_HANDLER(READLINE(cat_state, via0_cb2_r)) |
| 1543 | 1493 | MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(cat_state, via0_pa_w)) |
| 1544 | 1494 | MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(cat_state, via0_pb_w)) |
| 1545 | 1495 | MCFG_VIA6522_CA1_HANDLER(WRITELINE(cat_state, via0_ca1_w)) |
| r26859 | r26860 | |
| 1551 | 1501 | MCFG_DEVICE_ADD("via6522_1", VIA6522, XTAL_15_8976MHz/16) // unknown clock, GUESSED |
| 1552 | 1502 | MCFG_VIA6522_READPA_HANDLER(READ8(cat_state, via1_pa_r)) |
| 1553 | 1503 | MCFG_VIA6522_READPB_HANDLER(READ8(cat_state, via1_pb_r)) |
| 1554 | | MCFG_VIA6522_READCA1_HANDLER(READLINE(cat_state, via1_ca1_r)) |
| 1555 | | MCFG_VIA6522_READCB1_HANDLER(READLINE(cat_state, via1_cb1_r)) |
| 1556 | | MCFG_VIA6522_READCA2_HANDLER(READLINE(cat_state, via1_ca2_r)) |
| 1557 | | MCFG_VIA6522_READCB2_HANDLER(READLINE(cat_state, via1_cb2_r)) |
| 1558 | 1504 | MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(cat_state, via1_pa_w)) |
| 1559 | 1505 | MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(cat_state, via1_pb_w)) |
| 1560 | 1506 | MCFG_VIA6522_CA1_HANDLER(WRITELINE(cat_state, via1_ca1_w)) |