trunk/src/mame/drivers/aristmk4.c
| r26857 | r26858 | |
|---|
| 324 | 324 | DECLARE_READ8_MEMBER(via_b_r); |
| 325 | 325 | DECLARE_WRITE8_MEMBER(via_a_w); |
| 326 | 326 | DECLARE_WRITE8_MEMBER(via_b_w); |
| 327 | | DECLARE_READ_LINE_MEMBER(via_ca2_r); |
| 328 | | DECLARE_READ_LINE_MEMBER(via_cb2_r); |
| 329 | 327 | DECLARE_WRITE_LINE_MEMBER(via_ca2_w); |
| 330 | 328 | DECLARE_WRITE_LINE_MEMBER(via_cb2_w); |
| 331 | 329 | DECLARE_WRITE8_MEMBER(pblp_out); |
| r26857 | r26858 | |
|---|
| 833 | 831 | } |
| 834 | 832 | } |
| 835 | 833 | |
| 836 | | READ_LINE_MEMBER(aristmk4_state::via_ca2_r) |
| 837 | | { |
| 838 | | //logerror("Via Port CA2 read %02X\n",0) ; |
| 839 | | // CA2 is connected to CDSOL1 on schematics ? |
| 840 | | |
| 841 | | return 0 ; |
| 842 | | } |
| 843 | | |
| 844 | | READ_LINE_MEMBER(aristmk4_state::via_cb2_r) |
| 845 | | { |
| 846 | | //logerror("Via Port CB2 read %02X\n",0) ; |
| 847 | | // CB2 is connected to HOPMO1 on schematics ? |
| 848 | | |
| 849 | | return 0 ; |
| 850 | | } |
| 851 | | |
| 852 | 834 | WRITE_LINE_MEMBER(aristmk4_state::via_ca2_w) |
| 853 | 835 | { |
| 836 | // CA2 is connected to CDSOL1 on schematics ? |
| 854 | 837 | //logerror("Via Port CA2 write %02X\n",data) ; |
| 855 | 838 | } |
| 856 | 839 | |
| r26857 | r26858 | |
|---|
| 1729 | 1712 | MCFG_DEVICE_ADD("via6522_0", VIA6522, 0) /* 1 MHz.(only 1 or 2 MHz.are valid) */ |
| 1730 | 1713 | MCFG_VIA6522_READPA_HANDLER(READ8(aristmk4_state, via_a_r)) |
| 1731 | 1714 | MCFG_VIA6522_READPB_HANDLER(READ8(aristmk4_state, via_b_r)) |
| 1732 | | MCFG_VIA6522_READCA2_HANDLER(READLINE(aristmk4_state, via_ca2_r)) |
| 1733 | | MCFG_VIA6522_READCB2_HANDLER(READLINE(aristmk4_state, via_cb2_r)) |
| 1734 | 1715 | MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(aristmk4_state, via_a_w)) |
| 1735 | 1716 | MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(aristmk4_state, via_b_w)) |
| 1736 | 1717 | MCFG_VIA6522_CA2_HANDLER(WRITELINE(aristmk4_state, via_ca2_w)) |