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r26841 Tuesday 31st December, 2013 at 16:05:21 UTC by Wilbert Pol
tms32051.c: Modernized cpu core.  [Wilbert Pol]

[src/emu/cpu/tms32051]

32051ops.c 32051ops.h tms32051.c tms32051.h

trunk/src/emu/cpu/tms32051/tms32051.h

r26840	r26841
3	3	#ifndef __TMS32051_H__
4	4	#define __TMS32051_H__
5	5
6		DECLARE_LEGACY_CPU_DEVICE(TMS32051, tms32051);
7	6
8		CPU_DISASSEMBLE( tms32051 );
	7	struct TMS32051_PMST
	8	{
	9	UINT16 iptr;
	10	UINT16 avis;
	11	UINT16 ovly;
	12	UINT16 ram;
	13	UINT16 mpmc;
	14	UINT16 ndx;
	15	UINT16 trm;
	16	UINT16 braf;
	17	};
9	18
	19	struct TMS32051_ST0
	20	{
	21	UINT16 dp;
	22	UINT16 intm;
	23	UINT16 ovm;
	24	UINT16 ov;
	25	UINT16 arp;
	26	};
	27
	28	struct TMS32051_ST1
	29	{
	30	UINT16 arb;
	31	UINT16 cnf;
	32	UINT16 tc;
	33	UINT16 sxm;
	34	UINT16 c;
	35	UINT16 hm;
	36	UINT16 xf;
	37	UINT16 pm;
	38	};
	39
	40
	41	class tms32051_device : public cpu_device
	42	{
	43	public:
	44	// construction/destruction
	45	tms32051_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	46
	47	DECLARE_READ16_MEMBER( cpuregs_r );
	48	DECLARE_WRITE16_MEMBER( cpuregs_w );
	49
	50	protected:
	51	// device-level overrides
	52	virtual void device_start();
	53	virtual void device_reset();
	54
	55	// device_execute_interface overrides
	56	virtual UINT32 execute_min_cycles() const { return 1; }
	57	virtual UINT32 execute_max_cycles() const { return 5; }
	58	virtual UINT32 execute_input_lines() const { return 6; }
	59	virtual void execute_run();
	60	virtual void execute_set_input(int inputnum, int state);
	61
	62	// device_memory_interface overrides
	63	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ); }
	64	virtual bool memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value);
	65
	66	// device_disasm_interface overrides
	67	virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
	68	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
	69	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	70
	71	private:
	72	address_space_config m_program_config;
	73	address_space_config m_data_config;
	74
	75	typedef void ( tms32051_device::*opcode_func )();
	76	static const opcode_func s_opcode_table[256];
	77	static const opcode_func s_opcode_table_be[256];
	78	static const opcode_func s_opcode_table_bf[256];
	79
	80	UINT16 m_pc;
	81	UINT16 m_op;
	82	INT32 m_acc;
	83	INT32 m_accb;
	84	INT32 m_preg;
	85	UINT16 m_treg0;
	86	UINT16 m_treg1;
	87	UINT16 m_treg2;
	88	UINT16 m_ar[8];
	89	INT32 m_rptc;
	90
	91	UINT16 m_bmar;
	92	INT32 m_brcr;
	93	UINT16 m_paer;
	94	UINT16 m_pasr;
	95	UINT16 m_indx;
	96	UINT16 m_dbmr;
	97	UINT16 m_arcr;
	98
	99	TMS32051_ST0 m_st0;
	100	TMS32051_ST1 m_st1;
	101	TMS32051_PMST m_pmst;
	102
	103	UINT16 m_ifr;
	104	UINT16 m_imr;
	105
	106	UINT16 m_pcstack[8];
	107	int m_pcstack_ptr;
	108
	109	UINT16 m_rpt_start, m_rpt_end;
	110
	111	UINT16 m_cbcr;
	112	UINT16 m_cbsr1;
	113	UINT16 m_cber1;
	114	UINT16 m_cbsr2;
	115	UINT16 m_cber2;
	116
	117	struct
	118	{
	119	int tddr;
	120	int psc;
	121	UINT16 tim;
	122	UINT16 prd;
	123	} m_timer;
	124
	125	struct
	126	{
	127	INT32 acc;
	128	INT32 accb;
	129	UINT16 arcr;
	130	UINT16 indx;
	131	TMS32051_PMST pmst;
	132	INT32 preg;
	133	TMS32051_ST0 st0;
	134	TMS32051_ST1 st1;
	135	INT32 treg0;
	136	INT32 treg1;
	137	INT32 treg2;
	138	} m_shadow;
	139
	140	address_space *m_program;
	141	direct_read_data *m_direct;
	142	address_space *m_data;
	143	int m_icount;
	144
	145	inline void CHANGE_PC(UINT16 new_pc);
	146	inline UINT16 PM_READ16(UINT16 address);
	147	inline void PM_WRITE16(UINT16 address, UINT16 data);
	148	inline UINT16 DM_READ16(UINT16 address);
	149	inline void DM_WRITE16(UINT16 address, UINT16 data);
	150	inline void PUSH_STACK(UINT16 pc);
	151	inline UINT16 POP_STACK();
	152	inline INT32 SUB(UINT32 a, UINT32 b);
	153	inline INT32 ADD(UINT32 a, UINT32 b);
	154	inline void UPDATE_AR(int ar, int step);
	155	inline void UPDATE_ARP(int nar);
	156	UINT16 GET_ADDRESS();
	157	inline int GET_ZLVC_CONDITION(int zlvc, int zlvc_mask);
	158	inline int GET_TP_CONDITION(int tp);
	159	inline INT32 PREG_PSCALER(INT32 preg);
	160	void op_invalid();
	161	void op_abs();
	162	void op_adcb();
	163	void op_add_mem();
	164	void op_add_simm();
	165	void op_add_limm();
	166	void op_add_s16_mem();
	167	void op_addb();
	168	void op_addc();
	169	void op_adds();
	170	void op_addt();
	171	void op_and_mem();
	172	void op_and_limm();
	173	void op_and_s16_limm();
	174	void op_andb();
	175	void op_bsar();
	176	void op_cmpl();
	177	void op_crgt();
	178	void op_crlt();
	179	void op_exar();
	180	void op_lacb();
	181	void op_lacc_mem();
	182	void op_lacc_limm();
	183	void op_lacc_s16_mem();
	184	void op_lacl_simm();
	185	void op_lacl_mem();
	186	void op_lact();
	187	void op_lamm();
	188	void op_neg();
	189	void op_norm();
	190	void op_or_mem();
	191	void op_or_limm();
	192	void op_or_s16_limm();
	193	void op_orb();
	194	void op_rol();
	195	void op_rolb();
	196	void op_ror();
	197	void op_rorb();
	198	void op_sacb();
	199	void op_sach();
	200	void op_sacl();
	201	void op_samm();
	202	void op_sath();
	203	void op_satl();
	204	void op_sbb();
	205	void op_sbbb();
	206	void op_sfl();
	207	void op_sflb();
	208	void op_sfr();
	209	void op_sfrb();
	210	void op_sub_mem();
	211	void op_sub_s16_mem();
	212	void op_sub_simm();
	213	void op_sub_limm();
	214	void op_subb();
	215	void op_subc();
	216	void op_subs();
	217	void op_subt();
	218	void op_xor_mem();
	219	void op_xor_limm();
	220	void op_xor_s16_limm();
	221	void op_xorb();
	222	void op_zalr();
	223	void op_zap();
	224	void op_adrk();
	225	void op_cmpr();
	226	void op_lar_mem();
	227	void op_lar_simm();
	228	void op_lar_limm();
	229	void op_ldp_mem();
	230	void op_ldp_imm();
	231	void op_mar();
	232	void op_sar();
	233	void op_sbrk();
	234	void op_b();
	235	void op_bacc();
	236	void op_baccd();
	237	void op_banz();
	238	void op_banzd();
	239	void op_bcnd();
	240	void op_bcndd();
	241	void op_bd();
	242	void op_cala();
	243	void op_calad();
	244	void op_call();
	245	void op_calld();
	246	void op_cc();
	247	void op_ccd();
	248	void op_intr();
	249	void op_nmi();
	250	void op_retc();
	251	void op_retcd();
	252	void op_rete();
	253	void op_reti();
	254	void op_trap();
	255	void op_xc();
	256	void op_bldd_slimm();
	257	void op_bldd_dlimm();
	258	void op_bldd_sbmar();
	259	void op_bldd_dbmar();
	260	void op_bldp();
	261	void op_blpd_bmar();
	262	void op_blpd_imm();
	263	void op_dmov();
	264	void op_in();
	265	void op_lmmr();
	266	void op_out();
	267	void op_smmr();
	268	void op_tblr();
	269	void op_tblw();
	270	void op_apl_dbmr();
	271	void op_apl_imm();
	272	void op_cpl_dbmr();
	273	void op_cpl_imm();
	274	void op_opl_dbmr();
	275	void op_opl_imm();
	276	void op_splk();
	277	void op_xpl_dbmr();
	278	void op_xpl_imm();
	279	void op_apac();
	280	void op_lph();
	281	void op_lt();
	282	void op_lta();
	283	void op_ltd();
	284	void op_ltp();
	285	void op_lts();
	286	void op_mac();
	287	void op_macd();
	288	void op_madd();
	289	void op_mads();
	290	void op_mpy_mem();
	291	void op_mpy_simm();
	292	void op_mpy_limm();
	293	void op_mpya();
	294	void op_mpys();
	295	void op_mpyu();
	296	void op_pac();
	297	void op_spac();
	298	void op_sph();
	299	void op_spl();
	300	void op_spm();
	301	void op_sqra();
	302	void op_sqrs();
	303	void op_zpr();
	304	void op_bit();
	305	void op_bitt();
	306	void op_clrc_ov();
	307	void op_clrc_ext();
	308	void op_clrc_hold();
	309	void op_clrc_tc();
	310	void op_clrc_carry();
	311	void op_clrc_cnf();
	312	void op_clrc_intm();
	313	void op_clrc_xf();
	314	void op_idle();
	315	void op_idle2();
	316	void op_lst_st0();
	317	void op_lst_st1();
	318	void op_pop();
	319	void op_popd();
	320	void op_pshd();
	321	void op_push();
	322	void op_rpt_mem();
	323	void op_rpt_limm();
	324	void op_rpt_simm();
	325	void op_rptb();
	326	void op_rptz();
	327	void op_setc_ov();
	328	void op_setc_ext();
	329	void op_setc_hold();
	330	void op_setc_tc();
	331	void op_setc_carry();
	332	void op_setc_xf();
	333	void op_setc_cnf();
	334	void op_setc_intm();
	335	void op_sst_st0();
	336	void op_sst_st1();
	337	void op_group_be();
	338	void op_group_bf();
	339	void delay_slot(UINT16 startpc);
	340	void check_interrupts();
	341	void save_interrupt_context();
	342	void restore_interrupt_context();
	343	};
	344
	345
	346	extern const device_type TMS32051;
	347
	348
10	349	#endif /* __TMS32051_H__ */

trunk/src/emu/cpu/tms32051/32051ops.c

r26840	r26841
1	1	// stack is LIFO and is 8 levels deep, there is no stackpointer on the real chip
2		INLINE void PUSH_STACK(tms32051_state *cpustate, UINT16 pc)
	2	void tms32051_device::PUSH_STACK(UINT16 pc)
3	3	{
4		cpustate->pcstack_ptr = (cpustate->pcstack_ptr - 1) & 7;
5		cpustate->pcstack[cpustate->pcstack_ptr] = pc;
	4	m_pcstack_ptr = (m_pcstack_ptr - 1) & 7;
	5	m_pcstack[m_pcstack_ptr] = pc;
6	6	}
7	7
8		INLINE UINT16 POP_STACK(tms32051_state *cpustate)
	8	UINT16 tms32051_device::POP_STACK()
9	9	{
10		UINT16 pc = cpustate->pcstack[cpustate->pcstack_ptr];
11		cpustate->pcstack_ptr = (cpustate->pcstack_ptr + 1) & 7;
12		cpustate->pcstack[(cpustate->pcstack_ptr + 7) & 7] = cpustate->pcstack[(cpustate->pcstack_ptr + 6) & 7];
	10	UINT16 pc = m_pcstack[m_pcstack_ptr];
	11	m_pcstack_ptr = (m_pcstack_ptr + 1) & 7;
	12	m_pcstack[(m_pcstack_ptr + 7) & 7] = m_pcstack[(m_pcstack_ptr + 6) & 7];
13	13	return pc;
14	14	}
15	15
16		INLINE INT32 SUB(tms32051_state *cpustate, UINT32 a, UINT32 b)
	16	INT32 tms32051_device::SUB(UINT32 a, UINT32 b)
17	17	{
18	18	UINT32 res = a - b;
19	19
20	20	// C is cleared if borrow was generated
21		cpustate->st1.c = (b > a) ? 0 : 1;
	21	m_st1.c = (b > a) ? 0 : 1;
22	22
23	23	// check overflow
24	24	if ((a ^ b) & (a ^ res) & 0x80000000)
25	25	{
26		if (cpustate->st0.ovm)  // overflow saturation mode
	26	if (m_st0.ovm)  // overflow saturation mode
27	27	{
28	28	res = ((INT32)(res) < 0) ? 0x7fffffff : 0x80000000;
29	29	}
30	30
31	31	// set OV, this is a sticky flag
32		cpustate->st0.ov = 1;
	32	m_st0.ov = 1;
33	33	}
34	34
35	35	return (INT32)(res);
36	36	}
37	37
38		INLINE INT32 ADD(tms32051_state *cpustate, UINT32 a, UINT32 b)
	38	INT32 tms32051_device::ADD(UINT32 a, UINT32 b)
39	39	{
40	40	UINT32 res = a + b;
41	41
42	42	// C is set if carry was generated
43		cpustate->st1.c = (a > res) ? 1 : 0;
	43	m_st1.c = (a > res) ? 1 : 0;
44	44
45	45	// check overflow
46	46	if ((a ^ res) & (b ^ res) & 0x80000000)
47	47	{
48		if (cpustate->st0.ovm)  // overflow saturation mode
	48	if (m_st0.ovm)  // overflow saturation mode
49	49	{
50	50	res = ((INT32)(res) < 0) ? 0x7fffffff : 0x80000000;
51	51	}
52	52
53	53	// set OV, this is a sticky flag
54		cpustate->st0.ov = 1;
	54	m_st0.ov = 1;
55	55	}
56	56
57	57	return (INT32)(res);
58	58	}
59	59
60	60
61		INLINE void UPDATE_AR(tms32051_state *cpustate, int ar, int step)
	61	void tms32051_device::UPDATE_AR(int ar, int step)
62	62	{
63		int cenb1 = (cpustate->cbcr >> 3) & 0x1;
64		int car1 = cpustate->cbcr & 0x7;
65		int cenb2 = (cpustate->cbcr >> 7) & 0x1;
66		int car2 = (cpustate->cbcr >> 4) & 0x7;
	63	int cenb1 = (m_cbcr >> 3) & 0x1;
	64	int car1 = m_cbcr & 0x7;
	65	int cenb2 = (m_cbcr >> 7) & 0x1;
	66	int car2 = (m_cbcr >> 4) & 0x7;
67	67
68	68	if (cenb1 && ar == car1)
69	69	{
70	70	// update circular buffer 1, note that it only checks ==
71		if (cpustate->ar[ar] == cpustate->cber1)
	71	if (m_ar[ar] == m_cber1)
72	72	{
73		cpustate->ar[ar] = cpustate->cbsr1;
	73	m_ar[ar] = m_cbsr1;
74	74	}
75	75	else
76	76	{
77		cpustate->ar[ar] += step;
	77	m_ar[ar] += step;
78	78	}
79	79	}
80	80	else if (cenb2 && ar == car2)
81	81	{
82	82	// update circular buffer 2, note that it only checks ==
83		if (cpustate->ar[ar] == cpustate->cber2)
	83	if (m_ar[ar] == m_cber2)
84	84	{
85		cpustate->ar[ar] = cpustate->cbsr2;
	85	m_ar[ar] = m_cbsr2;
86	86	}
87	87	else
88	88	{
89		cpustate->ar[ar] += step;
	89	m_ar[ar] += step;
90	90	}
91	91	}
92	92	else
93	93	{
94		cpustate->ar[ar] += step;
	94	m_ar[ar] += step;
95	95	}
96	96	}
97	97
98		INLINE void UPDATE_ARP(tms32051_state *cpustate, int nar)
	98	void tms32051_device::UPDATE_ARP(int nar)
99	99	{
100		cpustate->st1.arb = cpustate->st0.arp;
101		cpustate->st0.arp = nar;
	100	m_st1.arb = m_st0.arp;
	101	m_st0.arp = nar;
102	102	}
103	103
104		static UINT16 GET_ADDRESS(tms32051_state *cpustate)
	104	UINT16 tms32051_device::GET_ADDRESS()
105	105	{
106		if (cpustate->op & 0x80)        // Indirect Addressing
	106	if (m_op & 0x80)        // Indirect Addressing
107	107	{
108	108	UINT16 ea;
109		int arp = cpustate->st0.arp;
110		int nar = cpustate->op & 0x7;
	109	int arp = m_st0.arp;
	110	int nar = m_op & 0x7;
111	111
112		ea = cpustate->ar[arp];
	112	ea = m_ar[arp];
113	113
114		switch ((cpustate->op >> 3) & 0xf)
	114	switch ((m_op >> 3) & 0xf)
115	115	{
116	116	case 0x0:   // *            (no operation)
117	117	{
r26840	r26841
119	119	}
120	120	case 0x1:   // *, ARn       (NAR -> ARP)
121	121	{
122		UPDATE_ARP(cpustate, nar);
	122	UPDATE_ARP(nar);
123	123	break;
124	124	}
125	125	case 0x2:   // *-           ((CurrentAR)-1 -> CurrentAR)
126	126	{
127		UPDATE_AR(cpustate, arp, -1);
	127	UPDATE_AR(arp, -1);
128	128	break;
129	129	}
130	130	case 0x3:   // *-, ARn      ((CurrentAR)-1 -> CurrentAR, NAR -> ARP)
131	131	{
132		UPDATE_AR(cpustate, arp, -1);
133		UPDATE_ARP(cpustate, nar);
	132	UPDATE_AR(arp, -1);
	133	UPDATE_ARP(nar);
134	134	break;
135	135	}
136	136	case 0x4:   // *+           ((CurrentAR)+1 -> CurrentAR)
137	137	{
138		UPDATE_AR(cpustate, arp, 1);
	138	UPDATE_AR(arp, 1);
139	139	break;
140	140	}
141	141	case 0x5:   // *+, ARn      ((CurrentAR)+1 -> CurrentAR, NAR -> ARP)
142	142	{
143		UPDATE_AR(cpustate, arp, 1);
144		UPDATE_ARP(cpustate, nar);
	143	UPDATE_AR(arp, 1);
	144	UPDATE_ARP(nar);
145	145	break;
146	146	}
147	147	case 0xa:   // *0-          ((CurrentAR) - INDX)
148	148	{
149		UPDATE_AR(cpustate, arp, -cpustate->indx);
	149	UPDATE_AR(arp, -m_indx);
150	150	break;
151	151	}
152	152	case 0xb:   // *0-, ARn     ((CurrentAR) - INDX -> CurrentAR, NAR -> ARP)
153	153	{
154		UPDATE_AR(cpustate, arp, -cpustate->indx);
155		UPDATE_ARP(cpustate, nar);
	154	UPDATE_AR(arp, -m_indx);
	155	UPDATE_ARP(nar);
156	156	break;
157	157	}
158	158	case 0xc:   // *0+          ((CurrentAR) + INDX -> CurrentAR)
159	159	{
160		UPDATE_AR(cpustate, arp, cpustate->indx);
	160	UPDATE_AR(arp, m_indx);
161	161	break;
162	162	}
163	163	case 0xd:   // *0+, ARn     ((CurrentAR) + INDX -> CurrentAR, NAR -> ARP)
164	164	{
165		UPDATE_AR(cpustate, arp, cpustate->indx);
166		UPDATE_ARP(cpustate, nar);
	165	UPDATE_AR(arp, m_indx);
	166	UPDATE_ARP(nar);
167	167	break;
168	168	}
169	169
170		default:    fatalerror("32051: GET_ADDRESS: unimplemented indirect addressing mode %d at %04X (%04X)\n", (cpustate->op >> 3) & 0xf, cpustate->pc, cpustate->op);
	170	default:    fatalerror("32051: GET_ADDRESS: unimplemented indirect addressing mode %d at %04X (%04X)\n", (m_op >> 3) & 0xf, m_pc, m_op);
171	171	}
172	172
173	173	return ea;
174	174	}
175	175	else                    // Direct Addressing
176	176	{
177		return cpustate->st0.dp | (cpustate->op & 0x7f);
	177	return m_st0.dp | (m_op & 0x7f);
178	178	}
179	179	}
180	180
181		INLINE int GET_ZLVC_CONDITION(tms32051_state *cpustate, int zlvc, int zlvc_mask)
	181	int tms32051_device::GET_ZLVC_CONDITION(int zlvc, int zlvc_mask)
182	182	{
183	183	if (zlvc_mask & 0x2)        // OV-bit
184	184	{
185		if ((zlvc & 0x2) && cpustate->st0.ov)                           // OV
	185	if ((zlvc & 0x2) && m_st0.ov)                           // OV
186	186	{
187	187	// clear OV
188		cpustate->st0.ov = 0;
	188	m_st0.ov = 0;
189	189
190	190	return 1;
191	191	}
192		else if ((zlvc & 0x2) == 0 && cpustate->st0.ov == 0)            // NOV
	192	else if ((zlvc & 0x2) == 0 && m_st0.ov == 0)            // NOV
193	193	return 1;
194	194	}
195	195	if (zlvc_mask & 0x1)        // C-bit
196	196	{
197		if ((zlvc & 0x1) && cpustate->st1.c)                            // C
	197	if ((zlvc & 0x1) && m_st1.c)                            // C
198	198	return 1;
199		else if ((zlvc & 0x1) == 0 && cpustate->st1.c == 0)         // NC
	199	else if ((zlvc & 0x1) == 0 && m_st1.c == 0)         // NC
200	200	return 1;
201	201	}
202	202	if (zlvc_mask & 0x8)        // Z-bit
203	203	{
204		if ((zlvc & 0x8) && (INT32)(cpustate->acc) == 0)                // EQ
	204	if ((zlvc & 0x8) && (INT32)(m_acc) == 0)                // EQ
205	205	return 1;
206		else if ((zlvc & 0x8) == 0 && (INT32)(cpustate->acc) != 0)  // NEQ
	206	else if ((zlvc & 0x8) == 0 && (INT32)(m_acc) != 0)  // NEQ
207	207	return 1;
208	208	}
209	209	if (zlvc_mask & 0x4)        // L-bit
210	210	{
211		if ((zlvc & 0x4) && (INT32)(cpustate->acc) < 0)             // LT
	211	if ((zlvc & 0x4) && (INT32)(m_acc) < 0)             // LT
212	212	return 1;
213		else if ((zlvc & 0x4) == 0 && (INT32)(cpustate->acc) > 0)       // GT
	213	else if ((zlvc & 0x4) == 0 && (INT32)(m_acc) > 0)       // GT
214	214	return 1;
215	215	}
216	216	return 0;
217	217	}
218	218
219		INLINE int GET_TP_CONDITION(tms32051_state *cpustate, int tp)
	219	int tms32051_device::GET_TP_CONDITION(int tp)
220	220	{
221	221	switch (tp)
222	222	{
r26840	r26841
227	227	}
228	228	case 1:     // TC = 1
229	229	{
230		return cpustate->st1.tc;
	230	return m_st1.tc;
231	231	}
232	232	case 2:     // TC = 0
233	233	{
234		return cpustate->st1.tc ^ 1;
	234	return m_st1.tc ^ 1;
235	235	}
236	236	case 3:     // always false
237	237	{
r26840	r26841
241	241	return 0;
242	242	}
243	243
244		INLINE INT32 PREG_PSCALER(tms32051_state *cpustate, INT32 preg)
	244	INT32 tms32051_device::PREG_PSCALER(INT32 preg)
245	245	{
246		switch (cpustate->st1.pm & 3)
	246	switch (m_st1.pm & 3)
247	247	{
248	248	case 0:     // No shift
249	249	{
r26840	r26841
267	267
268	268
269	269
270		static void op_invalid(tms32051_state *cpustate)
	270	void tms32051_device::op_invalid()
271	271	{
272		fatalerror("32051: invalid op at %08X\n", cpustate->pc-1);
	272	fatalerror("32051: invalid op at %08X\n", m_pc-1);
273	273	}
274	274
275		static void op_group_be(tms32051_state *cpustate);
276		static void op_group_bf(tms32051_state *cpustate);
277
278	275	/*****************************************************************************/
279	276
280		static void op_abs(tms32051_state *cpustate)
	277	void tms32051_device::op_abs()
281	278	{
282		fatalerror("32051: unimplemented op abs at %08X\n", cpustate->pc-1);
	279	fatalerror("32051: unimplemented op abs at %08X\n", m_pc-1);
283	280	}
284	281
285		static void op_adcb(tms32051_state *cpustate)
	282	void tms32051_device::op_adcb()
286	283	{
287		fatalerror("32051: unimplemented op adcb at %08X\n", cpustate->pc-1);
	284	fatalerror("32051: unimplemented op adcb at %08X\n", m_pc-1);
288	285	}
289	286
290		static void op_add_mem(tms32051_state *cpustate)
	287	void tms32051_device::op_add_mem()
291	288	{
292	289	INT32 d;
293		UINT16 ea = GET_ADDRESS(cpustate);
294		UINT16 data = DM_READ16(cpustate, ea);
295		int shift = (cpustate->op >> 8) & 0xf;
	290	UINT16 ea = GET_ADDRESS();
	291	UINT16 data = DM_READ16(ea);
	292	int shift = (m_op >> 8) & 0xf;
296	293
297		if (cpustate->st1.sxm)
	294	if (m_st1.sxm)
298	295	{
299	296	d = (INT32)(INT16)(data) << shift;
300	297	}
r26840	r26841
303	300	d = (UINT32)(UINT16)(data) << shift;
304	301	}
305	302
306		cpustate->acc = ADD(cpustate, cpustate->acc, d);
	303	m_acc = ADD(m_acc, d);
307	304
308	305	CYCLES(1);
309	306	}
310	307
311		static void op_add_simm(tms32051_state *cpustate)
	308	void tms32051_device::op_add_simm()
312	309	{
313		UINT16 imm = cpustate->op & 0xff;
	310	UINT16 imm = m_op & 0xff;
314	311
315		cpustate->acc = ADD(cpustate, cpustate->acc, imm);
	312	m_acc = ADD(m_acc, imm);
316	313
317	314	CYCLES(1);
318	315	}
319	316
320		static void op_add_limm(tms32051_state *cpustate)
	317	void tms32051_device::op_add_limm()
321	318	{
322	319	INT32 d;
323		UINT16 imm = ROPCODE(cpustate);
324		int shift = cpustate->op & 0xf;
	320	UINT16 imm = ROPCODE();
	321	int shift = m_op & 0xf;
325	322
326		if (cpustate->st1.sxm)
	323	if (m_st1.sxm)
327	324	{
328	325	d = (INT32)(INT16)(imm) << shift;
329	326	}
r26840	r26841
332	329	d = (UINT32)(UINT16)(imm) << shift;
333	330	}
334	331
335		cpustate->acc = ADD(cpustate, cpustate->acc, d);
	332	m_acc = ADD(m_acc, d);
336	333
337	334	CYCLES(2);
338	335	}
339	336
340		static void op_add_s16_mem(tms32051_state *cpustate)
	337	void tms32051_device::op_add_s16_mem()
341	338	{
342		fatalerror("32051: unimplemented op add s16 mem at %08X\n", cpustate->pc-1);
	339	fatalerror("32051: unimplemented op add s16 mem at %08X\n", m_pc-1);
343	340	}
344	341
345		static void op_addb(tms32051_state *cpustate)
	342	void tms32051_device::op_addb()
346	343	{
347		cpustate->acc = ADD(cpustate, cpustate->acc, cpustate->accb);
	344	m_acc = ADD(m_acc, m_accb);
348	345
349	346	CYCLES(1);
350	347	}
351	348
352		static void op_addc(tms32051_state *cpustate)
	349	void tms32051_device::op_addc()
353	350	{
354		fatalerror("32051: unimplemented op addc at %08X\n", cpustate->pc-1);
	351	fatalerror("32051: unimplemented op addc at %08X\n", m_pc-1);
355	352	}
356	353
357		static void op_adds(tms32051_state *cpustate)
	354	void tms32051_device::op_adds()
358	355	{
359		fatalerror("32051: unimplemented op adds at %08X\n", cpustate->pc-1);
	356	fatalerror("32051: unimplemented op adds at %08X\n", m_pc-1);
360	357	}
361	358
362		static void op_addt(tms32051_state *cpustate)
	359	void tms32051_device::op_addt()
363	360	{
364		fatalerror("32051: unimplemented op addt at %08X\n", cpustate->pc-1);
	361	fatalerror("32051: unimplemented op addt at %08X\n", m_pc-1);
365	362	}
366	363
367		static void op_and_mem(tms32051_state *cpustate)
	364	void tms32051_device::op_and_mem()
368	365	{
369		fatalerror("32051: unimplemented op and mem at %08X\n", cpustate->pc-1);
	366	fatalerror("32051: unimplemented op and mem at %08X\n", m_pc-1);
370	367	}
371	368
372		static void op_and_limm(tms32051_state *cpustate)
	369	void tms32051_device::op_and_limm()
373	370	{
374		UINT32 imm = ROPCODE(cpustate);
375		int shift = cpustate->op & 0xf;
	371	UINT32 imm = ROPCODE();
	372	int shift = m_op & 0xf;
376	373
377		cpustate->acc &= imm << shift;
	374	m_acc &= imm << shift;
378	375
379	376	CYCLES(2);
380	377	}
381	378
382		static void op_and_s16_limm(tms32051_state *cpustate)
	379	void tms32051_device::op_and_s16_limm()
383	380	{
384		fatalerror("32051: unimplemented op and s16 limm at %08X\n", cpustate->pc-1);
	381	fatalerror("32051: unimplemented op and s16 limm at %08X\n", m_pc-1);
385	382	}
386	383
387		static void op_andb(tms32051_state *cpustate)
	384	void tms32051_device::op_andb()
388	385	{
389		fatalerror("32051: unimplemented op andb at %08X\n", cpustate->pc-1);
	386	fatalerror("32051: unimplemented op andb at %08X\n", m_pc-1);
390	387	}
391	388
392		static void op_bsar(tms32051_state *cpustate)
	389	void tms32051_device::op_bsar()
393	390	{
394		int shift = (cpustate->op & 0xf) + 1;
	391	int shift = (m_op & 0xf) + 1;
395	392
396		if (cpustate->st1.sxm)
	393	if (m_st1.sxm)
397	394	{
398		cpustate->acc = (INT32)(cpustate->acc) >> shift;
	395	m_acc = (INT32)(m_acc) >> shift;
399	396	}
400	397	else
401	398	{
402		cpustate->acc = (UINT32)(cpustate->acc) >> shift;
	399	m_acc = (UINT32)(m_acc) >> shift;
403	400	}
404	401
405	402	CYCLES(1);
406	403	}
407	404
408		static void op_cmpl(tms32051_state *cpustate)
	405	void tms32051_device::op_cmpl()
409	406	{
410		cpustate->acc = ~(UINT32)(cpustate->acc);
	407	m_acc = ~(UINT32)(m_acc);
411	408
412	409	CYCLES(1);
413	410	}
414	411
415		static void op_crgt(tms32051_state *cpustate)
	412	void tms32051_device::op_crgt()
416	413	{
417		if (cpustate->acc >= cpustate->accb)
	414	if (m_acc >= m_accb)
418	415	{
419		cpustate->accb = cpustate->acc;
420		cpustate->st1.c = 1;
	416	m_accb = m_acc;
	417	m_st1.c = 1;
421	418	}
422	419	else
423	420	{
424		cpustate->acc = cpustate->accb;
425		cpustate->st1.c = 0;
	421	m_acc = m_accb;
	422	m_st1.c = 0;
426	423	}
427	424
428	425	CYCLES(1);
429	426	}
430	427
431		static void op_crlt(tms32051_state *cpustate)
	428	void tms32051_device::op_crlt()
432	429	{
433		if (cpustate->acc >= cpustate->accb)
	430	if (m_acc >= m_accb)
434	431	{
435		cpustate->acc = cpustate->accb;
436		cpustate->st1.c = 0;
	432	m_acc = m_accb;
	433	m_st1.c = 0;
437	434	}
438	435	else
439	436	{
440		cpustate->accb = cpustate->acc;
441		cpustate->st1.c = 1;
	437	m_accb = m_acc;
	438	m_st1.c = 1;
442	439	}
443	440
444	441	CYCLES(1);
445	442	}
446	443
447		static void op_exar(tms32051_state *cpustate)
	444	void tms32051_device::op_exar()
448	445	{
449		INT32 tmp = cpustate->acc;
450		cpustate->acc = cpustate->accb;
451		cpustate->accb = tmp;
	446	INT32 tmp = m_acc;
	447	m_acc = m_accb;
	448	m_accb = tmp;
452	449
453	450	CYCLES(1);
454	451	}
455	452
456		static void op_lacb(tms32051_state *cpustate)
	453	void tms32051_device::op_lacb()
457	454	{
458		cpustate->acc = cpustate->accb;
	455	m_acc = m_accb;
459	456
460	457	CYCLES(1);
461	458	}
462	459
463		static void op_lacc_mem(tms32051_state *cpustate)
	460	void tms32051_device::op_lacc_mem()
464	461	{
465		int shift = (cpustate->op >> 8) & 0xf;
466		UINT16 ea = GET_ADDRESS(cpustate);
467		UINT16 data = DM_READ16(cpustate, ea);
	462	int shift = (m_op >> 8) & 0xf;
	463	UINT16 ea = GET_ADDRESS();
	464	UINT16 data = DM_READ16(ea);
468	465
469		if (cpustate->st1.sxm)
	466	if (m_st1.sxm)
470	467	{
471		cpustate->acc = (INT32)(INT16)(data) << shift;
	468	m_acc = (INT32)(INT16)(data) << shift;
472	469	}
473	470	else
474	471	{
475		cpustate->acc = (UINT32)(UINT16)(data) << shift;
	472	m_acc = (UINT32)(UINT16)(data) << shift;
476	473	}
477	474
478	475	CYCLES(1);
479	476	}
480	477
481		static void op_lacc_limm(tms32051_state *cpustate)
	478	void tms32051_device::op_lacc_limm()
482	479	{
483		UINT16 imm = ROPCODE(cpustate);
484		int shift = cpustate->op & 0xf;
	480	UINT16 imm = ROPCODE();
	481	int shift = m_op & 0xf;
485	482
486		if (cpustate->st1.sxm)
	483	if (m_st1.sxm)
487	484	{
488		cpustate->acc = (INT32)(INT16)(imm) << shift;
	485	m_acc = (INT32)(INT16)(imm) << shift;
489	486	}
490	487	else
491	488	{
492		cpustate->acc = (UINT32)(UINT16)(imm) << shift;
	489	m_acc = (UINT32)(UINT16)(imm) << shift;
493	490	}
494	491
495	492	CYCLES(1);
496	493	}
497	494
498		static void op_lacc_s16_mem(tms32051_state *cpustate)
	495	void tms32051_device::op_lacc_s16_mem()
499	496	{
500		UINT16 ea = GET_ADDRESS(cpustate);
501		cpustate->acc = DM_READ16(cpustate, ea) << 16;
	497	UINT16 ea = GET_ADDRESS();
	498	m_acc = DM_READ16(ea) << 16;
502	499
503	500	CYCLES(1);
504	501	}
505	502
506		static void op_lacl_simm(tms32051_state *cpustate)
	503	void tms32051_device::op_lacl_simm()
507	504	{
508		cpustate->acc = cpustate->op & 0xff;
	505	m_acc = m_op & 0xff;
509	506
510	507	CYCLES(1);
511	508	}
512	509
513		static void op_lacl_mem(tms32051_state *cpustate)
	510	void tms32051_device::op_lacl_mem()
514	511	{
515		UINT16 ea = GET_ADDRESS(cpustate);
516		cpustate->acc = DM_READ16(cpustate, ea) & 0xffff;
	512	UINT16 ea = GET_ADDRESS();
	513	m_acc = DM_READ16(ea) & 0xffff;
517	514
518	515	CYCLES(1);
519	516	}
520	517
521		static void op_lact(tms32051_state *cpustate)
	518	void tms32051_device::op_lact()
522	519	{
523		fatalerror("32051: unimplemented op lact at %08X\n", cpustate->pc-1);
	520	fatalerror("32051: unimplemented op lact at %08X\n", m_pc-1);
524	521	}
525	522
526		static void op_lamm(tms32051_state *cpustate)
	523	void tms32051_device::op_lamm()
527	524	{
528		UINT16 ea = GET_ADDRESS(cpustate) & 0x7f;
529		cpustate->acc = DM_READ16(cpustate, ea) & 0xffff;
	525	UINT16 ea = GET_ADDRESS() & 0x7f;
	526	m_acc = DM_READ16(ea) & 0xffff;
530	527
531	528	CYCLES(1);
532	529	}
533	530
534		static void op_neg(tms32051_state *cpustate)
	531	void tms32051_device::op_neg()
535	532	{
536		if ((UINT32)(cpustate->acc) == 0x80000000)
	533	if ((UINT32)(m_acc) == 0x80000000)
537	534	{
538		cpustate->st0.ov = 1;
539		cpustate->st1.c = 0;
540		cpustate->acc = (cpustate->st0.ovm) ? 0x7fffffff : 0x80000000;
	535	m_st0.ov = 1;
	536	m_st1.c = 0;
	537	m_acc = (m_st0.ovm) ? 0x7fffffff : 0x80000000;
541	538	}
542	539	else
543	540	{
544		cpustate->acc = 0 - (UINT32)(cpustate->acc);
545		cpustate->st1.c = (cpustate->acc == 0) ? 1 : 0;
	541	m_acc = 0 - (UINT32)(m_acc);
	542	m_st1.c = (m_acc == 0) ? 1 : 0;
546	543	}
547	544
548	545	CYCLES(1);
549	546	}
550	547
551		static void op_norm(tms32051_state *cpustate)
	548	void tms32051_device::op_norm()
552	549	{
553		fatalerror("32051: unimplemented op norm at %08X\n", cpustate->pc-1);
	550	fatalerror("32051: unimplemented op norm at %08X\n", m_pc-1);
554	551	}
555	552
556		static void op_or_mem(tms32051_state *cpustate)
	553	void tms32051_device::op_or_mem()
557	554	{
558		UINT16 ea = GET_ADDRESS(cpustate);
559		UINT16 data = DM_READ16(cpustate, ea);
	555	UINT16 ea = GET_ADDRESS();
	556	UINT16 data = DM_READ16(ea);
560	557
561		cpustate->acc |= (UINT32)(data);
	558	m_acc |= (UINT32)(data);
562	559
563	560	CYCLES(1);
564	561	}
565	562
566		static void op_or_limm(tms32051_state *cpustate)
	563	void tms32051_device::op_or_limm()
567	564	{
568		UINT32 imm = ROPCODE(cpustate);
569		int shift = cpustate->op & 0xf;
	565	UINT32 imm = ROPCODE();
	566	int shift = m_op & 0xf;
570	567
571		cpustate->acc |= imm << shift;
	568	m_acc |= imm << shift;
572	569
573	570	CYCLES(1);
574	571	}
575	572
576		static void op_or_s16_limm(tms32051_state *cpustate)
	573	void tms32051_device::op_or_s16_limm()
577	574	{
578		fatalerror("32051: unimplemented op or s16 limm at %08X\n", cpustate->pc-1);
	575	fatalerror("32051: unimplemented op or s16 limm at %08X\n", m_pc-1);
579	576	}
580	577
581		static void op_orb(tms32051_state *cpustate)
	578	void tms32051_device::op_orb()
582	579	{
583		cpustate->acc |= cpustate->accb;
	580	m_acc |= m_accb;
584	581
585	582	CYCLES(1);
586	583	}
587	584
588		static void op_rol(tms32051_state *cpustate)
	585	void tms32051_device::op_rol()
589	586	{
590		fatalerror("32051: unimplemented op rol at %08X\n", cpustate->pc-1);
	587	fatalerror("32051: unimplemented op rol at %08X\n", m_pc-1);
591	588	}
592	589
593		static void op_rolb(tms32051_state *cpustate)
	590	void tms32051_device::op_rolb()
594	591	{
595		UINT32 acc = cpustate->acc;
596		UINT32 accb = cpustate->accb;
597		UINT32 c = cpustate->st1.c & 1;
	592	UINT32 acc = m_acc;
	593	UINT32 accb = m_accb;
	594	UINT32 c = m_st1.c & 1;
598	595
599		cpustate->acc = (acc << 1) | ((accb >> 31) & 1);
600		cpustate->accb = (accb << 1) | c;
601		cpustate->st1.c = (acc >> 31) & 1;
	596	m_acc = (acc << 1) | ((accb >> 31) & 1);
	597	m_accb = (accb << 1) | c;
	598	m_st1.c = (acc >> 31) & 1;
602	599
603	600	CYCLES(1);
604	601	}
605	602
606		static void op_ror(tms32051_state *cpustate)
	603	void tms32051_device::op_ror()
607	604	{
608		fatalerror("32051: unimplemented op ror at %08X\n", cpustate->pc-1);
	605	fatalerror("32051: unimplemented op ror at %08X\n", m_pc-1);
609	606	}
610	607
611		static void op_rorb(tms32051_state *cpustate)
	608	void tms32051_device::op_rorb()
612	609	{
613		fatalerror("32051: unimplemented op rorb at %08X\n", cpustate->pc-1);
	610	fatalerror("32051: unimplemented op rorb at %08X\n", m_pc-1);
614	611	}
615	612
616		static void op_sacb(tms32051_state *cpustate)
	613	void tms32051_device::op_sacb()
617	614	{
618		cpustate->accb = cpustate->acc;
	615	m_accb = m_acc;
619	616
620	617	CYCLES(1);
621	618	}
622	619
623		static void op_sach(tms32051_state *cpustate)
	620	void tms32051_device::op_sach()
624	621	{
625		UINT16 ea = GET_ADDRESS(cpustate);
626		int shift = (cpustate->op >> 8) & 0x7;
	622	UINT16 ea = GET_ADDRESS();
	623	int shift = (m_op >> 8) & 0x7;
627	624
628		DM_WRITE16(cpustate, ea, (UINT16)((cpustate->acc << shift) >> 16));
	625	DM_WRITE16(ea, (UINT16)((m_acc << shift) >> 16));
629	626	CYCLES(1);
630	627	}
631	628
632		static void op_sacl(tms32051_state *cpustate)
	629	void tms32051_device::op_sacl()
633	630	{
634		UINT16 ea = GET_ADDRESS(cpustate);
635		int shift = (cpustate->op >> 8) & 0x7;
	631	UINT16 ea = GET_ADDRESS();
	632	int shift = (m_op >> 8) & 0x7;
636	633
637		DM_WRITE16(cpustate, ea, (UINT16)(cpustate->acc << shift));
	634	DM_WRITE16(ea, (UINT16)(m_acc << shift));
638	635	CYCLES(1);
639	636	}
640	637
641		static void op_samm(tms32051_state *cpustate)
	638	void tms32051_device::op_samm()
642	639	{
643		UINT16 ea = GET_ADDRESS(cpustate);
	640	UINT16 ea = GET_ADDRESS();
644	641	ea &= 0x7f;
645	642
646		DM_WRITE16(cpustate, ea, (UINT16)(cpustate->acc));
	643	DM_WRITE16(ea, (UINT16)(m_acc));
647	644	CYCLES(1);
648	645	}
649	646
650		static void op_sath(tms32051_state *cpustate)
	647	void tms32051_device::op_sath()
651	648	{
652		fatalerror("32051: unimplemented op sath at %08X\n", cpustate->pc-1);
	649	fatalerror("32051: unimplemented op sath at %08X\n", m_pc-1);
653	650	}
654	651
655		static void op_satl(tms32051_state *cpustate)
	652	void tms32051_device::op_satl()
656	653	{
657		fatalerror("32051: unimplemented op satl at %08X\n", cpustate->pc-1);
	654	fatalerror("32051: unimplemented op satl at %08X\n", m_pc-1);
658	655	}
659	656
660		static void op_sbb(tms32051_state *cpustate)
	657	void tms32051_device::op_sbb()
661	658	{
662		cpustate->acc = SUB(cpustate, cpustate->acc, cpustate->accb);
	659	m_acc = SUB(m_acc, m_accb);
663	660
664	661	CYCLES(1);
665	662	}
666	663
667		static void op_sbbb(tms32051_state *cpustate)
	664	void tms32051_device::op_sbbb()
668	665	{
669		fatalerror("32051: unimplemented op sbbb at %08X\n", cpustate->pc-1);
	666	fatalerror("32051: unimplemented op sbbb at %08X\n", m_pc-1);
670	667	}
671	668
672		static void op_sfl(tms32051_state *cpustate)
	669	void tms32051_device::op_sfl()
673	670	{
674		cpustate->st1.c = (cpustate->acc >> 31) & 1;
675		cpustate->acc = cpustate->acc << 1;
	671	m_st1.c = (m_acc >> 31) & 1;
	672	m_acc = m_acc << 1;
676	673
677	674	CYCLES(1);
678	675	}
679	676
680		static void op_sflb(tms32051_state *cpustate)
	677	void tms32051_device::op_sflb()
681	678	{
682		UINT32 acc = cpustate->acc;
683		UINT32 accb = cpustate->accb;
	679	UINT32 acc = m_acc;
	680	UINT32 accb = m_accb;
684	681
685		cpustate->acc = (acc << 1) | ((accb >> 31) & 1);
686		cpustate->accb = (accb << 1);
687		cpustate->st1.c = (acc >> 31) & 1;
	682	m_acc = (acc << 1) | ((accb >> 31) & 1);
	683	m_accb = (accb << 1);
	684	m_st1.c = (acc >> 31) & 1;
688	685
689	686	CYCLES(1);
690	687	}
691	688
692		static void op_sfr(tms32051_state *cpustate)
	689	void tms32051_device::op_sfr()
693	690	{
694		cpustate->st1.c = cpustate->acc & 1;
	691	m_st1.c = m_acc & 1;
695	692
696		if (cpustate->st1.sxm)
	693	if (m_st1.sxm)
697	694	{
698		cpustate->acc = (INT32)(cpustate->acc) >> 1;
	695	m_acc = (INT32)(m_acc) >> 1;
699	696	}
700	697	else
701	698	{
702		cpustate->acc = (UINT32)(cpustate->acc) >> 1;
	699	m_acc = (UINT32)(m_acc) >> 1;
703	700	}
704	701
705	702	CYCLES(1);
706	703	}
707	704
708		static void op_sfrb(tms32051_state *cpustate)
	705	void tms32051_device::op_sfrb()
709	706	{
710		fatalerror("32051: unimplemented op sfrb at %08X\n", cpustate->pc-1);
	707	fatalerror("32051: unimplemented op sfrb at %08X\n", m_pc-1);
711	708	}
712	709
713		static void op_sub_mem(tms32051_state *cpustate)
	710	void tms32051_device::op_sub_mem()
714	711	{
715	712	INT32 d;
716		UINT16 ea = GET_ADDRESS(cpustate);
717		UINT16 data = DM_READ16(cpustate, ea);
718		int shift = (cpustate->op >> 8) & 0xf;
	713	UINT16 ea = GET_ADDRESS();
	714	UINT16 data = DM_READ16(ea);
	715	int shift = (m_op >> 8) & 0xf;
719	716
720		if (cpustate->st1.sxm)
	717	if (m_st1.sxm)
721	718	{
722	719	d = (INT32)(INT16)(data) << shift;
723	720	}
r26840	r26841
726	723	d = (UINT32)(UINT16)(data) << shift;
727	724	}
728	725
729		cpustate->acc = SUB(cpustate, cpustate->acc, d);
	726	m_acc = SUB(m_acc, d);
730	727
731	728	CYCLES(1);
732	729	}
733	730
734		static void op_sub_s16_mem(tms32051_state *cpustate)
	731	void tms32051_device::op_sub_s16_mem()
735	732	{
736		fatalerror("32051: unimplemented op sub s16 mem at %08X\n", cpustate->pc-1);
	733	fatalerror("32051: unimplemented op sub s16 mem at %08X\n", m_pc-1);
737	734	}
738	735
739		static void op_sub_simm(tms32051_state *cpustate)
	736	void tms32051_device::op_sub_simm()
740	737	{
741		UINT16 imm = cpustate->op & 0xff;
	738	UINT16 imm = m_op & 0xff;
742	739
743		cpustate->acc = SUB(cpustate, cpustate->acc, imm);
	740	m_acc = SUB(m_acc, imm);
744	741
745	742	CYCLES(1);
746	743	}
747	744
748		static void op_sub_limm(tms32051_state *cpustate)
	745	void tms32051_device::op_sub_limm()
749	746	{
750	747	INT32 d;
751		UINT16 imm = ROPCODE(cpustate);
752		int shift = cpustate->op & 0xf;
	748	UINT16 imm = ROPCODE();
	749	int shift = m_op & 0xf;
753	750
754		if (cpustate->st1.sxm)
	751	if (m_st1.sxm)
755	752	{
756	753	d = (INT32)(INT16)(imm) << shift;
757	754	}
r26840	r26841
760	757	d = (UINT32)(UINT16)(imm) << shift;
761	758	}
762	759
763		cpustate->acc = SUB(cpustate, cpustate->acc, d);
	760	m_acc = SUB(m_acc, d);
764	761
765	762	CYCLES(2);
766	763	}
767	764
768		static void op_subb(tms32051_state *cpustate)
	765	void tms32051_device::op_subb()
769	766	{
770		fatalerror("32051: unimplemented op subb at %08X\n", cpustate->pc-1);
	767	fatalerror("32051: unimplemented op subb at %08X\n", m_pc-1);
771	768	}
772	769
773		static void op_subc(tms32051_state *cpustate)
	770	void tms32051_device::op_subc()
774	771	{
775		fatalerror("32051: unimplemented op subc at %08X\n", cpustate->pc-1);
	772	fatalerror("32051: unimplemented op subc at %08X\n", m_pc-1);
776	773	}
777	774
778		static void op_subs(tms32051_state *cpustate)
	775	void tms32051_device::op_subs()
779	776	{
780		fatalerror("32051: unimplemented op subs at %08X\n", cpustate->pc-1);
	777	fatalerror("32051: unimplemented op subs at %08X\n", m_pc-1);
781	778	}
782	779
783		static void op_subt(tms32051_state *cpustate)
	780	void tms32051_device::op_subt()
784	781	{
785		fatalerror("32051: unimplemented op subt at %08X\n", cpustate->pc-1);
	782	fatalerror("32051: unimplemented op subt at %08X\n", m_pc-1);
786	783	}
787	784
788		static void op_xor_mem(tms32051_state *cpustate)
	785	void tms32051_device::op_xor_mem()
789	786	{
790		UINT16 ea = GET_ADDRESS(cpustate);
791		UINT16 data = DM_READ16(cpustate, ea);
	787	UINT16 ea = GET_ADDRESS();
	788	UINT16 data = DM_READ16(ea);
792	789
793		cpustate->acc ^= (UINT32)(data);
	790	m_acc ^= (UINT32)(data);
794	791
795	792	CYCLES(1);
796	793	}
797	794
798		static void op_xor_limm(tms32051_state *cpustate)
	795	void tms32051_device::op_xor_limm()
799	796	{
800		UINT32 imm = ROPCODE(cpustate);
801		int shift = cpustate->op & 0xf;
	797	UINT32 imm = ROPCODE();
	798	int shift = m_op & 0xf;
802	799
803		cpustate->acc ^= imm << shift;
	800	m_acc ^= imm << shift;
804	801
805	802	CYCLES(1);
806	803	}
807	804
808		static void op_xor_s16_limm(tms32051_state *cpustate)
	805	void tms32051_device::op_xor_s16_limm()
809	806	{
810		fatalerror("32051: unimplemented op xor s16 limm at %08X\n", cpustate->pc-1);
	807	fatalerror("32051: unimplemented op xor s16 limm at %08X\n", m_pc-1);
811	808	}
812	809
813		static void op_xorb(tms32051_state *cpustate)
	810	void tms32051_device::op_xorb()
814	811	{
815		fatalerror("32051: unimplemented op xorb at %08X\n", cpustate->pc-1);
	812	fatalerror("32051: unimplemented op xorb at %08X\n", m_pc-1);
816	813	}
817	814
818		static void op_zalr(tms32051_state *cpustate)
	815	void tms32051_device::op_zalr()
819	816	{
820		fatalerror("32051: unimplemented op zalr at %08X\n", cpustate->pc-1);
	817	fatalerror("32051: unimplemented op zalr at %08X\n", m_pc-1);
821	818	}
822	819
823		static void op_zap(tms32051_state *cpustate)
	820	void tms32051_device::op_zap()
824	821	{
825		cpustate->acc = 0;
826		cpustate->preg = 0;
	822	m_acc = 0;
	823	m_preg = 0;
827	824
828	825	CYCLES(1);
829	826	}
830	827
831	828	/*****************************************************************************/
832	829
833		static void op_adrk(tms32051_state *cpustate)
	830	void tms32051_device::op_adrk()
834	831	{
835		UINT16 imm = cpustate->op & 0xff;
836		UPDATE_AR(cpustate, cpustate->st0.arp, imm);
	832	UINT16 imm = m_op & 0xff;
	833	UPDATE_AR(m_st0.arp, imm);
837	834
838	835	CYCLES(1);
839	836	}
840	837
841		static void op_cmpr(tms32051_state *cpustate)
	838	void tms32051_device::op_cmpr()
842	839	{
843		cpustate->st1.tc = 0;
	840	m_st1.tc = 0;
844	841
845		switch (cpustate->op & 0x3)
	842	switch (m_op & 0x3)
846	843	{
847	844	case 0:         // (CurrentAR) == ARCR
848	845	{
849		if (cpustate->ar[cpustate->st0.arp] == cpustate->arcr)
	846	if (m_ar[m_st0.arp] == m_arcr)
850	847	{
851		cpustate->st1.tc = 1;
	848	m_st1.tc = 1;
852	849	}
853	850	break;
854	851	}
855	852	case 1:         // (CurrentAR) < ARCR
856	853	{
857		if (cpustate->ar[cpustate->st0.arp] < cpustate->arcr)
	854	if (m_ar[m_st0.arp] < m_arcr)
858	855	{
859		cpustate->st1.tc = 1;
	856	m_st1.tc = 1;
860	857	}
861	858	break;
862	859	}
863	860	case 2:         // (CurrentAR) > ARCR
864	861	{
865		if (cpustate->ar[cpustate->st0.arp] > cpustate->arcr)
	862	if (m_ar[m_st0.arp] > m_arcr)
866	863	{
867		cpustate->st1.tc = 1;
	864	m_st1.tc = 1;
868	865	}
869	866	break;
870	867	}
871	868	case 3:         // (CurrentAR) != ARCR
872	869	{
873		if (cpustate->ar[cpustate->st0.arp] != cpustate->arcr)
	870	if (m_ar[m_st0.arp] != m_arcr)
874	871	{
875		cpustate->st1.tc = 1;
	872	m_st1.tc = 1;
876	873	}
877	874	break;
878	875	}
r26840	r26841
881	878	CYCLES(1);
882	879	}
883	880
884		static void op_lar_mem(tms32051_state *cpustate)
	881	void tms32051_device::op_lar_mem()
885	882	{
886		int arx = (cpustate->op >> 8) & 0x7;
887		UINT16 ea = GET_ADDRESS(cpustate);
888		UINT16 data = DM_READ16(cpustate, ea);
	883	int arx = (m_op >> 8) & 0x7;
	884	UINT16 ea = GET_ADDRESS();
	885	UINT16 data = DM_READ16(ea);
889	886
890		cpustate->ar[arx] = data;
	887	m_ar[arx] = data;
891	888
892	889	CYCLES(2);
893	890	}
894	891
895		static void op_lar_simm(tms32051_state *cpustate)
	892	void tms32051_device::op_lar_simm()
896	893	{
897		int arx = (cpustate->op >> 8) & 0x7;
898		cpustate->ar[arx] = cpustate->op & 0xff;
	894	int arx = (m_op >> 8) & 0x7;
	895	m_ar[arx] = m_op & 0xff;
899	896
900	897	CYCLES(2);
901	898	}
902	899
903		static void op_lar_limm(tms32051_state *cpustate)
	900	void tms32051_device::op_lar_limm()
904	901	{
905		int arx = cpustate->op & 0x7;
906		UINT16 imm = ROPCODE(cpustate);
907		cpustate->ar[arx] = imm;
	902	int arx = m_op & 0x7;
	903	UINT16 imm = ROPCODE();
	904	m_ar[arx] = imm;
908	905
909	906	CYCLES(2);
910	907	}
911	908
912		static void op_ldp_mem(tms32051_state *cpustate)
	909	void tms32051_device::op_ldp_mem()
913	910	{
914		fatalerror("32051: unimplemented op ldp mem at %08X\n", cpustate->pc-1);
	911	fatalerror("32051: unimplemented op ldp mem at %08X\n", m_pc-1);
915	912	}
916	913
917		static void op_ldp_imm(tms32051_state *cpustate)
	914	void tms32051_device::op_ldp_imm()
918	915	{
919		cpustate->st0.dp = (cpustate->op & 0x1ff) << 7;
	916	m_st0.dp = (m_op & 0x1ff) << 7;
920	917	CYCLES(2);
921	918	}
922	919
923		static void op_mar(tms32051_state *cpustate)
	920	void tms32051_device::op_mar()
924	921	{
925	922	// direct addressing is NOP
926		if (cpustate->op & 0x80)
	923	if (m_op & 0x80)
927	924	{
928		GET_ADDRESS(cpustate);
	925	GET_ADDRESS();
929	926	}
930	927	CYCLES(1);
931	928	}
932	929
933		static void op_sar(tms32051_state *cpustate)
	930	void tms32051_device::op_sar()
934	931	{
935		int arx = (cpustate->op >> 8) & 0x7;
936		UINT16 ar = cpustate->ar[arx];
937		UINT16 ea = GET_ADDRESS(cpustate);
938		DM_WRITE16(cpustate, ea, ar);
	932	int arx = (m_op >> 8) & 0x7;
	933	UINT16 ar = m_ar[arx];
	934	UINT16 ea = GET_ADDRESS();
	935	DM_WRITE16(ea, ar);
939	936
940	937	CYCLES(1);
941	938	}
942	939
943		static void op_sbrk(tms32051_state *cpustate)
	940	void tms32051_device::op_sbrk()
944	941	{
945		UINT16 imm = cpustate->op & 0xff;
946		UPDATE_AR(cpustate, cpustate->st0.arp, -imm);
	942	UINT16 imm = m_op & 0xff;
	943	UPDATE_AR(m_st0.arp, -imm);
947	944
948	945	CYCLES(1);
949	946	}
950	947
951	948	/*****************************************************************************/
952	949
953		static void op_b(tms32051_state *cpustate)
	950	void tms32051_device::op_b()
954	951	{
955		UINT16 pma = ROPCODE(cpustate);
956		GET_ADDRESS(cpustate);      // update AR/ARP
	952	UINT16 pma = ROPCODE();
	953	GET_ADDRESS();      // update AR/ARP
957	954
958		CHANGE_PC(cpustate, pma);
	955	CHANGE_PC(pma);
959	956	CYCLES(4);
960	957	}
961	958
962		static void op_bacc(tms32051_state *cpustate)
	959	void tms32051_device::op_bacc()
963	960	{
964		CHANGE_PC(cpustate, (UINT16)(cpustate->acc));
	961	CHANGE_PC((UINT16)(m_acc));
965	962
966	963	CYCLES(4);
967	964	}
968	965
969		static void op_baccd(tms32051_state *cpustate)
	966	void tms32051_device::op_baccd()
970	967	{
971		UINT16 pc = (UINT16)(cpustate->acc);
	968	UINT16 pc = (UINT16)(m_acc);
972	969
973		delay_slot(cpustate, cpustate->pc);
974		CHANGE_PC(cpustate, pc);
	970	delay_slot(m_pc);
	971	CHANGE_PC(pc);
975	972
976	973	CYCLES(2);
977	974	}
978	975
979		static void op_banz(tms32051_state *cpustate)
	976	void tms32051_device::op_banz()
980	977	{
981		UINT16 pma = ROPCODE(cpustate);
	978	UINT16 pma = ROPCODE();
982	979
983		if (cpustate->ar[cpustate->st0.arp] != 0)
	980	if (m_ar[m_st0.arp] != 0)
984	981	{
985		CHANGE_PC(cpustate, pma);
	982	CHANGE_PC(pma);
986	983	CYCLES(4);
987	984	}
988	985	else
r26840	r26841
990	987	CYCLES(2);
991	988	}
992	989
993		GET_ADDRESS(cpustate);      // modify AR/ARP
	990	GET_ADDRESS();      // modify AR/ARP
994	991	}
995	992
996		static void op_banzd(tms32051_state *cpustate)
	993	void tms32051_device::op_banzd()
997	994	{
998		fatalerror("32051: unimplemented op banzd at %08X\n", cpustate->pc-1);
	995	fatalerror("32051: unimplemented op banzd at %08X\n", m_pc-1);
999	996	}
1000	997
1001		static void op_bcnd(tms32051_state *cpustate)
	998	void tms32051_device::op_bcnd()
1002	999	{
1003		UINT16 pma = ROPCODE(cpustate);
	1000	UINT16 pma = ROPCODE();
1004	1001
1005		if (GET_ZLVC_CONDITION(cpustate, (cpustate->op >> 4) & 0xf, cpustate->op & 0xf) || GET_TP_CONDITION(cpustate, (cpustate->op >> 8) & 0x3))
	1002	if (GET_ZLVC_CONDITION((m_op >> 4) & 0xf, m_op & 0xf) || GET_TP_CONDITION((m_op >> 8) & 0x3))
1006	1003	{
1007		CHANGE_PC(cpustate, pma);
	1004	CHANGE_PC(pma);
1008	1005	CYCLES(4);
1009	1006	}
1010	1007	else
r26840	r26841
1013	1010	}
1014	1011	}
1015	1012
1016		static void op_bcndd(tms32051_state *cpustate)
	1013	void tms32051_device::op_bcndd()
1017	1014	{
1018		UINT16 pma = ROPCODE(cpustate);
	1015	UINT16 pma = ROPCODE();
1019	1016
1020		if (GET_ZLVC_CONDITION(cpustate, (cpustate->op >> 4) & 0xf, cpustate->op & 0xf) || GET_TP_CONDITION(cpustate, (cpustate->op >> 8) & 0x3))
	1017	if (GET_ZLVC_CONDITION((m_op >> 4) & 0xf, m_op & 0xf) || GET_TP_CONDITION((m_op >> 8) & 0x3))
1021	1018	{
1022		delay_slot(cpustate, cpustate->pc);
1023		CHANGE_PC(cpustate, pma);
	1019	delay_slot(m_pc);
	1020	CHANGE_PC(pma);
1024	1021	CYCLES(4);
1025	1022	}
1026	1023	else
r26840	r26841
1029	1026	}
1030	1027	}
1031	1028
1032		static void op_bd(tms32051_state *cpustate)
	1029	void tms32051_device::op_bd()
1033	1030	{
1034		UINT16 pma = ROPCODE(cpustate);
1035		GET_ADDRESS(cpustate);      // update AR/ARP
	1031	UINT16 pma = ROPCODE();
	1032	GET_ADDRESS();      // update AR/ARP
1036	1033
1037		delay_slot(cpustate, cpustate->pc);
1038		CHANGE_PC(cpustate, pma);
	1034	delay_slot(m_pc);
	1035	CHANGE_PC(pma);
1039	1036	CYCLES(2);
1040	1037	}
1041	1038
1042		static void op_cala(tms32051_state *cpustate)
	1039	void tms32051_device::op_cala()
1043	1040	{
1044		PUSH_STACK(cpustate, cpustate->pc);
	1041	PUSH_STACK(m_pc);
1045	1042
1046		CHANGE_PC(cpustate, cpustate->acc);
	1043	CHANGE_PC(m_acc);
1047	1044
1048	1045	CYCLES(4);
1049	1046	}
1050	1047
1051		static void op_calad(tms32051_state *cpustate)
	1048	void tms32051_device::op_calad()
1052	1049	{
1053		UINT16 pma = cpustate->acc;
1054		PUSH_STACK(cpustate, cpustate->pc+2);
	1050	UINT16 pma = m_acc;
	1051	PUSH_STACK(m_pc+2);
1055	1052
1056		delay_slot(cpustate, cpustate->pc);
1057		CHANGE_PC(cpustate, pma);
	1053	delay_slot(m_pc);
	1054	CHANGE_PC(pma);
1058	1055
1059	1056	CYCLES(4);
1060	1057	}
1061	1058
1062		static void op_call(tms32051_state *cpustate)
	1059	void tms32051_device::op_call()
1063	1060	{
1064		UINT16 pma = ROPCODE(cpustate);
1065		GET_ADDRESS(cpustate);      // update AR/ARP
1066		PUSH_STACK(cpustate, cpustate->pc);
	1061	UINT16 pma = ROPCODE();
	1062	GET_ADDRESS();      // update AR/ARP
	1063	PUSH_STACK(m_pc);
1067	1064
1068		CHANGE_PC(cpustate, pma);
	1065	CHANGE_PC(pma);
1069	1066
1070	1067	CYCLES(4);
1071	1068	}
1072	1069
1073		static void op_calld(tms32051_state *cpustate)
	1070	void tms32051_device::op_calld()
1074	1071	{
1075		UINT16 pma = ROPCODE(cpustate);
1076		GET_ADDRESS(cpustate);      // update AR/ARP
1077		PUSH_STACK(cpustate, cpustate->pc+2);
	1072	UINT16 pma = ROPCODE();
	1073	GET_ADDRESS();      // update AR/ARP
	1074	PUSH_STACK(m_pc+2);
1078	1075
1079		delay_slot(cpustate, cpustate->pc);
1080		CHANGE_PC(cpustate, pma);
	1076	delay_slot(m_pc);
	1077	CHANGE_PC(pma);
1081	1078
1082	1079	CYCLES(4);
1083	1080	}
1084	1081
1085		static void op_cc(tms32051_state *cpustate)
	1082	void tms32051_device::op_cc()
1086	1083	{
1087		fatalerror("32051: unimplemented op cc at %08X\n", cpustate->pc-1);
	1084	fatalerror("32051: unimplemented op cc at %08X\n", m_pc-1);
1088	1085	}
1089	1086
1090		static void op_ccd(tms32051_state *cpustate)
	1087	void tms32051_device::op_ccd()
1091	1088	{
1092		UINT16 pma = ROPCODE(cpustate);
	1089	UINT16 pma = ROPCODE();
1093	1090
1094		if (GET_ZLVC_CONDITION(cpustate, (cpustate->op >> 4) & 0xf, cpustate->op & 0xf) || GET_TP_CONDITION(cpustate, (cpustate->op >> 8) & 0x3))
	1091	if (GET_ZLVC_CONDITION((m_op >> 4) & 0xf, m_op & 0xf) || GET_TP_CONDITION((m_op >> 8) & 0x3))
1095	1092	{
1096		PUSH_STACK(cpustate, cpustate->pc+2);
	1093	PUSH_STACK(m_pc+2);
1097	1094
1098		delay_slot(cpustate, cpustate->pc);
1099		CHANGE_PC(cpustate, pma);
	1095	delay_slot(m_pc);
	1096	CHANGE_PC(pma);
1100	1097	}
1101	1098
1102	1099	CYCLES(2);
1103	1100	}
1104	1101
1105		static void op_intr(tms32051_state *cpustate)
	1102	void tms32051_device::op_intr()
1106	1103	{
1107		fatalerror("32051: unimplemented op intr at %08X\n", cpustate->pc-1);
	1104	fatalerror("32051: unimplemented op intr at %08X\n", m_pc-1);
1108	1105	}
1109	1106
1110		static void op_nmi(tms32051_state *cpustate)
	1107	void tms32051_device::op_nmi()
1111	1108	{
1112		fatalerror("32051: unimplemented op nmi at %08X\n", cpustate->pc-1);
	1109	fatalerror("32051: unimplemented op nmi at %08X\n", m_pc-1);
1113	1110	}
1114	1111
1115		static void op_retc(tms32051_state *cpustate)
	1112	void tms32051_device::op_retc()
1116	1113	{
1117		if ((cpustate->op & 0x3ff) == 0x300 || GET_ZLVC_CONDITION(cpustate, (cpustate->op >> 4) & 0xf, cpustate->op & 0xf) || GET_TP_CONDITION(cpustate, (cpustate->op >> 8) & 0x3))
	1114	if ((m_op & 0x3ff) == 0x300 || GET_ZLVC_CONDITION((m_op >> 4) & 0xf, m_op & 0xf) || GET_TP_CONDITION((m_op >> 8) & 0x3))
1118	1115	{
1119		UINT16 pc = POP_STACK(cpustate);
1120		CHANGE_PC(cpustate, pc);
	1116	UINT16 pc = POP_STACK();
	1117	CHANGE_PC(pc);
1121	1118	CYCLES(4);
1122	1119	}
1123	1120	else
r26840	r26841
1126	1123	}
1127	1124	}
1128	1125
1129		static void op_retcd(tms32051_state *cpustate)
	1126	void tms32051_device::op_retcd()
1130	1127	{
1131		if ((cpustate->op & 0x3ff) == 0x300 || GET_ZLVC_CONDITION(cpustate, (cpustate->op >> 4) & 0xf, cpustate->op & 0xf) || GET_TP_CONDITION(cpustate, (cpustate->op >> 8) & 0x3))
	1128	if ((m_op & 0x3ff) == 0x300 || GET_ZLVC_CONDITION((m_op >> 4) & 0xf, m_op & 0xf) || GET_TP_CONDITION((m_op >> 8) & 0x3))
1132	1129	{
1133		UINT16 pc = POP_STACK(cpustate);
1134		delay_slot(cpustate, cpustate->pc);
1135		CHANGE_PC(cpustate, pc);
	1130	UINT16 pc = POP_STACK();
	1131	delay_slot(m_pc);
	1132	CHANGE_PC(pc);
1136	1133	CYCLES(4);
1137	1134	}
1138	1135	else
r26840	r26841
1141	1138	}
1142	1139	}
1143	1140
1144		static void op_rete(tms32051_state *cpustate)
	1141	void tms32051_device::op_rete()
1145	1142	{
1146		UINT16 pc = POP_STACK(cpustate);
1147		CHANGE_PC(cpustate, pc);
	1143	UINT16 pc = POP_STACK();
	1144	CHANGE_PC(pc);
1148	1145
1149		cpustate->st0.intm = 0;
	1146	m_st0.intm = 0;
1150	1147
1151		restore_interrupt_context(cpustate);
	1148	restore_interrupt_context();
1152	1149
1153	1150	CYCLES(4);
1154	1151	}
1155	1152
1156		static void op_reti(tms32051_state *cpustate)
	1153	void tms32051_device::op_reti()
1157	1154	{
1158		fatalerror("32051: unimplemented op reti at %08X\n", cpustate->pc-1);
	1155	fatalerror("32051: unimplemented op reti at %08X\n", m_pc-1);
1159	1156	}
1160	1157
1161		static void op_trap(tms32051_state *cpustate)
	1158	void tms32051_device::op_trap()
1162	1159	{
1163		fatalerror("32051: unimplemented op trap at %08X\n", cpustate->pc-1);
	1160	fatalerror("32051: unimplemented op trap at %08X\n", m_pc-1);
1164	1161	}
1165	1162
1166		static void op_xc(tms32051_state *cpustate)
	1163	void tms32051_device::op_xc()
1167	1164	{
1168		if (GET_ZLVC_CONDITION(cpustate, (cpustate->op >> 4) & 0xf, cpustate->op & 0xf) || GET_TP_CONDITION(cpustate, (cpustate->op >> 8) & 0x3))
	1165	if (GET_ZLVC_CONDITION((m_op >> 4) & 0xf, m_op & 0xf) || GET_TP_CONDITION((m_op >> 8) & 0x3))
1169	1166	{
1170	1167	CYCLES(1);
1171	1168	}
1172	1169	else
1173	1170	{
1174		int n = ((cpustate->op >> 12) & 0x1) + 1;
1175		CHANGE_PC(cpustate, cpustate->pc + n);
	1171	int n = ((m_op >> 12) & 0x1) + 1;
	1172	CHANGE_PC(m_pc + n);
1176	1173	CYCLES(1 + n);
1177	1174	}
1178	1175	}
1179	1176
1180	1177	/*****************************************************************************/
1181	1178
1182		static void op_bldd_slimm(tms32051_state *cpustate)
	1179	void tms32051_device::op_bldd_slimm()
1183	1180	{
1184		UINT16 pfc = ROPCODE(cpustate);
	1181	UINT16 pfc = ROPCODE();
1185	1182
1186		while (cpustate->rptc > -1)
	1183	while (m_rptc > -1)
1187	1184	{
1188		UINT16 ea = GET_ADDRESS(cpustate);
1189		UINT16 data = DM_READ16(cpustate, pfc);
1190		DM_WRITE16(cpustate, ea, data);
	1185	UINT16 ea = GET_ADDRESS();
	1186	UINT16 data = DM_READ16(pfc);
	1187	DM_WRITE16(ea, data);
1191	1188	pfc++;
1192	1189	CYCLES(2);
1193	1190
1194		cpustate->rptc--;
	1191	m_rptc--;
1195	1192	};
1196	1193	}
1197	1194
1198		static void op_bldd_dlimm(tms32051_state *cpustate)
	1195	void tms32051_device::op_bldd_dlimm()
1199	1196	{
1200		UINT16 pfc = ROPCODE(cpustate);
	1197	UINT16 pfc = ROPCODE();
1201	1198
1202		while (cpustate->rptc > -1)
	1199	while (m_rptc > -1)
1203	1200	{
1204		UINT16 ea = GET_ADDRESS(cpustate);
1205		UINT16 data = DM_READ16(cpustate, ea);
1206		DM_WRITE16(cpustate, pfc, data);
	1201	UINT16 ea = GET_ADDRESS();
	1202	UINT16 data = DM_READ16(ea);
	1203	DM_WRITE16(pfc, data);
1207	1204	pfc++;
1208	1205	CYCLES(2);
1209	1206
1210		cpustate->rptc--;
	1207	m_rptc--;
1211	1208	};
1212	1209	}
1213	1210
1214		static void op_bldd_sbmar(tms32051_state *cpustate)
	1211	void tms32051_device::op_bldd_sbmar()
1215	1212	{
1216		fatalerror("32051: unimplemented op bldd sbmar at %08X\n", cpustate->pc-1);
	1213	fatalerror("32051: unimplemented op bldd sbmar at %08X\n", m_pc-1);
1217	1214	}
1218	1215
1219		static void op_bldd_dbmar(tms32051_state *cpustate)
	1216	void tms32051_device::op_bldd_dbmar()
1220	1217	{
1221		UINT16 pfc = cpustate->bmar;
	1218	UINT16 pfc = m_bmar;
1222	1219
1223		while (cpustate->rptc > -1)
	1220	while (m_rptc > -1)
1224	1221	{
1225		UINT16 ea = GET_ADDRESS(cpustate);
1226		UINT16 data = DM_READ16(cpustate, ea);
1227		DM_WRITE16(cpustate, pfc, data);
	1222	UINT16 ea = GET_ADDRESS();
	1223	UINT16 data = DM_READ16(ea);
	1224	DM_WRITE16(pfc, data);
1228	1225	pfc++;
1229	1226	CYCLES(2);
1230	1227
1231		cpustate->rptc--;
	1228	m_rptc--;
1232	1229	};
1233	1230	}
1234	1231
1235		static void op_bldp(tms32051_state *cpustate)
	1232	void tms32051_device::op_bldp()
1236	1233	{
1237		UINT16 pfc = cpustate->bmar;
	1234	UINT16 pfc = m_bmar;
1238	1235
1239		while (cpustate->rptc > -1)
	1236	while (m_rptc > -1)
1240	1237	{
1241		UINT16 ea = GET_ADDRESS(cpustate);
1242		UINT16 data = DM_READ16(cpustate, ea);
1243		PM_WRITE16(cpustate, pfc, data);
	1238	UINT16 ea = GET_ADDRESS();
	1239	UINT16 data = DM_READ16(ea);
	1240	PM_WRITE16(pfc, data);
1244	1241	pfc++;
1245	1242	CYCLES(1);
1246	1243
1247		cpustate->rptc--;
	1244	m_rptc--;
1248	1245	};
1249	1246	}
1250	1247
1251		static void op_blpd_bmar(tms32051_state *cpustate)
	1248	void tms32051_device::op_blpd_bmar()
1252	1249	{
1253		fatalerror("32051: unimplemented op bpld bmar at %08X\n", cpustate->pc-1);
	1250	fatalerror("32051: unimplemented op bpld bmar at %08X\n", m_pc-1);
1254	1251	}
1255	1252
1256		static void op_blpd_imm(tms32051_state *cpustate)
	1253	void tms32051_device::op_blpd_imm()
1257	1254	{
1258		UINT16 pfc = ROPCODE(cpustate);
	1255	UINT16 pfc = ROPCODE();
1259	1256
1260		while (cpustate->rptc > -1)
	1257	while (m_rptc > -1)
1261	1258	{
1262		UINT16 ea = GET_ADDRESS(cpustate);
1263		UINT16 data = PM_READ16(cpustate, pfc);
1264		DM_WRITE16(cpustate, ea, data);
	1259	UINT16 ea = GET_ADDRESS();
	1260	UINT16 data = PM_READ16(pfc);
	1261	DM_WRITE16(ea, data);
1265	1262	pfc++;
1266	1263	CYCLES(2);
1267	1264
1268		cpustate->rptc--;
	1265	m_rptc--;
1269	1266	};
1270	1267	}
1271	1268
1272	1269	/*****************************************************************************/
1273	1270
1274		static void op_dmov(tms32051_state *cpustate)
	1271	void tms32051_device::op_dmov()
1275	1272	{
1276		fatalerror("32051: unimplemented op dmov at %08X\n", cpustate->pc-1);
	1273	fatalerror("32051: unimplemented op dmov at %08X\n", m_pc-1);
1277	1274	}
1278	1275
1279		static void op_in(tms32051_state *cpustate)
	1276	void tms32051_device::op_in()
1280	1277	{
1281		fatalerror("32051: unimplemented op in at %08X\n", cpustate->pc-1);
	1278	fatalerror("32051: unimplemented op in at %08X\n", m_pc-1);
1282	1279	}
1283	1280
1284		static void op_lmmr(tms32051_state *cpustate)
	1281	void tms32051_device::op_lmmr()
1285	1282	{
1286		UINT16 pfc = ROPCODE(cpustate);
	1283	UINT16 pfc = ROPCODE();
1287	1284
1288		while (cpustate->rptc > -1)
	1285	while (m_rptc > -1)
1289	1286	{
1290		UINT16 ea = GET_ADDRESS(cpustate);
1291		UINT16 data = DM_READ16(cpustate, pfc);
1292		DM_WRITE16(cpustate, ea & 0x7f, data);
	1287	UINT16 ea = GET_ADDRESS();
	1288	UINT16 data = DM_READ16(pfc);
	1289	DM_WRITE16(ea & 0x7f, data);
1293	1290	pfc++;
1294	1291	CYCLES(2);
1295	1292
1296		cpustate->rptc--;
	1293	m_rptc--;
1297	1294	};
1298	1295	}
1299	1296
1300		static void op_out(tms32051_state *cpustate)
	1297	void tms32051_device::op_out()
1301	1298	{
1302		fatalerror("32051: unimplemented op out at %08X\n", cpustate->pc-1);
	1299	fatalerror("32051: unimplemented op out at %08X\n", m_pc-1);
1303	1300	}
1304	1301
1305		static void op_smmr(tms32051_state *cpustate)
	1302	void tms32051_device::op_smmr()
1306	1303	{
1307		UINT16 pfc = ROPCODE(cpustate);
	1304	UINT16 pfc = ROPCODE();
1308	1305
1309		while (cpustate->rptc > -1)
	1306	while (m_rptc > -1)
1310	1307	{
1311		UINT16 ea = GET_ADDRESS(cpustate);
1312		UINT16 data = DM_READ16(cpustate, ea & 0x7f);
1313		DM_WRITE16(cpustate, pfc, data);
	1308	UINT16 ea = GET_ADDRESS();
	1309	UINT16 data = DM_READ16(ea & 0x7f);
	1310	DM_WRITE16(pfc, data);
1314	1311	pfc++;
1315	1312	CYCLES(2);
1316	1313
1317		cpustate->rptc--;
	1314	m_rptc--;
1318	1315	};
1319	1316	}
1320	1317
1321		static void op_tblr(tms32051_state *cpustate)
	1318	void tms32051_device::op_tblr()
1322	1319	{
1323		UINT16 pfc = (UINT16)(cpustate->acc);
	1320	UINT16 pfc = (UINT16)(m_acc);
1324	1321
1325		while (cpustate->rptc > -1)
	1322	while (m_rptc > -1)
1326	1323	{
1327		UINT16 ea = GET_ADDRESS(cpustate);
1328		UINT16 data = PM_READ16(cpustate, pfc);
1329		DM_WRITE16(cpustate, ea, data);
	1324	UINT16 ea = GET_ADDRESS();
	1325	UINT16 data = PM_READ16(pfc);
	1326	DM_WRITE16(ea, data);
1330	1327	pfc++;
1331	1328	CYCLES(2);
1332	1329
1333		cpustate->rptc--;
	1330	m_rptc--;
1334	1331	};
1335	1332	}
1336	1333
1337		static void op_tblw(tms32051_state *cpustate)
	1334	void tms32051_device::op_tblw()
1338	1335	{
1339		UINT16 pfc = (UINT16)(cpustate->acc);
	1336	UINT16 pfc = (UINT16)(m_acc);
1340	1337
1341		while (cpustate->rptc > -1)
	1338	while (m_rptc > -1)
1342	1339	{
1343		UINT16 ea = GET_ADDRESS(cpustate);
1344		UINT16 data = DM_READ16(cpustate, ea);
1345		PM_WRITE16(cpustate, pfc, data);
	1340	UINT16 ea = GET_ADDRESS();
	1341	UINT16 data = DM_READ16(ea);
	1342	PM_WRITE16(pfc, data);
1346	1343	pfc++;
1347	1344	CYCLES(2);
1348	1345
1349		cpustate->rptc--;
	1346	m_rptc--;
1350	1347	};
1351	1348	}
1352	1349
1353	1350	/*****************************************************************************/
1354	1351
1355		static void op_apl_dbmr(tms32051_state *cpustate)
	1352	void tms32051_device::op_apl_dbmr()
1356	1353	{
1357		UINT16 ea = GET_ADDRESS(cpustate);
1358		UINT16 data = DM_READ16(cpustate, ea);
1359		data &= cpustate->dbmr;
1360		DM_WRITE16(cpustate, ea, data);
	1354	UINT16 ea = GET_ADDRESS();
	1355	UINT16 data = DM_READ16(ea);
	1356	data &= m_dbmr;
	1357	DM_WRITE16(ea, data);
1361	1358	CYCLES(1);
1362	1359	}
1363	1360
1364		static void op_apl_imm(tms32051_state *cpustate)
	1361	void tms32051_device::op_apl_imm()
1365	1362	{
1366		UINT16 ea = GET_ADDRESS(cpustate);
1367		UINT16 imm = ROPCODE(cpustate);
1368		UINT16 data = DM_READ16(cpustate, ea);
	1363	UINT16 ea = GET_ADDRESS();
	1364	UINT16 imm = ROPCODE();
	1365	UINT16 data = DM_READ16(ea);
1369	1366	data &= imm;
1370		DM_WRITE16(cpustate, ea, data);
	1367	DM_WRITE16(ea, data);
1371	1368	CYCLES(1);
1372	1369	}
1373	1370
1374		static void op_cpl_dbmr(tms32051_state *cpustate)
	1371	void tms32051_device::op_cpl_dbmr()
1375	1372	{
1376		fatalerror("32051: unimplemented op cpl dbmr at %08X\n", cpustate->pc-1);
	1373	fatalerror("32051: unimplemented op cpl dbmr at %08X\n", m_pc-1);
1377	1374	}
1378	1375
1379		static void op_cpl_imm(tms32051_state *cpustate)
	1376	void tms32051_device::op_cpl_imm()
1380	1377	{
1381		UINT16 imm = ROPCODE(cpustate);
1382		UINT16 ea = GET_ADDRESS(cpustate);
1383		UINT16 data = DM_READ16(cpustate, ea);
	1378	UINT16 imm = ROPCODE();
	1379	UINT16 ea = GET_ADDRESS();
	1380	UINT16 data = DM_READ16(ea);
1384	1381
1385		cpustate->st1.tc = (data == imm) ? 1 : 0;
	1382	m_st1.tc = (data == imm) ? 1 : 0;
1386	1383
1387	1384	CYCLES(1);
1388	1385	}
1389	1386
1390		static void op_opl_dbmr(tms32051_state *cpustate)
	1387	void tms32051_device::op_opl_dbmr()
1391	1388	{
1392		UINT16 ea = GET_ADDRESS(cpustate);
1393		UINT16 data = DM_READ16(cpustate, ea);
1394		data |= cpustate->dbmr;
1395		DM_WRITE16(cpustate, ea, data);
	1389	UINT16 ea = GET_ADDRESS();
	1390	UINT16 data = DM_READ16(ea);
	1391	data |= m_dbmr;
	1392	DM_WRITE16(ea, data);
1396	1393	CYCLES(1);
1397	1394	}
1398	1395
1399		static void op_opl_imm(tms32051_state *cpustate)
	1396	void tms32051_device::op_opl_imm()
1400	1397	{
1401		UINT16 ea = GET_ADDRESS(cpustate);
1402		UINT16 imm = ROPCODE(cpustate);
1403		UINT16 data = DM_READ16(cpustate, ea);
	1398	UINT16 ea = GET_ADDRESS();
	1399	UINT16 imm = ROPCODE();
	1400	UINT16 data = DM_READ16(ea);
1404	1401	data |= imm;
1405		DM_WRITE16(cpustate, ea, data);
	1402	DM_WRITE16(ea, data);
1406	1403	CYCLES(1);
1407	1404	}
1408	1405
1409		static void op_splk(tms32051_state *cpustate)
	1406	void tms32051_device::op_splk()
1410	1407	{
1411		UINT16 ea = GET_ADDRESS(cpustate);
1412		UINT16 imm = ROPCODE(cpustate);
	1408	UINT16 ea = GET_ADDRESS();
	1409	UINT16 imm = ROPCODE();
1413	1410
1414		DM_WRITE16(cpustate, ea, imm);
	1411	DM_WRITE16(ea, imm);
1415	1412
1416	1413	CYCLES(2);
1417	1414	}
1418	1415
1419		static void op_xpl_dbmr(tms32051_state *cpustate)
	1416	void tms32051_device::op_xpl_dbmr()
1420	1417	{
1421		fatalerror("32051: unimplemented op xpl dbmr at %08X\n", cpustate->pc-1);
	1418	fatalerror("32051: unimplemented op xpl dbmr at %08X\n", m_pc-1);
1422	1419	}
1423	1420
1424		static void op_xpl_imm(tms32051_state *cpustate)
	1421	void tms32051_device::op_xpl_imm()
1425	1422	{
1426		fatalerror("32051: unimplemented op xpl imm at %08X\n", cpustate->pc-1);
	1423	fatalerror("32051: unimplemented op xpl imm at %08X\n", m_pc-1);
1427	1424	}
1428	1425
1429		static void op_apac(tms32051_state *cpustate)
	1426	void tms32051_device::op_apac()
1430	1427	{
1431		INT32 spreg = PREG_PSCALER(cpustate, cpustate->preg);
1432		cpustate->acc = ADD(cpustate, cpustate->acc, spreg);
	1428	INT32 spreg = PREG_PSCALER(m_preg);
	1429	m_acc = ADD(m_acc, spreg);
1433	1430
1434	1431	CYCLES(1);
1435	1432	}
1436	1433
1437		static void op_lph(tms32051_state *cpustate)
	1434	void tms32051_device::op_lph()
1438	1435	{
1439		fatalerror("32051: unimplemented op lph at %08X\n", cpustate->pc-1);
	1436	fatalerror("32051: unimplemented op lph at %08X\n", m_pc-1);
1440	1437	}
1441	1438
1442		static void op_lt(tms32051_state *cpustate)
	1439	void tms32051_device::op_lt()
1443	1440	{
1444		UINT16 ea = GET_ADDRESS(cpustate);
1445		UINT16 data = DM_READ16(cpustate, ea);
	1441	UINT16 ea = GET_ADDRESS();
	1442	UINT16 data = DM_READ16(ea);
1446	1443
1447		cpustate->treg0 = data;
1448		if (cpustate->pmst.trm == 0)
	1444	m_treg0 = data;
	1445	if (m_pmst.trm == 0)
1449	1446	{
1450		cpustate->treg1 = data;
1451		cpustate->treg2 = data;
	1447	m_treg1 = data;
	1448	m_treg2 = data;
1452	1449	}
1453	1450
1454	1451	CYCLES(1);
1455	1452	}
1456	1453
1457		static void op_lta(tms32051_state *cpustate)
	1454	void tms32051_device::op_lta()
1458	1455	{
1459	1456	INT32 spreg;
1460		UINT16 ea = GET_ADDRESS(cpustate);
1461		UINT16 data = DM_READ16(cpustate, ea);
	1457	UINT16 ea = GET_ADDRESS();
	1458	UINT16 data = DM_READ16(ea);
1462	1459
1463		cpustate->treg0 = data;
1464		spreg = PREG_PSCALER(cpustate, cpustate->preg);
1465		cpustate->acc = ADD(cpustate, cpustate->acc, spreg);
1466		if (cpustate->pmst.trm == 0)
	1460	m_treg0 = data;
	1461	spreg = PREG_PSCALER(m_preg);
	1462	m_acc = ADD(m_acc, spreg);
	1463	if (m_pmst.trm == 0)
1467	1464	{
1468		cpustate->treg1 = data;
1469		cpustate->treg2 = data;
	1465	m_treg1 = data;
	1466	m_treg2 = data;
1470	1467	}
1471	1468
1472	1469	CYCLES(1);
1473	1470	}
1474	1471
1475		static void op_ltd(tms32051_state *cpustate)
	1472	void tms32051_device::op_ltd()
1476	1473	{
1477		fatalerror("32051: unimplemented op ltd at %08X\n", cpustate->pc-1);
	1474	fatalerror("32051: unimplemented op ltd at %08X\n", m_pc-1);
1478	1475	}
1479	1476
1480		static void op_ltp(tms32051_state *cpustate)
	1477	void tms32051_device::op_ltp()
1481	1478	{
1482		fatalerror("32051: unimplemented op ltp at %08X\n", cpustate->pc-1);
	1479	fatalerror("32051: unimplemented op ltp at %08X\n", m_pc-1);
1483	1480	}
1484	1481
1485		static void op_lts(tms32051_state *cpustate)
	1482	void tms32051_device::op_lts()
1486	1483	{
1487		fatalerror("32051: unimplemented op lts at %08X\n", cpustate->pc-1);
	1484	fatalerror("32051: unimplemented op lts at %08X\n", m_pc-1);
1488	1485	}
1489	1486
1490		static void op_mac(tms32051_state *cpustate)
	1487	void tms32051_device::op_mac()
1491	1488	{
1492		fatalerror("32051: unimplemented op mac at %08X\n", cpustate->pc-1);
	1489	fatalerror("32051: unimplemented op mac at %08X\n", m_pc-1);
1493	1490	}
1494	1491
1495		static void op_macd(tms32051_state *cpustate)
	1492	void tms32051_device::op_macd()
1496	1493	{
1497		fatalerror("32051: unimplemented op macd at %08X\n", cpustate->pc-1);
	1494	fatalerror("32051: unimplemented op macd at %08X\n", m_pc-1);
1498	1495	}
1499	1496
1500		static void op_madd(tms32051_state *cpustate)
	1497	void tms32051_device::op_madd()
1501	1498	{
1502		fatalerror("32051: unimplemented op madd at %08X\n", cpustate->pc-1);
	1499	fatalerror("32051: unimplemented op madd at %08X\n", m_pc-1);
1503	1500	}
1504	1501
1505		static void op_mads(tms32051_state *cpustate)
	1502	void tms32051_device::op_mads()
1506	1503	{
1507		fatalerror("32051: unimplemented op mads at %08X\n", cpustate->pc-1);
	1504	fatalerror("32051: unimplemented op mads at %08X\n", m_pc-1);
1508	1505	}
1509	1506
1510		static void op_mpy_mem(tms32051_state *cpustate)
	1507	void tms32051_device::op_mpy_mem()
1511	1508	{
1512		UINT16 ea = GET_ADDRESS(cpustate);
1513		INT16 data = DM_READ16(cpustate, ea);
	1509	UINT16 ea = GET_ADDRESS();
	1510	INT16 data = DM_READ16(ea);
1514	1511
1515		cpustate->preg = (INT32)(data) * (INT32)(INT16)(cpustate->treg0);
	1512	m_preg = (INT32)(data) * (INT32)(INT16)(m_treg0);
1516	1513
1517	1514	CYCLES(1);
1518	1515	}
1519	1516
1520		static void op_mpy_simm(tms32051_state *cpustate)
	1517	void tms32051_device::op_mpy_simm()
1521	1518	{
1522		fatalerror("32051: unimplemented op mpy simm at %08X\n", cpustate->pc-1);
	1519	fatalerror("32051: unimplemented op mpy simm at %08X\n", m_pc-1);
1523	1520	}
1524	1521
1525		static void op_mpy_limm(tms32051_state *cpustate)
	1522	void tms32051_device::op_mpy_limm()
1526	1523	{
1527		fatalerror("32051: unimplemented op mpy limm at %08X\n", cpustate->pc-1);
	1524	fatalerror("32051: unimplemented op mpy limm at %08X\n", m_pc-1);
1528	1525	}
1529	1526
1530		static void op_mpya(tms32051_state *cpustate)
	1527	void tms32051_device::op_mpya()
1531	1528	{
1532		fatalerror("32051: unimplemented op mpya at %08X\n", cpustate->pc-1);
	1529	fatalerror("32051: unimplemented op mpya at %08X\n", m_pc-1);
1533	1530	}
1534	1531
1535		static void op_mpys(tms32051_state *cpustate)
	1532	void tms32051_device::op_mpys()
1536	1533	{
1537		fatalerror("32051: unimplemented op mpys at %08X\n", cpustate->pc-1);
	1534	fatalerror("32051: unimplemented op mpys at %08X\n", m_pc-1);
1538	1535	}
1539	1536
1540		static void op_mpyu(tms32051_state *cpustate)
	1537	void tms32051_device::op_mpyu()
1541	1538	{
1542		fatalerror("32051: unimplemented op mpyu at %08X\n", cpustate->pc-1);
	1539	fatalerror("32051: unimplemented op mpyu at %08X\n", m_pc-1);
1543	1540	}
1544	1541
1545		static void op_pac(tms32051_state *cpustate)
	1542	void tms32051_device::op_pac()
1546	1543	{
1547		fatalerror("32051: unimplemented op pac at %08X\n", cpustate->pc-1);
	1544	fatalerror("32051: unimplemented op pac at %08X\n", m_pc-1);
1548	1545	}
1549	1546
1550		static void op_spac(tms32051_state *cpustate)
	1547	void tms32051_device::op_spac()
1551	1548	{
1552		fatalerror("32051: unimplemented op spac at %08X\n", cpustate->pc-1);
	1549	fatalerror("32051: unimplemented op spac at %08X\n", m_pc-1);
1553	1550	}
1554	1551
1555		static void op_sph(tms32051_state *cpustate)
	1552	void tms32051_device::op_sph()
1556	1553	{
1557		UINT16 ea = GET_ADDRESS(cpustate);
1558		UINT16 spreg = (UINT16)(PREG_PSCALER(cpustate, cpustate->preg) >> 16);
1559		DM_WRITE16(cpustate, ea, spreg);
	1554	UINT16 ea = GET_ADDRESS();
	1555	UINT16 spreg = (UINT16)(PREG_PSCALER(m_preg) >> 16);
	1556	DM_WRITE16(ea, spreg);
1560	1557
1561	1558	CYCLES(1);
1562	1559	}
1563	1560
1564		static void op_spl(tms32051_state *cpustate)
	1561	void tms32051_device::op_spl()
1565	1562	{
1566		fatalerror("32051: unimplemented op spl at %08X\n", cpustate->pc-1);
	1563	fatalerror("32051: unimplemented op spl at %08X\n", m_pc-1);
1567	1564	}
1568	1565
1569		static void op_spm(tms32051_state *cpustate)
	1566	void tms32051_device::op_spm()
1570	1567	{
1571		cpustate->st1.pm = cpustate->op & 0x3;
	1568	m_st1.pm = m_op & 0x3;
1572	1569
1573	1570	CYCLES(1);
1574	1571	}
1575	1572
1576		static void op_sqra(tms32051_state *cpustate)
	1573	void tms32051_device::op_sqra()
1577	1574	{
1578		fatalerror("32051: unimplemented op sqra at %08X\n", cpustate->pc-1);
	1575	fatalerror("32051: unimplemented op sqra at %08X\n", m_pc-1);
1579	1576	}
1580	1577
1581		static void op_sqrs(tms32051_state *cpustate)
	1578	void tms32051_device::op_sqrs()
1582	1579	{
1583		fatalerror("32051: unimplemented op sqrs at %08X\n", cpustate->pc-1);
	1580	fatalerror("32051: unimplemented op sqrs at %08X\n", m_pc-1);
1584	1581	}
1585	1582
1586		static void op_zpr(tms32051_state *cpustate)
	1583	void tms32051_device::op_zpr()
1587	1584	{
1588		fatalerror("32051: unimplemented op zpr at %08X\n", cpustate->pc-1);
	1585	fatalerror("32051: unimplemented op zpr at %08X\n", m_pc-1);
1589	1586	}
1590	1587
1591		static void op_bit(tms32051_state *cpustate)
	1588	void tms32051_device::op_bit()
1592	1589	{
1593		UINT16 ea = GET_ADDRESS(cpustate);
1594		UINT16 data = DM_READ16(cpustate, ea);
	1590	UINT16 ea = GET_ADDRESS();
	1591	UINT16 data = DM_READ16(ea);
1595	1592
1596		cpustate->st1.tc = (data >> (~cpustate->op >> 8 & 0xf)) & 1;
	1593	m_st1.tc = (data >> (~m_op >> 8 & 0xf)) & 1;
1597	1594
1598	1595	CYCLES(1);
1599	1596	}
1600	1597
1601		static void op_bitt(tms32051_state *cpustate)
	1598	void tms32051_device::op_bitt()
1602	1599	{
1603		UINT16 ea = GET_ADDRESS(cpustate);
1604		UINT16 data = DM_READ16(cpustate, ea);
	1600	UINT16 ea = GET_ADDRESS();
	1601	UINT16 data = DM_READ16(ea);
1605	1602
1606		cpustate->st1.tc = (data >> (~cpustate->treg2 & 0xf)) & 1;
	1603	m_st1.tc = (data >> (~m_treg2 & 0xf)) & 1;
1607	1604
1608	1605	CYCLES(1);
1609	1606	}
1610	1607
1611		static void op_clrc_ov(tms32051_state *cpustate)
	1608	void tms32051_device::op_clrc_ov()
1612	1609	{
1613		cpustate->st0.ovm = 0;
	1610	m_st0.ovm = 0;
1614	1611
1615	1612	CYCLES(1);
1616	1613	}
1617	1614
1618		static void op_clrc_ext(tms32051_state *cpustate)
	1615	void tms32051_device::op_clrc_ext()
1619	1616	{
1620		cpustate->st1.sxm = 0;
	1617	m_st1.sxm = 0;
1621	1618
1622	1619	CYCLES(1);
1623	1620	}
1624	1621
1625		static void op_clrc_hold(tms32051_state *cpustate)
	1622	void tms32051_device::op_clrc_hold()
1626	1623	{
1627		fatalerror("32051: unimplemented op clrc hold at %08X\n", cpustate->pc-1);
	1624	fatalerror("32051: unimplemented op clrc hold at %08X\n", m_pc-1);
1628	1625	}
1629	1626
1630		static void op_clrc_tc(tms32051_state *cpustate)
	1627	void tms32051_device::op_clrc_tc()
1631	1628	{
1632		fatalerror("32051: unimplemented op clrc tc at %08X\n", cpustate->pc-1);
	1629	fatalerror("32051: unimplemented op clrc tc at %08X\n", m_pc-1);
1633	1630	}
1634	1631
1635		static void op_clrc_carry(tms32051_state *cpustate)
	1632	void tms32051_device::op_clrc_carry()
1636	1633	{
1637		fatalerror("32051: unimplemented op clrc carry at %08X\n", cpustate->pc-1);
	1634	fatalerror("32051: unimplemented op clrc carry at %08X\n", m_pc-1);
1638	1635	}
1639	1636
1640		static void op_clrc_cnf(tms32051_state *cpustate)
	1637	void tms32051_device::op_clrc_cnf()
1641	1638	{
1642		cpustate->st1.cnf = 0;
	1639	m_st1.cnf = 0;
1643	1640
1644	1641	CYCLES(1);
1645	1642	}
1646	1643
1647		static void op_clrc_intm(tms32051_state *cpustate)
	1644	void tms32051_device::op_clrc_intm()
1648	1645	{
1649		cpustate->st0.intm = 0;
	1646	m_st0.intm = 0;
1650	1647
1651		check_interrupts(cpustate);
	1648	check_interrupts();
1652	1649
1653	1650	CYCLES(1);
1654	1651	}
1655	1652
1656		static void op_clrc_xf(tms32051_state *cpustate)
	1653	void tms32051_device::op_clrc_xf()
1657	1654	{
1658		fatalerror("32051: unimplemented op clrc xf at %08X\n", cpustate->pc-1);
	1655	fatalerror("32051: unimplemented op clrc xf at %08X\n", m_pc-1);
1659	1656	}
1660	1657
1661		static void op_idle(tms32051_state *cpustate)
	1658	void tms32051_device::op_idle()
1662	1659	{
1663		fatalerror("32051: unimplemented op idle at %08X\n", cpustate->pc-1);
	1660	fatalerror("32051: unimplemented op idle at %08X\n", m_pc-1);
1664	1661	}
1665	1662
1666		static void op_idle2(tms32051_state *cpustate)
	1663	void tms32051_device::op_idle2()
1667	1664	{
1668		fatalerror("32051: unimplemented op idle2 at %08X\n", cpustate->pc-1);
	1665	fatalerror("32051: unimplemented op idle2 at %08X\n", m_pc-1);
1669	1666	}
1670	1667
1671		static void op_lst_st0(tms32051_state *cpustate)
	1668	void tms32051_device::op_lst_st0()
1672	1669	{
1673		fatalerror("32051: unimplemented op lst st0 at %08X\n", cpustate->pc-1);
	1670	fatalerror("32051: unimplemented op lst st0 at %08X\n", m_pc-1);
1674	1671	}
1675	1672
1676		static void op_lst_st1(tms32051_state *cpustate)
	1673	void tms32051_device::op_lst_st1()
1677	1674	{
1678		fatalerror("32051: unimplemented op lst st1 at %08X\n", cpustate->pc-1);
	1675	fatalerror("32051: unimplemented op lst st1 at %08X\n", m_pc-1);
1679	1676	}
1680	1677
1681		static void op_pop(tms32051_state *cpustate)
	1678	void tms32051_device::op_pop()
1682	1679	{
1683		cpustate->acc = POP_STACK(cpustate);
	1680	m_acc = POP_STACK();
1684	1681
1685	1682	CYCLES(1);
1686	1683	}
1687	1684
1688		static void op_popd(tms32051_state *cpustate)
	1685	void tms32051_device::op_popd()
1689	1686	{
1690		fatalerror("32051: unimplemented op popd at %08X\n", cpustate->pc-1);
	1687	fatalerror("32051: unimplemented op popd at %08X\n", m_pc-1);
1691	1688	}
1692	1689
1693		static void op_pshd(tms32051_state *cpustate)
	1690	void tms32051_device::op_pshd()
1694	1691	{
1695		fatalerror("32051: unimplemented op pshd at %08X\n", cpustate->pc-1);
	1692	fatalerror("32051: unimplemented op pshd at %08X\n", m_pc-1);
1696	1693	}
1697	1694
1698		static void op_push(tms32051_state *cpustate)
	1695	void tms32051_device::op_push()
1699	1696	{
1700		fatalerror("32051: unimplemented op push at %08X\n", cpustate->pc-1);
	1697	fatalerror("32051: unimplemented op push at %08X\n", m_pc-1);
1701	1698	}
1702	1699
1703		static void op_rpt_mem(tms32051_state *cpustate)
	1700	void tms32051_device::op_rpt_mem()
1704	1701	{
1705		UINT16 ea = GET_ADDRESS(cpustate);
1706		UINT16 data = DM_READ16(cpustate, ea);
1707		cpustate->rptc = data;
1708		cpustate->rpt_start = cpustate->pc;
1709		cpustate->rpt_end = cpustate->pc;
	1702	UINT16 ea = GET_ADDRESS();
	1703	UINT16 data = DM_READ16(ea);
	1704	m_rptc = data;
	1705	m_rpt_start = m_pc;
	1706	m_rpt_end = m_pc;
1710	1707
1711	1708	CYCLES(1);
1712	1709	}
1713	1710
1714		static void op_rpt_limm(tms32051_state *cpustate)
	1711	void tms32051_device::op_rpt_limm()
1715	1712	{
1716		cpustate->rptc = (UINT16)ROPCODE(cpustate);
1717		cpustate->rpt_start = cpustate->pc;
1718		cpustate->rpt_end = cpustate->pc;
	1713	m_rptc = (UINT16)ROPCODE();
	1714	m_rpt_start = m_pc;
	1715	m_rpt_end = m_pc;
1719	1716
1720	1717	CYCLES(2);
1721	1718	}
1722	1719
1723		static void op_rpt_simm(tms32051_state *cpustate)
	1720	void tms32051_device::op_rpt_simm()
1724	1721	{
1725		cpustate->rptc = (cpustate->op & 0xff);
1726		cpustate->rpt_start = cpustate->pc;
1727		cpustate->rpt_end = cpustate->pc;
	1722	m_rptc = (m_op & 0xff);
	1723	m_rpt_start = m_pc;
	1724	m_rpt_end = m_pc;
1728	1725
1729	1726	CYCLES(1);
1730	1727	}
1731	1728
1732		static void op_rptb(tms32051_state *cpustate)
	1729	void tms32051_device::op_rptb()
1733	1730	{
1734		UINT16 pma = ROPCODE(cpustate);
1735		cpustate->pmst.braf = 1;
1736		cpustate->pasr = cpustate->pc;
1737		cpustate->paer = pma + 1;
	1731	UINT16 pma = ROPCODE();
	1732	m_pmst.braf = 1;
	1733	m_pasr = m_pc;
	1734	m_paer = pma + 1;
1738	1735
1739	1736	CYCLES(2);
1740	1737	}
1741	1738
1742		static void op_rptz(tms32051_state *cpustate)
	1739	void tms32051_device::op_rptz()
1743	1740	{
1744		fatalerror("32051: unimplemented op rptz at %08X\n", cpustate->pc-1);
	1741	fatalerror("32051: unimplemented op rptz at %08X\n", m_pc-1);
1745	1742	}
1746	1743
1747		static void op_setc_ov(tms32051_state *cpustate)
	1744	void tms32051_device::op_setc_ov()
1748	1745	{
1749		cpustate->st0.ovm = 1;
	1746	m_st0.ovm = 1;
1750	1747
1751	1748	CYCLES(1);
1752	1749	}
1753	1750
1754		static void op_setc_ext(tms32051_state *cpustate)
	1751	void tms32051_device::op_setc_ext()
1755	1752	{
1756		cpustate->st1.sxm = 1;
	1753	m_st1.sxm = 1;
1757	1754
1758	1755	CYCLES(1);
1759	1756	}
1760	1757
1761		static void op_setc_hold(tms32051_state *cpustate)
	1758	void tms32051_device::op_setc_hold()
1762	1759	{
1763		fatalerror("32051: unimplemented op setc hold at %08X\n", cpustate->pc-1);
	1760	fatalerror("32051: unimplemented op setc hold at %08X\n", m_pc-1);
1764	1761	}
1765	1762
1766		static void op_setc_tc(tms32051_state *cpustate)
	1763	void tms32051_device::op_setc_tc()
1767	1764	{
1768		fatalerror("32051: unimplemented op setc tc at %08X\n", cpustate->pc-1);
	1765	fatalerror("32051: unimplemented op setc tc at %08X\n", m_pc-1);
1769	1766	}
1770	1767
1771		static void op_setc_carry(tms32051_state *cpustate)
	1768	void tms32051_device::op_setc_carry()
1772	1769	{
1773		fatalerror("32051: unimplemented op setc carry at %08X\n", cpustate->pc-1);
	1770	fatalerror("32051: unimplemented op setc carry at %08X\n", m_pc-1);
1774	1771	}
1775	1772
1776		static void op_setc_xf(tms32051_state *cpustate)
	1773	void tms32051_device::op_setc_xf()
1777	1774	{
1778		fatalerror("32051: unimplemented op setc xf at %08X\n", cpustate->pc-1);
	1775	fatalerror("32051: unimplemented op setc xf at %08X\n", m_pc-1);
1779	1776	}
1780	1777
1781		static void op_setc_cnf(tms32051_state *cpustate)
	1778	void tms32051_device::op_setc_cnf()
1782	1779	{
1783		cpustate->st1.cnf = 1;
	1780	m_st1.cnf = 1;
1784	1781
1785	1782	CYCLES(1);
1786	1783	}
1787	1784
1788		static void op_setc_intm(tms32051_state *cpustate)
	1785	void tms32051_device::op_setc_intm()
1789	1786	{
1790		cpustate->st0.intm = 1;
	1787	m_st0.intm = 1;
1791	1788
1792		check_interrupts(cpustate);
	1789	check_interrupts();
1793	1790
1794	1791	CYCLES(1);
1795	1792	}
1796	1793
1797		static void op_sst_st0(tms32051_state *cpustate)
	1794	void tms32051_device::op_sst_st0()
1798	1795	{
1799		fatalerror("32051: unimplemented op sst st0 at %08X\n", cpustate->pc-1);
	1796	fatalerror("32051: unimplemented op sst st0 at %08X\n", m_pc-1);
1800	1797	}
1801	1798
1802		static void op_sst_st1(tms32051_state *cpustate)
	1799	void tms32051_device::op_sst_st1()
1803	1800	{
1804		fatalerror("32051: unimplemented op sst st1 at %08X\n", cpustate->pc-1);
	1801	fatalerror("32051: unimplemented op sst st1 at %08X\n", m_pc-1);
1805	1802	}

trunk/src/emu/cpu/tms32051/tms32051.c

r26840	r26841
46	46	TMS32051_AR7,
47	47	};
48	48
49		struct PMST
50		{
51		UINT16 iptr;
52		UINT16 avis;
53		UINT16 ovly;
54		UINT16 ram;
55		UINT16 mpmc;
56		UINT16 ndx;
57		UINT16 trm;
58		UINT16 braf;
59		};
60	49
61		struct ST0
62		{
63		UINT16 dp;
64		UINT16 intm;
65		UINT16 ovm;
66		UINT16 ov;
67		UINT16 arp;
68		};
	50	const device_type TMS32051 = &device_creator<tms32051_device>;
69	51
70		struct ST1
71		{
72		UINT16 arb;
73		UINT16 cnf;
74		UINT16 tc;
75		UINT16 sxm;
76		UINT16 c;
77		UINT16 hm;
78		UINT16 xf;
79		UINT16 pm;
80		};
81	52
82		struct tms32051_state
83		{
84		UINT16 pc;
85		UINT16 op;
86		INT32 acc;
87		INT32 accb;
88		INT32 preg;
89		UINT16 treg0;
90		UINT16 treg1;
91		UINT16 treg2;
92		UINT16 ar[8];
93		INT32 rptc;
	53	/**************************************************************************
	54	* Internal memory map
	55	**************************************************************************/
94	56
95		UINT16 bmar;
96		INT32 brcr;
97		UINT16 paer;
98		UINT16 pasr;
99		UINT16 indx;
100		UINT16 dbmr;
101		UINT16 arcr;
	57	static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 16, tms32051_device )
	58	AM_RANGE(0x0000, 0x1fff) AM_ROM                         // ROM          TODO: is off-chip if MP/_MC = 0
	59	AM_RANGE(0x2000, 0x23ff) AM_RAM AM_SHARE("saram")       // SARAM        TODO: is off-chip if RAM bit = 0
	60	AM_RANGE(0xfe00, 0xffff) AM_RAM AM_SHARE("daram_b0")    // DARAM B0     TODO: is off-chip if CNF = 0
	61	ADDRESS_MAP_END
102	62
103		ST0 st0;
104		ST1 st1;
105		PMST pmst;
	63	static ADDRESS_MAP_START( internal_data, AS_DATA, 16, tms32051_device )
	64	AM_RANGE(0x0000, 0x005f) AM_READWRITE(cpuregs_r, cpuregs_w)
	65	AM_RANGE(0x0060, 0x007f) AM_RAM                         // DARAM B2
	66	AM_RANGE(0x0100, 0x02ff) AM_RAM AM_SHARE("daram_b0")    // DARAM B0     TODO: is unconnected if CNF = 1
	67	AM_RANGE(0x0300, 0x04ff) AM_RAM                         // DARAM B1
	68	AM_RANGE(0x0800, 0x0bff) AM_RAM AM_SHARE("saram")       // SARAM        TODO: is off-chip if OVLY = 0
	69	ADDRESS_MAP_END
106	70
107		UINT16 ifr;
108		UINT16 imr;
109	71
110		UINT16 pcstack[8];
111		int pcstack_ptr;
	72	tms32051_device::tms32051_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	73	: cpu_device(mconfig, TMS32051, "TMS32051", tag, owner, clock, "tms32051", __FILE__)
	74	, m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(internal_pgm))
	75	, m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(internal_data))
	76	{
	77	}
112	78
113		UINT16 rpt_start, rpt_end;
114	79
115		UINT16 cbcr;
116		UINT16 cbsr1;
117		UINT16 cber1;
118		UINT16 cbsr2;
119		UINT16 cber2;
120
121		struct
122		{
123		int tddr;
124		int psc;
125		UINT16 tim;
126		UINT16 prd;
127		} timer;
128
129		struct
130		{
131		INT32 acc;
132		INT32 accb;
133		UINT16 arcr;
134		UINT16 indx;
135		PMST pmst;
136		INT32 preg;
137		ST0 st0;
138		ST1 st1;
139		INT32 treg0;
140		INT32 treg1;
141		INT32 treg2;
142		} shadow;
143
144		legacy_cpu_device *device;
145		address_space *program;
146		direct_read_data *direct;
147		address_space *data;
148		int icount;
149		};
150
151		INLINE tms32051_state *get_safe_token(device_t *device)
	80	offs_t tms32051_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
152	81	{
153		assert(device != NULL);
154		assert(device->type() == TMS32051);
155		return (tms32051_state *)downcast<legacy_cpu_device *>(device)->token();
	82	extern CPU_DISASSEMBLE( tms32051 );
	83	return CPU_DISASSEMBLE_NAME(tms32051)(this, buffer, pc, oprom, opram, options);
156	84	}
157	85
158		static void delay_slot(tms32051_state *cpustate, UINT16 startpc);
159		static void save_interrupt_context(tms32051_state *cpustate);
160		static void restore_interrupt_context(tms32051_state *cpustate);
161		static void check_interrupts(tms32051_state *cpustate);
162	86
	87	#define CYCLES(x)       (m_icount -= x)
163	88
164		#define CYCLES(x)       (cpustate->icount -= x)
	89	#define ROPCODE()       m_direct->read_decrypted_word((m_pc++) << 1)
165	90
166		#define ROPCODE(cpustate)       cpustate->direct->read_decrypted_word((cpustate->pc++) << 1)
167
168		INLINE void CHANGE_PC(tms32051_state *cpustate, UINT16 new_pc)
	91	void tms32051_device::CHANGE_PC(UINT16 new_pc)
169	92	{
170		cpustate->pc = new_pc;
	93	m_pc = new_pc;
171	94	}
172	95
173		INLINE UINT16 PM_READ16(tms32051_state *cpustate, UINT16 address)
	96	UINT16 tms32051_device::PM_READ16(UINT16 address)
174	97	{
175		return cpustate->program->read_word(address << 1);
	98	return m_program->read_word(address << 1);
176	99	}
177	100
178		INLINE void PM_WRITE16(tms32051_state *cpustate, UINT16 address, UINT16 data)
	101	void tms32051_device::PM_WRITE16(UINT16 address, UINT16 data)
179	102	{
180		cpustate->program->write_word(address << 1, data);
	103	m_program->write_word(address << 1, data);
181	104	}
182	105
183		INLINE UINT16 DM_READ16(tms32051_state *cpustate, UINT16 address)
	106	UINT16 tms32051_device::DM_READ16(UINT16 address)
184	107	{
185		return cpustate->data->read_word(address << 1);
	108	return m_data->read_word(address << 1);
186	109	}
187	110
188		INLINE void DM_WRITE16(tms32051_state *cpustate, UINT16 address, UINT16 data)
	111	void tms32051_device::DM_WRITE16(UINT16 address, UINT16 data)
189	112	{
190		cpustate->data->write_word(address << 1, data);
	113	m_data->write_word(address << 1, data);
191	114	}
192	115
193	116	#include "32051ops.c"
194	117	#include "32051ops.h"
195	118
196		static void op_group_be(tms32051_state *cpustate)
	119	void tms32051_device::op_group_be()
197	120	{
198		tms32051_opcode_table_be[cpustate->op & 0xff](cpustate);
	121	(this->*s_opcode_table_be[m_op & 0xff])();
199	122	}
200	123
201		static void op_group_bf(tms32051_state *cpustate)
	124	void tms32051_device::op_group_bf()
202	125	{
203		tms32051_opcode_table_bf[cpustate->op & 0xff](cpustate);
	126	(this->*s_opcode_table_bf[m_op & 0xff])();
204	127	}
205	128
206		static void delay_slot(tms32051_state *cpustate, UINT16 startpc)
	129	void tms32051_device::delay_slot(UINT16 startpc)
207	130	{
208		cpustate->op = ROPCODE(cpustate);
209		tms32051_opcode_table[cpustate->op >> 8](cpustate);
	131	m_op = ROPCODE();
	132	(this->*s_opcode_table[m_op >> 8])();
210	133
211		while (cpustate->pc - startpc < 2)
	134	while (m_pc - startpc < 2)
212	135	{
213		cpustate->op = ROPCODE(cpustate);
214		tms32051_opcode_table[cpustate->op >> 8](cpustate);
	136	m_op = ROPCODE();
	137	(this->*s_opcode_table[m_op >> 8])();
215	138	}
216	139	}
217	140
218	141	/*****************************************************************************/
219	142
220		static CPU_INIT( tms )
	143	void tms32051_device::device_start()
221	144	{
222		tms32051_state *cpustate = get_safe_token(device);
	145	m_program = &space(AS_PROGRAM);
	146	m_direct = &m_program->direct();
	147	m_data = &space(AS_DATA);
223	148
224		cpustate->device = device;
225		cpustate->program = &device->space(AS_PROGRAM);
226		cpustate->direct = &cpustate->program->direct();
227		cpustate->data = &device->space(AS_DATA);
	149	m_pcstack_ptr = 0;
	150	m_op = 0;
	151	m_acc = 0;
	152	m_accb = 0;
	153	m_preg = 0;
	154	m_treg0 = 0;
	155	m_treg1 = 0;
	156	m_treg2 = 0;
	157	memset(m_ar, 0, sizeof(m_ar));
	158	m_bmar = 0;
	159	m_brcr = 0;
	160	m_paer = 0;
	161	m_pasr = 0;
	162	m_indx = 0;
	163	m_dbmr = 0;
	164	m_arcr = 0;
	165	memset(&m_st0, 0, sizeof(m_st0));
	166	memset(&m_st1, 0, sizeof(m_st1));
	167	memset(&m_pmst, 0, sizeof(m_pmst));
	168	memset(m_pcstack, 0, sizeof(m_pcstack));
	169	m_imr = 0;
	170	m_cbsr1 = 0;
	171	m_cber1 = 0;
	172	m_cbsr2 = 0;
	173	m_cber2 = 0;
	174	memset(&m_timer, 0, sizeof(m_timer));
228	175
229		cpustate->pcstack_ptr = 0;
	176	state_add( TMS32051_PC,    "PC", m_pc).formatstr("%04X");
	177	state_add( TMS32051_ACC,   "ACC", m_acc).formatstr("%08X");
	178	state_add( TMS32051_ACCB,  "ACCB", m_accb).formatstr("%08X");
	179	state_add( TMS32051_PREG,  "PREG", m_preg).formatstr("%08X");
	180	state_add( TMS32051_TREG0, "TREG0", m_treg0).formatstr("%04X");
	181	state_add( TMS32051_TREG1, "TREG1", m_treg1).formatstr("%04X");
	182	state_add( TMS32051_TREG2, "TREG2", m_treg2).formatstr("%04X");
	183	state_add( TMS32051_BMAR,  "BMAR", m_bmar).formatstr("%08X");
	184	state_add( TMS32051_RPTC,  "RPTC", m_rptc).formatstr("%08X");
	185	state_add( TMS32051_BRCR,  "BRCR", m_brcr).formatstr("%08X");
	186	state_add( TMS32051_INDX,  "INDX", m_indx).formatstr("%04X");
	187	state_add( TMS32051_DBMR,  "DBMR", m_dbmr).formatstr("%04X");
	188	state_add( TMS32051_ARCR,  "ARCR", m_arcr).formatstr("%04X");
	189	state_add( TMS32051_DP,    "DP", m_st0.dp).formatstr("%04X");
	190	state_add( TMS32051_ARP,   "ARP", m_st0.arp).formatstr("%04X");
	191	state_add( TMS32051_ARB,   "ARB", m_st1.arb).formatstr("%04X");
	192	state_add( TMS32051_AR0,   "AR0", m_ar[0]).formatstr("%04X");
	193	state_add( TMS32051_AR1,   "AR1", m_ar[1]).formatstr("%04X");
	194	state_add( TMS32051_AR2,   "AR2", m_ar[2]).formatstr("%04X");
	195	state_add( TMS32051_AR3,   "AR3", m_ar[3]).formatstr("%04X");
	196	state_add( TMS32051_AR4,   "AR4", m_ar[4]).formatstr("%04X");
	197	state_add( TMS32051_AR5,   "AR5", m_ar[5]).formatstr("%04X");
	198	state_add( TMS32051_AR6,   "AR6", m_ar[6]).formatstr("%04X");
	199	state_add( TMS32051_AR7,   "AR7", m_ar[7]).formatstr("%04X");
	200
	201	state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%04X").noshow();
	202
	203	m_icountptr = &m_icount;
230	204	}
231	205
232		static CPU_RESET( tms )
	206	void tms32051_device::device_reset()
233	207	{
234		tms32051_state *cpustate = get_safe_token(device);
235
236	208	// reset registers
237		cpustate->st0.intm  = 1;
238		cpustate->st0.ov    = 0;
239		cpustate->st1.c     = 1;
240		cpustate->st1.cnf   = 0;
241		cpustate->st1.hm    = 1;
242		cpustate->st1.pm    = 0;
243		cpustate->st1.sxm   = 1;
244		cpustate->st1.xf    = 1;
245		cpustate->pmst.avis = 0;
246		cpustate->pmst.braf = 0;
247		cpustate->pmst.iptr = 0;
248		cpustate->pmst.ndx  = 0;
249		cpustate->pmst.ovly = 0;
250		cpustate->pmst.ram  = 0;
251		cpustate->pmst.mpmc = 0; // TODO: this is set to logical pin state at reset
252		cpustate->pmst.trm  = 0;
253		cpustate->ifr       = 0;
254		cpustate->cbcr      = 0;
255		cpustate->rptc      = -1;
	209	m_st0.intm  = 1;
	210	m_st0.ov    = 0;
	211	m_st1.c     = 1;
	212	m_st1.cnf   = 0;
	213	m_st1.hm    = 1;
	214	m_st1.pm    = 0;
	215	m_st1.sxm   = 1;
	216	m_st1.xf    = 1;
	217	m_pmst.avis = 0;
	218	m_pmst.braf = 0;
	219	m_pmst.iptr = 0;
	220	m_pmst.ndx  = 0;
	221	m_pmst.ovly = 0;
	222	m_pmst.ram  = 0;
	223	m_pmst.mpmc = 0; // TODO: this is set to logical pin state at reset
	224	m_pmst.trm  = 0;
	225	m_ifr       = 0;
	226	m_cbcr      = 0;
	227	m_rptc      = -1;
256	228
257	229	// simulate internal rom boot loader (can be removed when the dsp rom(s) is dumped)
258		cpustate->st0.intm  = 1;
259		cpustate->st1.cnf   = 1;
260		cpustate->pmst.ram  = 1;
261		cpustate->pmst.ovly = 0;
	230	m_st0.intm  = 1;
	231	m_st1.cnf   = 1;
	232	m_pmst.ram  = 1;
	233	m_pmst.ovly = 0;
262	234
263	235	int i;
264	236	UINT16 src, dst, length;
265	237
266	238	src = 0x7800;
267		dst = DM_READ16(cpustate, src++);
268		length = DM_READ16(cpustate, src++);
	239	dst = DM_READ16(src++);
	240	length = DM_READ16(src++);
269	241
270		CHANGE_PC(cpustate, dst);
	242	CHANGE_PC(dst);
271	243
272	244	/* TODO: if you soft reset on Taito JC it tries to do a 0x7802->0x9007 (0xff00) transfer. */
273	245	for (i=0; i < (length & 0x7ff); i++)
274	246	{
275		UINT16 data = DM_READ16(cpustate, src++);
276		PM_WRITE16(cpustate, dst++, data);
	247	UINT16 data = DM_READ16(src++);
	248	PM_WRITE16(dst++, data);
277	249	}
278	250	}
279	251
280		static void check_interrupts(tms32051_state *cpustate)
	252	void tms32051_device::check_interrupts()
281	253	{
282	254	int i;
283	255
284		if (cpustate->st0.intm == 0 && cpustate->ifr != 0)
	256	if (m_st0.intm == 0 && m_ifr != 0)
285	257	{
286	258	for (i=0; i < 16; i++)
287	259	{
288		if (cpustate->ifr & (1 << i))
	260	if (m_ifr & (1 << i))
289	261	{
290		cpustate->st0.intm = 1;
291		PUSH_STACK(cpustate, cpustate->pc);
	262	m_st0.intm = 1;
	263	PUSH_STACK(m_pc);
292	264
293		cpustate->pc = (cpustate->pmst.iptr << 11) | ((i+1) << 1);
294		cpustate->ifr &= ~(1 << i);
	265	m_pc = (m_pmst.iptr << 11) | ((i+1) << 1);
	266	m_ifr &= ~(1 << i);
295	267
296		save_interrupt_context(cpustate);
	268	save_interrupt_context();
297	269	break;
298	270	}
299	271	}
300	272	}
301	273	}
302	274
303		static void save_interrupt_context(tms32051_state *cpustate)
	275	void tms32051_device::save_interrupt_context()
304	276	{
305		cpustate->shadow.acc        = cpustate->acc;
306		cpustate->shadow.accb       = cpustate->accb;
307		cpustate->shadow.arcr       = cpustate->arcr;
308		cpustate->shadow.indx       = cpustate->indx;
309		cpustate->shadow.preg       = cpustate->preg;
310		cpustate->shadow.treg0  = cpustate->treg0;
311		cpustate->shadow.treg1  = cpustate->treg1;
312		cpustate->shadow.treg2  = cpustate->treg2;
313		memcpy(&cpustate->shadow.pmst, &cpustate->pmst, sizeof(PMST));
314		memcpy(&cpustate->shadow.st0, &cpustate->st0, sizeof(ST0));
315		memcpy(&cpustate->shadow.st1, &cpustate->st1, sizeof(ST1));
	277	m_shadow.acc        = m_acc;
	278	m_shadow.accb       = m_accb;
	279	m_shadow.arcr       = m_arcr;
	280	m_shadow.indx       = m_indx;
	281	m_shadow.preg       = m_preg;
	282	m_shadow.treg0  = m_treg0;
	283	m_shadow.treg1  = m_treg1;
	284	m_shadow.treg2  = m_treg2;
	285	memcpy(&m_shadow.pmst, &m_pmst, sizeof(TMS32051_PMST));
	286	memcpy(&m_shadow.st0, &m_st0, sizeof(TMS32051_ST0));
	287	memcpy(&m_shadow.st1, &m_st1, sizeof(TMS32051_ST1));
316	288	}
317	289
318		static void restore_interrupt_context(tms32051_state *cpustate)
	290	void tms32051_device::restore_interrupt_context()
319	291	{
320		cpustate->acc               = cpustate->shadow.acc;
321		cpustate->accb          = cpustate->shadow.accb;
322		cpustate->arcr          = cpustate->shadow.arcr;
323		cpustate->indx          = cpustate->shadow.indx;
324		cpustate->preg          = cpustate->shadow.preg;
325		cpustate->treg0         = cpustate->shadow.treg0;
326		cpustate->treg1         = cpustate->shadow.treg1;
327		cpustate->treg2         = cpustate->shadow.treg2;
328		memcpy(&cpustate->pmst, &cpustate->shadow.pmst, sizeof(PMST));
329		memcpy(&cpustate->st0, &cpustate->shadow.st0, sizeof(ST0));
330		memcpy(&cpustate->st1, &cpustate->shadow.st1, sizeof(ST1));
	292	m_acc               = m_shadow.acc;
	293	m_accb          = m_shadow.accb;
	294	m_arcr          = m_shadow.arcr;
	295	m_indx          = m_shadow.indx;
	296	m_preg          = m_shadow.preg;
	297	m_treg0         = m_shadow.treg0;
	298	m_treg1         = m_shadow.treg1;
	299	m_treg2         = m_shadow.treg2;
	300	memcpy(&m_pmst, &m_shadow.pmst, sizeof(TMS32051_PMST));
	301	memcpy(&m_st0, &m_shadow.st0, sizeof(TMS32051_ST0));
	302	memcpy(&m_st1, &m_shadow.st1, sizeof(TMS32051_ST1));
331	303	}
332	304
333		static void tms_interrupt(tms32051_state *cpustate, int irq)
	305	void tms32051_device::execute_set_input(int irq, int state)
334	306	{
335		if ((cpustate->imr & (1 << irq)) != 0)
	307	if ( state == ASSERT_LINE )
336	308	{
337		cpustate->ifr |= 1 << irq;
338		}
	309	if ((m_imr & (1 << irq)) != 0)
	310	{
	311	m_ifr |= 1 << irq;
	312	}
339	313
340		check_interrupts(cpustate);
	314	check_interrupts();
	315	}
341	316	}
342	317
343		static CPU_EXIT( tms )
344		{
345		/* TODO */
346		}
347	318
348		static CPU_EXECUTE( tms )
	319	void tms32051_device::execute_run()
349	320	{
350		tms32051_state *cpustate = get_safe_token(device);
351
352		while(cpustate->icount > 0)
	321	while(m_icount > 0)
353	322	{
354	323	UINT16 ppc;
355	324
356	325	// handle block repeat
357		if (cpustate->pmst.braf)
	326	if (m_pmst.braf)
358	327	{
359		if (cpustate->pc == cpustate->paer)
	328	if (m_pc == m_paer)
360	329	{
361		if (cpustate->brcr > 0)
	330	if (m_brcr > 0)
362	331	{
363		CHANGE_PC(cpustate, cpustate->pasr);
	332	CHANGE_PC(m_pasr);
364	333	}
365	334
366		cpustate->brcr--;
367		if (cpustate->brcr <= 0)
	335	m_brcr--;
	336	if (m_brcr <= 0)
368	337	{
369		cpustate->pmst.braf = 0;
	338	m_pmst.braf = 0;
370	339	}
371	340	}
372	341	}
373	342
374		ppc = cpustate->pc;
375		debugger_instruction_hook(device, cpustate->pc);
	343	ppc = m_pc;
	344	debugger_instruction_hook(this, m_pc);
376	345
377		cpustate->op = ROPCODE(cpustate);
378		tms32051_opcode_table[cpustate->op >> 8](cpustate);
	346	m_op = ROPCODE();
	347	(this->*s_opcode_table[m_op >> 8])();
379	348
380	349	// handle single repeat
381		if (cpustate->rptc > 0)
	350	if (m_rptc > 0)
382	351	{
383		if (ppc == cpustate->rpt_end)
	352	if (ppc == m_rpt_end)
384	353	{
385		CHANGE_PC(cpustate, cpustate->rpt_start);
386		cpustate->rptc--;
	354	CHANGE_PC(m_rpt_start);
	355	m_rptc--;
387	356	}
388	357	}
389	358	else
390	359	{
391		cpustate->rptc = 0;
	360	m_rptc = 0;
392	361	}
393	362
394		cpustate->timer.psc--;
395		if (cpustate->timer.psc <= 0)
	363	m_timer.psc--;
	364	if (m_timer.psc <= 0)
396	365	{
397		cpustate->timer.psc = cpustate->timer.tddr;
398		cpustate->timer.tim--;
399		if (cpustate->timer.tim <= 0)
	366	m_timer.psc = m_timer.tddr;
	367	m_timer.tim--;
	368	if (m_timer.tim <= 0)
400	369	{
401	370	// reset timer
402		cpustate->timer.tim = cpustate->timer.prd;
	371	m_timer.tim = m_timer.prd;
403	372
404		tms_interrupt(cpustate, INTERRUPT_TINT);
	373	execute_set_input(INTERRUPT_TINT, ASSERT_LINE);
405	374	}
406	375	}
407	376	}
r26840	r26841
410	379
411	380	/*****************************************************************************/
412	381
413		static READ16_HANDLER( cpuregs_r )
	382	READ16_MEMBER( tms32051_device::cpuregs_r )
414	383	{
415		tms32051_state *cpustate = get_safe_token(&space.device());
416
417	384	switch (offset)
418	385	{
419		case 0x04:  return cpustate->imr;
420		case 0x06:  return cpustate->ifr;
	386	case 0x04:  return m_imr;
	387	case 0x06:  return m_ifr;
421	388
422	389	case 0x07:      // PMST
423	390	{
424	391	UINT16 r = 0;
425		r |= cpustate->pmst.iptr << 11;
426		r |= cpustate->pmst.avis << 7;
427		r |= cpustate->pmst.ovly << 5;
428		r |= cpustate->pmst.ram << 4;
429		r |= cpustate->pmst.mpmc << 3;
430		r |= cpustate->pmst.ndx << 2;
431		r |= cpustate->pmst.trm << 1;
432		r |= cpustate->pmst.braf << 0;
	392	r |= m_pmst.iptr << 11;
	393	r |= m_pmst.avis << 7;
	394	r |= m_pmst.ovly << 5;
	395	r |= m_pmst.ram << 4;
	396	r |= m_pmst.mpmc << 3;
	397	r |= m_pmst.ndx << 2;
	398	r |= m_pmst.trm << 1;
	399	r |= m_pmst.braf << 0;
433	400	return r;
434	401	}
435	402
436		case 0x09:  return cpustate->brcr;
437		case 0x10:  return cpustate->ar[0];
438		case 0x11:  return cpustate->ar[1];
439		case 0x12:  return cpustate->ar[2];
440		case 0x13:  return cpustate->ar[3];
441		case 0x14:  return cpustate->ar[4];
442		case 0x15:  return cpustate->ar[5];
443		case 0x16:  return cpustate->ar[6];
444		case 0x17:  return cpustate->ar[7];
445		case 0x1e:  return cpustate->cbcr;
446		case 0x1f:  return cpustate->bmar;
447		case 0x24:  return cpustate->timer.tim;
448		case 0x25:  return cpustate->timer.prd;
	403	case 0x09:  return m_brcr;
	404	case 0x10:  return m_ar[0];
	405	case 0x11:  return m_ar[1];
	406	case 0x12:  return m_ar[2];
	407	case 0x13:  return m_ar[3];
	408	case 0x14:  return m_ar[4];
	409	case 0x15:  return m_ar[5];
	410	case 0x16:  return m_ar[6];
	411	case 0x17:  return m_ar[7];
	412	case 0x1e:  return m_cbcr;
	413	case 0x1f:  return m_bmar;
	414	case 0x24:  return m_timer.tim;
	415	case 0x25:  return m_timer.prd;
449	416
450	417	case 0x26:      // TCR
451	418	{
452	419	UINT16 r = 0;
453		r |= (cpustate->timer.psc & 0xf) << 6;
454		r |= (cpustate->timer.tddr & 0xf);
	420	r |= (m_timer.psc & 0xf) << 6;
	421	r |= (m_timer.tddr & 0xf);
455	422	return r;
456	423	}
457	424
458	425	case 0x28:  return 0;   // PDWSR
459	426	default:
460	427	if(!space.debugger_access())
461		fatalerror("32051: cpuregs_r: unimplemented memory-mapped register %02X at %04X\n", offset, cpustate->pc-1);
	428	fatalerror("32051: cpuregs_r: unimplemented memory-mapped register %02X at %04X\n", offset, m_pc-1);
462	429	}
463	430
464	431	return 0;
465	432	}
466	433
467		static WRITE16_HANDLER( cpuregs_w )
	434	WRITE16_MEMBER( tms32051_device::cpuregs_w )
468	435	{
469		tms32051_state *cpustate = get_safe_token(&space.device());
470
471	436	switch (offset)
472	437	{
473	438	case 0x00:  break;
474		case 0x04:  cpustate->imr = data; break;
	439	case 0x04:  m_imr = data; break;
475	440	case 0x06:      // IFR
476	441	{
477	442	int i;
r26840	r26841
479	444	{
480	445	if (data & (1 << i))
481	446	{
482		cpustate->ifr &= ~(1 << i);
	447	m_ifr &= ~(1 << i);
483	448	}
484	449	}
485	450	break;
r26840	r26841
487	452
488	453	case 0x07:      // PMST
489	454	{
490		cpustate->pmst.iptr = (data >> 11) & 0x1f;
491		cpustate->pmst.avis = (data & 0x80) ? 1 : 0;
492		cpustate->pmst.ovly = (data & 0x20) ? 1 : 0;
493		cpustate->pmst.ram = (data & 0x10) ? 1 : 0;
494		cpustate->pmst.mpmc = (data & 0x08) ? 1 : 0;
495		cpustate->pmst.ndx = (data & 0x04) ? 1 : 0;
496		cpustate->pmst.trm = (data & 0x02) ? 1 : 0;
497		cpustate->pmst.braf = (data & 0x01) ? 1 : 0;
	455	m_pmst.iptr = (data >> 11) & 0x1f;
	456	m_pmst.avis = (data & 0x80) ? 1 : 0;
	457	m_pmst.ovly = (data & 0x20) ? 1 : 0;
	458	m_pmst.ram = (data & 0x10) ? 1 : 0;
	459	m_pmst.mpmc = (data & 0x08) ? 1 : 0;
	460	m_pmst.ndx = (data & 0x04) ? 1 : 0;
	461	m_pmst.trm = (data & 0x02) ? 1 : 0;
	462	m_pmst.braf = (data & 0x01) ? 1 : 0;
498	463	break;
499	464	}
500	465
501		case 0x09:  cpustate->brcr = data; break;
502		case 0x0e:  cpustate->treg2 = data; break;
503		case 0x0f:  cpustate->dbmr = data; break;
504		case 0x10:  cpustate->ar[0] = data; break;
505		case 0x11:  cpustate->ar[1] = data; break;
506		case 0x12:  cpustate->ar[2] = data; break;
507		case 0x13:  cpustate->ar[3] = data; break;
508		case 0x14:  cpustate->ar[4] = data; break;
509		case 0x15:  cpustate->ar[5] = data; break;
510		case 0x16:  cpustate->ar[6] = data; break;
511		case 0x17:  cpustate->ar[7] = data; break;
512		case 0x18:  cpustate->indx = data; break;
513		case 0x19:  cpustate->arcr = data; break;
514		case 0x1a:  cpustate->cbsr1 = data; break;
515		case 0x1b:  cpustate->cber1 = data; break;
516		case 0x1c:  cpustate->cbsr2 = data; break;
517		case 0x1d:  cpustate->cber2 = data; break;
518		case 0x1e:  cpustate->cbcr = data; break;
519		case 0x1f:  cpustate->bmar = data; break;
520		case 0x24:  cpustate->timer.tim = data; break;
521		case 0x25:  cpustate->timer.prd = data; break;
	466	case 0x09:  m_brcr = data; break;
	467	case 0x0e:  m_treg2 = data; break;
	468	case 0x0f:  m_dbmr = data; break;
	469	case 0x10:  m_ar[0] = data; break;
	470	case 0x11:  m_ar[1] = data; break;
	471	case 0x12:  m_ar[2] = data; break;
	472	case 0x13:  m_ar[3] = data; break;
	473	case 0x14:  m_ar[4] = data; break;
	474	case 0x15:  m_ar[5] = data; break;
	475	case 0x16:  m_ar[6] = data; break;
	476	case 0x17:  m_ar[7] = data; break;
	477	case 0x18:  m_indx = data; break;
	478	case 0x19:  m_arcr = data; break;
	479	case 0x1a:  m_cbsr1 = data; break;
	480	case 0x1b:  m_cber1 = data; break;
	481	case 0x1c:  m_cbsr2 = data; break;
	482	case 0x1d:  m_cber2 = data; break;
	483	case 0x1e:  m_cbcr = data; break;
	484	case 0x1f:  m_bmar = data; break;
	485	case 0x24:  m_timer.tim = data; break;
	486	case 0x25:  m_timer.prd = data; break;
522	487
523	488	case 0x26:      // TCR
524	489	{
525		cpustate->timer.tddr = data & 0xf;
526		cpustate->timer.psc = (data >> 6) & 0xf;
	490	m_timer.tddr = data & 0xf;
	491	m_timer.psc = (data >> 6) & 0xf;
527	492
528	493	if (data & 0x20)
529	494	{
530		cpustate->timer.tim = cpustate->timer.prd;
531		cpustate->timer.psc = cpustate->timer.tddr;
	495	m_timer.tim = m_timer.prd;
	496	m_timer.psc = m_timer.tddr;
532	497	}
533	498	break;
534	499	}
r26840	r26841
536	501	case 0x28:  break;      // PDWSR
537	502	default:
538	503	if(!space.debugger_access())
539		fatalerror("32051: cpuregs_w: unimplemented memory-mapped register %02X, data %04X at %04X\n", offset, data, cpustate->pc-1);
	504	fatalerror("32051: cpuregs_w: unimplemented memory-mapped register %02X, data %04X at %04X\n", offset, data, m_pc-1);
540	505	}
541	506	}
542	507
543		/**************************************************************************
544		* Internal memory map
545		**************************************************************************/
546	508
547		static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 16, legacy_cpu_device )
548		AM_RANGE(0x0000, 0x1fff) AM_ROM                         // ROM          TODO: is off-chip if MP/_MC = 0
549		AM_RANGE(0x2000, 0x23ff) AM_RAM AM_SHARE("saram")       // SARAM        TODO: is off-chip if RAM bit = 0
550		AM_RANGE(0xfe00, 0xffff) AM_RAM AM_SHARE("daram_b0")    // DARAM B0     TODO: is off-chip if CNF = 0
551		ADDRESS_MAP_END
	509	bool tms32051_device::memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value)
552	510
553		static ADDRESS_MAP_START( internal_data, AS_DATA, 16, legacy_cpu_device )
554		AM_RANGE(0x0000, 0x005f) AM_READWRITE_LEGACY(cpuregs_r, cpuregs_w)
555		AM_RANGE(0x0060, 0x007f) AM_RAM                         // DARAM B2
556		AM_RANGE(0x0100, 0x02ff) AM_RAM AM_SHARE("daram_b0")    // DARAM B0     TODO: is unconnected if CNF = 1
557		AM_RANGE(0x0300, 0x04ff) AM_RAM                         // DARAM B1
558		AM_RANGE(0x0800, 0x0bff) AM_RAM AM_SHARE("saram")       // SARAM        TODO: is off-chip if OVLY = 0
559		ADDRESS_MAP_END
560
561		/**************************************************************************
562		* Generic set_info
563		**************************************************************************/
564
565		static CPU_SET_INFO( tms )
566	511	{
567		tms32051_state *cpustate = get_safe_token(device);
568
569		switch (state)
570		{
571		case CPUINFO_INT_PC:
572		case CPUINFO_INT_REGISTER + TMS32051_PC:        cpustate->pc = info->i;                     break;
573		}
574		}
575
576		static CPU_READ( tms )
577		{
578		tms32051_state *cpustate = get_safe_token(device);
579	512	/* TODO: alignment if offset is odd */
580		if (space == AS_PROGRAM)
	513	if (spacenum == AS_PROGRAM)
581	514	{
582		*value = (PM_READ16(cpustate, offset>>1));
	515	value = (PM_READ16(offset>>1));
583	516	}
584		else if (space == AS_DATA)
	517	else if (spacenum == AS_DATA)
585	518	{
586		*value = (DM_READ16(cpustate, offset>>1));
	519	value = (DM_READ16(offset>>1));
587	520	}
588	521	return 1;
589	522	}
590	523
591		static CPU_GET_INFO( tms )
592		{
593		tms32051_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
594
595		switch(state)
596		{
597		/* --- the following bits of info are returned as 64-bit signed integers --- */
598		case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(tms32051_state);                   break;
599		case CPUINFO_INT_INPUT_LINES:                   info->i = 6;                            break;
600		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
601		case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
602		case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
603		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
604		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 2;                            break;
605		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 4;                            break;
606		case CPUINFO_INT_MIN_CYCLES:                    info->i = 1;                            break;
607		case CPUINFO_INT_MAX_CYCLES:                    info->i = 5;                            break;
608
609		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 16;                   break;
610		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16;                  break;
611		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -1;                  break;
612		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 16;                   break;
613		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 16;                   break;
614		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = -1;                   break;
615		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 0;                    break;
616		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 0;                    break;
617		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = 0;                    break;
618
619		case CPUINFO_INT_INPUT_STATE:                   info->i = CLEAR_LINE;                   break;
620
621		case CPUINFO_INT_PREVIOUSPC:                    /* not implemented */                   break;
622
623		case CPUINFO_INT_PC:
624		case CPUINFO_INT_REGISTER + TMS32051_PC:        info->i = cpustate->pc;                     break;
625		case CPUINFO_INT_REGISTER + TMS32051_ACC:       info->i = cpustate->acc;                        break;
626		case CPUINFO_INT_REGISTER + TMS32051_ACCB:      info->i = cpustate->accb;                       break;
627		case CPUINFO_INT_REGISTER + TMS32051_PREG:      info->i = cpustate->preg;                       break;
628		case CPUINFO_INT_REGISTER + TMS32051_TREG0:     info->i = cpustate->treg0;                  break;
629		case CPUINFO_INT_REGISTER + TMS32051_TREG1:     info->i = cpustate->treg1;                  break;
630		case CPUINFO_INT_REGISTER + TMS32051_TREG2:     info->i = cpustate->treg2;                  break;
631		case CPUINFO_INT_REGISTER + TMS32051_BMAR:      info->i = cpustate->bmar;                       break;
632		case CPUINFO_INT_REGISTER + TMS32051_RPTC:      info->i = cpustate->rptc;                       break;
633		case CPUINFO_INT_REGISTER + TMS32051_BRCR:      info->i = cpustate->brcr;                       break;
634		case CPUINFO_INT_REGISTER + TMS32051_INDX:      info->i = cpustate->indx;                       break;
635		case CPUINFO_INT_REGISTER + TMS32051_DBMR:      info->i = cpustate->dbmr;                       break;
636		case CPUINFO_INT_REGISTER + TMS32051_ARCR:      info->i = cpustate->arcr;                       break;
637		case CPUINFO_INT_REGISTER + TMS32051_DP:        info->i = cpustate->st0.dp;                 break;
638		case CPUINFO_INT_REGISTER + TMS32051_ARP:       info->i = cpustate->st0.arp;                    break;
639		case CPUINFO_INT_REGISTER + TMS32051_ARB:       info->i = cpustate->st1.arb;                    break;
640		case CPUINFO_INT_REGISTER + TMS32051_AR0:       info->i = cpustate->ar[0];                  break;
641		case CPUINFO_INT_REGISTER + TMS32051_AR1:       info->i = cpustate->ar[1];                  break;
642		case CPUINFO_INT_REGISTER + TMS32051_AR2:       info->i = cpustate->ar[2];                  break;
643		case CPUINFO_INT_REGISTER + TMS32051_AR3:       info->i = cpustate->ar[3];                  break;
644		case CPUINFO_INT_REGISTER + TMS32051_AR4:       info->i = cpustate->ar[4];                  break;
645		case CPUINFO_INT_REGISTER + TMS32051_AR5:       info->i = cpustate->ar[5];                  break;
646		case CPUINFO_INT_REGISTER + TMS32051_AR6:       info->i = cpustate->ar[6];                  break;
647		case CPUINFO_INT_REGISTER + TMS32051_AR7:       info->i = cpustate->ar[7];                  break;
648
649		/* --- the following bits of info are returned as pointers to data or functions --- */
650		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(tms);                    break;
651		case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(tms);              break;
652		case CPUINFO_FCT_EXIT:                          info->exit = CPU_EXIT_NAME(tms);                    break;
653		case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(tms);          break;
654		case CPUINFO_FCT_BURN:                          info->burn = NULL;                      break;
655		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(tms32051);     break;
656		case CPUINFO_FCT_READ:                          info->read = CPU_READ_NAME(tms);            break;
657		case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &cpustate->icount;               break;
658		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(internal_pgm); break;
659		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map16 = ADDRESS_MAP_NAME(internal_data); break;
660
661		/* --- the following bits of info are returned as NULL-terminated strings --- */
662		case CPUINFO_STR_FAMILY:                    strcpy(info->s, "TMS3205x");            break;
663		case CPUINFO_STR_VERSION:                   strcpy(info->s, "1.0");                 break;
664		case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__);              break;
665		case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Copyright Ville Linde"); break;
666
667		case CPUINFO_STR_FLAGS:                         strcpy(info->s, " ");                   break;
668
669		case CPUINFO_STR_REGISTER + TMS32051_PC:        sprintf(info->s, "PC: %04X", cpustate->pc); break;
670		case CPUINFO_STR_REGISTER + TMS32051_ACC:       sprintf(info->s, "ACC: %08X", cpustate->acc); break;
671		case CPUINFO_STR_REGISTER + TMS32051_ACCB:      sprintf(info->s, "ACCB: %08X", cpustate->accb); break;
672		case CPUINFO_STR_REGISTER + TMS32051_PREG:      sprintf(info->s, "PREG: %08X", cpustate->preg); break;
673		case CPUINFO_STR_REGISTER + TMS32051_TREG0:     sprintf(info->s, "TREG0: %04X", cpustate->treg0); break;
674		case CPUINFO_STR_REGISTER + TMS32051_TREG1:     sprintf(info->s, "TREG1: %04X", cpustate->treg1); break;
675		case CPUINFO_STR_REGISTER + TMS32051_TREG2:     sprintf(info->s, "TREG2: %04X", cpustate->treg2); break;
676		case CPUINFO_STR_REGISTER + TMS32051_BMAR:      sprintf(info->s, "BMAR: %08X", cpustate->bmar); break;
677		case CPUINFO_STR_REGISTER + TMS32051_RPTC:      sprintf(info->s, "RPTC: %08X", cpustate->rptc); break;
678		case CPUINFO_STR_REGISTER + TMS32051_BRCR:      sprintf(info->s, "BRCR: %08X", cpustate->brcr); break;
679		case CPUINFO_STR_REGISTER + TMS32051_INDX:      sprintf(info->s, "INDX: %04X", cpustate->indx); break;
680		case CPUINFO_STR_REGISTER + TMS32051_DBMR:      sprintf(info->s, "DBMR: %04X", cpustate->dbmr); break;
681		case CPUINFO_STR_REGISTER + TMS32051_ARCR:      sprintf(info->s, "ARCR: %04X", cpustate->arcr); break;
682		case CPUINFO_STR_REGISTER + TMS32051_DP:        sprintf(info->s, "DP: %04X", cpustate->st0.dp); break;
683		case CPUINFO_STR_REGISTER + TMS32051_ARP:       sprintf(info->s, "ARP: %04X", cpustate->st0.arp); break;
684		case CPUINFO_STR_REGISTER + TMS32051_ARB:       sprintf(info->s, "ARB: %04X", cpustate->st1.arb); break;
685		case CPUINFO_STR_REGISTER + TMS32051_AR0:       sprintf(info->s, "AR0: %04X", cpustate->ar[0]); break;
686		case CPUINFO_STR_REGISTER + TMS32051_AR1:       sprintf(info->s, "AR1: %04X", cpustate->ar[1]); break;
687		case CPUINFO_STR_REGISTER + TMS32051_AR2:       sprintf(info->s, "AR2: %04X", cpustate->ar[2]); break;
688		case CPUINFO_STR_REGISTER + TMS32051_AR3:       sprintf(info->s, "AR3: %04X", cpustate->ar[3]); break;
689		case CPUINFO_STR_REGISTER + TMS32051_AR4:       sprintf(info->s, "AR4: %04X", cpustate->ar[4]); break;
690		case CPUINFO_STR_REGISTER + TMS32051_AR5:       sprintf(info->s, "AR5: %04X", cpustate->ar[5]); break;
691		case CPUINFO_STR_REGISTER + TMS32051_AR6:       sprintf(info->s, "AR6: %04X", cpustate->ar[6]); break;
692		case CPUINFO_STR_REGISTER + TMS32051_AR7:       sprintf(info->s, "AR7: %04X", cpustate->ar[7]); break;
693		}
694		}
695
696		static CPU_SET_INFO( tms32051 )
697		{
698		tms32051_state *cpustate = get_safe_token(device);
699
700		if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + 5)
701		{
702		return;
703		}
704		switch(state)
705		{
706		case CPUINFO_INT_PC:
707		case CPUINFO_INT_REGISTER + TMS32051_PC:        cpustate->pc = info->i;                         break;
708		case CPUINFO_INT_REGISTER + TMS32051_ACC:       cpustate->acc = info->i;                        break;
709		case CPUINFO_INT_REGISTER + TMS32051_ACCB:      cpustate->accb = info->i;                       break;
710		case CPUINFO_INT_REGISTER + TMS32051_PREG:      cpustate->preg = info->i;                       break;
711		case CPUINFO_INT_REGISTER + TMS32051_TREG0:     cpustate->treg0 = info->i;                  break;
712		case CPUINFO_INT_REGISTER + TMS32051_TREG1:     cpustate->treg1 = info->i;                  break;
713		case CPUINFO_INT_REGISTER + TMS32051_TREG2:     cpustate->treg2 = info->i;                  break;
714		case CPUINFO_INT_REGISTER + TMS32051_BMAR:      cpustate->bmar = info->i;                       break;
715		case CPUINFO_INT_REGISTER + TMS32051_BRCR:      cpustate->brcr = info->i;                       break;
716		case CPUINFO_INT_REGISTER + TMS32051_INDX:      cpustate->indx = info->i;                       break;
717		case CPUINFO_INT_REGISTER + TMS32051_DBMR:      cpustate->dbmr = info->i;                       break;
718		case CPUINFO_INT_REGISTER + TMS32051_ARCR:      cpustate->arcr = info->i;                       break;
719		case CPUINFO_INT_REGISTER + TMS32051_DP:        cpustate->st0.dp = info->i;                 break;
720		case CPUINFO_INT_REGISTER + TMS32051_ARP:       cpustate->st0.arp = info->i;                    break;
721		case CPUINFO_INT_REGISTER + TMS32051_ARB:       cpustate->st1.arb = info->i;                    break;
722		case CPUINFO_INT_REGISTER + TMS32051_AR0:       cpustate->ar[0] = info->i;                  break;
723		case CPUINFO_INT_REGISTER + TMS32051_AR1:       cpustate->ar[1] = info->i;                  break;
724		case CPUINFO_INT_REGISTER + TMS32051_AR2:       cpustate->ar[2] = info->i;                  break;
725		case CPUINFO_INT_REGISTER + TMS32051_AR3:       cpustate->ar[3] = info->i;                  break;
726		case CPUINFO_INT_REGISTER + TMS32051_AR4:       cpustate->ar[4] = info->i;                  break;
727		case CPUINFO_INT_REGISTER + TMS32051_AR5:       cpustate->ar[5] = info->i;                  break;
728		case CPUINFO_INT_REGISTER + TMS32051_AR6:       cpustate->ar[6] = info->i;                  break;
729		case CPUINFO_INT_REGISTER + TMS32051_AR7:       cpustate->ar[7] = info->i;                  break;
730
731		default:                                        CPU_SET_INFO_CALL(tms);             break;
732		}
733		}
734
735		CPU_GET_INFO( tms32051 )
736		{
737		switch(state)
738		{
739		/* --- the following bits of info are returned as pointers to data or functions --- */
740		case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(tms32051);        break;
741
742		/* --- the following bits of info are returned as NULL-terminated strings --- */
743		case CPUINFO_STR_NAME:                          strcpy(info->s, "TMS32051");            break;
744		case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "tms32051");            break;
745
746		default:                                        CPU_GET_INFO_CALL(tms);             break;
747		}
748		}
749
750		DEFINE_LEGACY_CPU_DEVICE(TMS32051, tms32051);

trunk/src/emu/cpu/tms32051/32051ops.h

r26840	r26841
1		static void (*const tms32051_opcode_table[256])(tms32051_state *cpustate) =
	1	const tms32051_device::opcode_func tms32051_device::s_opcode_table[256] =
2	2	{
3	3	/* 0x00 - 0x0f */
4		op_lar_mem,     op_lar_mem,     op_lar_mem,     op_lar_mem,
5		op_lar_mem,     op_lar_mem,     op_lar_mem,     op_lar_mem,
6		op_lamm,        op_smmr,        op_subc,        op_rpt_mem,
7		op_out,         op_ldp_mem,     op_lst_st0,     op_lst_st1,
	4	&tms32051_device::op_lar_mem,     &tms32051_device::op_lar_mem,     &tms32051_device::op_lar_mem,     &tms32051_device::op_lar_mem,
	5	&tms32051_device::op_lar_mem,     &tms32051_device::op_lar_mem,     &tms32051_device::op_lar_mem,     &tms32051_device::op_lar_mem,
	6	&tms32051_device::op_lamm,        &tms32051_device::op_smmr,        &tms32051_device::op_subc,        &tms32051_device::op_rpt_mem,
	7	&tms32051_device::op_out,         &tms32051_device::op_ldp_mem,     &tms32051_device::op_lst_st0,     &tms32051_device::op_lst_st1,
8	8	/* 0x10 - 0x1f */
9		op_lacc_mem,    op_lacc_mem,    op_lacc_mem,    op_lacc_mem,
10		op_lacc_mem,    op_lacc_mem,    op_lacc_mem,    op_lacc_mem,
11		op_lacc_mem,    op_lacc_mem,    op_lacc_mem,    op_lacc_mem,
12		op_lacc_mem,    op_lacc_mem,    op_lacc_mem,    op_lacc_mem,
	9	&tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,
	10	&tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,
	11	&tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,
	12	&tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,    &tms32051_device::op_lacc_mem,
13	13	/* 0x20 - 0x2f */
14		op_add_mem,     op_add_mem,     op_add_mem,     op_add_mem,
15		op_add_mem,     op_add_mem,     op_add_mem,     op_add_mem,
16		op_add_mem,     op_add_mem,     op_add_mem,     op_add_mem,
17		op_add_mem,     op_add_mem,     op_add_mem,     op_add_mem,
	14	&tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,
	15	&tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,
	16	&tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,
	17	&tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,     &tms32051_device::op_add_mem,
18	18	/* 0x30 - 0x3f */
19		op_sub_mem,     op_sub_mem,     op_sub_mem,     op_sub_mem,
20		op_sub_mem,     op_sub_mem,     op_sub_mem,     op_sub_mem,
21		op_sub_mem,     op_sub_mem,     op_sub_mem,     op_sub_mem,
22		op_sub_mem,     op_sub_mem,     op_sub_mem,     op_sub_mem,
	19	&tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,
	20	&tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,
	21	&tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,
	22	&tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,     &tms32051_device::op_sub_mem,
23	23	/* 0x40 - 0x4f */
24		op_bit,         op_bit,         op_bit,         op_bit,
25		op_bit,         op_bit,         op_bit,         op_bit,
26		op_bit,         op_bit,         op_bit,         op_bit,
27		op_bit,         op_bit,         op_bit,         op_bit,
	24	&tms32051_device::op_bit,         &tms32051_device::op_bit,         &tms32051_device::op_bit,         &tms32051_device::op_bit,
	25	&tms32051_device::op_bit,         &tms32051_device::op_bit,         &tms32051_device::op_bit,         &tms32051_device::op_bit,
	26	&tms32051_device::op_bit,         &tms32051_device::op_bit,         &tms32051_device::op_bit,         &tms32051_device::op_bit,
	27	&tms32051_device::op_bit,         &tms32051_device::op_bit,         &tms32051_device::op_bit,         &tms32051_device::op_bit,
28	28	/* 0x50 - 0x5f */
29		op_mpya,        op_mpys,        op_sqra,        op_sqrs,
30		op_mpy_mem,     op_mpyu,        op_invalid,     op_bldp,
31		op_xpl_dbmr,    op_opl_dbmr,    op_apl_dbmr,    op_cpl_dbmr,
32		op_xpl_imm,     op_opl_imm,     op_apl_imm,     op_cpl_imm,
	29	&tms32051_device::op_mpya,        &tms32051_device::op_mpys,        &tms32051_device::op_sqra,        &tms32051_device::op_sqrs,
	30	&tms32051_device::op_mpy_mem,     &tms32051_device::op_mpyu,        &tms32051_device::op_invalid,     &tms32051_device::op_bldp,
	31	&tms32051_device::op_xpl_dbmr,    &tms32051_device::op_opl_dbmr,    &tms32051_device::op_apl_dbmr,    &tms32051_device::op_cpl_dbmr,
	32	&tms32051_device::op_xpl_imm,     &tms32051_device::op_opl_imm,     &tms32051_device::op_apl_imm,     &tms32051_device::op_cpl_imm,
33	33	/* 0x60 - 0x6f */
34		op_addc,        op_add_s16_mem, op_adds,        op_addt,
35		op_subb,        op_sub_s16_mem, op_subs,        op_subt,
36		op_zalr,        op_lacl_mem,    op_lacc_s16_mem,op_lact,
37		op_xor_mem,     op_or_mem,      op_and_mem,     op_bitt,
	34	&tms32051_device::op_addc,        &tms32051_device::op_add_s16_mem, &tms32051_device::op_adds,        &tms32051_device::op_addt,
	35	&tms32051_device::op_subb,        &tms32051_device::op_sub_s16_mem, &tms32051_device::op_subs,        &tms32051_device::op_subt,
	36	&tms32051_device::op_zalr,        &tms32051_device::op_lacl_mem,    &tms32051_device::op_lacc_s16_mem,&tms32051_device::op_lact,
	37	&tms32051_device::op_xor_mem,     &tms32051_device::op_or_mem,      &tms32051_device::op_and_mem,     &tms32051_device::op_bitt,
38	38	/* 0x70 - 0x7f */
39		op_lta,         op_ltp,         op_ltd,         op_lt,
40		op_lts,         op_lph,         op_pshd,        op_dmov,
41		op_adrk,        op_b,           op_call,        op_banz,
42		op_sbrk,        op_bd,          op_calld,       op_banzd,
	39	&tms32051_device::op_lta,         &tms32051_device::op_ltp,         &tms32051_device::op_ltd,         &tms32051_device::op_lt,
	40	&tms32051_device::op_lts,         &tms32051_device::op_lph,         &tms32051_device::op_pshd,        &tms32051_device::op_dmov,
	41	&tms32051_device::op_adrk,        &tms32051_device::op_b,           &tms32051_device::op_call,        &tms32051_device::op_banz,
	42	&tms32051_device::op_sbrk,        &tms32051_device::op_bd,          &tms32051_device::op_calld,       &tms32051_device::op_banzd,
43	43	/* 0x80 - 0x8f */
44		op_sar,         op_sar,         op_sar,         op_sar,
45		op_sar,         op_sar,         op_sar,         op_sar,
46		op_samm,        op_lmmr,        op_popd,        op_mar,
47		op_spl,         op_sph,         op_sst_st0,     op_sst_st1,
	44	&tms32051_device::op_sar,         &tms32051_device::op_sar,         &tms32051_device::op_sar,         &tms32051_device::op_sar,
	45	&tms32051_device::op_sar,         &tms32051_device::op_sar,         &tms32051_device::op_sar,         &tms32051_device::op_sar,
	46	&tms32051_device::op_samm,        &tms32051_device::op_lmmr,        &tms32051_device::op_popd,        &tms32051_device::op_mar,
	47	&tms32051_device::op_spl,         &tms32051_device::op_sph,         &tms32051_device::op_sst_st0,     &tms32051_device::op_sst_st1,
48	48	/* 0x90 - 0x9f */
49		op_sacl,        op_sacl,        op_sacl,        op_sacl,
50		op_sacl,        op_sacl,        op_sacl,        op_sacl,
51		op_sach,        op_sach,        op_sach,        op_sach,
52		op_sach,        op_sach,        op_sach,        op_sach,
	49	&tms32051_device::op_sacl,        &tms32051_device::op_sacl,        &tms32051_device::op_sacl,        &tms32051_device::op_sacl,
	50	&tms32051_device::op_sacl,        &tms32051_device::op_sacl,        &tms32051_device::op_sacl,        &tms32051_device::op_sacl,
	51	&tms32051_device::op_sach,        &tms32051_device::op_sach,        &tms32051_device::op_sach,        &tms32051_device::op_sach,
	52	&tms32051_device::op_sach,        &tms32051_device::op_sach,        &tms32051_device::op_sach,        &tms32051_device::op_sach,
53	53	/* 0xa0 - 0xaf */
54		op_norm,        op_invalid,     op_mac,         op_macd,
55		op_blpd_bmar,   op_blpd_imm,    op_tblr,        op_tblw,
56		op_bldd_slimm,  op_bldd_dlimm,  op_mads,        op_madd,
57		op_bldd_sbmar,  op_bldd_dbmar,  op_splk,        op_in,
	54	&tms32051_device::op_norm,        &tms32051_device::op_invalid,     &tms32051_device::op_mac,         &tms32051_device::op_macd,
	55	&tms32051_device::op_blpd_bmar,   &tms32051_device::op_blpd_imm,    &tms32051_device::op_tblr,        &tms32051_device::op_tblw,
	56	&tms32051_device::op_bldd_slimm,  &tms32051_device::op_bldd_dlimm,  &tms32051_device::op_mads,        &tms32051_device::op_madd,
	57	&tms32051_device::op_bldd_sbmar,  &tms32051_device::op_bldd_dbmar,  &tms32051_device::op_splk,        &tms32051_device::op_in,
58	58	/* 0xb0 - 0xbf */
59		op_lar_simm,    op_lar_simm,    op_lar_simm,    op_lar_simm,
60		op_lar_simm,    op_lar_simm,    op_lar_simm,    op_lar_simm,
61		op_add_simm,    op_lacl_simm,   op_sub_simm,    op_rpt_simm,
62		op_ldp_imm,     op_ldp_imm,     op_group_be,    op_group_bf,
	59	&tms32051_device::op_lar_simm,    &tms32051_device::op_lar_simm,    &tms32051_device::op_lar_simm,    &tms32051_device::op_lar_simm,
	60	&tms32051_device::op_lar_simm,    &tms32051_device::op_lar_simm,    &tms32051_device::op_lar_simm,    &tms32051_device::op_lar_simm,
	61	&tms32051_device::op_add_simm,    &tms32051_device::op_lacl_simm,   &tms32051_device::op_sub_simm,    &tms32051_device::op_rpt_simm,
	62	&tms32051_device::op_ldp_imm,     &tms32051_device::op_ldp_imm,     &tms32051_device::op_group_be,    &tms32051_device::op_group_bf,
63	63	/* 0xc0 - 0xcf */
64		op_mpy_simm,    op_mpy_simm,    op_mpy_simm,    op_mpy_simm,
65		op_mpy_simm,    op_mpy_simm,    op_mpy_simm,    op_mpy_simm,
66		op_mpy_simm,    op_mpy_simm,    op_mpy_simm,    op_mpy_simm,
67		op_mpy_simm,    op_mpy_simm,    op_mpy_simm,    op_mpy_simm,
	64	&tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,
	65	&tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,
	66	&tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,
	67	&tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,
68	68	/* 0xd0 - 0xdf */
69		op_mpy_simm,    op_mpy_simm,    op_mpy_simm,    op_mpy_simm,
70		op_mpy_simm,    op_mpy_simm,    op_mpy_simm,    op_mpy_simm,
71		op_mpy_simm,    op_mpy_simm,    op_mpy_simm,    op_mpy_simm,
72		op_mpy_simm,    op_mpy_simm,    op_mpy_simm,    op_mpy_simm,
	69	&tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,
	70	&tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,
	71	&tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,
	72	&tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,    &tms32051_device::op_mpy_simm,
73	73	/* 0xe0 - 0xef */
74		op_bcnd,        op_bcnd,        op_bcnd,        op_bcnd,
75		op_xc,          op_xc,          op_xc,          op_xc,
76		op_cc,          op_cc,          op_cc,          op_cc,
77		op_retc,        op_retc,        op_retc,        op_retc,
	74	&tms32051_device::op_bcnd,        &tms32051_device::op_bcnd,        &tms32051_device::op_bcnd,        &tms32051_device::op_bcnd,
	75	&tms32051_device::op_xc,          &tms32051_device::op_xc,          &tms32051_device::op_xc,          &tms32051_device::op_xc,
	76	&tms32051_device::op_cc,          &tms32051_device::op_cc,          &tms32051_device::op_cc,          &tms32051_device::op_cc,
	77	&tms32051_device::op_retc,        &tms32051_device::op_retc,        &tms32051_device::op_retc,        &tms32051_device::op_retc,
78	78	/* 0xf0 - 0xff */
79		op_bcndd,       op_bcndd,       op_bcndd,       op_bcndd,
80		op_xc,          op_xc,          op_xc,          op_xc,
81		op_ccd,         op_ccd,         op_ccd,         op_ccd,
82		op_retcd,       op_retcd,       op_retcd,       op_retcd
	79	&tms32051_device::op_bcndd,       &tms32051_device::op_bcndd,       &tms32051_device::op_bcndd,       &tms32051_device::op_bcndd,
	80	&tms32051_device::op_xc,          &tms32051_device::op_xc,          &tms32051_device::op_xc,          &tms32051_device::op_xc,
	81	&tms32051_device::op_ccd,         &tms32051_device::op_ccd,         &tms32051_device::op_ccd,         &tms32051_device::op_ccd,
	82	&tms32051_device::op_retcd,       &tms32051_device::op_retcd,       &tms32051_device::op_retcd,       &tms32051_device::op_retcd
83	83	};
84	84
85		static void (*const tms32051_opcode_table_be[256])(tms32051_state *cpustate) =
	85	const tms32051_device::opcode_func tms32051_device::s_opcode_table_be[256] =
86	86	{
87	87	/* 0x00 - 0x0f */
88		op_abs,         op_cmpl,        op_neg,         op_pac,
89		op_apac,        op_spac,        op_invalid,     op_invalid,
90		op_invalid,     op_sfl,         op_sfr,         op_invalid,
91		op_rol,         op_ror,         op_invalid,     op_invalid,
	88	&tms32051_device::op_abs,         &tms32051_device::op_cmpl,        &tms32051_device::op_neg,         &tms32051_device::op_pac,
	89	&tms32051_device::op_apac,        &tms32051_device::op_spac,        &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	90	&tms32051_device::op_invalid,     &tms32051_device::op_sfl,         &tms32051_device::op_sfr,         &tms32051_device::op_invalid,
	91	&tms32051_device::op_rol,         &tms32051_device::op_ror,         &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
92	92	/* 0x10 - 0x1f */
93		op_addb,        op_adcb,        op_andb,        op_orb,
94		op_rolb,        op_rorb,        op_sflb,        op_sfrb,
95		op_sbb,         op_sbbb,        op_xorb,        op_crgt,
96		op_crlt,        op_exar,        op_sacb,        op_lacb,
	93	&tms32051_device::op_addb,        &tms32051_device::op_adcb,        &tms32051_device::op_andb,        &tms32051_device::op_orb,
	94	&tms32051_device::op_rolb,        &tms32051_device::op_rorb,        &tms32051_device::op_sflb,        &tms32051_device::op_sfrb,
	95	&tms32051_device::op_sbb,         &tms32051_device::op_sbbb,        &tms32051_device::op_xorb,        &tms32051_device::op_crgt,
	96	&tms32051_device::op_crlt,        &tms32051_device::op_exar,        &tms32051_device::op_sacb,        &tms32051_device::op_lacb,
97	97	/* 0x20 - 0x2f */
98		op_bacc,        op_baccd,       op_idle,        op_idle2,
99		op_invalid,     op_invalid,     op_invalid,     op_invalid,
100		op_invalid,     op_invalid,     op_invalid,     op_invalid,
101		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	98	&tms32051_device::op_bacc,        &tms32051_device::op_baccd,       &tms32051_device::op_idle,        &tms32051_device::op_idle2,
	99	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	100	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	101	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
102	102	/* 0x30 - 0x3f */
103		op_cala,        op_invalid,     op_pop,         op_invalid,
104		op_invalid,     op_invalid,     op_invalid,     op_invalid,
105		op_reti,        op_invalid,     op_rete,        op_invalid,
106		op_push,        op_calad,       op_invalid,     op_invalid,
	103	&tms32051_device::op_cala,        &tms32051_device::op_invalid,     &tms32051_device::op_pop,         &tms32051_device::op_invalid,
	104	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	105	&tms32051_device::op_reti,        &tms32051_device::op_invalid,     &tms32051_device::op_rete,        &tms32051_device::op_invalid,
	106	&tms32051_device::op_push,        &tms32051_device::op_calad,       &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
107	107	/* 0x40 - 0x4f */
108		op_clrc_intm,   op_setc_intm,   op_clrc_ov,     op_setc_ov,
109		op_clrc_cnf,    op_setc_cnf,    op_clrc_ext,    op_setc_ext,
110		op_clrc_hold,   op_setc_hold,   op_clrc_tc,     op_setc_tc,
111		op_clrc_xf,     op_setc_xf,     op_clrc_carry,  op_setc_carry,
	108	&tms32051_device::op_clrc_intm,   &tms32051_device::op_setc_intm,   &tms32051_device::op_clrc_ov,     &tms32051_device::op_setc_ov,
	109	&tms32051_device::op_clrc_cnf,    &tms32051_device::op_setc_cnf,    &tms32051_device::op_clrc_ext,    &tms32051_device::op_setc_ext,
	110	&tms32051_device::op_clrc_hold,   &tms32051_device::op_setc_hold,   &tms32051_device::op_clrc_tc,     &tms32051_device::op_setc_tc,
	111	&tms32051_device::op_clrc_xf,     &tms32051_device::op_setc_xf,     &tms32051_device::op_clrc_carry,  &tms32051_device::op_setc_carry,
112	112	/* 0x50 - 0x5f */
113		op_invalid,     op_trap,        op_nmi,         op_invalid,
114		op_invalid,     op_invalid,     op_invalid,     op_invalid,
115		op_zpr,         op_zap,         op_sath,        op_satl,
116		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	113	&tms32051_device::op_invalid,     &tms32051_device::op_trap,        &tms32051_device::op_nmi,         &tms32051_device::op_invalid,
	114	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	115	&tms32051_device::op_zpr,         &tms32051_device::op_zap,         &tms32051_device::op_sath,        &tms32051_device::op_satl,
	116	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
117	117	/* 0x60 - 0x6f */
118		op_intr,        op_intr,        op_intr,        op_intr,
119		op_intr,        op_intr,        op_intr,        op_intr,
120		op_intr,        op_intr,        op_intr,        op_intr,
121		op_intr,        op_intr,        op_intr,        op_intr,
	118	&tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,
	119	&tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,
	120	&tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,
	121	&tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,
122	122	/* 0x70 - 0x7f */
123		op_intr,        op_intr,        op_intr,        op_intr,
124		op_intr,        op_intr,        op_intr,        op_intr,
125		op_intr,        op_intr,        op_intr,        op_intr,
126		op_intr,        op_intr,        op_intr,        op_intr,
	123	&tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,
	124	&tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,
	125	&tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,
	126	&tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,        &tms32051_device::op_intr,
127	127	/* 0x80 - 0x8f */
128		op_mpy_limm,    op_and_s16_limm,op_or_s16_limm, op_xor_s16_limm,
129		op_invalid,     op_invalid,     op_invalid,     op_invalid,
130		op_invalid,     op_invalid,     op_invalid,     op_invalid,
131		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	128	&tms32051_device::op_mpy_limm,    &tms32051_device::op_and_s16_limm,&tms32051_device::op_or_s16_limm, &tms32051_device::op_xor_s16_limm,
	129	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	130	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	131	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
132	132	/* 0x90 - 0x9f */
133		op_invalid,     op_invalid,     op_invalid,     op_invalid,
134		op_invalid,     op_invalid,     op_invalid,     op_invalid,
135		op_invalid,     op_invalid,     op_invalid,     op_invalid,
136		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	133	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	134	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	135	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	136	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
137	137	/* 0xa0 - 0xaf */
138		op_invalid,     op_invalid,     op_invalid,     op_invalid,
139		op_invalid,     op_invalid,     op_invalid,     op_invalid,
140		op_invalid,     op_invalid,     op_invalid,     op_invalid,
141		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	138	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	139	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	140	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	141	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
142	142	/* 0xb0 - 0xbf */
143		op_invalid,     op_invalid,     op_invalid,     op_invalid,
144		op_invalid,     op_invalid,     op_invalid,     op_invalid,
145		op_invalid,     op_invalid,     op_invalid,     op_invalid,
146		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	143	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	144	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	145	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	146	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
147	147	/* 0xc0 - 0xcf */
148		op_invalid,     op_invalid,     op_invalid,     op_invalid,
149		op_rpt_limm,    op_rptz,        op_rptb,        op_invalid,
150		op_invalid,     op_invalid,     op_invalid,     op_invalid,
151		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	148	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	149	&tms32051_device::op_rpt_limm,    &tms32051_device::op_rptz,        &tms32051_device::op_rptb,        &tms32051_device::op_invalid,
	150	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	151	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
152	152	/* 0xd0 - 0xdf */
153		op_invalid,     op_invalid,     op_invalid,     op_invalid,
154		op_invalid,     op_invalid,     op_invalid,     op_invalid,
155		op_invalid,     op_invalid,     op_invalid,     op_invalid,
156		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	153	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	154	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	155	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	156	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
157	157	/* 0xe0 - 0xef */
158		op_invalid,     op_invalid,     op_invalid,     op_invalid,
159		op_invalid,     op_invalid,     op_invalid,     op_invalid,
160		op_invalid,     op_invalid,     op_invalid,     op_invalid,
161		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	158	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	159	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	160	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	161	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
162	162	/* 0xf0 - 0xff */
163		op_invalid,     op_invalid,     op_invalid,     op_invalid,
164		op_invalid,     op_invalid,     op_invalid,     op_invalid,
165		op_invalid,     op_invalid,     op_invalid,     op_invalid,
166		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	163	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	164	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	165	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	166	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
167	167	};
168	168
169		static void (*const tms32051_opcode_table_bf[256])(tms32051_state *cpustate) =
	169	const tms32051_device::opcode_func tms32051_device::s_opcode_table_bf[256] =
170	170	{
171	171	/* 0x00 - 0x0f */
172		op_spm,         op_spm,         op_spm,         op_spm,
173		op_invalid,     op_invalid,     op_invalid,     op_invalid,
174		op_lar_limm,    op_lar_limm,    op_lar_limm,    op_lar_limm,
175		op_lar_limm,    op_lar_limm,    op_lar_limm,    op_lar_limm,
	172	&tms32051_device::op_spm,         &tms32051_device::op_spm,         &tms32051_device::op_spm,         &tms32051_device::op_spm,
	173	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	174	&tms32051_device::op_lar_limm,    &tms32051_device::op_lar_limm,    &tms32051_device::op_lar_limm,    &tms32051_device::op_lar_limm,
	175	&tms32051_device::op_lar_limm,    &tms32051_device::op_lar_limm,    &tms32051_device::op_lar_limm,    &tms32051_device::op_lar_limm,
176	176	/* 0x10 - 0x1f */
177		op_invalid,     op_invalid,     op_invalid,     op_invalid,
178		op_invalid,     op_invalid,     op_invalid,     op_invalid,
179		op_invalid,     op_invalid,     op_invalid,     op_invalid,
180		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	177	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	178	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	179	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	180	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
181	181	/* 0x20 - 0x2f */
182		op_invalid,     op_invalid,     op_invalid,     op_invalid,
183		op_invalid,     op_invalid,     op_invalid,     op_invalid,
184		op_invalid,     op_invalid,     op_invalid,     op_invalid,
185		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	182	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	183	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	184	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	185	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
186	186	/* 0x30 - 0x3f */
187		op_invalid,     op_invalid,     op_invalid,     op_invalid,
188		op_invalid,     op_invalid,     op_invalid,     op_invalid,
189		op_invalid,     op_invalid,     op_invalid,     op_invalid,
190		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	187	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	188	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	189	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	190	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
191	191	/* 0x40 - 0x4f */
192		op_invalid,     op_invalid,     op_invalid,     op_invalid,
193		op_cmpr,        op_cmpr,        op_cmpr,        op_cmpr,
194		op_invalid,     op_invalid,     op_invalid,     op_invalid,
195		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	192	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	193	&tms32051_device::op_cmpr,        &tms32051_device::op_cmpr,        &tms32051_device::op_cmpr,        &tms32051_device::op_cmpr,
	194	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	195	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
196	196	/* 0x50 - 0x5f */
197		op_invalid,     op_invalid,     op_invalid,     op_invalid,
198		op_invalid,     op_invalid,     op_invalid,     op_invalid,
199		op_invalid,     op_invalid,     op_invalid,     op_invalid,
200		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	197	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	198	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	199	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	200	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
201	201	/* 0x60 - 0x6f */
202		op_invalid,     op_invalid,     op_invalid,     op_invalid,
203		op_invalid,     op_invalid,     op_invalid,     op_invalid,
204		op_invalid,     op_invalid,     op_invalid,     op_invalid,
205		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	202	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	203	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	204	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	205	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
206	206	/* 0x70 - 0x7f */
207		op_invalid,     op_invalid,     op_invalid,     op_invalid,
208		op_invalid,     op_invalid,     op_invalid,     op_invalid,
209		op_invalid,     op_invalid,     op_invalid,     op_invalid,
210		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	207	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	208	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	209	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	210	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
211	211	/* 0x80 - 0x8f */
212		op_lacc_limm,   op_lacc_limm,   op_lacc_limm,   op_lacc_limm,
213		op_lacc_limm,   op_lacc_limm,   op_lacc_limm,   op_lacc_limm,
214		op_lacc_limm,   op_lacc_limm,   op_lacc_limm,   op_lacc_limm,
215		op_lacc_limm,   op_lacc_limm,   op_lacc_limm,   op_lacc_limm,
	212	&tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,
	213	&tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,
	214	&tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,
	215	&tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,   &tms32051_device::op_lacc_limm,
216	216	/* 0x90 - 0x9f */
217		op_add_limm,    op_add_limm,    op_add_limm,    op_add_limm,
218		op_add_limm,    op_add_limm,    op_add_limm,    op_add_limm,
219		op_add_limm,    op_add_limm,    op_add_limm,    op_add_limm,
220		op_add_limm,    op_add_limm,    op_add_limm,    op_add_limm,
	217	&tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,
	218	&tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,
	219	&tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,
	220	&tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,    &tms32051_device::op_add_limm,
221	221	/* 0xa0 - 0xaf */
222		op_sub_limm,    op_sub_limm,    op_sub_limm,    op_sub_limm,
223		op_sub_limm,    op_sub_limm,    op_sub_limm,    op_sub_limm,
224		op_sub_limm,    op_sub_limm,    op_sub_limm,    op_sub_limm,
225		op_sub_limm,    op_sub_limm,    op_sub_limm,    op_sub_limm,
	222	&tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,
	223	&tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,
	224	&tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,
	225	&tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,    &tms32051_device::op_sub_limm,
226	226	/* 0xb0 - 0xbf */
227		op_and_limm,    op_and_limm,    op_and_limm,    op_and_limm,
228		op_and_limm,    op_and_limm,    op_and_limm,    op_and_limm,
229		op_and_limm,    op_and_limm,    op_and_limm,    op_and_limm,
230		op_and_limm,    op_and_limm,    op_and_limm,    op_and_limm,
	227	&tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,
	228	&tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,
	229	&tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,
	230	&tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,    &tms32051_device::op_and_limm,
231	231	/* 0xc0 - 0xcf */
232		op_or_limm,     op_or_limm,     op_or_limm,     op_or_limm,
233		op_or_limm,     op_or_limm,     op_or_limm,     op_or_limm,
234		op_or_limm,     op_or_limm,     op_or_limm,     op_or_limm,
235		op_or_limm,     op_or_limm,     op_or_limm,     op_or_limm,
	232	&tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,
	233	&tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,
	234	&tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,
	235	&tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,     &tms32051_device::op_or_limm,
236	236	/* 0xd0 - 0xdf */
237		op_xor_limm,    op_xor_limm,    op_xor_limm,    op_xor_limm,
238		op_xor_limm,    op_xor_limm,    op_xor_limm,    op_xor_limm,
239		op_xor_limm,    op_xor_limm,    op_xor_limm,    op_xor_limm,
240		op_xor_limm,    op_xor_limm,    op_xor_limm,    op_xor_limm,
	237	&tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,
	238	&tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,
	239	&tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,
	240	&tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,    &tms32051_device::op_xor_limm,
241	241	/* 0xe0 - 0xef */
242		op_bsar,        op_bsar,        op_bsar,        op_bsar,
243		op_bsar,        op_bsar,        op_bsar,        op_bsar,
244		op_bsar,        op_bsar,        op_bsar,        op_bsar,
245		op_bsar,        op_bsar,        op_bsar,        op_bsar,
	242	&tms32051_device::op_bsar,        &tms32051_device::op_bsar,        &tms32051_device::op_bsar,        &tms32051_device::op_bsar,
	243	&tms32051_device::op_bsar,        &tms32051_device::op_bsar,        &tms32051_device::op_bsar,        &tms32051_device::op_bsar,
	244	&tms32051_device::op_bsar,        &tms32051_device::op_bsar,        &tms32051_device::op_bsar,        &tms32051_device::op_bsar,
	245	&tms32051_device::op_bsar,        &tms32051_device::op_bsar,        &tms32051_device::op_bsar,        &tms32051_device::op_bsar,
246	246	/* 0xf0 - 0xff */
247		op_invalid,     op_invalid,     op_invalid,     op_invalid,
248		op_invalid,     op_invalid,     op_invalid,     op_invalid,
249		op_invalid,     op_invalid,     op_invalid,     op_invalid,
250		op_invalid,     op_invalid,     op_invalid,     op_invalid,
	247	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	248	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	249	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
	250	&tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,     &tms32051_device::op_invalid,
251	251	};

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