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r26838 Tuesday 31st December, 2013 at 12:42:14 UTC by Wilbert Pol
tms32025.c: Modernized cpu core.  [Wilbert Pol]

[src/emu/cpu/tms32025]

tms32025.c tms32025.h

trunk/src/emu/cpu/tms32025/tms32025.h

r26837	r26838
66	66	*  Public Functions
67	67	*/
68	68
69		DECLARE_LEGACY_CPU_DEVICE(TMS32025, tms32025);
70		DECLARE_LEGACY_CPU_DEVICE(TMS32026, tms32026);
71	69
72		CPU_DISASSEMBLE( tms32025 );
	70	class tms32025_device : public cpu_device
	71	{
	72	public:
	73	// construction/destruction
	74	tms32025_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	75	tms32025_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
73	76
	77	protected:
	78	// device-level overrides
	79	virtual void device_start();
	80	virtual void device_reset();
	81
	82	// device_execute_interface overrides
	83	virtual UINT32 execute_min_cycles() const { return 4; }
	84	virtual UINT32 execute_max_cycles() const { return 20; }
	85	virtual UINT32 execute_input_lines() const { return 6; }
	86	virtual void execute_run();
	87	virtual void execute_set_input(int inputnum, int state);
	88
	89	// device_memory_interface overrides
	90	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) ); }
	91	virtual bool memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value);
	92	virtual bool memory_write(address_spacenum spacenum, offs_t offset, int size, UINT64 value);
	93	virtual bool memory_readop(offs_t offset, int size, UINT64 &value);
	94
	95	// device_state_interface overrides
	96	virtual void state_import(const device_state_entry &entry);
	97	virtual void state_export(const device_state_entry &entry);
	98	void state_string_export(const device_state_entry &entry, astring &string);
	99
	100	// device_disasm_interface overrides
	101	virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
	102	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
	103	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	104
	105	private:
	106	address_space_config m_program_config;
	107	address_space_config m_data_config;
	108	address_space_config m_io_config;
	109
	110	typedef void ( tms32025_device::*opcode_func ) ();
	111	struct tms32025_opcode
	112	{
	113	UINT8       cycles;
	114	opcode_func function;
	115	};
	116	static const tms32025_opcode s_opcode_main[256];
	117	static const tms32025_opcode s_opcode_CE_subset[256];
	118	static const tms32025_opcode s_opcode_Dx_subset[8];
	119
	120
	121	/******************** CPU Internal Registers *******************/
	122	UINT16  m_PREVPC;     /* previous program counter */
	123	UINT16  m_PC;
	124	UINT16  m_PFC;
	125	UINT16  m_STR0, m_STR1;
	126	UINT8   m_IFR;
	127	UINT8   m_RPTC;
	128	PAIR    m_ACC;
	129	PAIR    m_Preg;
	130	UINT16  m_Treg;
	131	UINT16  m_AR[8];
	132	UINT16  m_STACK[8];
	133	PAIR    m_ALU;
	134	protected:
	135	UINT16  m_intRAM[0x800];
	136	private:
	137	UINT8   m_timerover;
	138
	139	/********************** Status data ****************************/
	140	PAIR    m_opcode;
	141	int     m_idle;
	142	int     m_hold;
	143	int     m_external_mem_access;    /** required for hold mode. Implement it ! */
	144	int     m_init_load_addr;         /* 0=No, 1=Yes, 2=Once for repeat mode */
	145	int     m_tms32025_irq_cycles;
	146	int     m_tms32025_dec_cycles;
	147
	148	PAIR    m_oldacc;
	149	UINT32  m_memaccess;
	150	int     m_icount;
	151	int     m_mHackIgnoreARP;          /* special handling for lst, lst1 instructions */
	152	int     m_waiting_for_serial_frame;
	153
	154	address_space *m_program;
	155	direct_read_data *m_direct;
	156	address_space *m_data;
	157	address_space *m_io;
	158
	159	UINT16 *m_pgmmap[0x200];
	160	protected:
	161	UINT16 *m_datamap[0x200];
	162
	163	private:
	164	UINT32 m_debugger_temp;
	165
	166	inline void CLR0(UINT16 flag);
	167	inline void SET0(UINT16 flag);
	168	inline void CLR1(UINT16 flag);
	169	inline void SET1(UINT16 flag);
	170	inline void MODIFY_DP(int data);
	171	inline void MODIFY_PM(int data);
	172	inline void MODIFY_ARP(int data);
	173	inline UINT16 M_RDROM(offs_t addr);
	174	inline void M_WRTROM(offs_t addr, UINT16 data);
	175	inline UINT16 M_RDRAM(offs_t addr);
	176	inline void M_WRTRAM(offs_t addr, UINT16 data);
	177	UINT16 reverse_carry_add(UINT16 arg0, UINT16 arg1 );
	178	inline void MODIFY_AR_ARP();
	179	inline void CALCULATE_ADD_CARRY();
	180	inline void CALCULATE_SUB_CARRY();
	181	inline void CALCULATE_ADD_OVERFLOW(INT32 addval);
	182	inline void CALCULATE_SUB_OVERFLOW(INT32 subval);
	183	inline UINT16 POP_STACK();
	184	inline void PUSH_STACK(UINT16 data);
	185	inline void SHIFT_Preg_TO_ALU();
	186	inline void GETDATA(int shift,int signext);
	187	inline void PUTDATA(UINT16 data);
	188	inline void PUTDATA_SST(UINT16 data);
	189	void opcodes_CE();
	190	void opcodes_Dx();
	191	void illegal();
	192	void abst();
	193	void add();
	194	void addc();
	195	void addh();
	196	void addk();
	197	void adds();
	198	void addt();
	199	void adlk();
	200	void adrk();
	201	void and_();
	202	void andk();
	203	void apac();
	204	void br();
	205	void bacc();
	206	void banz();
	207	void bbnz();
	208	void bbz();
	209	void bc();
	210	void bgez();
	211	void bgz();
	212	void bioz();
	213	void bit();
	214	void bitt();
	215	void blez();
	216	void blkd();
	217	void blkp();
	218	void blz();
	219	void bnc();
	220	void bnv();
	221	void bnz();
	222	void bv();
	223	void bz();
	224	void cala();
	225	void call();
	226	void cmpl();
	227	void cmpr();
	228	void cnfd();
	229	void cnfp();
	230	void conf();
	231	void dint();
	232	void dmov();
	233	void eint();
	234	void fort();
	235	void idle();
	236	void in();
	237	void lac();
	238	void lack();
	239	void lact();
	240	void lalk();
	241	void lar_ar0();
	242	void lar_ar1();
	243	void lar_ar2();
	244	void lar_ar3();
	245	void lar_ar4();
	246	void lar_ar5();
	247	void lar_ar6();
	248	void lar_ar7();
	249	void lark_ar0();
	250	void lark_ar1();
	251	void lark_ar2();
	252	void lark_ar3();
	253	void lark_ar4();
	254	void lark_ar5();
	255	void lark_ar6();
	256	void lark_ar7();
	257	void ldp();
	258	void ldpk();
	259	void lph();
	260	void lrlk();
	261	void lst();
	262	void lst1();
	263	void lt();
	264	void lta();
	265	void ltd();
	266	void ltp();
	267	void lts();
	268	void mac();
	269	void macd();
	270	void mar();
	271	void mpy();
	272	void mpya();
	273	void mpyk();
	274	void mpys();
	275	void mpyu();
	276	void neg();
	277	void nop();
	278	void norm();
	279	void or_();
	280	void ork();
	281	void out();
	282	void pac();
	283	void pop();
	284	void popd();
	285	void pshd();
	286	void push();
	287	void rc();
	288	void ret();
	289	void rfsm();
	290	void rhm();
	291	void rol();
	292	void ror();
	293	void rovm();
	294	void rpt();
	295	void rptk();
	296	void rsxm();
	297	void rtc();
	298	void rtxm();
	299	void rxf();
	300	void sach();
	301	void sacl();
	302	void sar_ar0();
	303	void sar_ar1();
	304	void sar_ar2();
	305	void sar_ar3();
	306	void sar_ar4();
	307	void sar_ar5();
	308	void sar_ar6();
	309	void sar_ar7();
	310	void sblk();
	311	void sbrk_ar();
	312	void sc();
	313	void sfl();
	314	void sfr();
	315	void sfsm();
	316	void shm();
	317	void sovm();
	318	void spac();
	319	void sph();
	320	void spl();
	321	void spm();
	322	void sqra();
	323	void sqrs();
	324	void sst();
	325	void sst1();
	326	void ssxm();
	327	void stc();
	328	void stxm();
	329	void sub();
	330	void subb();
	331	void subc();
	332	void subh();
	333	void subk();
	334	void subs();
	335	void subt();
	336	void sxf();
	337	void tblr();
	338	void tblw();
	339	void trap();
	340	void xor_();
	341	void xork();
	342	void zalh();
	343	void zalr();
	344	void zals();
	345	inline int process_IRQs();
	346	inline void process_timer(int clocks);
	347
	348	};
	349
	350
	351	class tms32026_device : public tms32025_device
	352	{
	353	public:
	354	// construction/destruction
	355	tms32026_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	356
	357	protected:
	358	virtual void device_reset();
	359	};
	360
	361
	362	extern const device_type TMS32025;
	363	extern const device_type TMS32026;
	364
	365
74	366	#endif  /* __TMS32025_H__ */

trunk/src/emu/cpu/tms32025/tms32025.c

r26837	r26838
125	125
126	126
127	127
128		#define SET_PC(x)   do { cpustate->PC = (x); } while (0)
	128	#define SET_PC(x)   do { m_PC = (x); } while (0)
129	129
130		#define P_IN(A)         (cpustate->io->read_word((A)<<1))
131		#define P_OUT(A,V)      (cpustate->io->write_word(((A)<<1),(V)))
132		#define S_IN(A)         (cpustate->io->read_word((A)<<1))
133		#define S_OUT(A,V)      (cpustate->io->write_word(((A)<<1),(V)))
	130	#define P_IN(A)         (m_io->read_word((A)<<1))
	131	#define P_OUT(A,V)      (m_io->write_word(((A)<<1),(V)))
	132	#define S_IN(A)         (m_io->read_word((A)<<1))
	133	#define S_OUT(A,V)      (m_io->write_word(((A)<<1),(V)))
134	134
135		#define M_RDOP(A)       ((cpustate->pgmmap[(A) >> 7]) ? (cpustate->pgmmap[(A) >> 7][(A) & 0x7f]) : cpustate->direct->read_decrypted_word((A)<<1))
136		#define M_RDOP_ARG(A)   ((cpustate->pgmmap[(A) >> 7]) ? (cpustate->pgmmap[(A) >> 7][(A) & 0x7f]) : cpustate->direct->read_decrypted_word((A)<<1))
	135	#define M_RDOP(A)       ((m_pgmmap[(A) >> 7]) ? (m_pgmmap[(A) >> 7][(A) & 0x7f]) : m_direct->read_decrypted_word((A)<<1))
	136	#define M_RDOP_ARG(A)   ((m_pgmmap[(A) >> 7]) ? (m_pgmmap[(A) >> 7][(A) & 0x7f]) : m_direct->read_decrypted_word((A)<<1))
137	137
138	138
139
140		struct tms32025_state
141		{
142		/******************** CPU Internal Registers *******************/
143		UINT16  PREVPC;     /* previous program counter */
144		UINT16  PC;
145		UINT16  PFC;
146		UINT16  STR0, STR1;
147		UINT8   IFR;
148		UINT8   RPTC;
149		PAIR    ACC;
150		PAIR    Preg;
151		UINT16  Treg;
152		UINT16  AR[8];
153		UINT16  STACK[8];
154		PAIR    ALU;
155		UINT16  *intRAM;
156		UINT8   timerover;
157
158		/********************** Status data ****************************/
159		PAIR    opcode;
160		int     idle;
161		int     hold;
162		int     external_mem_access;    /** required for hold mode. Implement it ! */
163		int     init_load_addr;         /* 0=No, 1=Yes, 2=Once for repeat mode */
164		int     tms32025_irq_cycles;
165		int     tms32025_dec_cycles;
166		device_irq_acknowledge_callback irq_callback;
167
168		PAIR    oldacc;
169		UINT32  memaccess;
170		int     icount;
171		int     mHackIgnoreARP;          /* special handling for lst, lst1 instructions */
172		int     waiting_for_serial_frame;
173
174		legacy_cpu_device *device;
175		address_space *program;
176		direct_read_data *direct;
177		address_space *data;
178		address_space *io;
179
180		UINT16 *pgmmap[0x200];
181		UINT16 *datamap[0x200];
182		};
183
184		INLINE tms32025_state *get_safe_token(device_t *device)
185		{
186		assert(device != NULL);
187		assert(device->type() == TMS32025 ||
188		device->type() == TMS32026);
189		return (tms32025_state *)downcast<legacy_cpu_device *>(device)->token();
190		}
191
192		/* opcode table entry */
193		struct tms32025_opcode
194		{
195		UINT8   cycles;
196		void    (*function)(tms32025_state *);
197		};
198		/* opcode table entry (Opcode CE has sub-opcodes) */
199		struct tms32025_opcode_CE
200		{
201		UINT8   cycles;
202		void    (*function)(tms32025_state *);
203		};
204		/* opcode table entry (Opcode Dx has sub-opcodes) */
205		struct tms32025_opcode_Dx
206		{
207		UINT8   cycles;
208		void    (*function)(tms32025_state *);
209		};
210
211
212
213	139	/************************** Memory mapped registers ****************/
214		#define DRR     cpustate->intRAM[0]
215		#define DXR     cpustate->intRAM[1]
216		#define TIM     cpustate->intRAM[2]
217		#define PRD     cpustate->intRAM[3]
218		#define IMR     cpustate->intRAM[4]
219		#define GREG    cpustate->intRAM[5]
	140	#define DRR     m_intRAM[0]
	141	#define DXR     m_intRAM[1]
	142	#define TIM     m_intRAM[2]
	143	#define PRD     m_intRAM[3]
	144	#define IMR     m_intRAM[4]
	145	#define GREG    m_intRAM[5]
220	146
221	147
222
223	148	/****************************************************************************
224	149	*******  The following is the Status (Flag) register 0 definition.  ********
225	150	| 15 | 14 | 13 | 12 |  11 | 10 |   9  | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
r26837	r26838
255	180	#define PM_REG      0x0003  /* PM   (Product shift Mode) */
256	181
257	182
258		#define OV      ( cpustate->STR0 & OV_FLAG)         /* OV   (Overflow flag) */
259		#define OVM     ( cpustate->STR0 & OVM_FLAG)        /* OVM  (Overflow Mode bit) 1 indicates an overflow */
260		#define INTM    ( cpustate->STR0 & INTM_FLAG)       /* INTM (Interrupt enable flag) 0 enables maskable interrupts */
261		#define ARP     ((cpustate->STR0 & ARP_REG) >> 13)  /* ARP  (Auxiliary Register Pointer) */
262		#define DP      ((cpustate->STR0 & DP_REG) << 7)    /* DP   (Data memory Pointer bit) */
263		#define ARB     ( cpustate->STR1 & ARB_REG)         /* ARB  (Backup Auxiliary Register pointer) */
264		#define CNF0    ( cpustate->STR1 & CNF0_REG)        /* CNF0 (Onchip Ram Config register) */
265		#define TC      ( cpustate->STR1 & TC_FLAG)         /* TC   (Test Control Flag) */
266		#define SXM     ( cpustate->STR1 & SXM_FLAG)        /* SXM  (Sign Extension Mode) */
267		#define CARRY   ( cpustate->STR1 & C_FLAG)          /* C    (Carry Flag for accumulator) */
268		#define HM      ( cpustate->STR1 & HM_FLAG)         /* HM   (Processor Hold Mode) */
269		#define FSM     ( cpustate->STR1 & FSM_FLAG)        /* FSM  (Frame Synchronization Mode - for serial port) */
270		#define XF      ( cpustate->STR1 & FSM_FLAG)        /* XF   (XF output pin status) */
271		#define FO      ( cpustate->STR1 & FO_FLAG)         /* FO   (Serial port Format In/Out mode) */
272		#define TXM     ( cpustate->STR1 & TXM_FLAG)        /* TXM  (Transmit Mode - for serial port) */
273		#define PM      ( cpustate->STR1 & PM_REG)          /* PM   (P register shift Mode. See SHIFT_Preg_TO_ALU below )*/
	183	#define OV      ( m_STR0 & OV_FLAG)         /* OV   (Overflow flag) */
	184	#define OVM     ( m_STR0 & OVM_FLAG)        /* OVM  (Overflow Mode bit) 1 indicates an overflow */
	185	#define INTM    ( m_STR0 & INTM_FLAG)       /* INTM (Interrupt enable flag) 0 enables maskable interrupts */
	186	#define ARP     ((m_STR0 & ARP_REG) >> 13)  /* ARP  (Auxiliary Register Pointer) */
	187	#define DP      ((m_STR0 & DP_REG) << 7)    /* DP   (Data memory Pointer bit) */
	188	#define ARB     ( m_STR1 & ARB_REG)         /* ARB  (Backup Auxiliary Register pointer) */
	189	#define CNF0    ( m_STR1 & CNF0_REG)        /* CNF0 (Onchip Ram Config register) */
	190	#define TC      ( m_STR1 & TC_FLAG)         /* TC   (Test Control Flag) */
	191	#define SXM     ( m_STR1 & SXM_FLAG)        /* SXM  (Sign Extension Mode) */
	192	#define CARRY   ( m_STR1 & C_FLAG)          /* C    (Carry Flag for accumulator) */
	193	#define HM      ( m_STR1 & HM_FLAG)         /* HM   (Processor Hold Mode) */
	194	#define FSM     ( m_STR1 & FSM_FLAG)        /* FSM  (Frame Synchronization Mode - for serial port) */
	195	#define XF      ( m_STR1 & FSM_FLAG)        /* XF   (XF output pin status) */
	196	#define FO      ( m_STR1 & FO_FLAG)         /* FO   (Serial port Format In/Out mode) */
	197	#define TXM     ( m_STR1 & TXM_FLAG)        /* TXM  (Transmit Mode - for serial port) */
	198	#define PM      ( m_STR1 & PM_REG)          /* PM   (P register shift Mode. See SHIFT_Preg_TO_ALU below )*/
274	199
275		#define DMA     (DP | (cpustate->opcode.b.l & 0x7f))    /* address used in direct memory access operations */
276		#define DMApg0  (cpustate->opcode.b.l & 0x7f)           /* address used in direct memory access operations for sst instruction */
277		#define IND     cpustate->AR[ARP]                       /* address used in indirect memory access operations */
	200	#define DMA     (DP | (m_opcode.b.l & 0x7f))    /* address used in direct memory access operations */
	201	#define DMApg0  (m_opcode.b.l & 0x7f)           /* address used in direct memory access operations for sst instruction */
	202	#define IND     m_AR[ARP]                       /* address used in indirect memory access operations */
278	203
279		INLINE void CLR0(tms32025_state *cpustate, UINT16 flag) { cpustate->STR0 &= ~flag; cpustate->STR0 |= 0x0400; }
280		INLINE void SET0(tms32025_state *cpustate, UINT16 flag) { cpustate->STR0 |=  flag; cpustate->STR0 |= 0x0400; }
281		INLINE void CLR1(tms32025_state *cpustate, UINT16 flag) { cpustate->STR1 &= ~flag; cpustate->STR1 |= 0x0180; }
282		INLINE void SET1(tms32025_state *cpustate, UINT16 flag) { cpustate->STR1 |=  flag; cpustate->STR1 |= 0x0180; }
283	204
284		INLINE void MODIFY_DP(tms32025_state *cpustate, int data)
	205	const device_type TMS32025 = &device_creator<tms32025_device>;
	206	const device_type TMS32026 = &device_creator<tms32026_device>;
	207
	208
	209	tms32025_device::tms32025_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	210	: cpu_device(mconfig, TMS32025, "TMS32025", tag, owner, clock, "tms32025", __FILE__)
	211	, m_program_config("program", ENDIANNESS_BIG, 16, 16, -1)
	212	, m_data_config("data", ENDIANNESS_BIG, 16, 16, -1)
	213	, m_io_config("io", ENDIANNESS_BIG, 16, 17, -1)
285	214	{
286		cpustate->STR0 &= ~DP_REG;
287		cpustate->STR0 |= (data & DP_REG);
288		cpustate->STR0 |= 0x0400;
289	215	}
290		INLINE void MODIFY_PM(tms32025_state *cpustate, int data)
	216
	217
	218	tms32025_device::tms32025_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
	219	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
	220	, m_program_config("program", ENDIANNESS_BIG, 16, 16, -1)
	221	, m_data_config("data", ENDIANNESS_BIG, 16, 16, -1)
	222	, m_io_config("io", ENDIANNESS_BIG, 16, 16, -1)
291	223	{
292		cpustate->STR1 &= ~PM_REG;
293		cpustate->STR1 |= (data & PM_REG);
294		cpustate->STR1 |= 0x0180;
295	224	}
296		INLINE void MODIFY_ARP(tms32025_state *cpustate, int data)
	225
	226
	227	tms32026_device::tms32026_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	228	: tms32025_device(mconfig, TMS32026, "TMS32026", tag, owner, clock, "tms32026", __FILE__)
297	229	{
298		cpustate->STR1 &= ~ARB_REG;
299		cpustate->STR1 |= (cpustate->STR0 & ARP_REG);
300		cpustate->STR1 |= 0x0180;
301		cpustate->STR0 &= ~ARP_REG;
302		cpustate->STR0 |= ((data << 13) & ARP_REG);
303		cpustate->STR0 |= 0x0400;
304	230	}
305	231
306		INLINE UINT16 M_RDROM(tms32025_state *cpustate, offs_t addr)
	232
	233	offs_t tms32025_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
307	234	{
	235	extern CPU_DISASSEMBLE( tms32025 );
	236	return CPU_DISASSEMBLE_NAME(tms32025)(this, buffer, pc, oprom, opram, options);
	237	}
	238
	239
	240	void tms32025_device::CLR0(UINT16 flag) { m_STR0 &= ~flag; m_STR0 |= 0x0400; }
	241	void tms32025_device::SET0(UINT16 flag) { m_STR0 |=  flag; m_STR0 |= 0x0400; }
	242	void tms32025_device::CLR1(UINT16 flag) { m_STR1 &= ~flag; m_STR1 |= 0x0180; }
	243	void tms32025_device::SET1(UINT16 flag) { m_STR1 |=  flag; m_STR1 |= 0x0180; }
	244
	245	void tms32025_device::MODIFY_DP(int data)
	246	{
	247	m_STR0 &= ~DP_REG;
	248	m_STR0 |= (data & DP_REG);
	249	m_STR0 |= 0x0400;
	250	}
	251	void tms32025_device::MODIFY_PM(int data)
	252	{
	253	m_STR1 &= ~PM_REG;
	254	m_STR1 |= (data & PM_REG);
	255	m_STR1 |= 0x0180;
	256	}
	257	void tms32025_device::MODIFY_ARP(int data)
	258	{
	259	m_STR1 &= ~ARB_REG;
	260	m_STR1 |= (m_STR0 & ARP_REG);
	261	m_STR1 |= 0x0180;
	262	m_STR0 &= ~ARP_REG;
	263	m_STR0 |= ((data << 13) & ARP_REG);
	264	m_STR0 |= 0x0400;
	265	}
	266
	267	UINT16 tms32025_device::M_RDROM(offs_t addr)
	268	{
308	269	UINT16 *ram;
309	270	addr &= 0xffff;
310		ram = cpustate->pgmmap[addr >> 7];
	271	ram = m_pgmmap[addr >> 7];
311	272	if (ram) return ram[addr & 0x7f];
312		return cpustate->program->read_word(addr << 1);
	273	return m_program->read_word(addr << 1);
313	274	}
314	275
315		INLINE void M_WRTROM(tms32025_state *cpustate, offs_t addr, UINT16 data)
	276	void tms32025_device::M_WRTROM(offs_t addr, UINT16 data)
316	277	{
317	278	UINT16 *ram;
318	279	addr &= 0xffff;
319		ram = cpustate->pgmmap[addr >> 7];
	280	ram = m_pgmmap[addr >> 7];
320	281	if (ram) { ram[addr & 0x7f] = data; }
321		else cpustate->program->write_word(addr << 1, data);
	282	else m_program->write_word(addr << 1, data);
322	283	}
323	284
324		INLINE UINT16 M_RDRAM(tms32025_state *cpustate, offs_t addr)
	285	UINT16 tms32025_device::M_RDRAM(offs_t addr)
325	286	{
326	287	UINT16 *ram;
327	288	addr &= 0xffff;
328		ram = cpustate->datamap[addr >> 7];
	289	ram = m_datamap[addr >> 7];
329	290	if (ram) return ram[addr & 0x7f];
330		return cpustate->data->read_word(addr << 1);
	291	return m_data->read_word(addr << 1);
331	292	}
332	293
333		INLINE void M_WRTRAM(tms32025_state *cpustate, offs_t addr, UINT16 data)
	294	void tms32025_device::M_WRTRAM(offs_t addr, UINT16 data)
334	295	{
335	296	UINT16 *ram;
336	297	addr &= 0xffff;
337		ram = cpustate->datamap[addr >> 7];
	298	ram = m_datamap[addr >> 7];
338	299	if (ram) {
339	300	ram[addr & 0x7f] = data;
340		if(addr == 1 && ram == cpustate->intRAM && TXM) {
	301	if(addr == 1 && ram == m_intRAM && TXM) {
341	302	if(FSM)
342		cpustate->waiting_for_serial_frame = 1;
	303	m_waiting_for_serial_frame = 1;
343	304	else
344		cpustate->IFR |= 0x20;
	305	m_IFR |= 0x20;
345	306	}
346	307	}
347		else cpustate->data->write_word(addr << 1, data);
	308	else m_data->write_word(addr << 1, data);
348	309	}
349	310
350	311
351		static UINT16 reverse_carry_add(UINT16 arg0, UINT16 arg1 )
	312	UINT16 tms32025_device::reverse_carry_add(UINT16 arg0, UINT16 arg1 )
352	313	{
353	314	UINT16 result = 0;
354	315	int carry = 0;
r26837	r26838
364	325	return result;
365	326	}
366	327
367		INLINE void MODIFY_AR_ARP(tms32025_state *cpustate)
	328	void tms32025_device::MODIFY_AR_ARP()
368	329	{ /* modify address register referenced by ARP */
369		switch (cpustate->opcode.b.l & 0x70)        /* Cases ordered by predicted useage */
	330	switch (m_opcode.b.l & 0x70)        /* Cases ordered by predicted useage */
370	331	{
371	332	case 0x00: /* 000   nop      */
372	333	break;
373	334
374	335	case 0x10: /* 001   *-       */
375		cpustate->AR[ARP] -- ;
	336	m_AR[ARP] -- ;
376	337	break;
377	338
378	339	case 0x20: /* 010   *+       */
379		cpustate->AR[ARP] ++ ;
	340	m_AR[ARP] ++ ;
380	341	break;
381	342
382	343	case 0x30: /* 011   reserved */
383	344	break;
384	345
385	346	case 0x40: /* 100   *BR0-    */
386		cpustate->AR[ARP] = reverse_carry_add(cpustate->AR[ARP],-cpustate->AR[0]);
	347	m_AR[ARP] = reverse_carry_add(m_AR[ARP],-m_AR[0]);
387	348	break;
388	349
389	350	case 0x50: /* 101   *0-      */
390		cpustate->AR[ARP] -= cpustate->AR[0];
	351	m_AR[ARP] -= m_AR[0];
391	352	break;
392	353
393	354	case 0x60: /* 110   *0+      */
394		cpustate->AR[ARP] += cpustate->AR[0];
	355	m_AR[ARP] += m_AR[0];
395	356	break;
396	357
397	358	case 0x70: /* 111   *BR0+    */
398		cpustate->AR[ARP] += reverse_carry_add(cpustate->AR[ARP],cpustate->AR[0]);
	359	m_AR[ARP] += reverse_carry_add(m_AR[ARP],m_AR[0]);
399	360	break;
400	361	}
401	362
402		if( !cpustate->mHackIgnoreARP )
	363	if( !m_mHackIgnoreARP )
403	364	{
404		if (cpustate->opcode.b.l & 8)
	365	if (m_opcode.b.l & 8)
405	366	{ /* bit 3 determines if new value is loaded into ARP */
406		MODIFY_ARP(cpustate, (cpustate->opcode.b.l & 7) );
	367	MODIFY_ARP((m_opcode.b.l & 7) );
407	368	}
408	369	}
409	370	}
410	371
411		INLINE void CALCULATE_ADD_CARRY(tms32025_state *cpustate)
	372	void tms32025_device::CALCULATE_ADD_CARRY()
412	373	{
413		if ( (UINT32)(cpustate->oldacc.d) > (UINT32)(cpustate->ACC.d) ) {
414		SET1(cpustate, C_FLAG);
	374	if ( (UINT32)(m_oldacc.d) > (UINT32)(m_ACC.d) ) {
	375	SET1(C_FLAG);
415	376	}
416	377	else {
417		CLR1(cpustate, C_FLAG);
	378	CLR1(C_FLAG);
418	379	}
419	380	}
420	381
421		INLINE void CALCULATE_SUB_CARRY(tms32025_state *cpustate)
	382	void tms32025_device::CALCULATE_SUB_CARRY()
422	383	{
423		if ( (UINT32)(cpustate->oldacc.d) < (UINT32)(cpustate->ACC.d) ) {
424		CLR1(cpustate, C_FLAG);
	384	if ( (UINT32)(m_oldacc.d) < (UINT32)(m_ACC.d) ) {
	385	CLR1(C_FLAG);
425	386	}
426	387	else {
427		SET1(cpustate, C_FLAG);
	388	SET1(C_FLAG);
428	389	}
429	390	}
430	391
431		INLINE void CALCULATE_ADD_OVERFLOW(tms32025_state *cpustate, INT32 addval)
	392	void tms32025_device::CALCULATE_ADD_OVERFLOW(INT32 addval)
432	393	{
433		if ((INT32)((cpustate->ACC.d ^ addval) & (cpustate->oldacc.d ^ cpustate->ACC.d)) < 0)
	394	if ((INT32)((m_ACC.d ^ addval) & (m_oldacc.d ^ m_ACC.d)) < 0)
434	395	{
435		SET0(cpustate, OV_FLAG);
	396	SET0(OV_FLAG);
436	397	if (OVM)
437	398	{
438		cpustate->ACC.d = ((INT32)cpustate->oldacc.d < 0) ? 0x80000000 : 0x7fffffff;
	399	m_ACC.d = ((INT32)m_oldacc.d < 0) ? 0x80000000 : 0x7fffffff;
439	400	}
440	401	}
441	402	}
442		INLINE void CALCULATE_SUB_OVERFLOW(tms32025_state *cpustate, INT32 subval)
	403	void tms32025_device::CALCULATE_SUB_OVERFLOW(INT32 subval)
443	404	{
444		if ((INT32)((cpustate->oldacc.d ^ subval) & (cpustate->oldacc.d ^ cpustate->ACC.d)) < 0)
	405	if ((INT32)((m_oldacc.d ^ subval) & (m_oldacc.d ^ m_ACC.d)) < 0)
445	406	{
446		SET0(cpustate, OV_FLAG);
	407	SET0(OV_FLAG);
447	408	if (OVM)
448	409	{
449		cpustate->ACC.d = ((INT32)cpustate->oldacc.d < 0) ? 0x80000000 : 0x7fffffff;
	410	m_ACC.d = ((INT32)m_oldacc.d < 0) ? 0x80000000 : 0x7fffffff;
450	411	}
451	412	}
452	413	}
453	414
454		INLINE UINT16 POP_STACK(tms32025_state *cpustate)
	415	UINT16 tms32025_device::POP_STACK()
455	416	{
456		UINT16 data = cpustate->STACK[7];
457		cpustate->STACK[7] = cpustate->STACK[6];
458		cpustate->STACK[6] = cpustate->STACK[5];
459		cpustate->STACK[5] = cpustate->STACK[4];
460		cpustate->STACK[4] = cpustate->STACK[3];
461		cpustate->STACK[3] = cpustate->STACK[2];
462		cpustate->STACK[2] = cpustate->STACK[1];
463		cpustate->STACK[1] = cpustate->STACK[0];
	417	UINT16 data = m_STACK[7];
	418	m_STACK[7] = m_STACK[6];
	419	m_STACK[6] = m_STACK[5];
	420	m_STACK[5] = m_STACK[4];
	421	m_STACK[4] = m_STACK[3];
	422	m_STACK[3] = m_STACK[2];
	423	m_STACK[2] = m_STACK[1];
	424	m_STACK[1] = m_STACK[0];
464	425	return data;
465	426	}
466		INLINE void PUSH_STACK(tms32025_state *cpustate, UINT16 data)
	427	void tms32025_device::PUSH_STACK(UINT16 data)
467	428	{
468		cpustate->STACK[0] = cpustate->STACK[1];
469		cpustate->STACK[1] = cpustate->STACK[2];
470		cpustate->STACK[2] = cpustate->STACK[3];
471		cpustate->STACK[3] = cpustate->STACK[4];
472		cpustate->STACK[4] = cpustate->STACK[5];
473		cpustate->STACK[5] = cpustate->STACK[6];
474		cpustate->STACK[6] = cpustate->STACK[7];
475		cpustate->STACK[7] = data;
	429	m_STACK[0] = m_STACK[1];
	430	m_STACK[1] = m_STACK[2];
	431	m_STACK[2] = m_STACK[3];
	432	m_STACK[3] = m_STACK[4];
	433	m_STACK[4] = m_STACK[5];
	434	m_STACK[5] = m_STACK[6];
	435	m_STACK[6] = m_STACK[7];
	436	m_STACK[7] = data;
476	437	}
477	438
478		INLINE void SHIFT_Preg_TO_ALU(tms32025_state *cpustate)
	439	void tms32025_device::SHIFT_Preg_TO_ALU()
479	440	{
480	441	switch(PM)      /* PM (in STR1) is the shift mode for Preg */
481	442	{
482		case 0:     cpustate->ALU.d = cpustate->Preg.d; break;
483		case 1:     cpustate->ALU.d = (cpustate->Preg.d << 1); break;
484		case 2:     cpustate->ALU.d = (cpustate->Preg.d << 4); break;
485		case 3:     cpustate->ALU.d = (cpustate->Preg.d >> 6); if (cpustate->Preg.d & 0x80000000) cpustate->ALU.d |= 0xfc000000; break;
	443	case 0:     m_ALU.d = m_Preg.d; break;
	444	case 1:     m_ALU.d = (m_Preg.d << 1); break;
	445	case 2:     m_ALU.d = (m_Preg.d << 4); break;
	446	case 3:     m_ALU.d = (m_Preg.d >> 6); if (m_Preg.d & 0x80000000) m_ALU.d |= 0xfc000000; break;
486	447	default:    break;
487	448	}
488	449	}
489	450
490		INLINE void GETDATA(tms32025_state *cpustate, int shift,int signext)
	451	void tms32025_device::GETDATA(int shift,int signext)
491	452	{
492		if (cpustate->opcode.b.l & 0x80)
	453	if (m_opcode.b.l & 0x80)
493	454	{ /* indirect memory access */
494		cpustate->memaccess = IND;
	455	m_memaccess = IND;
495	456	}
496	457	else
497	458	{ /* direct memory address */
498		cpustate->memaccess = DMA;
	459	m_memaccess = DMA;
499	460	}
500	461
501		if (cpustate->memaccess >= 0x800)
	462	if (m_memaccess >= 0x800)
502	463	{
503		cpustate->external_mem_access = 1;  /* Pause if hold pin is active */
	464	m_external_mem_access = 1;  /* Pause if hold pin is active */
504	465	}
505	466	else
506	467	{
507		cpustate->external_mem_access = 0;
	468	m_external_mem_access = 0;
508	469	}
509	470
510		cpustate->ALU.d = (UINT16)M_RDRAM(cpustate, cpustate->memaccess);
511		if (signext) cpustate->ALU.d = (INT16)cpustate->ALU.d;
512		cpustate->ALU.d <<= shift;
	471	m_ALU.d = (UINT16)M_RDRAM(m_memaccess);
	472	if (signext) m_ALU.d = (INT16)m_ALU.d;
	473	m_ALU.d <<= shift;
513	474
514	475	/* next ARP */
515		if (cpustate->opcode.b.l & 0x80) MODIFY_AR_ARP(cpustate);
	476	if (m_opcode.b.l & 0x80) MODIFY_AR_ARP();
516	477	}
517	478
518		INLINE void PUTDATA(tms32025_state *cpustate, UINT16 data)
	479	void tms32025_device::PUTDATA(UINT16 data)
519	480	{
520		if (cpustate->opcode.b.l & 0x80) {
521		if (cpustate->memaccess >= 0x800) cpustate->external_mem_access = 1;    /* Pause if hold pin is active */
522		else cpustate->external_mem_access = 0;
	481	if (m_opcode.b.l & 0x80) {
	482	if (m_memaccess >= 0x800) m_external_mem_access = 1;    /* Pause if hold pin is active */
	483	else m_external_mem_access = 0;
523	484
524		M_WRTRAM(cpustate, IND, data);
525		MODIFY_AR_ARP(cpustate);
	485	M_WRTRAM(IND, data);
	486	MODIFY_AR_ARP();
526	487	}
527	488	else {
528		if (cpustate->memaccess >= 0x800) cpustate->external_mem_access = 1;    /* Pause if hold pin is active */
529		else cpustate->external_mem_access = 0;
	489	if (m_memaccess >= 0x800) m_external_mem_access = 1;    /* Pause if hold pin is active */
	490	else m_external_mem_access = 0;
530	491
531		M_WRTRAM(cpustate, DMA, data);
	492	M_WRTRAM(DMA, data);
532	493	}
533	494	}
534		INLINE void PUTDATA_SST(tms32025_state *cpustate, UINT16 data)
	495	void tms32025_device::PUTDATA_SST(UINT16 data)
535	496	{
536		if (cpustate->opcode.b.l & 0x80) cpustate->memaccess = IND;
537		else cpustate->memaccess = DMApg0;
	497	if (m_opcode.b.l & 0x80) m_memaccess = IND;
	498	else m_memaccess = DMApg0;
538	499
539		if (cpustate->memaccess >= 0x800) cpustate->external_mem_access = 1;        /* Pause if hold pin is active */
540		else cpustate->external_mem_access = 0;
	500	if (m_memaccess >= 0x800) m_external_mem_access = 1;        /* Pause if hold pin is active */
	501	else m_external_mem_access = 0;
541	502
542		if (cpustate->opcode.b.l & 0x80) {
543		cpustate->opcode.b.l &= 0xf7;                   /* Stop ARP changes */
544		MODIFY_AR_ARP(cpustate);
	503	if (m_opcode.b.l & 0x80) {
	504	m_opcode.b.l &= 0xf7;                   /* Stop ARP changes */
	505	MODIFY_AR_ARP();
545	506	}
546		M_WRTRAM(cpustate, cpustate->memaccess, data);
	507	M_WRTRAM(m_memaccess, data);
547	508	}
548	509
549	510
r26837	r26838
554	515
555	516	/* The following functions are here to fill the void for the */
556	517	/* opcode call functions. These functions are never actually called. */
557		static void opcodes_CE(tms32025_state *cpustate) { }
558		static void opcodes_Dx(tms32025_state *cpustate) { }
	518	void tms32025_device::opcodes_CE() { fatalerror("Should never get here!\n"); }
	519	void tms32025_device::opcodes_Dx() { fatalerror("Should never get here!\n"); }
559	520
560		static void illegal(tms32025_state *cpustate)
	521	void tms32025_device::illegal()
561	522	{
562		logerror("TMS32025:  PC = %04x,  Illegal opcode = %04x\n", (cpustate->PC-1), cpustate->opcode.w.l);
	523	logerror("TMS32025:  PC = %04x,  Illegal opcode = %04x\n", (m_PC-1), m_opcode.w.l);
563	524	}
564	525
565		static void abst(tms32025_state *cpustate)
	526	void tms32025_device::abst()
566	527	{
567		if ( (INT32)(cpustate->ACC.d) < 0 ) {
568		cpustate->ACC.d = -cpustate->ACC.d;
569		if (cpustate->ACC.d == 0x80000000) {
570		SET0(cpustate, OV_FLAG);
571		if (OVM) cpustate->ACC.d-- ;
	528	if ( (INT32)(m_ACC.d) < 0 ) {
	529	m_ACC.d = -m_ACC.d;
	530	if (m_ACC.d == 0x80000000) {
	531	SET0(OV_FLAG);
	532	if (OVM) m_ACC.d-- ;
572	533	}
573	534	}
574		CLR1(cpustate, C_FLAG);
	535	CLR1(C_FLAG);
575	536	}
576		static void add(tms32025_state *cpustate)
	537	void tms32025_device::add()
577	538	{
578		cpustate->oldacc.d = cpustate->ACC.d;
579		GETDATA(cpustate, (cpustate->opcode.b.h & 0xf), SXM);
580		cpustate->ACC.d += cpustate->ALU.d;
581		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
582		CALCULATE_ADD_CARRY(cpustate);
	539	m_oldacc.d = m_ACC.d;
	540	GETDATA((m_opcode.b.h & 0xf), SXM);
	541	m_ACC.d += m_ALU.d;
	542	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	543	CALCULATE_ADD_CARRY();
583	544	}
584		static void addc(tms32025_state *cpustate)
	545	void tms32025_device::addc()
585	546	{
586		cpustate->oldacc.d = cpustate->ACC.d;
587		GETDATA(cpustate, 0, 0);
588		if (CARRY) cpustate->ACC.d++;
589		cpustate->ACC.d += cpustate->ALU.d;
590		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
591		if (cpustate->ACC.d == cpustate->oldacc.d) {}   /* edge case, carry remains same */
592		else CALCULATE_ADD_CARRY(cpustate);
	547	m_oldacc.d = m_ACC.d;
	548	GETDATA(0, 0);
	549	if (CARRY) m_ACC.d++;
	550	m_ACC.d += m_ALU.d;
	551	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	552	if (m_ACC.d == m_oldacc.d) {}   /* edge case, carry remains same */
	553	else CALCULATE_ADD_CARRY();
593	554	}
594		static void addh(tms32025_state *cpustate)
	555	void tms32025_device::addh()
595	556	{
596		cpustate->oldacc.d = cpustate->ACC.d;
597		GETDATA(cpustate, 0, 0);
598		cpustate->ACC.w.h += cpustate->ALU.w.l;
599		if ( (UINT16)(cpustate->oldacc.w.h) > (UINT16)(cpustate->ACC.w.h) ) {
600		SET1(cpustate, C_FLAG); /* Carry flag is not cleared, if no carry occurred */
	557	m_oldacc.d = m_ACC.d;
	558	GETDATA(0, 0);
	559	m_ACC.w.h += m_ALU.w.l;
	560	if ( (UINT16)(m_oldacc.w.h) > (UINT16)(m_ACC.w.h) ) {
	561	SET1(C_FLAG); /* Carry flag is not cleared, if no carry occurred */
601	562	}
602		if ((INT16)((cpustate->ACC.w.h ^ cpustate->ALU.w.l) & (cpustate->oldacc.w.h ^ cpustate->ACC.w.h)) < 0) {
603		SET0(cpustate, OV_FLAG);
604		if (OVM) cpustate->ACC.w.h = ((INT16)cpustate->oldacc.w.h < 0) ? 0x8000 : 0x7fff;
	563	if ((INT16)((m_ACC.w.h ^ m_ALU.w.l) & (m_oldacc.w.h ^ m_ACC.w.h)) < 0) {
	564	SET0(OV_FLAG);
	565	if (OVM) m_ACC.w.h = ((INT16)m_oldacc.w.h < 0) ? 0x8000 : 0x7fff;
605	566	}
606	567	}
607		static void addk(tms32025_state *cpustate)
	568	void tms32025_device::addk()
608	569	{
609		cpustate->oldacc.d = cpustate->ACC.d;
610		cpustate->ALU.d = (UINT8)cpustate->opcode.b.l;
611		cpustate->ACC.d += cpustate->ALU.d;
612		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
613		CALCULATE_ADD_CARRY(cpustate);
	570	m_oldacc.d = m_ACC.d;
	571	m_ALU.d = (UINT8)m_opcode.b.l;
	572	m_ACC.d += m_ALU.d;
	573	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	574	CALCULATE_ADD_CARRY();
614	575	}
615		static void adds(tms32025_state *cpustate)
	576	void tms32025_device::adds()
616	577	{
617		cpustate->oldacc.d = cpustate->ACC.d;
618		GETDATA(cpustate, 0, 0);
619		cpustate->ACC.d += cpustate->ALU.d;
620		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
621		CALCULATE_ADD_CARRY(cpustate);
	578	m_oldacc.d = m_ACC.d;
	579	GETDATA(0, 0);
	580	m_ACC.d += m_ALU.d;
	581	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	582	CALCULATE_ADD_CARRY();
622	583	}
623		static void addt(tms32025_state *cpustate)
	584	void tms32025_device::addt()
624	585	{
625		cpustate->oldacc.d = cpustate->ACC.d;
626		GETDATA(cpustate, (cpustate->Treg & 0xf), SXM);
627		cpustate->ACC.d += cpustate->ALU.d;
628		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
629		CALCULATE_ADD_CARRY(cpustate);
	586	m_oldacc.d = m_ACC.d;
	587	GETDATA((m_Treg & 0xf), SXM);
	588	m_ACC.d += m_ALU.d;
	589	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	590	CALCULATE_ADD_CARRY();
630	591	}
631		static void adlk(tms32025_state *cpustate)
	592	void tms32025_device::adlk()
632	593	{
633		cpustate->oldacc.d = cpustate->ACC.d;
634		if (SXM) cpustate->ALU.d =  (INT16)M_RDOP_ARG(cpustate->PC);
635		else     cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
636		cpustate->PC++;
637		cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
638		cpustate->ACC.d += cpustate->ALU.d;
639		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
640		CALCULATE_ADD_CARRY(cpustate);
	594	m_oldacc.d = m_ACC.d;
	595	if (SXM) m_ALU.d =  (INT16)M_RDOP_ARG(m_PC);
	596	else     m_ALU.d = (UINT16)M_RDOP_ARG(m_PC);
	597	m_PC++;
	598	m_ALU.d <<= (m_opcode.b.h & 0xf);
	599	m_ACC.d += m_ALU.d;
	600	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	601	CALCULATE_ADD_CARRY();
641	602	}
642		static void adrk(tms32025_state *cpustate)
	603	void tms32025_device::adrk()
643	604	{
644		cpustate->AR[ARP] += cpustate->opcode.b.l;
	605	m_AR[ARP] += m_opcode.b.l;
645	606	}
646		static void and_(tms32025_state *cpustate)
	607	void tms32025_device::and_()
647	608	{
648		GETDATA(cpustate, 0, 0);
649		cpustate->ACC.d &= cpustate->ALU.d;
	609	GETDATA(0, 0);
	610	m_ACC.d &= m_ALU.d;
650	611	}
651		static void andk(tms32025_state *cpustate)
	612	void tms32025_device::andk()
652	613	{
653		cpustate->oldacc.d = cpustate->ACC.d;
654		cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
655		cpustate->PC++;
656		cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
657		cpustate->ACC.d &= cpustate->ALU.d;
	614	m_oldacc.d = m_ACC.d;
	615	m_ALU.d = (UINT16)M_RDOP_ARG(m_PC);
	616	m_PC++;
	617	m_ALU.d <<= (m_opcode.b.h & 0xf);
	618	m_ACC.d &= m_ALU.d;
658	619	}
659		static void apac(tms32025_state *cpustate)
	620	void tms32025_device::apac()
660	621	{
661		cpustate->oldacc.d = cpustate->ACC.d;
662		SHIFT_Preg_TO_ALU(cpustate);
663		cpustate->ACC.d += cpustate->ALU.d;
664		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
665		CALCULATE_ADD_CARRY(cpustate);
	622	m_oldacc.d = m_ACC.d;
	623	SHIFT_Preg_TO_ALU();
	624	m_ACC.d += m_ALU.d;
	625	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	626	CALCULATE_ADD_CARRY();
666	627	}
667		static void br(tms32025_state *cpustate)
	628	void tms32025_device::br()
668	629	{
669		SET_PC(M_RDOP_ARG(cpustate->PC));
670		MODIFY_AR_ARP(cpustate);
	630	SET_PC(M_RDOP_ARG(m_PC));
	631	MODIFY_AR_ARP();
671	632	}
672		static void bacc(tms32025_state *cpustate)
	633	void tms32025_device::bacc()
673	634	{
674		SET_PC(cpustate->ACC.w.l);
	635	SET_PC(m_ACC.w.l);
675	636	}
676		static void banz(tms32025_state *cpustate)
	637	void tms32025_device::banz()
677	638	{
678		if (cpustate->AR[ARP]) SET_PC(M_RDOP_ARG(cpustate->PC));
679		else cpustate->PC++ ;
680		MODIFY_AR_ARP(cpustate);
	639	if (m_AR[ARP]) SET_PC(M_RDOP_ARG(m_PC));
	640	else m_PC++ ;
	641	MODIFY_AR_ARP();
681	642	}
682		static void bbnz(tms32025_state *cpustate)
	643	void tms32025_device::bbnz()
683	644	{
684		if (TC) SET_PC(M_RDOP_ARG(cpustate->PC));
685		else cpustate->PC++ ;
686		MODIFY_AR_ARP(cpustate);
	645	if (TC) SET_PC(M_RDOP_ARG(m_PC));
	646	else m_PC++ ;
	647	MODIFY_AR_ARP();
687	648	}
688		static void bbz(tms32025_state *cpustate)
	649	void tms32025_device::bbz()
689	650	{
690		if (TC == 0) SET_PC(M_RDOP_ARG(cpustate->PC));
691		else cpustate->PC++ ;
692		MODIFY_AR_ARP(cpustate);
	651	if (TC == 0) SET_PC(M_RDOP_ARG(m_PC));
	652	else m_PC++ ;
	653	MODIFY_AR_ARP();
693	654	}
694		static void bc(tms32025_state *cpustate)
	655	void tms32025_device::bc()
695	656	{
696		if (CARRY) SET_PC(M_RDOP_ARG(cpustate->PC));
697		else cpustate->PC++ ;
698		MODIFY_AR_ARP(cpustate);
	657	if (CARRY) SET_PC(M_RDOP_ARG(m_PC));
	658	else m_PC++ ;
	659	MODIFY_AR_ARP();
699	660	}
700		static void bgez(tms32025_state *cpustate)
	661	void tms32025_device::bgez()
701	662	{
702		if ( (INT32)(cpustate->ACC.d) >= 0 ) SET_PC(M_RDOP_ARG(cpustate->PC));
703		else cpustate->PC++ ;
704		MODIFY_AR_ARP(cpustate);
	663	if ( (INT32)(m_ACC.d) >= 0 ) SET_PC(M_RDOP_ARG(m_PC));
	664	else m_PC++ ;
	665	MODIFY_AR_ARP();
705	666	}
706		static void bgz(tms32025_state *cpustate)
	667	void tms32025_device::bgz()
707	668	{
708		if ( (INT32)(cpustate->ACC.d) > 0 ) SET_PC(M_RDOP_ARG(cpustate->PC));
709		else cpustate->PC++ ;
710		MODIFY_AR_ARP(cpustate);
	669	if ( (INT32)(m_ACC.d) > 0 ) SET_PC(M_RDOP_ARG(m_PC));
	670	else m_PC++ ;
	671	MODIFY_AR_ARP();
711	672	}
712		static void bioz(tms32025_state *cpustate)
	673	void tms32025_device::bioz()
713	674	{
714		if (S_IN(TMS32025_BIO) != CLEAR_LINE) SET_PC(M_RDOP_ARG(cpustate->PC));
715		else cpustate->PC++ ;
716		MODIFY_AR_ARP(cpustate);
	675	if (S_IN(TMS32025_BIO) != CLEAR_LINE) SET_PC(M_RDOP_ARG(m_PC));
	676	else m_PC++ ;
	677	MODIFY_AR_ARP();
717	678	}
718		static void bit(tms32025_state *cpustate)
	679	void tms32025_device::bit()
719	680	{
720		GETDATA(cpustate, 0, 0);
721		if (cpustate->ALU.d & (0x8000 >> (cpustate->opcode.b.h & 0xf))) SET1(cpustate, TC_FLAG);
722		else CLR1(cpustate, TC_FLAG);
	681	GETDATA(0, 0);
	682	if (m_ALU.d & (0x8000 >> (m_opcode.b.h & 0xf))) SET1(TC_FLAG);
	683	else CLR1(TC_FLAG);
723	684	}
724		static void bitt(tms32025_state *cpustate)
	685	void tms32025_device::bitt()
725	686	{
726		GETDATA(cpustate, 0, 0);
727		if (cpustate->ALU.d & (0x8000 >> (cpustate->Treg & 0xf))) SET1(cpustate, TC_FLAG);
728		else CLR1(cpustate, TC_FLAG);
	687	GETDATA(0, 0);
	688	if (m_ALU.d & (0x8000 >> (m_Treg & 0xf))) SET1(TC_FLAG);
	689	else CLR1(TC_FLAG);
729	690	}
730		static void blez(tms32025_state *cpustate)
	691	void tms32025_device::blez()
731	692	{
732		if ( (INT32)(cpustate->ACC.d) <= 0 ) SET_PC(M_RDOP_ARG(cpustate->PC));
733		else cpustate->PC++ ;
734		MODIFY_AR_ARP(cpustate);
	693	if ( (INT32)(m_ACC.d) <= 0 ) SET_PC(M_RDOP_ARG(m_PC));
	694	else m_PC++ ;
	695	MODIFY_AR_ARP();
735	696	}
736		static void blkd(tms32025_state *cpustate)
	697	void tms32025_device::blkd()
737	698	{                                       /** Fix cycle timing **/
738		if (cpustate->init_load_addr) {
739		cpustate->PFC = M_RDOP_ARG(cpustate->PC);
740		cpustate->PC++;
	699	if (m_init_load_addr) {
	700	m_PFC = M_RDOP_ARG(m_PC);
	701	m_PC++;
741	702	}
742		cpustate->ALU.d = M_RDRAM(cpustate, cpustate->PFC);
743		PUTDATA(cpustate, cpustate->ALU.d);
744		cpustate->PFC++;
745		cpustate->tms32025_dec_cycles += (1*CLK);
	703	m_ALU.d = M_RDRAM(m_PFC);
	704	PUTDATA(m_ALU.d);
	705	m_PFC++;
	706	m_tms32025_dec_cycles += (1*CLK);
746	707	}
747		static void blkp(tms32025_state *cpustate)
	708	void tms32025_device::blkp()
748	709	{                                       /** Fix cycle timing **/
749		if (cpustate->init_load_addr) {
750		cpustate->PFC = M_RDOP_ARG(cpustate->PC);
751		cpustate->PC++;
	710	if (m_init_load_addr) {
	711	m_PFC = M_RDOP_ARG(m_PC);
	712	m_PC++;
752	713	}
753		cpustate->ALU.d = M_RDROM(cpustate, cpustate->PFC);
754		PUTDATA(cpustate, cpustate->ALU.d);
755		cpustate->PFC++;
756		cpustate->tms32025_dec_cycles += (2*CLK);
	714	m_ALU.d = M_RDROM(m_PFC);
	715	PUTDATA(m_ALU.d);
	716	m_PFC++;
	717	m_tms32025_dec_cycles += (2*CLK);
757	718	}
758		static void blz(tms32025_state *cpustate)
	719	void tms32025_device::blz()
759	720	{
760		if ( (INT32)(cpustate->ACC.d) <  0 ) SET_PC(M_RDOP_ARG(cpustate->PC));
761		else cpustate->PC++ ;
762		MODIFY_AR_ARP(cpustate);
	721	if ( (INT32)(m_ACC.d) <  0 ) SET_PC(M_RDOP_ARG(m_PC));
	722	else m_PC++ ;
	723	MODIFY_AR_ARP();
763	724	}
764		static void bnc(tms32025_state *cpustate)
	725	void tms32025_device::bnc()
765	726	{
766		if (CARRY == 0) SET_PC(M_RDOP_ARG(cpustate->PC));
767		else cpustate->PC++ ;
768		MODIFY_AR_ARP(cpustate);
	727	if (CARRY == 0) SET_PC(M_RDOP_ARG(m_PC));
	728	else m_PC++ ;
	729	MODIFY_AR_ARP();
769	730	}
770		static void bnv(tms32025_state *cpustate)
	731	void tms32025_device::bnv()
771	732	{
772		if (OV == 0) SET_PC(M_RDOP_ARG(cpustate->PC));
	733	if (OV == 0) SET_PC(M_RDOP_ARG(m_PC));
773	734	else {
774		cpustate->PC++ ;
775		CLR0(cpustate, OV_FLAG);
	735	m_PC++ ;
	736	CLR0(OV_FLAG);
776	737	}
777		MODIFY_AR_ARP(cpustate);
	738	MODIFY_AR_ARP();
778	739	}
779		static void bnz(tms32025_state *cpustate)
	740	void tms32025_device::bnz()
780	741	{
781		if (cpustate->ACC.d != 0) SET_PC(M_RDOP_ARG(cpustate->PC));
782		else cpustate->PC++ ;
783		MODIFY_AR_ARP(cpustate);
	742	if (m_ACC.d != 0) SET_PC(M_RDOP_ARG(m_PC));
	743	else m_PC++ ;
	744	MODIFY_AR_ARP();
784	745	}
785		static void bv(tms32025_state *cpustate)
	746	void tms32025_device::bv()
786	747	{
787	748	if (OV) {
788		SET_PC(M_RDOP_ARG(cpustate->PC));
789		CLR0(cpustate, OV_FLAG);
	749	SET_PC(M_RDOP_ARG(m_PC));
	750	CLR0(OV_FLAG);
790	751	}
791		else cpustate->PC++ ;
792		MODIFY_AR_ARP(cpustate);
	752	else m_PC++ ;
	753	MODIFY_AR_ARP();
793	754	}
794		static void bz(tms32025_state *cpustate)
	755	void tms32025_device::bz()
795	756	{
796		if (cpustate->ACC.d == 0) SET_PC(M_RDOP_ARG(cpustate->PC));
797		else cpustate->PC++ ;
798		MODIFY_AR_ARP(cpustate);
	757	if (m_ACC.d == 0) SET_PC(M_RDOP_ARG(m_PC));
	758	else m_PC++ ;
	759	MODIFY_AR_ARP();
799	760	}
800		static void cala(tms32025_state *cpustate)
	761	void tms32025_device::cala()
801	762	{
802		PUSH_STACK(cpustate, cpustate->PC);
803		SET_PC(cpustate->ACC.w.l);
	763	PUSH_STACK(m_PC);
	764	SET_PC(m_ACC.w.l);
804	765	}
805		static void call(tms32025_state *cpustate)
	766	void tms32025_device::call()
806	767	{
807		cpustate->PC++ ;
808		PUSH_STACK(cpustate, cpustate->PC);
809		SET_PC(M_RDOP_ARG((cpustate->PC - 1)));
810		MODIFY_AR_ARP(cpustate);
	768	m_PC++ ;
	769	PUSH_STACK(m_PC);
	770	SET_PC(M_RDOP_ARG((m_PC - 1)));
	771	MODIFY_AR_ARP();
811	772	}
812		static void cmpl(tms32025_state *cpustate)
	773	void tms32025_device::cmpl()
813	774	{
814		cpustate->ACC.d = (~cpustate->ACC.d);
	775	m_ACC.d = (~m_ACC.d);
815	776	}
816		static void cmpr(tms32025_state *cpustate)
	777	void tms32025_device::cmpr()
817	778	{
818		switch (cpustate->opcode.b.l & 3)
	779	switch (m_opcode.b.l & 3)
819	780	{
820		case 00:    if ( (UINT16)(cpustate->AR[ARP]) == (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG);
821		else CLR1(cpustate, TC_FLAG);
	781	case 00:    if ( (UINT16)(m_AR[ARP]) == (UINT16)(m_AR[0]) ) SET1(TC_FLAG);
	782	else CLR1(TC_FLAG);
822	783	break;
823		case 01:    if ( (UINT16)(cpustate->AR[ARP]) <  (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG);
824		else CLR1(cpustate, TC_FLAG);
	784	case 01:    if ( (UINT16)(m_AR[ARP]) <  (UINT16)(m_AR[0]) ) SET1(TC_FLAG);
	785	else CLR1(TC_FLAG);
825	786	break;
826		case 02:    if ( (UINT16)(cpustate->AR[ARP])  > (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG);
827		else CLR1(cpustate, TC_FLAG);
	787	case 02:    if ( (UINT16)(m_AR[ARP])  > (UINT16)(m_AR[0]) ) SET1(TC_FLAG);
	788	else CLR1(TC_FLAG);
828	789	break;
829		case 03:    if ( (UINT16)(cpustate->AR[ARP]) != (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG);
830		else CLR1(cpustate, TC_FLAG);
	790	case 03:    if ( (UINT16)(m_AR[ARP]) != (UINT16)(m_AR[0]) ) SET1(TC_FLAG);
	791	else CLR1(TC_FLAG);
831	792	break;
832	793	}
833	794	}
834		static void cnfd(tms32025_state *cpustate)  /** next two fetches need to use previous CNF value ! **/
	795	void tms32025_device::cnfd()  /** next two fetches need to use previous CNF value ! **/
835	796	{
836		CLR1(cpustate, CNF0_REG);
837		cpustate->datamap[4] = &cpustate->intRAM[0x200];            /* B0 */
838		cpustate->datamap[5] = &cpustate->intRAM[0x280];            /* B0 */
839		cpustate->pgmmap[510] = NULL;
840		cpustate->pgmmap[511] = NULL;
	797	CLR1(CNF0_REG);
	798	m_datamap[4] = &m_intRAM[0x200];            /* B0 */
	799	m_datamap[5] = &m_intRAM[0x280];            /* B0 */
	800	m_pgmmap[510] = NULL;
	801	m_pgmmap[511] = NULL;
841	802	}
842		static void cnfp(tms32025_state *cpustate)  /** next two fetches need to use previous CNF value ! **/
	803	void tms32025_device::cnfp()  /** next two fetches need to use previous CNF value ! **/
843	804	{
844		SET1(cpustate, CNF0_REG);
845		cpustate->datamap[4] = NULL;                        /* B0 */
846		cpustate->datamap[5] = NULL;                        /* B0 */
847		cpustate->pgmmap[510] = &cpustate->intRAM[0x200];
848		cpustate->pgmmap[511] = &cpustate->intRAM[0x280];
	805	SET1(CNF0_REG);
	806	m_datamap[4] = NULL;                        /* B0 */
	807	m_datamap[5] = NULL;                        /* B0 */
	808	m_pgmmap[510] = &m_intRAM[0x200];
	809	m_pgmmap[511] = &m_intRAM[0x280];
849	810	}
850		static void conf(tms32025_state *cpustate)  /** Need to reconfigure the memory blocks */
	811	void tms32025_device::conf()  /** Need to reconfigure the memory blocks */
851	812	{
852		switch (cpustate->opcode.b.l & 3)
	813	switch (m_opcode.b.l & 3)
853	814	{
854		case 00:    CLR1(cpustate, CNF1_REG); CLR1(cpustate, CNF0_REG);
855		cpustate->datamap[4] = &cpustate->intRAM[0x200];    /* B0 */
856		cpustate->datamap[5] = &cpustate->intRAM[0x280];    /* B0 */
857		cpustate->datamap[6] = &cpustate->intRAM[0x300];    /* B0 */
858		cpustate->datamap[7] = &cpustate->intRAM[0x380];    /* B0 */
859		cpustate->datamap[8] = &cpustate->intRAM[0x400];    /* B1 */
860		cpustate->datamap[9] = &cpustate->intRAM[0x480];    /* B1 */
861		cpustate->datamap[10] = &cpustate->intRAM[0x500];   /* B1 */
862		cpustate->datamap[11] = &cpustate->intRAM[0x580];   /* B1 */
863		cpustate->datamap[12] = &cpustate->intRAM[0x600];   /* B3 */
864		cpustate->datamap[13] = &cpustate->intRAM[0x680];   /* B3 */
865		cpustate->datamap[14] = &cpustate->intRAM[0x700];   /* B3 */
866		cpustate->datamap[15] = &cpustate->intRAM[0x780];   /* B3 */
867		cpustate->pgmmap[500] = NULL;
868		cpustate->pgmmap[501] = NULL;
869		cpustate->pgmmap[502] = NULL;
870		cpustate->pgmmap[503] = NULL;
871		cpustate->pgmmap[504] = NULL;
872		cpustate->pgmmap[505] = NULL;
873		cpustate->pgmmap[506] = NULL;
874		cpustate->pgmmap[507] = NULL;
875		cpustate->pgmmap[508] = NULL;
876		cpustate->pgmmap[509] = NULL;
877		cpustate->pgmmap[510] = NULL;
878		cpustate->pgmmap[511] = NULL;
	815	case 00:    CLR1(CNF1_REG); CLR1(CNF0_REG);
	816	m_datamap[4] = &m_intRAM[0x200];    /* B0 */
	817	m_datamap[5] = &m_intRAM[0x280];    /* B0 */
	818	m_datamap[6] = &m_intRAM[0x300];    /* B0 */
	819	m_datamap[7] = &m_intRAM[0x380];    /* B0 */
	820	m_datamap[8] = &m_intRAM[0x400];    /* B1 */
	821	m_datamap[9] = &m_intRAM[0x480];    /* B1 */
	822	m_datamap[10] = &m_intRAM[0x500];   /* B1 */
	823	m_datamap[11] = &m_intRAM[0x580];   /* B1 */
	824	m_datamap[12] = &m_intRAM[0x600];   /* B3 */
	825	m_datamap[13] = &m_intRAM[0x680];   /* B3 */
	826	m_datamap[14] = &m_intRAM[0x700];   /* B3 */
	827	m_datamap[15] = &m_intRAM[0x780];   /* B3 */
	828	m_pgmmap[500] = NULL;
	829	m_pgmmap[501] = NULL;
	830	m_pgmmap[502] = NULL;
	831	m_pgmmap[503] = NULL;
	832	m_pgmmap[504] = NULL;
	833	m_pgmmap[505] = NULL;
	834	m_pgmmap[506] = NULL;
	835	m_pgmmap[507] = NULL;
	836	m_pgmmap[508] = NULL;
	837	m_pgmmap[509] = NULL;
	838	m_pgmmap[510] = NULL;
	839	m_pgmmap[511] = NULL;
879	840	break;
880	841
881		case 01:    CLR1(cpustate, CNF1_REG); SET1(cpustate, CNF0_REG);
882		cpustate->datamap[4] = NULL;
883		cpustate->datamap[5] = NULL;
884		cpustate->datamap[6] = NULL;
885		cpustate->datamap[7] = NULL;
886		cpustate->datamap[8] = &cpustate->intRAM[0x400];    /* B1 */
887		cpustate->datamap[9] = &cpustate->intRAM[0x480];    /* B1 */
888		cpustate->datamap[10] = &cpustate->intRAM[0x500];   /* B1 */
889		cpustate->datamap[11] = &cpustate->intRAM[0x580];   /* B1 */
890		cpustate->datamap[12] = &cpustate->intRAM[0x600];   /* B3 */
891		cpustate->datamap[13] = &cpustate->intRAM[0x680];   /* B3 */
892		cpustate->datamap[14] = &cpustate->intRAM[0x700];   /* B3 */
893		cpustate->datamap[15] = &cpustate->intRAM[0x780];   /* B3 */
894		cpustate->pgmmap[500] = &cpustate->intRAM[0x200];   /* B0 */
895		cpustate->pgmmap[501] = &cpustate->intRAM[0x280];   /* B0 */
896		cpustate->pgmmap[502] = &cpustate->intRAM[0x300];   /* B0 */
897		cpustate->pgmmap[503] = &cpustate->intRAM[0x380];   /* B0 */
898		cpustate->pgmmap[504] = NULL;
899		cpustate->pgmmap[505] = NULL;
900		cpustate->pgmmap[506] = NULL;
901		cpustate->pgmmap[507] = NULL;
902		cpustate->pgmmap[508] = NULL;
903		cpustate->pgmmap[509] = NULL;
904		cpustate->pgmmap[510] = NULL;
905		cpustate->pgmmap[511] = NULL;
	842	case 01:    CLR1(CNF1_REG); SET1(CNF0_REG);
	843	m_datamap[4] = NULL;
	844	m_datamap[5] = NULL;
	845	m_datamap[6] = NULL;
	846	m_datamap[7] = NULL;
	847	m_datamap[8] = &m_intRAM[0x400];    /* B1 */
	848	m_datamap[9] = &m_intRAM[0x480];    /* B1 */
	849	m_datamap[10] = &m_intRAM[0x500];   /* B1 */
	850	m_datamap[11] = &m_intRAM[0x580];   /* B1 */
	851	m_datamap[12] = &m_intRAM[0x600];   /* B3 */
	852	m_datamap[13] = &m_intRAM[0x680];   /* B3 */
	853	m_datamap[14] = &m_intRAM[0x700];   /* B3 */
	854	m_datamap[15] = &m_intRAM[0x780];   /* B3 */
	855	m_pgmmap[500] = &m_intRAM[0x200];   /* B0 */
	856	m_pgmmap[501] = &m_intRAM[0x280];   /* B0 */
	857	m_pgmmap[502] = &m_intRAM[0x300];   /* B0 */
	858	m_pgmmap[503] = &m_intRAM[0x380];   /* B0 */
	859	m_pgmmap[504] = NULL;
	860	m_pgmmap[505] = NULL;
	861	m_pgmmap[506] = NULL;
	862	m_pgmmap[507] = NULL;
	863	m_pgmmap[508] = NULL;
	864	m_pgmmap[509] = NULL;
	865	m_pgmmap[510] = NULL;
	866	m_pgmmap[511] = NULL;
906	867	break;
907	868
908		case 02:    SET1(cpustate, CNF1_REG); CLR1(cpustate, CNF0_REG);
909		cpustate->datamap[4] = NULL;
910		cpustate->datamap[5] = NULL;
911		cpustate->datamap[6] = NULL;
912		cpustate->datamap[7] = NULL;
913		cpustate->datamap[8] = NULL;
914		cpustate->datamap[9] = NULL;
915		cpustate->datamap[10] = NULL;
916		cpustate->datamap[11] = NULL;
917		cpustate->datamap[12] = &cpustate->intRAM[0x600];   /* B3 */
918		cpustate->datamap[13] = &cpustate->intRAM[0x680];   /* B3 */
919		cpustate->datamap[14] = &cpustate->intRAM[0x700];   /* B3 */
920		cpustate->datamap[15] = &cpustate->intRAM[0x780];   /* B3 */
921		cpustate->pgmmap[500] = &cpustate->intRAM[0x200];   /* B0 */
922		cpustate->pgmmap[501] = &cpustate->intRAM[0x280];   /* B0 */
923		cpustate->pgmmap[502] = &cpustate->intRAM[0x300];   /* B0 */
924		cpustate->pgmmap[503] = &cpustate->intRAM[0x380];   /* B0 */
925		cpustate->pgmmap[504] = &cpustate->intRAM[0x400];   /* B1 */
926		cpustate->pgmmap[505] = &cpustate->intRAM[0x480];   /* B1 */
927		cpustate->pgmmap[506] = &cpustate->intRAM[0x500];   /* B1 */
928		cpustate->pgmmap[507] = &cpustate->intRAM[0x580];   /* B1 */
929		cpustate->pgmmap[508] = NULL;
930		cpustate->pgmmap[509] = NULL;
931		cpustate->pgmmap[510] = NULL;
932		cpustate->pgmmap[511] = NULL;
	869	case 02:    SET1(CNF1_REG); CLR1(CNF0_REG);
	870	m_datamap[4] = NULL;
	871	m_datamap[5] = NULL;
	872	m_datamap[6] = NULL;
	873	m_datamap[7] = NULL;
	874	m_datamap[8] = NULL;
	875	m_datamap[9] = NULL;
	876	m_datamap[10] = NULL;
	877	m_datamap[11] = NULL;
	878	m_datamap[12] = &m_intRAM[0x600];   /* B3 */
	879	m_datamap[13] = &m_intRAM[0x680];   /* B3 */
	880	m_datamap[14] = &m_intRAM[0x700];   /* B3 */
	881	m_datamap[15] = &m_intRAM[0x780];   /* B3 */
	882	m_pgmmap[500] = &m_intRAM[0x200];   /* B0 */
	883	m_pgmmap[501] = &m_intRAM[0x280];   /* B0 */
	884	m_pgmmap[502] = &m_intRAM[0x300];   /* B0 */
	885	m_pgmmap[503] = &m_intRAM[0x380];   /* B0 */
	886	m_pgmmap[504] = &m_intRAM[0x400];   /* B1 */
	887	m_pgmmap[505] = &m_intRAM[0x480];   /* B1 */
	888	m_pgmmap[506] = &m_intRAM[0x500];   /* B1 */
	889	m_pgmmap[507] = &m_intRAM[0x580];   /* B1 */
	890	m_pgmmap[508] = NULL;
	891	m_pgmmap[509] = NULL;
	892	m_pgmmap[510] = NULL;
	893	m_pgmmap[511] = NULL;
933	894	break;
934	895
935		case 03:    SET1(cpustate, CNF1_REG); SET1(cpustate, CNF0_REG);
936		cpustate->datamap[4] = NULL;
937		cpustate->datamap[5] = NULL;
938		cpustate->datamap[6] = NULL;
939		cpustate->datamap[7] = NULL;
940		cpustate->datamap[8] = NULL;
941		cpustate->datamap[9] = NULL;
942		cpustate->datamap[10] = NULL;
943		cpustate->datamap[11] = NULL;
944		cpustate->datamap[12] = NULL;
945		cpustate->datamap[13] = NULL;
946		cpustate->datamap[14] = NULL;
947		cpustate->datamap[15] = NULL;
948		cpustate->pgmmap[500] = &cpustate->intRAM[0x200];   /* B0 */
949		cpustate->pgmmap[501] = &cpustate->intRAM[0x280];   /* B0 */
950		cpustate->pgmmap[502] = &cpustate->intRAM[0x300];   /* B0 */
951		cpustate->pgmmap[503] = &cpustate->intRAM[0x380];   /* B0 */
952		cpustate->pgmmap[504] = &cpustate->intRAM[0x400];   /* B1 */
953		cpustate->pgmmap[505] = &cpustate->intRAM[0x480];   /* B1 */
954		cpustate->pgmmap[506] = &cpustate->intRAM[0x500];   /* B1 */
955		cpustate->pgmmap[507] = &cpustate->intRAM[0x580];   /* B1 */
956		cpustate->pgmmap[508] = &cpustate->intRAM[0x600];   /* B3 */
957		cpustate->pgmmap[509] = &cpustate->intRAM[0x680];   /* B3 */
958		cpustate->pgmmap[510] = &cpustate->intRAM[0x700];   /* B3 */
959		cpustate->pgmmap[511] = &cpustate->intRAM[0x780];   /* B3 */
	896	case 03:    SET1(CNF1_REG); SET1(CNF0_REG);
	897	m_datamap[4] = NULL;
	898	m_datamap[5] = NULL;
	899	m_datamap[6] = NULL;
	900	m_datamap[7] = NULL;
	901	m_datamap[8] = NULL;
	902	m_datamap[9] = NULL;
	903	m_datamap[10] = NULL;
	904	m_datamap[11] = NULL;
	905	m_datamap[12] = NULL;
	906	m_datamap[13] = NULL;
	907	m_datamap[14] = NULL;
	908	m_datamap[15] = NULL;
	909	m_pgmmap[500] = &m_intRAM[0x200];   /* B0 */
	910	m_pgmmap[501] = &m_intRAM[0x280];   /* B0 */
	911	m_pgmmap[502] = &m_intRAM[0x300];   /* B0 */
	912	m_pgmmap[503] = &m_intRAM[0x380];   /* B0 */
	913	m_pgmmap[504] = &m_intRAM[0x400];   /* B1 */
	914	m_pgmmap[505] = &m_intRAM[0x480];   /* B1 */
	915	m_pgmmap[506] = &m_intRAM[0x500];   /* B1 */
	916	m_pgmmap[507] = &m_intRAM[0x580];   /* B1 */
	917	m_pgmmap[508] = &m_intRAM[0x600];   /* B3 */
	918	m_pgmmap[509] = &m_intRAM[0x680];   /* B3 */
	919	m_pgmmap[510] = &m_intRAM[0x700];   /* B3 */
	920	m_pgmmap[511] = &m_intRAM[0x780];   /* B3 */
960	921	break;
961	922	}
962	923	}
963		static void dint(tms32025_state *cpustate)
	924	void tms32025_device::dint()
964	925	{
965		SET0(cpustate, INTM_FLAG);
	926	SET0(INTM_FLAG);
966	927	}
967		static void dmov(tms32025_state *cpustate)  /** Careful with how memory is configured !! */
	928	void tms32025_device::dmov()  /** Careful with how memory is configured !! */
968	929	{
969		GETDATA(cpustate, 0, 0);
970		M_WRTRAM(cpustate, (cpustate->memaccess + 1), cpustate->ALU.w.l);
	930	GETDATA(0, 0);
	931	M_WRTRAM((m_memaccess + 1), m_ALU.w.l);
971	932	}
972		static void eint(tms32025_state *cpustate)
	933	void tms32025_device::eint()
973	934	{
974		CLR0(cpustate, INTM_FLAG);
	935	CLR0(INTM_FLAG);
975	936	}
976		static void fort(tms32025_state *cpustate)
	937	void tms32025_device::fort()
977	938	{
978		if (cpustate->opcode.b.l & 1) SET1(cpustate, FO_FLAG);
979		else CLR1(cpustate, FO_FLAG);
	939	if (m_opcode.b.l & 1) SET1(FO_FLAG);
	940	else CLR1(FO_FLAG);
980	941	}
981		static void idle(tms32025_state *cpustate)
	942	void tms32025_device::idle()
982	943	{
983		CLR0(cpustate, INTM_FLAG);
984		cpustate->idle = 1;
	944	CLR0(INTM_FLAG);
	945	m_idle = 1;
985	946	}
986		static void in(tms32025_state *cpustate)
	947	void tms32025_device::in()
987	948	{
988		cpustate->ALU.w.l = P_IN( (cpustate->opcode.b.h & 0xf) );
989		PUTDATA(cpustate, cpustate->ALU.w.l);
	949	m_ALU.w.l = P_IN( (m_opcode.b.h & 0xf) );
	950	PUTDATA(m_ALU.w.l);
990	951	}
991		static void lac(tms32025_state *cpustate)
	952	void tms32025_device::lac()
992	953	{
993		GETDATA(cpustate, (cpustate->opcode.b.h & 0xf), SXM);
994		cpustate->ACC.d = cpustate->ALU.d;
	954	GETDATA((m_opcode.b.h & 0xf), SXM);
	955	m_ACC.d = m_ALU.d;
995	956	}
996		static void lack(tms32025_state *cpustate)      /* ZAC is a subset of this instruction */
	957	void tms32025_device::lack()      /* ZAC is a subset of this instruction */
997	958	{
998		cpustate->ACC.d = (UINT8)cpustate->opcode.b.l;
	959	m_ACC.d = (UINT8)m_opcode.b.l;
999	960	}
1000		static void lact(tms32025_state *cpustate)
	961	void tms32025_device::lact()
1001	962	{
1002		GETDATA(cpustate, (cpustate->Treg & 0xf), SXM);
1003		cpustate->ACC.d = cpustate->ALU.d;
	963	GETDATA((m_Treg & 0xf), SXM);
	964	m_ACC.d = m_ALU.d;
1004	965	}
1005		static void lalk(tms32025_state *cpustate)
	966	void tms32025_device::lalk()
1006	967	{
1007		if (SXM) cpustate->ALU.d =  (INT16)M_RDOP_ARG(cpustate->PC);
1008		else     cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
1009		cpustate->PC++;
1010		cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
1011		cpustate->ACC.d = cpustate->ALU.d;
	968	if (SXM) m_ALU.d =  (INT16)M_RDOP_ARG(m_PC);
	969	else     m_ALU.d = (UINT16)M_RDOP_ARG(m_PC);
	970	m_PC++;
	971	m_ALU.d <<= (m_opcode.b.h & 0xf);
	972	m_ACC.d = m_ALU.d;
1012	973	}
1013		static void lar_ar0(tms32025_state *cpustate)   { GETDATA(cpustate, 0, 0); cpustate->AR[0] = cpustate->ALU.w.l; }
1014		static void lar_ar1(tms32025_state *cpustate)   { GETDATA(cpustate, 0, 0); cpustate->AR[1] = cpustate->ALU.w.l; }
1015		static void lar_ar2(tms32025_state *cpustate)   { GETDATA(cpustate, 0, 0); cpustate->AR[2] = cpustate->ALU.w.l; }
1016		static void lar_ar3(tms32025_state *cpustate)   { GETDATA(cpustate, 0, 0); cpustate->AR[3] = cpustate->ALU.w.l; }
1017		static void lar_ar4(tms32025_state *cpustate)   { GETDATA(cpustate, 0, 0); cpustate->AR[4] = cpustate->ALU.w.l; }
1018		static void lar_ar5(tms32025_state *cpustate)   { GETDATA(cpustate, 0, 0); cpustate->AR[5] = cpustate->ALU.w.l; }
1019		static void lar_ar6(tms32025_state *cpustate)   { GETDATA(cpustate, 0, 0); cpustate->AR[6] = cpustate->ALU.w.l; }
1020		static void lar_ar7(tms32025_state *cpustate)   { GETDATA(cpustate, 0, 0); cpustate->AR[7] = cpustate->ALU.w.l; }
1021		static void lark_ar0(tms32025_state *cpustate)  { cpustate->AR[0] = cpustate->opcode.b.l; }
1022		static void lark_ar1(tms32025_state *cpustate)  { cpustate->AR[1] = cpustate->opcode.b.l; }
1023		static void lark_ar2(tms32025_state *cpustate)  { cpustate->AR[2] = cpustate->opcode.b.l; }
1024		static void lark_ar3(tms32025_state *cpustate)  { cpustate->AR[3] = cpustate->opcode.b.l; }
1025		static void lark_ar4(tms32025_state *cpustate)  { cpustate->AR[4] = cpustate->opcode.b.l; }
1026		static void lark_ar5(tms32025_state *cpustate)  { cpustate->AR[5] = cpustate->opcode.b.l; }
1027		static void lark_ar6(tms32025_state *cpustate)  { cpustate->AR[6] = cpustate->opcode.b.l; }
1028		static void lark_ar7(tms32025_state *cpustate)  { cpustate->AR[7] = cpustate->opcode.b.l; }
1029		static void ldp(tms32025_state *cpustate)
	974	void tms32025_device::lar_ar0()   { GETDATA(0, 0); m_AR[0] = m_ALU.w.l; }
	975	void tms32025_device::lar_ar1()   { GETDATA(0, 0); m_AR[1] = m_ALU.w.l; }
	976	void tms32025_device::lar_ar2()   { GETDATA(0, 0); m_AR[2] = m_ALU.w.l; }
	977	void tms32025_device::lar_ar3()   { GETDATA(0, 0); m_AR[3] = m_ALU.w.l; }
	978	void tms32025_device::lar_ar4()   { GETDATA(0, 0); m_AR[4] = m_ALU.w.l; }
	979	void tms32025_device::lar_ar5()   { GETDATA(0, 0); m_AR[5] = m_ALU.w.l; }
	980	void tms32025_device::lar_ar6()   { GETDATA(0, 0); m_AR[6] = m_ALU.w.l; }
	981	void tms32025_device::lar_ar7()   { GETDATA(0, 0); m_AR[7] = m_ALU.w.l; }
	982	void tms32025_device::lark_ar0()  { m_AR[0] = m_opcode.b.l; }
	983	void tms32025_device::lark_ar1()  { m_AR[1] = m_opcode.b.l; }
	984	void tms32025_device::lark_ar2()  { m_AR[2] = m_opcode.b.l; }
	985	void tms32025_device::lark_ar3()  { m_AR[3] = m_opcode.b.l; }
	986	void tms32025_device::lark_ar4()  { m_AR[4] = m_opcode.b.l; }
	987	void tms32025_device::lark_ar5()  { m_AR[5] = m_opcode.b.l; }
	988	void tms32025_device::lark_ar6()  { m_AR[6] = m_opcode.b.l; }
	989	void tms32025_device::lark_ar7()  { m_AR[7] = m_opcode.b.l; }
	990	void tms32025_device::ldp()
1030	991	{
1031		GETDATA(cpustate, 0, 0);
1032		MODIFY_DP(cpustate, cpustate->ALU.d & 0x1ff);
	992	GETDATA(0, 0);
	993	MODIFY_DP(m_ALU.d & 0x1ff);
1033	994	}
1034		static void ldpk(tms32025_state *cpustate)
	995	void tms32025_device::ldpk()
1035	996	{
1036		MODIFY_DP(cpustate, cpustate->opcode.w.l & 0x1ff);
	997	MODIFY_DP(m_opcode.w.l & 0x1ff);
1037	998	}
1038		static void lph(tms32025_state *cpustate)
	999	void tms32025_device::lph()
1039	1000	{
1040		GETDATA(cpustate, 0, 0);
1041		cpustate->Preg.w.h = cpustate->ALU.w.l;
	1001	GETDATA(0, 0);
	1002	m_Preg.w.h = m_ALU.w.l;
1042	1003	}
1043		static void lrlk(tms32025_state *cpustate)
	1004	void tms32025_device::lrlk()
1044	1005	{
1045		cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
1046		cpustate->PC++;
1047		cpustate->AR[cpustate->opcode.b.h & 7] = cpustate->ALU.w.l;
	1006	m_ALU.d = (UINT16)M_RDOP_ARG(m_PC);
	1007	m_PC++;
	1008	m_AR[m_opcode.b.h & 7] = m_ALU.w.l;
1048	1009	}
1049		static void lst(tms32025_state *cpustate)
	1010	void tms32025_device::lst()
1050	1011	{
1051		cpustate->mHackIgnoreARP = 1;
1052		GETDATA(cpustate, 0, 0);
1053		cpustate->mHackIgnoreARP = 0;
	1012	m_mHackIgnoreARP = 1;
	1013	GETDATA(0, 0);
	1014	m_mHackIgnoreARP = 0;
1054	1015
1055		cpustate->ALU.w.l &= (~INTM_FLAG);
1056		cpustate->STR0 &= INTM_FLAG;
1057		cpustate->STR0 |= cpustate->ALU.w.l;        /* Must not affect INTM */
1058		cpustate->STR0 |= 0x0400;
	1016	m_ALU.w.l &= (~INTM_FLAG);
	1017	m_STR0 &= INTM_FLAG;
	1018	m_STR0 |= m_ALU.w.l;        /* Must not affect INTM */
	1019	m_STR0 |= 0x0400;
1059	1020	}
1060		static void lst1(tms32025_state *cpustate)
	1021	void tms32025_device::lst1()
1061	1022	{
1062		cpustate->mHackIgnoreARP = 1;
1063		GETDATA(cpustate, 0, 0);
1064		cpustate->mHackIgnoreARP = 0;
	1023	m_mHackIgnoreARP = 1;
	1024	GETDATA(0, 0);
	1025	m_mHackIgnoreARP = 0;
1065	1026
1066		cpustate->STR1 = cpustate->ALU.w.l;
1067		cpustate->STR1 |= 0x0180;
1068		cpustate->STR0 &= (~ARP_REG);       /* ARB also gets copied to ARP */
1069		cpustate->STR0 |= (cpustate->STR1 & ARB_REG);
	1027	m_STR1 = m_ALU.w.l;
	1028	m_STR1 |= 0x0180;
	1029	m_STR0 &= (~ARP_REG);       /* ARB also gets copied to ARP */
	1030	m_STR0 |= (m_STR1 & ARB_REG);
1070	1031	}
1071		static void lt(tms32025_state *cpustate)
	1032	void tms32025_device::lt()
1072	1033	{
1073		GETDATA(cpustate, 0, 0);
1074		cpustate->Treg = cpustate->ALU.w.l;
	1034	GETDATA(0, 0);
	1035	m_Treg = m_ALU.w.l;
1075	1036	}
1076		static void lta(tms32025_state *cpustate)
	1037	void tms32025_device::lta()
1077	1038	{
1078		cpustate->oldacc.d = cpustate->ACC.d;
1079		GETDATA(cpustate, 0, 0);
1080		cpustate->Treg = cpustate->ALU.w.l;
1081		SHIFT_Preg_TO_ALU(cpustate);
1082		cpustate->ACC.d += cpustate->ALU.d;
1083		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1084		CALCULATE_ADD_CARRY(cpustate);
	1039	m_oldacc.d = m_ACC.d;
	1040	GETDATA(0, 0);
	1041	m_Treg = m_ALU.w.l;
	1042	SHIFT_Preg_TO_ALU();
	1043	m_ACC.d += m_ALU.d;
	1044	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	1045	CALCULATE_ADD_CARRY();
1085	1046	}
1086		static void ltd(tms32025_state *cpustate)   /** Careful with how memory is configured !! */
	1047	void tms32025_device::ltd()   /** Careful with how memory is configured !! */
1087	1048	{
1088		cpustate->oldacc.d = cpustate->ACC.d;
1089		GETDATA(cpustate, 0, 0);
1090		cpustate->Treg = cpustate->ALU.w.l;
1091		M_WRTRAM(cpustate, (cpustate->memaccess+1), cpustate->ALU.w.l);
1092		SHIFT_Preg_TO_ALU(cpustate);
1093		cpustate->ACC.d += cpustate->ALU.d;
1094		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1095		CALCULATE_ADD_CARRY(cpustate);
	1049	m_oldacc.d = m_ACC.d;
	1050	GETDATA(0, 0);
	1051	m_Treg = m_ALU.w.l;
	1052	M_WRTRAM((m_memaccess+1), m_ALU.w.l);
	1053	SHIFT_Preg_TO_ALU();
	1054	m_ACC.d += m_ALU.d;
	1055	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	1056	CALCULATE_ADD_CARRY();
1096	1057	}
1097		static void ltp(tms32025_state *cpustate)
	1058	void tms32025_device::ltp()
1098	1059	{
1099		cpustate->oldacc.d = cpustate->ACC.d;
1100		GETDATA(cpustate, 0, 0);
1101		cpustate->Treg = cpustate->ALU.w.l;
1102		SHIFT_Preg_TO_ALU(cpustate);
1103		cpustate->ACC.d = cpustate->ALU.d;
	1060	m_oldacc.d = m_ACC.d;
	1061	GETDATA(0, 0);
	1062	m_Treg = m_ALU.w.l;
	1063	SHIFT_Preg_TO_ALU();
	1064	m_ACC.d = m_ALU.d;
1104	1065	}
1105		static void lts(tms32025_state *cpustate)
	1066	void tms32025_device::lts()
1106	1067	{
1107		cpustate->oldacc.d = cpustate->ACC.d;
1108		GETDATA(cpustate, 0, 0);
1109		cpustate->Treg = cpustate->ALU.w.l;
1110		SHIFT_Preg_TO_ALU(cpustate);
1111		cpustate->ACC.d -= cpustate->ALU.d;
1112		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1113		CALCULATE_SUB_CARRY(cpustate);
	1068	m_oldacc.d = m_ACC.d;
	1069	GETDATA(0, 0);
	1070	m_Treg = m_ALU.w.l;
	1071	SHIFT_Preg_TO_ALU();
	1072	m_ACC.d -= m_ALU.d;
	1073	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1074	CALCULATE_SUB_CARRY();
1114	1075	}
1115		static void mac(tms32025_state *cpustate)           /** RAM blocks B0,B1,B2 may be important ! */
	1076	void tms32025_device::mac()           /** RAM blocks B0,B1,B2 may be important ! */
1116	1077	{                               /** Fix cycle timing **/
1117		cpustate->oldacc.d = cpustate->ACC.d;
1118		if (cpustate->init_load_addr) {
1119		cpustate->PFC = M_RDOP_ARG(cpustate->PC);
1120		cpustate->PC++;
	1078	m_oldacc.d = m_ACC.d;
	1079	if (m_init_load_addr) {
	1080	m_PFC = M_RDOP_ARG(m_PC);
	1081	m_PC++;
1121	1082	}
1122		SHIFT_Preg_TO_ALU(cpustate);
1123		cpustate->ACC.d += cpustate->ALU.d;
1124		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1125		CALCULATE_ADD_CARRY(cpustate);
1126		GETDATA(cpustate, 0, 0);
1127		cpustate->Treg = cpustate->ALU.w.l;
1128		cpustate->Preg.d = ( (INT16)cpustate->ALU.w.l * (INT16)M_RDROM(cpustate, cpustate->PFC) );
1129		cpustate->PFC++;
1130		cpustate->tms32025_dec_cycles += (2*CLK);
	1083	SHIFT_Preg_TO_ALU();
	1084	m_ACC.d += m_ALU.d;
	1085	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	1086	CALCULATE_ADD_CARRY();
	1087	GETDATA(0, 0);
	1088	m_Treg = m_ALU.w.l;
	1089	m_Preg.d = ( (INT16)m_ALU.w.l * (INT16)M_RDROM(m_PFC) );
	1090	m_PFC++;
	1091	m_tms32025_dec_cycles += (2*CLK);
1131	1092	}
1132		static void macd(tms32025_state *cpustate)          /** RAM blocks B0,B1,B2 may be important ! */
	1093	void tms32025_device::macd()          /** RAM blocks B0,B1,B2 may be important ! */
1133	1094	{                                                   /** Fix cycle timing **/
1134		cpustate->oldacc.d = cpustate->ACC.d;
1135		if (cpustate->init_load_addr) {
1136		cpustate->PFC = M_RDOP_ARG(cpustate->PC);
1137		cpustate->PC++;
	1095	m_oldacc.d = m_ACC.d;
	1096	if (m_init_load_addr) {
	1097	m_PFC = M_RDOP_ARG(m_PC);
	1098	m_PC++;
1138	1099	}
1139		SHIFT_Preg_TO_ALU(cpustate);
1140		cpustate->ACC.d += cpustate->ALU.d;
1141		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1142		CALCULATE_ADD_CARRY(cpustate);
1143		GETDATA(cpustate, 0, 0);
1144		if ( (cpustate->opcode.b.l & 0x80) || cpustate->init_load_addr ) {  /* No writing during repitition, or DMA mode */
1145		M_WRTRAM(cpustate, (cpustate->memaccess+1), cpustate->ALU.w.l);
	1100	SHIFT_Preg_TO_ALU();
	1101	m_ACC.d += m_ALU.d;
	1102	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	1103	CALCULATE_ADD_CARRY();
	1104	GETDATA(0, 0);
	1105	if ( (m_opcode.b.l & 0x80) || m_init_load_addr ) {  /* No writing during repitition, or DMA mode */
	1106	M_WRTRAM((m_memaccess+1), m_ALU.w.l);
1146	1107	}
1147		cpustate->Treg = cpustate->ALU.w.l;
1148		cpustate->Preg.d = ( (INT16)cpustate->ALU.w.l * (INT16)M_RDROM(cpustate, cpustate->PFC) );
1149		cpustate->PFC++;
1150		cpustate->tms32025_dec_cycles += (2*CLK);
	1108	m_Treg = m_ALU.w.l;
	1109	m_Preg.d = ( (INT16)m_ALU.w.l * (INT16)M_RDROM(m_PFC) );
	1110	m_PFC++;
	1111	m_tms32025_dec_cycles += (2*CLK);
1151	1112	}
1152		static void mar(tms32025_state *cpustate)       /* LARP and NOP are a subset of this instruction */
	1113	void tms32025_device::mar()       /* LARP and NOP are a subset of this instruction */
1153	1114	{
1154		if (cpustate->opcode.b.l & 0x80) MODIFY_AR_ARP(cpustate);
	1115	if (m_opcode.b.l & 0x80) MODIFY_AR_ARP();
1155	1116	}
1156		static void mpy(tms32025_state *cpustate)
	1117	void tms32025_device::mpy()
1157	1118	{
1158		GETDATA(cpustate, 0, 0);
1159		cpustate->Preg.d = (INT16)(cpustate->ALU.w.l) * (INT16)(cpustate->Treg);
	1119	GETDATA(0, 0);
	1120	m_Preg.d = (INT16)(m_ALU.w.l) * (INT16)(m_Treg);
1160	1121	}
1161		static void mpya(tms32025_state *cpustate)
	1122	void tms32025_device::mpya()
1162	1123	{
1163		cpustate->oldacc.d = cpustate->ACC.d;
1164		SHIFT_Preg_TO_ALU(cpustate);
1165		cpustate->ACC.d += cpustate->ALU.d;
1166		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1167		CALCULATE_ADD_CARRY(cpustate);
1168		GETDATA(cpustate, 0, 0);
1169		cpustate->Preg.d = (INT16)(cpustate->ALU.w.l) * (INT16)(cpustate->Treg);
	1124	m_oldacc.d = m_ACC.d;
	1125	SHIFT_Preg_TO_ALU();
	1126	m_ACC.d += m_ALU.d;
	1127	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	1128	CALCULATE_ADD_CARRY();
	1129	GETDATA(0, 0);
	1130	m_Preg.d = (INT16)(m_ALU.w.l) * (INT16)(m_Treg);
1170	1131	}
1171		static void mpyk(tms32025_state *cpustate)
	1132	void tms32025_device::mpyk()
1172	1133	{
1173		cpustate->Preg.d = (INT16)cpustate->Treg * ((INT16)(cpustate->opcode.w.l << 3) >> 3);
	1134	m_Preg.d = (INT16)m_Treg * ((INT16)(m_opcode.w.l << 3) >> 3);
1174	1135
1175	1136	}
1176		static void mpys(tms32025_state *cpustate)
	1137	void tms32025_device::mpys()
1177	1138	{
1178		cpustate->oldacc.d = cpustate->ACC.d;
1179		SHIFT_Preg_TO_ALU(cpustate);
1180		cpustate->ACC.d -= cpustate->ALU.d;
1181		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1182		CALCULATE_SUB_CARRY(cpustate);
1183		GETDATA(cpustate, 0, 0);
1184		cpustate->Preg.d = (INT16)(cpustate->ALU.w.l) * (INT16)(cpustate->Treg);
	1139	m_oldacc.d = m_ACC.d;
	1140	SHIFT_Preg_TO_ALU();
	1141	m_ACC.d -= m_ALU.d;
	1142	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1143	CALCULATE_SUB_CARRY();
	1144	GETDATA(0, 0);
	1145	m_Preg.d = (INT16)(m_ALU.w.l) * (INT16)(m_Treg);
1185	1146	}
1186		static void mpyu(tms32025_state *cpustate)
	1147	void tms32025_device::mpyu()
1187	1148	{
1188		GETDATA(cpustate, 0, 0);
1189		cpustate->Preg.d = (UINT16)(cpustate->ALU.w.l) * (UINT16)(cpustate->Treg);
	1149	GETDATA(0, 0);
	1150	m_Preg.d = (UINT16)(m_ALU.w.l) * (UINT16)(m_Treg);
1190	1151	}
1191		static void neg(tms32025_state *cpustate)
	1152	void tms32025_device::neg()
1192	1153	{
1193		if (cpustate->ACC.d == 0x80000000) {
1194		SET0(cpustate, OV_FLAG);
1195		if (OVM) cpustate->ACC.d = 0x7fffffff;
	1154	if (m_ACC.d == 0x80000000) {
	1155	SET0(OV_FLAG);
	1156	if (OVM) m_ACC.d = 0x7fffffff;
1196	1157	}
1197		else cpustate->ACC.d = -cpustate->ACC.d;
1198		if (cpustate->ACC.d) CLR0(cpustate, C_FLAG);
1199		else SET0(cpustate, C_FLAG);
	1158	else m_ACC.d = -m_ACC.d;
	1159	if (m_ACC.d) CLR0(C_FLAG);
	1160	else SET0(C_FLAG);
1200	1161	}
1201	1162	/*
1202		static void nop(tms32025_state *cpustate) { }   // NOP is a subset of the MAR instruction
	1163	void tms32025_device::nop() { }   // NOP is a subset of the MAR instruction
1203	1164	*/
1204		static void norm(tms32025_state *cpustate)
	1165	void tms32025_device::norm()
1205	1166	{
1206		if (cpustate->ACC.d !=0 && (INT32)(cpustate->ACC.d ^ (cpustate->ACC.d << 1)) >= 0)
	1167	if (m_ACC.d !=0 && (INT32)(m_ACC.d ^ (m_ACC.d << 1)) >= 0)
1207	1168	{
1208		CLR1(cpustate, TC_FLAG);
1209		cpustate->ACC.d <<= 1;
1210		MODIFY_AR_ARP(cpustate);
	1169	CLR1(TC_FLAG);
	1170	m_ACC.d <<= 1;
	1171	MODIFY_AR_ARP();
1211	1172	}
1212		else SET1(cpustate, TC_FLAG);
	1173	else SET1(TC_FLAG);
1213	1174	}
1214		static void or_(tms32025_state *cpustate)
	1175	void tms32025_device::or_()
1215	1176	{
1216		GETDATA(cpustate, 0, 0);
1217		cpustate->ACC.w.l |= cpustate->ALU.w.l;
	1177	GETDATA(0, 0);
	1178	m_ACC.w.l |= m_ALU.w.l;
1218	1179	}
1219		static void ork(tms32025_state *cpustate)
	1180	void tms32025_device::ork()
1220	1181	{
1221		cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
1222		cpustate->PC++;
1223		cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
1224		cpustate->ACC.d |=  (cpustate->ALU.d);
	1182	m_ALU.d = (UINT16)M_RDOP_ARG(m_PC);
	1183	m_PC++;
	1184	m_ALU.d <<= (m_opcode.b.h & 0xf);
	1185	m_ACC.d |=  (m_ALU.d);
1225	1186	}
1226		static void out(tms32025_state *cpustate)
	1187	void tms32025_device::out()
1227	1188	{
1228		GETDATA(cpustate, 0, 0);
1229		P_OUT( (cpustate->opcode.b.h & 0xf), cpustate->ALU.w.l );
	1189	GETDATA(0, 0);
	1190	P_OUT( (m_opcode.b.h & 0xf), m_ALU.w.l );
1230	1191	}
1231		static void pac(tms32025_state *cpustate)
	1192	void tms32025_device::pac()
1232	1193	{
1233		SHIFT_Preg_TO_ALU(cpustate);
1234		cpustate->ACC.d = cpustate->ALU.d;
	1194	SHIFT_Preg_TO_ALU();
	1195	m_ACC.d = m_ALU.d;
1235	1196	}
1236		static void pop(tms32025_state *cpustate)
	1197	void tms32025_device::pop()
1237	1198	{
1238		cpustate->ACC.d = (UINT16)POP_STACK(cpustate);
	1199	m_ACC.d = (UINT16)POP_STACK();
1239	1200	}
1240		static void popd(tms32025_state *cpustate)
	1201	void tms32025_device::popd()
1241	1202	{
1242		cpustate->ALU.d = (UINT16)POP_STACK(cpustate);
1243		PUTDATA(cpustate, cpustate->ALU.w.l);
	1203	m_ALU.d = (UINT16)POP_STACK();
	1204	PUTDATA(m_ALU.w.l);
1244	1205	}
1245		static void pshd(tms32025_state *cpustate)
	1206	void tms32025_device::pshd()
1246	1207	{
1247		GETDATA(cpustate, 0, 0);
1248		PUSH_STACK(cpustate, cpustate->ALU.w.l);
	1208	GETDATA(0, 0);
	1209	PUSH_STACK(m_ALU.w.l);
1249	1210	}
1250		static void push(tms32025_state *cpustate)
	1211	void tms32025_device::push()
1251	1212	{
1252		PUSH_STACK(cpustate, cpustate->ACC.w.l);
	1213	PUSH_STACK(m_ACC.w.l);
1253	1214	}
1254		static void rc(tms32025_state *cpustate)
	1215	void tms32025_device::rc()
1255	1216	{
1256		CLR1(cpustate, C_FLAG);
	1217	CLR1(C_FLAG);
1257	1218	}
1258		static void ret(tms32025_state *cpustate)
	1219	void tms32025_device::ret()
1259	1220	{
1260		SET_PC(POP_STACK(cpustate));
	1221	SET_PC(POP_STACK());
1261	1222	}
1262		static void rfsm(tms32025_state *cpustate)              /** serial port mode */
	1223	void tms32025_device::rfsm()              /** serial port mode */
1263	1224	{
1264		CLR1(cpustate, FSM_FLAG);
	1225	CLR1(FSM_FLAG);
1265	1226	}
1266		static void rhm(tms32025_state *cpustate)
	1227	void tms32025_device::rhm()
1267	1228	{
1268		CLR1(cpustate, HM_FLAG);
	1229	CLR1(HM_FLAG);
1269	1230	}
1270		static void rol(tms32025_state *cpustate)
	1231	void tms32025_device::rol()
1271	1232	{
1272		cpustate->ALU.d = cpustate->ACC.d;
1273		cpustate->ACC.d <<= 1;
1274		if (CARRY) cpustate->ACC.d |= 1;
1275		if (cpustate->ALU.d & 0x80000000) SET1(cpustate, C_FLAG);
1276		else CLR1(cpustate, C_FLAG);
	1233	m_ALU.d = m_ACC.d;
	1234	m_ACC.d <<= 1;
	1235	if (CARRY) m_ACC.d |= 1;
	1236	if (m_ALU.d & 0x80000000) SET1(C_FLAG);
	1237	else CLR1(C_FLAG);
1277	1238	}
1278		static void ror(tms32025_state *cpustate)
	1239	void tms32025_device::ror()
1279	1240	{
1280		cpustate->ALU.d = cpustate->ACC.d;
1281		cpustate->ACC.d >>= 1;
1282		if (CARRY) cpustate->ACC.d |= 0x80000000;
1283		if (cpustate->ALU.d & 1) SET1(cpustate, C_FLAG);
1284		else CLR1(cpustate, C_FLAG);
	1241	m_ALU.d = m_ACC.d;
	1242	m_ACC.d >>= 1;
	1243	if (CARRY) m_ACC.d |= 0x80000000;
	1244	if (m_ALU.d & 1) SET1(C_FLAG);
	1245	else CLR1(C_FLAG);
1285	1246	}
1286		static void rovm(tms32025_state *cpustate)
	1247	void tms32025_device::rovm()
1287	1248	{
1288		CLR0(cpustate, OVM_FLAG);
	1249	CLR0(OVM_FLAG);
1289	1250	}
1290		static void rpt(tms32025_state *cpustate)
	1251	void tms32025_device::rpt()
1291	1252	{
1292		GETDATA(cpustate, 0, 0);
1293		cpustate->RPTC = cpustate->ALU.b.l;
1294		cpustate->init_load_addr = 2;       /* Initiate repeat mode */
	1253	GETDATA(0, 0);
	1254	m_RPTC = m_ALU.b.l;
	1255	m_init_load_addr = 2;       /* Initiate repeat mode */
1295	1256	}
1296		static void rptk(tms32025_state *cpustate)
	1257	void tms32025_device::rptk()
1297	1258	{
1298		cpustate->RPTC = cpustate->opcode.b.l;
1299		cpustate->init_load_addr = 2;       /* Initiate repeat mode */
	1259	m_RPTC = m_opcode.b.l;
	1260	m_init_load_addr = 2;       /* Initiate repeat mode */
1300	1261	}
1301		static void rsxm(tms32025_state *cpustate)
	1262	void tms32025_device::rsxm()
1302	1263	{
1303		CLR1(cpustate, SXM_FLAG);
	1264	CLR1(SXM_FLAG);
1304	1265	}
1305		static void rtc(tms32025_state *cpustate)
	1266	void tms32025_device::rtc()
1306	1267	{
1307		CLR1(cpustate, TC_FLAG);
	1268	CLR1(TC_FLAG);
1308	1269	}
1309		static void rtxm(tms32025_state *cpustate)  /** Serial port stuff */
	1270	void tms32025_device::rtxm()  /** Serial port stuff */
1310	1271	{
1311		CLR1(cpustate, TXM_FLAG);
	1272	CLR1(TXM_FLAG);
1312	1273	}
1313		static void rxf(tms32025_state *cpustate)
	1274	void tms32025_device::rxf()
1314	1275	{
1315		CLR1(cpustate, XF_FLAG);
	1276	CLR1(XF_FLAG);
1316	1277	S_OUT(TMS32025_XF,CLEAR_LINE);
1317	1278	}
1318		static void sach(tms32025_state *cpustate)
	1279	void tms32025_device::sach()
1319	1280	{
1320		cpustate->ALU.d = (cpustate->ACC.d << (cpustate->opcode.b.h & 7));
1321		PUTDATA(cpustate, cpustate->ALU.w.h);
	1281	m_ALU.d = (m_ACC.d << (m_opcode.b.h & 7));
	1282	PUTDATA(m_ALU.w.h);
1322	1283	}
1323		static void sacl(tms32025_state *cpustate)
	1284	void tms32025_device::sacl()
1324	1285	{
1325		cpustate->ALU.d = (cpustate->ACC.d << (cpustate->opcode.b.h & 7));
1326		PUTDATA(cpustate, cpustate->ALU.w.l);
	1286	m_ALU.d = (m_ACC.d << (m_opcode.b.h & 7));
	1287	PUTDATA(m_ALU.w.l);
1327	1288	}
1328		static void sar_ar0(tms32025_state *cpustate)   { PUTDATA(cpustate, cpustate->AR[0]); }
1329		static void sar_ar1(tms32025_state *cpustate)   { PUTDATA(cpustate, cpustate->AR[1]); }
1330		static void sar_ar2(tms32025_state *cpustate)   { PUTDATA(cpustate, cpustate->AR[2]); }
1331		static void sar_ar3(tms32025_state *cpustate)   { PUTDATA(cpustate, cpustate->AR[3]); }
1332		static void sar_ar4(tms32025_state *cpustate)   { PUTDATA(cpustate, cpustate->AR[4]); }
1333		static void sar_ar5(tms32025_state *cpustate)   { PUTDATA(cpustate, cpustate->AR[5]); }
1334		static void sar_ar6(tms32025_state *cpustate)   { PUTDATA(cpustate, cpustate->AR[6]); }
1335		static void sar_ar7(tms32025_state *cpustate)   { PUTDATA(cpustate, cpustate->AR[7]); }
	1289	void tms32025_device::sar_ar0()   { PUTDATA(m_AR[0]); }
	1290	void tms32025_device::sar_ar1()   { PUTDATA(m_AR[1]); }
	1291	void tms32025_device::sar_ar2()   { PUTDATA(m_AR[2]); }
	1292	void tms32025_device::sar_ar3()   { PUTDATA(m_AR[3]); }
	1293	void tms32025_device::sar_ar4()   { PUTDATA(m_AR[4]); }
	1294	void tms32025_device::sar_ar5()   { PUTDATA(m_AR[5]); }
	1295	void tms32025_device::sar_ar6()   { PUTDATA(m_AR[6]); }
	1296	void tms32025_device::sar_ar7()   { PUTDATA(m_AR[7]); }
1336	1297
1337		static void sblk(tms32025_state *cpustate)
	1298	void tms32025_device::sblk()
1338	1299	{
1339		cpustate->oldacc.d = cpustate->ACC.d;
1340		if (SXM) cpustate->ALU.d =  (INT16)M_RDOP_ARG(cpustate->PC);
1341		else     cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
1342		cpustate->PC++;
1343		cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
1344		cpustate->ACC.d -= cpustate->ALU.d;
1345		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1346		CALCULATE_SUB_CARRY(cpustate);
	1300	m_oldacc.d = m_ACC.d;
	1301	if (SXM) m_ALU.d =  (INT16)M_RDOP_ARG(m_PC);
	1302	else     m_ALU.d = (UINT16)M_RDOP_ARG(m_PC);
	1303	m_PC++;
	1304	m_ALU.d <<= (m_opcode.b.h & 0xf);
	1305	m_ACC.d -= m_ALU.d;
	1306	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1307	CALCULATE_SUB_CARRY();
1347	1308	}
1348		static void sbrk_ar(tms32025_state *cpustate)
	1309	void tms32025_device::sbrk_ar()
1349	1310	{
1350		cpustate->AR[ARP] -= cpustate->opcode.b.l;
	1311	m_AR[ARP] -= m_opcode.b.l;
1351	1312	}
1352		static void sc(tms32025_state *cpustate)
	1313	void tms32025_device::sc()
1353	1314	{
1354		SET1(cpustate, C_FLAG);
	1315	SET1(C_FLAG);
1355	1316	}
1356		static void sfl(tms32025_state *cpustate)
	1317	void tms32025_device::sfl()
1357	1318	{
1358		cpustate->ALU.d = cpustate->ACC.d;
1359		cpustate->ACC.d <<= 1;
1360		if (cpustate->ALU.d & 0x80000000) SET1(cpustate, C_FLAG);
1361		else CLR1(cpustate, C_FLAG);
	1319	m_ALU.d = m_ACC.d;
	1320	m_ACC.d <<= 1;
	1321	if (m_ALU.d & 0x80000000) SET1(C_FLAG);
	1322	else CLR1(C_FLAG);
1362	1323	}
1363		static void sfr(tms32025_state *cpustate)
	1324	void tms32025_device::sfr()
1364	1325	{
1365		cpustate->ALU.d = cpustate->ACC.d;
1366		cpustate->ACC.d >>= 1;
	1326	m_ALU.d = m_ACC.d;
	1327	m_ACC.d >>= 1;
1367	1328	if (SXM) {
1368		if (cpustate->ALU.d & 0x80000000) cpustate->ACC.d |= 0x80000000;
	1329	if (m_ALU.d & 0x80000000) m_ACC.d |= 0x80000000;
1369	1330	}
1370		if (cpustate->ALU.d & 1) SET1(cpustate, C_FLAG);
1371		else CLR1(cpustate, C_FLAG);
	1331	if (m_ALU.d & 1) SET1(C_FLAG);
	1332	else CLR1(C_FLAG);
1372	1333	}
1373		static void sfsm(tms32025_state *cpustate)  /** Serial port mode */
	1334	void tms32025_device::sfsm()  /** Serial port mode */
1374	1335	{
1375		SET1(cpustate, FSM_FLAG);
	1336	SET1(FSM_FLAG);
1376	1337	}
1377		static void shm(tms32025_state *cpustate)
	1338	void tms32025_device::shm()
1378	1339	{
1379		SET1(cpustate, HM_FLAG);
	1340	SET1(HM_FLAG);
1380	1341	}
1381		static void sovm(tms32025_state *cpustate)
	1342	void tms32025_device::sovm()
1382	1343	{
1383		SET0(cpustate, OVM_FLAG);
	1344	SET0(OVM_FLAG);
1384	1345	}
1385		static void spac(tms32025_state *cpustate)
	1346	void tms32025_device::spac()
1386	1347	{
1387		cpustate->oldacc.d = cpustate->ACC.d;
1388		SHIFT_Preg_TO_ALU(cpustate);
1389		cpustate->ACC.d -= cpustate->ALU.d;
1390		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1391		CALCULATE_SUB_CARRY(cpustate);
	1348	m_oldacc.d = m_ACC.d;
	1349	SHIFT_Preg_TO_ALU();
	1350	m_ACC.d -= m_ALU.d;
	1351	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1352	CALCULATE_SUB_CARRY();
1392	1353	}
1393		static void sph(tms32025_state *cpustate)
	1354	void tms32025_device::sph()
1394	1355	{
1395		SHIFT_Preg_TO_ALU(cpustate);
1396		PUTDATA(cpustate, cpustate->ALU.w.h);
	1356	SHIFT_Preg_TO_ALU();
	1357	PUTDATA(m_ALU.w.h);
1397	1358	}
1398		static void spl(tms32025_state *cpustate)
	1359	void tms32025_device::spl()
1399	1360	{
1400		SHIFT_Preg_TO_ALU(cpustate);
1401		PUTDATA(cpustate, cpustate->ALU.w.l);
	1361	SHIFT_Preg_TO_ALU();
	1362	PUTDATA(m_ALU.w.l);
1402	1363	}
1403		static void spm(tms32025_state *cpustate)
	1364	void tms32025_device::spm()
1404	1365	{
1405		MODIFY_PM(cpustate, (cpustate->opcode.b.l & 3) );
	1366	MODIFY_PM((m_opcode.b.l & 3) );
1406	1367	}
1407		static void sqra(tms32025_state *cpustate)
	1368	void tms32025_device::sqra()
1408	1369	{
1409		cpustate->oldacc.d = cpustate->ACC.d;
1410		SHIFT_Preg_TO_ALU(cpustate);
1411		cpustate->ACC.d += cpustate->ALU.d;
1412		CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1413		CALCULATE_ADD_CARRY(cpustate);
1414		GETDATA(cpustate, 0, 0);
1415		cpustate->Treg = cpustate->ALU.w.l;
1416		cpustate->Preg.d = ((INT16)cpustate->ALU.w.l * (INT16)cpustate->ALU.w.l);
	1370	m_oldacc.d = m_ACC.d;
	1371	SHIFT_Preg_TO_ALU();
	1372	m_ACC.d += m_ALU.d;
	1373	CALCULATE_ADD_OVERFLOW(m_ALU.d);
	1374	CALCULATE_ADD_CARRY();
	1375	GETDATA(0, 0);
	1376	m_Treg = m_ALU.w.l;
	1377	m_Preg.d = ((INT16)m_ALU.w.l * (INT16)m_ALU.w.l);
1417	1378	}
1418		static void sqrs(tms32025_state *cpustate)
	1379	void tms32025_device::sqrs()
1419	1380	{
1420		cpustate->oldacc.d = cpustate->ACC.d;
1421		SHIFT_Preg_TO_ALU(cpustate);
1422		cpustate->ACC.d -= cpustate->ALU.d;
1423		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1424		CALCULATE_SUB_CARRY(cpustate);
1425		GETDATA(cpustate, 0, 0);
1426		cpustate->Treg = cpustate->ALU.w.l;
1427		cpustate->Preg.d = ((INT16)cpustate->ALU.w.l * (INT16)cpustate->ALU.w.l);
	1381	m_oldacc.d = m_ACC.d;
	1382	SHIFT_Preg_TO_ALU();
	1383	m_ACC.d -= m_ALU.d;
	1384	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1385	CALCULATE_SUB_CARRY();
	1386	GETDATA(0, 0);
	1387	m_Treg = m_ALU.w.l;
	1388	m_Preg.d = ((INT16)m_ALU.w.l * (INT16)m_ALU.w.l);
1428	1389	}
1429		static void sst(tms32025_state *cpustate)
	1390	void tms32025_device::sst()
1430	1391	{
1431		PUTDATA_SST(cpustate, cpustate->STR0);
	1392	PUTDATA_SST(m_STR0);
1432	1393	}
1433		static void sst1(tms32025_state *cpustate)
	1394	void tms32025_device::sst1()
1434	1395	{
1435		PUTDATA_SST(cpustate, cpustate->STR1);
	1396	PUTDATA_SST(m_STR1);
1436	1397	}
1437		static void ssxm(tms32025_state *cpustate)
	1398	void tms32025_device::ssxm()
1438	1399	{
1439		SET1(cpustate, SXM_FLAG);
	1400	SET1(SXM_FLAG);
1440	1401	}
1441		static void stc(tms32025_state *cpustate)
	1402	void tms32025_device::stc()
1442	1403	{
1443		SET1(cpustate, TC_FLAG);
	1404	SET1(TC_FLAG);
1444	1405	}
1445		static void stxm(tms32025_state *cpustate)      /** Serial port stuff */
	1406	void tms32025_device::stxm()      /** Serial port stuff */
1446	1407	{
1447		SET1(cpustate, TXM_FLAG);
	1408	SET1(TXM_FLAG);
1448	1409	}
1449		static void sub(tms32025_state *cpustate)
	1410	void tms32025_device::sub()
1450	1411	{
1451		cpustate->oldacc.d = cpustate->ACC.d;
1452		GETDATA(cpustate, (cpustate->opcode.b.h & 0xf), SXM);
1453		cpustate->ACC.d -= cpustate->ALU.d;
1454		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1455		CALCULATE_SUB_CARRY(cpustate);
	1412	m_oldacc.d = m_ACC.d;
	1413	GETDATA((m_opcode.b.h & 0xf), SXM);
	1414	m_ACC.d -= m_ALU.d;
	1415	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1416	CALCULATE_SUB_CARRY();
1456	1417	}
1457		static void subb(tms32025_state *cpustate)
	1418	void tms32025_device::subb()
1458	1419	{
1459		cpustate->oldacc.d = cpustate->ACC.d;
1460		GETDATA(cpustate, 0, 0);
1461		if (CARRY == 0) cpustate->ACC.d--;
1462		cpustate->ACC.d -= cpustate->ALU.d;
1463		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1464		if (cpustate->ACC.d == cpustate->oldacc.d) {}   /* edge case, carry remains same */
1465		else CALCULATE_SUB_CARRY(cpustate);
	1420	m_oldacc.d = m_ACC.d;
	1421	GETDATA(0, 0);
	1422	if (CARRY == 0) m_ACC.d--;
	1423	m_ACC.d -= m_ALU.d;
	1424	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1425	if (m_ACC.d == m_oldacc.d) {}   /* edge case, carry remains same */
	1426	else CALCULATE_SUB_CARRY();
1466	1427	}
1467		static void subc(tms32025_state *cpustate)
	1428	void tms32025_device::subc()
1468	1429	{
1469		cpustate->oldacc.d = cpustate->ACC.d;
1470		GETDATA(cpustate, 15, SXM);
1471		cpustate->ACC.d -= cpustate->ALU.d;     /* Temporary switch to ACC. Actual calculation is done as (ACC)-[mem] -> ALU, will be preserved later on. */
1472		if ((INT32)((cpustate->oldacc.d ^ cpustate->ALU.d) & (cpustate->oldacc.d ^ cpustate->ACC.d)) < 0) {
1473		SET0(cpustate, OV_FLAG);            /* Not affected by OVM */
	1430	m_oldacc.d = m_ACC.d;
	1431	GETDATA(15, SXM);
	1432	m_ACC.d -= m_ALU.d;     /* Temporary switch to ACC. Actual calculation is done as (ACC)-[mem] -> ALU, will be preserved later on. */
	1433	if ((INT32)((m_oldacc.d ^ m_ALU.d) & (m_oldacc.d ^ m_ACC.d)) < 0) {
	1434	SET0(OV_FLAG);            /* Not affected by OVM */
1474	1435	}
1475		CALCULATE_SUB_CARRY(cpustate);
1476		if( cpustate->oldacc.d >= cpustate->ALU.d ) {
1477		cpustate->ALU.d = cpustate->ACC.d;
1478		cpustate->ACC.d = cpustate->ACC.d << 1 | 1;
	1436	CALCULATE_SUB_CARRY();
	1437	if( m_oldacc.d >= m_ALU.d ) {
	1438	m_ALU.d = m_ACC.d;
	1439	m_ACC.d = m_ACC.d << 1 | 1;
1479	1440	}
1480	1441	else {
1481		cpustate->ALU.d = cpustate->ACC.d;
1482		cpustate->ACC.d = cpustate->oldacc.d << 1;
	1442	m_ALU.d = m_ACC.d;
	1443	m_ACC.d = m_oldacc.d << 1;
1483	1444	}
1484	1445	}
1485		static void subh(tms32025_state *cpustate)
	1446	void tms32025_device::subh()
1486	1447	{
1487		cpustate->oldacc.d = cpustate->ACC.d;
1488		GETDATA(cpustate, 0, 0);
1489		cpustate->ACC.w.h -= cpustate->ALU.w.l;
1490		if ( (UINT16)(cpustate->oldacc.w.h) < (UINT16)(cpustate->ACC.w.h) ) {
1491		CLR1(cpustate, C_FLAG); /* Carry flag is not affected, if no borrow occurred */
	1448	m_oldacc.d = m_ACC.d;
	1449	GETDATA(0, 0);
	1450	m_ACC.w.h -= m_ALU.w.l;
	1451	if ( (UINT16)(m_oldacc.w.h) < (UINT16)(m_ACC.w.h) ) {
	1452	CLR1(C_FLAG); /* Carry flag is not affected, if no borrow occurred */
1492	1453	}
1493		if ((INT16)((cpustate->oldacc.w.h ^ cpustate->ALU.w.l) & (cpustate->oldacc.w.h ^ cpustate->ACC.w.h)) < 0) {
1494		SET0(cpustate, OV_FLAG);
1495		if (OVM) cpustate->ACC.w.h = ((INT16)cpustate->oldacc.w.h < 0) ? 0x8000 : 0x7fff;
	1454	if ((INT16)((m_oldacc.w.h ^ m_ALU.w.l) & (m_oldacc.w.h ^ m_ACC.w.h)) < 0) {
	1455	SET0(OV_FLAG);
	1456	if (OVM) m_ACC.w.h = ((INT16)m_oldacc.w.h < 0) ? 0x8000 : 0x7fff;
1496	1457	}
1497	1458	}
1498		static void subk(tms32025_state *cpustate)
	1459	void tms32025_device::subk()
1499	1460	{
1500		cpustate->oldacc.d = cpustate->ACC.d;
1501		cpustate->ALU.d = (UINT8)cpustate->opcode.b.l;
1502		cpustate->ACC.d -= cpustate->ALU.b.l;
1503		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1504		CALCULATE_SUB_CARRY(cpustate);
	1461	m_oldacc.d = m_ACC.d;
	1462	m_ALU.d = (UINT8)m_opcode.b.l;
	1463	m_ACC.d -= m_ALU.b.l;
	1464	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1465	CALCULATE_SUB_CARRY();
1505	1466	}
1506		static void subs(tms32025_state *cpustate)
	1467	void tms32025_device::subs()
1507	1468	{
1508		cpustate->oldacc.d = cpustate->ACC.d;
1509		GETDATA(cpustate, 0, 0);
1510		cpustate->ACC.d -= cpustate->ALU.w.l;
1511		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1512		CALCULATE_SUB_CARRY(cpustate);
	1469	m_oldacc.d = m_ACC.d;
	1470	GETDATA(0, 0);
	1471	m_ACC.d -= m_ALU.w.l;
	1472	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1473	CALCULATE_SUB_CARRY();
1513	1474	}
1514		static void subt(tms32025_state *cpustate)
	1475	void tms32025_device::subt()
1515	1476	{
1516		cpustate->oldacc.d = cpustate->ACC.d;
1517		GETDATA(cpustate, (cpustate->Treg & 0xf), SXM);
1518		cpustate->ACC.d -= cpustate->ALU.d;
1519		CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1520		CALCULATE_SUB_CARRY(cpustate);
	1477	m_oldacc.d = m_ACC.d;
	1478	GETDATA((m_Treg & 0xf), SXM);
	1479	m_ACC.d -= m_ALU.d;
	1480	CALCULATE_SUB_OVERFLOW(m_ALU.d);
	1481	CALCULATE_SUB_CARRY();
1521	1482	}
1522		static void sxf(tms32025_state *cpustate)
	1483	void tms32025_device::sxf()
1523	1484	{
1524		SET1(cpustate, XF_FLAG);
	1485	SET1(XF_FLAG);
1525	1486	S_OUT(TMS32025_XF,ASSERT_LINE);
1526	1487	}
1527		static void tblr(tms32025_state *cpustate)
	1488	void tms32025_device::tblr()
1528	1489	{
1529		if (cpustate->init_load_addr) {
1530		cpustate->PFC = cpustate->ACC.w.l;
	1490	if (m_init_load_addr) {
	1491	m_PFC = m_ACC.w.l;
1531	1492	}
1532		cpustate->ALU.w.l = M_RDROM(cpustate, cpustate->PFC);
1533		if ( (CNF0) && ( (UINT16)(cpustate->PFC) >= 0xff00 ) ) {}   /** TMS32025 only */
1534		else cpustate->tms32025_dec_cycles += (1*CLK);
1535		PUTDATA(cpustate, cpustate->ALU.w.l);
1536		cpustate->PFC++;
	1493	m_ALU.w.l = M_RDROM(m_PFC);
	1494	if ( (CNF0) && ( (UINT16)(m_PFC) >= 0xff00 ) ) {}   /** TMS32025 only */
	1495	else m_tms32025_dec_cycles += (1*CLK);
	1496	PUTDATA(m_ALU.w.l);
	1497	m_PFC++;
1537	1498	}
1538		static void tblw(tms32025_state *cpustate)
	1499	void tms32025_device::tblw()
1539	1500	{
1540		if (cpustate->init_load_addr) {
1541		cpustate->PFC = cpustate->ACC.w.l;
	1501	if (m_init_load_addr) {
	1502	m_PFC = m_ACC.w.l;
1542	1503	}
1543		cpustate->tms32025_dec_cycles += (1*CLK);
1544		GETDATA(cpustate, 0, 0);
1545		if (cpustate->external_mem_access) cpustate->tms32025_dec_cycles += (1*CLK);
1546		M_WRTROM(cpustate, cpustate->PFC, cpustate->ALU.w.l);
1547		cpustate->PFC++;
	1504	m_tms32025_dec_cycles += (1*CLK);
	1505	GETDATA(0, 0);
	1506	if (m_external_mem_access) m_tms32025_dec_cycles += (1*CLK);
	1507	M_WRTROM(m_PFC, m_ALU.w.l);
	1508	m_PFC++;
1548	1509	}
1549		static void trap(tms32025_state *cpustate)
	1510	void tms32025_device::trap()
1550	1511	{
1551		PUSH_STACK(cpustate, cpustate->PC);
	1512	PUSH_STACK(m_PC);
1552	1513	SET_PC(0x001E);     /* Trap vector */
1553	1514	}
1554		static void xor_(tms32025_state *cpustate)
	1515	void tms32025_device::xor_()
1555	1516	{
1556		GETDATA(cpustate, 0, 0);
1557		cpustate->ACC.w.l ^= cpustate->ALU.w.l;
	1517	GETDATA(0, 0);
	1518	m_ACC.w.l ^= m_ALU.w.l;
1558	1519	}
1559		static void xork(tms32025_state *cpustate)
	1520	void tms32025_device::xork()
1560	1521	{
1561		cpustate->ALU.d = M_RDOP_ARG(cpustate->PC);
1562		cpustate->PC++;
1563		cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
1564		cpustate->ACC.d ^= cpustate->ALU.d;
	1522	m_ALU.d = M_RDOP_ARG(m_PC);
	1523	m_PC++;
	1524	m_ALU.d <<= (m_opcode.b.h & 0xf);
	1525	m_ACC.d ^= m_ALU.d;
1565	1526	}
1566		static void zalh(tms32025_state *cpustate)
	1527	void tms32025_device::zalh()
1567	1528	{
1568		GETDATA(cpustate, 0, 0);
1569		cpustate->ACC.w.h = cpustate->ALU.w.l;
1570		cpustate->ACC.w.l = 0x0000;
	1529	GETDATA(0, 0);
	1530	m_ACC.w.h = m_ALU.w.l;
	1531	m_ACC.w.l = 0x0000;
1571	1532	}
1572		static void zalr(tms32025_state *cpustate)
	1533	void tms32025_device::zalr()
1573	1534	{
1574		GETDATA(cpustate, 0, 0);
1575		cpustate->ACC.w.h = cpustate->ALU.w.l;
1576		cpustate->ACC.w.l = 0x8000;
	1535	GETDATA(0, 0);
	1536	m_ACC.w.h = m_ALU.w.l;
	1537	m_ACC.w.l = 0x8000;
1577	1538	}
1578		static void zals(tms32025_state *cpustate)
	1539	void tms32025_device::zals()
1579	1540	{
1580		GETDATA(cpustate, 0, 0);
1581		cpustate->ACC.w.l = cpustate->ALU.w.l;
1582		cpustate->ACC.w.h = 0x0000;
	1541	GETDATA(0, 0);
	1542	m_ACC.w.l = m_ALU.w.l;
	1543	m_ACC.w.h = 0x0000;
1583	1544	}
1584	1545
1585	1546
r26837	r26838
1587	1548	*  Opcode Table (Cycles, Instruction)
1588	1549	***********************************************************************/
1589	1550
1590		static const tms32025_opcode opcode_main[256]=
	1551	const tms32025_device::tms32025_opcode tms32025_device::s_opcode_main[256]=
1591	1552	{
1592		/*00*/ {1*CLK, add      },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },
1593		/*08*/ {1*CLK, add      },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },{1*CLK, add       },
1594		/*10*/ {1*CLK, sub      },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },
1595		/*18*/ {1*CLK, sub      },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },{1*CLK, sub       },
1596		/*20*/ {1*CLK, lac      },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },
1597		/*28*/ {1*CLK, lac      },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },{1*CLK, lac       },
1598		/*30*/ {1*CLK, lar_ar0  },{1*CLK, lar_ar1   },{1*CLK, lar_ar2   },{1*CLK, lar_ar3   },{1*CLK, lar_ar4   },{1*CLK, lar_ar5   },{1*CLK, lar_ar6   },{1*CLK, lar_ar7   },
1599		/*38*/ {1*CLK, mpy      },{1*CLK, sqra      },{1*CLK, mpya      },{1*CLK, mpys      },{1*CLK, lt        },{1*CLK, lta       },{1*CLK, ltp       },{1*CLK, ltd       },
1600		/*40*/ {1*CLK, zalh     },{1*CLK, zals      },{1*CLK, lact      },{1*CLK, addc      },{1*CLK, subh      },{1*CLK, subs      },{1*CLK, subt      },{1*CLK, subc      },
1601		/*48*/ {1*CLK, addh     },{1*CLK, adds      },{1*CLK, addt      },{1*CLK, rpt       },{1*CLK, xor_      },{1*CLK, or_       },{1*CLK, and_      },{1*CLK, subb      },
1602		/*50*/ {1*CLK, lst      },{1*CLK, lst1      },{1*CLK, ldp       },{1*CLK, lph       },{1*CLK, pshd      },{1*CLK, mar       },{1*CLK, dmov      },{1*CLK, bitt      },
1603		/*58*/ {3*CLK, tblr     },{2*CLK, tblw      },{1*CLK, sqrs      },{1*CLK, lts       },{2*CLK, macd      },{2*CLK, mac       },{2*CLK, bc        },{2*CLK, bnc       },
1604		/*60*/ {1*CLK, sacl     },{1*CLK, sacl      },{1*CLK, sacl      },{1*CLK, sacl      },{1*CLK, sacl      },{1*CLK, sacl      },{1*CLK, sacl      },{1*CLK, sacl      },
1605		/*68*/ {1*CLK, sach     },{1*CLK, sach      },{1*CLK, sach      },{1*CLK, sach      },{1*CLK, sach      },{1*CLK, sach      },{1*CLK, sach      },{1*CLK, sach      },
1606		/*70*/ {1*CLK, sar_ar0  },{1*CLK, sar_ar1   },{1*CLK, sar_ar2   },{1*CLK, sar_ar3   },{1*CLK, sar_ar4   },{1*CLK, sar_ar5   },{1*CLK, sar_ar6   },{1*CLK, sar_ar7   },
1607		/*78*/ {1*CLK, sst      },{1*CLK, sst1      },{1*CLK, popd      },{1*CLK, zalr      },{1*CLK, spl       },{1*CLK, sph       },{1*CLK, adrk      },{1*CLK, sbrk_ar   },
1608		/*80*/ {2*CLK, in       },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },
1609		/*88*/ {2*CLK, in       },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },{2*CLK, in        },
1610		/*90*/ {1*CLK, bit      },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },
1611		/*98*/ {1*CLK, bit      },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },{1*CLK, bit       },
1612		/*A0*/ {1*CLK, mpyk     },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },
1613		/*A8*/ {1*CLK, mpyk     },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },
1614		/*B0*/ {1*CLK, mpyk     },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },
1615		/*B8*/ {1*CLK, mpyk     },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },{1*CLK, mpyk      },
1616		/*C0*/ {1*CLK, lark_ar0 },{1*CLK, lark_ar1  },{1*CLK, lark_ar2  },{1*CLK, lark_ar3  },{1*CLK, lark_ar4  },{1*CLK, lark_ar5  },{1*CLK, lark_ar6  },{1*CLK, lark_ar7  },
1617		/*C8*/ {1*CLK, ldpk     },{1*CLK, ldpk      },{1*CLK, lack      },{1*CLK, rptk      },{1*CLK, addk      },{1*CLK, subk      },{1*CLK, opcodes_CE},{1*CLK, mpyu      },
1618		/*D0*/ {1*CLK,opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{0*CLK, opcodes_Dx},
1619		/*D8*/ {1*CLK,opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},
1620		/*E0*/ {2*CLK, out      },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },
1621		/*E8*/ {2*CLK, out      },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },{2*CLK, out       },
1622		/*F0*/ {2*CLK, bv       },{2*CLK, bgz       },{2*CLK, blez      },{2*CLK, blz       },{2*CLK, bgez      },{2*CLK, bnz       },{2*CLK, bz        },{2*CLK, bnv       },
1623		/*F8*/ {2*CLK, bbz      },{2*CLK, bbnz      },{2*CLK, bioz      },{2*CLK, banz      },{2*CLK, blkp      },{2*CLK, blkd      },{2*CLK, call      },{2*CLK, br        }
	1553	/*00*/ {1*CLK, &tms32025_device::add      },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },
	1554	/*08*/ {1*CLK, &tms32025_device::add      },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },{1*CLK, &tms32025_device::add       },
	1555	/*10*/ {1*CLK, &tms32025_device::sub      },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },
	1556	/*18*/ {1*CLK, &tms32025_device::sub      },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },{1*CLK, &tms32025_device::sub       },
	1557	/*20*/ {1*CLK, &tms32025_device::lac      },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },
	1558	/*28*/ {1*CLK, &tms32025_device::lac      },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },{1*CLK, &tms32025_device::lac       },
	1559	/*30*/ {1*CLK, &tms32025_device::lar_ar0  },{1*CLK, &tms32025_device::lar_ar1   },{1*CLK, &tms32025_device::lar_ar2   },{1*CLK, &tms32025_device::lar_ar3   },{1*CLK, &tms32025_device::lar_ar4   },{1*CLK, &tms32025_device::lar_ar5   },{1*CLK, &tms32025_device::lar_ar6   },{1*CLK, &tms32025_device::lar_ar7   },
	1560	/*38*/ {1*CLK, &tms32025_device::mpy      },{1*CLK, &tms32025_device::sqra      },{1*CLK, &tms32025_device::mpya      },{1*CLK, &tms32025_device::mpys      },{1*CLK, &tms32025_device::lt        },{1*CLK, &tms32025_device::lta       },{1*CLK, &tms32025_device::ltp       },{1*CLK, &tms32025_device::ltd       },
	1561	/*40*/ {1*CLK, &tms32025_device::zalh     },{1*CLK, &tms32025_device::zals      },{1*CLK, &tms32025_device::lact      },{1*CLK, &tms32025_device::addc      },{1*CLK, &tms32025_device::subh      },{1*CLK, &tms32025_device::subs      },{1*CLK, &tms32025_device::subt      },{1*CLK, &tms32025_device::subc      },
	1562	/*48*/ {1*CLK, &tms32025_device::addh     },{1*CLK, &tms32025_device::adds      },{1*CLK, &tms32025_device::addt      },{1*CLK, &tms32025_device::rpt       },{1*CLK, &tms32025_device::xor_      },{1*CLK, &tms32025_device::or_       },{1*CLK, &tms32025_device::and_      },{1*CLK, &tms32025_device::subb      },
	1563	/*50*/ {1*CLK, &tms32025_device::lst      },{1*CLK, &tms32025_device::lst1      },{1*CLK, &tms32025_device::ldp       },{1*CLK, &tms32025_device::lph       },{1*CLK, &tms32025_device::pshd      },{1*CLK, &tms32025_device::mar       },{1*CLK, &tms32025_device::dmov      },{1*CLK, &tms32025_device::bitt      },
	1564	/*58*/ {3*CLK, &tms32025_device::tblr     },{2*CLK, &tms32025_device::tblw      },{1*CLK, &tms32025_device::sqrs      },{1*CLK, &tms32025_device::lts       },{2*CLK, &tms32025_device::macd      },{2*CLK, &tms32025_device::mac       },{2*CLK, &tms32025_device::bc        },{2*CLK, &tms32025_device::bnc       },
	1565	/*60*/ {1*CLK, &tms32025_device::sacl     },{1*CLK, &tms32025_device::sacl      },{1*CLK, &tms32025_device::sacl      },{1*CLK, &tms32025_device::sacl      },{1*CLK, &tms32025_device::sacl      },{1*CLK, &tms32025_device::sacl      },{1*CLK, &tms32025_device::sacl      },{1*CLK, &tms32025_device::sacl      },
	1566	/*68*/ {1*CLK, &tms32025_device::sach     },{1*CLK, &tms32025_device::sach      },{1*CLK, &tms32025_device::sach      },{1*CLK, &tms32025_device::sach      },{1*CLK, &tms32025_device::sach      },{1*CLK, &tms32025_device::sach      },{1*CLK, &tms32025_device::sach      },{1*CLK, &tms32025_device::sach      },
	1567	/*70*/ {1*CLK, &tms32025_device::sar_ar0  },{1*CLK, &tms32025_device::sar_ar1   },{1*CLK, &tms32025_device::sar_ar2   },{1*CLK, &tms32025_device::sar_ar3   },{1*CLK, &tms32025_device::sar_ar4   },{1*CLK, &tms32025_device::sar_ar5   },{1*CLK, &tms32025_device::sar_ar6   },{1*CLK, &tms32025_device::sar_ar7   },
	1568	/*78*/ {1*CLK, &tms32025_device::sst      },{1*CLK, &tms32025_device::sst1      },{1*CLK, &tms32025_device::popd      },{1*CLK, &tms32025_device::zalr      },{1*CLK, &tms32025_device::spl       },{1*CLK, &tms32025_device::sph       },{1*CLK, &tms32025_device::adrk      },{1*CLK, &tms32025_device::sbrk_ar   },
	1569	/*80*/ {2*CLK, &tms32025_device::in       },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },
	1570	/*88*/ {2*CLK, &tms32025_device::in       },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },{2*CLK, &tms32025_device::in        },
	1571	/*90*/ {1*CLK, &tms32025_device::bit      },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },
	1572	/*98*/ {1*CLK, &tms32025_device::bit      },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },{1*CLK, &tms32025_device::bit       },
	1573	/*A0*/ {1*CLK, &tms32025_device::mpyk     },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },
	1574	/*A8*/ {1*CLK, &tms32025_device::mpyk     },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },
	1575	/*B0*/ {1*CLK, &tms32025_device::mpyk     },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },
	1576	/*B8*/ {1*CLK, &tms32025_device::mpyk     },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },{1*CLK, &tms32025_device::mpyk      },
	1577	/*C0*/ {1*CLK, &tms32025_device::lark_ar0 },{1*CLK, &tms32025_device::lark_ar1  },{1*CLK, &tms32025_device::lark_ar2  },{1*CLK, &tms32025_device::lark_ar3  },{1*CLK, &tms32025_device::lark_ar4  },{1*CLK, &tms32025_device::lark_ar5  },{1*CLK, &tms32025_device::lark_ar6  },{1*CLK, &tms32025_device::lark_ar7  },
	1578	/*C8*/ {1*CLK, &tms32025_device::ldpk     },{1*CLK, &tms32025_device::ldpk      },{1*CLK, &tms32025_device::lack      },{1*CLK, &tms32025_device::rptk      },{1*CLK, &tms32025_device::addk      },{1*CLK, &tms32025_device::subk      },{1*CLK, &tms32025_device::opcodes_CE},{1*CLK, &tms32025_device::mpyu      },
	1579	/*D0*/ {1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{0*CLK, &tms32025_device::opcodes_Dx},
	1580	/*D8*/ {1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},
	1581	/*E0*/ {2*CLK, &tms32025_device::out      },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },
	1582	/*E8*/ {2*CLK, &tms32025_device::out      },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },{2*CLK, &tms32025_device::out       },
	1583	/*F0*/ {2*CLK, &tms32025_device::bv       },{2*CLK, &tms32025_device::bgz       },{2*CLK, &tms32025_device::blez      },{2*CLK, &tms32025_device::blz       },{2*CLK, &tms32025_device::bgez      },{2*CLK, &tms32025_device::bnz       },{2*CLK, &tms32025_device::bz        },{2*CLK, &tms32025_device::bnv       },
	1584	/*F8*/ {2*CLK, &tms32025_device::bbz      },{2*CLK, &tms32025_device::bbnz      },{2*CLK, &tms32025_device::bioz      },{2*CLK, &tms32025_device::banz      },{2*CLK, &tms32025_device::blkp      },{2*CLK, &tms32025_device::blkd      },{2*CLK, &tms32025_device::call      },{2*CLK, &tms32025_device::br        }
1624	1585	};
1625	1586
1626		static const tms32025_opcode_CE opcode_CE_subset[256]=  /* Instructions living under the CExx opcode */
	1587	const tms32025_device::tms32025_opcode tms32025_device::s_opcode_CE_subset[256]=  /* Instructions living under the CExx opcode */
1627	1588	{
1628		/*00*/ {1*CLK, eint     },{1*CLK, dint      },{1*CLK, rovm      },{1*CLK, sovm      },{1*CLK, cnfd      },{1*CLK, cnfp      },{1*CLK, rsxm      },{1*CLK, ssxm      },
1629		/*08*/ {1*CLK, spm      },{1*CLK, spm       },{1*CLK, spm       },{1*CLK, spm       },{1*CLK, rxf       },{1*CLK, sxf       },{1*CLK, fort      },{1*CLK, fort      },
1630		/*10*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{1*CLK, pac       },{1*CLK, apac      },{1*CLK, spac      },{0*CLK, illegal   },
1631		/*18*/ {1*CLK, sfl      },{1*CLK, sfr       },{0*CLK, illegal   },{1*CLK, abst      },{1*CLK, push      },{1*CLK, pop       },{2*CLK, trap      },{3*CLK, idle      },
1632		/*20*/ {1*CLK, rtxm     },{1*CLK, stxm      },{0*CLK, illegal   },{1*CLK, neg       },{2*CLK, cala      },{2*CLK, bacc      },{2*CLK, ret       },{1*CLK, cmpl      },
1633		/*28*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1634		/*30*/ {1*CLK, rc       },{1*CLK, sc        },{1*CLK, rtc       },{1*CLK, stc       },{1*CLK, rol       },{1*CLK, ror       },{1*CLK, rfsm      },{1*CLK, sfsm      },
1635		/*38*/ {1*CLK, rhm      },{1*CLK, shm       },{0*CLK, illegal   },{0*CLK, illegal   },{1*CLK, conf      },{1*CLK, conf      },{1*CLK, conf      },{1*CLK, conf      },
1636		/*40*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1637		/*48*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1638		/*50*/ {1*CLK, cmpr     },{1*CLK, cmpr      },{1*CLK, cmpr      },{1*CLK, cmpr      },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1639		/*58*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1640		/*60*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1641		/*68*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1642		/*70*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1643		/*78*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1644		/*80*/ {0*CLK, illegal  },{0*CLK, illegal   },{1*CLK, norm      },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1645		/*88*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1646		/*90*/ {0*CLK, illegal  },{0*CLK, illegal   },{1*CLK, norm      },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1647		/*98*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1648		/*A0*/ {0*CLK, illegal  },{0*CLK, illegal   },{1*CLK, norm      },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1649		/*A8*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1650		/*B0*/ {0*CLK, illegal  },{0*CLK, illegal   },{1*CLK, norm      },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1651		/*B8*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1652		/*C0*/ {0*CLK, illegal  },{0*CLK, illegal   },{1*CLK, norm      },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1653		/*C8*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1654		/*D0*/ {0*CLK, illegal  },{0*CLK, illegal   },{1*CLK, norm      },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1655		/*D8*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1656		/*E0*/ {0*CLK, illegal  },{0*CLK, illegal   },{1*CLK, norm      },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1657		/*E8*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1658		/*F0*/ {0*CLK, illegal  },{0*CLK, illegal   },{1*CLK, norm      },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },
1659		/*F8*/ {0*CLK, illegal  },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   },{0*CLK, illegal   }
	1589	/*00*/ {1*CLK, &tms32025_device::eint     },{1*CLK, &tms32025_device::dint      },{1*CLK, &tms32025_device::rovm      },{1*CLK, &tms32025_device::sovm      },{1*CLK, &tms32025_device::cnfd      },{1*CLK, &tms32025_device::cnfp      },{1*CLK, &tms32025_device::rsxm      },{1*CLK, &tms32025_device::ssxm      },
	1590	/*08*/ {1*CLK, &tms32025_device::spm      },{1*CLK, &tms32025_device::spm       },{1*CLK, &tms32025_device::spm       },{1*CLK, &tms32025_device::spm       },{1*CLK, &tms32025_device::rxf       },{1*CLK, &tms32025_device::sxf       },{1*CLK, &tms32025_device::fort      },{1*CLK, &tms32025_device::fort      },
	1591	/*10*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::pac       },{1*CLK, &tms32025_device::apac      },{1*CLK, &tms32025_device::spac      },{0*CLK, &tms32025_device::illegal   },
	1592	/*18*/ {1*CLK, &tms32025_device::sfl      },{1*CLK, &tms32025_device::sfr       },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::abst      },{1*CLK, &tms32025_device::push      },{1*CLK, &tms32025_device::pop       },{2*CLK, &tms32025_device::trap      },{3*CLK, &tms32025_device::idle      },
	1593	/*20*/ {1*CLK, &tms32025_device::rtxm     },{1*CLK, &tms32025_device::stxm      },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::neg       },{2*CLK, &tms32025_device::cala      },{2*CLK, &tms32025_device::bacc      },{2*CLK, &tms32025_device::ret       },{1*CLK, &tms32025_device::cmpl      },
	1594	/*28*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1595	/*30*/ {1*CLK, &tms32025_device::rc       },{1*CLK, &tms32025_device::sc        },{1*CLK, &tms32025_device::rtc       },{1*CLK, &tms32025_device::stc       },{1*CLK, &tms32025_device::rol       },{1*CLK, &tms32025_device::ror       },{1*CLK, &tms32025_device::rfsm      },{1*CLK, &tms32025_device::sfsm      },
	1596	/*38*/ {1*CLK, &tms32025_device::rhm      },{1*CLK, &tms32025_device::shm       },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::conf      },{1*CLK, &tms32025_device::conf      },{1*CLK, &tms32025_device::conf      },{1*CLK, &tms32025_device::conf      },
	1597	/*40*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1598	/*48*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1599	/*50*/ {1*CLK, &tms32025_device::cmpr     },{1*CLK, &tms32025_device::cmpr      },{1*CLK, &tms32025_device::cmpr      },{1*CLK, &tms32025_device::cmpr      },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1600	/*58*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1601	/*60*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1602	/*68*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1603	/*70*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1604	/*78*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1605	/*80*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::norm      },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1606	/*88*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1607	/*90*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::norm      },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1608	/*98*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1609	/*A0*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::norm      },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1610	/*A8*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1611	/*B0*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::norm      },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1612	/*B8*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1613	/*C0*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::norm      },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1614	/*C8*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1615	/*D0*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::norm      },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1616	/*D8*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1617	/*E0*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::norm      },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1618	/*E8*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1619	/*F0*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{1*CLK, &tms32025_device::norm      },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },
	1620	/*F8*/ {0*CLK, &tms32025_device::illegal  },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   },{0*CLK, &tms32025_device::illegal   }
1660	1621	};
1661	1622
1662		static const tms32025_opcode_Dx opcode_Dx_subset[8]=    /* Instructions living under the Dxxx opcode */
	1623	const tms32025_device::tms32025_opcode tms32025_device::s_opcode_Dx_subset[8]=    /* Instructions living under the Dxxx opcode */
1663	1624	{
1664		/*00*/ {2*CLK, lrlk     },{2*CLK, lalk      },{2*CLK, adlk      },{2*CLK, sblk      },{2*CLK, andk      },{2*CLK, ork       },{2*CLK, xork      },{0*CLK, illegal   }
	1625	/*00*/ {2*CLK, &tms32025_device::lrlk     },{2*CLK, &tms32025_device::lalk      },{2*CLK, &tms32025_device::adlk      },{2*CLK, &tms32025_device::sblk      },{2*CLK, &tms32025_device::andk      },{2*CLK, &tms32025_device::ork       },{2*CLK, &tms32025_device::xork      },{0*CLK, &tms32025_device::illegal   }
1665	1626	};
1666	1627
1667	1628
r26837	r26838
1669	1630	/****************************************************************************
1670	1631	*  Initialise the CPU emulation
1671	1632	****************************************************************************/
1672		static CPU_INIT( tms32025 )
	1633	void tms32025_device::device_start()
1673	1634	{
1674		tms32025_state *cpustate = get_safe_token(device);
	1635	m_program = &space(AS_PROGRAM);
	1636	m_direct = &m_program->direct();
	1637	m_data = &space(AS_DATA);
	1638	m_io = &space(AS_IO);
1675	1639
1676		cpustate->intRAM = auto_alloc_array(device->machine(), UINT16, 0x800);
1677		cpustate->irq_callback = irqcallback;
1678		cpustate->device = device;
1679		cpustate->program = &device->space(AS_PROGRAM);
1680		cpustate->direct = &cpustate->program->direct();
1681		cpustate->data = &device->space(AS_DATA);
1682		cpustate->io = &device->space(AS_IO);
	1640	m_PREVPC = 0;
	1641	m_PFC = 0;
	1642	m_STR0 = 0;
	1643	m_STR1 = 0;
	1644	m_ACC.d = 0;
	1645	m_Preg.d = 0;
	1646	m_Treg = 0;
	1647	m_AR[0] = m_AR[1] = m_AR[2] = m_AR[3] = m_AR[4] = m_AR[5] = m_AR[6] = m_AR[7] = 0;
	1648	m_STACK[0] = m_STACK[1] = m_STACK[2] = m_STACK[3] = m_STACK[4] = m_STACK[5] = m_STACK[6] = m_STACK[7] = 0;
	1649	m_ALU.d = 0;
	1650	memset(m_intRAM, 0, sizeof(m_intRAM));
	1651	m_timerover = 0;
	1652	m_opcode.d = 0;
	1653	m_external_mem_access = 0;
	1654	m_tms32025_irq_cycles = 0;
	1655	m_oldacc.d = 0;
	1656	m_memaccess = 0;
	1657	m_mHackIgnoreARP = 0;
	1658	m_waiting_for_serial_frame = 0;
1683	1659
1684		device->save_item(NAME(cpustate->PC));
1685		device->save_item(NAME(cpustate->STR0));
1686		device->save_item(NAME(cpustate->STR1));
1687		device->save_item(NAME(cpustate->PFC));
1688		device->save_item(NAME(cpustate->IFR));
1689		device->save_item(NAME(cpustate->RPTC));
1690		device->save_item(NAME(cpustate->ACC.d));
1691		device->save_item(NAME(cpustate->ALU.d));
1692		device->save_item(NAME(cpustate->Preg.d));
1693		device->save_item(NAME(cpustate->Treg));
1694		device->save_item(NAME(cpustate->AR[0]));
1695		device->save_item(NAME(cpustate->AR[1]));
1696		device->save_item(NAME(cpustate->AR[2]));
1697		device->save_item(NAME(cpustate->AR[3]));
1698		device->save_item(NAME(cpustate->AR[4]));
1699		device->save_item(NAME(cpustate->AR[5]));
1700		device->save_item(NAME(cpustate->AR[6]));
1701		device->save_item(NAME(cpustate->AR[7]));
1702		device->save_item(NAME(cpustate->STACK[0]));
1703		device->save_item(NAME(cpustate->STACK[1]));
1704		device->save_item(NAME(cpustate->STACK[2]));
1705		device->save_item(NAME(cpustate->STACK[3]));
1706		device->save_item(NAME(cpustate->STACK[4]));
1707		device->save_item(NAME(cpustate->STACK[5]));
1708		device->save_item(NAME(cpustate->STACK[6]));
1709		device->save_item(NAME(cpustate->STACK[7]));
	1660	save_item(NAME(m_PC));
	1661	save_item(NAME(m_STR0));
	1662	save_item(NAME(m_STR1));
	1663	save_item(NAME(m_PFC));
	1664	save_item(NAME(m_IFR));
	1665	save_item(NAME(m_RPTC));
	1666	save_item(NAME(m_ACC.d));
	1667	save_item(NAME(m_ALU.d));
	1668	save_item(NAME(m_Preg.d));
	1669	save_item(NAME(m_Treg));
	1670	save_item(NAME(m_AR[0]));
	1671	save_item(NAME(m_AR[1]));
	1672	save_item(NAME(m_AR[2]));
	1673	save_item(NAME(m_AR[3]));
	1674	save_item(NAME(m_AR[4]));
	1675	save_item(NAME(m_AR[5]));
	1676	save_item(NAME(m_AR[6]));
	1677	save_item(NAME(m_AR[7]));
	1678	save_item(NAME(m_STACK[0]));
	1679	save_item(NAME(m_STACK[1]));
	1680	save_item(NAME(m_STACK[2]));
	1681	save_item(NAME(m_STACK[3]));
	1682	save_item(NAME(m_STACK[4]));
	1683	save_item(NAME(m_STACK[5]));
	1684	save_item(NAME(m_STACK[6]));
	1685	save_item(NAME(m_STACK[7]));
1710	1686
1711		device->save_item(NAME(cpustate->oldacc));
1712		device->save_item(NAME(cpustate->memaccess));
1713		device->save_item(NAME(cpustate->icount));
1714		device->save_item(NAME(cpustate->mHackIgnoreARP));
	1687	save_item(NAME(m_oldacc));
	1688	save_item(NAME(m_memaccess));
	1689	save_item(NAME(m_icount));
	1690	save_item(NAME(m_mHackIgnoreARP));
1715	1691
1716		device->save_item(NAME(cpustate->idle));
1717		device->save_item(NAME(cpustate->hold));
1718		device->save_item(NAME(cpustate->external_mem_access));
1719		device->save_item(NAME(cpustate->init_load_addr));
1720		device->save_item(NAME(cpustate->PREVPC));
	1692	save_item(NAME(m_idle));
	1693	save_item(NAME(m_hold));
	1694	save_item(NAME(m_external_mem_access));
	1695	save_item(NAME(m_init_load_addr));
	1696	save_item(NAME(m_PREVPC));
1721	1697
1722		//  device->save_pointer(NAME(cpustate->intRAM), 0x800*2);
	1698	save_item(NAME(m_intRAM));
	1699
	1700	state_add( TMS32025_PC,   "PC",   m_PC).formatstr("%04X");
	1701	state_add( TMS32025_STR0, "STR0", m_STR0).formatstr("%04X");
	1702	state_add( TMS32025_STR1, "STR1", m_STR1).formatstr("%04X");
	1703	state_add( TMS32025_IFR,  "IFR",  m_IFR).formatstr("%04X");
	1704	state_add( TMS32025_RPTC, "RPTC", m_RPTC).formatstr("%02X");
	1705	state_add( TMS32025_STK7, "STK7", m_STACK[7]).formatstr("%04X");
	1706	state_add( TMS32025_STK6, "STK6", m_STACK[6]).formatstr("%04X");
	1707	state_add( TMS32025_STK5, "STK5", m_STACK[5]).formatstr("%04X");
	1708	state_add( TMS32025_STK4, "STK4", m_STACK[4]).formatstr("%04X");
	1709	state_add( TMS32025_STK3, "STK3", m_STACK[3]).formatstr("%04X");
	1710	state_add( TMS32025_STK2, "STK2", m_STACK[2]).formatstr("%04X");
	1711	state_add( TMS32025_STK1, "STK1", m_STACK[1]).formatstr("%04X");
	1712	state_add( TMS32025_STK0, "STK0", m_STACK[0]).formatstr("%04X");
	1713	state_add( TMS32025_ACC,  "ACC",  m_ACC.d).formatstr("%08X");
	1714	state_add( TMS32025_PREG, "P",    m_Preg.d).formatstr("%08X");
	1715	state_add( TMS32025_TREG, "T",    m_Treg).formatstr("%04X");
	1716	state_add( TMS32025_AR0,  "AR0",  m_AR[0]).formatstr("%04X");
	1717	state_add( TMS32025_AR1,  "AR1",  m_AR[1]).formatstr("%04X");
	1718	state_add( TMS32025_AR2,  "AR2",  m_AR[2]).formatstr("%04X");
	1719	state_add( TMS32025_AR3,  "AR3",  m_AR[3]).formatstr("%04X");
	1720	state_add( TMS32025_AR4,  "AR4",  m_AR[4]).formatstr("%04X");
	1721	state_add( TMS32025_AR5,  "AR5",  m_AR[5]).formatstr("%04X");
	1722	state_add( TMS32025_AR6,  "AR6",  m_AR[6]).formatstr("%04X");
	1723	state_add( TMS32025_AR7,  "AR7",  m_AR[7]).formatstr("%04X");
	1724	state_add( TMS32025_DRR,  "DRR",  m_debugger_temp).callimport().callexport().formatstr("%04X");
	1725	state_add( TMS32025_DXR,  "DXR",  m_debugger_temp).callimport().callexport().formatstr("%04X");
	1726	state_add( TMS32025_TIM,  "TIM",  m_debugger_temp).callimport().callexport().formatstr("%04X");
	1727	state_add( TMS32025_PRD,  "PRD",  m_debugger_temp).callimport().callexport().formatstr("%04X");
	1728	state_add( TMS32025_IMR,  "IMR",  m_debugger_temp).callimport().callexport().formatstr("%04X");
	1729	state_add( TMS32025_GREG, "GREG", m_debugger_temp).callimport().callexport().formatstr("%04X");
	1730
	1731	state_add(STATE_GENPC, "GENPC", m_PC).formatstr("%04X").noshow();
	1732	/* This is actually not a stack pointer, but the stack contents */
	1733	state_add(STATE_GENSP, "GENSP", m_STACK[7]).formatstr("%04X").noshow();
	1734	state_add(STATE_GENFLAGS, "GENFLAGS",  m_STR0).formatstr("%33s").noshow();
	1735	state_add(STATE_GENPCBASE, "GENPCBASE", m_PREVPC).formatstr("%04X").noshow();
	1736
	1737	m_icountptr = &m_icount;
1723	1738	}
1724	1739
	1740
	1741	void tms32025_device::state_import(const device_state_entry &entry)
	1742	{
	1743	switch (entry.index())
	1744	{
	1745	case TMS32025_DRR:
	1746	M_WRTRAM(0, m_debugger_temp);
	1747	break;
	1748
	1749	case TMS32025_DXR:
	1750	M_WRTRAM(1, m_debugger_temp);
	1751	break;
	1752
	1753	case TMS32025_TIM:
	1754	M_WRTRAM(2, m_debugger_temp);
	1755	break;
	1756
	1757	case TMS32025_PRD:
	1758	M_WRTRAM(3, m_debugger_temp);
	1759	break;
	1760
	1761	case TMS32025_IMR:
	1762	M_WRTRAM(4,m_debugger_temp);
	1763	break;
	1764
	1765	case TMS32025_GREG:
	1766	M_WRTRAM(5, m_debugger_temp);
	1767	break;
	1768	}
	1769	}
	1770
	1771
	1772	void tms32025_device::state_export(const device_state_entry &entry)
	1773	{
	1774	switch (entry.index())
	1775	{
	1776	case TMS32025_DRR:
	1777	m_debugger_temp = M_RDRAM(0);
	1778	break;
	1779
	1780	case TMS32025_DXR:
	1781	m_debugger_temp = M_RDRAM(1);
	1782	break;
	1783
	1784	case TMS32025_TIM:
	1785	m_debugger_temp = M_RDRAM(2);
	1786	break;
	1787
	1788	case TMS32025_PRD:
	1789	m_debugger_temp = M_RDRAM(3);
	1790	break;
	1791
	1792	case TMS32025_IMR:
	1793	m_debugger_temp = M_RDRAM(4);
	1794	break;
	1795
	1796	case TMS32025_GREG:
	1797	m_debugger_temp = M_RDRAM(5);
	1798	break;
	1799	}
	1800	}
	1801
	1802
	1803	void tms32025_device::state_string_export(const device_state_entry &entry, astring &string)
	1804	{
	1805	switch (entry.index())
	1806	{
	1807	case STATE_GENFLAGS:
	1808	string.printf("arp%d%c%c%c%cdp%03x  arb%d%c%c%c%c%c%c%c%c%c%c%cpm%d",
	1809	(m_STR0 & 0xe000) >> 13,
	1810	m_STR0 & 0x1000 ? 'O':'.',
	1811	m_STR0 & 0x0800 ? 'M':'.',
	1812	m_STR0 & 0x0400 ? '.':'?',
	1813	m_STR0 & 0x0200 ? 'I':'.',
	1814	(m_STR0 & 0x01ff),
	1815
	1816	(m_STR1 & 0xe000) >> 13,
	1817	m_STR1 & 0x1000 ? 'P':'D',
	1818	m_STR1 & 0x0800 ? 'T':'.',
	1819	m_STR1 & 0x0400 ? 'S':'.',
	1820	m_STR1 & 0x0200 ? 'C':'?',
	1821	m_STR0 & 0x0100 ? '.':'?',
	1822	m_STR1 & 0x0080 ? '.':'?',
	1823	m_STR1 & 0x0040 ? 'H':'.',
	1824	m_STR1 & 0x0020 ? 'F':'.',
	1825	m_STR1 & 0x0010 ? 'X':'.',
	1826	m_STR1 & 0x0008 ? 'f':'.',
	1827	m_STR1 & 0x0004 ? 'o':'i',
	1828	(m_STR1 & 0x0003)
	1829	);
	1830	break;
	1831	}
	1832	}
	1833
	1834
1725	1835	/****************************************************************************
1726	1836	*  Reset registers to their initial values
1727	1837	****************************************************************************/
1728		static CPU_RESET( tms32025 )
	1838	void tms32025_device::device_reset()
1729	1839	{
1730		tms32025_state *cpustate = get_safe_token(device);
1731
1732	1840	SET_PC(0);                  /* Starting address on a reset */
1733		cpustate->STR0 |= 0x0600;   /* INTM and unused bit set to 1 */
1734		cpustate->STR0 &= 0xefff;   /* OV cleared to 0. Remaining bits undefined */
1735		cpustate->STR1 |= 0x07f0;   /* SXM, C, HM, FSM, XF and unused bits set to 1 */
1736		cpustate->STR1 &= 0xeff0;   /* CNF, FO, TXM, PM bits cleared to 0. Remaining bits undefined */
1737		cpustate->RPTC = 0;         /* Reset repeat counter to 0 */
1738		cpustate->IFR = 0;          /* IRQ pending flags */
	1841	m_STR0 |= 0x0600;   /* INTM and unused bit set to 1 */
	1842	m_STR0 &= 0xefff;   /* OV cleared to 0. Remaining bits undefined */
	1843	m_STR1 |= 0x07f0;   /* SXM, C, HM, FSM, XF and unused bits set to 1 */
	1844	m_STR1 &= 0xeff0;   /* CNF, FO, TXM, PM bits cleared to 0. Remaining bits undefined */
	1845	m_RPTC = 0;         /* Reset repeat counter to 0 */
	1846	m_IFR = 0;          /* IRQ pending flags */
1739	1847
1740	1848	S_OUT(TMS32025_XF,ASSERT_LINE); /* XF flag is high. Must set the pin */
1741	1849
r26837	r26838
1745	1853	PRD  = 0xffff;
1746	1854	IMR  = 0xffc0;
1747	1855
1748		cpustate->idle = 0;
1749		cpustate->hold = 0;
1750		cpustate->tms32025_dec_cycles = 0;
1751		cpustate->init_load_addr = 1;
	1856	m_idle = 0;
	1857	m_hold = 0;
	1858	m_tms32025_dec_cycles = 0;
	1859	m_init_load_addr = 1;
1752	1860
1753	1861	/* Reset the Data/Program address banks */
1754		memset(cpustate->pgmmap, 0, sizeof(cpustate->pgmmap));
1755		memset(cpustate->datamap, 0, sizeof(cpustate->datamap));
	1862	memset(m_pgmmap, 0, sizeof(m_pgmmap));
	1863	memset(m_datamap, 0, sizeof(m_datamap));
1756	1864
1757		cpustate->datamap[0] = &cpustate->intRAM[0x000];            /* B2 */
1758		cpustate->datamap[4] = &cpustate->intRAM[0x200];            /* B0 */
1759		cpustate->datamap[5] = &cpustate->intRAM[0x280];            /* B0 */
1760		cpustate->datamap[6] = &cpustate->intRAM[0x300];            /* B1 */
1761		cpustate->datamap[7] = &cpustate->intRAM[0x380];            /* B1 */
	1865	m_datamap[0] = &m_intRAM[0x000];            /* B2 */
	1866	m_datamap[4] = &m_intRAM[0x200];            /* B0 */
	1867	m_datamap[5] = &m_intRAM[0x280];            /* B0 */
	1868	m_datamap[6] = &m_intRAM[0x300];            /* B1 */
	1869	m_datamap[7] = &m_intRAM[0x380];            /* B1 */
1762	1870	}
1763	1871
1764		static CPU_RESET( tms32026 )
	1872	void tms32026_device::device_reset()
1765	1873	{
1766		tms32025_state *cpustate = get_safe_token(device);
	1874	tms32025_device::device_reset();
1767	1875
1768		CPU_RESET_CALL(tms32025);
1769
1770		/* Reset the Data/Program address banks */
1771		memset(cpustate->pgmmap, 0, sizeof(cpustate->pgmmap));
1772		memset(cpustate->datamap, 0, sizeof(cpustate->datamap));
1773
1774		cpustate->datamap[0] = &cpustate->intRAM[0x000];            /* B2 */
1775		cpustate->datamap[4] = &cpustate->intRAM[0x200];            /* B0 */
1776		cpustate->datamap[5] = &cpustate->intRAM[0x280];            /* B0 */
1777		cpustate->datamap[6] = &cpustate->intRAM[0x300];            /* B0 */
1778		cpustate->datamap[7] = &cpustate->intRAM[0x380];            /* B0 */
1779		cpustate->datamap[8] = &cpustate->intRAM[0x400];            /* B1 */
1780		cpustate->datamap[9] = &cpustate->intRAM[0x480];            /* B1 */
1781		cpustate->datamap[10] = &cpustate->intRAM[0x500];           /* B1 */
1782		cpustate->datamap[11] = &cpustate->intRAM[0x580];           /* B1 */
1783		cpustate->datamap[12] = &cpustate->intRAM[0x600];           /* B3 */
1784		cpustate->datamap[13] = &cpustate->intRAM[0x680];           /* B3 */
1785		cpustate->datamap[14] = &cpustate->intRAM[0x700];           /* B3 */
1786		cpustate->datamap[15] = &cpustate->intRAM[0x780];           /* B3 */
	1876	m_datamap[8] = &m_intRAM[0x400];            /* B1 */
	1877	m_datamap[9] = &m_intRAM[0x480];            /* B1 */
	1878	m_datamap[10] = &m_intRAM[0x500];           /* B1 */
	1879	m_datamap[11] = &m_intRAM[0x580];           /* B1 */
	1880	m_datamap[12] = &m_intRAM[0x600];           /* B3 */
	1881	m_datamap[13] = &m_intRAM[0x680];           /* B3 */
	1882	m_datamap[14] = &m_intRAM[0x700];           /* B3 */
	1883	m_datamap[15] = &m_intRAM[0x780];           /* B3 */
1787	1884	}
1788	1885
1789	1886
1790	1887	/****************************************************************************
1791		*  Shut down CPU emulation
1792		****************************************************************************/
1793		static CPU_EXIT( tms32025 )
1794		{
1795		}
1796
1797
1798		/****************************************************************************
1799	1888	*  Issue an interrupt if necessary
1800	1889	****************************************************************************/
1801		INLINE int process_IRQs(tms32025_state *cpustate)
	1890	int tms32025_device::process_IRQs()
1802	1891	{
1803	1892	/********** Interrupt Flag Register (IFR) **********
1804	1893	|  5  |  4  |  3  |  2  |  1  |  0  |
1805	1894	| XINT| RINT| TINT| INT2| INT1| INT0|
1806	1895	*/
1807	1896
1808		cpustate->tms32025_irq_cycles = 0;
	1897	m_tms32025_irq_cycles = 0;
1809	1898
1810	1899	/* Dont service Interrupts if masked, or prev instruction was EINT ! */
1811	1900
1812		if ( (INTM == 0) && (cpustate->opcode.w.l != 0xce00) && (cpustate->IFR & IMR) )
	1901	if ( (INTM == 0) && (m_opcode.w.l != 0xce00) && (m_IFR & IMR) )
1813	1902	{
1814		cpustate->tms32025_irq_cycles = (3*CLK);    /* 3 clock cycles used due to PUSH and DINT operation ? */
1815		PUSH_STACK(cpustate, cpustate->PC);
	1903	m_tms32025_irq_cycles = (3*CLK);    /* 3 clock cycles used due to PUSH and DINT operation ? */
	1904	PUSH_STACK(m_PC);
1816	1905
1817		if ((cpustate->IFR & 0x01) && (IMR & 0x01)) {       /* IRQ line 0 */
	1906	if ((m_IFR & 0x01) && (IMR & 0x01)) {       /* IRQ line 0 */
1818	1907	//logerror("TMS32025:  Active INT0\n");
1819	1908	SET_PC(0x0002);
1820		(*cpustate->irq_callback)(cpustate->device, 0);
1821		cpustate->idle = 0;
1822		cpustate->IFR &= (~0x01);
1823		SET0(cpustate, INTM_FLAG);
1824		return cpustate->tms32025_irq_cycles;
	1909	standard_irq_callback(0);
	1910	m_idle = 0;
	1911	m_IFR &= (~0x01);
	1912	SET0(INTM_FLAG);
	1913	return m_tms32025_irq_cycles;
1825	1914	}
1826		if ((cpustate->IFR & 0x02) && (IMR & 0x02)) {       /* IRQ line 1 */
	1915	if ((m_IFR & 0x02) && (IMR & 0x02)) {       /* IRQ line 1 */
1827	1916	//logerror("TMS32025:  Active INT1\n");
1828	1917	SET_PC(0x0004);
1829		(*cpustate->irq_callback)(cpustate->device, 1);
1830		cpustate->idle = 0;
1831		cpustate->IFR &= (~0x02);
1832		SET0(cpustate, INTM_FLAG);
1833		return cpustate->tms32025_irq_cycles;
	1918	standard_irq_callback(1);
	1919	m_idle = 0;
	1920	m_IFR &= (~0x02);
	1921	SET0(INTM_FLAG);
	1922	return m_tms32025_irq_cycles;
1834	1923	}
1835		if ((cpustate->IFR & 0x04) && (IMR & 0x04)) {       /* IRQ line 2 */
	1924	if ((m_IFR & 0x04) && (IMR & 0x04)) {       /* IRQ line 2 */
1836	1925	//logerror("TMS32025:  Active INT2\n");
1837	1926	SET_PC(0x0006);
1838		(*cpustate->irq_callback)(cpustate->device, 2);
1839		cpustate->idle = 0;
1840		cpustate->IFR &= (~0x04);
1841		SET0(cpustate, INTM_FLAG);
1842		return cpustate->tms32025_irq_cycles;
	1927	standard_irq_callback(2);
	1928	m_idle = 0;
	1929	m_IFR &= (~0x04);
	1930	SET0(INTM_FLAG);
	1931	return m_tms32025_irq_cycles;
1843	1932	}
1844		if ((cpustate->IFR & 0x08) && (IMR & 0x08)) {       /* Timer IRQ (internal) */
	1933	if ((m_IFR & 0x08) && (IMR & 0x08)) {       /* Timer IRQ (internal) */
1845	1934	//          logerror("TMS32025:  Active TINT (Timer)\n");
1846	1935	SET_PC(0x0018);
1847		cpustate->idle = 0;
1848		cpustate->IFR &= (~0x08);
1849		SET0(cpustate, INTM_FLAG);
1850		return cpustate->tms32025_irq_cycles;
	1936	m_idle = 0;
	1937	m_IFR &= (~0x08);
	1938	SET0(INTM_FLAG);
	1939	return m_tms32025_irq_cycles;
1851	1940	}
1852		if ((cpustate->IFR & 0x10) && (IMR & 0x10)) {       /* Serial port receive IRQ (internal) */
	1941	if ((m_IFR & 0x10) && (IMR & 0x10)) {       /* Serial port receive IRQ (internal) */
1853	1942	//          logerror("TMS32025:  Active RINT (Serial receive)\n");
1854	1943	DRR = S_IN(TMS32025_DR);
1855	1944	SET_PC(0x001A);
1856		cpustate->idle = 0;
1857		cpustate->IFR &= (~0x10);
1858		SET0(cpustate, INTM_FLAG);
1859		return cpustate->tms32025_irq_cycles;
	1945	m_idle = 0;
	1946	m_IFR &= (~0x10);
	1947	SET0(INTM_FLAG);
	1948	return m_tms32025_irq_cycles;
1860	1949	}
1861		if ((cpustate->IFR & 0x20) && (IMR & 0x20)) {       /* Serial port transmit IRQ (internal) */
	1950	if ((m_IFR & 0x20) && (IMR & 0x20)) {       /* Serial port transmit IRQ (internal) */
1862	1951	//          logerror("TMS32025:  Active XINT (Serial transmit)\n");
1863	1952	S_OUT(TMS32025_DX,DXR);
1864	1953	SET_PC(0x001C);
1865		cpustate->idle = 0;
1866		cpustate->IFR &= (~0x20);
1867		SET0(cpustate, INTM_FLAG);
1868		return cpustate->tms32025_irq_cycles;
	1954	m_idle = 0;
	1955	m_IFR &= (~0x20);
	1956	SET0(INTM_FLAG);
	1957	return m_tms32025_irq_cycles;
1869	1958	}
1870	1959	}
1871		return cpustate->tms32025_irq_cycles;
	1960	return m_tms32025_irq_cycles;
1872	1961	}
1873	1962
1874		static void set_fsx_line(tms32025_state *cpustate, int state)
1875		{
1876		if (state != CLEAR_LINE && cpustate->waiting_for_serial_frame)
1877		{
1878		cpustate->waiting_for_serial_frame = 0;
1879		cpustate->IFR = 0x20;
1880		}
1881		}
1882	1963
1883		INLINE void process_timer(tms32025_state *cpustate, int clocks)
	1964	void tms32025_device::process_timer(int clocks)
1884	1965	{
1885	1966	int preclocks, ticks;
1886	1967
1887	1968	/* easy case: no actual ticks */
1888	1969	again:
1889		preclocks = CLK - cpustate->timerover;
	1970	preclocks = CLK - m_timerover;
1890	1971	if (clocks < preclocks)
1891	1972	{
1892		cpustate->timerover += clocks;
1893		cpustate->icount -= clocks;
	1973	m_timerover += clocks;
	1974	m_icount -= clocks;
1894	1975	return;
1895	1976	}
1896	1977
r26837	r26838
1898	1979	ticks = 1 + (clocks - preclocks) / CLK;
1899	1980	if (ticks <= TIM)
1900	1981	{
1901		cpustate->icount -= clocks;
1902		cpustate->timerover = clocks - (ticks - 1) * CLK - preclocks;
	1982	m_icount -= clocks;
	1983	m_timerover = clocks - (ticks - 1) * CLK - preclocks;
1903	1984	TIM -= ticks;
1904	1985	}
1905	1986
1906	1987	/* otherwise, overflow the timer and signal an interrupt */
1907	1988	else
1908	1989	{
1909		cpustate->icount -= preclocks + CLK * TIM;
1910		cpustate->timerover = 0;
	1990	m_icount -= preclocks + CLK * TIM;
	1991	m_timerover = 0;
1911	1992	TIM = PRD;
1912	1993
1913		cpustate->IFR |= 0x08;
1914		clocks = process_IRQs(cpustate);        /* Handle Timer IRQ */
	1994	m_IFR |= 0x08;
	1995	clocks = process_IRQs();        /* Handle Timer IRQ */
1915	1996	goto again;
1916	1997	}
1917	1998	}
r26837	r26838
1920	2001	/****************************************************************************
1921	2002	*  Execute ICount cycles. Exit when 0 or less
1922	2003	****************************************************************************/
1923		static CPU_EXECUTE( tms32025 )
	2004	void tms32025_device::execute_run()
1924	2005	{
1925		tms32025_state *cpustate = get_safe_token(device);
1926
1927
1928	2006	/**** Respond to external hold signal */
1929	2007	if (S_IN(TMS32025_HOLD) == ASSERT_LINE) {
1930		if (cpustate->hold == 0) {
	2008	if (m_hold == 0) {
1931	2009	S_OUT(TMS32025_HOLDA,ASSERT_LINE);  /* Hold-Ack (active low) */
1932	2010	}
1933		cpustate->hold = 1;
	2011	m_hold = 1;
1934	2012	if (HM) {
1935		cpustate->icount = 0;       /* Exit */
	2013	m_icount = 0;       /* Exit */
1936	2014	}
1937	2015	else {
1938		if (cpustate->external_mem_access) {
1939		cpustate->icount = 0;   /* Exit */
	2016	if (m_external_mem_access) {
	2017	m_icount = 0;   /* Exit */
1940	2018	}
1941	2019	}
1942	2020	}
1943	2021	else {
1944		if (cpustate->hold == 1) {
	2022	if (m_hold == 1) {
1945	2023	S_OUT(TMS32025_HOLDA,CLEAR_LINE);   /* Hold-Ack (active low) */
1946		process_timer(cpustate, 3);
	2024	process_timer(3);
1947	2025	}
1948		cpustate->hold = 0;
	2026	m_hold = 0;
1949	2027	}
1950	2028
1951	2029	/**** If idling, update timer and/or exit execution, but test for irqs first */
1952		if (cpustate->idle && cpustate->IFR && cpustate->icount > 0)
1953		cpustate->icount -= process_IRQs(cpustate);
	2030	if (m_idle && m_IFR && m_icount > 0)
	2031	m_icount -= process_IRQs();
1954	2032
1955		while (cpustate->idle && cpustate->icount > 0)
1956		process_timer(cpustate, cpustate->icount);
	2033	while (m_idle && m_icount > 0)
	2034	process_timer(m_icount);
1957	2035
1958		if (cpustate->icount <= 0) debugger_instruction_hook(device, cpustate->PC);
	2036	if (m_icount <= 0) debugger_instruction_hook(this, m_PC);
1959	2037
1960	2038
1961		while (cpustate->icount > 0)
	2039	while (m_icount > 0)
1962	2040	{
1963		cpustate->tms32025_dec_cycles = 0;
	2041	m_tms32025_dec_cycles = 0;
1964	2042
1965		if (cpustate->IFR) {    /* Check IRQ Flag Register for pending IRQs */
1966		cpustate->tms32025_dec_cycles += process_IRQs(cpustate);
	2043	if (m_IFR) {    /* Check IRQ Flag Register for pending IRQs */
	2044	m_tms32025_dec_cycles += process_IRQs();
1967	2045	}
1968	2046
1969		cpustate->PREVPC = cpustate->PC;
	2047	m_PREVPC = m_PC;
1970	2048
1971		debugger_instruction_hook(device, cpustate->PC);
	2049	debugger_instruction_hook(this, m_PC);
1972	2050
1973		cpustate->opcode.d = M_RDOP(cpustate->PC);
1974		cpustate->PC++;
	2051	m_opcode.d = M_RDOP(m_PC);
	2052	m_PC++;
1975	2053
1976		if (cpustate->opcode.b.h == 0xCE)   /* Opcode 0xCExx has many sub-opcodes in its minor byte */
	2054	if (m_opcode.b.h == 0xCE)   /* Opcode 0xCExx has many sub-opcodes in its minor byte */
1977	2055	{
1978		cpustate->tms32025_dec_cycles += opcode_CE_subset[cpustate->opcode.b.l].cycles;
1979		(*opcode_CE_subset[cpustate->opcode.b.l].function)(cpustate);
	2056	m_tms32025_dec_cycles += s_opcode_CE_subset[m_opcode.b.l].cycles;
	2057	(this->*s_opcode_CE_subset[m_opcode.b.l].function)();
1980	2058	}
1981		else if ((cpustate->opcode.w.l & 0xf0f8) == 0xd000) /* Opcode 0xDxxx has many sub-opcodes in its minor byte */
	2059	else if ((m_opcode.w.l & 0xf0f8) == 0xd000) /* Opcode 0xDxxx has many sub-opcodes in its minor byte */
1982	2060	{
1983		cpustate->tms32025_dec_cycles += opcode_Dx_subset[cpustate->opcode.b.l].cycles;
1984		(*opcode_Dx_subset[cpustate->opcode.b.l].function)(cpustate);
	2061	m_tms32025_dec_cycles += s_opcode_Dx_subset[m_opcode.b.l].cycles;
	2062	(this->*s_opcode_Dx_subset[m_opcode.b.l].function)();
1985	2063	}
1986	2064	else            /* Do all opcodes except the CExx and Dxxx ones */
1987	2065	{
1988		cpustate->tms32025_dec_cycles += opcode_main[cpustate->opcode.b.h].cycles;
1989		(*opcode_main[cpustate->opcode.b.h].function)(cpustate);
	2066	m_tms32025_dec_cycles += s_opcode_main[m_opcode.b.h].cycles;
	2067	(this->*s_opcode_main[m_opcode.b.h].function)();
1990	2068	}
1991	2069
1992	2070
1993		if (cpustate->init_load_addr == 2) {        /* Repeat next instruction */
	2071	if (m_init_load_addr == 2) {        /* Repeat next instruction */
1994	2072	/****************************************************\
1995	2073	******* These instructions are not repeatable ********
1996	2074	** ADLK, ANDK, LALK, LRLK, ORK,  SBLK, XORK         **
r26837	r26838
2000	2078	** B,    BANZ, BBNZ, BBZ,  BC,   BGEZ, BGZ,  BIOZ   **
2001	2079	** BNC,  BNV,  BNZ,  BV,   BZ,   CALL, BLEZ, BLZ    **
2002	2080	\****************************************************/
2003		cpustate->PREVPC = cpustate->PC;
	2081	m_PREVPC = m_PC;
2004	2082
2005		debugger_instruction_hook(device, cpustate->PC);
	2083	debugger_instruction_hook(this, m_PC);
2006	2084
2007		cpustate->opcode.d = M_RDOP(cpustate->PC);
2008		cpustate->PC++;
2009		cpustate->tms32025_dec_cycles += (1*CLK);
	2085	m_opcode.d = M_RDOP(m_PC);
	2086	m_PC++;
	2087	m_tms32025_dec_cycles += (1*CLK);
2010	2088
2011	2089	do {
2012		if (cpustate->opcode.b.h == 0xCE)
	2090	if (m_opcode.b.h == 0xCE)
2013	2091	{                           /* Do all 0xCExx Opcodes */
2014		if (cpustate->init_load_addr) {
2015		cpustate->tms32025_dec_cycles += (1*CLK);
	2092	if (m_init_load_addr) {
	2093	m_tms32025_dec_cycles += (1*CLK);
2016	2094	}
2017	2095	else {
2018		cpustate->tms32025_dec_cycles += (1*CLK);
	2096	m_tms32025_dec_cycles += (1*CLK);
2019	2097	}
2020		(*opcode_CE_subset[cpustate->opcode.b.l].function)(cpustate);
	2098	(this->*s_opcode_CE_subset[m_opcode.b.l].function)();
2021	2099	}
2022	2100	else
2023	2101	{                           /* Do all other opcodes */
2024		if (cpustate->init_load_addr) {
2025		cpustate->tms32025_dec_cycles += (1*CLK);
	2102	if (m_init_load_addr) {
	2103	m_tms32025_dec_cycles += (1*CLK);
2026	2104	}
2027	2105	else {
2028		cpustate->tms32025_dec_cycles += (1*CLK);
	2106	m_tms32025_dec_cycles += (1*CLK);
2029	2107	}
2030		(*opcode_main[cpustate->opcode.b.h].function)(cpustate);
	2108	(this->*s_opcode_main[m_opcode.b.h].function)();
2031	2109	}
2032		cpustate->init_load_addr = 0;
2033		cpustate->RPTC-- ;
2034		} while ((INT8)(cpustate->RPTC) != -1);
2035		cpustate->RPTC = 0;
2036		cpustate->PFC = cpustate->PC;
2037		cpustate->init_load_addr = 1;
	2110	m_init_load_addr = 0;
	2111	m_RPTC-- ;
	2112	} while ((INT8)(m_RPTC) != -1);
	2113	m_RPTC = 0;
	2114	m_PFC = m_PC;
	2115	m_init_load_addr = 1;
2038	2116	}
2039	2117
2040		process_timer(cpustate, cpustate->tms32025_dec_cycles);
	2118	process_timer(m_tms32025_dec_cycles);
2041	2119
2042	2120	/**** If device is put into idle mode, exit and wait for an interrupt */
2043		while (cpustate->idle && cpustate->icount > 0)
2044		process_timer(cpustate, cpustate->icount);
	2121	while (m_idle && m_icount > 0)
	2122	process_timer(m_icount);
2045	2123
2046	2124
2047	2125	/**** If hold pin is active, exit if accessing external memory or if HM is set */
2048		if (cpustate->hold) {
2049		if (cpustate->external_mem_access || (HM)) {
2050		if (cpustate->icount > 0) {
2051		cpustate->icount = 0;
	2126	if (m_hold) {
	2127	if (m_external_mem_access || (HM)) {
	2128	if (m_icount > 0) {
	2129	m_icount = 0;
2052	2130	}
2053	2131	}
2054	2132	}
r26837	r26838
2060	2138	/****************************************************************************
2061	2139	*  Set IRQ line state
2062	2140	****************************************************************************/
2063		static void set_irq_line(tms32025_state *cpustate, int irqline, int state)
	2141	void tms32025_device::execute_set_input(int irqline, int state)
2064	2142	{
2065		/* Pending IRQs cannot be cleared */
2066
2067		if (state != CLEAR_LINE)
	2143	if ( irqline == TMS32025_FSX ) {
	2144	if (state != CLEAR_LINE && m_waiting_for_serial_frame)
	2145	{
	2146	m_waiting_for_serial_frame = 0;
	2147	m_IFR = 0x20;
	2148	}
	2149	}
	2150	else
2068	2151	{
2069		cpustate->IFR |= (1 << irqline);
	2152	/* Pending IRQs cannot be cleared */
	2153	if (state != CLEAR_LINE)
	2154	{
	2155	m_IFR |= (1 << irqline);
	2156	}
2070	2157	}
2071	2158	}
2072	2159
r26837	r26838
2074	2161	/****************************************************************************
2075	2162	*  Opcode fetcher
2076	2163	****************************************************************************/
2077		static CPU_READOP( tms32025 )
	2164	bool tms32025_device::memory_readop(offs_t offset, int size, UINT64 &value)
2078	2165	{
2079		tms32025_state *cpustate = get_safe_token(device);
2080
2081	2166	void *ptr;
2082	2167
2083	2168	/* skip if not custom */
2084		if (!cpustate->pgmmap[offset >> 8])
	2169	if (!m_pgmmap[offset >> 8])
2085	2170	return 0;
2086	2171
2087		ptr = &((UINT8 *)&cpustate->pgmmap[offset >> 8])[offset & 0xff];
	2172	ptr = &((UINT8 *)&m_pgmmap[offset >> 8])[offset & 0xff];
2088	2173	switch (size)
2089	2174	{
2090		case 1: *value = *((UINT8 *) ptr);
2091		case 2: *value = *((UINT16 *) ptr);
2092		case 4: *value = *((UINT32 *) ptr);
2093		case 8: *value = *((UINT64 *) ptr);
	2175	case 1: value = *((UINT8 *) ptr);
	2176	case 2: value = *((UINT16 *) ptr);
	2177	case 4: value = *((UINT32 *) ptr);
	2178	case 8: value = *((UINT64 *) ptr);
2094	2179	}
2095	2180	return 1;
2096	2181	}
r26837	r26838
2099	2184	/****************************************************************************
2100	2185	*  Memory reader
2101	2186	****************************************************************************/
2102		static CPU_READ( tms32025 )
	2187	bool tms32025_device::memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value)
2103	2188	{
2104		tms32025_state *cpustate = get_safe_token(device);
2105
2106	2189	void *ptr = NULL;
2107	2190	UINT64 temp = 0;
2108	2191
2109		switch (space)
	2192	switch (spacenum)
2110	2193	{
2111	2194	case AS_PROGRAM:
2112		ptr = cpustate->pgmmap[offset >> 8];
	2195	ptr = m_pgmmap[offset >> 8];
2113	2196	if (!ptr)
2114	2197	return 0;
2115	2198	break;
2116	2199
2117	2200	case AS_DATA:
2118		ptr = cpustate->datamap[offset >> 8];
	2201	ptr = m_datamap[offset >> 8];
2119	2202	if (!ptr)
2120	2203	return 0;
2121	2204	break;
r26837	r26838
2128	2211	switch (size)
2129	2212	{
2130	2213	case 1:
2131		*value = ((UINT8 *)ptr)[BYTE_XOR_BE(offset & 0xff)];
	2214	value = ((UINT8 *)ptr)[BYTE_XOR_BE(offset & 0xff)];
2132	2215	break;
2133	2216	case 2:
2134		*value = ((UINT16 *)ptr)[(offset & 0xff) / 2];
	2217	value = ((UINT16 *)ptr)[(offset & 0xff) / 2];
2135	2218	break;
2136	2219	case 4:
2137		CPU_READ_NAME(tms32025)(device, space, offset + 0, 2, &temp);
2138		*value = temp << 16;
2139		CPU_READ_NAME(tms32025)(device, space, offset + 2, 2, &temp);
2140		*value |= temp & 0xffff;
	2220	memory_read(spacenum, offset + 0, 2, temp);
	2221	value = temp << 16;
	2222	memory_read(spacenum, offset + 2, 2, temp);
	2223	value |= temp & 0xffff;
2141	2224	break;
2142	2225	case 8:
2143		CPU_READ_NAME(tms32025)(device, space, offset + 0, 4, &temp);
2144		*value = temp << 32;
2145		CPU_READ_NAME(tms32025)(device, space, offset + 4, 4, &temp);
2146		*value |= temp & 0xffffffff;
	2226	memory_read(spacenum, offset + 0, 4, temp);
	2227	value = temp << 32;
	2228	memory_read(spacenum, offset + 4, 4, temp);
	2229	value |= temp & 0xffffffff;
2147	2230	break;
2148	2231	}
2149	2232	return 1;
r26837	r26838
2153	2236	/****************************************************************************
2154	2237	*  Memory writer
2155	2238	****************************************************************************/
2156		static CPU_WRITE( tms32025 )
	2239	bool tms32025_device::memory_write(address_spacenum spacenum, offs_t offset, int size, UINT64 value)
2157	2240	{
2158		tms32025_state *cpustate = get_safe_token(device);
2159
2160	2241	void *ptr = NULL;
2161	2242
2162		switch (space)
	2243	switch (spacenum)
2163	2244	{
2164	2245	case AS_PROGRAM:
2165		ptr = cpustate->pgmmap[offset >> 8];
	2246	ptr = m_pgmmap[offset >> 8];
2166	2247	if (!ptr)
2167	2248	return 0;
2168	2249	break;
2169	2250
2170	2251	case AS_DATA:
2171		ptr = cpustate->datamap[offset >> 8];
	2252	ptr = m_datamap[offset >> 8];
2172	2253	if (!ptr)
2173	2254	return 0;
2174	2255	break;
r26837	r26838
2187	2268	((UINT16 *)ptr)[(offset & 0xff) / 2] = value;
2188	2269	break;
2189	2270	case 4:
2190		CPU_WRITE_NAME(tms32025)(device, space, offset + 0, 2, value >> 16);
2191		CPU_WRITE_NAME(tms32025)(device, space, offset + 2, 2, value);
	2271	memory_write(spacenum, offset + 0, 2, value >> 16);
	2272	memory_write(spacenum, offset + 2, 2, value);
2192	2273	break;
2193	2274	case 8:
2194		CPU_WRITE_NAME(tms32025)(device, space, offset + 0, 4, value >> 32);
2195		CPU_WRITE_NAME(tms32025)(device, space, offset + 4, 4, value);
	2275	memory_write(spacenum, offset + 0, 4, value >> 32);
	2276	memory_write(spacenum, offset + 4, 4, value);
2196	2277	break;
2197	2278	}
2198	2279
2199	2280	return 1;
2200	2281	}
2201	2282
2202
2203		/**************************************************************************
2204		* Generic set_info
2205		**************************************************************************/
2206
2207		static CPU_SET_INFO( tms32025 )
2208		{
2209		tms32025_state *cpustate = get_safe_token(device);
2210
2211		switch (state)
2212		{
2213		/* --- the following bits of info are set as 64-bit signed integers --- */
2214		case CPUINFO_INT_INPUT_STATE + TMS32025_INT0:       set_irq_line(cpustate, TMS32025_INT0, info->i); break;
2215		case CPUINFO_INT_INPUT_STATE + TMS32025_INT1:       set_irq_line(cpustate, TMS32025_INT1, info->i); break;
2216		case CPUINFO_INT_INPUT_STATE + TMS32025_INT2:       set_irq_line(cpustate, TMS32025_INT2, info->i); break;
2217		case CPUINFO_INT_INPUT_STATE + TMS32025_TINT:       set_irq_line(cpustate, TMS32025_TINT, info->i); break;
2218		case CPUINFO_INT_INPUT_STATE + TMS32025_RINT:       set_irq_line(cpustate, TMS32025_RINT, info->i); break;
2219		case CPUINFO_INT_INPUT_STATE + TMS32025_XINT:       set_irq_line(cpustate, TMS32025_XINT, info->i); break;
2220		case CPUINFO_INT_INPUT_STATE + TMS32025_FSX:        set_fsx_line(cpustate, info->i); break;
2221
2222		case CPUINFO_INT_PC:
2223		case CPUINFO_INT_REGISTER + TMS32025_PC:        cpustate->PC = info->i;                         break;
2224		/* This is actually not a stack pointer, but the stack contents */
2225		case CPUINFO_INT_SP:
2226		case CPUINFO_INT_REGISTER + TMS32025_STK7:      cpustate->STACK[7] = info->i;                   break;
2227		case CPUINFO_INT_REGISTER + TMS32025_STK6:      cpustate->STACK[6] = info->i;                   break;
2228		case CPUINFO_INT_REGISTER + TMS32025_STK5:      cpustate->STACK[5] = info->i;                   break;
2229		case CPUINFO_INT_REGISTER + TMS32025_STK4:      cpustate->STACK[4] = info->i;                   break;
2230		case CPUINFO_INT_REGISTER + TMS32025_STK3:      cpustate->STACK[3] = info->i;                   break;
2231		case CPUINFO_INT_REGISTER + TMS32025_STK2:      cpustate->STACK[2] = info->i;                   break;
2232		case CPUINFO_INT_REGISTER + TMS32025_STK1:      cpustate->STACK[1] = info->i;                   break;
2233		case CPUINFO_INT_REGISTER + TMS32025_STK0:      cpustate->STACK[0] = info->i;                   break;
2234		case CPUINFO_INT_REGISTER + TMS32025_STR0:      cpustate->STR0 = info->i;                       break;
2235		case CPUINFO_INT_REGISTER + TMS32025_STR1:      cpustate->STR1 = info->i;                       break;
2236		case CPUINFO_INT_REGISTER + TMS32025_IFR:       cpustate->IFR = info->i;                        break;
2237		case CPUINFO_INT_REGISTER + TMS32025_RPTC:      cpustate->RPTC = info->i;                       break;
2238		case CPUINFO_INT_REGISTER + TMS32025_ACC:       cpustate->ACC.d = info->i;                      break;
2239		case CPUINFO_INT_REGISTER + TMS32025_PREG:      cpustate->Preg.d = info->i;                     break;
2240		case CPUINFO_INT_REGISTER + TMS32025_TREG:      cpustate->Treg = info->i;                       break;
2241		case CPUINFO_INT_REGISTER + TMS32025_AR0:       cpustate->AR[0] = info->i;                      break;
2242		case CPUINFO_INT_REGISTER + TMS32025_AR1:       cpustate->AR[1] = info->i;                      break;
2243		case CPUINFO_INT_REGISTER + TMS32025_AR2:       cpustate->AR[2] = info->i;                      break;
2244		case CPUINFO_INT_REGISTER + TMS32025_AR3:       cpustate->AR[3] = info->i;                      break;
2245		case CPUINFO_INT_REGISTER + TMS32025_AR4:       cpustate->AR[4] = info->i;                      break;
2246		case CPUINFO_INT_REGISTER + TMS32025_AR5:       cpustate->AR[5] = info->i;                      break;
2247		case CPUINFO_INT_REGISTER + TMS32025_AR6:       cpustate->AR[6] = info->i;                      break;
2248		case CPUINFO_INT_REGISTER + TMS32025_AR7:       cpustate->AR[7] = info->i;                      break;
2249		case CPUINFO_INT_REGISTER + TMS32025_DRR:       M_WRTRAM(cpustate, 0,info->i);                  break;
2250		case CPUINFO_INT_REGISTER + TMS32025_DXR:       M_WRTRAM(cpustate, 1,info->i);                  break;
2251		case CPUINFO_INT_REGISTER + TMS32025_TIM:       M_WRTRAM(cpustate, 2,info->i);                  break;
2252		case CPUINFO_INT_REGISTER + TMS32025_PRD:       M_WRTRAM(cpustate, 3,info->i);                  break;
2253		case CPUINFO_INT_REGISTER + TMS32025_IMR:       M_WRTRAM(cpustate, 4,info->i);                  break;
2254		case CPUINFO_INT_REGISTER + TMS32025_GREG:      M_WRTRAM(cpustate, 5,info->i);                  break;
2255		}
2256		}
2257
2258
2259
2260		/**************************************************************************
2261		* Generic get_info
2262		**************************************************************************/
2263
2264		CPU_GET_INFO( tms32025 )
2265		{
2266		tms32025_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
2267
2268		switch (state)
2269		{
2270		/* --- the following bits of info are returned as 64-bit signed integers --- */
2271		case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(tms32025_state);       break;
2272		case CPUINFO_INT_INPUT_LINES:                   info->i = 6;                            break;
2273		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
2274		case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;               break;
2275		case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
2276		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
2277		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 2;                            break;
2278		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 4;                            break;
2279		case CPUINFO_INT_MIN_CYCLES:                    info->i = 1*CLK;                        break;
2280		case CPUINFO_INT_MAX_CYCLES:                    info->i = 5*CLK;                        break;
2281
2282		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 16;                   break;
2283		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16;                  break;
2284		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -1;                  break;
2285		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 16;                   break;
2286		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 16;                   break;
2287		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = -1;                   break;
2288		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 16;                   break;
2289		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 17;                   break;
2290		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = -1;                   break;
2291
2292		case CPUINFO_INT_INPUT_STATE + TMS32025_INT0:       info->i = (cpustate->IFR & 0x01) ? ASSERT_LINE : CLEAR_LINE; break;
2293		case CPUINFO_INT_INPUT_STATE + TMS32025_INT1:       info->i = (cpustate->IFR & 0x02) ? ASSERT_LINE : CLEAR_LINE; break;
2294		case CPUINFO_INT_INPUT_STATE + TMS32025_INT2:       info->i = (cpustate->IFR & 0x04) ? ASSERT_LINE : CLEAR_LINE; break;
2295		case CPUINFO_INT_INPUT_STATE + TMS32025_TINT:       info->i = (cpustate->IFR & 0x08) ? ASSERT_LINE : CLEAR_LINE; break;
2296		case CPUINFO_INT_INPUT_STATE + TMS32025_RINT:       info->i = (cpustate->IFR & 0x10) ? ASSERT_LINE : CLEAR_LINE; break;
2297		case CPUINFO_INT_INPUT_STATE + TMS32025_XINT:       info->i = (cpustate->IFR & 0x20) ? ASSERT_LINE : CLEAR_LINE; break;
2298
2299		case CPUINFO_INT_PREVIOUSPC:                    info->i = cpustate->PREVPC;                     break;
2300
2301		case CPUINFO_INT_PC:
2302		case CPUINFO_INT_REGISTER + TMS32025_PC:        info->i = cpustate->PC;                         break;
2303		/* This is actually not a stack pointer, but the stack contents */
2304		case CPUINFO_INT_SP:
2305		case CPUINFO_INT_REGISTER + TMS32025_STK7:      info->i = cpustate->STACK[7];                   break;
2306		case CPUINFO_INT_REGISTER + TMS32025_STK6:      info->i = cpustate->STACK[6];                   break;
2307		case CPUINFO_INT_REGISTER + TMS32025_STK5:      info->i = cpustate->STACK[5];                   break;
2308		case CPUINFO_INT_REGISTER + TMS32025_STK4:      info->i = cpustate->STACK[4];                   break;
2309		case CPUINFO_INT_REGISTER + TMS32025_STK3:      info->i = cpustate->STACK[3];                   break;
2310		case CPUINFO_INT_REGISTER + TMS32025_STK2:      info->i = cpustate->STACK[2];                   break;
2311		case CPUINFO_INT_REGISTER + TMS32025_STK1:      info->i = cpustate->STACK[1];                   break;
2312		case CPUINFO_INT_REGISTER + TMS32025_STK0:      info->i = cpustate->STACK[0];                   break;
2313		case CPUINFO_INT_REGISTER + TMS32025_STR0:      info->i = cpustate->STR0;                       break;
2314		case CPUINFO_INT_REGISTER + TMS32025_STR1:      info->i = cpustate->STR1;                       break;
2315		case CPUINFO_INT_REGISTER + TMS32025_IFR:       info->i = cpustate->IFR;                        break;
2316		case CPUINFO_INT_REGISTER + TMS32025_RPTC:      info->i = cpustate->RPTC;                       break;
2317		case CPUINFO_INT_REGISTER + TMS32025_ACC:       info->i = cpustate->ACC.d;                      break;
2318		case CPUINFO_INT_REGISTER + TMS32025_PREG:      info->i = cpustate->Preg.d;                     break;
2319		case CPUINFO_INT_REGISTER + TMS32025_TREG:      info->i = cpustate->Treg;                       break;
2320		case CPUINFO_INT_REGISTER + TMS32025_AR0:       info->i = cpustate->AR[0];                      break;
2321		case CPUINFO_INT_REGISTER + TMS32025_AR1:       info->i = cpustate->AR[1];                      break;
2322		case CPUINFO_INT_REGISTER + TMS32025_AR2:       info->i = cpustate->AR[2];                      break;
2323		case CPUINFO_INT_REGISTER + TMS32025_AR3:       info->i = cpustate->AR[3];                      break;
2324		case CPUINFO_INT_REGISTER + TMS32025_AR4:       info->i = cpustate->AR[4];                      break;
2325		case CPUINFO_INT_REGISTER + TMS32025_AR5:       info->i = cpustate->AR[5];                      break;
2326		case CPUINFO_INT_REGISTER + TMS32025_AR6:       info->i = cpustate->AR[6];                      break;
2327		case CPUINFO_INT_REGISTER + TMS32025_AR7:       info->i = cpustate->AR[7];                      break;
2328		case CPUINFO_INT_REGISTER + TMS32025_DRR:       info->i = M_RDRAM(cpustate, 0);                 break;
2329		case CPUINFO_INT_REGISTER + TMS32025_DXR:       info->i = M_RDRAM(cpustate, 1);                 break;
2330		case CPUINFO_INT_REGISTER + TMS32025_TIM:       info->i = M_RDRAM(cpustate, 2);                 break;
2331		case CPUINFO_INT_REGISTER + TMS32025_PRD:       info->i = M_RDRAM(cpustate, 3);                 break;
2332		case CPUINFO_INT_REGISTER + TMS32025_IMR:       info->i = M_RDRAM(cpustate, 4);                 break;
2333		case CPUINFO_INT_REGISTER + TMS32025_GREG:      info->i = M_RDRAM(cpustate, 5);                 break;
2334
2335		/* --- the following bits of info are returned as pointers to data or functions --- */
2336		case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(tms32025);    break;
2337		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(tms32025);           break;
2338		case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(tms32025);         break;
2339		case CPUINFO_FCT_EXIT:                          info->exit = CPU_EXIT_NAME(tms32025);           break;
2340		case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(tms32025);     break;
2341		case CPUINFO_FCT_BURN:                          info->burn = NULL;                              break;
2342		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(tms32025); break;
2343		case CPUINFO_FCT_READ:                          info->read = CPU_READ_NAME(tms32025);               break;
2344		case CPUINFO_FCT_WRITE:                         info->write = CPU_WRITE_NAME(tms32025);         break;
2345		case CPUINFO_FCT_READOP:                        info->readop = CPU_READOP_NAME(tms32025);           break;
2346		case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &cpustate->icount;       break;
2347
2348		/* --- the following bits of info are returned as NULL-terminated strings --- */
2349		case CPUINFO_STR_NAME:                          strcpy(info->s, "TMS32025");            break;
2350		case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "tms32025");            break;
2351		case CPUINFO_STR_FAMILY:                    strcpy(info->s, "Texas Instruments TMS320x25"); break;
2352		case CPUINFO_STR_VERSION:                   strcpy(info->s, "1.10");                break;
2353		case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__);              break;
2354		case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Copyright Tony La Porta"); break;
2355
2356		case CPUINFO_STR_FLAGS:
2357		sprintf(info->s, "arp%d%c%c%c%cdp%03x  arb%d%c%c%c%c%c%c%c%c%c%c%cpm%d",
2358		(cpustate->STR0 & 0xe000) >> 13,
2359		cpustate->STR0 & 0x1000 ? 'O':'.',
2360		cpustate->STR0 & 0x0800 ? 'M':'.',
2361		cpustate->STR0 & 0x0400 ? '.':'?',
2362		cpustate->STR0 & 0x0200 ? 'I':'.',
2363		(cpustate->STR0 & 0x01ff),
2364
2365		(cpustate->STR1 & 0xe000) >> 13,
2366		cpustate->STR1 & 0x1000 ? 'P':'D',
2367		cpustate->STR1 & 0x0800 ? 'T':'.',
2368		cpustate->STR1 & 0x0400 ? 'S':'.',
2369		cpustate->STR1 & 0x0200 ? 'C':'?',
2370		cpustate->STR0 & 0x0100 ? '.':'?',
2371		cpustate->STR1 & 0x0080 ? '.':'?',
2372		cpustate->STR1 & 0x0040 ? 'H':'.',
2373		cpustate->STR1 & 0x0020 ? 'F':'.',
2374		cpustate->STR1 & 0x0010 ? 'X':'.',
2375		cpustate->STR1 & 0x0008 ? 'f':'.',
2376		cpustate->STR1 & 0x0004 ? 'o':'i',
2377		(cpustate->STR1 & 0x0003) );
2378		break;
2379
2380		case CPUINFO_STR_REGISTER + TMS32025_PC:        sprintf(info->s, "PC:%04X",  cpustate->PC); break;
2381		case CPUINFO_STR_REGISTER + TMS32025_STR0:      sprintf(info->s, "STR0:%04X", cpustate->STR0); break;
2382		case CPUINFO_STR_REGISTER + TMS32025_STR1:      sprintf(info->s, "STR1:%04X", cpustate->STR1); break;
2383		case CPUINFO_STR_REGISTER + TMS32025_IFR:       sprintf(info->s, "IFR:%04X", cpustate->IFR); break;
2384		case CPUINFO_STR_REGISTER + TMS32025_RPTC:      sprintf(info->s, "RPTC:%02X", cpustate->RPTC); break;
2385		case CPUINFO_STR_REGISTER + TMS32025_STK7:      sprintf(info->s, "STK7:%04X", cpustate->STACK[7]); break;
2386		case CPUINFO_STR_REGISTER + TMS32025_STK6:      sprintf(info->s, "STK6:%04X", cpustate->STACK[6]); break;
2387		case CPUINFO_STR_REGISTER + TMS32025_STK5:      sprintf(info->s, "STK5:%04X", cpustate->STACK[5]); break;
2388		case CPUINFO_STR_REGISTER + TMS32025_STK4:      sprintf(info->s, "STK4:%04X", cpustate->STACK[4]); break;
2389		case CPUINFO_STR_REGISTER + TMS32025_STK3:      sprintf(info->s, "STK3:%04X", cpustate->STACK[3]); break;
2390		case CPUINFO_STR_REGISTER + TMS32025_STK2:      sprintf(info->s, "STK2:%04X", cpustate->STACK[2]); break;
2391		case CPUINFO_STR_REGISTER + TMS32025_STK1:      sprintf(info->s, "STK1:%04X", cpustate->STACK[1]); break;
2392		case CPUINFO_STR_REGISTER + TMS32025_STK0:      sprintf(info->s, "STK0:%04X", cpustate->STACK[0]); break;
2393		case CPUINFO_STR_REGISTER + TMS32025_ACC:       sprintf(info->s, "ACC:%08X", cpustate->ACC.d); break;
2394		case CPUINFO_STR_REGISTER + TMS32025_PREG:      sprintf(info->s, "P:%08X", cpustate->Preg.d); break;
2395		case CPUINFO_STR_REGISTER + TMS32025_TREG:      sprintf(info->s, "T:%04X", cpustate->Treg); break;
2396		case CPUINFO_STR_REGISTER + TMS32025_AR0:       sprintf(info->s, "AR0:%04X", cpustate->AR[0]); break;
2397		case CPUINFO_STR_REGISTER + TMS32025_AR1:       sprintf(info->s, "AR1:%04X", cpustate->AR[1]); break;
2398		case CPUINFO_STR_REGISTER + TMS32025_AR2:       sprintf(info->s, "AR2:%04X", cpustate->AR[2]); break;
2399		case CPUINFO_STR_REGISTER + TMS32025_AR3:       sprintf(info->s, "AR3:%04X", cpustate->AR[3]); break;
2400		case CPUINFO_STR_REGISTER + TMS32025_AR4:       sprintf(info->s, "AR4:%04X", cpustate->AR[4]); break;
2401		case CPUINFO_STR_REGISTER + TMS32025_AR5:       sprintf(info->s, "AR5:%04X", cpustate->AR[5]); break;
2402		case CPUINFO_STR_REGISTER + TMS32025_AR6:       sprintf(info->s, "AR6:%04X", cpustate->AR[6]); break;
2403		case CPUINFO_STR_REGISTER + TMS32025_AR7:       sprintf(info->s, "AR7:%04X", cpustate->AR[7]); break;
2404		case CPUINFO_STR_REGISTER + TMS32025_DRR:       sprintf(info->s, "DRR:%04X", M_RDRAM(cpustate, 0)); break;
2405		case CPUINFO_STR_REGISTER + TMS32025_DXR:       sprintf(info->s, "DXR:%04X", M_RDRAM(cpustate, 1)); break;
2406		case CPUINFO_STR_REGISTER + TMS32025_TIM:       sprintf(info->s, "TIM:%04X", M_RDRAM(cpustate, 2)); break;
2407		case CPUINFO_STR_REGISTER + TMS32025_PRD:       sprintf(info->s, "PRD:%04X", M_RDRAM(cpustate, 3)); break;
2408		case CPUINFO_STR_REGISTER + TMS32025_IMR:       sprintf(info->s, "IMR:%04X", M_RDRAM(cpustate, 4)); break;
2409		case CPUINFO_STR_REGISTER + TMS32025_GREG:      sprintf(info->s, "GREG:%04X", M_RDRAM(cpustate, 5)); break;
2410		}
2411		}
2412
2413
2414		/**************************************************************************
2415		* CPU-specific set_info
2416		**************************************************************************/
2417
2418		CPU_GET_INFO( tms32026 )
2419		{
2420		switch (state)
2421		{
2422		/* --- the following bits of info are returned as pointers to data or functions --- */
2423		case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(tms32026); break;
2424
2425		/* --- the following bits of info are returned as NULL-terminated strings --- */
2426		case CPUINFO_STR_NAME:                          strcpy(info->s, "TMS32026");            break;
2427		case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "tms32026");            break;
2428
2429		default:                                        CPU_GET_INFO_CALL(tms32025);            break;
2430		}
2431		}
2432
2433		DEFINE_LEGACY_CPU_DEVICE(TMS32025, tms32025);
2434		DEFINE_LEGACY_CPU_DEVICE(TMS32026, tms32026);

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