trunk/src/emu/machine/mc68901.c
| r26788 | r26789 | |
|---|
| 408 | 408 | save_item(NAME(m_rsr)); |
| 409 | 409 | save_item(NAME(m_tsr)); |
| 410 | 410 | save_item(NAME(m_udr)); |
| 411 | | save_item(NAME(m_rx_bits)); |
| 412 | | save_item(NAME(m_tx_bits)); |
| 413 | | save_item(NAME(m_rx_parity)); |
| 414 | | save_item(NAME(m_tx_parity)); |
| 415 | | save_item(NAME(m_rx_state)); |
| 416 | | save_item(NAME(m_tx_state)); |
| 417 | | save_item(NAME(m_rx_buffer)); |
| 418 | | save_item(NAME(m_tx_buffer)); |
| 419 | | save_item(NAME(m_xmit_state)); |
| 411 | save_item(NAME(m_udr_written)); |
| 420 | 412 | save_item(NAME(m_rxtx_word)); |
| 421 | 413 | save_item(NAME(m_rxtx_start)); |
| 422 | 414 | save_item(NAME(m_rxtx_stop)); |
| r26788 | r26789 | |
|---|
| 431 | 423 | |
| 432 | 424 | void mc68901_device::device_reset() |
| 433 | 425 | { |
| 434 | | m_xmit_state = XMIT_OFF; |
| 435 | | m_rx_state = SERIAL_STOP; |
| 436 | | m_rx_buffer = 0; |
| 437 | | m_tx_buffer = 0; |
| 426 | m_tsr = 0; |
| 427 | m_udr_written = 0; |
| 438 | 428 | |
| 439 | 429 | // Avoid read-before-write |
| 440 | 430 | m_ipr = m_imr = 0; |
| r26788 | r26789 | |
|---|
| 463 | 453 | register_w(REGISTER_SCR, 0); |
| 464 | 454 | register_w(REGISTER_UCR, 0); |
| 465 | 455 | register_w(REGISTER_RSR, 0); |
| 456 | |
| 457 | transmit_register_reset(); |
| 466 | 458 | } |
| 467 | 459 | |
| 468 | 460 | |
| r26788 | r26789 | |
|---|
| 498 | 490 | |
| 499 | 491 | void mc68901_device::tra_complete() |
| 500 | 492 | { |
| 493 | if (m_tsr & TSR_XMIT_ENABLE) |
| 494 | { |
| 495 | if (m_udr_written) |
| 496 | { |
| 497 | transmit_register_setup(m_udr); |
| 498 | m_udr_written = 0; |
| 499 | m_tsr |= TSR_BUFFER_EMPTY; |
| 500 | } |
| 501 | } |
| 502 | else |
| 503 | { |
| 504 | m_tsr |= TSR_END_OF_XMIT; |
| 505 | } |
| 501 | 506 | } |
| 502 | 507 | |
| 503 | 508 | |
| r26788 | r26789 | |
|---|
| 573 | 578 | { |
| 574 | 579 | /* clear UE bit (in reality, this won't be cleared until one full clock cycle of the transmitter has passed since the bit was set) */ |
| 575 | 580 | UINT8 tsr = m_tsr; |
| 576 | | m_tsr &= 0xbf; |
| 581 | m_tsr &= ~TSR_UNDERRUN_ERROR; |
| 577 | 582 | |
| 578 | 583 | return tsr; |
| 579 | 584 | } |
| r26788 | r26789 | |
|---|
| 999 | 1004 | break; |
| 1000 | 1005 | |
| 1001 | 1006 | case REGISTER_TSR: |
| 1007 | m_tsr = (m_tsr & (TSR_BUFFER_EMPTY | TSR_UNDERRUN_ERROR | TSR_END_OF_XMIT)) | (data & ~(TSR_BUFFER_EMPTY | TSR_UNDERRUN_ERROR | TSR_END_OF_XMIT)); |
| 1008 | |
| 1002 | 1009 | if ((data & TSR_XMIT_ENABLE) == 0) |
| 1003 | 1010 | { |
| 1004 | 1011 | if (LOG) logerror("MC68901 '%s' Transmitter Disabled\n", tag()); |
| 1005 | 1012 | |
| 1006 | | m_tsr = data & 0x27; |
| 1013 | m_tsr &= ~TSR_UNDERRUN_ERROR; |
| 1014 | |
| 1015 | if (is_transmit_register_empty()) |
| 1016 | m_tsr |= TSR_END_OF_XMIT; |
| 1007 | 1017 | } |
| 1008 | 1018 | else |
| 1009 | 1019 | { |
| r26788 | r26789 | |
|---|
| 1043 | 1053 | if (LOG) logerror("MC68901 '%s' Transmitter Auto Turnaround Disabled\n", tag()); |
| 1044 | 1054 | } |
| 1045 | 1055 | |
| 1046 | | m_tsr = data & 0x2f; |
| 1047 | | m_tsr |= TSR_BUFFER_EMPTY; // x68000 expects the buffer to be empty, so this will do for now |
| 1056 | m_tsr &= ~TSR_END_OF_XMIT; |
| 1057 | |
| 1058 | if(m_udr_written && is_transmit_register_empty()) |
| 1059 | { |
| 1060 | transmit_register_setup(m_udr); |
| 1061 | m_udr_written = 0; |
| 1062 | m_tsr |= TSR_BUFFER_EMPTY; |
| 1063 | } |
| 1048 | 1064 | } |
| 1049 | 1065 | break; |
| 1050 | 1066 | |
| 1051 | 1067 | case REGISTER_UDR: |
| 1052 | 1068 | if (LOG) logerror("MC68901 '%s' UDR %x\n", tag(), data); |
| 1053 | 1069 | m_udr = data; |
| 1054 | | //m_tsr &= ~TSR_BUFFER_EMPTY; |
| 1070 | m_udr_written = 1; |
| 1071 | m_tsr &= ~TSR_BUFFER_EMPTY; |
| 1072 | |
| 1073 | if ((m_tsr & TSR_XMIT_ENABLE) && is_transmit_register_empty()) |
| 1074 | { |
| 1075 | transmit_register_setup(m_udr); |
| 1076 | m_udr_written = 0; |
| 1077 | m_tsr |= TSR_BUFFER_EMPTY; |
| 1078 | } |
| 1055 | 1079 | break; |
| 1056 | 1080 | } |
| 1057 | 1081 | } |
trunk/src/emu/machine/mc68901.h
| r26788 | r26789 | |
|---|
| 270 | 270 | UINT8 m_tsr; /* transmitter status register */ |
| 271 | 271 | UINT8 m_rsr; /* receiver status register */ |
| 272 | 272 | UINT8 m_udr; /* USART data register */ |
| 273 | int m_udr_written; |
| 273 | 274 | |
| 274 | 275 | /* counter timer state */ |
| 275 | 276 | UINT8 m_tmc[4]; /* timer main counters */ |
| r26788 | r26789 | |
|---|
| 286 | 287 | int m_rxtx_start; /* start bits */ |
| 287 | 288 | int m_rxtx_stop; /* stop bits */ |
| 288 | 289 | |
| 289 | | /* receive state */ |
| 290 | | UINT8 m_rx_buffer; /* receive buffer */ |
| 291 | | int m_rx_bits; /* receive bit count */ |
| 292 | | int m_rx_parity; /* receive parity bit */ |
| 293 | | int m_rx_state; /* receive state */ |
| 294 | | |
| 295 | | /* transmit state */ |
| 296 | | UINT8 m_tx_buffer; /* transmit buffer */ |
| 297 | | int m_tx_bits; /* transmit bit count */ |
| 298 | | int m_tx_parity; /* transmit parity bit */ |
| 299 | | int m_tx_state; /* transmit state */ |
| 300 | | int m_xmit_state; /* transmitter state */ |
| 301 | | |
| 302 | 290 | // timers |
| 303 | 291 | emu_timer *m_timer[4]; /* counter timers */ |
| 304 | 292 | }; |