Previous

199869 Revisions

Next

r26785 Friday 27th December, 2013 at 18:17:26 UTC by Wilbert Pol
sc61860.c: Modernized cpu core.  [Wilbert Pol]

[src/emu/cpu/sc61860]	sc61860.c sc61860.h scops.c sctable.c
[src/mess/drivers]	pocketc.c
[src/mess/includes]	pc1251.h pc1350.h pc1401.h pc1403.h
[src/mess/machine]	pc1251.c pc1350.c pc1401.c pc1403.c

trunk/src/emu/cpu/sc61860/sctable.c

r26784	r26785
1	1
2		static void sc61860_instruction(sc61860_state *cpustate)
	2	void sc61860_device::sc61860_instruction()
3	3	{
4		int oper=READ_OP(cpustate);
	4	int oper=READ_OP();
5	5	if ((oper&0xc0)==0x80) {
6		sc61860_load_imm_p(cpustate, oper&0x3f);cpustate->icount-=2;
	6	sc61860_load_imm_p(oper&0x3f);m_icount-=2;
7	7	} else if ((oper&0xe0)==0xe0) {
8		sc61860_call(cpustate, READ_OP(cpustate)|((oper&0x1f)<<8));cpustate->icount-=7;
	8	sc61860_call(READ_OP()|((oper&0x1f)<<8));m_icount-=7;
9	9	} else {
10	10	switch(oper) {
11		case 0: sc61860_load_imm(cpustate, I, READ_OP(cpustate));cpustate->icount-=4;break;
12		case 1: sc61860_load_imm(cpustate, J, READ_OP(cpustate));cpustate->icount-=4;break;
13		case 2: sc61860_load_imm(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
14		case 3: sc61860_load_imm(cpustate, B, READ_OP(cpustate));cpustate->icount-=4;break;
15		case 4: sc61860_inc_load_dp(cpustate, XL);cpustate->icount-=6;break;
16		case 5: sc61860_dec_load_dp(cpustate, XL);cpustate->icount-=6;break;
17		case 6: sc61860_inc_load_dp(cpustate, YL);cpustate->icount-=6;break;
18		case 7: sc61860_dec_load_dp(cpustate, YL);cpustate->icount-=6;break;
19		case 8: sc61860_copy(cpustate, READ_RAM(cpustate, I));break;
20		case 9: sc61860_exchange(cpustate, READ_RAM(cpustate, I));break;
21		case 10: sc61860_copy(cpustate, READ_RAM(cpustate, J));break;
22		case 11: sc61860_exchange(cpustate, READ_RAM(cpustate, J));break;
23		case 12: sc61860_add_bcd_a(cpustate);cpustate->icount-=7;break;
24		case 13: sc61860_sub_bcd_a(cpustate);cpustate->icount-=7;break;
25		case 14: sc61860_add_bcd(cpustate);cpustate->icount-=7;break;
26		case 15: sc61860_sub_bcd(cpustate);cpustate->icount-=7;break;
27		case 16: sc61860_load_dp(cpustate);cpustate->icount-=8;break;
28		case 17: sc61860_load_dl(cpustate);cpustate->icount-=5;break;
29		case 18: sc61860_load_imm_p(cpustate, READ_OP(cpustate));cpustate->icount-=4;break;
30		case 19: sc61860_load_imm_q(cpustate, READ_OP(cpustate));cpustate->icount-=4;break;
31		case 20: sc61860_add_word(cpustate);cpustate->icount-=5;break;
32		case 21: sc61860_sub_word(cpustate);cpustate->icount-=5;break;
33		case 24: sc61860_copy_ext(cpustate, READ_RAM(cpustate, I));break;
34		case 25: sc61860_exchange_ext(cpustate, READ_RAM(cpustate, I));break;
35		case 26: sc61860_copy_ext(cpustate, READ_RAM(cpustate, J));break;
36		case 27: sc61860_exchange_ext(cpustate, READ_RAM(cpustate, J));break;
37		case 28: sc61860_shift_right_nibble(cpustate);cpustate->icount-=5;break;
38		case 29: sc61860_shift_left_nibble(cpustate);cpustate->icount-=5;break;
39		case 30: sc61860_fill(cpustate);cpustate->icount-=5;break;
40		case 31: sc61860_fill_ext(cpustate);cpustate->icount-=4;break;
41		case 32: sc61860_store_p(cpustate);cpustate->icount-=2;break;
42		case 33: sc61860_store_q(cpustate);cpustate->icount-=2;break;
43		case 34: sc61860_store_r(cpustate);cpustate->icount-=2;break;
44		case 36: sc61860_inc_load_dp_load(cpustate);cpustate->icount-=7;break;
45		case 37: sc61860_dec_load_dp_load(cpustate);cpustate->icount-=7;break;
46		case 38: sc61860_inc_load_dp_store(cpustate);cpustate->icount-=7;break;
47		case 39: sc61860_dec_load_dp_store(cpustate);cpustate->icount-=7;break;
48		case 40: sc61860_jump_rel_plus(cpustate, !cpustate->zero);cpustate->icount-=4;break;
49		case 41: sc61860_jump_rel_minus(cpustate, !cpustate->zero);cpustate->icount-=4;break;
50		case 42: sc61860_jump_rel_plus(cpustate, !cpustate->carry);cpustate->icount-=4;break;
51		case 43: sc61860_jump_rel_minus(cpustate, !cpustate->carry);cpustate->icount-=4;break;
52		case 44: sc61860_jump_rel_plus(cpustate, TRUE);cpustate->icount-=4;break;
53		case 45: sc61860_jump_rel_minus(cpustate, TRUE);cpustate->icount-=4;break;
54		case 47: sc61860_loop(cpustate);cpustate->icount-=7;break;
55		case 48: sc61860_load_imm_p(cpustate, READ_RAM(cpustate, A));cpustate->icount-=2;break;
56		case 49: sc61860_load_imm_q(cpustate, READ_RAM(cpustate, A));cpustate->icount-=2;break;
57		case 50: sc61860_load_r(cpustate);cpustate->icount-=2;break;
58		case 52: sc61860_push(cpustate);cpustate->icount-=3;break;
59		case 53: sc61860_copy_int(cpustate, READ_RAM(cpustate, I));break;
60		case 55: sc61860_return(cpustate);cpustate->icount-=4;break;
61		case 56: sc61860_jump_rel_plus(cpustate, cpustate->zero);cpustate->icount-=4;break;
62		case 57: sc61860_jump_rel_minus(cpustate, cpustate->zero);cpustate->icount-=4;break;
63		case 58: sc61860_jump_rel_plus(cpustate, cpustate->carry);cpustate->icount-=4;break;
64		case 59: sc61860_jump_rel_minus(cpustate, cpustate->carry);cpustate->icount-=4;break;
65		case 64: sc61860_inc(cpustate, I);cpustate->icount-=4;break;
66		case 65: sc61860_dec(cpustate, I);cpustate->icount-=4;break;
67		case 66: sc61860_inc(cpustate, A);cpustate->icount-=4;break;
68		case 67: sc61860_dec(cpustate, A);cpustate->icount-=4;break;
69		case 68: sc61860_add(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
70		case 69: sc61860_sub(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
71		case 70: sc61860_and(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
72		case 71: sc61860_or(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
73		case 72: sc61860_inc(cpustate, K);cpustate->icount-=4;break;
74		case 73: sc61860_dec(cpustate, K);cpustate->icount-=4;break;
75		case 74: sc61860_inc(cpustate, V);cpustate->icount-=4;break;
76		case 75: sc61860_dec(cpustate, V);cpustate->icount-=4;break;
77		case 76: sc61860_in_a(cpustate);cpustate->icount-=2;break;
78		case 77: /*nopw*/;cpustate->icount-=2;break;
79		case 78: sc61860_wait(cpustate);cpustate->icount-=6;break;
80		case 79: sc61860_wait_x(cpustate, FALSE);cpustate->icount-=1;break;
81		case 80: sc61860_inc_p(cpustate);cpustate->icount-=2;break;
82		case 81: sc61860_dec_p(cpustate);cpustate->icount-=2;break;
83		case 82: sc61860_store_ext(cpustate, A);cpustate->icount-=2;break;
84		case 83: sc61860_store_ext(cpustate, cpustate->p);cpustate->icount-=2;break;
85		case 84: sc61860_load_imm(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=3/*?*/;break; // undocumented
86		case 85: sc61860_load_ext(cpustate, cpustate->p);cpustate->icount-=3;break;
87		case 86: sc61860_load_imm(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=3/*?*/;break; // undocumented
88		case 87: sc61860_load_ext(cpustate, A);cpustate->icount-=3;break;
89		case 88: sc61860_swap(cpustate);cpustate->icount-=2;break;
90		case 89: sc61860_load(cpustate);cpustate->icount-=2;break;
91		case 90: sc61860_rotate_left(cpustate);cpustate->icount-=2;break;
92		case 91: sc61860_pop(cpustate);cpustate->icount-=2;break;
93		case 93: sc61860_out_a(cpustate);cpustate->icount-=3;break;
94		case 95: sc61860_out_f(cpustate);cpustate->icount-=3;break;
95		case 96: sc61860_and(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
96		case 97: sc61860_or(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
97		case 98: sc61860_test(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
98		case 99: sc61860_cmp(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
99		case 100: sc61860_and(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
100		case 101: sc61860_or(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
101		case 102: sc61860_test(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
102		case 103: sc61860_cmp(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
103		case 105: sc61860_execute_table_call(cpustate);cpustate->icount-=3;break;
104		case 107: sc61860_test_special(cpustate);cpustate->icount-=4;break;
105		case 111: sc61860_wait_x(cpustate, TRUE);cpustate->icount-=1;break;
106		case 112: sc61860_add(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
107		case 113: sc61860_sub(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
108		case 116: sc61860_add(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
109		case 117: sc61860_sub(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
110		case 120: sc61860_call(cpustate, READ_OP_ARG_WORD(cpustate));cpustate->icount-=8;break;
111		case 121: sc61860_jump(cpustate, 1);cpustate->icount-=6;break;
112		case 122: sc61860_prepare_table_call(cpustate);cpustate->icount-=9;break;
113		case 124: sc61860_jump(cpustate, !cpustate->zero);cpustate->icount-=6;break;
114		case 125: sc61860_jump(cpustate, !cpustate->carry);cpustate->icount-=6;break;
115		case 126: sc61860_jump(cpustate, cpustate->zero);cpustate->icount-=6;break;
116		case 127: sc61860_jump(cpustate, cpustate->carry);cpustate->icount-=6;break;
117		case 192: sc61860_inc(cpustate, J);cpustate->icount-=4;break;
118		case 193: sc61860_dec(cpustate, J);cpustate->icount-=4;break;
119		case 194: sc61860_inc(cpustate, B);cpustate->icount-=4;break;
120		case 195: sc61860_dec(cpustate, B);cpustate->icount-=4;break;
121		case 196: sc61860_add_carry(cpustate);cpustate->icount-=3;break;
122		case 197: sc61860_sub_carry(cpustate);cpustate->icount-=3;break;
123		case 199: sc61860_cmp(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
124		case 200: sc61860_inc(cpustate, L);cpustate->icount-=4;break;
125		case 201: sc61860_dec(cpustate, L);cpustate->icount-=4;break;
126		case 202: sc61860_inc(cpustate, W);cpustate->icount-=4;break;
127		case 203: sc61860_dec(cpustate, W);cpustate->icount-=4;break;
128		case 204: sc61860_in_b(cpustate);cpustate->icount-=2;break;
129		case 206: /*nopt*/;cpustate->icount-=3;break;
130		case 208: sc61860_set_carry(cpustate);cpustate->icount-=2;break;
131		case 209: sc61860_reset_carry(cpustate);cpustate->icount-=4;break;
132		case 210: sc61860_rotate_right(cpustate);cpustate->icount-=2;break;
133		case 212: sc61860_and_ext(cpustate);cpustate->icount-=6;break;
134		case 213: sc61860_or_ext(cpustate);cpustate->icount-=6;break;
135		case 214: sc61860_test_ext(cpustate);cpustate->icount-=6;break;
136		case 216: sc61860_leave(cpustate);cpustate->icount-=2;break;
137		case 218: sc61860_exam(cpustate, A, B);cpustate->icount-=3;break;
138		case 219: sc61860_exam(cpustate, A, cpustate->p);cpustate->icount-=3;break;
139		case 221: sc61860_out_b(cpustate);cpustate->icount-=2;break;
140		case 223: sc61860_out_c(cpustate);cpustate->icount-=2;break;
141		default: logerror("sc61860 illegal opcode at %.4x %.2x\n",cpustate->pc-1, oper);
	11	case 0: sc61860_load_imm(I, READ_OP());m_icount-=4;break;
	12	case 1: sc61860_load_imm(J, READ_OP());m_icount-=4;break;
	13	case 2: sc61860_load_imm(A, READ_OP());m_icount-=4;break;
	14	case 3: sc61860_load_imm(B, READ_OP());m_icount-=4;break;
	15	case 4: sc61860_inc_load_dp(XL);m_icount-=6;break;
	16	case 5: sc61860_dec_load_dp(XL);m_icount-=6;break;
	17	case 6: sc61860_inc_load_dp(YL);m_icount-=6;break;
	18	case 7: sc61860_dec_load_dp(YL);m_icount-=6;break;
	19	case 8: sc61860_copy(READ_RAM(I));break;
	20	case 9: sc61860_exchange(READ_RAM(I));break;
	21	case 10: sc61860_copy(READ_RAM(J));break;
	22	case 11: sc61860_exchange(READ_RAM(J));break;
	23	case 12: sc61860_add_bcd_a();m_icount-=7;break;
	24	case 13: sc61860_sub_bcd_a();m_icount-=7;break;
	25	case 14: sc61860_add_bcd();m_icount-=7;break;
	26	case 15: sc61860_sub_bcd();m_icount-=7;break;
	27	case 16: sc61860_load_dp();m_icount-=8;break;
	28	case 17: sc61860_load_dl();m_icount-=5;break;
	29	case 18: sc61860_load_imm_p(READ_OP());m_icount-=4;break;
	30	case 19: sc61860_load_imm_q(READ_OP());m_icount-=4;break;
	31	case 20: sc61860_add_word();m_icount-=5;break;
	32	case 21: sc61860_sub_word();m_icount-=5;break;
	33	case 24: sc61860_copy_ext(READ_RAM(I));break;
	34	case 25: sc61860_exchange_ext(READ_RAM(I));break;
	35	case 26: sc61860_copy_ext(READ_RAM(J));break;
	36	case 27: sc61860_exchange_ext(READ_RAM(J));break;
	37	case 28: sc61860_shift_right_nibble();m_icount-=5;break;
	38	case 29: sc61860_shift_left_nibble();m_icount-=5;break;
	39	case 30: sc61860_fill();m_icount-=5;break;
	40	case 31: sc61860_fill_ext();m_icount-=4;break;
	41	case 32: sc61860_store_p();m_icount-=2;break;
	42	case 33: sc61860_store_q();m_icount-=2;break;
	43	case 34: sc61860_store_r();m_icount-=2;break;
	44	case 36: sc61860_inc_load_dp_load();m_icount-=7;break;
	45	case 37: sc61860_dec_load_dp_load();m_icount-=7;break;
	46	case 38: sc61860_inc_load_dp_store();m_icount-=7;break;
	47	case 39: sc61860_dec_load_dp_store();m_icount-=7;break;
	48	case 40: sc61860_jump_rel_plus(!m_zero);m_icount-=4;break;
	49	case 41: sc61860_jump_rel_minus(!m_zero);m_icount-=4;break;
	50	case 42: sc61860_jump_rel_plus(!m_carry);m_icount-=4;break;
	51	case 43: sc61860_jump_rel_minus(!m_carry);m_icount-=4;break;
	52	case 44: sc61860_jump_rel_plus(TRUE);m_icount-=4;break;
	53	case 45: sc61860_jump_rel_minus(TRUE);m_icount-=4;break;
	54	case 47: sc61860_loop();m_icount-=7;break;
	55	case 48: sc61860_load_imm_p(READ_RAM(A));m_icount-=2;break;
	56	case 49: sc61860_load_imm_q(READ_RAM(A));m_icount-=2;break;
	57	case 50: sc61860_load_r();m_icount-=2;break;
	58	case 52: sc61860_push();m_icount-=3;break;
	59	case 53: sc61860_copy_int(READ_RAM(I));break;
	60	case 55: sc61860_return();m_icount-=4;break;
	61	case 56: sc61860_jump_rel_plus(m_zero);m_icount-=4;break;
	62	case 57: sc61860_jump_rel_minus(m_zero);m_icount-=4;break;
	63	case 58: sc61860_jump_rel_plus(m_carry);m_icount-=4;break;
	64	case 59: sc61860_jump_rel_minus(m_carry);m_icount-=4;break;
	65	case 64: sc61860_inc(I);m_icount-=4;break;
	66	case 65: sc61860_dec(I);m_icount-=4;break;
	67	case 66: sc61860_inc(A);m_icount-=4;break;
	68	case 67: sc61860_dec(A);m_icount-=4;break;
	69	case 68: sc61860_add(m_p, READ_RAM(A));m_icount-=3;break;
	70	case 69: sc61860_sub(m_p, READ_RAM(A));m_icount-=3;break;
	71	case 70: sc61860_and(m_p, READ_RAM(A));m_icount-=3;break;
	72	case 71: sc61860_or(m_p, READ_RAM(A));m_icount-=3;break;
	73	case 72: sc61860_inc(K);m_icount-=4;break;
	74	case 73: sc61860_dec(K);m_icount-=4;break;
	75	case 74: sc61860_inc(V);m_icount-=4;break;
	76	case 75: sc61860_dec(V);m_icount-=4;break;
	77	case 76: sc61860_in_a();m_icount-=2;break;
	78	case 77: /*nopw*/;m_icount-=2;break;
	79	case 78: sc61860_wait();m_icount-=6;break;
	80	case 79: sc61860_wait_x(FALSE);m_icount-=1;break;
	81	case 80: sc61860_inc_p();m_icount-=2;break;
	82	case 81: sc61860_dec_p();m_icount-=2;break;
	83	case 82: sc61860_store_ext(A);m_icount-=2;break;
	84	case 83: sc61860_store_ext(m_p);m_icount-=2;break;
	85	case 84: sc61860_load_imm(m_p, READ_OP());m_icount-=3/*?*/;break; // undocumented
	86	case 85: sc61860_load_ext(m_p);m_icount-=3;break;
	87	case 86: sc61860_load_imm(m_p, READ_OP());m_icount-=3/*?*/;break; // undocumented
	88	case 87: sc61860_load_ext(A);m_icount-=3;break;
	89	case 88: sc61860_swap();m_icount-=2;break;
	90	case 89: sc61860_load();m_icount-=2;break;
	91	case 90: sc61860_rotate_left();m_icount-=2;break;
	92	case 91: sc61860_pop();m_icount-=2;break;
	93	case 93: sc61860_out_a();m_icount-=3;break;
	94	case 95: sc61860_out_f();m_icount-=3;break;
	95	case 96: sc61860_and(m_p, READ_OP());m_icount-=4;break;
	96	case 97: sc61860_or(m_p, READ_OP());m_icount-=4;break;
	97	case 98: sc61860_test(m_p, READ_OP());m_icount-=4;break;
	98	case 99: sc61860_cmp(m_p, READ_OP());m_icount-=4;break;
	99	case 100: sc61860_and(A, READ_OP());m_icount-=4;break;
	100	case 101: sc61860_or(A, READ_OP());m_icount-=4;break;
	101	case 102: sc61860_test(A, READ_OP());m_icount-=4;break;
	102	case 103: sc61860_cmp(A, READ_OP());m_icount-=4;break;
	103	case 105: sc61860_execute_table_call();m_icount-=3;break;
	104	case 107: sc61860_test_special();m_icount-=4;break;
	105	case 111: sc61860_wait_x(TRUE);m_icount-=1;break;
	106	case 112: sc61860_add(m_p, READ_OP());m_icount-=4;break;
	107	case 113: sc61860_sub(m_p, READ_OP());m_icount-=4;break;
	108	case 116: sc61860_add(A, READ_OP());m_icount-=4;break;
	109	case 117: sc61860_sub(A, READ_OP());m_icount-=4;break;
	110	case 120: sc61860_call(READ_OP_ARG_WORD());m_icount-=8;break;
	111	case 121: sc61860_jump(1);m_icount-=6;break;
	112	case 122: sc61860_prepare_table_call();m_icount-=9;break;
	113	case 124: sc61860_jump(!m_zero);m_icount-=6;break;
	114	case 125: sc61860_jump(!m_carry);m_icount-=6;break;
	115	case 126: sc61860_jump(m_zero);m_icount-=6;break;
	116	case 127: sc61860_jump(m_carry);m_icount-=6;break;
	117	case 192: sc61860_inc(J);m_icount-=4;break;
	118	case 193: sc61860_dec(J);m_icount-=4;break;
	119	case 194: sc61860_inc(B);m_icount-=4;break;
	120	case 195: sc61860_dec(B);m_icount-=4;break;
	121	case 196: sc61860_add_carry();m_icount-=3;break;
	122	case 197: sc61860_sub_carry();m_icount-=3;break;
	123	case 199: sc61860_cmp(m_p, READ_RAM(A));m_icount-=3;break;
	124	case 200: sc61860_inc(L);m_icount-=4;break;
	125	case 201: sc61860_dec(L);m_icount-=4;break;
	126	case 202: sc61860_inc(W);m_icount-=4;break;
	127	case 203: sc61860_dec(W);m_icount-=4;break;
	128	case 204: sc61860_in_b();m_icount-=2;break;
	129	case 206: /*nopt*/;m_icount-=3;break;
	130	case 208: sc61860_set_carry();m_icount-=2;break;
	131	case 209: sc61860_reset_carry();m_icount-=4;break;
	132	case 210: sc61860_rotate_right();m_icount-=2;break;
	133	case 212: sc61860_and_ext();m_icount-=6;break;
	134	case 213: sc61860_or_ext();m_icount-=6;break;
	135	case 214: sc61860_test_ext();m_icount-=6;break;
	136	case 216: sc61860_leave();m_icount-=2;break;
	137	case 218: sc61860_exam(A, B);m_icount-=3;break;
	138	case 219: sc61860_exam(A, m_p);m_icount-=3;break;
	139	case 221: sc61860_out_b();m_icount-=2;break;
	140	case 223: sc61860_out_c();m_icount-=2;break;
	141	default: logerror("sc61860 illegal opcode at %.4x %.2x\n",m_pc-1, oper);
142	142	}
143	143	}
144	144	}

trunk/src/emu/cpu/sc61860/sc61860.h

r26784	r26785
54	54	};
55	55
56	56
57		struct sc61860_cpu_core
	57	#define MCFG_SC61860_CONFIG(_reset, _brk, _x, _ina, _outa, _inb, _outb, _outc) \
	58	sc61860_device::set_reset_cb(*device, DEVCB2_##_reset); \
	59	sc61860_device::set_brk_cb(*device, DEVCB2_##_brk); \
	60	sc61860_device::set_x_cb(*device, DEVCB2_##_x); \
	61	sc61860_device::set_ina_cb(*device, DEVCB2_##_ina); \
	62	sc61860_device::set_outa_cb(*device, DEVCB2_##_outa); \
	63	sc61860_device::set_inb_cb(*device, DEVCB2_##_inb); \
	64	sc61860_device::set_outb_cb(*device, DEVCB2_##_outb); \
	65	sc61860_device::set_outc_cb(*device, DEVCB2_##_outc);
	66
	67
	68	class sc61860_device : public cpu_device
58	69	{
59		devcb_read_line reset;
60		devcb_read_line brk;
61		devcb_read_line x;
62		devcb_read8 ina;
63		devcb_write8 outa;
64		devcb_read8 inb;
65		devcb_write8 outb;
66		devcb_write8 outc;
	70	public:
	71	// construction/destruction
	72	sc61860_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	73
	74	// static configuration helpers
	75	template<class _Object> static devcb2_base &set_reset_cb(device_t &device, _Object object) { return downcast<sc61860_device &>(device).m_reset.set_callback(object); }
	76	template<class _Object> static devcb2_base &set_brk_cb(device_t &device, _Object object) { return downcast<sc61860_device &>(device).m_brk.set_callback(object); }
	77	template<class _Object> static devcb2_base &set_x_cb(device_t &device, _Object object) { return downcast<sc61860_device &>(device).m_x.set_callback(object); }
	78	template<class _Object> static devcb2_base &set_ina_cb(device_t &device, _Object object) { return downcast<sc61860_device &>(device).m_ina.set_callback(object); }
	79	template<class _Object> static devcb2_base &set_outa_cb(device_t &device, _Object object) { return downcast<sc61860_device &>(device).m_outa.set_callback(object); }
	80	template<class _Object> static devcb2_base &set_inb_cb(device_t &device, _Object object) { return downcast<sc61860_device &>(device).m_inb.set_callback(object); }
	81	template<class _Object> static devcb2_base &set_outb_cb(device_t &device, _Object object) { return downcast<sc61860_device &>(device).m_outb.set_callback(object); }
	82	template<class _Object> static devcb2_base &set_outc_cb(device_t &device, _Object object) { return downcast<sc61860_device &>(device).m_outc.set_callback(object); }
	83
	84	/* this is though for power on/off of the sharps */
	85	UINT8 *internal_ram();
	86
	87	TIMER_CALLBACK_MEMBER(sc61860_2ms_tick);
	88
	89	protected:
	90	// device-level overrides
	91	virtual void device_start();
	92	virtual void device_reset();
	93
	94	// device_execute_interface overrides
	95	virtual UINT32 execute_min_cycles() const { return 2; }
	96	virtual UINT32 execute_max_cycles() const { return 4; }
	97	virtual UINT32 execute_input_lines() const { return 0; }
	98	virtual void execute_run();
	99
	100	// device_memory_interface overrides
	101	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
	102
	103	// device_state_interface overrides
	104	virtual void state_import(const device_state_entry &entry);
	105	virtual void state_export(const device_state_entry &entry);
	106	void state_string_export(const device_state_entry &entry, astring &string);
	107
	108	// device_disasm_interface overrides
	109	virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
	110	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
	111	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	112
	113	private:
	114	address_space_config m_program_config;
	115
	116	devcb2_read_line m_reset;
	117	devcb2_read_line m_brk;
	118	devcb2_read_line m_x;
	119	devcb2_read8 m_ina;
	120	devcb2_write8 m_outa;
	121	devcb2_read8 m_inb;
	122	devcb2_write8 m_outb;
	123	devcb2_write8 m_outc;
	124
	125	UINT8 m_p, m_q, m_r; //7 bits only?
	126
	127	UINT8 m_c;        // port c, used for HLT.
	128	UINT8 m_d, m_h;
	129	UINT16 m_oldpc, m_pc, m_dp;
	130
	131	int m_carry, m_zero;
	132
	133	struct { int t2ms, t512ms; int count; } m_timer;
	134
	135	address_space *m_program;
	136	direct_read_data *m_direct;
	137	int m_icount;
	138	UINT8 m_ram[0x100]; // internal special ram, should be 0x60, 0x100 to avoid memory corruption for now
	139
	140	UINT32 m_debugger_temp;
	141
	142	inline UINT8 READ_OP();
	143	inline UINT8 READ_OP_ARG();
	144	inline UINT16 READ_OP_ARG_WORD();
	145	inline UINT8 READ_BYTE(UINT16 adr);
	146	inline void WRITE_BYTE(UINT16 a, UINT8 v);
	147	inline UINT8 READ_RAM(int r);
	148	inline void WRITE_RAM(int r, UINT8 v);
	149	inline void PUSH(UINT8 v);
	150	inline UINT8 POP();
	151	inline void sc61860_load_imm(int r, UINT8 v);
	152	inline void sc61860_load();
	153	inline void sc61860_load_imm_p(UINT8 v);
	154	inline void sc61860_load_imm_q(UINT8 v);
	155	inline void sc61860_load_r();
	156	inline void sc61860_load_ext(int r);
	157	inline void sc61860_load_dp();
	158	inline void sc61860_load_dl();
	159	inline void sc61860_store_p();
	160	inline void sc61860_store_q();
	161	inline void sc61860_store_r();
	162	inline void sc61860_store_ext(int r);
	163	inline void sc61860_exam(int a, int b);
	164	inline void sc61860_test(int reg, UINT8 value);
	165	inline void sc61860_test_ext();
	166	inline void sc61860_and(int reg, UINT8 value);
	167	inline void sc61860_and_ext();
	168	inline void sc61860_or(int reg, UINT8 value);
	169	inline void sc61860_or_ext();
	170	inline void sc61860_rotate_right();
	171	inline void sc61860_rotate_left();
	172	inline void sc61860_swap();
	173	inline void sc61860_inc(int reg);
	174	inline void sc61860_inc_p();
	175	inline void sc61860_dec(int reg);
	176	inline void sc61860_dec_p();
	177	inline void sc61860_add(int reg, UINT8 value);
	178	inline void sc61860_add_carry();
	179	inline void sc61860_add_word();
	180	inline void sc61860_sub(int reg, UINT8 value);
	181	inline void sc61860_sub_carry();
	182	inline void sc61860_sub_word();
	183	inline void sc61860_cmp(int reg, UINT8 value);
	184	inline void sc61860_pop();
	185	inline void sc61860_push();
	186	inline void sc61860_prepare_table_call();
	187	inline void sc61860_execute_table_call();
	188	inline void sc61860_call(UINT16 adr);
	189	inline void sc61860_return();
	190	inline void sc61860_jump(int yes);
	191	inline void sc61860_jump_rel_plus(int yes);
	192	inline void sc61860_jump_rel_minus(int yes);
	193	inline void sc61860_loop();
	194	inline void sc61860_leave();
	195	inline void sc61860_wait();
	196	inline void sc61860_set_carry();
	197	inline void sc61860_reset_carry();
	198	inline void sc61860_out_a();
	199	inline void sc61860_out_b();
	200	inline void sc61860_out_f();
	201	inline void sc61860_out_c();
	202	inline void sc61860_in_a();
	203	inline void sc61860_in_b();
	204	inline void sc61860_test_special();
	205	inline void sc61860_add_bcd_a();
	206	inline void sc61860_add_bcd();
	207	inline void sc61860_sub_bcd_a();
	208	inline void sc61860_sub_bcd();
	209	inline void sc61860_shift_left_nibble();
	210	inline void sc61860_shift_right_nibble();
	211	inline void sc61860_inc_load_dp(int reg);
	212	inline void sc61860_dec_load_dp(int reg);
	213	inline void sc61860_inc_load_dp_load();
	214	inline void sc61860_dec_load_dp_load();
	215	inline void sc61860_inc_load_dp_store();
	216	inline void sc61860_dec_load_dp_store();
	217	inline void sc61860_fill();
	218	inline void sc61860_fill_ext();
	219	inline void sc61860_copy(int count);
	220	inline void sc61860_copy_ext(int count);
	221	inline void sc61860_copy_int(int count);
	222	inline void sc61860_exchange(int count);
	223	inline void sc61860_exchange_ext(int count);
	224	inline void sc61860_wait_x(int level);
	225	void sc61860_instruction();
	226
67	227	};
68	228
69		CPU_DISASSEMBLE( sc61860 );
70	229
71		/* this is though for power on/off of the sharps */
72		UINT8 *sc61860_internal_ram(device_t *device);
	230	extern const device_type SC61860;
73	231
74		DECLARE_LEGACY_CPU_DEVICE(SC61860, sc61860);
75	232
76	233	#endif /* __SC61860_H__ */

trunk/src/emu/cpu/sc61860/scops.c

r26784	r26785
26	26	*
27	27	*****************************************************************************/
28	28
29		INLINE UINT8 READ_OP(sc61860_state *cpustate)
	29	UINT8 sc61860_device::READ_OP()
30	30	{
31		return cpustate->direct->read_decrypted_byte(cpustate->pc++);
	31	return m_direct->read_decrypted_byte(m_pc++);
32	32	}
33	33
34		INLINE UINT8 READ_OP_ARG(sc61860_state *cpustate)
	34	UINT8 sc61860_device::READ_OP_ARG()
35	35	{
36		return cpustate->direct->read_raw_byte(cpustate->pc++);
	36	return m_direct->read_raw_byte(m_pc++);
37	37	}
38	38
39		INLINE UINT16 READ_OP_ARG_WORD(sc61860_state *cpustate)
	39	UINT16 sc61860_device::READ_OP_ARG_WORD()
40	40	{
41		UINT16 t=cpustate->direct->read_decrypted_byte(cpustate->pc++)<<8;
42		t|=cpustate->direct->read_decrypted_byte(cpustate->pc++);
	41	UINT16 t=m_direct->read_decrypted_byte(m_pc++)<<8;
	42	t|=m_direct->read_decrypted_byte(m_pc++);
43	43	return t;
44	44	}
45	45
46		INLINE UINT8 READ_BYTE(sc61860_state *cpustate, UINT16 adr)
	46	UINT8 sc61860_device::READ_BYTE(UINT16 adr)
47	47	{
48		return cpustate->program->read_byte(adr);
	48	return m_program->read_byte(adr);
49	49	}
50	50
51		INLINE void WRITE_BYTE(sc61860_state *cpustate, UINT16 a, UINT8 v)
	51	void sc61860_device::WRITE_BYTE(UINT16 a, UINT8 v)
52	52	{
53		cpustate->program->write_byte(a, v);
	53	m_program->write_byte(a, v);
54	54	}
55	55
56		INLINE UINT8 READ_RAM(sc61860_state *cpustate, int r)
	56	UINT8 sc61860_device::READ_RAM(int r)
57	57	{
58		return cpustate->ram[r];
	58	return m_ram[r];
59	59	}
60	60
61		INLINE void WRITE_RAM(sc61860_state *cpustate, int r, UINT8 v)
	61	void sc61860_device::WRITE_RAM(int r, UINT8 v)
62	62	{
63		cpustate->ram[r] = v;
	63	m_ram[r] = v;
64	64	}
65	65
66		INLINE void PUSH(sc61860_state *cpustate, UINT8 v)
	66	void sc61860_device::PUSH(UINT8 v)
67	67	{
68		cpustate->r--;
69		WRITE_RAM(cpustate, cpustate->r, v);
	68	m_r--;
	69	WRITE_RAM(m_r, v);
70	70	}
71	71
72		INLINE UINT8 POP(sc61860_state *cpustate)
	72	UINT8 sc61860_device::POP()
73	73	{
74		UINT8 t = READ_RAM(cpustate, cpustate->r);
75		cpustate->r++;
	74	UINT8 t = READ_RAM(m_r);
	75	m_r++;
76	76	return t;
77	77	}
78	78
79		INLINE void sc61860_load_imm(sc61860_state *cpustate, int r, UINT8 v)
	79	void sc61860_device::sc61860_load_imm(int r, UINT8 v)
80	80	{
81		WRITE_RAM(cpustate, r, v);
	81	WRITE_RAM(r, v);
82	82	}
83	83
84		INLINE void sc61860_load(sc61860_state *cpustate)
	84	void sc61860_device::sc61860_load()
85	85	{
86		WRITE_RAM(cpustate, A, READ_RAM(cpustate, cpustate->p));
	86	WRITE_RAM(A, READ_RAM(m_p));
87	87	}
88	88
89		INLINE void sc61860_load_imm_p(sc61860_state *cpustate, UINT8 v)
	89	void sc61860_device::sc61860_load_imm_p(UINT8 v)
90	90	{
91		cpustate->p=v&0x7f;
	91	m_p=v&0x7f;
92	92	}
93	93
94		INLINE void sc61860_load_imm_q(sc61860_state *cpustate, UINT8 v)
	94	void sc61860_device::sc61860_load_imm_q(UINT8 v)
95	95	{
96		cpustate->q=v&0x7f;
	96	m_q=v&0x7f;
97	97	}
98	98
99		INLINE void sc61860_load_r(sc61860_state *cpustate)
	99	void sc61860_device::sc61860_load_r()
100	100	{
101		cpustate->r = READ_RAM(cpustate, A) & 0x7f;
	101	m_r = READ_RAM(A) & 0x7f;
102	102	}
103	103
104		INLINE void sc61860_load_ext(sc61860_state *cpustate, int r)
	104	void sc61860_device::sc61860_load_ext(int r)
105	105	{
106		WRITE_RAM(cpustate, r, READ_BYTE(cpustate, cpustate->dp));
	106	WRITE_RAM(r, READ_BYTE(m_dp));
107	107	}
108	108
109		INLINE void sc61860_load_dp(sc61860_state *cpustate)
	109	void sc61860_device::sc61860_load_dp()
110	110	{
111		cpustate->dp=READ_OP_ARG_WORD(cpustate);
	111	m_dp=READ_OP_ARG_WORD();
112	112	}
113	113
114		INLINE void sc61860_load_dl(sc61860_state *cpustate)
	114	void sc61860_device::sc61860_load_dl()
115	115	{
116		cpustate->dp=(cpustate->dp&~0xff)|READ_OP_ARG(cpustate);
	116	m_dp=(m_dp&~0xff)|READ_OP_ARG();
117	117	}
118	118
119		INLINE void sc61860_store_p(sc61860_state *cpustate)
	119	void sc61860_device::sc61860_store_p()
120	120	{
121		WRITE_RAM(cpustate, A, cpustate->p);
	121	WRITE_RAM(A, m_p);
122	122	}
123	123
124		INLINE void sc61860_store_q(sc61860_state *cpustate)
	124	void sc61860_device::sc61860_store_q()
125	125	{
126		WRITE_RAM(cpustate, A, cpustate->q);
	126	WRITE_RAM(A, m_q);
127	127	}
128	128
129		INLINE void sc61860_store_r(sc61860_state *cpustate)
	129	void sc61860_device::sc61860_store_r()
130	130	{
131		WRITE_RAM(cpustate, A, cpustate->r);
	131	WRITE_RAM(A, m_r);
132	132	}
133	133
134		INLINE void sc61860_store_ext(sc61860_state *cpustate, int r)
	134	void sc61860_device::sc61860_store_ext(int r)
135	135	{
136		WRITE_BYTE(cpustate, cpustate->dp, READ_RAM(cpustate, r));
	136	WRITE_BYTE(m_dp, READ_RAM(r));
137	137	}
138	138
139		INLINE void sc61860_exam(sc61860_state *cpustate, int a, int b)
	139	void sc61860_device::sc61860_exam(int a, int b)
140	140	{
141		UINT8 t = READ_RAM(cpustate, a);
142		WRITE_RAM(cpustate, a, READ_RAM(cpustate, b));
143		WRITE_RAM(cpustate, b, t);
	141	UINT8 t = READ_RAM(a);
	142	WRITE_RAM(a, READ_RAM(b));
	143	WRITE_RAM(b, t);
144	144	}
145	145
146		INLINE void sc61860_test(sc61860_state *cpustate, int reg, UINT8 value)
	146	void sc61860_device::sc61860_test(int reg, UINT8 value)
147	147	{
148		cpustate->zero=(READ_RAM(cpustate, reg) & value)==0;
	148	m_zero=(READ_RAM(reg) & value)==0;
149	149	}
150	150
151		INLINE void sc61860_test_ext(sc61860_state *cpustate)
	151	void sc61860_device::sc61860_test_ext()
152	152	{
153		cpustate->zero=(READ_BYTE(cpustate, cpustate->dp)&READ_OP_ARG(cpustate))==0;
	153	m_zero=(READ_BYTE(m_dp)&READ_OP_ARG())==0;
154	154	}
155	155
156		INLINE void sc61860_and(sc61860_state *cpustate, int reg, UINT8 value)
	156	void sc61860_device::sc61860_and(int reg, UINT8 value)
157	157	{
158		UINT8 t = READ_RAM(cpustate, reg) & value;
159		WRITE_RAM(cpustate, reg,  t);
160		cpustate->zero=t==0;
	158	UINT8 t = READ_RAM(reg) & value;
	159	WRITE_RAM(reg,  t);
	160	m_zero=t==0;
161	161	}
162	162
163		INLINE void sc61860_and_ext(sc61860_state *cpustate)
	163	void sc61860_device::sc61860_and_ext()
164	164	{
165		UINT8 t = READ_BYTE(cpustate, cpustate->dp) & READ_OP_ARG(cpustate);
166		cpustate->zero=t==0;
167		WRITE_BYTE(cpustate, cpustate->dp, t);
	165	UINT8 t = READ_BYTE(m_dp) & READ_OP_ARG();
	166	m_zero=t==0;
	167	WRITE_BYTE(m_dp, t);
168	168	}
169	169
170		INLINE void sc61860_or(sc61860_state *cpustate, int reg, UINT8 value)
	170	void sc61860_device::sc61860_or(int reg, UINT8 value)
171	171	{
172		UINT8 t = READ_RAM(cpustate, reg) | value;
173		WRITE_RAM(cpustate, reg, t);
174		cpustate->zero=t==0;
	172	UINT8 t = READ_RAM(reg) | value;
	173	WRITE_RAM(reg, t);
	174	m_zero=t==0;
175	175	}
176	176
177		INLINE void sc61860_or_ext(sc61860_state *cpustate)
	177	void sc61860_device::sc61860_or_ext()
178	178	{
179		UINT8 t=READ_BYTE(cpustate, cpustate->dp)|READ_OP_ARG(cpustate);
180		cpustate->zero=t==0;
181		WRITE_BYTE(cpustate, cpustate->dp, t);
	179	UINT8 t=READ_BYTE(m_dp)|READ_OP_ARG();
	180	m_zero=t==0;
	181	WRITE_BYTE(m_dp, t);
182	182	}
183	183
184		INLINE void sc61860_rotate_right(sc61860_state *cpustate)
	184	void sc61860_device::sc61860_rotate_right()
185	185	{
186		int t = READ_RAM(cpustate, A);
187		if (cpustate->carry) t|=0x100;
188		cpustate->carry=t&1;
189		WRITE_RAM(cpustate, A, t>>1);
	186	int t = READ_RAM(A);
	187	if (m_carry) t|=0x100;
	188	m_carry=t&1;
	189	WRITE_RAM(A, t>>1);
190	190	}
191	191
192		INLINE void sc61860_rotate_left(sc61860_state *cpustate)
	192	void sc61860_device::sc61860_rotate_left()
193	193	{
194		int t = READ_RAM(cpustate, A) << 1;
195		if (cpustate->carry) t|=1;
196		cpustate->carry=t&0x100;
197		WRITE_RAM(cpustate, A, t);
	194	int t = READ_RAM(A) << 1;
	195	if (m_carry) t|=1;
	196	m_carry=t&0x100;
	197	WRITE_RAM(A, t);
198	198	}
199	199
200		INLINE void sc61860_swap(sc61860_state *cpustate)
	200	void sc61860_device::sc61860_swap()
201	201	{
202		int t = READ_RAM(cpustate, A);
203		WRITE_RAM(cpustate, A, (t<<4)|((t>>4)&0xf));
	202	int t = READ_RAM(A);
	203	WRITE_RAM(A, (t<<4)|((t>>4)&0xf));
204	204	}
205	205
206	206	// q=reg sideeffect
207		INLINE void sc61860_inc(sc61860_state *cpustate, int reg)
	207	void sc61860_device::sc61860_inc(int reg)
208	208	{
209		UINT8 t = READ_RAM(cpustate, reg) + 1;
210		cpustate->q=reg;
211		WRITE_RAM(cpustate, reg, t);
212		cpustate->zero=t==0;
213		cpustate->carry=t==0;
	209	UINT8 t = READ_RAM(reg) + 1;
	210	m_q=reg;
	211	WRITE_RAM(reg, t);
	212	m_zero=t==0;
	213	m_carry=t==0;
214	214	}
215	215
216		INLINE void sc61860_inc_p(sc61860_state *cpustate)
	216	void sc61860_device::sc61860_inc_p()
217	217	{
218		cpustate->p++;
	218	m_p++;
219	219	}
220	220
221	221	// q=reg sideeffect
222		INLINE void sc61860_dec(sc61860_state *cpustate, int reg)
	222	void sc61860_device::sc61860_dec(int reg)
223	223	{
224		UINT8 t = READ_RAM(cpustate, reg) - 1;
225		cpustate->q=reg;
226		WRITE_RAM(cpustate, reg, t);
227		cpustate->zero=t==0;
228		cpustate->carry=t==0xff;
	224	UINT8 t = READ_RAM(reg) - 1;
	225	m_q=reg;
	226	WRITE_RAM(reg, t);
	227	m_zero=t==0;
	228	m_carry=t==0xff;
229	229	}
230	230
231		INLINE void sc61860_dec_p(sc61860_state *cpustate)
	231	void sc61860_device::sc61860_dec_p()
232	232	{
233		cpustate->p--;
	233	m_p--;
234	234	}
235	235
236		INLINE void sc61860_add(sc61860_state *cpustate, int reg, UINT8 value)
	236	void sc61860_device::sc61860_add(int reg, UINT8 value)
237	237	{
238		int t = READ_RAM(cpustate, reg) + value;
239		WRITE_RAM(cpustate, reg, t);
240		cpustate->zero=(t&0xff)==0;
241		cpustate->carry=t>=0x100;
	238	int t = READ_RAM(reg) + value;
	239	WRITE_RAM(reg, t);
	240	m_zero=(t&0xff)==0;
	241	m_carry=t>=0x100;
242	242	}
243	243
244		INLINE void sc61860_add_carry(sc61860_state *cpustate)
	244	void sc61860_device::sc61860_add_carry()
245	245	{
246		int t = READ_RAM(cpustate, cpustate->p) + READ_RAM(cpustate, A);
247		if (cpustate->carry) t++;
248		WRITE_RAM(cpustate, cpustate->p, t);
249		cpustate->zero=(t&0xff)==0;
250		cpustate->carry=t>=0x100;
	246	int t = READ_RAM(m_p) + READ_RAM(A);
	247	if (m_carry) t++;
	248	WRITE_RAM(m_p, t);
	249	m_zero=(t&0xff)==0;
	250	m_carry=t>=0x100;
251	251	}
252	252
253	253	// p++ sideeffect
254		INLINE void sc61860_add_word(sc61860_state *cpustate)
	254	void sc61860_device::sc61860_add_word()
255	255	{
256		int t = READ_RAM(cpustate, cpustate->p) + READ_RAM(cpustate, A), t2;
257		WRITE_RAM(cpustate, cpustate->p, t);
258		cpustate->p++;
259		t2 = READ_RAM(cpustate, cpustate->p) + READ_RAM(cpustate, B);
	256	int t = READ_RAM(m_p) + READ_RAM(A), t2;
	257	WRITE_RAM(m_p, t);
	258	m_p++;
	259	t2 = READ_RAM(m_p) + READ_RAM(B);
260	260	if (t>=0x100) t2++;
261		WRITE_RAM(cpustate, cpustate->p, t2);
262		cpustate->zero=(t2&0xff)==0 &&(t&0xff)==0;
263		cpustate->carry=t2>=0x100;
	261	WRITE_RAM(m_p, t2);
	262	m_zero=(t2&0xff)==0 &&(t&0xff)==0;
	263	m_carry=t2>=0x100;
264	264	}
265	265
266	266
267		INLINE void sc61860_sub(sc61860_state *cpustate, int reg, UINT8 value)
	267	void sc61860_device::sc61860_sub(int reg, UINT8 value)
268	268	{
269		int t = READ_RAM(cpustate, reg) - value;
270		WRITE_RAM(cpustate, reg, t);
271		cpustate->zero=(t&0xff)==0;
272		cpustate->carry=t<0;
	269	int t = READ_RAM(reg) - value;
	270	WRITE_RAM(reg, t);
	271	m_zero=(t&0xff)==0;
	272	m_carry=t<0;
273	273	}
274	274
275		INLINE void sc61860_sub_carry(sc61860_state *cpustate)
	275	void sc61860_device::sc61860_sub_carry()
276	276	{
277		int t = READ_RAM(cpustate, cpustate->p) - READ_RAM(cpustate, A);
278		if (cpustate->carry) t--;
279		WRITE_RAM(cpustate, cpustate->p, t);
280		cpustate->zero=(t&0xff)==0;
281		cpustate->carry=t<0;
	277	int t = READ_RAM(m_p) - READ_RAM(A);
	278	if (m_carry) t--;
	279	WRITE_RAM(m_p, t);
	280	m_zero=(t&0xff)==0;
	281	m_carry=t<0;
282	282	}
283	283
284	284
285	285	// p++ sideeffect
286		INLINE void sc61860_sub_word(sc61860_state *cpustate)
	286	void sc61860_device::sc61860_sub_word()
287	287	{
288		int t = READ_RAM(cpustate, cpustate->p) - READ_RAM(cpustate, A), t2;
289		WRITE_RAM(cpustate, cpustate->p, t);
290		cpustate->p++;
291		t2 = READ_RAM(cpustate, cpustate->p) - READ_RAM(cpustate, B);
	288	int t = READ_RAM(m_p) - READ_RAM(A), t2;
	289	WRITE_RAM(m_p, t);
	290	m_p++;
	291	t2 = READ_RAM(m_p) - READ_RAM(B);
292	292	if (t<0) t2--;
293		WRITE_RAM(cpustate, cpustate->p, t2);
294		cpustate->zero=(t2&0xff)==0 && (t&0xff)==0;
295		cpustate->carry=t2<0;
	293	WRITE_RAM(m_p, t2);
	294	m_zero=(t2&0xff)==0 && (t&0xff)==0;
	295	m_carry=t2<0;
296	296	}
297	297
298		INLINE void sc61860_cmp(sc61860_state *cpustate, int reg, UINT8 value)
	298	void sc61860_device::sc61860_cmp(int reg, UINT8 value)
299	299	{
300		int t = READ_RAM(cpustate, reg) - value;
301		cpustate->zero=t==0;
302		cpustate->carry=t<0;
	300	int t = READ_RAM(reg) - value;
	301	m_zero=t==0;
	302	m_carry=t<0;
303	303	}
304	304
305		INLINE void sc61860_pop(sc61860_state *cpustate)
	305	void sc61860_device::sc61860_pop()
306	306	{
307		WRITE_RAM(cpustate, A, POP(cpustate));
	307	WRITE_RAM(A, POP());
308	308	}
309	309
310		INLINE void sc61860_push(sc61860_state *cpustate)
	310	void sc61860_device::sc61860_push()
311	311	{
312		PUSH(cpustate, READ_RAM(cpustate, A));
	312	PUSH(READ_RAM(A));
313	313	}
314	314
315		INLINE void sc61860_prepare_table_call(sc61860_state *cpustate)
	315	void sc61860_device::sc61860_prepare_table_call()
316	316	{
317	317	int adr;
318		cpustate->h=READ_OP(cpustate);
319		adr=READ_OP_ARG_WORD(cpustate);
320		PUSH(cpustate, adr>>8);
321		PUSH(cpustate, adr&0xff);
	318	m_h=READ_OP();
	319	adr=READ_OP_ARG_WORD();
	320	PUSH(adr>>8);
	321	PUSH(adr&0xff);
322	322	}
323	323
324		INLINE void sc61860_execute_table_call(sc61860_state *cpustate)
	324	void sc61860_device::sc61860_execute_table_call()
325	325	{
326	326	int i, v, adr;
327		for (i=0; i<cpustate->h; i++) {
328		v=READ_OP(cpustate);
329		adr=READ_OP_ARG_WORD(cpustate);
330		cpustate->zero=v==READ_RAM(cpustate, A);
331		if (cpustate->zero) {
332		cpustate->pc=adr;
	327	for (i=0; i<m_h; i++) {
	328	v=READ_OP();
	329	adr=READ_OP_ARG_WORD();
	330	m_zero=v==READ_RAM(A);
	331	if (m_zero) {
	332	m_pc=adr;
333	333	return;
334	334	}
335	335	}
336		cpustate->pc=READ_OP_ARG_WORD(cpustate);
	336	m_pc=READ_OP_ARG_WORD();
337	337	}
338	338
339	339
340		INLINE void sc61860_call(sc61860_state *cpustate, UINT16 adr)
	340	void sc61860_device::sc61860_call(UINT16 adr)
341	341	{
342		PUSH(cpustate, cpustate->pc>>8);
343		PUSH(cpustate, cpustate->pc&0xff);
344		cpustate->pc=adr;
	342	PUSH(m_pc>>8);
	343	PUSH(m_pc&0xff);
	344	m_pc=adr;
345	345	}
346	346
347		INLINE void sc61860_return(sc61860_state *cpustate)
	347	void sc61860_device::sc61860_return()
348	348	{
349		UINT16 t=POP(cpustate);
350		t|=POP(cpustate)<<8;
351		cpustate->pc=t;
	349	UINT16 t=POP();
	350	t|=POP()<<8;
	351	m_pc=t;
352	352	}
353	353
354		INLINE void sc61860_jump(sc61860_state *cpustate, int yes)
	354	void sc61860_device::sc61860_jump(int yes)
355	355	{
356		UINT16 adr = READ_OP_ARG_WORD(cpustate);
	356	UINT16 adr = READ_OP_ARG_WORD();
357	357	if (yes) {
358		cpustate->pc=adr;
	358	m_pc=adr;
359	359	}
360	360	}
361	361
362		INLINE void sc61860_jump_rel_plus(sc61860_state *cpustate, int yes)
	362	void sc61860_device::sc61860_jump_rel_plus(int yes)
363	363	{
364		UINT16 adr = cpustate->pc + READ_OP_ARG(cpustate);
	364	UINT16 adr = m_pc + READ_OP_ARG();
365	365	if (yes) {
366		cpustate->pc=adr;
367		cpustate->icount-=3;
	366	m_pc=adr;
	367	m_icount-=3;
368	368	}
369	369	}
370	370
371		INLINE void sc61860_jump_rel_minus(sc61860_state *cpustate, int yes)
	371	void sc61860_device::sc61860_jump_rel_minus(int yes)
372	372	{
373		UINT16 adr = cpustate->pc - READ_OP_ARG(cpustate);
	373	UINT16 adr = m_pc - READ_OP_ARG();
374	374	if (yes) {
375		cpustate->pc=adr;
376		cpustate->icount-=3;
	375	m_pc=adr;
	376	m_icount-=3;
377	377	}
378	378	}
379	379
380		INLINE void sc61860_loop(sc61860_state *cpustate)
	380	void sc61860_device::sc61860_loop()
381	381	{
382		UINT16 adr = cpustate->pc - READ_OP_ARG(cpustate);
383		UINT8 t = READ_RAM(cpustate, cpustate->r) - 1;
384		WRITE_RAM(cpustate, cpustate->r, t);
385		cpustate->zero=t==0;
386		cpustate->carry=t==0xff;
387		if (!cpustate->carry) {
388		cpustate->pc=adr;
389		adr=POP(cpustate);
390		cpustate->icount-=3;
	382	UINT16 adr = m_pc - READ_OP_ARG();
	383	UINT8 t = READ_RAM(m_r) - 1;
	384	WRITE_RAM(m_r, t);
	385	m_zero=t==0;
	386	m_carry=t==0xff;
	387	if (!m_carry) {
	388	m_pc=adr;
	389	adr=POP();
	390	m_icount-=3;
391	391	}
392	392	}
393	393
394		INLINE void sc61860_leave(sc61860_state *cpustate)
	394	void sc61860_device::sc61860_leave()
395	395	{
396		WRITE_RAM(cpustate, cpustate->r, 0);
	396	WRITE_RAM(m_r, 0);
397	397	}
398	398
399		INLINE void sc61860_wait(sc61860_state *cpustate)
	399	void sc61860_device::sc61860_wait()
400	400	{
401		int t=READ_OP(cpustate);
402		cpustate->icount-=t;
403		cpustate->icount-=t;
404		cpustate->icount-=3;
	401	int t=READ_OP();
	402	m_icount-=t;
	403	m_icount-=t;
	404	m_icount-=3;
405	405	}
406	406
407		INLINE void sc61860_set_carry(sc61860_state *cpustate)
	407	void sc61860_device::sc61860_set_carry()
408	408	{
409		cpustate->carry=1;
410		cpustate->zero=1;
	409	m_carry=1;
	410	m_zero=1;
411	411	}
412	412
413		INLINE void sc61860_reset_carry(sc61860_state *cpustate)
	413	void sc61860_device::sc61860_reset_carry()
414	414	{
415		cpustate->carry=0;
416		cpustate->zero=1;
	415	m_carry=0;
	416	m_zero=1;
417	417	}
418	418
419		INLINE void sc61860_out_a(sc61860_state *cpustate)
	419	void sc61860_device::sc61860_out_a()
420	420	{
421		cpustate->q=IA;
422		if (!cpustate->outa.isnull())
423		cpustate->outa(0,READ_RAM(cpustate, IA));
	421	m_q=IA;
	422	m_outa(READ_RAM(IA));
424	423	}
425	424
426		INLINE void sc61860_out_b(sc61860_state *cpustate)
	425	void sc61860_device::sc61860_out_b()
427	426	{
428		cpustate->q=IB;
429		if (!cpustate->outb.isnull())
430		cpustate->outb(0, READ_RAM(cpustate, IB));
	427	m_q=IB;
	428	m_outb( READ_RAM(IB));
431	429	}
432	430
433		INLINE void sc61860_out_f(sc61860_state *cpustate)
	431	void sc61860_device::sc61860_out_f()
434	432	{
435		cpustate->q=F0;
436		/*READ_RAM(cpustate, F0); */
	433	m_q=F0;
	434	/*READ_RAM(F0); */
437	435	}
438	436
439	437
r26784	r26785
444	442	c4 beeper frequency (1 4khz, 0 2khz), or (c5=0) membran pos1/pos2
445	443	c5 beeper on
446	444	c6 beeper steuerung*/
447		INLINE void sc61860_out_c(sc61860_state *cpustate)
	445	void sc61860_device::sc61860_out_c()
448	446	{
449		cpustate->q=C;
450		if (!cpustate->outc.isnull())
451		cpustate->outc(0, READ_RAM(cpustate, C));
452		cpustate->c = READ_RAM(cpustate, C);
	447	m_q=C;
	448	m_outc( READ_RAM(C));
	449	m_c = READ_RAM(C);
453	450	}
454	451
455		INLINE void sc61860_in_a(sc61860_state *cpustate)
	452	void sc61860_device::sc61860_in_a()
456	453	{
457	454	int data=0;
458		if (!cpustate->ina.isnull()) data=cpustate->ina(0);
459		WRITE_RAM(cpustate, A, data);
460		cpustate->zero=data==0;
	455	data=m_ina();
	456	WRITE_RAM(A, data);
	457	m_zero=data==0;
461	458	}
462	459
463		INLINE void sc61860_in_b(sc61860_state *cpustate)
	460	void sc61860_device::sc61860_in_b()
464	461	{
465	462	int data=0;
466		if (!cpustate->inb.isnull()) data=cpustate->inb(0);
467		WRITE_RAM(cpustate, A, data);
468		cpustate->zero=data==0;
	463	data=m_inb();
	464	WRITE_RAM(A, data);
	465	m_zero=data==0;
469	466	}
470	467
471	468	/* 0 systemclock 512ms
r26784	r26785
476	473	5 ?
477	474	6 reset
478	475	7 cassette input */
479		INLINE void sc61860_test_special(sc61860_state *cpustate)
	476	void sc61860_device::sc61860_test_special()
480	477	{
481	478	int t=0;
482		if (cpustate->timer.t512ms) t|=1;
483		if (cpustate->timer.t2ms) t|=2;
484		if (!cpustate->brk.isnull()&&cpustate->brk()) t|=8;
485		if (!cpustate->reset.isnull()&&cpustate->reset()) t|=0x40;
486		if (!cpustate->x.isnull()&&cpustate->x()) t|=0x80;
	479	if (m_timer.t512ms) t|=1;
	480	if (m_timer.t2ms) t|=2;
	481	if (!m_brk.isnull()&&m_brk()) t|=8;
	482	if (!m_reset.isnull()&&m_reset()) t|=0x40;
	483	if (!m_x.isnull()&&m_x()) t|=0x80;
487	484
488		cpustate->zero=(t&READ_OP(cpustate))==0;
	485	m_zero=(t&READ_OP())==0;
489	486	}
490	487
491	488	/************************************************************************************
r26784	r26785
493	490	***********************************************************************************/
494	491
495	492	// p-=I+1 sideeffect
496		INLINE void sc61860_add_bcd_a(sc61860_state *cpustate)
	493	void sc61860_device::sc61860_add_bcd_a()
497	494	{
498		UINT8 help = READ_RAM(cpustate, A);
	495	UINT8 help = READ_RAM(A);
499	496	int i, hlp, hlp1 = 0;
500		cpustate->zero=1;
501		for (i=0; i <= READ_RAM(cpustate, I); i++) {
502		int t = READ_RAM(cpustate, cpustate->p);
	497	m_zero=1;
	498	for (i=0; i <= READ_RAM(I); i++) {
	499	int t = READ_RAM(m_p);
503	500	hlp1 = (t & 0x0f) + (help & 0x0f) + hlp1;
504	501	if (hlp1 > 9) { hlp = hlp1 - 0x0a; hlp1 = 0x10; }
505	502	else { hlp = hlp1; hlp1 = 0x00; }
506	503	hlp1 = (t & 0xf0) + (help & 0xf0) + hlp1;
507		if (hlp1 > 0x90) { WRITE_RAM(cpustate, cpustate->p, hlp1 - 0xa0 + hlp); hlp1 = 1; }
508		else { WRITE_RAM(cpustate, cpustate->p, hlp1 + hlp); hlp1 = 0; }
509		if ( READ_RAM(cpustate, cpustate->p) != 0 ) cpustate->zero = 0;
510		cpustate->p--;
	504	if (hlp1 > 0x90) { WRITE_RAM(m_p, hlp1 - 0xa0 + hlp); hlp1 = 1; }
	505	else { WRITE_RAM(m_p, hlp1 + hlp); hlp1 = 0; }
	506	if ( READ_RAM(m_p) != 0 ) m_zero = 0;
	507	m_p--;
511	508	help = 0;
512	509	}
513		cpustate->carry= ( hlp1 ) ? 1 : 0;
514		cpustate->icount-=3*(READ_RAM(cpustate, I)+1);
	510	m_carry= ( hlp1 ) ? 1 : 0;
	511	m_icount-=3*(READ_RAM(I)+1);
515	512	}
516	513
517	514
518	515	// p-=I+1, q-=I+2 sideeffect
519		INLINE void sc61860_add_bcd(sc61860_state *cpustate)
	516	void sc61860_device::sc61860_add_bcd()
520	517	{
521	518	int i, hlp, hlp1 = 0;
522		cpustate->zero=1;
523		for (i=0; i <= READ_RAM(cpustate, I); i++) {
524		int t = READ_RAM(cpustate, cpustate->p);
525		int t2 = READ_RAM(cpustate, cpustate->q);
	519	m_zero=1;
	520	for (i=0; i <= READ_RAM(I); i++) {
	521	int t = READ_RAM(m_p);
	522	int t2 = READ_RAM(m_q);
526	523	hlp1 = (t & 0x0f) + (t2 & 0x0f) + hlp1;
527	524	if (hlp1 > 9) { hlp = hlp1 - 0x0a; hlp1 = 0x10; }
528	525	else { hlp = hlp1; hlp1 = 0x00; }
529	526	hlp1 = (t & 0xf0) + (t2 & 0xf0) + hlp1;
530		cpustate->q--;
531		if (hlp1 > 0x90) { WRITE_RAM(cpustate, cpustate->p, hlp1 - 0xa0 + hlp); hlp1 = 1; }
532		else { WRITE_RAM(cpustate, cpustate->p, hlp1 + hlp); hlp1 = 0; }
533		if ( READ_RAM(cpustate, cpustate->p) != 0 ) cpustate->zero = 0;
534		cpustate->p--;
	527	m_q--;
	528	if (hlp1 > 0x90) { WRITE_RAM(m_p, hlp1 - 0xa0 + hlp); hlp1 = 1; }
	529	else { WRITE_RAM(m_p, hlp1 + hlp); hlp1 = 0; }
	530	if ( READ_RAM(m_p) != 0 ) m_zero = 0;
	531	m_p--;
535	532	}
536		cpustate->carry= ( hlp1 ) ? 1 : 0;
537		cpustate->icount-=3*(READ_RAM(cpustate, I)+1);
538		cpustate->q--;
	533	m_carry= ( hlp1 ) ? 1 : 0;
	534	m_icount-=3*(READ_RAM(I)+1);
	535	m_q--;
539	536	}
540	537
541	538
542	539	// p-=I+1 sideeffect
543		INLINE void sc61860_sub_bcd_a(sc61860_state *cpustate)
	540	void sc61860_device::sc61860_sub_bcd_a()
544	541	{
545		UINT8 help = READ_RAM(cpustate, A);
	542	UINT8 help = READ_RAM(A);
546	543	int i, hlp, hlp1 = 0;
547		cpustate->zero=1;
548		for (i=0; i <= READ_RAM(cpustate, I); i++) {
549		int t = READ_RAM(cpustate, cpustate->p);
	544	m_zero=1;
	545	for (i=0; i <= READ_RAM(I); i++) {
	546	int t = READ_RAM(m_p);
550	547	hlp1 = (t & 0x0f) - (help & 0x0f) - hlp1;
551	548	if ( hlp1 < 0 ) { hlp = hlp1 + 0x0a; hlp1 = 0x10; }
552	549	else { hlp = hlp1; hlp1 = 0x00; }
553	550	hlp1 = (t & 0xf0) - (help & 0xf0) - hlp1;
554		if ( hlp1 < 0 ) { WRITE_RAM(cpustate, cpustate->p, hlp1 + 0xa0 + hlp); hlp1 = 1; }
555		else { WRITE_RAM(cpustate, cpustate->p, hlp1 + hlp); hlp1 = 0; }
556		if ( READ_RAM(cpustate, cpustate->p) != 0 ) cpustate->zero = 0;
557		cpustate->p--;
	551	if ( hlp1 < 0 ) { WRITE_RAM(m_p, hlp1 + 0xa0 + hlp); hlp1 = 1; }
	552	else { WRITE_RAM(m_p, hlp1 + hlp); hlp1 = 0; }
	553	if ( READ_RAM(m_p) != 0 ) m_zero = 0;
	554	m_p--;
558	555	help = 0;
559	556	}
560		cpustate->carry= ( hlp1 ) ? 1 : 0;
561		cpustate->icount-=3*(READ_RAM(cpustate, I)+1);
	557	m_carry= ( hlp1 ) ? 1 : 0;
	558	m_icount-=3*(READ_RAM(I)+1);
562	559	}
563	560
564	561
565	562	// p-=I+1, q-=I+2 sideeffect
566		INLINE void sc61860_sub_bcd(sc61860_state *cpustate)
	563	void sc61860_device::sc61860_sub_bcd()
567	564	{
568	565	int i, hlp, hlp1 = 0;
569		cpustate->zero=1;
570		for (i=0; i <= READ_RAM(cpustate, I); i++) {
571		int t = READ_RAM(cpustate, cpustate->p);
572		int t2 = READ_RAM(cpustate, cpustate->q);
	566	m_zero=1;
	567	for (i=0; i <= READ_RAM(I); i++) {
	568	int t = READ_RAM(m_p);
	569	int t2 = READ_RAM(m_q);
573	570	hlp1 = (t & 0x0f) - (t2 & 0x0f) - hlp1;
574	571	if ( hlp1 < 0 ) { hlp = hlp1 + 0x0a; hlp1 = 0x10; }
575	572	else { hlp = hlp1; hlp1 = 0x00; }
576	573	hlp1 = (t & 0xf0) - (t2 & 0xf0) - hlp1;
577		cpustate->q--;
578		if ( hlp1 < 0 ) { WRITE_RAM(cpustate, cpustate->p, hlp1 + 0xa0 + hlp); hlp1 = 1; }
579		else { WRITE_RAM(cpustate, cpustate->p, hlp1 + hlp); hlp1 = 0; }
580		if ( READ_RAM(cpustate, cpustate->p) != 0 ) cpustate->zero = 0;
581		cpustate->p--;
	574	m_q--;
	575	if ( hlp1 < 0 ) { WRITE_RAM(m_p, hlp1 + 0xa0 + hlp); hlp1 = 1; }
	576	else { WRITE_RAM(m_p, hlp1 + hlp); hlp1 = 0; }
	577	if ( READ_RAM(m_p) != 0 ) m_zero = 0;
	578	m_p--;
582	579	}
583		cpustate->carry= ( hlp1 ) ? 1 : 0;
584		cpustate->icount-=3*(READ_RAM(cpustate, I)+1);
585		cpustate->q--;
	580	m_carry= ( hlp1 ) ? 1 : 0;
	581	m_icount-=3*(READ_RAM(I)+1);
	582	m_q--;
586	583	}
587	584
588	585	/* side effect p-i-1 -> p correct! */
589		INLINE void sc61860_shift_left_nibble(sc61860_state *cpustate)
	586	void sc61860_device::sc61860_shift_left_nibble()
590	587	{
591	588	int i,t=0;
592		for (i=0; i<=READ_RAM(cpustate, I); i++) {
593		t |= READ_RAM(cpustate, cpustate->p)<<4;
594		WRITE_RAM(cpustate, cpustate->p, t);
595		cpustate->p--;
	589	for (i=0; i<=READ_RAM(I); i++) {
	590	t |= READ_RAM(m_p)<<4;
	591	WRITE_RAM(m_p, t);
	592	m_p--;
596	593	t>>=8;
597		cpustate->icount--;
	594	m_icount--;
598	595	}
599	596	}
600	597
601	598	/* side effect p+i+1 -> p correct! */
602		INLINE void sc61860_shift_right_nibble(sc61860_state *cpustate)
	599	void sc61860_device::sc61860_shift_right_nibble()
603	600	{
604	601	int i,t=0;
605		for (i=0; i<=READ_RAM(cpustate, I); i++) {
606		t |= READ_RAM(cpustate, cpustate->p);
607		WRITE_RAM(cpustate, cpustate->p, t>>4);
608		cpustate->p++;
	602	for (i=0; i<=READ_RAM(I); i++) {
	603	t |= READ_RAM(m_p);
	604	WRITE_RAM(m_p, t>>4);
	605	m_p++;
609	606	t=(t<<8)&0xf00;
610		cpustate->icount--;
	607	m_icount--;
611	608	}
612	609	}
613	610
614	611	// q=reg+1 sideeffect
615		INLINE void sc61860_inc_load_dp(sc61860_state *cpustate, int reg)
	612	void sc61860_device::sc61860_inc_load_dp(int reg)
616	613	{
617		UINT8 t = READ_RAM(cpustate, reg) + 1;
618		UINT8 t2 = READ_RAM(cpustate, reg + 1);
619		WRITE_RAM(cpustate, reg, t);
620		if (t == 0) { t2++; WRITE_RAM(cpustate, reg + 1, t2); }
621		cpustate->dp=t|(t2<<8);
622		cpustate->q=reg+1;
	614	UINT8 t = READ_RAM(reg) + 1;
	615	UINT8 t2 = READ_RAM(reg + 1);
	616	WRITE_RAM(reg, t);
	617	if (t == 0) { t2++; WRITE_RAM(reg + 1, t2); }
	618	m_dp=t|(t2<<8);
	619	m_q=reg+1;
623	620	}
624	621
625	622	// q=reg+1 sideeffect
626		INLINE void sc61860_dec_load_dp(sc61860_state *cpustate, int reg)
	623	void sc61860_device::sc61860_dec_load_dp(int reg)
627	624	{
628		UINT8 t = READ_RAM(cpustate, reg) - 1;
629		UINT8 t2 = READ_RAM(cpustate, reg + 1);
630		WRITE_RAM(cpustate, reg, t);
631		if (t == 0xff) { t2--; WRITE_RAM(cpustate, reg + 1, t2); }
632		cpustate->dp=t|(t2<<8);
633		cpustate->q=reg+1;
	625	UINT8 t = READ_RAM(reg) - 1;
	626	UINT8 t2 = READ_RAM(reg + 1);
	627	WRITE_RAM(reg, t);
	628	if (t == 0xff) { t2--; WRITE_RAM(reg + 1, t2); }
	629	m_dp=t|(t2<<8);
	630	m_q=reg+1;
634	631	}
635	632
636	633	// q=XH sideeffect
637		INLINE void sc61860_inc_load_dp_load(sc61860_state *cpustate)
	634	void sc61860_device::sc61860_inc_load_dp_load()
638	635	{
639		sc61860_inc_load_dp(cpustate, XL);
640		WRITE_RAM(cpustate, A, READ_BYTE(cpustate, cpustate->dp));
	636	sc61860_inc_load_dp(XL);
	637	WRITE_RAM(A, READ_BYTE(m_dp));
641	638	}
642	639
643	640	// q=XH sideeffect
644		INLINE void sc61860_dec_load_dp_load(sc61860_state *cpustate)
	641	void sc61860_device::sc61860_dec_load_dp_load()
645	642	{
646		sc61860_dec_load_dp(cpustate, XL);
647		WRITE_RAM(cpustate, A, READ_BYTE(cpustate, cpustate->dp));
	643	sc61860_dec_load_dp(XL);
	644	WRITE_RAM(A, READ_BYTE(m_dp));
648	645	}
649	646
650	647	// q=YH sideeffect
651		INLINE void sc61860_inc_load_dp_store(sc61860_state *cpustate)
	648	void sc61860_device::sc61860_inc_load_dp_store()
652	649	{
653		sc61860_inc_load_dp(cpustate, YL);
654		WRITE_BYTE(cpustate, cpustate->dp, READ_RAM(cpustate, A));
	650	sc61860_inc_load_dp(YL);
	651	WRITE_BYTE(m_dp, READ_RAM(A));
655	652	}
656	653
657	654	// q=YH sideeffect
658		INLINE void sc61860_dec_load_dp_store(sc61860_state *cpustate)
	655	void sc61860_device::sc61860_dec_load_dp_store()
659	656	{
660		sc61860_dec_load_dp(cpustate, YL);
661		WRITE_BYTE(cpustate, cpustate->dp, READ_RAM(cpustate, A));
	657	sc61860_dec_load_dp(YL);
	658	WRITE_BYTE(m_dp, READ_RAM(A));
662	659	}
663	660
664		INLINE void sc61860_fill(sc61860_state *cpustate)
	661	void sc61860_device::sc61860_fill()
665	662	{
666	663	int i;
667		for (i=0;i<=READ_RAM(cpustate, I);i++) {
668		WRITE_RAM(cpustate, cpustate->p, READ_RAM(cpustate, A)); /* could be overwritten? */
669		cpustate->p++;
670		cpustate->icount--;
	664	for (i=0;i<=READ_RAM(I);i++) {
	665	WRITE_RAM(m_p, READ_RAM(A)); /* could be overwritten? */
	666	m_p++;
	667	m_icount--;
671	668	}
672	669	}
673	670
674		INLINE void sc61860_fill_ext(sc61860_state *cpustate)
	671	void sc61860_device::sc61860_fill_ext()
675	672	{
676	673	int i;
677		for (i=0;i<=READ_RAM(cpustate, I);i++) {
678		WRITE_BYTE(cpustate, cpustate->dp, READ_RAM(cpustate, A));
679		if (i!=READ_RAM(cpustate, I)) cpustate->dp++;
680		cpustate->icount-=3;
	674	for (i=0;i<=READ_RAM(I);i++) {
	675	WRITE_BYTE(m_dp, READ_RAM(A));
	676	if (i!=READ_RAM(I)) m_dp++;
	677	m_icount-=3;
681	678	}
682	679	}
683	680
684	681	// p+=count+1, q+=count+1 sideeffects
685		INLINE void sc61860_copy(sc61860_state *cpustate, int count)
	682	void sc61860_device::sc61860_copy(int count)
686	683	{
687	684	int i;
688	685	for (i=0; i<=count; i++) {
689		WRITE_RAM(cpustate, cpustate->p, READ_RAM(cpustate, cpustate->q));
690		cpustate->p++;
691		cpustate->q++;
692		cpustate->icount-=2;
	686	WRITE_RAM(m_p, READ_RAM(m_q));
	687	m_p++;
	688	m_q++;
	689	m_icount-=2;
693	690	}
694	691
695	692	}
696	693
697	694	// p+=count+1, dp+=count sideeffects
698		INLINE void sc61860_copy_ext(sc61860_state *cpustate, int count)
	695	void sc61860_device::sc61860_copy_ext(int count)
699	696	{
700	697	int i;
701	698	for (i=0; i<=count; i++) {
702		WRITE_RAM(cpustate, cpustate->p, READ_BYTE(cpustate, cpustate->dp));
703		cpustate->p++;
704		if (i!=count) cpustate->dp++;
705		cpustate->icount-=4;
	699	WRITE_RAM(m_p, READ_BYTE(m_dp));
	700	m_p++;
	701	if (i!=count) m_dp++;
	702	m_icount-=4;
706	703	}
707	704	}
708	705
709		INLINE void sc61860_copy_int(sc61860_state *cpustate, int count)
	706	void sc61860_device::sc61860_copy_int(int count)
710	707	{
711	708	int i;
712	709	for (i=0; i<=count; i++) {
713		UINT8 t = READ_BYTE(cpustate, (READ_RAM(cpustate, A)|(READ_RAM(cpustate, B)<<8))); /* internal rom! */
714		WRITE_RAM(cpustate, cpustate->p, t);
715		cpustate->p++;
	710	UINT8 t = READ_BYTE((READ_RAM(A)|(READ_RAM(B)<<8))); /* internal rom! */
	711	WRITE_RAM(m_p, t);
	712	m_p++;
716	713	if (i!=count) {
717		t = READ_RAM(cpustate, A) + 1;
718		WRITE_RAM(cpustate, A, t);
	714	t = READ_RAM(A) + 1;
	715	WRITE_RAM(A, t);
719	716	if (t==0) {
720		t = READ_RAM(cpustate, B) + 1;
721		WRITE_RAM(cpustate, B, t);
	717	t = READ_RAM(B) + 1;
	718	WRITE_RAM(B, t);
722	719	}
723	720	}
724		cpustate->icount-=4;
	721	m_icount-=4;
725	722	}
726	723	}
727	724
728		INLINE void sc61860_exchange(sc61860_state *cpustate, int count)
	725	void sc61860_device::sc61860_exchange(int count)
729	726	{
730	727	int i;
731	728	UINT8 t;
732	729	for (i=0; i<=count; i++) {
733		t = READ_RAM(cpustate, cpustate->p);
734		WRITE_RAM(cpustate, cpustate->p, READ_RAM(cpustate, cpustate->q));
735		WRITE_RAM(cpustate, cpustate->q, t);
736		cpustate->p++;
737		cpustate->q++;
738		cpustate->icount-=3;
	730	t = READ_RAM(m_p);
	731	WRITE_RAM(m_p, READ_RAM(m_q));
	732	WRITE_RAM(m_q, t);
	733	m_p++;
	734	m_q++;
	735	m_icount-=3;
739	736	}
740	737	}
741	738
742		INLINE void sc61860_exchange_ext(sc61860_state *cpustate, int count)
	739	void sc61860_device::sc61860_exchange_ext(int count)
743	740	{
744	741	int i;
745	742	UINT8 t;
746	743	for (i=0; i<=count; i++) {
747		t = READ_RAM(cpustate, cpustate->p);
748		WRITE_RAM(cpustate, cpustate->p, READ_BYTE(cpustate, cpustate->dp));
749		cpustate->p++;
750		WRITE_BYTE(cpustate, cpustate->dp, t);
751		if (i!=count) cpustate->dp++;
752		cpustate->icount-=6;
	744	t = READ_RAM(m_p);
	745	WRITE_RAM(m_p, READ_BYTE(m_dp));
	746	m_p++;
	747	WRITE_BYTE(m_dp, t);
	748	if (i!=count) m_dp++;
	749	m_icount-=6;
753	750	}
754	751	}
755	752
756	753	// undocumented
757	754	// only 1 opcode working in pc1403
758	755	// both opcodes working in pc1350
759		INLINE void sc61860_wait_x(sc61860_state *cpustate, int level)
	756	void sc61860_device::sc61860_wait_x(int level)
760	757	{
761	758	int c;
762		cpustate->zero=level;
	759	m_zero=level;
763	760
764		if (!cpustate->x.isnull()) {
765		for (c=READ_RAM(cpustate, I); c>=0; c--) {
766		UINT8 t = (READ_RAM(cpustate, cpustate->p)+1)&0x7f;
767		WRITE_RAM(cpustate, cpustate->p, t);
768		cpustate->zero=cpustate->x();
769		cpustate->icount-=4;
770		if (level != cpustate->zero) break;
	761	if (!m_x.isnull()) {
	762	for (c=READ_RAM(I); c>=0; c--) {
	763	UINT8 t = (READ_RAM(m_p)+1)&0x7f;
	764	WRITE_RAM(m_p, t);
	765	m_zero=m_x();
	766	m_icount-=4;
	767	if (level != m_zero) break;
771	768	}
772	769	}
773	770	}

trunk/src/emu/cpu/sc61860/sc61860.c

r26784	r26785
55	55
56	56	#define LOG(x)  do { if (VERBOSE) logerror x; } while (0)
57	57
58		/****************************************************************************
59		* The 61860 registers.
60		****************************************************************************/
61		struct sc61860_state
62		{
63		sc61860_cpu_core *config;
64		UINT8 p, q, r; //7 bits only?
65	58
66		UINT8 c;        // port c, used for HLT.
67		UINT8 d, h;
68		UINT16 oldpc, pc, dp;
	59	const device_type SC61860 = &device_creator<sc61860_device>;
69	60
70		int carry, zero;
71	61
72		struct { int t2ms, t512ms; int count; } timer;
	62	sc61860_device::sc61860_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	63	: cpu_device(mconfig, SC61860, "SC61860", tag, owner, clock, "sc61860", __FILE__)
	64	, m_program_config("program", ENDIANNESS_BIG, 8, 16, 0)
	65	, m_reset(*this)
	66	, m_brk(*this)
	67	, m_x(*this)
	68	, m_ina(*this)
	69	, m_outa(*this)
	70	, m_inb(*this)
	71	, m_outb(*this)
	72	, m_outc(*this)
	73	{
	74	}
73	75
74		legacy_cpu_device *device;
75		address_space *program;
76		direct_read_data *direct;
77		int icount;
78		UINT8 ram[0x100]; // internal special ram, should be 0x60, 0x100 to avoid memory corruption for now
79	76
80		devcb_resolved_read_line reset;
81		devcb_resolved_read_line brk;
82		devcb_resolved_read_line x;
83		devcb_resolved_read8 ina;
84		devcb_resolved_write8 outa;
85		devcb_resolved_read8 inb;
86		devcb_resolved_write8 outb;
87		devcb_resolved_write8 outc;
88
89		};
90
91		INLINE sc61860_state *get_safe_token(device_t *device)
	77	offs_t sc61860_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
92	78	{
93		assert(device != NULL);
94		assert(device->type() == SC61860);
95		return (sc61860_state *)downcast<legacy_cpu_device *>(device)->token();
	79	extern CPU_DISASSEMBLE( sc61860 );
	80	return CPU_DISASSEMBLE_NAME(sc61860)(this, buffer, pc, oprom, opram, options);
96	81	}
97	82
98		UINT8 *sc61860_internal_ram(device_t *device)
	83
	84	UINT8 *sc61860_device::internal_ram()
99	85	{
100		sc61860_state *cpustate = get_safe_token(device);
101		return cpustate->ram;
	86	return m_ram;
102	87	}
103	88
104		static TIMER_CALLBACK(sc61860_2ms_tick)
	89	TIMER_CALLBACK_MEMBER(sc61860_device::sc61860_2ms_tick)
105	90	{
106		sc61860_state *cpustate = (sc61860_state *)ptr;
107		if (--cpustate->timer.count == 0)
	91	if (--m_timer.count == 0)
108	92	{
109		cpustate->timer.count = 128;
110		cpustate->timer.t512ms = !cpustate->timer.t512ms;
	93	m_timer.count = 128;
	94	m_timer.t512ms = !m_timer.t512ms;
111	95	}
112		cpustate->timer.t2ms = !cpustate->timer.t2ms;
	96	m_timer.t2ms = !m_timer.t2ms;
113	97	}
114	98
115	99	/***************************************************************
r26784	r26785
118	102	#include "scops.c"
119	103	#include "sctable.c"
120	104
121		static CPU_RESET( sc61860 )
	105	void sc61860_device::device_reset()
122	106	{
123		sc61860_state *cpustate = get_safe_token(device);
124		cpustate->timer.t2ms=0;
125		cpustate->timer.t512ms=0;
126		cpustate->timer.count=256;
127		cpustate->pc=0;
	107	m_timer.t2ms=0;
	108	m_timer.t512ms=0;
	109	m_timer.count=256;
	110	m_pc=0;
128	111	}
129	112
130		static CPU_INIT( sc61860 )
	113	void sc61860_device::device_start()
131	114	{
132		sc61860_state *cpustate = get_safe_token(device);
133		cpustate->config = (sc61860_cpu_core *) device->static_config();
134		device->machine().scheduler().timer_pulse(attotime::from_hz(500), FUNC(sc61860_2ms_tick), 0, cpustate);
135		cpustate->device = device;
136		cpustate->program = &device->space(AS_PROGRAM);
137		cpustate->direct = &cpustate->program->direct();
138		cpustate->reset.resolve(cpustate->config->reset,*device);
139		cpustate->brk.resolve(  cpustate->config->brk,*device);
140		cpustate->x.resolve(    cpustate->config->x,*device);
141		cpustate->ina.resolve(  cpustate->config->ina,*device);
142		cpustate->outa.resolve( cpustate->config->outa,*device);
143		cpustate->inb.resolve(  cpustate->config->inb,*device);
144		cpustate->outb.resolve( cpustate->config->outb,*device);
145		cpustate->outc.resolve( cpustate->config->outc,*device);
146		}
	115	machine().scheduler().timer_pulse(attotime::from_hz(500), timer_expired_delegate( FUNC(sc61860_device::sc61860_2ms_tick), this));
147	116
148		static CPU_EXECUTE( sc61860 )
149		{
150		sc61860_state *cpustate = get_safe_token(device);
	117	m_program = &space(AS_PROGRAM);
	118	m_direct = &m_program->direct();
	119	m_reset.resolve();
	120	m_brk.resolve();
	121	m_x.resolve();
	122	m_ina.resolve();
	123	m_outa.resolve();
	124	m_inb.resolve();
	125	m_outb.resolve();
	126	m_outc.resolve();
151	127
152		do
153		{
154		cpustate->oldpc = cpustate->pc;
	128	m_p = 0;
	129	m_q = 0;
	130	m_r = 0;
	131	m_c = 0;
	132	m_d = 0;
	133	m_h = 0;
	134	m_oldpc = 0;
	135	m_dp = 0;
	136	m_carry = 0;
	137	m_zero = 0;
	138	memset( m_ram, 0, sizeof(m_ram) );
155	139
156		debugger_instruction_hook(device, cpustate->pc);
	140	save_item(NAME(m_p));
	141	save_item(NAME(m_q));
	142	save_item(NAME(m_r));
	143	save_item(NAME(m_c));
	144	save_item(NAME(m_d));
	145	save_item(NAME(m_h));
	146	save_item(NAME(m_pc));
	147	save_item(NAME(m_dp));
	148	save_item(NAME(m_carry));
	149	save_item(NAME(m_zero));
	150	save_item(NAME(m_timer.t2ms));
	151	save_item(NAME(m_timer.t512ms));
	152	save_item(NAME(m_timer.count));
	153	save_item(NAME(m_ram));
157	154
158		sc61860_instruction(cpustate);
	155	state_add( SC61860_PC,    "PC",    m_pc            ).formatstr("%04X");
	156	state_add( SC61860_DP,    "DP",    m_dp            ).formatstr("%04X");
	157	state_add( SC61860_P,     "P",     m_p             ).mask(0x7f).formatstr("%02X");
	158	state_add( SC61860_Q,     "Q",     m_q             ).mask(0x7f).formatstr("%02X");
	159	state_add( SC61860_R,     "R",     m_r             ).mask(0x7f).formatstr("%02X");
	160	state_add( SC61860_I,     "I",     m_ram[I]        ).formatstr("%02X");
	161	state_add( SC61860_J,     "J",     m_ram[J]        ).formatstr("%02X");
	162	state_add( SC61860_K,     "K",     m_ram[K]        ).formatstr("%02X");
	163	state_add( SC61860_L,     "L",     m_ram[L]        ).formatstr("%02X");
	164	state_add( SC61860_V,     "V",     m_ram[V]        ).formatstr("%02X");
	165	state_add( SC61860_W,     "Wx",    m_ram[W]        ).formatstr("%02X");
	166	state_add( SC61860_H,     "W",     m_h             ).formatstr("%02X");
	167	state_add( SC61860_BA,    "BA",    m_debugger_temp ).callimport().callexport().formatstr("%04X");
	168	state_add( SC61860_X,     "X",     m_debugger_temp ).callimport().callexport().formatstr("%04X");
	169	state_add( SC61860_Y,     "Y",     m_debugger_temp ).callimport().callexport().formatstr("%04X");
	170	state_add( SC61860_CARRY, "Carry", m_carry         ).mask(1).formatstr("%1u");
	171	state_add( SC61860_ZERO,  "Zero" , m_zero          ).mask(1).formatstr("%1u");
159	172
160		#if 0
161		/* Are we in HLT-mode? */
162		if (cpustate->c & 4)
163		{
164		if ((cpustate->config && cpustate->config->ina && (cpustate->config->ina(cpustate)!=0)) || cpustate->timer.t512ms)
165		{
166		cpustate->c&=0xfb;
167		if (cpustate->config->outc) cpustate->config->outc(cpustate->c);
168		}
169		cpustate->icount-=4;
170		}
171		else if(cpustate->c & 8) {}
	173	state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%04X").noshow();
	174	state_add(STATE_GENFLAGS, "GENFLAGS",  m_debugger_temp).formatstr("%2s").noshow();
	175	state_add(STATE_GENSP, "GENSP", m_r).mask(0x7f).formatstr("%02X").noshow();
	176	state_add(STATE_GENPCBASE, "GENPCBASE", m_oldpc).formatstr("%04X").noshow();
172	177
173		else sc61860_instruction(cpustate);
174		#endif
175
176		} while (cpustate->icount > 0);
	178	m_icountptr = &m_icount;
177	179	}
178	180
179	181
180		/**************************************************************************
181		* Generic set_info
182		**************************************************************************/
183
184		static CPU_SET_INFO( sc61860 )
	182	void sc61860_device::state_string_export(const device_state_entry &entry, astring &string)
185	183	{
186		sc61860_state *cpustate = get_safe_token(device);
187		switch (state)
	184	switch (entry.index())
188	185	{
189		case CPUINFO_INT_PC:
190		case CPUINFO_INT_REGISTER + SC61860_PC:         cpustate->pc = info->i; break;
191		case CPUINFO_INT_SP:
192		case CPUINFO_INT_REGISTER + SC61860_R:          cpustate->r = info->i & 0x7F;                       break;
193		case CPUINFO_INT_REGISTER + SC61860_DP:         cpustate->dp = info->i;         break;
194		case CPUINFO_INT_REGISTER + SC61860_P:          cpustate->p = info->i & 0x7F;       break;
195		case CPUINFO_INT_REGISTER + SC61860_Q:          cpustate->q = info->i & 0x7F;       break;
196		case CPUINFO_INT_REGISTER + SC61860_CARRY:      cpustate->carry = info->i;          break;
197		case CPUINFO_INT_REGISTER + SC61860_ZERO:       cpustate->zero = info->i;           break;
	186	case STATE_GENFLAGS:
	187	string.printf("%c%c", m_zero?'Z':'.', m_carry ? 'C':'.');
	188	break;
198	189	}
199	190	}
200	191
201	192
	193	void sc61860_device::state_import(const device_state_entry &entry)
	194	{
	195	switch (entry.index())
	196	{
	197	case SC61860_BA:
	198	m_ram[A] = m_debugger_temp & 0xff;
	199	m_ram[B] = ( m_debugger_temp >> 8 ) & 0xff;
	200	break;
202	201
203		/**************************************************************************
204		* Generic get_info
205		**************************************************************************/
	202	case SC61860_X:
	203	m_ram[XL] = m_debugger_temp & 0xff;
	204	m_ram[XH] = ( m_debugger_temp >> 8 ) & 0xff;
	205	break;
206	206
207		CPU_GET_INFO( sc61860 )
	207	case SC61860_Y:
	208	m_ram[YL] = m_debugger_temp & 0xff;
	209	m_ram[YH] = ( m_debugger_temp >> 8 ) & 0xff;
	210	break;
	211	}
	212	}
	213
	214
	215	void sc61860_device::state_export(const device_state_entry &entry)
208	216	{
209		sc61860_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
210		switch (state)
	217	switch (entry.index())
211	218	{
212		/* --- the following bits of info are returned as 64-bit signed integers --- */
213		case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(sc61860_state);                break;
214		case CPUINFO_INT_INPUT_LINES:                       info->i = 0;                            break;
215		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
216		case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
217		case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
218		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
219		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 1;                            break;
220		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 4;                            break;
221		case CPUINFO_INT_MIN_CYCLES:                    info->i = 2;                            break;
222		case CPUINFO_INT_MAX_CYCLES:                    info->i = 4;                            break;
	219	case SC61860_BA:
	220	m_debugger_temp = ( m_ram[B] << 8 ) | m_ram[A];
	221	break;
223	222
224		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 8;                    break;
225		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16;                  break;
226		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;                   break;
227		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;                    break;
228		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;                    break;
229		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;                    break;
230		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 0;                    break;
231		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 0;                    break;
232		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = 0;                    break;
	223	case SC61860_X:
	224	m_debugger_temp = ( m_ram[XH] << 8 ) | m_ram[XL];
	225	break;
233	226
234		case CPUINFO_INT_PREVIOUSPC:                    info->i = cpustate->oldpc;                      break;
	227	case SC61860_Y:
	228	m_debugger_temp = ( m_ram[YH] << 8 ) | m_ram[YL];
	229	break;
	230	}
	231	}
235	232
236		case CPUINFO_INT_PC:
237		case CPUINFO_INT_REGISTER + SC61860_PC:             info->i =  cpustate->pc;                        break;
238		case CPUINFO_INT_SP:
239		case CPUINFO_INT_REGISTER + SC61860_R:              info->i =  cpustate->r;                     break;
240		case CPUINFO_INT_REGISTER + SC61860_DP:             info->i =  cpustate->dp;                        break;
241		case CPUINFO_INT_REGISTER + SC61860_P:              info->i =  cpustate->p;                     break;
242		case CPUINFO_INT_REGISTER + SC61860_Q:              info->i =  cpustate->q;                     break;
243		case CPUINFO_INT_REGISTER + SC61860_CARRY:          info->i =  cpustate->carry;                 break;
244		case CPUINFO_INT_REGISTER + SC61860_ZERO:           info->i =  cpustate->zero;                  break;
245	233
246		/* --- the following bits of info are returned as pointers to data or functions --- */
247		case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(sc61860);             break;
248		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(sc61860);                        break;
249		case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(sc61860);                  break;
250		case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(sc61860);              break;
251		case CPUINFO_FCT_BURN:                          info->burn = NULL;                              break;
252		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(sc61860);              break;
253		case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &cpustate->icount;                   break;
	234	void sc61860_device::execute_run()
	235	{
	236	do
	237	{
	238	m_oldpc = m_pc;
254	239
255		/* --- the following bits of info are returned as NULL-terminated strings --- */
256		case CPUINFO_STR_NAME:                          strcpy(info->s, "SC61860"); break;
257		case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "sc61860"); break;
258		case CPUINFO_STR_FAMILY:                    strcpy(info->s, "SC61860"); break;
259		case CPUINFO_STR_VERSION:                   strcpy(info->s, "1.0beta"); break;
260		case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__); break;
261		case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Copyright Peter Trauner, all rights reserved."); break;
	240	debugger_instruction_hook(this, m_pc);
262	241
263		case CPUINFO_STR_FLAGS:
264		sprintf(info->s, "%c%c", cpustate->zero?'Z':'.', cpustate->carry ? 'C':'.');
265		break;
	242	sc61860_instruction();
266	243
267		case CPUINFO_STR_REGISTER + SC61860_PC:     sprintf(info->s, "PC:%.4x", cpustate->pc);break;
268		case CPUINFO_STR_REGISTER + SC61860_DP:     sprintf(info->s, "DP:%.4x", cpustate->dp);break;
269		case CPUINFO_STR_REGISTER + SC61860_P:      sprintf(info->s, "P:%.2x", cpustate->p);break;
270		case CPUINFO_STR_REGISTER + SC61860_Q:      sprintf(info->s, "Q:%.2x", cpustate->q);break;
271		case CPUINFO_STR_REGISTER + SC61860_R:      sprintf(info->s, "R:%.2x", cpustate->r);break;
272		case CPUINFO_STR_REGISTER + SC61860_I:      sprintf(info->s, "I:%.2x", cpustate->ram[I]);break;
273		case CPUINFO_STR_REGISTER + SC61860_J:      sprintf(info->s, "J:%.2x", cpustate->ram[J]);break;
274		case CPUINFO_STR_REGISTER + SC61860_K:      sprintf(info->s, "K:%.2x", cpustate->ram[K]);break;
275		case CPUINFO_STR_REGISTER + SC61860_L:      sprintf(info->s, "L:%.2x", cpustate->ram[L]);break;
276		case CPUINFO_STR_REGISTER + SC61860_V:      sprintf(info->s, "V:%.2x", cpustate->ram[V]);break;
277		case CPUINFO_STR_REGISTER + SC61860_W:      sprintf(info->s, "W:%.2x", cpustate->ram[W]);break;
278		case CPUINFO_STR_REGISTER + SC61860_H:      sprintf(info->s, "W:%.2x", cpustate->h);break;
279		case CPUINFO_STR_REGISTER + SC61860_BA:     sprintf(info->s, "BA:%.2x%.2x", cpustate->ram[B], cpustate->ram[A]);break;
280		case CPUINFO_STR_REGISTER + SC61860_X:      sprintf(info->s, "X: %.2x%.2x", cpustate->ram[XH], cpustate->ram[XL]);break;
281		case CPUINFO_STR_REGISTER + SC61860_Y:      sprintf(info->s, "Y: %.2x%.2x", cpustate->ram[YH], cpustate->ram[YL]);break;
282		case CPUINFO_STR_REGISTER + SC61860_CARRY:  sprintf(info->s, "Carry: %d", cpustate->carry);break;
283		case CPUINFO_STR_REGISTER + SC61860_ZERO:   sprintf(info->s, "Zero: %d", cpustate->zero);break;
284		}
	244	#if 0
	245	/* Are we in HLT-mode? */
	246	if (m_c & 4)
	247	{
	248	if (((m_ina()!=0)) || m_timer.t512ms)
	249	{
	250	m_c&=0xfb;
	251	m_outc(m_c);
	252	}
	253	m_icount-=4;
	254	}
	255	else if(m_c & 8) {}
	256
	257	else sc61860_instruction();
	258	#endif
	259
	260	} while (m_icount > 0);
285	261	}
286	262
287		DEFINE_LEGACY_CPU_DEVICE(SC61860, sc61860);

trunk/src/mess/drivers/pocketc.c

r26784	r26785
708	708	GFXDECODE_ENTRY( "gfx1", 0x0000, pc1251_charlayout, 0, 8 )
709	709	GFXDECODE_END
710	710
711		static const sc61860_cpu_core pc1401_config =
712		{
713		DEVCB_DRIVER_LINE_MEMBER(pc1401_state,pc1401_reset), DEVCB_DRIVER_LINE_MEMBER(pc1401_state,pc1401_brk), DEVCB_NULL,
714		DEVCB_DRIVER_MEMBER(pc1401_state,pc1401_ina), DEVCB_DRIVER_MEMBER(pc1401_state,pc1401_outa),
715		DEVCB_DRIVER_MEMBER(pc1401_state,pc1401_inb), DEVCB_DRIVER_MEMBER(pc1401_state,pc1401_outb),
716		DEVCB_DRIVER_MEMBER(pc1401_state,pc1401_outc)
717		};
718
719	711	static MACHINE_CONFIG_FRAGMENT( pocketc )
720	712	MCFG_QUANTUM_TIME(attotime::from_hz(60))
721	713
r26784	r26785
746	738	static MACHINE_CONFIG_START( pc1401, pc1401_state )
747	739	MCFG_CPU_ADD("maincpu", SC61860, 192000)        /* 7.8336 MHz */
748	740	MCFG_CPU_PROGRAM_MAP(pc1401_mem)
749		MCFG_CPU_CONFIG(pc1401_config)
	741	MCFG_SC61860_CONFIG(
	742	READLINE(pc1401_state,pc1401_reset), READLINE(pc1401_state,pc1401_brk), NULL,
	743	READ8(pc1401_state,pc1401_ina), WRITE8(pc1401_state,pc1401_outa),
	744	READ8(pc1401_state,pc1401_inb), WRITE8(pc1401_state,pc1401_outb),
	745	WRITE8(pc1401_state,pc1401_outc)
	746	)
750	747
751	748	MCFG_FRAGMENT_ADD(pocketc)
752	749
r26784	r26785
759	756	MCFG_CPU_PROGRAM_MAP( pc1402_mem)
760	757	MACHINE_CONFIG_END
761	758
762		static const sc61860_cpu_core pc1251_config =
763		{
764		DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(pc1251_state,pc1251_brk), DEVCB_NULL,
765		DEVCB_DRIVER_MEMBER(pc1251_state,pc1251_ina), DEVCB_DRIVER_MEMBER(pc1251_state,pc1251_outa),
766		DEVCB_DRIVER_MEMBER(pc1251_state,pc1251_inb), DEVCB_DRIVER_MEMBER(pc1251_state,pc1251_outb),
767		DEVCB_DRIVER_MEMBER(pc1251_state,pc1251_outc)
768		};
769
770	759	static MACHINE_CONFIG_START( pc1250, pc1251_state )
771	760	MCFG_CPU_ADD("maincpu", SC61860, 192000)        /* 7.8336 MHz */
772	761	MCFG_CPU_PROGRAM_MAP( pc1250_mem)
773		MCFG_CPU_CONFIG( pc1251_config )
	762	MCFG_SC61860_CONFIG(
	763	NULL, READLINE(pc1251_state,pc1251_brk), NULL,
	764	READ8(pc1251_state,pc1251_ina), WRITE8(pc1251_state,pc1251_outa),
	765	READ8(pc1251_state,pc1251_inb), WRITE8(pc1251_state,pc1251_outb),
	766	WRITE8(pc1251_state,pc1251_outc)
	767	)
774	768
775	769	MCFG_FRAGMENT_ADD(pocketc)
776	770
r26784	r26785
804	798	MCFG_CPU_PROGRAM_MAP( pc1261_mem)
805	799	MACHINE_CONFIG_END
806	800
807		static const sc61860_cpu_core pc1350_config =
808		{
809		DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(pc1350_state,pc1350_brk), DEVCB_NULL,
810		DEVCB_DRIVER_MEMBER(pc1350_state,pc1350_ina), DEVCB_DRIVER_MEMBER(pc1350_state,pc1350_outa),
811		DEVCB_DRIVER_MEMBER(pc1350_state,pc1350_inb), DEVCB_DRIVER_MEMBER(pc1350_state,pc1350_outb),
812		DEVCB_DRIVER_MEMBER(pc1350_state,pc1350_outc)
813		};
814
815	801	static MACHINE_CONFIG_START( pc1350, pc1350_state )
816	802	MCFG_CPU_ADD("maincpu", SC61860, 192000)        /* 7.8336 MHz */
817	803	MCFG_CPU_PROGRAM_MAP( pc1350_mem)
818		MCFG_CPU_CONFIG( pc1350_config )
	804	MCFG_SC61860_CONFIG(
	805	NULL, READLINE(pc1350_state,pc1350_brk), NULL,
	806	READ8(pc1350_state,pc1350_ina), WRITE8(pc1350_state,pc1350_outa),
	807	READ8(pc1350_state,pc1350_inb), WRITE8(pc1350_state,pc1350_outb),
	808	WRITE8(pc1350_state,pc1350_outc)
	809	)
819	810
820	811	MCFG_FRAGMENT_ADD( pocketc )
821	812
r26784	r26785
835	826	MCFG_RAM_EXTRA_OPTIONS("12K,20K")
836	827	MACHINE_CONFIG_END
837	828
838		static const sc61860_cpu_core pc1403_config =
839		{
840		DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(pc1403_state,pc1403_brk), DEVCB_NULL,
841		DEVCB_DRIVER_MEMBER(pc1403_state,pc1403_ina), DEVCB_DRIVER_MEMBER(pc1403_state,pc1403_outa),
842		DEVCB_NULL, DEVCB_NULL,
843		DEVCB_DRIVER_MEMBER(pc1403_state,pc1403_outc)
844		};
845
846	829	static MACHINE_CONFIG_START( pc1403, pc1403_state )
847		MCFG_CPU_ADD("maincpu", SC61860, 192000)        /* 7.8336 MHz */
848		MCFG_CPU_PROGRAM_MAP(pc1401_mem)
849		MCFG_CPU_CONFIG(pc1401_config)
	830	MCFG_CPU_ADD( "maincpu", SC61860, 256000 )
	831	MCFG_CPU_PROGRAM_MAP( pc1403_mem)
	832	MCFG_SC61860_CONFIG(
	833	NULL, READLINE(pc1403_state,pc1403_brk), NULL,
	834	READ8(pc1403_state,pc1403_ina), WRITE8(pc1403_state,pc1403_outa),
	835	NULL, NULL,
	836	WRITE8(pc1403_state,pc1403_outc)
	837	)
850	838
851	839	MCFG_FRAGMENT_ADD( pocketc )
852	840
853		MCFG_CPU_REPLACE( "maincpu", SC61860, 256000 )
854		MCFG_CPU_PROGRAM_MAP( pc1403_mem)
855		MCFG_CPU_CONFIG( pc1403_config )
856
857	841	/*
858	842	aim: show sharp with keyboard
859	843	resolution depends on the dots of the lcd

trunk/src/mess/machine/pc1401.c

r26784	r26785
111	111
112	112	void pc1401_state::machine_start()
113	113	{
114		device_t *main_cpu = m_maincpu;
115	114	UINT8 *ram = memregion("maincpu")->base() + 0x2000;
116		UINT8 *cpu = sc61860_internal_ram(main_cpu);
	115	UINT8 *cpu = m_maincpu->internal_ram();
117	116
118	117	machine().device<nvram_device>("cpu_nvram")->set_base(cpu, 96);
119	118	machine().device<nvram_device>("ram_nvram")->set_base(ram, 0x2800);

trunk/src/mess/machine/pc1403.c

r26784	r26785
138	138
139	139	void pc1403_state::machine_start()
140	140	{
141		device_t *main_cpu = m_maincpu;
142	141	UINT8 *ram = memregion("maincpu")->base() + 0x8000;
143		UINT8 *cpu = sc61860_internal_ram(main_cpu);
	142	UINT8 *cpu = m_maincpu->internal_ram();
144	143
145	144	machine().device<nvram_device>("cpu_nvram")->set_base(cpu, 96);
146	145	machine().device<nvram_device>("ram_nvram")->set_base(ram, 0x8000);

trunk/src/mess/machine/pc1251.c

r26784	r26785
87	87
88	88	void pc1251_state::machine_start()
89	89	{
90		device_t *main_cpu = m_maincpu;
91	90	UINT8 *ram = memregion("maincpu")->base() + 0x8000;
92		UINT8 *cpu = sc61860_internal_ram(main_cpu);
	91	UINT8 *cpu = m_maincpu->internal_ram();
93	92
94	93	machine().device<nvram_device>("cpu_nvram")->set_base(cpu, 96);
95	94	machine().device<nvram_device>("ram_nvram")->set_base(ram, 0x4800);
r26784	r26785
97	96
98	97	MACHINE_START_MEMBER(pc1251_state,pc1260 )
99	98	{
100		device_t *main_cpu = m_maincpu;
101	99	UINT8 *ram = memregion("maincpu")->base() + 0x4000;
102		UINT8 *cpu = sc61860_internal_ram(main_cpu);
	100	UINT8 *cpu = m_maincpu->internal_ram();
103	101
104	102	machine().device<nvram_device>("cpu_nvram")->set_base(cpu, 96);
105	103	machine().device<nvram_device>("ram_nvram")->set_base(ram, 0x2800);

trunk/src/mess/machine/pc1350.c

r26784	r26785
125	125	space.nop_readwrite(0x2000, 0x3fff);
126	126	}
127	127
128		device_t *main_cpu = m_maincpu;
129	128	UINT8 *ram = memregion("maincpu")->base() + 0x2000;
130		UINT8 *cpu = sc61860_internal_ram(main_cpu);
	129	UINT8 *cpu = m_maincpu->internal_ram();
131	130
132	131	machine().device<nvram_device>("cpu_nvram")->set_base(cpu, 96);
133	132	machine().device<nvram_device>("ram_nvram")->set_base(ram, 0x5000);

trunk/src/mess/includes/pc1251.h

r26784	r26785
9	9	#ifndef PC1251_H_
10	10	#define PC1251_H_
11	11
	12	#include "cpu/sc61860/sc61860.h"
12	13	#include "machine/nvram.h"
13	14
14	15	#define PC1251_CONTRAST (ioport("DSW0")->read() & 0x07)
r26784	r26785
45	46	DECLARE_WRITE8_MEMBER(pc1251_lcd_write);
46	47	virtual void machine_start();
47	48	DECLARE_MACHINE_START(pc1260);
48		required_device<cpu_device> m_maincpu;
	49	required_device<sc61860_device> m_maincpu;
49	50
50	51	protected:
51	52	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);

trunk/src/mess/includes/pc1401.h

r26784	r26785
9	9	#ifndef PC1401_H_
10	10	#define PC1401_H_
11	11
	12	#include "cpu/sc61860/sc61860.h"
12	13	#include "machine/nvram.h"
13	14
14	15	#define CONTRAST (ioport("DSW0")->read() & 0x07)
r26784	r26785
44	45	DECLARE_WRITE8_MEMBER(pc1401_lcd_write);
45	46
46	47	virtual void machine_start();
47		required_device<cpu_device> m_maincpu;
	48	required_device<sc61860_device> m_maincpu;
48	49
49	50	protected:
50	51	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);

trunk/src/mess/includes/pc1350.h

r26784	r26785
9	9	#ifndef PC1350_H_
10	10	#define PC1350_H_
11	11
	12	#include "cpu/sc61860/sc61860.h"
12	13	#include "machine/nvram.h"
13	14	#include "machine/ram.h"
14	15
r26784	r26785
46	47	DECLARE_READ8_MEMBER(pc1350_keyboard_line_r);
47	48
48	49	virtual void machine_start();
49		required_device<cpu_device> m_maincpu;
	50	required_device<sc61860_device> m_maincpu;
50	51	required_device<ram_device> m_ram;
51	52
52	53	protected:

trunk/src/mess/includes/pc1403.h

r26784	r26785
9	9	#ifndef PC1403_H_
10	10	#define PC1403_H_
11	11
	12	#include "cpu/sc61860/sc61860.h"
12	13	#include "machine/nvram.h"
13	14
14	15	#define CONTRAST (ioport("DSW0")->read() & 0x07)
r26784	r26785
48	49	DECLARE_WRITE8_MEMBER(pc1403_lcd_write);
49	50	virtual void video_start();
50	51	virtual void machine_start();
51		required_device<cpu_device> m_maincpu;
	52	required_device<sc61860_device> m_maincpu;
52	53
53	54	protected:
54	55	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team