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r26753 Wednesday 25th December, 2013 at 19:39:13 UTC by Wilbert Pol
superfx.c: Modernized cpu core.  [Wilbert Pol]

[src/emu/cpu/superfx]	superfx.c superfx.h
[src/mess/machine]	sns_sfx.c sns_sfx.h

trunk/src/emu/cpu/superfx/superfx.c

r26752	r26753
2	2	#include "debugger.h"
3	3	#include "superfx.h"
4	4
5		struct pixelcache_t
6		{
7		UINT16 offset;
8		UINT8 bitpend;
9		UINT8 data[8];
10		};
11	5
12		struct cache_t
13		{
14		UINT8 buffer[0x200];
15		UINT8 valid[0x20];
16		};
	6	const device_type SUPERFX = &device_creator<superfx_device>;
17	7
18		struct superfx_state
	8	superfx_device::superfx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	9	: cpu_device(mconfig, SUPERFX, "SuperFX", tag, owner, clock, "superfx", __FILE__)
	10	, m_program_config("program", ENDIANNESS_LITTLE, 8, 32, 0)
	11	, m_out_irq_func(*this)
19	12	{
20		superfx_config config;
21
22		devcb_resolved_write_line   out_irq_func;
23
24		UINT8  pipeline;
25		UINT16 ramaddr; // RAM Address
26
27		UINT16 r[16];   // GPRs
28		UINT16 sfr;     // Status Flag Register
29		UINT8  pbr;     // Program Bank Register
30		UINT8  rombr;   // Game Pack ROM Bank Register
31		UINT8  rambr;   // Game Pack RAM Bank Register
32		UINT16 cbr;     // Cache Base Register
33		UINT8  scbr;    // Screen Base Register
34		UINT8  scmr;    // Screen Mode Register
35		UINT8  colr;    // Color Register
36		UINT8  por;     // Plot Option Register
37		UINT8  bramr;   // Back-Up RAM Register
38		UINT8  vcr;     // Version Code Register
39		UINT8  cfgr;    // Config Register
40		UINT8  clsr;    // Clock Select Register
41
42		UINT32 romcl;   // Clock ticks until ROMDR is valid
43		UINT8  romdr;   // ROM Buffer Data Register
44
45		UINT32 ramcl;   // Clock ticks until RAMDR is valid;
46		UINT16 ramar;   // RAM Buffer Address Register
47		UINT8  ramdr;   // RAM Buffer Data Register
48
49		UINT16 *sreg;   // Source Register (From)
50		UINT8  sreg_idx;// Source Register (To), index
51		UINT16 *dreg;   // Destination Register (To)
52		UINT8  dreg_idx;// Destination Register (To), index
53		UINT8  r15_modified;
54
55		UINT8  irq;     // IRQ Pending
56
57		UINT32 cache_access_speed;
58		UINT32 memory_access_speed;
59
60		cache_t cache;
61		pixelcache_t pixelcache[2];
62
63		legacy_cpu_device *device;
64		address_space *program;
65		int icount;
66		};
67
68		INLINE superfx_state *get_safe_token(device_t *device)
69		{
70		assert(device != NULL);
71		assert(device->type() == SUPERFX);
72		return (superfx_state *)downcast<legacy_cpu_device *>(device)->token();
73	13	}
74	14
75		/*****************************************************************************/
76	15
77		INLINE void superfx_regs_reset(superfx_state *cpustate);
78		static void superfx_update_speed(superfx_state *cpustate);
79		static void superfx_cache_flush(superfx_state *cpustate);
80		static UINT8 superfx_cache_mmio_read(superfx_state *cpustate, UINT32 addr);
81		static void superfx_cache_mmio_write(superfx_state *cpustate, UINT32 addr, UINT8 data);
82		static void superfx_memory_reset(superfx_state *cpustate);
83		INLINE UINT8 superfx_bus_read(superfx_state *cpustate, UINT32 addr);
84		INLINE void superfx_bus_write(superfx_state *cpustate, UINT32 addr, UINT8 data);
85		INLINE void superfx_pixelcache_flush(superfx_state *cpustate, INT32 line);
86		INLINE void superfx_plot(superfx_state *cpustate, UINT8 x, UINT8 y);
87		static UINT8 superfx_rpix(superfx_state *cpustate, UINT8 r1, UINT8 r2);
88		INLINE UINT8 superfx_color(superfx_state *cpustate, UINT8 source);
	16	#define SUPERFX_SFR_OV_SET      ((m_sfr & SUPERFX_SFR_OV) ? 1 : 0)
	17	#define SUPERFX_SFR_OV_CLEAR    ((m_sfr & SUPERFX_SFR_OV) ? 0 : 1)
	18	#define SUPERFX_SFR_S_SET       ((m_sfr & SUPERFX_SFR_S) ? 1 : 0)
	19	#define SUPERFX_SFR_S_CLEAR     ((m_sfr & SUPERFX_SFR_S) ? 0 : 1)
	20	#define SUPERFX_SFR_CY_SET      ((m_sfr & SUPERFX_SFR_CY) ? 1 : 0)
	21	#define SUPERFX_SFR_CY_CLEAR    ((m_sfr & SUPERFX_SFR_CY) ? 0 : 1)
	22	#define SUPERFX_SFR_Z_SET       ((m_sfr & SUPERFX_SFR_Z) ? 1 : 0)
	23	#define SUPERFX_SFR_Z_CLEAR     ((m_sfr & SUPERFX_SFR_Z) ? 0 : 1)
89	24
90		INLINE void superfx_rambuffer_sync(superfx_state *cpustate);
91		INLINE UINT8 superfx_rambuffer_read(superfx_state *cpustate, UINT16 addr);
92		INLINE void superfx_rambuffer_write(superfx_state *cpustate, UINT16 addr, UINT8 val);
93	25
94		INLINE void superfx_rombuffer_sync(superfx_state *cpustate);
95		INLINE void superfx_rombuffer_update(superfx_state *cpustate);
96		INLINE UINT8 superfx_rombuffer_read(superfx_state *cpustate);
97
98		INLINE void superfx_gpr_write(superfx_state *cpustate, UINT8 r, UINT16 data);
99		INLINE UINT8 superfx_op_read(superfx_state *cpustate, UINT16 addr);
100		INLINE UINT8 superfx_peekpipe(superfx_state *cpustate);
101		INLINE UINT8 superfx_pipe(superfx_state *cpustate);
102		INLINE void superfx_add_clocks_internal(superfx_state *cpustate, UINT32 clocks);
103		static void superfx_timing_reset(superfx_state *cpustate);
104
105		/*****************************************************************************/
106
107		#define SUPERFX_SFR_OV_SET      ((cpustate->sfr & SUPERFX_SFR_OV) ? 1 : 0)
108		#define SUPERFX_SFR_OV_CLEAR    ((cpustate->sfr & SUPERFX_SFR_OV) ? 0 : 1)
109		#define SUPERFX_SFR_S_SET       ((cpustate->sfr & SUPERFX_SFR_S) ? 1 : 0)
110		#define SUPERFX_SFR_S_CLEAR     ((cpustate->sfr & SUPERFX_SFR_S) ? 0 : 1)
111		#define SUPERFX_SFR_CY_SET      ((cpustate->sfr & SUPERFX_SFR_CY) ? 1 : 0)
112		#define SUPERFX_SFR_CY_CLEAR    ((cpustate->sfr & SUPERFX_SFR_CY) ? 0 : 1)
113		#define SUPERFX_SFR_Z_SET       ((cpustate->sfr & SUPERFX_SFR_Z) ? 1 : 0)
114		#define SUPERFX_SFR_Z_CLEAR     ((cpustate->sfr & SUPERFX_SFR_Z) ? 0 : 1)
115
116		INLINE void superfx_regs_reset(superfx_state *cpustate)
	26	void superfx_device::superfx_regs_reset()
117	27	{
118		cpustate->sfr &= ~(SUPERFX_SFR_B | SUPERFX_SFR_ALT3);
	28	m_sfr &= ~(SUPERFX_SFR_B | SUPERFX_SFR_ALT3);
119	29
120		cpustate->sreg = &cpustate->r[0];
121		cpustate->dreg = &cpustate->r[0];
122		cpustate->dreg_idx = 0;
123		cpustate->sreg_idx = 0;
	30	m_sreg = &m_r[0];
	31	m_dreg = &m_r[0];
	32	m_dreg_idx = 0;
	33	m_sreg_idx = 0;
124	34	}
125	35
126		static void superfx_update_speed(superfx_state *cpustate)
	36	void superfx_device::superfx_update_speed()
127	37	{
128		cpustate->cache_access_speed = (cpustate->clsr ? 1 : 2);
129		cpustate->memory_access_speed = (cpustate->clsr ? 5 : 6);
130		if(cpustate->clsr)
	38	m_cache_access_speed = (m_clsr ? 1 : 2);
	39	m_memory_access_speed = (m_clsr ? 5 : 6);
	40	if(m_clsr)
131	41	{
132		cpustate->cfgr &= ~SUPERFX_CFGR_MS0; // Cannot use high-speed multiplication in 21MHz mode
	42	m_cfgr &= ~SUPERFX_CFGR_MS0; // Cannot use high-speed multiplication in 21MHz mode
133	43	}
134	44	}
135	45
136		static void superfx_cache_flush(superfx_state *cpustate)
	46	void superfx_device::superfx_cache_flush()
137	47	{
138	48	UINT32 n = 0;
139	49	for(n = 0; n < 32; n++)
140	50	{
141		cpustate->cache.valid[n] = 0;
	51	m_cache.valid[n] = 0;
142	52	}
143	53	}
144	54
145		static UINT8 superfx_cache_mmio_read(superfx_state *cpustate, UINT32 addr)
	55	UINT8 superfx_device::superfx_cache_mmio_read(UINT32 addr)
146	56	{
147		addr = (addr + cpustate->cbr) & 0x1ff;
148		return cpustate->cache.buffer[addr];
	57	addr = (addr + m_cbr) & 0x1ff;
	58	return m_cache.buffer[addr];
149	59	}
150	60
151		static void superfx_cache_mmio_write(superfx_state *cpustate, UINT32 addr, UINT8 data)
	61	void superfx_device::superfx_cache_mmio_write(UINT32 addr, UINT8 data)
152	62	{
153		addr = (addr + cpustate->cbr) & 0x1ff;
154		cpustate->cache.buffer[addr] = data;
	63	addr = (addr + m_cbr) & 0x1ff;
	64	m_cache.buffer[addr] = data;
155	65	if((addr & 15) == 15)
156	66	{
157		cpustate->cache.valid[addr >> 4] = 1;
	67	m_cache.valid[addr >> 4] = 1;
158	68	}
159	69	}
160	70
161		static void superfx_memory_reset(superfx_state *cpustate)
	71	void superfx_device::superfx_memory_reset()
162	72	{
163	73	UINT32 n = 0;
164	74	for(n = 0; n < 0x200; n++)
165	75	{
166		cpustate->cache.buffer[n] = 0x00;
	76	m_cache.buffer[n] = 0x00;
167	77	}
168	78	for(n = 0; n < 0x20; n++)
169	79	{
170		cpustate->cache.valid[n] = 0;
	80	m_cache.valid[n] = 0;
171	81	}
172	82	for(n = 0; n < 2; n++)
173	83	{
174		cpustate->pixelcache[n].offset = ~0;
175		cpustate->pixelcache[n].bitpend = 0x00;
	84	m_pixelcache[n].offset = ~0;
	85	m_pixelcache[n].bitpend = 0x00;
176	86	}
177	87	}
178	88
179		INLINE UINT8 superfx_bus_read(superfx_state *cpustate, UINT32 addr)
	89	UINT8 superfx_device::superfx_bus_read(UINT32 addr)
180	90	{
181		return cpustate->program->read_byte(addr);
	91	return m_program->read_byte(addr);
182	92	}
183	93
184		INLINE void superfx_bus_write(superfx_state *cpustate, UINT32 addr, UINT8 data)
	94	void superfx_device::superfx_bus_write(UINT32 addr, UINT8 data)
185	95	{
186		cpustate->program->write_byte(addr, data);
	96	m_program->write_byte(addr, data);
187	97	}
188	98
189		INLINE void superfx_pixelcache_flush(superfx_state *cpustate, INT32 line)
	99	void superfx_device::superfx_pixelcache_flush(INT32 line)
190	100	{
191		UINT8 x = cpustate->pixelcache[line].offset << 3;
192		UINT8 y = cpustate->pixelcache[line].offset >> 5;
	101	UINT8 x = m_pixelcache[line].offset << 3;
	102	UINT8 y = m_pixelcache[line].offset >> 5;
193	103	UINT32 cn = 0;
194		UINT32 bpp = 2 << ((cpustate->scmr & SUPERFX_SCMR_MD) - ((cpustate->scmr & SUPERFX_SCMR_MD) >> 1)); // = [regs.scmr.md]{ 2, 4, 4, 8 };
	104	UINT32 bpp = 2 << ((m_scmr & SUPERFX_SCMR_MD) - ((m_scmr & SUPERFX_SCMR_MD) >> 1)); // = [regs.scmr.md]{ 2, 4, 4, 8 };
195	105	UINT32 addr = 0;
196	106	UINT32 n = 0;
197	107
198		if(cpustate->pixelcache[line].bitpend == 0x00)
	108	if(m_pixelcache[line].bitpend == 0x00)
199	109	{
200	110	return;
201	111	}
202	112
203		switch(((cpustate->por & SUPERFX_POR_OBJ) ? SUPERFX_SCMR_HT3 : (cpustate->scmr & SUPERFX_SCMR_HT_MASK)))
	113	switch(((m_por & SUPERFX_POR_OBJ) ? SUPERFX_SCMR_HT3 : (m_scmr & SUPERFX_SCMR_HT_MASK)))
204	114	{
205	115	case SUPERFX_SCMR_HT0:
206	116	cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 3);
r26752	r26753
216	126	break;
217	127	}
218	128
219		addr = 0x700000 + (cn * (bpp << 3)) + (cpustate->scbr << 10) + ((y & 0x07) * 2);
	129	addr = 0x700000 + (cn * (bpp << 3)) + (m_scbr << 10) + ((y & 0x07) * 2);
220	130
221	131	for(n = 0; n < bpp; n++)
222	132	{
r26752	r26753
225	135	UINT32 x32 = 0;
226	136	for(x32 = 0; x32 < 8; x32++)
227	137	{
228		data |= ((cpustate->pixelcache[line].data[x32] >> n) & 1) << x32;
	138	data |= ((m_pixelcache[line].data[x32] >> n) & 1) << x32;
229	139	}
230		if(cpustate->pixelcache[line].bitpend != 0xff)
	140	if(m_pixelcache[line].bitpend != 0xff)
231	141	{
232		superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
233		data &= cpustate->pixelcache[line].bitpend;
234		data |= superfx_bus_read(cpustate, addr + byte) & ~cpustate->pixelcache[line].bitpend;
	142	superfx_add_clocks_internal(m_memory_access_speed);
	143	data &= m_pixelcache[line].bitpend;
	144	data |= superfx_bus_read(addr + byte) & ~m_pixelcache[line].bitpend;
235	145	}
236		superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
237		superfx_bus_write(cpustate, addr + byte, data);
	146	superfx_add_clocks_internal(m_memory_access_speed);
	147	superfx_bus_write(addr + byte, data);
238	148	}
239	149
240		cpustate->pixelcache[line].bitpend = 0x00;
	150	m_pixelcache[line].bitpend = 0x00;
241	151	}
242	152
243		INLINE void superfx_plot(superfx_state *cpustate, UINT8 x, UINT8 y)
	153	void superfx_device::superfx_plot(UINT8 x, UINT8 y)
244	154	{
245		UINT8 color = cpustate->colr;
	155	UINT8 color = m_colr;
246	156	UINT16 offset = (y << 5) + (x >> 3);
247	157
248		if((cpustate->por & SUPERFX_POR_DITHER) != 0 && (cpustate->scmr & SUPERFX_SCMR_MD) != 3)
	158	if((m_por & SUPERFX_POR_DITHER) != 0 && (m_scmr & SUPERFX_SCMR_MD) != 3)
249	159	{
250	160	if((x ^ y) & 1)
251	161	{
r26752	r26753
254	164	color &= 0x0f;
255	165	}
256	166
257		if((cpustate->por & SUPERFX_POR_TRANSPARENT) == 0)
	167	if((m_por & SUPERFX_POR_TRANSPARENT) == 0)
258	168	{
259		if((cpustate->scmr & SUPERFX_SCMR_MD) == 3)
	169	if((m_scmr & SUPERFX_SCMR_MD) == 3)
260	170	{
261		if(cpustate->por & SUPERFX_POR_FREEZEHIGH)
	171	if(m_por & SUPERFX_POR_FREEZEHIGH)
262	172	{
263	173	if((color & 0x0f) == 0)
264	174	{
r26752	r26753
282	192	}
283	193	}
284	194
285		if(offset != cpustate->pixelcache[0].offset)
	195	if(offset != m_pixelcache[0].offset)
286	196	{
287		superfx_pixelcache_flush(cpustate, 1);
288		cpustate->pixelcache[1] = cpustate->pixelcache[0];
289		cpustate->pixelcache[0].bitpend = 0x00;
290		cpustate->pixelcache[0].offset = offset;
	197	superfx_pixelcache_flush(1);
	198	m_pixelcache[1] = m_pixelcache[0];
	199	m_pixelcache[0].bitpend = 0x00;
	200	m_pixelcache[0].offset = offset;
291	201	}
292	202
293	203	x = (x & 7) ^ 7;
294		cpustate->pixelcache[0].data[x] = color;
295		cpustate->pixelcache[0].bitpend |= 1 << x;
296		if(cpustate->pixelcache[0].bitpend == 0xff)
	204	m_pixelcache[0].data[x] = color;
	205	m_pixelcache[0].bitpend |= 1 << x;
	206	if(m_pixelcache[0].bitpend == 0xff)
297	207	{
298		superfx_pixelcache_flush(cpustate, 1);
299		cpustate->pixelcache[1] = cpustate->pixelcache[0];
300		cpustate->pixelcache[0].bitpend = 0x00;
	208	superfx_pixelcache_flush(1);
	209	m_pixelcache[1] = m_pixelcache[0];
	210	m_pixelcache[0].bitpend = 0x00;
301	211	}
302	212	}
303	213
304		static UINT8 superfx_rpix(superfx_state *cpustate, UINT8 x, UINT8 y)
	214	UINT8 superfx_device::superfx_rpix(UINT8 x, UINT8 y)
305	215	{
306	216	UINT32 cn = 0;
307	217	UINT32 bpp = 0;
r26752	r26753
309	219	UINT8 data = 0x00;
310	220	UINT32 n = 0;
311	221
312		superfx_pixelcache_flush(cpustate, 1);
313		superfx_pixelcache_flush(cpustate, 0);
	222	superfx_pixelcache_flush(1);
	223	superfx_pixelcache_flush(0);
314	224
315		bpp = 2 << ((cpustate->scmr & SUPERFX_SCMR_MD) - ((cpustate->scmr & SUPERFX_SCMR_MD) >> 1)); // = [regs.scmr.md]{ 2, 4, 4, 8 };
	225	bpp = 2 << ((m_scmr & SUPERFX_SCMR_MD) - ((m_scmr & SUPERFX_SCMR_MD) >> 1)); // = [regs.scmr.md]{ 2, 4, 4, 8 };
316	226
317		switch((cpustate->por & SUPERFX_POR_OBJ) ? SUPERFX_SCMR_HT3 : (cpustate->scmr & SUPERFX_SCMR_HT_MASK))
	227	switch((m_por & SUPERFX_POR_OBJ) ? SUPERFX_SCMR_HT3 : (m_scmr & SUPERFX_SCMR_HT_MASK))
318	228	{
319	229	case SUPERFX_SCMR_HT0:
320	230	cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 3);
r26752	r26753
330	240	break;
331	241	}
332	242
333		addr = 0x700000 + (cn * (bpp << 3)) + (cpustate->scbr << 10) + ((y & 0x07) * 2);
	243	addr = 0x700000 + (cn * (bpp << 3)) + (m_scbr << 10) + ((y & 0x07) * 2);
334	244	x = (x & 7) ^ 7;
335	245
336	246	for(n = 0; n < bpp; n++)
337	247	{
338	248	UINT32 byte = ((n >> 1) << 4) + (n & 1);  // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
339		superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
340		data |= ((superfx_bus_read(cpustate, addr + byte) >> x) & 1) << n;
	249	superfx_add_clocks_internal(m_memory_access_speed);
	250	data |= ((superfx_bus_read(addr + byte) >> x) & 1) << n;
341	251	}
342	252
343	253	return data;
344	254	}
345	255
346		INLINE UINT8 superfx_color(superfx_state *cpustate, UINT8 source)
	256	UINT8 superfx_device::superfx_color(UINT8 source)
347	257	{
348		if(cpustate->por & SUPERFX_POR_HIGHNIBBLE)
	258	if(m_por & SUPERFX_POR_HIGHNIBBLE)
349	259	{
350		return (cpustate->colr & 0xf0) | (source >> 4);
	260	return (m_colr & 0xf0) | (source >> 4);
351	261	}
352		if(cpustate->por & SUPERFX_POR_FREEZEHIGH)
	262	if(m_por & SUPERFX_POR_FREEZEHIGH)
353	263	{
354		return (cpustate->colr & 0xf0) | (source & 0x0f);
	264	return (m_colr & 0xf0) | (source & 0x0f);
355	265	}
356	266	return source;
357	267	}
358	268
359		INLINE void superfx_rambuffer_sync(superfx_state *cpustate)
	269	void superfx_device::superfx_rambuffer_sync()
360	270	{
361		if(cpustate->ramcl)
	271	if(m_ramcl)
362	272	{
363		superfx_add_clocks_internal(cpustate, cpustate->ramcl);
	273	superfx_add_clocks_internal(m_ramcl);
364	274	}
365	275	}
366	276
367		INLINE UINT8 superfx_rambuffer_read(superfx_state *cpustate, UINT16 addr)
	277	UINT8 superfx_device::superfx_rambuffer_read(UINT16 addr)
368	278	{
369		superfx_rambuffer_sync(cpustate);
370		return superfx_bus_read(cpustate, 0x700000 + (cpustate->rambr << 16) + addr);
	279	superfx_rambuffer_sync();
	280	return superfx_bus_read(0x700000 + (m_rambr << 16) + addr);
371	281	}
372	282
373		INLINE void superfx_rambuffer_write(superfx_state *cpustate, UINT16 addr, UINT8 data)
	283	void superfx_device::superfx_rambuffer_write(UINT16 addr, UINT8 data)
374	284	{
375		superfx_rambuffer_sync(cpustate);
376		cpustate->ramcl = cpustate->memory_access_speed;
377		cpustate->ramar = addr;
378		cpustate->ramdr = data;
	285	superfx_rambuffer_sync();
	286	m_ramcl = m_memory_access_speed;
	287	m_ramar = addr;
	288	m_ramdr = data;
379	289	}
380	290
381		INLINE void superfx_rombuffer_sync(superfx_state *cpustate)
	291	void superfx_device::superfx_rombuffer_sync()
382	292	{
383		if(cpustate->romcl)
	293	if(m_romcl)
384	294	{
385		superfx_add_clocks_internal(cpustate, cpustate->romcl);
	295	superfx_add_clocks_internal(m_romcl);
386	296	}
387	297	}
388	298
389		INLINE void superfx_rombuffer_update(superfx_state *cpustate)
	299	void superfx_device::superfx_rombuffer_update()
390	300	{
391		cpustate->sfr |= SUPERFX_SFR_R;
392		cpustate->romcl = cpustate->memory_access_speed;
	301	m_sfr |= SUPERFX_SFR_R;
	302	m_romcl = m_memory_access_speed;
393	303	}
394	304
395		INLINE UINT8 superfx_rombuffer_read(superfx_state *cpustate)
	305	UINT8 superfx_device::superfx_rombuffer_read()
396	306	{
397		superfx_rombuffer_sync(cpustate);
398		return cpustate->romdr;
	307	superfx_rombuffer_sync();
	308	return m_romdr;
399	309	}
400	310
401		INLINE void superfx_gpr_write(superfx_state *cpustate, UINT8 r, UINT16 data)
	311	void superfx_device::superfx_gpr_write(UINT8 r, UINT16 data)
402	312	{
403		cpustate->r[r] = data;
	313	m_r[r] = data;
404	314	if(r == 14)
405	315	{
406		superfx_rombuffer_update(cpustate);
	316	superfx_rombuffer_update();
407	317	}
408	318	else if(r == 15)
409	319	{
410		cpustate->r15_modified = 1;
	320	m_r15_modified = 1;
411	321	}
412	322	}
413	323
414		INLINE UINT8 superfx_op_read(superfx_state *cpustate, UINT16 addr)
	324	UINT8 superfx_device::superfx_op_read(UINT16 addr)
415	325	{
416		UINT16 offset = addr - cpustate->cbr;
	326	UINT16 offset = addr - m_cbr;
417	327	if(offset < 512)
418	328	{
419		if(!cpustate->cache.valid[offset >> 4])
	329	if(!m_cache.valid[offset >> 4])
420	330	{
421	331	UINT32 dp = offset & 0xfff0;
422		UINT32 sp = (cpustate->pbr << 16) + ((cpustate->cbr + dp) & 0xfff0);
	332	UINT32 sp = (m_pbr << 16) + ((m_cbr + dp) & 0xfff0);
423	333	UINT32 n = 0;
424	334	for(n = 0; n < 16; n++)
425	335	{
426		superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
427		cpustate->cache.buffer[dp++] = superfx_bus_read(cpustate, sp++);
	336	superfx_add_clocks_internal(m_memory_access_speed);
	337	m_cache.buffer[dp++] = superfx_bus_read(sp++);
428	338	}
429		cpustate->cache.valid[offset >> 4] = 1;
	339	m_cache.valid[offset >> 4] = 1;
430	340	}
431	341	else
432	342	{
433		superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
	343	superfx_add_clocks_internal(m_memory_access_speed);
434	344	}
435		return cpustate->cache.buffer[offset];
	345	return m_cache.buffer[offset];
436	346	}
437	347
438		if(cpustate->pbr <= 0x5f)
	348	if(m_pbr <= 0x5f)
439	349	{
440	350	//$[00-5f]:[0000-ffff] ROM
441		superfx_rombuffer_sync(cpustate);
442		superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
443		return superfx_bus_read(cpustate, (cpustate->pbr << 16) + addr);
	351	superfx_rombuffer_sync();
	352	superfx_add_clocks_internal(m_memory_access_speed);
	353	return superfx_bus_read((m_pbr << 16) + addr);
444	354	}
445	355	else
446	356	{
447	357	//$[60-7f]:[0000-ffff] RAM
448		superfx_rambuffer_sync(cpustate);
449		superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
450		return superfx_bus_read(cpustate, (cpustate->pbr << 16) + addr);
	358	superfx_rambuffer_sync();
	359	superfx_add_clocks_internal(m_memory_access_speed);
	360	return superfx_bus_read((m_pbr << 16) + addr);
451	361	}
452	362	}
453	363
454		INLINE UINT8 superfx_peekpipe(superfx_state *cpustate)
	364	UINT8 superfx_device::superfx_peekpipe()
455	365	{
456		UINT8 result = cpustate->pipeline;
457		cpustate->pipeline = superfx_op_read(cpustate, cpustate->r[15]);
458		cpustate->r15_modified = 0;
	366	UINT8 result = m_pipeline;
	367	m_pipeline = superfx_op_read(m_r[15]);
	368	m_r15_modified = 0;
459	369	return result;
460	370	}
461	371
462		INLINE UINT8 superfx_pipe(superfx_state *cpustate)
	372	UINT8 superfx_device::superfx_pipe()
463	373	{
464		UINT8 result = cpustate->pipeline;
465		cpustate->pipeline = superfx_op_read(cpustate, ++cpustate->r[15]);
466		cpustate->r15_modified = 0;
	374	UINT8 result = m_pipeline;
	375	m_pipeline = superfx_op_read(++m_r[15]);
	376	m_r15_modified = 0;
467	377	return result;
468	378	}
469	379
470	380	/*****************************************************************************/
471	381
472	382	/* reads to SuperFX RAM only happen if this returns 1 */
473		int superfx_access_ram(device_t *cpu)
	383	int superfx_device::access_ram()
474	384	{
475		superfx_state *cpustate = get_safe_token(cpu);
476
477		if ((cpustate->sfr & SUPERFX_SFR_G) && (cpustate->scmr & SUPERFX_SCMR_RAN))
	385	if ((m_sfr & SUPERFX_SFR_G) && (m_scmr & SUPERFX_SCMR_RAN))
478	386	return 0;
479	387
480	388	return 1;
481	389	}
482	390
483	391	/* reads to SuperFX ROM only happen if this returns 1 */
484		int superfx_access_rom(device_t *cpu)
	392	int superfx_device::access_rom()
485	393	{
486		superfx_state *cpustate = get_safe_token(cpu);
487
488		if ((cpustate->sfr & SUPERFX_SFR_G) && (cpustate->scmr & SUPERFX_SCMR_RON))
	394	if ((m_sfr & SUPERFX_SFR_G) && (m_scmr & SUPERFX_SCMR_RON))
489	395	return 0;
490	396
491	397	return 1;
492	398	}
493	399
494		UINT8 superfx_mmio_read(device_t *cpu, UINT32 addr)
	400	UINT8 superfx_device::mmio_read(UINT32 addr)
495	401	{
496		superfx_state *cpustate = get_safe_token(cpu);
497
498	402	addr &= 0xffff;
499	403
500	404	if(addr >= 0x3100 && addr <= 0x32ff)
501	405	{
502		return superfx_cache_mmio_read(cpustate, addr - 0x3100);
	406	return superfx_cache_mmio_read(addr - 0x3100);
503	407	}
504	408
505	409	if(addr >= 0x3000 && addr <= 0x301f)
506	410	{
507		return cpustate->r[(addr >> 1) & 0xf] >> ((addr & 1) << 3);
	411	return m_r[(addr >> 1) & 0xf] >> ((addr & 1) << 3);
508	412	}
509	413
510	414	switch(addr)
511	415	{
512	416	case 0x3030:
513		return cpustate->sfr >> 0;
	417	return m_sfr >> 0;
514	418
515	419	case 0x3031:
516	420	{
517		UINT8 r = cpustate->sfr >> 8;
518		cpustate->sfr &= ~SUPERFX_SFR_IRQ;
519		cpustate->irq = 0;
520		cpustate->out_irq_func(cpustate->irq);
	421	UINT8 r = m_sfr >> 8;
	422	m_sfr &= ~SUPERFX_SFR_IRQ;
	423	m_irq = 0;
	424	m_out_irq_func(m_irq);
521	425	return r;
522	426	}
523	427
524	428	case 0x3034:
525		return cpustate->pbr;
	429	return m_pbr;
526	430
527	431	case 0x3036:
528		return cpustate->rombr;
	432	return m_rombr;
529	433
530	434	case 0x303b:
531		return cpustate->vcr;
	435	return m_vcr;
532	436
533	437	case 0x303c:
534		return cpustate->rambr;
	438	return m_rambr;
535	439
536	440	case 0x303e:
537		return cpustate->cbr >> 0;
	441	return m_cbr >> 0;
538	442
539	443	case 0x303f:
540		return cpustate->cbr >> 8;
	444	return m_cbr >> 8;
541	445	}
542	446
543	447	return 0;
544	448	}
545	449
546		void superfx_mmio_write(device_t *cpu, UINT32 addr, UINT8 data)
	450	void superfx_device::mmio_write(UINT32 addr, UINT8 data)
547	451	{
548		superfx_state *cpustate = get_safe_token(cpu);
549
550	452	addr &= 0xffff;
551	453
552	454	//printf( "superfx_mmio_write: %08x = %02x\n", addr, data );
553	455
554	456	if(addr >= 0x3100 && addr <= 0x32ff)
555	457	{
556		superfx_cache_mmio_write(cpustate, addr - 0x3100, data);
	458	superfx_cache_mmio_write(addr - 0x3100, data);
557	459	return;
558	460	}
559	461
r26752	r26753
562	464	UINT32 n = (addr >> 1) & 0xf;
563	465	if((addr & 1) == 0)
564	466	{
565		cpustate->r[n] = (cpustate->r[n] & 0xff00) | data;
	467	m_r[n] = (m_r[n] & 0xff00) | data;
566	468	}
567	469	else
568	470	{
569		cpustate->r[n] = (data << 8) | (cpustate->r[n] & 0xff);
	471	m_r[n] = (data << 8) | (m_r[n] & 0xff);
570	472	}
571	473
572	474	if(addr == 0x301f)
573	475	{
574		cpustate->sfr |= SUPERFX_SFR_G;
	476	m_sfr |= SUPERFX_SFR_G;
575	477	}
576	478	return;
577	479	}
r26752	r26753
580	482	{
581	483	case 0x3030:
582	484	{
583		UINT8 g = (cpustate->sfr & SUPERFX_SFR_G) ? 1 : 0;
584		cpustate->sfr = (cpustate->sfr & 0xff00) | (data << 0);
585		if(g == 1 && !(cpustate->sfr & SUPERFX_SFR_G))
	485	UINT8 g = (m_sfr & SUPERFX_SFR_G) ? 1 : 0;
	486	m_sfr = (m_sfr & 0xff00) | (data << 0);
	487	if(g == 1 && !(m_sfr & SUPERFX_SFR_G))
586	488	{
587		cpustate->cbr = 0x0000;
588		superfx_cache_flush(cpustate);
	489	m_cbr = 0x0000;
	490	superfx_cache_flush();
589	491	}
590	492	break;
591	493	}
592	494
593	495	case 0x3031:
594		cpustate->sfr = (data << 8) | (cpustate->sfr & 0x00ff);
	496	m_sfr = (data << 8) | (m_sfr & 0x00ff);
595	497	break;
596	498
597	499	case 0x3033:
598		cpustate->bramr = data & 1;
	500	m_bramr = data & 1;
599	501	break;
600	502
601	503	case 0x3034:
602		cpustate->pbr = data & 0x7f;
603		superfx_cache_flush(cpustate);
	504	m_pbr = data & 0x7f;
	505	superfx_cache_flush();
604	506	break;
605	507
606	508	case 0x3037:
607		cpustate->cfgr = data;
608		superfx_update_speed(cpustate);
	509	m_cfgr = data;
	510	superfx_update_speed();
609	511	break;
610	512
611	513	case 0x3038:
612		cpustate->scbr = data;
	514	m_scbr = data;
613	515	break;
614	516
615	517	case 0x3039:
616		cpustate->clsr = data & 1;
617		superfx_update_speed(cpustate);
	518	m_clsr = data & 1;
	519	superfx_update_speed();
618	520	break;
619	521
620	522	case 0x303a:
621		cpustate->scmr = data;
	523	m_scmr = data;
622	524	break;
623	525	}
624	526	}
625	527
626		INLINE void superfx_add_clocks_internal(superfx_state *cpustate, UINT32 clocks)
	528	void superfx_device::superfx_add_clocks_internal(UINT32 clocks)
627	529	{
628		if(cpustate->romcl)
	530	if(m_romcl)
629	531	{
630		cpustate->romcl -= MIN(clocks, cpustate->romcl);
631		if(cpustate->romcl == 0)
	532	m_romcl -= MIN(clocks, m_romcl);
	533	if(m_romcl == 0)
632	534	{
633		cpustate->sfr &= ~SUPERFX_SFR_R;
634		cpustate->romdr = superfx_bus_read(cpustate, (cpustate->rombr << 16) + cpustate->r[14]);
	535	m_sfr &= ~SUPERFX_SFR_R;
	536	m_romdr = superfx_bus_read((m_rombr << 16) + m_r[14]);
635	537	}
636	538	}
637	539
638		if(cpustate->ramcl)
	540	if(m_ramcl)
639	541	{
640		cpustate->ramcl -= MIN(clocks, cpustate->ramcl);
641		if(cpustate->ramcl == 0)
	542	m_ramcl -= MIN(clocks, m_ramcl);
	543	if(m_ramcl == 0)
642	544	{
643		superfx_bus_write(cpustate, 0x700000 + (cpustate->rambr << 16) + cpustate->ramar, cpustate->ramdr);
	545	superfx_bus_write(0x700000 + (m_rambr << 16) + m_ramar, m_ramdr);
644	546	}
645	547	}
646	548	}
647	549
648		static void superfx_timing_reset(superfx_state *cpustate)
	550	void superfx_device::superfx_timing_reset()
649	551	{
650		superfx_update_speed(cpustate);
651		cpustate->r15_modified = 0;
	552	superfx_update_speed();
	553	m_r15_modified = 0;
652	554
653		cpustate->romcl = 0;
654		cpustate->romdr = 0;
	555	m_romcl = 0;
	556	m_romdr = 0;
655	557
656		cpustate->ramcl = 0;
657		cpustate->ramar = 0;
658		cpustate->ramdr = 0;
	558	m_ramcl = 0;
	559	m_ramar = 0;
	560	m_ramdr = 0;
659	561	}
660	562
661		void superfx_add_clocks(device_t *cpu, INT32 clocks)
	563	void superfx_device::add_clocks(INT32 clocks)
662	564	{
663		superfx_state *cpustate = get_safe_token(cpu);
664
665		superfx_add_clocks_internal(cpustate, clocks);
	565	superfx_add_clocks_internal(clocks);
666	566	}
667	567
668	568	/*****************************************************************************/
669	569
670		static void superfx_register_save( legacy_cpu_device *device )
	570	void superfx_device::device_start()
671	571	{
672		superfx_state *cpustate = get_safe_token(device);
673		int i;
	572	for(int i = 0; i < 16; i++)
	573	{
	574	m_r[i] = 0;
	575	}
674	576
675		device->save_item(NAME(cpustate->pipeline));
676		device->save_item(NAME(cpustate->ramaddr));
	577	m_sfr = 0;
	578	m_pbr = 0;
	579	m_rombr = 0;
	580	m_rambr = 0;
	581	m_cbr = 0;
	582	m_scbr = 0;
	583	m_scmr = 0;
	584	m_colr = 0;
	585	m_por = 0;
	586	m_bramr = 0;
	587	m_vcr = 0x04;
	588	m_cfgr = 0;
	589	m_clsr = 0;
	590	m_pipeline = 0x01; // nop
	591	m_ramaddr = 0;
	592	m_r15_modified = 0;
	593	m_irq = 0;
	594	m_cache_access_speed = 0;
	595	m_memory_access_speed = 0;
677	596
678		device->save_item(NAME(cpustate->r));
679		device->save_item(NAME(cpustate->sfr));
680		device->save_item(NAME(cpustate->pbr));
681		device->save_item(NAME(cpustate->rombr));
682		device->save_item(NAME(cpustate->rambr));
683		device->save_item(NAME(cpustate->cbr));
684		device->save_item(NAME(cpustate->scbr));
685		device->save_item(NAME(cpustate->scmr));
686		device->save_item(NAME(cpustate->colr));
687		device->save_item(NAME(cpustate->por));
688		device->save_item(NAME(cpustate->bramr));
689		device->save_item(NAME(cpustate->vcr));
690		device->save_item(NAME(cpustate->cfgr));
691		device->save_item(NAME(cpustate->clsr));
	597	superfx_regs_reset();
	598	superfx_memory_reset();
	599	superfx_update_speed();
692	600
693		device->save_item(NAME(cpustate->romcl));
694		device->save_item(NAME(cpustate->romdr));
	601	m_program = &space(AS_PROGRAM);
695	602
696		device->save_item(NAME(cpustate->ramcl));
697		device->save_item(NAME(cpustate->ramar));
698		device->save_item(NAME(cpustate->ramdr));
	603	m_out_irq_func.resolve();
699	604
700		device->save_item(NAME(cpustate->sreg_idx));
701		device->save_item(NAME(cpustate->dreg_idx));
702		device->save_item(NAME(cpustate->r15_modified));
	605	save_item(NAME(m_pipeline));
	606	save_item(NAME(m_ramaddr));
703	607
704		device->save_item(NAME(cpustate->irq));
	608	save_item(NAME(m_r));
	609	save_item(NAME(m_sfr));
	610	save_item(NAME(m_pbr));
	611	save_item(NAME(m_rombr));
	612	save_item(NAME(m_rambr));
	613	save_item(NAME(m_cbr));
	614	save_item(NAME(m_scbr));
	615	save_item(NAME(m_scmr));
	616	save_item(NAME(m_colr));
	617	save_item(NAME(m_por));
	618	save_item(NAME(m_bramr));
	619	save_item(NAME(m_vcr));
	620	save_item(NAME(m_cfgr));
	621	save_item(NAME(m_clsr));
705	622
706		device->save_item(NAME(cpustate->cache_access_speed));
707		device->save_item(NAME(cpustate->memory_access_speed));
	623	save_item(NAME(m_romcl));
	624	save_item(NAME(m_romdr));
708	625
709		device->save_item(NAME(cpustate->cache.buffer));
710		device->save_item(NAME(cpustate->cache.valid));
	626	save_item(NAME(m_ramcl));
	627	save_item(NAME(m_ramar));
	628	save_item(NAME(m_ramdr));
711	629
712		for (i = 0; i < 2; i++)
713		{
714		device->save_item(NAME(cpustate->pixelcache[i].offset), i);
715		device->save_item(NAME(cpustate->pixelcache[i].bitpend), i);
716		device->save_item(NAME(cpustate->pixelcache[i].data), i);
717		}
	630	save_item(NAME(m_sreg_idx));
	631	save_item(NAME(m_dreg_idx));
	632	save_item(NAME(m_r15_modified));
718	633
719		device->save_item(NAME(cpustate->icount));
720		}
	634	save_item(NAME(m_irq));
721	635
722		static CPU_INIT( superfx )
723		{
724		int i;
725		superfx_state *cpustate = get_safe_token(device);
	636	save_item(NAME(m_cache_access_speed));
	637	save_item(NAME(m_memory_access_speed));
726	638
727		for(i = 0; i < 16; i++)
	639	save_item(NAME(m_cache.buffer));
	640	save_item(NAME(m_cache.valid));
	641
	642	for (int i = 0; i < 2; i++)
728	643	{
729		cpustate->r[i] = 0;
	644	save_item(NAME(m_pixelcache[i].offset), i);
	645	save_item(NAME(m_pixelcache[i].bitpend), i);
	646	save_item(NAME(m_pixelcache[i].data), i);
730	647	}
731	648
732		cpustate->sfr = 0;
733		cpustate->pbr = 0;
734		cpustate->rombr = 0;
735		cpustate->rambr = 0;
736		cpustate->cbr = 0;
737		cpustate->scbr = 0;
738		cpustate->scmr = 0;
739		cpustate->colr = 0;
740		cpustate->por = 0;
741		cpustate->bramr = 0;
742		cpustate->vcr = 0x04;
743		cpustate->cfgr = 0;
744		cpustate->clsr = 0;
745		cpustate->pipeline = 0x01; // nop
746		cpustate->ramaddr = 0;
747		cpustate->r15_modified = 0;
	649	save_item(NAME(m_icount));
748	650
749		superfx_regs_reset(cpustate);
750		superfx_memory_reset(cpustate);
751		superfx_update_speed(cpustate);
	651	state_add( SUPERFX_PC,      "PC",      m_debugger_temp).callimport().callexport().formatstr("%06X");
	652	state_add( SUPERFX_DREG,    "DREG",    m_dreg_idx).mask(0xf).formatstr("%02u");
	653	state_add( SUPERFX_SREG,    "SREG",    m_sreg_idx).mask(0xf).formatstr("%02u");
	654	state_add( SUPERFX_R0,      "R0",      m_r[0]).formatstr("%04X");
	655	state_add( SUPERFX_R1,      "R1",      m_r[1]).formatstr("%04X");
	656	state_add( SUPERFX_R2,      "R2",      m_r[2]).formatstr("%04X");
	657	state_add( SUPERFX_R3,      "R3",      m_r[3]).formatstr("%04X");
	658	state_add( SUPERFX_R4,      "R4",      m_r[4]).formatstr("%04X");
	659	state_add( SUPERFX_R5,      "R5",      m_r[5]).formatstr("%04X");
	660	state_add( SUPERFX_R6,      "R6",      m_r[6]).formatstr("%04X");
	661	state_add( SUPERFX_R7,      "R7",      m_r[7]).formatstr("%04X");
	662	state_add( SUPERFX_R8,      "R8",      m_r[8]).formatstr("%04X");
	663	state_add( SUPERFX_R9,      "R9",      m_r[9]).formatstr("%04X");
	664	state_add( SUPERFX_R10,     "R10",     m_r[10]).formatstr("%04X");
	665	state_add( SUPERFX_R11,     "R11",     m_r[11]).formatstr("%04X");
	666	state_add( SUPERFX_R12,     "R12",     m_r[12]).formatstr("%04X");
	667	state_add( SUPERFX_R13,     "R13",     m_r[13]).formatstr("%04X");
	668	state_add( SUPERFX_R14,     "R14",     m_r[14]).formatstr("%04X");
	669	state_add( SUPERFX_R15,     "R15",     m_r[15]).formatstr("%04X");
	670	state_add( SUPERFX_SFR,     "SFR",     m_sfr).formatstr("%04X");
	671	state_add( SUPERFX_PBR,     "PBR",     m_pbr).formatstr("%02X");
	672	state_add( SUPERFX_ROMBR,   "ROMBR",   m_rombr).formatstr("%02X");
	673	state_add( SUPERFX_RAMBR,   "RAMBR",   m_rambr).formatstr("%02X");
	674	state_add( SUPERFX_CBR,     "CBR",     m_cbr).formatstr("%04X");
	675	state_add( SUPERFX_SCBR,    "SCBR",    m_scbr).formatstr("%02X");
	676	state_add( SUPERFX_SCMR,    "SCMR",    m_scmr).formatstr("%02X");
	677	state_add( SUPERFX_COLR,    "COLR",    m_colr).formatstr("%02X");
	678	state_add( SUPERFX_POR,     "POR",     m_por).formatstr("%02X");
	679	state_add( SUPERFX_BRAMR,   "BRAMR",   m_bramr).formatstr("%02X");
	680	state_add( SUPERFX_VCR,     "VCR",     m_vcr).formatstr("%02X");
	681	state_add( SUPERFX_CFGR,    "CFGR",    m_cfgr).formatstr("%02X");
	682	state_add( SUPERFX_CLSR,    "CLSR",    m_clsr).formatstr("%02X");
	683	state_add( SUPERFX_ROMCL,   "ROMCL",   m_romcl).formatstr("%08X");
	684	state_add( SUPERFX_ROMDR,   "ROMDR",   m_romdr).formatstr("%02X");
	685	state_add( SUPERFX_RAMCL,   "RAMCL",   m_ramcl).formatstr("%08X");
	686	state_add( SUPERFX_RAMAR,   "RAMAR",   m_ramar).formatstr("%04X");
	687	state_add( SUPERFX_RAMDR,   "RAMDR",   m_ramdr).formatstr("%02X");
	688	state_add( SUPERFX_RAMADDR, "RAMADDR", m_ramaddr).formatstr("%04X");
752	689
753		cpustate->device = device;
754		cpustate->program = &device->space(AS_PROGRAM);
	690	m_icountptr = &m_icount;
	691	}
755	692
756		if (device->static_config() != NULL)
	693
	694	void superfx_device::state_import(const device_state_entry &entry)
	695	{
	696	switch (entry.index())
757	697	{
758		cpustate->config = *(superfx_config *)device->static_config();
	698	case SUPERFX_PC:
	699	m_r[15] = m_debugger_temp;
	700	break;
759	701	}
760
761		cpustate->out_irq_func.resolve(cpustate->config.out_irq_func, *device);
762
763		superfx_register_save(device);
764	702	}
765	703
766		static CPU_EXIT( superfx )
	704
	705	void superfx_device::state_export(const device_state_entry &entry)
767	706	{
	707	switch (entry.index())
	708	{
	709	case STATE_GENPC:
	710	case SUPERFX_PC:
	711	m_debugger_temp = ( (m_pbr << 16) | m_r[15] ) - 1;
	712	break;
	713	}
768	714	}
769	715
770		static CPU_RESET( superfx )
	716
	717	void superfx_device::device_reset()
771	718	{
772	719	int i;
773	720
774		superfx_state *cpustate = get_safe_token(device);
775
776	721	for(i = 0; i < 16; i++)
777	722	{
778		cpustate->r[i] = 0;
	723	m_r[i] = 0;
779	724	}
780	725
781		cpustate->sfr = 0;
782		cpustate->pbr = 0;
783		cpustate->rombr = 0;
784		cpustate->rambr = 0;
785		cpustate->cbr = 0;
786		cpustate->scbr = 0;
787		cpustate->scmr = 0;
788		cpustate->colr = 0;
789		cpustate->por = 0;
790		cpustate->bramr = 0;
791		cpustate->vcr = 0x04;
792		cpustate->cfgr = 0;
793		cpustate->clsr = 0;
794		cpustate->pipeline = 0x01; // nop
795		cpustate->ramaddr = 0;
	726	m_sfr = 0;
	727	m_pbr = 0;
	728	m_rombr = 0;
	729	m_rambr = 0;
	730	m_cbr = 0;
	731	m_scbr = 0;
	732	m_scmr = 0;
	733	m_colr = 0;
	734	m_por = 0;
	735	m_bramr = 0;
	736	m_vcr = 0x04;
	737	m_cfgr = 0;
	738	m_clsr = 0;
	739	m_pipeline = 0x01; // nop
	740	m_ramaddr = 0;
796	741
797		superfx_regs_reset(cpustate);
798		superfx_timing_reset(cpustate);
	742	superfx_regs_reset();
	743	superfx_timing_reset();
799	744	}
800	745
801		INLINE void superfx_dreg_sfr_sz_update(superfx_state *cpustate)
	746	void superfx_device::superfx_dreg_sfr_sz_update()
802	747	{
803		cpustate->sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
804		cpustate->sfr |= (*(cpustate->dreg) & 0x8000) ? SUPERFX_SFR_S : 0;
805		cpustate->sfr |= (*(cpustate->dreg) == 0) ? SUPERFX_SFR_Z : 0;
	748	m_sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
	749	m_sfr |= (*(m_dreg) & 0x8000) ? SUPERFX_SFR_S : 0;
	750	m_sfr |= (*(m_dreg) == 0) ? SUPERFX_SFR_Z : 0;
806	751	}
807	752
808		static CPU_EXECUTE( superfx )
	753	void superfx_device::execute_run()
809	754	{
810		superfx_state *cpustate = get_safe_token(device);
811	755	UINT8 op;
812	756
813		if(!(cpustate->sfr & SUPERFX_SFR_G))
	757	if(!(m_sfr & SUPERFX_SFR_G))
814	758	{
815		superfx_add_clocks_internal(cpustate, 6);
816		cpustate->icount = MIN(cpustate->icount, 0);
	759	superfx_add_clocks_internal(6);
	760	m_icount = MIN(m_icount, 0);
817	761	}
818	762
819		while (cpustate->icount > 0 && (cpustate->sfr & SUPERFX_SFR_G))
	763	while (m_icount > 0 && (m_sfr & SUPERFX_SFR_G))
820	764	{
821		if(!(cpustate->sfr & SUPERFX_SFR_G))
	765	if(!(m_sfr & SUPERFX_SFR_G))
822	766	{
823		superfx_add_clocks_internal(cpustate, 6);
824		cpustate->icount = MIN(cpustate->icount, 0);
	767	superfx_add_clocks_internal(6);
	768	m_icount = MIN(m_icount, 0);
825	769	break;
826	770	}
827	771
828		debugger_instruction_hook(device, (cpustate->pbr << 16) | cpustate->r[15]);
	772	debugger_instruction_hook(this, (m_pbr << 16) | m_r[15]);
829	773
830		op = superfx_peekpipe(cpustate);
	774	op = superfx_peekpipe();
831	775
832	776	switch(op)
833	777	{
834	778	case 0x00: // STOP
835		if((cpustate->cfgr & SUPERFX_CFGR_IRQ) == 0)
	779	if((m_cfgr & SUPERFX_CFGR_IRQ) == 0)
836	780	{
837		cpustate->sfr |= SUPERFX_SFR_IRQ;
838		cpustate->irq = 1;
839		cpustate->out_irq_func(cpustate->irq ? ASSERT_LINE : CLEAR_LINE );
	781	m_sfr |= SUPERFX_SFR_IRQ;
	782	m_irq = 1;
	783	m_out_irq_func(m_irq ? ASSERT_LINE : CLEAR_LINE );
840	784	}
841		cpustate->sfr &= ~SUPERFX_SFR_G;
842		cpustate->pipeline = 0x01;
843		superfx_regs_reset(cpustate);
	785	m_sfr &= ~SUPERFX_SFR_G;
	786	m_pipeline = 0x01;
	787	superfx_regs_reset();
844	788	break;
845	789	case 0x01: // NOP
846		superfx_regs_reset(cpustate);
	790	superfx_regs_reset();
847	791	break;
848	792	case 0x02: // CACHE
849		if(cpustate->cbr != (cpustate->r[15] & 0xfff0))
	793	if(m_cbr != (m_r[15] & 0xfff0))
850	794	{
851		cpustate->cbr = cpustate->r[15] & 0xfff0;
852		superfx_cache_flush(cpustate);
	795	m_cbr = m_r[15] & 0xfff0;
	796	superfx_cache_flush();
853	797	}
854		superfx_regs_reset(cpustate);
	798	superfx_regs_reset();
855	799	break;
856	800	case 0x03: // LSR
857		cpustate->sfr &= ~SUPERFX_SFR_CY;
858		cpustate->sfr |= (*(cpustate->sreg) & 1) ? SUPERFX_SFR_CY : 0;
859		superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) >> 1);
860		superfx_dreg_sfr_sz_update(cpustate);
861		superfx_regs_reset(cpustate);
	801	m_sfr &= ~SUPERFX_SFR_CY;
	802	m_sfr |= (*(m_sreg) & 1) ? SUPERFX_SFR_CY : 0;
	803	superfx_gpr_write(m_dreg_idx, *(m_sreg) >> 1);
	804	superfx_dreg_sfr_sz_update();
	805	superfx_regs_reset();
862	806	break;
863	807	case 0x04: // ROL
864	808	{
865		UINT16 carry = *(cpustate->sreg) & 0x8000;
866		superfx_gpr_write(cpustate, cpustate->dreg_idx, (*(cpustate->sreg) << 1) | SUPERFX_SFR_CY_SET);
867		cpustate->sfr &= ~SUPERFX_SFR_CY;
868		cpustate->sfr |= carry ? SUPERFX_SFR_CY : 0;
869		superfx_dreg_sfr_sz_update(cpustate);
870		superfx_regs_reset(cpustate);
	809	UINT16 carry = *(m_sreg) & 0x8000;
	810	superfx_gpr_write(m_dreg_idx, (*(m_sreg) << 1) | SUPERFX_SFR_CY_SET);
	811	m_sfr &= ~SUPERFX_SFR_CY;
	812	m_sfr |= carry ? SUPERFX_SFR_CY : 0;
	813	superfx_dreg_sfr_sz_update();
	814	superfx_regs_reset();
871	815	break;
872	816	}
873	817	case 0x05: // BRA
874	818	{
875		INT32 e = (INT8)superfx_pipe(cpustate);
876		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	819	INT32 e = (INT8)superfx_pipe();
	820	superfx_gpr_write(15, m_r[15] + e);
877	821	break;
878	822	}
879	823	case 0x06: // BLT
880	824	{
881		INT32 e = (INT8)superfx_pipe(cpustate);
	825	INT32 e = (INT8)superfx_pipe();
882	826	if((SUPERFX_SFR_S_SET ^ SUPERFX_SFR_OV_SET) == 0)
883	827	{
884		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	828	superfx_gpr_write(15, m_r[15] + e);
885	829	}
886	830	break;
887	831	}
888	832	case 0x07: // BGE
889	833	{
890		INT32 e = (INT8)superfx_pipe(cpustate);
	834	INT32 e = (INT8)superfx_pipe();
891	835	if((SUPERFX_SFR_S_SET ^ SUPERFX_SFR_OV_SET) == 1)
892	836	{
893		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	837	superfx_gpr_write(15, m_r[15] + e);
894	838	}
895	839	break;
896	840	}
897	841	case 0x08: // BNE
898	842	{
899		INT32 e = (INT8)superfx_pipe(cpustate);
	843	INT32 e = (INT8)superfx_pipe();
900	844	if(SUPERFX_SFR_Z_SET == 0)
901	845	{
902		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	846	superfx_gpr_write(15, m_r[15] + e);
903	847	}
904	848	break;
905	849	}
906	850	case 0x09: // BEQ
907	851	{
908		INT32 e = (INT8)superfx_pipe(cpustate);
	852	INT32 e = (INT8)superfx_pipe();
909	853	if(SUPERFX_SFR_Z_SET == 1)
910	854	{
911		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	855	superfx_gpr_write(15, m_r[15] + e);
912	856	}
913	857	break;
914	858	}
915	859	case 0x0a: // BPL
916	860	{
917		INT32 e = (INT8)superfx_pipe(cpustate);
	861	INT32 e = (INT8)superfx_pipe();
918	862	if(SUPERFX_SFR_S_SET == 0)
919	863	{
920		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	864	superfx_gpr_write(15, m_r[15] + e);
921	865	}
922	866	break;
923	867	}
924	868	case 0x0b: // BMI
925	869	{
926		INT32 e = (INT8)superfx_pipe(cpustate);
	870	INT32 e = (INT8)superfx_pipe();
927	871	if(SUPERFX_SFR_S_SET == 1)
928	872	{
929		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	873	superfx_gpr_write(15, m_r[15] + e);
930	874	}
931	875	break;
932	876	}
933	877	case 0x0c: // BCC
934	878	{
935		INT32 e = (INT8)superfx_pipe(cpustate);
	879	INT32 e = (INT8)superfx_pipe();
936	880	if(SUPERFX_SFR_CY_SET == 0)
937	881	{
938		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	882	superfx_gpr_write(15, m_r[15] + e);
939	883	}
940	884	break;
941	885	}
942	886	case 0x0d: // BCS
943	887	{
944		INT32 e = (INT8)superfx_pipe(cpustate);
	888	INT32 e = (INT8)superfx_pipe();
945	889	if(SUPERFX_SFR_CY_SET == 1)
946	890	{
947		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	891	superfx_gpr_write(15, m_r[15] + e);
948	892	}
949	893	break;
950	894	}
951	895	case 0x0e: // BVC
952	896	{
953		INT32 e = (INT8)superfx_pipe(cpustate);
	897	INT32 e = (INT8)superfx_pipe();
954	898	if(SUPERFX_SFR_OV_SET == 0)
955	899	{
956		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	900	superfx_gpr_write(15, m_r[15] + e);
957	901	}
958	902	break;
959	903	}
960	904	case 0x0f: // BVS
961	905	{
962		INT32 e = (INT8)superfx_pipe(cpustate);
	906	INT32 e = (INT8)superfx_pipe();
963	907	if(SUPERFX_SFR_OV_SET == 1)
964	908	{
965		superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	909	superfx_gpr_write(15, m_r[15] + e);
966	910	}
967	911	break;
968	912	}
969	913
970	914	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
971	915	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: // TO
972		if((cpustate->sfr & SUPERFX_SFR_B) == 0)
	916	if((m_sfr & SUPERFX_SFR_B) == 0)
973	917	{
974		cpustate->dreg = &cpustate->r[op & 0xf];
975		cpustate->dreg_idx = op & 0xf;
	918	m_dreg = &m_r[op & 0xf];
	919	m_dreg_idx = op & 0xf;
976	920	}
977	921	else
978	922	{
979		superfx_gpr_write(cpustate, op & 0xf, *(cpustate->sreg));
980		superfx_regs_reset(cpustate);
	923	superfx_gpr_write(op & 0xf, *(m_sreg));
	924	superfx_regs_reset();
981	925	}
982	926	break;
983	927
984	928	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
985	929	case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: // WITH
986		cpustate->sreg = &cpustate->r[op & 0xf];
987		cpustate->sreg_idx = op & 0xf;
988		cpustate->dreg = &cpustate->r[op & 0xf];
989		cpustate->dreg_idx = op & 0xf;
990		cpustate->sfr |= SUPERFX_SFR_B;
	930	m_sreg = &m_r[op & 0xf];
	931	m_sreg_idx = op & 0xf;
	932	m_dreg = &m_r[op & 0xf];
	933	m_dreg_idx = op & 0xf;
	934	m_sfr |= SUPERFX_SFR_B;
991	935	break;
992	936
993	937	case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35:
994	938	case 0x36: case 0x37: case 0x38: case 0x39: case 0x3a: case 0x3b:   // STW_IR / STB_IR
995		if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	939	if((m_sfr & SUPERFX_SFR_ALT1) == 0)
996	940	{ // STW_IR
997		cpustate->ramaddr = cpustate->r[op & 0xf];
998		superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 0, (*(cpustate->sreg)) >> 0);
999		superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 1, (*(cpustate->sreg)) >> 8);
1000		superfx_regs_reset(cpustate);
	941	m_ramaddr = m_r[op & 0xf];
	942	superfx_rambuffer_write(m_ramaddr ^ 0, (*(m_sreg)) >> 0);
	943	superfx_rambuffer_write(m_ramaddr ^ 1, (*(m_sreg)) >> 8);
	944	superfx_regs_reset();
1001	945	}
1002	946	else
1003	947	{ // STB_IR
1004		cpustate->ramaddr = cpustate->r[op & 0xf];
1005		superfx_rambuffer_write(cpustate, cpustate->ramaddr, *(cpustate->sreg));
1006		superfx_regs_reset(cpustate);
	948	m_ramaddr = m_r[op & 0xf];
	949	superfx_rambuffer_write(m_ramaddr, *(m_sreg));
	950	superfx_regs_reset();
1007	951	}
1008	952	break;
1009	953
1010	954	case 0x3c: // LOOP
1011		superfx_gpr_write(cpustate, 12, cpustate->r[12] - 1);
1012		cpustate->sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
1013		cpustate->sfr |= (cpustate->r[12] & 0x8000) ? SUPERFX_SFR_S : 0;
1014		cpustate->sfr |= (cpustate->r[12] == 0) ? SUPERFX_SFR_Z : 0;
1015		if(!(cpustate->sfr & SUPERFX_SFR_Z))
	955	superfx_gpr_write(12, m_r[12] - 1);
	956	m_sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
	957	m_sfr |= (m_r[12] & 0x8000) ? SUPERFX_SFR_S : 0;
	958	m_sfr |= (m_r[12] == 0) ? SUPERFX_SFR_Z : 0;
	959	if(!(m_sfr & SUPERFX_SFR_Z))
1016	960	{
1017		superfx_gpr_write(cpustate, 15, cpustate->r[13]);
	961	superfx_gpr_write(15, m_r[13]);
1018	962	}
1019		superfx_regs_reset(cpustate);
	963	superfx_regs_reset();
1020	964	break;
1021	965	case 0x3d: // ALT1
1022		cpustate->sfr &= ~SUPERFX_SFR_B;
1023		cpustate->sfr |= SUPERFX_SFR_ALT1;
	966	m_sfr &= ~SUPERFX_SFR_B;
	967	m_sfr |= SUPERFX_SFR_ALT1;
1024	968	break;
1025	969	case 0x3e: // ALT2
1026		cpustate->sfr &= ~SUPERFX_SFR_B;
1027		cpustate->sfr |= SUPERFX_SFR_ALT2;
	970	m_sfr &= ~SUPERFX_SFR_B;
	971	m_sfr |= SUPERFX_SFR_ALT2;
1028	972	break;
1029	973	case 0x3f: // ALT3
1030		cpustate->sfr &= ~SUPERFX_SFR_B;
1031		cpustate->sfr |= SUPERFX_SFR_ALT1;
1032		cpustate->sfr |= SUPERFX_SFR_ALT2;
	974	m_sfr &= ~SUPERFX_SFR_B;
	975	m_sfr |= SUPERFX_SFR_ALT1;
	976	m_sfr |= SUPERFX_SFR_ALT2;
1033	977	break;
1034	978
1035	979	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45:
1036	980	case 0x46: case 0x47: case 0x48: case 0x49: case 0x4a: case 0x4b:   // LDW_IR / LDB_IR
1037		if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	981	if((m_sfr & SUPERFX_SFR_ALT1) == 0)
1038	982	{ // LDW_IR
1039	983	UINT16 data = 0;
1040		cpustate->ramaddr = cpustate->r[op & 0xf];
1041		data  = superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 0) << 0;
1042		data |= superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 1) << 8;
1043		superfx_gpr_write(cpustate, cpustate->dreg_idx, data);
1044		superfx_regs_reset(cpustate);
	984	m_ramaddr = m_r[op & 0xf];
	985	data  = superfx_rambuffer_read(m_ramaddr ^ 0) << 0;
	986	data |= superfx_rambuffer_read(m_ramaddr ^ 1) << 8;
	987	superfx_gpr_write(m_dreg_idx, data);
	988	superfx_regs_reset();
1045	989	}
1046	990	else
1047	991	{ // LDB_IR
1048		cpustate->ramaddr = cpustate->r[op & 0xf];
1049		superfx_gpr_write(cpustate, cpustate->dreg_idx, superfx_rambuffer_read(cpustate, cpustate->ramaddr));
1050		superfx_regs_reset(cpustate);
	992	m_ramaddr = m_r[op & 0xf];
	993	superfx_gpr_write(m_dreg_idx, superfx_rambuffer_read(m_ramaddr));
	994	superfx_regs_reset();
1051	995	}
1052	996	break;
1053	997
1054	998	case 0x4c: // PLOT / RPIX
1055		if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	999	if((m_sfr & SUPERFX_SFR_ALT1) == 0)
1056	1000	{ // PLOT
1057		superfx_plot(cpustate, cpustate->r[1], cpustate->r[2]);
1058		superfx_gpr_write(cpustate, 1, cpustate->r[1] + 1);
1059		superfx_regs_reset(cpustate);
	1001	superfx_plot(m_r[1], m_r[2]);
	1002	superfx_gpr_write(1, m_r[1] + 1);
	1003	superfx_regs_reset();
1060	1004	}
1061	1005	else
1062	1006	{ // RPIX
1063		superfx_gpr_write(cpustate, cpustate->dreg_idx, superfx_rpix(cpustate, cpustate->r[1], cpustate->r[2]));
1064		superfx_dreg_sfr_sz_update(cpustate);
1065		superfx_regs_reset(cpustate);
	1007	superfx_gpr_write(m_dreg_idx, superfx_rpix(m_r[1], m_r[2]));
	1008	superfx_dreg_sfr_sz_update();
	1009	superfx_regs_reset();
1066	1010	}
1067	1011	break;
1068	1012
1069	1013	case 0x4d: // SWAP
1070		superfx_gpr_write(cpustate, cpustate->dreg_idx, (*(cpustate->sreg) >> 8) | (*(cpustate->sreg) << 8));
1071		superfx_dreg_sfr_sz_update(cpustate);
1072		superfx_regs_reset(cpustate);
	1014	superfx_gpr_write(m_dreg_idx, (*(m_sreg) >> 8) | (*(m_sreg) << 8));
	1015	superfx_dreg_sfr_sz_update();
	1016	superfx_regs_reset();
1073	1017	break;
1074	1018
1075	1019	case 0x4e: // COLOR / CMODE
1076		if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	1020	if((m_sfr & SUPERFX_SFR_ALT1) == 0)
1077	1021	{ // COLOR
1078		cpustate->colr = superfx_color(cpustate, *(cpustate->sreg));
1079		superfx_regs_reset(cpustate);
	1022	m_colr = superfx_color(*(m_sreg));
	1023	superfx_regs_reset();
1080	1024	}
1081	1025	else
1082	1026	{ // CMODE
1083		cpustate->por = *(cpustate->sreg);
1084		superfx_regs_reset(cpustate);
	1027	m_por = *(m_sreg);
	1028	superfx_regs_reset();
1085	1029	}
1086	1030	break;
1087	1031
1088	1032	case 0x4f: // NOT
1089		superfx_gpr_write(cpustate, cpustate->dreg_idx, ~(*(cpustate->sreg)));
1090		superfx_dreg_sfr_sz_update(cpustate);
1091		superfx_regs_reset(cpustate);
	1033	superfx_gpr_write(m_dreg_idx, ~(*(m_sreg)));
	1034	superfx_dreg_sfr_sz_update();
	1035	superfx_regs_reset();
1092	1036	break;
1093	1037
1094	1038	case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
1095	1039	case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: // ADD / ADC / ADDI / ADCI
1096	1040	{
1097		INT32 r = *(cpustate->sreg);
1098		cpustate->sfr &= ~(SUPERFX_SFR_OV | SUPERFX_SFR_S | SUPERFX_SFR_Z);
1099		switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1041	INT32 r = *(m_sreg);
	1042	m_sfr &= ~(SUPERFX_SFR_OV | SUPERFX_SFR_S | SUPERFX_SFR_Z);
	1043	switch(m_sfr & SUPERFX_SFR_ALT)
1100	1044	{
1101	1045	case SUPERFX_SFR_ALT0: // ADD
1102		r += cpustate->r[op & 0xf];
1103		cpustate->sfr |= (~(*(cpustate->sreg) ^ cpustate->r[op & 0xf]) & (cpustate->r[op & 0xf] ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1046	r += m_r[op & 0xf];
	1047	m_sfr |= (~(*(m_sreg) ^ m_r[op & 0xf]) & (m_r[op & 0xf] ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
1104	1048	break;
1105	1049	case SUPERFX_SFR_ALT1: // ADC
1106		r += cpustate->r[op & 0xf] + SUPERFX_SFR_CY_SET;
1107		cpustate->sfr |= (~(*(cpustate->sreg) ^ cpustate->r[op & 0xf]) & (cpustate->r[op & 0xf] ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1050	r += m_r[op & 0xf] + SUPERFX_SFR_CY_SET;
	1051	m_sfr |= (~(*(m_sreg) ^ m_r[op & 0xf]) & (m_r[op & 0xf] ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
1108	1052	break;
1109	1053	case SUPERFX_SFR_ALT2: // ADDI
1110	1054	r += op & 0xf;
1111		cpustate->sfr |= (~(*(cpustate->sreg) ^ (op & 0xf)) & ((op & 0xf) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1055	m_sfr |= (~(*(m_sreg) ^ (op & 0xf)) & ((op & 0xf) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
1112	1056	break;
1113	1057	case SUPERFX_SFR_ALT3: // ADCI
1114	1058	r += (op & 0xf) + SUPERFX_SFR_CY_SET;
1115		cpustate->sfr |= (~(*(cpustate->sreg) ^ (op & 0xf)) & ((op & 0xf) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1059	m_sfr |= (~(*(m_sreg) ^ (op & 0xf)) & ((op & 0xf) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
1116	1060	break;
1117	1061	}
1118		cpustate->sfr &= ~SUPERFX_SFR_CY;
1119		cpustate->sfr |= (r & 0x8000) ? SUPERFX_SFR_S : 0;
1120		cpustate->sfr |= (r >= 0x10000) ? SUPERFX_SFR_CY : 0;
1121		cpustate->sfr |= ((UINT16)r == 0) ? SUPERFX_SFR_Z : 0;
1122		superfx_gpr_write(cpustate, cpustate->dreg_idx, r);
1123		superfx_regs_reset(cpustate);
	1062	m_sfr &= ~SUPERFX_SFR_CY;
	1063	m_sfr |= (r & 0x8000) ? SUPERFX_SFR_S : 0;
	1064	m_sfr |= (r >= 0x10000) ? SUPERFX_SFR_CY : 0;
	1065	m_sfr |= ((UINT16)r == 0) ? SUPERFX_SFR_Z : 0;
	1066	superfx_gpr_write(m_dreg_idx, r);
	1067	superfx_regs_reset();
1124	1068	break;
1125	1069	}
1126	1070
r26752	r26753
1128	1072	case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f: // SUB / SBC / SUBI / CMP
1129	1073	{
1130	1074	INT32 r = 0;
1131		cpustate->sfr &= ~(SUPERFX_SFR_OV | SUPERFX_SFR_S | SUPERFX_SFR_Z);
1132		switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1075	m_sfr &= ~(SUPERFX_SFR_OV | SUPERFX_SFR_S | SUPERFX_SFR_Z);
	1076	switch(m_sfr & SUPERFX_SFR_ALT)
1133	1077	{
1134	1078	case SUPERFX_SFR_ALT0: // SUB
1135		r = *(cpustate->sreg) - cpustate->r[op & 0xf];
1136		cpustate->sfr |= ((*(cpustate->sreg) ^ cpustate->r[op & 0xf]) & (*(cpustate->sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
1137		superfx_gpr_write(cpustate, cpustate->dreg_idx, r);
	1079	r = *(m_sreg) - m_r[op & 0xf];
	1080	m_sfr |= ((*(m_sreg) ^ m_r[op & 0xf]) & (*(m_sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1081	superfx_gpr_write(m_dreg_idx, r);
1138	1082	break;
1139	1083	case SUPERFX_SFR_ALT1: // SBC
1140		r = *(cpustate->sreg) - cpustate->r[op & 0xf] - SUPERFX_SFR_CY_CLEAR;
1141		cpustate->sfr |= ((*(cpustate->sreg) ^ cpustate->r[op & 0xf]) & (*(cpustate->sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
1142		superfx_gpr_write(cpustate, cpustate->dreg_idx, r);
	1084	r = *(m_sreg) - m_r[op & 0xf] - SUPERFX_SFR_CY_CLEAR;
	1085	m_sfr |= ((*(m_sreg) ^ m_r[op & 0xf]) & (*(m_sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1086	superfx_gpr_write(m_dreg_idx, r);
1143	1087	break;
1144	1088	case SUPERFX_SFR_ALT2: // SUBI
1145		r = *(cpustate->sreg) - (op & 0xf);
1146		cpustate->sfr |= ((*(cpustate->sreg) ^ (op & 0xf)) & (*(cpustate->sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
1147		superfx_gpr_write(cpustate, cpustate->dreg_idx, r);
	1089	r = *(m_sreg) - (op & 0xf);
	1090	m_sfr |= ((*(m_sreg) ^ (op & 0xf)) & (*(m_sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1091	superfx_gpr_write(m_dreg_idx, r);
1148	1092	break;
1149	1093	case SUPERFX_SFR_ALT3: // CMP
1150		r = *(cpustate->sreg) - cpustate->r[op & 0xf];
1151		cpustate->sfr |= ((*(cpustate->sreg) ^ cpustate->r[op & 0xf]) & (*(cpustate->sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1094	r = *(m_sreg) - m_r[op & 0xf];
	1095	m_sfr |= ((*(m_sreg) ^ m_r[op & 0xf]) & (*(m_sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
1152	1096	break;
1153	1097	}
1154		cpustate->sfr &= ~SUPERFX_SFR_CY;
1155		cpustate->sfr |= (r & 0x8000) ? SUPERFX_SFR_S : 0;
1156		cpustate->sfr |= (r >= 0x0) ? SUPERFX_SFR_CY : 0;
1157		cpustate->sfr |= ((UINT16)r == 0) ? SUPERFX_SFR_Z : 0;
1158		superfx_regs_reset(cpustate);
	1098	m_sfr &= ~SUPERFX_SFR_CY;
	1099	m_sfr |= (r & 0x8000) ? SUPERFX_SFR_S : 0;
	1100	m_sfr |= (r >= 0x0) ? SUPERFX_SFR_CY : 0;
	1101	m_sfr |= ((UINT16)r == 0) ? SUPERFX_SFR_Z : 0;
	1102	superfx_regs_reset();
1159	1103	break;
1160	1104	}
1161	1105
1162	1106	case 0x70: // MERGE
1163		superfx_gpr_write(cpustate, cpustate->dreg_idx, (cpustate->r[7] & 0xff00) | (cpustate->r[8] >> 8));
1164		cpustate->sfr &= ~(SUPERFX_SFR_OV | SUPERFX_SFR_S | SUPERFX_SFR_CY | SUPERFX_SFR_Z);
1165		cpustate->sfr |= (*(cpustate->dreg) & 0xc0c0) ? SUPERFX_SFR_OV : 0;
1166		cpustate->sfr |= (*(cpustate->dreg) & 0x8080) ? SUPERFX_SFR_S : 0;
1167		cpustate->sfr |= (*(cpustate->dreg) & 0xe0e0) ? SUPERFX_SFR_CY : 0;
1168		cpustate->sfr |= (*(cpustate->dreg) & 0xf0f0) ? SUPERFX_SFR_Z : 0;
1169		superfx_regs_reset(cpustate);
	1107	superfx_gpr_write(m_dreg_idx, (m_r[7] & 0xff00) | (m_r[8] >> 8));
	1108	m_sfr &= ~(SUPERFX_SFR_OV | SUPERFX_SFR_S | SUPERFX_SFR_CY | SUPERFX_SFR_Z);
	1109	m_sfr |= (*(m_dreg) & 0xc0c0) ? SUPERFX_SFR_OV : 0;
	1110	m_sfr |= (*(m_dreg) & 0x8080) ? SUPERFX_SFR_S : 0;
	1111	m_sfr |= (*(m_dreg) & 0xe0e0) ? SUPERFX_SFR_CY : 0;
	1112	m_sfr |= (*(m_dreg) & 0xf0f0) ? SUPERFX_SFR_Z : 0;
	1113	superfx_regs_reset();
1170	1114	break;
1171	1115
1172	1116	case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
1173	1117	case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: // AND / BIC / ANDI / BICI
1174		switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1118	switch(m_sfr & SUPERFX_SFR_ALT)
1175	1119	{
1176	1120	case SUPERFX_SFR_ALT0: // AND
1177		superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) & cpustate->r[op & 0xf]);
	1121	superfx_gpr_write(m_dreg_idx, *(m_sreg) & m_r[op & 0xf]);
1178	1122	break;
1179	1123	case SUPERFX_SFR_ALT1: // BIC
1180		superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) & ~cpustate->r[op & 0xf]);
	1124	superfx_gpr_write(m_dreg_idx, *(m_sreg) & ~m_r[op & 0xf]);
1181	1125	break;
1182	1126	case SUPERFX_SFR_ALT2: // ANDI
1183		superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) & (op & 0xf));
	1127	superfx_gpr_write(m_dreg_idx, *(m_sreg) & (op & 0xf));
1184	1128	break;
1185	1129	case SUPERFX_SFR_ALT3: // BICI
1186		superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) & ~(op & 0xf));
	1130	superfx_gpr_write(m_dreg_idx, *(m_sreg) & ~(op & 0xf));
1187	1131	break;
1188	1132	}
1189		superfx_dreg_sfr_sz_update(cpustate);
1190		superfx_regs_reset(cpustate);
	1133	superfx_dreg_sfr_sz_update();
	1134	superfx_regs_reset();
1191	1135	break;
1192	1136
1193	1137	case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
1194	1138	case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f: // MULT / UMULT / MULTI / UMULTI
1195		switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1139	switch(m_sfr & SUPERFX_SFR_ALT)
1196	1140	{
1197	1141	case SUPERFX_SFR_ALT0: // MULT
1198		superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT8)(*(cpustate->sreg)) * (INT8)(cpustate->r[op & 0xf]));
	1142	superfx_gpr_write(m_dreg_idx, (INT8)(*(m_sreg)) * (INT8)(m_r[op & 0xf]));
1199	1143	break;
1200	1144	case SUPERFX_SFR_ALT1: // UMULT
1201		superfx_gpr_write(cpustate, cpustate->dreg_idx, (UINT8)(*(cpustate->sreg)) * (UINT8)(cpustate->r[op & 0xf]));
	1145	superfx_gpr_write(m_dreg_idx, (UINT8)(*(m_sreg)) * (UINT8)(m_r[op & 0xf]));
1202	1146	break;
1203	1147	case SUPERFX_SFR_ALT2: // MULTI
1204		superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT8)(*(cpustate->sreg)) * (INT8)(op & 0xf));
	1148	superfx_gpr_write(m_dreg_idx, (INT8)(*(m_sreg)) * (INT8)(op & 0xf));
1205	1149	break;
1206	1150	case SUPERFX_SFR_ALT3: // UMULTI
1207		superfx_gpr_write(cpustate, cpustate->dreg_idx, (UINT8)(*(cpustate->sreg)) * (UINT8)(op & 0xf));
	1151	superfx_gpr_write(m_dreg_idx, (UINT8)(*(m_sreg)) * (UINT8)(op & 0xf));
1208	1152	break;
1209	1153	}
1210		superfx_dreg_sfr_sz_update(cpustate);
1211		superfx_regs_reset(cpustate);
1212		if(!(cpustate->cfgr & SUPERFX_CFGR_MS0))
	1154	superfx_dreg_sfr_sz_update();
	1155	superfx_regs_reset();
	1156	if(!(m_cfgr & SUPERFX_CFGR_MS0))
1213	1157	{
1214		superfx_add_clocks_internal(cpustate, 2);
	1158	superfx_add_clocks_internal(2);
1215	1159	}
1216	1160	break;
1217	1161
1218	1162	case 0x90: // SBK
1219		superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 0, *(cpustate->sreg) >> 0);
1220		superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 1, *(cpustate->sreg) >> 8);
1221		superfx_regs_reset(cpustate);
	1163	superfx_rambuffer_write(m_ramaddr ^ 0, *(m_sreg) >> 0);
	1164	superfx_rambuffer_write(m_ramaddr ^ 1, *(m_sreg) >> 8);
	1165	superfx_regs_reset();
1222	1166	break;
1223	1167
1224	1168	case 0x91: case 0x92: case 0x93: case 0x94: // LINK
1225		superfx_gpr_write(cpustate, 11, cpustate->r[15] + (op & 0xf));
1226		superfx_regs_reset(cpustate);
	1169	superfx_gpr_write(11, m_r[15] + (op & 0xf));
	1170	superfx_regs_reset();
1227	1171	break;
1228	1172
1229	1173	case 0x95: // SEX
1230		superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT8)(*(cpustate->sreg)));
1231		superfx_dreg_sfr_sz_update(cpustate);
1232		superfx_regs_reset(cpustate);
	1174	superfx_gpr_write(m_dreg_idx, (INT8)(*(m_sreg)));
	1175	superfx_dreg_sfr_sz_update();
	1176	superfx_regs_reset();
1233	1177	break;
1234	1178
1235	1179	case 0x96: // ASR / DIV2
1236		if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	1180	if((m_sfr & SUPERFX_SFR_ALT1) == 0)
1237	1181	{ // ASR
1238		cpustate->sfr &= ~SUPERFX_SFR_CY;
1239		cpustate->sfr |= (*(cpustate->sreg) & 1) ? SUPERFX_SFR_CY : 0;
1240		superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT16)(*(cpustate->sreg)) >> 1);
1241		superfx_dreg_sfr_sz_update(cpustate);
1242		superfx_regs_reset(cpustate);
	1182	m_sfr &= ~SUPERFX_SFR_CY;
	1183	m_sfr |= (*(m_sreg) & 1) ? SUPERFX_SFR_CY : 0;
	1184	superfx_gpr_write(m_dreg_idx, (INT16)(*(m_sreg)) >> 1);
	1185	superfx_dreg_sfr_sz_update();
	1186	superfx_regs_reset();
1243	1187	}
1244	1188	else
1245	1189	{ // DIV2
1246		cpustate->sfr &= ~SUPERFX_SFR_CY;
1247		cpustate->sfr |= (*(cpustate->sreg) & 1) ? SUPERFX_SFR_CY : 0;
1248		superfx_gpr_write(cpustate, cpustate->dreg_idx, ((INT16)(*(cpustate->sreg)) >> 1) + ((UINT32)(*(cpustate->sreg) + 1) >> 16));
1249		superfx_dreg_sfr_sz_update(cpustate);
1250		superfx_regs_reset(cpustate);
	1190	m_sfr &= ~SUPERFX_SFR_CY;
	1191	m_sfr |= (*(m_sreg) & 1) ? SUPERFX_SFR_CY : 0;
	1192	superfx_gpr_write(m_dreg_idx, ((INT16)(*(m_sreg)) >> 1) + ((UINT32)(*(m_sreg) + 1) >> 16));
	1193	superfx_dreg_sfr_sz_update();
	1194	superfx_regs_reset();
1251	1195	}
1252	1196	break;
1253	1197
1254	1198	case 0x97: // ROR
1255	1199	{
1256		UINT16 carry = *(cpustate->sreg) & 1;
1257		superfx_gpr_write(cpustate, cpustate->dreg_idx, (SUPERFX_SFR_CY_SET << 15) | ((UINT16)(*(cpustate->sreg)) >> 1));
1258		cpustate->sfr &= ~SUPERFX_SFR_CY;
1259		cpustate->sfr |= carry ? SUPERFX_SFR_CY : 0;
1260		superfx_dreg_sfr_sz_update(cpustate);
1261		superfx_regs_reset(cpustate);
	1200	UINT16 carry = *(m_sreg) & 1;
	1201	superfx_gpr_write(m_dreg_idx, (SUPERFX_SFR_CY_SET << 15) | ((UINT16)(*(m_sreg)) >> 1));
	1202	m_sfr &= ~SUPERFX_SFR_CY;
	1203	m_sfr |= carry ? SUPERFX_SFR_CY : 0;
	1204	superfx_dreg_sfr_sz_update();
	1205	superfx_regs_reset();
1262	1206	break;
1263	1207	}
1264	1208
1265	1209	case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: // JMP / LJMP
1266		if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	1210	if((m_sfr & SUPERFX_SFR_ALT1) == 0)
1267	1211	{ // JMP
1268		superfx_gpr_write(cpustate, 15, cpustate->r[op & 0xf]);
1269		superfx_regs_reset(cpustate);
	1212	superfx_gpr_write(15, m_r[op & 0xf]);
	1213	superfx_regs_reset();
1270	1214	}
1271	1215	else
1272	1216	{ // LJMP
1273		cpustate->pbr = cpustate->r[op & 0xf] & 0x7f;
1274		superfx_gpr_write(cpustate, 15, *(cpustate->sreg));
1275		cpustate->cbr = cpustate->r[15] & 0xfff0;
1276		superfx_cache_flush(cpustate);
1277		superfx_regs_reset(cpustate);
	1217	m_pbr = m_r[op & 0xf] & 0x7f;
	1218	superfx_gpr_write(15, *(m_sreg));
	1219	m_cbr = m_r[15] & 0xfff0;
	1220	superfx_cache_flush();
	1221	superfx_regs_reset();
1278	1222	}
1279	1223	break;
1280	1224
1281	1225	case 0x9e: // LOB
1282		superfx_gpr_write(cpustate, cpustate->dreg_idx, (UINT16)(*(cpustate->sreg)) & 0x00ff);
1283		cpustate->sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
1284		cpustate->sfr |= (*(cpustate->dreg) & 0x80) ? SUPERFX_SFR_S : 0;
1285		cpustate->sfr |= (*(cpustate->dreg) == 0) ? SUPERFX_SFR_Z : 0;
1286		superfx_regs_reset(cpustate);
	1226	superfx_gpr_write(m_dreg_idx, (UINT16)(*(m_sreg)) & 0x00ff);
	1227	m_sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
	1228	m_sfr |= (*(m_dreg) & 0x80) ? SUPERFX_SFR_S : 0;
	1229	m_sfr |= (*(m_dreg) == 0) ? SUPERFX_SFR_Z : 0;
	1230	superfx_regs_reset();
1287	1231	break;
1288	1232
1289	1233	case 0x9f: // FMULT / LMULT
1290	1234	{
1291		UINT32 result = (INT16)(*(cpustate->sreg)) * (INT16)(cpustate->r[6]);
1292		if(cpustate->sfr & SUPERFX_SFR_ALT1)
	1235	UINT32 result = (INT16)(*(m_sreg)) * (INT16)(m_r[6]);
	1236	if(m_sfr & SUPERFX_SFR_ALT1)
1293	1237	{ // LMULT
1294		superfx_gpr_write(cpustate, 4, result);
	1238	superfx_gpr_write(4, result);
1295	1239	}
1296		superfx_gpr_write(cpustate, cpustate->dreg_idx, result >> 16);
1297		cpustate->sfr &= ~SUPERFX_SFR_CY;
1298		cpustate->sfr |= (result & 0x8000) ? SUPERFX_SFR_CY : 0;
1299		superfx_dreg_sfr_sz_update(cpustate);
1300		superfx_regs_reset(cpustate);
1301		superfx_add_clocks_internal(cpustate, 4 + ((cpustate->cfgr & SUPERFX_CFGR_MS0) ? 4 : 0));
	1240	superfx_gpr_write(m_dreg_idx, result >> 16);
	1241	m_sfr &= ~SUPERFX_SFR_CY;
	1242	m_sfr |= (result & 0x8000) ? SUPERFX_SFR_CY : 0;
	1243	superfx_dreg_sfr_sz_update();
	1244	superfx_regs_reset();
	1245	superfx_add_clocks_internal(4 + ((m_cfgr & SUPERFX_CFGR_MS0) ? 4 : 0));
1302	1246	break;
1303	1247	}
1304	1248
1305	1249	case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1306	1250	case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: // IBT / LMS / SMS / LMS
1307		switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1251	switch(m_sfr & SUPERFX_SFR_ALT)
1308	1252	{
1309	1253	case SUPERFX_SFR_ALT0: // IBT
1310		superfx_gpr_write(cpustate, op & 0xf, (INT8)superfx_pipe(cpustate));
1311		superfx_regs_reset(cpustate);
	1254	superfx_gpr_write(op & 0xf, (INT8)superfx_pipe());
	1255	superfx_regs_reset();
1312	1256	break;
1313	1257	case SUPERFX_SFR_ALT2: // SMS
1314		cpustate->ramaddr = superfx_pipe(cpustate) << 1;
1315		superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 0, cpustate->r[op & 0xf] >> 0);
1316		superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 1, cpustate->r[op & 0xf] >> 8);
1317		superfx_regs_reset(cpustate);
	1258	m_ramaddr = superfx_pipe() << 1;
	1259	superfx_rambuffer_write(m_ramaddr ^ 0, m_r[op & 0xf] >> 0);
	1260	superfx_rambuffer_write(m_ramaddr ^ 1, m_r[op & 0xf] >> 8);
	1261	superfx_regs_reset();
1318	1262	break;
1319	1263	case SUPERFX_SFR_ALT1: // LMS
1320	1264	case SUPERFX_SFR_ALT3: // LMS
1321	1265	{
1322	1266	UINT16 data = 0;
1323		cpustate->ramaddr = superfx_pipe(cpustate) << 1;
1324		data  = superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 0) << 0;
1325		data |= superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 1) << 8;
1326		superfx_gpr_write(cpustate, op & 0xf, data);
1327		superfx_regs_reset(cpustate);
	1267	m_ramaddr = superfx_pipe() << 1;
	1268	data  = superfx_rambuffer_read(m_ramaddr ^ 0) << 0;
	1269	data |= superfx_rambuffer_read(m_ramaddr ^ 1) << 8;
	1270	superfx_gpr_write(op & 0xf, data);
	1271	superfx_regs_reset();
1328	1272	break;
1329	1273	}
1330	1274	}
r26752	r26753
1332	1276
1333	1277	case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1334	1278	case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: // FROM
1335		if((cpustate->sfr & SUPERFX_SFR_B) == 0)
	1279	if((m_sfr & SUPERFX_SFR_B) == 0)
1336	1280	{
1337		cpustate->sreg = &(cpustate->r[op & 0xf]);
1338		cpustate->sreg_idx = op & 0xf;
	1281	m_sreg = &(m_r[op & 0xf]);
	1282	m_sreg_idx = op & 0xf;
1339	1283	}
1340	1284	else
1341	1285	{
1342		superfx_gpr_write(cpustate, cpustate->dreg_idx, cpustate->r[op & 0xf]);
1343		cpustate->sfr &= ~SUPERFX_SFR_OV;
1344		cpustate->sfr |= (*(cpustate->dreg) & 0x80) ? SUPERFX_SFR_OV : 0;
1345		superfx_dreg_sfr_sz_update(cpustate);
1346		superfx_regs_reset(cpustate);
	1286	superfx_gpr_write(m_dreg_idx, m_r[op & 0xf]);
	1287	m_sfr &= ~SUPERFX_SFR_OV;
	1288	m_sfr |= (*(m_dreg) & 0x80) ? SUPERFX_SFR_OV : 0;
	1289	superfx_dreg_sfr_sz_update();
	1290	superfx_regs_reset();
1347	1291	}
1348	1292	break;
1349	1293
1350	1294	case 0xc0: // HIB
1351		superfx_gpr_write(cpustate, cpustate->dreg_idx, (*(cpustate->sreg)) >> 8);
1352		cpustate->sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
1353		cpustate->sfr |= (*(cpustate->dreg) & 0x80) ? SUPERFX_SFR_S : 0;
1354		cpustate->sfr |= (*(cpustate->dreg) == 0) ? SUPERFX_SFR_Z : 0;
1355		superfx_regs_reset(cpustate);
	1295	superfx_gpr_write(m_dreg_idx, (*(m_sreg)) >> 8);
	1296	m_sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
	1297	m_sfr |= (*(m_dreg) & 0x80) ? SUPERFX_SFR_S : 0;
	1298	m_sfr |= (*(m_dreg) == 0) ? SUPERFX_SFR_Z : 0;
	1299	superfx_regs_reset();
1356	1300	break;
1357	1301
1358	1302	case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1359	1303	case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: // OR / XOR / ORI / XORI
1360		switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1304	switch(m_sfr & SUPERFX_SFR_ALT)
1361	1305	{
1362	1306	case SUPERFX_SFR_ALT0: // OR
1363		superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) | cpustate->r[op & 0xf]);
	1307	superfx_gpr_write(m_dreg_idx, *(m_sreg) | m_r[op & 0xf]);
1364	1308	break;
1365	1309	case SUPERFX_SFR_ALT1: // XOR
1366		superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) ^ cpustate->r[op & 0xf]);
	1310	superfx_gpr_write(m_dreg_idx, *(m_sreg) ^ m_r[op & 0xf]);
1367	1311	break;
1368	1312	case SUPERFX_SFR_ALT2: // ORI
1369		superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) | (op & 0xf));
	1313	superfx_gpr_write(m_dreg_idx, *(m_sreg) | (op & 0xf));
1370	1314	break;
1371	1315	case SUPERFX_SFR_ALT3: // XORI
1372		superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) ^ (op & 0xf));
	1316	superfx_gpr_write(m_dreg_idx, *(m_sreg) ^ (op & 0xf));
1373	1317	break;
1374	1318	}
1375		superfx_dreg_sfr_sz_update(cpustate);
1376		superfx_regs_reset(cpustate);
	1319	superfx_dreg_sfr_sz_update();
	1320	superfx_regs_reset();
1377	1321	break;
1378	1322
1379	1323	case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1380	1324	case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde:            // INC
1381		superfx_gpr_write(cpustate, op & 0xf, cpustate->r[op & 0xf] + 1);
1382		cpustate->sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
1383		cpustate->sfr |= (cpustate->r[op & 0xf] & 0x8000) ? SUPERFX_SFR_S : 0;
1384		cpustate->sfr |= (cpustate->r[op & 0xf] == 0) ? SUPERFX_SFR_Z : 0;
1385		superfx_regs_reset(cpustate);
	1325	superfx_gpr_write(op & 0xf, m_r[op & 0xf] + 1);
	1326	m_sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
	1327	m_sfr |= (m_r[op & 0xf] & 0x8000) ? SUPERFX_SFR_S : 0;
	1328	m_sfr |= (m_r[op & 0xf] == 0) ? SUPERFX_SFR_Z : 0;
	1329	superfx_regs_reset();
1386	1330	break;
1387	1331
1388	1332	case 0xdf: // GETC / RAMB / ROMB
1389		switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1333	switch(m_sfr & SUPERFX_SFR_ALT)
1390	1334	{
1391	1335	case SUPERFX_SFR_ALT0: // GETC
1392	1336	case SUPERFX_SFR_ALT1: // GETC
1393		cpustate->colr = superfx_color(cpustate, superfx_rombuffer_read(cpustate));
1394		superfx_regs_reset(cpustate);
	1337	m_colr = superfx_color(superfx_rombuffer_read());
	1338	superfx_regs_reset();
1395	1339	break;
1396	1340	case SUPERFX_SFR_ALT2: // RAMB
1397		superfx_rambuffer_sync(cpustate);
1398		cpustate->rambr = ((*(cpustate->sreg)) & 1) ? 1 : 0;
1399		superfx_regs_reset(cpustate);
	1341	superfx_rambuffer_sync();
	1342	m_rambr = ((*(m_sreg)) & 1) ? 1 : 0;
	1343	superfx_regs_reset();
1400	1344	break;
1401	1345	case SUPERFX_SFR_ALT3: // ROMB
1402		superfx_rombuffer_sync(cpustate);
1403		cpustate->rombr = *(cpustate->sreg) & 0x7f;
1404		superfx_regs_reset(cpustate);
	1346	superfx_rombuffer_sync();
	1347	m_rombr = *(m_sreg) & 0x7f;
	1348	superfx_regs_reset();
1405	1349	break;
1406	1350	}
1407	1351	break;
1408	1352
1409	1353	case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1410	1354	case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee:            // DEC
1411		superfx_gpr_write(cpustate, op & 0xf, cpustate->r[op & 0xf] - 1);
1412		cpustate->sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
1413		cpustate->sfr |= (cpustate->r[op & 0xf] & 0x8000) ? SUPERFX_SFR_S : 0;
1414		cpustate->sfr |= (cpustate->r[op & 0xf] == 0) ? SUPERFX_SFR_Z : 0;
1415		superfx_regs_reset(cpustate);
	1355	superfx_gpr_write(op & 0xf, m_r[op & 0xf] - 1);
	1356	m_sfr &= ~(SUPERFX_SFR_S | SUPERFX_SFR_Z);
	1357	m_sfr |= (m_r[op & 0xf] & 0x8000) ? SUPERFX_SFR_S : 0;
	1358	m_sfr |= (m_r[op & 0xf] == 0) ? SUPERFX_SFR_Z : 0;
	1359	superfx_regs_reset();
1416	1360	break;
1417	1361
1418	1362	case 0xef: // GETB / GETBH / GETBL / GETBS
1419	1363	{
1420		UINT8 byte = superfx_rombuffer_read(cpustate);
1421		switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1364	UINT8 byte = superfx_rombuffer_read();
	1365	switch(m_sfr & SUPERFX_SFR_ALT)
1422	1366	{
1423	1367	case SUPERFX_SFR_ALT0: // GETB
1424		superfx_gpr_write(cpustate, cpustate->dreg_idx, byte);
	1368	superfx_gpr_write(m_dreg_idx, byte);
1425	1369	break;
1426	1370	case SUPERFX_SFR_ALT1: // GETBH
1427		superfx_gpr_write(cpustate, cpustate->dreg_idx, (byte << 8) | (*(cpustate->sreg) & 0x00ff));
	1371	superfx_gpr_write(m_dreg_idx, (byte << 8) | (*(m_sreg) & 0x00ff));
1428	1372	break;
1429	1373	case SUPERFX_SFR_ALT2: // GETBL
1430		superfx_gpr_write(cpustate, cpustate->dreg_idx, (*(cpustate->sreg) & 0xff00) | (byte << 0));
	1374	superfx_gpr_write(m_dreg_idx, (*(m_sreg) & 0xff00) | (byte << 0));
1431	1375	break;
1432	1376	case SUPERFX_SFR_ALT3: // GETBS
1433		superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT8)byte);
	1377	superfx_gpr_write(m_dreg_idx, (INT8)byte);
1434	1378	break;
1435	1379	}
1436		superfx_regs_reset(cpustate);
	1380	superfx_regs_reset();
1437	1381	break;
1438	1382	}
1439	1383
r26752	r26753
1441	1385	case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: // IWT / LM / SM / LM
1442	1386	{
1443	1387	UINT16 data;
1444		switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1388	switch(m_sfr & SUPERFX_SFR_ALT)
1445	1389	{
1446	1390	case SUPERFX_SFR_ALT0: // IWT
1447		data  = superfx_pipe(cpustate) << 0;
1448		data |= superfx_pipe(cpustate) << 8;
1449		superfx_gpr_write(cpustate, op & 0xf, data);
1450		superfx_regs_reset(cpustate);
	1391	data  = superfx_pipe() << 0;
	1392	data |= superfx_pipe() << 8;
	1393	superfx_gpr_write(op & 0xf, data);
	1394	superfx_regs_reset();
1451	1395	break;
1452	1396	case SUPERFX_SFR_ALT2: // SM
1453		cpustate->ramaddr  = superfx_pipe(cpustate) << 0;
1454		cpustate->ramaddr |= superfx_pipe(cpustate) << 8;
1455		superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 0, cpustate->r[op & 0xf] >> 0);
1456		superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 1, cpustate->r[op & 0xf] >> 8);
1457		superfx_regs_reset(cpustate);
	1397	m_ramaddr  = superfx_pipe() << 0;
	1398	m_ramaddr |= superfx_pipe() << 8;
	1399	superfx_rambuffer_write(m_ramaddr ^ 0, m_r[op & 0xf] >> 0);
	1400	superfx_rambuffer_write(m_ramaddr ^ 1, m_r[op & 0xf] >> 8);
	1401	superfx_regs_reset();
1458	1402	break;
1459	1403	case SUPERFX_SFR_ALT1:
1460	1404	case SUPERFX_SFR_ALT3: // LM
1461		cpustate->ramaddr  = superfx_pipe(cpustate) << 0;
1462		cpustate->ramaddr |= superfx_pipe(cpustate) << 8;
1463		data  = superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 0) << 0;
1464		data |= superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 1) << 8;
1465		superfx_gpr_write(cpustate, op & 0xf, data);
1466		superfx_regs_reset(cpustate);
	1405	m_ramaddr  = superfx_pipe() << 0;
	1406	m_ramaddr |= superfx_pipe() << 8;
	1407	data  = superfx_rambuffer_read(m_ramaddr ^ 0) << 0;
	1408	data |= superfx_rambuffer_read(m_ramaddr ^ 1) << 8;
	1409	superfx_gpr_write(op & 0xf, data);
	1410	superfx_regs_reset();
1467	1411	break;
1468	1412	}
1469	1413	break;
1470	1414	}
1471	1415	}
1472	1416
1473		if(!cpustate->r15_modified)
	1417	if(!m_r15_modified)
1474	1418	{
1475		cpustate->r[15]++;
	1419	m_r[15]++;
1476	1420	}
1477	1421
1478		//printf( " r0:%04x  r1:%04x  r2:%04x  r3:%04x  r4:%04x  r5:%04x  r6:%04x  r7:%04x\n",  cpustate->r[0],  cpustate->r[1],  cpustate->r[2],  cpustate->r[3],  cpustate->r[4],  cpustate->r[5],  cpustate->r[6],  cpustate->r[7] );
1479		//printf( " r8:%04x  r9:%04x r10:%04x r11:%04x r12:%04x r13:%04x r14:%04x r15:%04x\n",  cpustate->r[8],  cpustate->r[9], cpustate->r[10], cpustate->r[11], cpustate->r[12], cpustate->r[13], cpustate->r[14], cpustate->r[15] );
1480		//printf( "sfr:%04x\n", cpustate->sfr );
	1422	//printf( " r0:%04x  r1:%04x  r2:%04x  r3:%04x  r4:%04x  r5:%04x  r6:%04x  r7:%04x\n",  m_r[0],  m_r[1],  m_r[2],  m_r[3],  m_r[4],  m_r[5],  m_r[6],  m_r[7] );
	1423	//printf( " r8:%04x  r9:%04x r10:%04x r11:%04x r12:%04x r13:%04x r14:%04x r15:%04x\n",  m_r[8],  m_r[9], m_r[10], m_r[11], m_r[12], m_r[13], m_r[14], m_r[15] );
	1424	//printf( "sfr:%04x\n", m_sfr );
1481	1425
1482		--cpustate->icount;
	1426	--m_icount;
1483	1427	}
1484	1428	}
1485	1429
1486		/*****************************************************************************/
1487	1430
1488		CPU_DISASSEMBLE( superfx )
	1431	offs_t superfx_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
1489	1432	{
1490		superfx_state *cpustate = get_safe_token(device);
	1433	extern offs_t superfx_dasm_one(char *buffer, offs_t pc, UINT8 op, UINT8 param0, UINT8 param1, UINT16 alt);
1491	1434
1492		UINT8  op = *(UINT8 *)(opram + 0);
1493		UINT8  param0 = *(UINT8 *)(opram + 1);
1494		UINT8  param1 = *(UINT8 *)(opram + 2);
1495		UINT16 alt = cpustate->sfr & SUPERFX_SFR_ALT;
	1435	UINT8  op = *(UINT8 *)(opram + 0);
	1436	UINT8  param0 = *(UINT8 *)(opram + 1);
	1437	UINT8  param1 = *(UINT8 *)(opram + 2);
	1438	UINT16 alt = m_sfr & SUPERFX_SFR_ALT;
1496	1439
1497		return superfx_dasm_one(buffer, pc, op, param0, param1, alt);
	1440	return superfx_dasm_one(buffer, pc, op, param0, param1, alt);
1498	1441	}
1499	1442
1500		/*****************************************************************************/
1501
1502		static CPU_SET_INFO( superfx )
1503		{
1504		superfx_state *cpustate = get_safe_token(device);
1505
1506		switch (state)
1507		{
1508		/* --- the following bits of info are set as 64-bit signed integers --- */
1509		case CPUINFO_INT_PC:
1510		case CPUINFO_INT_REGISTER + SUPERFX_PC:         cpustate->r[15] = info->i;      break;
1511		case CPUINFO_INT_REGISTER + SUPERFX_DREG:       info->i = cpustate->dreg_idx;   break;
1512		case CPUINFO_INT_REGISTER + SUPERFX_SREG:       info->i = cpustate->sreg_idx;   break;
1513		case CPUINFO_INT_REGISTER + SUPERFX_R0:         cpustate->r[0] = info->i;       break;
1514		case CPUINFO_INT_REGISTER + SUPERFX_R1:         cpustate->r[1] = info->i;       break;
1515		case CPUINFO_INT_REGISTER + SUPERFX_R2:         cpustate->r[2] = info->i;       break;
1516		case CPUINFO_INT_REGISTER + SUPERFX_R3:         cpustate->r[3] = info->i;       break;
1517		case CPUINFO_INT_REGISTER + SUPERFX_R4:         cpustate->r[4] = info->i;       break;
1518		case CPUINFO_INT_REGISTER + SUPERFX_R5:         cpustate->r[5] = info->i;       break;
1519		case CPUINFO_INT_REGISTER + SUPERFX_R6:         cpustate->r[6] = info->i;       break;
1520		case CPUINFO_INT_REGISTER + SUPERFX_R7:         cpustate->r[7] = info->i;       break;
1521		case CPUINFO_INT_REGISTER + SUPERFX_R8:         cpustate->r[8] = info->i;       break;
1522		case CPUINFO_INT_REGISTER + SUPERFX_R9:         cpustate->r[9] = info->i;       break;
1523		case CPUINFO_INT_REGISTER + SUPERFX_R10:        cpustate->r[10] = info->i;      break;
1524		case CPUINFO_INT_REGISTER + SUPERFX_R11:        cpustate->r[11] = info->i;      break;
1525		case CPUINFO_INT_REGISTER + SUPERFX_R12:        cpustate->r[12] = info->i;      break;
1526		case CPUINFO_INT_REGISTER + SUPERFX_R13:        cpustate->r[13] = info->i;      break;
1527		case CPUINFO_INT_REGISTER + SUPERFX_R14:        cpustate->r[14] = info->i;      break;
1528		case CPUINFO_INT_REGISTER + SUPERFX_R15:        cpustate->r[15] = info->i;      break;
1529		case CPUINFO_INT_REGISTER + SUPERFX_SFR:        cpustate->sfr = info->i;        break;
1530		case CPUINFO_INT_REGISTER + SUPERFX_PBR:        cpustate->pbr = info->i;        break;
1531		case CPUINFO_INT_REGISTER + SUPERFX_ROMBR:      cpustate->rombr = info->i;      break;
1532		case CPUINFO_INT_REGISTER + SUPERFX_RAMBR:      cpustate->rambr = info->i;      break;
1533		case CPUINFO_INT_REGISTER + SUPERFX_CBR:        cpustate->cbr = info->i;        break;
1534		case CPUINFO_INT_REGISTER + SUPERFX_SCBR:       cpustate->scbr = info->i;       break;
1535		case CPUINFO_INT_REGISTER + SUPERFX_SCMR:       cpustate->scmr = info->i;       break;
1536		case CPUINFO_INT_REGISTER + SUPERFX_COLR:       cpustate->colr = info->i;       break;
1537		case CPUINFO_INT_REGISTER + SUPERFX_POR:        cpustate->por = info->i;        break;
1538		case CPUINFO_INT_REGISTER + SUPERFX_BRAMR:      cpustate->bramr = info->i;      break;
1539		case CPUINFO_INT_REGISTER + SUPERFX_VCR:        cpustate->vcr = info->i;        break;
1540		case CPUINFO_INT_REGISTER + SUPERFX_CFGR:       cpustate->cfgr = info->i;       break;
1541		case CPUINFO_INT_REGISTER + SUPERFX_CLSR:       cpustate->clsr = info->i;       break;
1542		case CPUINFO_INT_REGISTER + SUPERFX_ROMCL:      cpustate->romcl = info->i;      break;
1543		case CPUINFO_INT_REGISTER + SUPERFX_ROMDR:      cpustate->romdr = info->i;      break;
1544		case CPUINFO_INT_REGISTER + SUPERFX_RAMCL:      cpustate->ramcl = info->i;      break;
1545		case CPUINFO_INT_REGISTER + SUPERFX_RAMAR:      cpustate->ramar = info->i;      break;
1546		case CPUINFO_INT_REGISTER + SUPERFX_RAMDR:      cpustate->ramdr = info->i;      break;
1547		case CPUINFO_INT_REGISTER + SUPERFX_RAMADDR:    cpustate->ramaddr = info->i;    break;
1548		}
1549		}
1550
1551		CPU_GET_INFO( superfx )
1552		{
1553		superfx_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
1554
1555		switch(state)
1556		{
1557		/* --- the following bits of info are returned as 64-bit signed integers --- */
1558		case CPUINFO_INT_CONTEXT_SIZE:              info->i = sizeof(superfx_state);                    break;
1559		case CPUINFO_INT_INPUT_LINES:               info->i = 0;                                        break;
1560		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:        info->i = 0;                                        break;
1561		case CPUINFO_INT_ENDIANNESS:                info->i = ENDIANNESS_LITTLE;                        break;
1562		case CPUINFO_INT_CLOCK_MULTIPLIER:          info->i = 1;                                        break;
1563		case CPUINFO_INT_CLOCK_DIVIDER:             info->i = 1;                                        break;
1564		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:     info->i = 1;                                        break;
1565		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:     info->i = 3;                                        break;
1566		case CPUINFO_INT_MIN_CYCLES:                info->i = 1;                                        break;
1567		case CPUINFO_INT_MAX_CYCLES:                info->i = 1;                                        break;
1568
1569		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 8;                                        break;
1570		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM:    info->i = 32;                                       break;
1571		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM:    info->i = 0;                                        break;
1572		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:       info->i = 0;                                        break;
1573		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:       info->i = 0;                                        break;
1574		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:       info->i = 0;                                        break;
1575		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:         info->i = 0;                                        break;
1576		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:         info->i = 0;                                        break;
1577		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:         info->i = 0;                                        break;
1578
1579		case CPUINFO_INT_PC:    /* intentional fallthrough */
1580		case CPUINFO_INT_REGISTER + SUPERFX_PC:         info->i = ((cpustate->pbr << 16) | cpustate->r[15]) - 1; break;
1581		case CPUINFO_INT_REGISTER + SUPERFX_DREG:       info->i = cpustate->dreg_idx;   break;
1582		case CPUINFO_INT_REGISTER + SUPERFX_SREG:       info->i = cpustate->sreg_idx;   break;
1583		case CPUINFO_INT_REGISTER + SUPERFX_R0:         info->i = cpustate->r[0];       break;
1584		case CPUINFO_INT_REGISTER + SUPERFX_R1:         info->i = cpustate->r[1];       break;
1585		case CPUINFO_INT_REGISTER + SUPERFX_R2:         info->i = cpustate->r[2];       break;
1586		case CPUINFO_INT_REGISTER + SUPERFX_R3:         info->i = cpustate->r[3];       break;
1587		case CPUINFO_INT_REGISTER + SUPERFX_R4:         info->i = cpustate->r[4];       break;
1588		case CPUINFO_INT_REGISTER + SUPERFX_R5:         info->i = cpustate->r[5];       break;
1589		case CPUINFO_INT_REGISTER + SUPERFX_R6:         info->i = cpustate->r[6];       break;
1590		case CPUINFO_INT_REGISTER + SUPERFX_R7:         info->i = cpustate->r[7];       break;
1591		case CPUINFO_INT_REGISTER + SUPERFX_R8:         info->i = cpustate->r[8];       break;
1592		case CPUINFO_INT_REGISTER + SUPERFX_R9:         info->i = cpustate->r[9];       break;
1593		case CPUINFO_INT_REGISTER + SUPERFX_R10:        info->i = cpustate->r[10];      break;
1594		case CPUINFO_INT_REGISTER + SUPERFX_R11:        info->i = cpustate->r[11];      break;
1595		case CPUINFO_INT_REGISTER + SUPERFX_R12:        info->i = cpustate->r[12];      break;
1596		case CPUINFO_INT_REGISTER + SUPERFX_R13:        info->i = cpustate->r[13];      break;
1597		case CPUINFO_INT_REGISTER + SUPERFX_R14:        info->i = cpustate->r[14];      break;
1598		case CPUINFO_INT_REGISTER + SUPERFX_R15:        info->i = cpustate->r[15];      break;
1599		case CPUINFO_INT_REGISTER + SUPERFX_SFR:        info->i = cpustate->sfr;        break;
1600		case CPUINFO_INT_REGISTER + SUPERFX_PBR:        info->i = cpustate->pbr;        break;
1601		case CPUINFO_INT_REGISTER + SUPERFX_ROMBR:      info->i = cpustate->rombr;      break;
1602		case CPUINFO_INT_REGISTER + SUPERFX_RAMBR:      info->i = cpustate->rambr;      break;
1603		case CPUINFO_INT_REGISTER + SUPERFX_CBR:        info->i = cpustate->cbr;        break;
1604		case CPUINFO_INT_REGISTER + SUPERFX_SCBR:       info->i = cpustate->scbr;       break;
1605		case CPUINFO_INT_REGISTER + SUPERFX_SCMR:       info->i = cpustate->scmr;       break;
1606		case CPUINFO_INT_REGISTER + SUPERFX_COLR:       info->i = cpustate->colr;       break;
1607		case CPUINFO_INT_REGISTER + SUPERFX_POR:        info->i = cpustate->por;        break;
1608		case CPUINFO_INT_REGISTER + SUPERFX_BRAMR:      info->i = cpustate->bramr;      break;
1609		case CPUINFO_INT_REGISTER + SUPERFX_VCR:        info->i = cpustate->vcr;        break;
1610		case CPUINFO_INT_REGISTER + SUPERFX_CFGR:       info->i = cpustate->cfgr;       break;
1611		case CPUINFO_INT_REGISTER + SUPERFX_CLSR:       info->i = cpustate->clsr;       break;
1612		case CPUINFO_INT_REGISTER + SUPERFX_ROMCL:      info->i = cpustate->romcl;      break;
1613		case CPUINFO_INT_REGISTER + SUPERFX_ROMDR:      info->i = cpustate->romdr;      break;
1614		case CPUINFO_INT_REGISTER + SUPERFX_RAMCL:      info->i = cpustate->ramcl;      break;
1615		case CPUINFO_INT_REGISTER + SUPERFX_RAMAR:      info->i = cpustate->ramar;      break;
1616		case CPUINFO_INT_REGISTER + SUPERFX_RAMDR:      info->i = cpustate->ramdr;      break;
1617		case CPUINFO_INT_REGISTER + SUPERFX_RAMADDR:    info->i = cpustate->ramaddr;    break;
1618
1619		/* --- the following bits of info are returned as pointers to data or functions --- */
1620		case CPUINFO_FCT_SET_INFO:              info->setinfo = CPU_SET_INFO_NAME(superfx);             break;
1621		case CPUINFO_FCT_INIT:                  info->init = CPU_INIT_NAME(superfx);                    break;
1622		case CPUINFO_FCT_RESET:                 info->reset = CPU_RESET_NAME(superfx);                  break;
1623		case CPUINFO_FCT_EXIT:                  info->exit = CPU_EXIT_NAME(superfx);                    break;
1624		case CPUINFO_FCT_EXECUTE:               info->execute = CPU_EXECUTE_NAME(superfx);              break;
1625		case CPUINFO_FCT_BURN:                  info->burn = NULL;                                      break;
1626		case CPUINFO_FCT_DISASSEMBLE:           info->disassemble = CPU_DISASSEMBLE_NAME(superfx);      break;
1627		case CPUINFO_PTR_INSTRUCTION_COUNTER:   info->icount = &cpustate->icount;                       break;
1628
1629		/* --- the following bits of info are returned as NULL-terminated strings --- */
1630		case CPUINFO_STR_NAME:                          strcpy(info->s, "SuperFX");                     break;
1631		case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "superfx");                     break;
1632		case CPUINFO_STR_FAMILY:                        strcpy(info->s, "SuperFX");                     break;
1633		case CPUINFO_STR_VERSION:                       strcpy(info->s, "1.0");                         break;
1634		case CPUINFO_STR_SOURCE_FILE:                   strcpy(info->s, __FILE__);                      break;
1635		case CPUINFO_STR_CREDITS:                       strcpy(info->s, "Copyright Nicola Salmoria and the MAME Team"); break;
1636
1637		case CPUINFO_STR_FLAGS:                         strcpy(info->s, " ");                           break;
1638
1639		case CPUINFO_STR_REGISTER + SUPERFX_PC:         sprintf(info->s, "PC:      %06X", (cpustate->pbr << 16) | cpustate->r[15]); break;
1640		case CPUINFO_STR_REGISTER + SUPERFX_DREG:       sprintf(info->s, "DREG:    R%d",  cpustate->dreg_idx);  break;
1641		case CPUINFO_STR_REGISTER + SUPERFX_SREG:       sprintf(info->s, "SREG:    R%d",  cpustate->sreg_idx);  break;
1642		case CPUINFO_STR_REGISTER + SUPERFX_R0:         sprintf(info->s, "R0:      %04X", cpustate->r[0]);      break;
1643		case CPUINFO_STR_REGISTER + SUPERFX_R1:         sprintf(info->s, "R1:      %04X", cpustate->r[1]);      break;
1644		case CPUINFO_STR_REGISTER + SUPERFX_R2:         sprintf(info->s, "R2:      %04X", cpustate->r[2]);      break;
1645		case CPUINFO_STR_REGISTER + SUPERFX_R3:         sprintf(info->s, "R3:      %04X", cpustate->r[3]);      break;
1646		case CPUINFO_STR_REGISTER + SUPERFX_R4:         sprintf(info->s, "R4:      %04X", cpustate->r[4]);      break;
1647		case CPUINFO_STR_REGISTER + SUPERFX_R5:         sprintf(info->s, "R5:      %04X", cpustate->r[5]);      break;
1648		case CPUINFO_STR_REGISTER + SUPERFX_R6:         sprintf(info->s, "R6:      %04X", cpustate->r[6]);      break;
1649		case CPUINFO_STR_REGISTER + SUPERFX_R7:         sprintf(info->s, "R7:      %04X", cpustate->r[7]);      break;
1650		case CPUINFO_STR_REGISTER + SUPERFX_R8:         sprintf(info->s, "R8:      %04X", cpustate->r[8]);      break;
1651		case CPUINFO_STR_REGISTER + SUPERFX_R9:         sprintf(info->s, "R9:      %04X", cpustate->r[9]);      break;
1652		case CPUINFO_STR_REGISTER + SUPERFX_R10:        sprintf(info->s, "R10:     %04X", cpustate->r[10]);     break;
1653		case CPUINFO_STR_REGISTER + SUPERFX_R11:        sprintf(info->s, "R11:     %04X", cpustate->r[11]);     break;
1654		case CPUINFO_STR_REGISTER + SUPERFX_R12:        sprintf(info->s, "R12:     %04X", cpustate->r[12]);     break;
1655		case CPUINFO_STR_REGISTER + SUPERFX_R13:        sprintf(info->s, "R13:     %04X", cpustate->r[13]);     break;
1656		case CPUINFO_STR_REGISTER + SUPERFX_R14:        sprintf(info->s, "R14:     %04X", cpustate->r[14]);     break;
1657		case CPUINFO_STR_REGISTER + SUPERFX_R15:        sprintf(info->s, "R15:     %04X", cpustate->r[15]);     break;
1658		case CPUINFO_STR_REGISTER + SUPERFX_SFR:        sprintf(info->s, "SFR:     %04X", cpustate->sfr);       break;
1659		case CPUINFO_STR_REGISTER + SUPERFX_PBR:        sprintf(info->s, "PBR:     %02X", cpustate->pbr);       break;
1660		case CPUINFO_STR_REGISTER + SUPERFX_ROMBR:      sprintf(info->s, "ROMBR:   %02X", cpustate->rombr);     break;
1661		case CPUINFO_STR_REGISTER + SUPERFX_RAMBR:      sprintf(info->s, "RAMBR:   %02X", cpustate->rambr);     break;
1662		case CPUINFO_STR_REGISTER + SUPERFX_CBR:        sprintf(info->s, "CBR:     %04X", cpustate->cbr);       break;
1663		case CPUINFO_STR_REGISTER + SUPERFX_SCBR:       sprintf(info->s, "SCBR:    %02X", cpustate->scbr);      break;
1664		case CPUINFO_STR_REGISTER + SUPERFX_SCMR:       sprintf(info->s, "SCMR:    %02X", cpustate->scmr);      break;
1665		case CPUINFO_STR_REGISTER + SUPERFX_COLR:       sprintf(info->s, "COLR     %02X", cpustate->colr);      break;
1666		case CPUINFO_STR_REGISTER + SUPERFX_POR:        sprintf(info->s, "POR:     %02X", cpustate->por);       break;
1667		case CPUINFO_STR_REGISTER + SUPERFX_BRAMR:      sprintf(info->s, "BRAMR:   %02X", cpustate->bramr);     break;
1668		case CPUINFO_STR_REGISTER + SUPERFX_VCR:        sprintf(info->s, "VCR:     %02X", cpustate->vcr);       break;
1669		case CPUINFO_STR_REGISTER + SUPERFX_CFGR:       sprintf(info->s, "CFGR:    %02X", cpustate->cfgr);      break;
1670		case CPUINFO_STR_REGISTER + SUPERFX_CLSR:       sprintf(info->s, "CLSR:    %02X", cpustate->clsr);      break;
1671		case CPUINFO_STR_REGISTER + SUPERFX_ROMCL:      sprintf(info->s, "ROMCL:   %08X", cpustate->romcl);     break;
1672		case CPUINFO_STR_REGISTER + SUPERFX_ROMDR:      sprintf(info->s, "ROMDR:   %02X", cpustate->romdr);     break;
1673		case CPUINFO_STR_REGISTER + SUPERFX_RAMCL:      sprintf(info->s, "RAMCL:   %08X", cpustate->ramcl);     break;
1674		case CPUINFO_STR_REGISTER + SUPERFX_RAMAR:      sprintf(info->s, "RAMAR:   %04X", cpustate->ramar);     break;
1675		case CPUINFO_STR_REGISTER + SUPERFX_RAMDR:      sprintf(info->s, "RAMDR:   %02X", cpustate->ramdr);     break;
1676		case CPUINFO_STR_REGISTER + SUPERFX_RAMADDR:    sprintf(info->s, "RAMADDR: %04X", cpustate->ramaddr);   break;
1677		}
1678		}
1679
1680		DEFINE_LEGACY_CPU_DEVICE(SUPERFX, superfx);

trunk/src/emu/cpu/superfx/superfx.h

r26752	r26753
83	83	#define SUPERFX_CFGR_IRQ    0x80    // IRQ
84	84	#define SUPERFX_CFGR_MS0    0x20    // MS0
85	85
86		struct superfx_config
	86
	87	#define MCFG_SUPERFX_OUT_IRQ(_devcb) \
	88	superfx_device::set_out_irq_func(*device, DEVCB2_##_devcb);
	89
	90
	91	class superfx_device :  public cpu_device
87	92	{
88		devcb_write_line    out_irq_func;           /* IRQ changed callback */
	93	public:
	94	// construction/destruction
	95	superfx_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
	96
	97	// static configuration helpers
	98	template<class _Object> static devcb2_base &set_out_irq_func(device_t &device, _Object object) { return downcast<superfx_device &>(device).m_out_irq_func.set_callback(object); }
	99
	100	UINT8 mmio_read(UINT32 addr);
	101	void mmio_write(UINT32 addr, UINT8 data);
	102	void add_clocks(INT32 clocks);
	103	int access_ram();
	104	int access_rom();
	105
	106	protected:
	107	// device-level overrides
	108	virtual void device_start();
	109	virtual void device_reset();
	110
	111	// device_execute_interface overrides
	112	virtual UINT32 execute_min_cycles() const { return 1; }
	113	virtual UINT32 execute_max_cycles() const { return 1; }
	114	virtual UINT32 execute_input_lines() const { return 0; }
	115	virtual void execute_run();
	116
	117	// device_memory_interface overrides
	118	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
	119
	120	// device_state_interface overrides
	121	virtual void state_import(const device_state_entry &entry);
	122	virtual void state_export(const device_state_entry &entry);
	123
	124	// device_disasm_interface overrides
	125	virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
	126	virtual UINT32 disasm_max_opcode_bytes() const { return 3; }
	127	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	128
	129	private:
	130	address_space_config m_program_config;
	131
	132	devcb2_write_line   m_out_irq_func;
	133
	134	UINT8  m_pipeline;
	135	UINT16 m_ramaddr; // RAM Address
	136
	137	UINT16 m_r[16];   // GPRs
	138	UINT16 m_sfr;     // Status Flag Register
	139	UINT8  m_pbr;     // Program Bank Register
	140	UINT8  m_rombr;   // Game Pack ROM Bank Register
	141	UINT8  m_rambr;   // Game Pack RAM Bank Register
	142	UINT16 m_cbr;     // Cache Base Register
	143	UINT8  m_scbr;    // Screen Base Register
	144	UINT8  m_scmr;    // Screen Mode Register
	145	UINT8  m_colr;    // Color Register
	146	UINT8  m_por;     // Plot Option Register
	147	UINT8  m_bramr;   // Back-Up RAM Register
	148	UINT8  m_vcr;     // Version Code Register
	149	UINT8  m_cfgr;    // Config Register
	150	UINT8  m_clsr;    // Clock Select Register
	151
	152	UINT32 m_romcl;   // Clock ticks until ROMDR is valid
	153	UINT8  m_romdr;   // ROM Buffer Data Register
	154
	155	UINT32 m_ramcl;   // Clock ticks until RAMDR is valid;
	156	UINT16 m_ramar;   // RAM Buffer Address Register
	157	UINT8  m_ramdr;   // RAM Buffer Data Register
	158
	159	UINT16 *m_sreg;   // Source Register (From)
	160	UINT8  m_sreg_idx;// Source Register (To), index
	161	UINT16 *m_dreg;   // Destination Register (To)
	162	UINT8  m_dreg_idx;// Destination Register (To), index
	163	UINT8  m_r15_modified;
	164
	165	UINT8  m_irq;     // IRQ Pending
	166
	167	UINT32 m_cache_access_speed;
	168	UINT32 m_memory_access_speed;
	169
	170	struct {
	171	UINT8 buffer[0x200];
	172	UINT8 valid[0x20];
	173	} m_cache;
	174	struct {
	175	UINT16 offset;
	176	UINT8 bitpend;
	177	UINT8 data[8];
	178	} m_pixelcache[2];
	179
	180	address_space *m_program;
	181	int m_icount;
	182
	183	UINT32 m_debugger_temp;
	184
	185	inline void superfx_regs_reset();
	186	void superfx_update_speed();
	187	void superfx_cache_flush();;
	188	UINT8 superfx_cache_mmio_read(UINT32 addr);
	189	void superfx_cache_mmio_write(UINT32 addr, UINT8 data);
	190	void superfx_memory_reset();
	191	inline UINT8 superfx_bus_read(UINT32 addr);
	192	inline void superfx_bus_write(UINT32 addr, UINT8 data);
	193	inline void superfx_pixelcache_flush(INT32 line);
	194	inline void superfx_plot(UINT8 x, UINT8 y);
	195	UINT8 superfx_rpix(UINT8 x, UINT8 y);
	196	inline UINT8 superfx_color(UINT8 source);
	197	inline void superfx_rambuffer_sync();
	198	inline UINT8 superfx_rambuffer_read(UINT16 addr);
	199	inline void superfx_rambuffer_write(UINT16 addr, UINT8 data);
	200	inline void superfx_rombuffer_sync();
	201	inline void superfx_rombuffer_update();
	202	inline UINT8 superfx_rombuffer_read();
	203	inline void superfx_gpr_write(UINT8 r, UINT16 data);
	204	inline UINT8 superfx_op_read(UINT16 addr);
	205	inline UINT8 superfx_peekpipe();
	206	inline UINT8 superfx_pipe();
	207	inline void superfx_add_clocks_internal(UINT32 clocks);
	208	void superfx_timing_reset();
	209	inline void superfx_dreg_sfr_sz_update();
89	210	};
90		#define SUPERFX_CONFIG(name) const superfx_config (name) =
91	211
92		DECLARE_LEGACY_CPU_DEVICE(SUPERFX, superfx);
93	212
94		CPU_DISASSEMBLE( superfx );
95		extern offs_t superfx_dasm_one(char *buffer, offs_t pc, UINT8 op, UINT8 param0, UINT8 param1, UINT16 alt);
	213	extern const device_type SUPERFX;
96	214
97		UINT8 superfx_mmio_read(device_t *cpu, UINT32 addr);
98		void superfx_mmio_write(device_t *cpu, UINT32 addr, UINT8 data);
99		void superfx_add_clocks(device_t *cpu, INT32 clocks);
100		int superfx_access_ram(device_t *cpu);
101		int superfx_access_rom(device_t *cpu);
102
103	215	#endif /* __SUPERFX_H__ */

trunk/src/mess/machine/sns_sfx.c

r26752	r26753
85	85	machine().device("maincpu")->execute().set_input_line(G65816_LINE_IRQ, state);
86	86	}
87	87
88		static SUPERFX_CONFIG( snes_sfx_config )
89		{
90		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, sns_rom_superfx_device, snes_extern_irq_w)  /* IRQ line from cart */
91		};
92	88
93
94	89	static MACHINE_CONFIG_FRAGMENT( snes_sfx )
95	90	MCFG_CPU_ADD("superfx", SUPERFX, 21480000)  /* 21.48MHz */
96	91	MCFG_CPU_PROGRAM_MAP(sfx_map)
97		MCFG_CPU_CONFIG(snes_sfx_config)
	92	MCFG_SUPERFX_OUT_IRQ(WRITELINE(sns_rom_superfx_device, snes_extern_irq_w))  /* IRQ line from cart */
98	93	MACHINE_CONFIG_END
99	94
100	95	machine_config_constructor sns_rom_superfx_device::device_mconfig_additions() const
r26752	r26753
104	99
105	100	READ8_MEMBER( sns_rom_superfx_device::chip_read )
106	101	{
107		return superfx_mmio_read(m_superfx, offset);
	102	return m_superfx->mmio_read(offset);
108	103	}
109	104
110	105	WRITE8_MEMBER( sns_rom_superfx_device::chip_write )
111	106	{
112		superfx_mmio_write(m_superfx, offset, data);
	107	m_superfx->mmio_write(offset, data);
113	108	}
114	109
115	110
r26752	r26753
124	119	return m_rom[rom_bank_map[offset / 0x10000] * 0x8000 + (offset & 0x7fff)];
125	120	else if (offset < 0x600000)
126	121	{
127		if (superfx_access_rom(m_superfx))
	122	if (m_superfx->access_rom())
128	123	{
129	124	return m_rom[rom_bank_map[(offset - 0x400000) / 0x8000] * 0x8000 + (offset & 0x7fff)];
130	125	}
r26752	r26753
142	137
143	138	READ8_MEMBER( sns_rom_superfx_device::read_ram )
144	139	{
145		if (superfx_access_ram(m_superfx))
	140	if (m_superfx->access_ram())
146	141	return sfx_ram[offset & 0xfffff];
147	142	return 0xff;    // should be open bus...
148	143	}
149	144
150	145	WRITE8_MEMBER( sns_rom_superfx_device::write_ram )
151	146	{
152		if (superfx_access_ram(m_superfx))
	147	if (m_superfx->access_ram())
153	148	sfx_ram[offset & 0xfffff] = data;
154	149	}

trunk/src/mess/machine/sns_sfx.h

r26752	r26753
19	19	virtual void device_reset();
20	20	virtual machine_config_constructor device_mconfig_additions() const;
21	21
22		required_device<device_t> m_superfx;
	22	required_device<superfx_device> m_superfx;
23	23
24	24	// additional reading and writing
25	25	virtual DECLARE_READ8_MEMBER(read_l);

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