trunk/src/emu/machine/mc6852.c
| r26711 | r26712 | |
|---|
| 128 | 128 | // or initialize to defaults if none provided |
| 129 | 129 | else |
| 130 | 130 | { |
| 131 | | memset(&m_in_rx_data_cb, 0, sizeof(m_in_rx_data_cb)); |
| 132 | 131 | memset(&m_out_tx_data_cb, 0, sizeof(m_out_tx_data_cb)); |
| 133 | 132 | memset(&m_out_irq_cb, 0, sizeof(m_out_irq_cb)); |
| 134 | | memset(&m_in_cts_cb, 0, sizeof(m_in_cts_cb)); |
| 135 | | memset(&m_in_dcd_cb, 0, sizeof(m_in_dcd_cb)); |
| 136 | 133 | memset(&m_out_sm_dtr_cb, 0, sizeof(m_out_sm_dtr_cb)); |
| 137 | 134 | memset(&m_out_tuf_cb, 0, sizeof(m_out_tuf_cb)); |
| 138 | 135 | } |
| r26711 | r26712 | |
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| 146 | 143 | void mc6852_device::device_start() |
| 147 | 144 | { |
| 148 | 145 | // resolve callbacks |
| 149 | | m_in_rx_data_func.resolve(m_in_rx_data_cb, *this); |
| 150 | 146 | m_out_tx_data_func.resolve(m_out_tx_data_cb, *this); |
| 151 | 147 | m_out_irq_func.resolve(m_out_irq_cb, *this); |
| 152 | | m_in_cts_func.resolve(m_in_cts_cb, *this); |
| 153 | | m_in_dcd_func.resolve(m_in_dcd_cb, *this); |
| 154 | 148 | m_out_sm_dtr_func.resolve(m_out_sm_dtr_cb, *this); |
| 155 | 149 | m_out_tuf_func.resolve(m_out_tuf_cb, *this); |
| 156 | 150 | |
| r26711 | r26712 | |
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| 369 | 363 | { |
| 370 | 364 | return m_tuf; |
| 371 | 365 | } |
| 366 | |
| 367 | |
| 368 | //------------------------------------------------- |
| 369 | // write_rx - |
| 370 | //------------------------------------------------- |
| 371 | |
| 372 | WRITE_LINE_MEMBER( mc6852_device::write_rx ) |
| 373 | { |
| 374 | m_rxd = state; |
| 375 | } |
trunk/src/emu/machine/mc6852.h
| r26711 | r26712 | |
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| 57 | 57 | UINT32 m_rx_clock; |
| 58 | 58 | UINT32 m_tx_clock; |
| 59 | 59 | |
| 60 | | devcb_read_line m_in_rx_data_cb; |
| 61 | 60 | devcb_write_line m_out_tx_data_cb; |
| 62 | 61 | |
| 63 | 62 | devcb_write_line m_out_irq_cb; |
| 64 | 63 | |
| 65 | | devcb_read_line m_in_cts_cb; |
| 66 | | devcb_read_line m_in_dcd_cb; |
| 67 | 64 | devcb_write_line m_out_sm_dtr_cb; |
| 68 | 65 | devcb_write_line m_out_tuf_cb; |
| 69 | 66 | }; |
| r26711 | r26712 | |
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| 81 | 78 | DECLARE_READ8_MEMBER( read ); |
| 82 | 79 | DECLARE_WRITE8_MEMBER( write ); |
| 83 | 80 | |
| 81 | DECLARE_WRITE_LINE_MEMBER( write_rx ); |
| 84 | 82 | DECLARE_WRITE_LINE_MEMBER( rx_clk_w ); |
| 85 | 83 | DECLARE_WRITE_LINE_MEMBER( tx_clk_w ); |
| 86 | 84 | DECLARE_WRITE_LINE_MEMBER( cts_w ); |
| r26711 | r26712 | |
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| 122 | 120 | UINT8 m_rdr; // receive data register |
| 123 | 121 | UINT8 m_rsr; // receive shift register |
| 124 | 122 | |
| 123 | int m_rxd; |
| 125 | 124 | int m_cts; // clear to send |
| 126 | 125 | int m_dcd; // data carrier detect |
| 127 | 126 | int m_sm_dtr; // sync match/data terminal ready |