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r26689 Sunday 22nd December, 2013 at 21:17:17 UTC by Carl

(mess) mega Soviet clone patch [shattered] - moves ec184*, iskr103* and mc1502 out of pc.c - moves CGA font upload support to a subclass - adds new drivers: poisk1, ec1847, pk88 - adds a skeleton of native iskr103* keyboard i8089: implement remaining instructions and support execution from "io" space. [Carl] (mess) isbc-215g: add intel isbc-215g hdd controller, read only for now [Carl] (mess) isbc: add hdd support to isbc2861 (nw)

[hash]	ec1841.xml mc1502_flop.xml
[src/emu/bus]	bus.mak
[src/emu/bus/pc_kbd]	ec1841.c iskr1030.c* iskr1030.h* keyboards.c keyboards.h
[src/emu/cpu/i8089]	i8089.c i8089.h i8089_channel.c i8089_channel.h i8089_dasm.c i8089_ops.c
[src/emu/video]	pc_cga.c
[src/mess]	mess.lst mess.mak
[src/mess/drivers]	ec184x.c* isbc.c iskr103x.c* mc1502.c* pc.c poisk1.c*
[src/mess/includes]	ec184x.h* genpc.h mc1502.h* pc.h poisk1.h*
[src/mess/machine]	genpc.c isa_cards.c isbc_215g.c* isbc_215g.h* kb_poisk1.h* mc1502_fdc.c* mc1502_fdc.h* mc1502_rom.c* mc1502_rom.h* p1_fdc.c* p1_fdc.h* p1_hdc.c* p1_hdc.h* p1_rom.c* p1_rom.h* pc.c xsu_cards.c* xsu_cards.h*
[src/mess/video]	isa_cga.c isa_cga.h poisk1.c* poisk1.h*

trunk/src/emu/bus/pc_kbd/iskr1030.h

r0	r26689
	1	/**********************************************************************
	2
	3	Iskra-1030 XX-key keyboard emulation
	4
	5	Copyright MESS Team.
	6	Visit http://mamedev.org for licensing and usage restrictions.
	7
	8	*********************************************************************/
	9
	10	#pragma once
	11
	12	#ifndef __PC_KBD_ISKR_1030__
	13	#define __PC_KBD_ISKR_1030__
	14
	15	#include "emu.h"
	16	#include "cpu/mcs48/mcs48.h"
	17	#include "pc_kbdc.h"
	18	#include "machine/rescap.h"
	19
	20
	21
	22	//**************************************************************************
	23	//  TYPE DEFINITIONS
	24	//**************************************************************************
	25
	26	// ======================> iskr_1030_keyboard_device
	27
	28	class iskr_1030_keyboard_device :  public device_t,
	29	public device_pc_kbd_interface
	30	{
	31	public:
	32	// construction/destruction
	33	iskr_1030_keyboard_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	34
	35	// optional information overrides
	36	virtual const rom_entry *device_rom_region() const;
	37	virtual machine_config_constructor device_mconfig_additions() const;
	38	virtual ioport_constructor device_input_ports() const;
	39
	40	DECLARE_READ8_MEMBER( p1_r );
	41	DECLARE_WRITE8_MEMBER( p1_w );
	42	DECLARE_WRITE8_MEMBER( p2_w );
	43	DECLARE_READ8_MEMBER( t0_r );
	44	DECLARE_READ8_MEMBER( t1_r );
	45
	46	protected:
	47	// device-level overrides
	48	virtual void device_start();
	49	virtual void device_reset();
	50
	51	// device_pc_kbd_interface overrides
	52	virtual DECLARE_WRITE_LINE_MEMBER( clock_write );
	53	virtual DECLARE_WRITE_LINE_MEMBER( data_write );
	54
	55	private:
	56	required_device<cpu_device> m_maincpu;
	57	required_ioport m_md00;
	58	required_ioport m_md01;
	59	required_ioport m_md02;
	60	required_ioport m_md03;
	61	required_ioport m_md04;
	62	required_ioport m_md05;
	63	required_ioport m_md06;
	64	required_ioport m_md07;
	65	required_ioport m_md08;
	66	required_ioport m_md09;
	67	required_ioport m_md10;
	68	required_ioport m_md11;
	69	required_ioport m_md12;
	70	required_ioport m_md13;
	71	required_ioport m_md14;
	72	required_ioport m_md15;
	73
	74	UINT8 m_p1;
	75	UINT8 m_p2;
	76	int m_q;
	77	};
	78
	79
	80	// device type definition
	81	extern const device_type PC_KBD_ISKR_1030;
	82
	83	#endif

Property changes on: trunk/src/emu/bus/pc_kbd/iskr1030.h

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/emu/bus/pc_kbd/keyboards.c

r26688	r26689
2	2	#include "emu.h"
3	3	#include "keyboards.h"
4	4	#include "ec1841.h"
	5	#include "iskr1030.h"
5	6	#include "keytro.h"
6	7	#include "msnat.h"
7	8	#include "pc83.h"
r26688	r26689
13	14	SLOT_INTERFACE(STR_KBD_IBM_PC_83, PC_KBD_IBM_PC_83)
14	15	SLOT_INTERFACE(STR_KBD_IBM_PC_XT_83, PC_KBD_IBM_PC_XT_83)
15	16	SLOT_INTERFACE(STR_KBD_EC_1841, PC_KBD_EC_1841)
	17	SLOT_INTERFACE(STR_KBD_ISKR_1030, PC_KBD_ISKR_1030)
16	18	SLOT_INTERFACE_END
17	19
18	20

trunk/src/emu/bus/pc_kbd/keyboards.h

r26688	r26689
13	13	#define STR_KBD_IBM_PC_83           "pc"
14	14	#define STR_KBD_IBM_PC_XT_83        "pcxt"
15	15	#define STR_KBD_EC_1841             "ec1841"
	16	#define STR_KBD_ISKR_1030           "iskr1030"
16	17
17	18	SLOT_INTERFACE_EXTERN(pc_xt_keyboards);
18	19

trunk/src/emu/bus/pc_kbd/ec1841.c

r26688	r26689
107	107	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TAB) PORT_CHAR(UCHAR_MAMEKEY(TAB))
108	108	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
109	109	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
110		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?59?") // 0x59 = Inf
	110	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Inf") PORT_CODE(KEYCODE_SLASH_PAD) PORT_CHAR(UCHAR_MAMEKEY(SLASH_PAD)) // 0x59
111	111	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS_PAD) PORT_CHAR(UCHAR_MAMEKEY(MINUS_PAD))
112	112	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
113	113	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )

trunk/src/emu/bus/pc_kbd/iskr1030.c

r0	r26689
	1	/**********************************************************************
	2
	3	Iskra-1030 and -1031 XX-key keyboard emulation
	4
	5	Copyright MESS Team.
	6	Visit http://mamedev.org for licensing and usage restrictions.
	7
	8	*********************************************************************/
	9
	10	#include "iskr1030.h"
	11
	12	#define VERBOSE_DBG 1       /* general debug messages */
	13
	14	#define DBG_LOG(N,M,A) \
	15	do { \
	16	if(VERBOSE_DBG>=N) \
	17	{ \
	18	logerror("%11.6f at %s: ",machine().time().as_double(),machine().describe_context()); \
	19	logerror A; \
	20	} \
	21	} while (0)
	22
	23
	24
	25	//**************************************************************************
	26	//  MACROS / CONSTANTS
	27	//**************************************************************************
	28
	29	#define I8048_TAG       "i8048"
	30
	31
	32
	33	//**************************************************************************
	34	//  DEVICE DEFINITIONS
	35	//**************************************************************************
	36
	37	const device_type PC_KBD_ISKR_1030 = &device_creator<iskr_1030_keyboard_device>;
	38
	39
	40	//-------------------------------------------------
	41	//  ROM( iskr_1030_keyboard )
	42	//-------------------------------------------------
	43
	44	ROM_START( iskr_1030_keyboard )
	45	ROM_REGION( 0x800, I8048_TAG, 0 )
	46	// XXX add P/N etc
	47	ROM_LOAD( "i1030.bin", 0x000, 0x800, CRC(7cac9c4b) SHA1(03959d3350e012ebfe61cee9c062b6c1fdd8766e) )
	48	ROM_END
	49
	50
	51	//-------------------------------------------------
	52	//  rom_region - device-specific ROM region
	53	//-------------------------------------------------
	54
	55	const rom_entry *iskr_1030_keyboard_device::device_rom_region() const
	56	{
	57	return ROM_NAME( iskr_1030_keyboard );
	58	}
	59
	60
	61	//-------------------------------------------------
	62	//  ADDRESS_MAP( kb_io )
	63	//-------------------------------------------------
	64
	65	static ADDRESS_MAP_START( iskr_1030_keyboard_io, AS_IO, 8, iskr_1030_keyboard_device )
	66	AM_RANGE(0x00, 0xFF) AM_RAM
	67	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_READWRITE(p1_r, p1_w)
	68	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_WRITE(p2_w)
	69	//   AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ(t0_r)
	70	AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ(t1_r)
	71	ADDRESS_MAP_END
	72
	73
	74	//-------------------------------------------------
	75	//  MACHINE_DRIVER( iskr_1030_keyboard )
	76	//-------------------------------------------------
	77
	78	static MACHINE_CONFIG_FRAGMENT( iskr_1030_keyboard )
	79	// XXX check
	80	MCFG_CPU_ADD(I8048_TAG, I8048, MCS48_LC_CLOCK(IND_U(47), CAP_P(20.7)))
	81	MCFG_CPU_IO_MAP(iskr_1030_keyboard_io)
	82	MACHINE_CONFIG_END
	83
	84
	85	//-------------------------------------------------
	86	//  machine_config_additions - device-specific
	87	//  machine configurations
	88	//-------------------------------------------------
	89
	90	machine_config_constructor iskr_1030_keyboard_device::device_mconfig_additions() const
	91	{
	92	return MACHINE_CONFIG_NAME( iskr_1030_keyboard );
	93	}
	94
	95
	96	//-------------------------------------------------
	97	//  INPUT_PORTS( iskr_1030_keyboard )
	98	//-------------------------------------------------
	99
	100	INPUT_PORTS_START( iskr_1030_keyboard )
	101	PORT_START("MD00")
	102	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
	103	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TAB) PORT_CHAR(UCHAR_MAMEKEY(TAB))
	104	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
	105	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
	106	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?59?") // 0x59 = Inf
	107	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS_PAD) PORT_CHAR(UCHAR_MAMEKEY(MINUS_PAD))
	108	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	109	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	110
	111	PORT_START("MD01")
	112	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
	113	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
	114	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
	115	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
	116	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
	117	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 7 Home") PORT_CODE(KEYCODE_7_PAD) PORT_CHAR(UCHAR_MAMEKEY(7_PAD))
	118	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	119	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	120
	121	PORT_START("MD02")
	122	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
	123	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
	124	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
	125	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
	126	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_RCONTROL) // 0x5a = R/L (R)
	127	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 8 "UTF8_UP) PORT_CODE(KEYCODE_8_PAD) PORT_CHAR(UCHAR_MAMEKEY(8_PAD))
	128	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	129	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	130
	131	PORT_START("MD03")
	132	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('@')
	133	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
	134	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
	135	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
	136	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F12) PORT_CHAR(UCHAR_MAMEKEY(F12)) // 0x5b = Rus
	137	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 9 PgUp") PORT_CODE(KEYCODE_9_PAD) PORT_CHAR(UCHAR_MAMEKEY(9_PAD))
	138	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	139	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	140
	141	PORT_START("MD04")
	142	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
	143	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
	144	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
	145	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
	146	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1))
	147	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 4 "UTF8_LEFT) PORT_CODE(KEYCODE_4_PAD) PORT_CHAR(UCHAR_MAMEKEY(4_PAD))
	148	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	149	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	150
	151	PORT_START("MD05")
	152	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
	153	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
	154	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
	155	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')
	156	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F2))
	157	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5_PAD) PORT_CHAR(UCHAR_MAMEKEY(5_PAD))
	158	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	159	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	160
	161	PORT_START("MD06")
	162	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
	163	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
	164	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
	165	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')
	166	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F3) PORT_CHAR(UCHAR_MAMEKEY(F3))
	167	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 6 "UTF8_RIGHT) PORT_CODE(KEYCODE_6_PAD) PORT_CHAR(UCHAR_MAMEKEY(6_PAD))
	168	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	169	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	170
	171	PORT_START("MD07")
	172	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('^')
	173	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
	174	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
	175	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TILDE) PORT_CHAR('`') PORT_CHAR('~')
	176	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F4) PORT_CHAR(UCHAR_MAMEKEY(F4))
	177	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 1 End") PORT_CODE(KEYCODE_1_PAD) PORT_CHAR(UCHAR_MAMEKEY(1_PAD))
	178	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	179	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	180
	181	PORT_START("MD08")
	182	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&')
	183	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
	184	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
	185	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?2a?")
	186	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F5) PORT_CHAR(UCHAR_MAMEKEY(F5))
	187	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 2 "UTF8_DOWN) PORT_CODE(KEYCODE_2_PAD) PORT_CHAR(UCHAR_MAMEKEY(2_PAD))
	188	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	189	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	190
	191	PORT_START("MD09")
	192	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('*')
	193	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
	194	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
	195	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?5c?") // 0x5c = YO
	196	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F6) PORT_CHAR(UCHAR_MAMEKEY(F6))
	197	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 3 PgDn") PORT_CODE(KEYCODE_3_PAD) PORT_CHAR(UCHAR_MAMEKEY(3_PAD))
	198	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	199	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	200
	201	PORT_START("MD10")
	202	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR('(')
	203	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
	204	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}')
	205	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
	206	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F7) PORT_CHAR(UCHAR_MAMEKEY(F7))
	207	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 0 Ins") PORT_CODE(KEYCODE_0_PAD) PORT_CHAR(UCHAR_MAMEKEY(0_PAD))
	208	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	209	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	210
	211	PORT_START("MD11")
	212	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(')')
	213	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?36?")
	214	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
	215	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
	216	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F8) PORT_CHAR(UCHAR_MAMEKEY(F8))
	217	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad . Del") PORT_CODE(KEYCODE_DEL_PAD) PORT_CHAR(UCHAR_MAMEKEY(DEL_PAD))
	218	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	219	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	220
	221	PORT_START("MD12")
	222	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('_')
	223	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?3a?")
	224	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('\'') PORT_CHAR('"')
	225	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1) // 0x55
	226	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F9) PORT_CHAR(UCHAR_MAMEKEY(F9))
	227	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_PLUS_PAD) PORT_CHAR(UCHAR_MAMEKEY(PLUS_PAD))
	228	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	229	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	230
	231	PORT_START("MD13")
	232	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('+')
	233	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
	234	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
	235	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK)) // 0x56
	236	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F10) PORT_CHAR(UCHAR_MAMEKEY(F10))
	237	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
	238	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	239	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	240
	241	PORT_START("MD14")
	242	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|')
	243	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_PRTSCR)
	244	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LALT) PORT_CHAR(UCHAR_MAMEKEY(LALT))
	245	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F11) PORT_CHAR(UCHAR_MAMEKEY(F11)) // 0x57 = Lat
	246	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_NUMLOCK) PORT_CHAR(UCHAR_MAMEKEY(NUMLOCK))
	247	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
	248	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	249	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	250
	251	PORT_START("MD15")
	252	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
	253	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
	254	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1) // 0x54
	255	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_RALT) // 0x58 = R/L (L)
	256	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Scroll Lock Break") PORT_CODE(KEYCODE_SCRLOCK) PORT_CHAR(UCHAR_MAMEKEY(SCRLOCK))
	257	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
	258	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	259	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	260	INPUT_PORTS_END
	261
	262
	263	//-------------------------------------------------
	264	//  input_ports - device-specific input ports
	265	//-------------------------------------------------
	266
	267	ioport_constructor iskr_1030_keyboard_device::device_input_ports() const
	268	{
	269	return INPUT_PORTS_NAME( iskr_1030_keyboard );
	270	}
	271
	272
	273
	274	//**************************************************************************
	275	//  LIVE DEVICE
	276	//**************************************************************************
	277
	278	//-------------------------------------------------
	279	//  iskr_1030_keyboard_device - constructor
	280	//-------------------------------------------------
	281
	282	iskr_1030_keyboard_device::iskr_1030_keyboard_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	283	: device_t(mconfig, PC_KBD_ISKR_1030, "Iskra-1030 Keyboard", tag, owner, clock, "kb_iskr1030", __FILE__),
	284	device_pc_kbd_interface(mconfig, *this),
	285	m_maincpu(*this, I8048_TAG),
	286	m_md00(*this, "MD00"),
	287	m_md01(*this, "MD01"),
	288	m_md02(*this, "MD02"),
	289	m_md03(*this, "MD03"),
	290	m_md04(*this, "MD04"),
	291	m_md05(*this, "MD05"),
	292	m_md06(*this, "MD06"),
	293	m_md07(*this, "MD07"),
	294	m_md08(*this, "MD08"),
	295	m_md09(*this, "MD09"),
	296	m_md10(*this, "MD10"),
	297	m_md11(*this, "MD11"),
	298	m_md12(*this, "MD12"),
	299	m_md13(*this, "MD13"),
	300	m_md14(*this, "MD14"),
	301	m_md15(*this, "MD15"),
	302	m_p1(0),
	303	m_p2(0),
	304	m_q(0)
	305	{
	306	}
	307
	308
	309	//-------------------------------------------------
	310	//  device_start - device-specific startup
	311	//-------------------------------------------------
	312
	313	void iskr_1030_keyboard_device::device_start()
	314	{
	315	set_pc_kbdc_device();
	316
	317	// state saving
	318	save_item(NAME(m_p1));
	319	save_item(NAME(m_p2));
	320	save_item(NAME(m_q));
	321	}
	322
	323
	324	//-------------------------------------------------
	325	//  device_reset - device-specific reset
	326	//-------------------------------------------------
	327
	328	void iskr_1030_keyboard_device::device_reset()
	329	{
	330	}
	331
	332
	333	//-------------------------------------------------
	334	//  clock_write -
	335	//-------------------------------------------------
	336
	337	WRITE_LINE_MEMBER( iskr_1030_keyboard_device::clock_write )
	338	{
	339	DBG_LOG(1,0,( "%s: clock write %d\n", tag(), state));
	340	m_maincpu->set_input_line(MCS48_INPUT_IRQ, state ? CLEAR_LINE : ASSERT_LINE);
	341	}
	342
	343
	344	//-------------------------------------------------
	345	//  data_write -
	346	//-------------------------------------------------
	347
	348	WRITE_LINE_MEMBER( iskr_1030_keyboard_device::data_write )
	349	{
	350	DBG_LOG(1,0,( "%s: data write %d\n", tag(), state));
	351	}
	352
	353
	354	//-------------------------------------------------
	355	//  t0_r - XXX ENT0 CLK
	356	//-------------------------------------------------
	357
	358	READ8_MEMBER( iskr_1030_keyboard_device::t0_r )
	359	{
	360	return 0;
	361	//   return clock_signal();
	362	}
	363
	364
	365	//-------------------------------------------------
	366	//  t1_r - OK
	367	//-------------------------------------------------
	368
	369	READ8_MEMBER( iskr_1030_keyboard_device::t1_r )
	370	{
	371	UINT8 data = data_signal();
	372
	373	DBG_LOG(2,0,( "%s: t1_r %d\n", tag(), data));
	374
	375	return data;
	376	}
	377
	378
	379	//-------------------------------------------------
	380	//  p1_r -
	381	//-------------------------------------------------
	382
	383	READ8_MEMBER( iskr_1030_keyboard_device::p1_r )
	384	{
	385	/*
	386
	387	bit     description
	388
	389	0       -REQ IN
	390	1       DATA IN
	391	2
	392	3
	393	4
	394	5
	395	6
	396	7
	397
	398	*/
	399
	400	UINT8 data = 0;
	401
	402	DBG_LOG(1,0,( "%s: p1_r %02x\n", tag(), data));
	403
	404	return data;
	405	}
	406
	407
	408	//-------------------------------------------------
	409	//  p2_w -
	410	//-------------------------------------------------
	411
	412	WRITE8_MEMBER( iskr_1030_keyboard_device::p2_w )
	413	{
	414	/*
	415	bit     description
	416
	417	0
	418	1
	419	2
	420	3
	421	4
	422	5       LED XXX
	423	6       LED XXX
	424	7       LED XXX
	425	*/
	426	DBG_LOG(1,0,( "%s: p2_w %02x\n", tag(), data));
	427
	428	m_p1 = data;
	429	}
	430
	431
	432	//-------------------------------------------------
	433	//  p1_w - OK
	434	//-------------------------------------------------
	435
	436	WRITE8_MEMBER( iskr_1030_keyboard_device::p1_w )
	437	{
	438	/*
	439	bit     description
	440
	441	0       XXX
	442	1       XXX
	443	2       XXX
	444	3       XXX
	445	4       CLOCK out
	446	5       DATA out (inverted!)
	447	6       XXX
	448	7       XXX
	449	*/
	450	DBG_LOG(1,0,( "%s: p1_w %02x (clk %d data %d)\n", tag(), data, BIT(data, 4), BIT(data, 5)));
	451
	452	m_pc_kbdc->data_write_from_kb(BIT(data, 5));
	453	m_pc_kbdc->clock_write_from_kb(BIT(data, 4));
	454	}

Property changes on: trunk/src/emu/bus/pc_kbd/iskr1030.c

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/emu/bus/bus.mak

r26688	r26689
313	313	BUSOBJS += $(BUSOBJ)/pc_kbd/pc_kbdc.o
314	314	BUSOBJS += $(BUSOBJ)/pc_kbd/keyboards.o
315	315	BUSOBJS += $(BUSOBJ)/pc_kbd/ec1841.o
	316	BUSOBJS += $(BUSOBJ)/pc_kbd/iskr1030.o
316	317	BUSOBJS += $(BUSOBJ)/pc_kbd/keytro.o
317	318	BUSOBJS += $(BUSOBJ)/pc_kbd/msnat.o
318	319	BUSOBJS += $(BUSOBJ)/pc_kbd/pc83.o

trunk/src/emu/video/pc_cga.c

r26688	r26689
144	144	PORT_BIT ( 0x03, 0x01, IPT_UNUSED ) /* via poisk2 */
145	145	PORT_CONFNAME( 0x1C, 0x00, "CGA monitor type")
146	146	PORT_CONFSETTING(0x00, "Colour RGB")
147		PORT_CONFSETTING(0x04, "Mono RGB")
	147	PORT_CONFSETTING(0x08, "Colour composite")
148	148	PORT_BIT ( 0xE0, 0x00, IPT_UNUSED ) /* Chipset is always IBM */
149	149	INPUT_PORTS_END
150	150

trunk/src/emu/cpu/i8089/i8089_channel.c

r26688	r26689
104	104	//  IMPLEMENTATION
105	105	//**************************************************************************
106	106
107		void i8089_channel::set_reg(int reg, int value, int tag)
	107	void i8089_channel::set_reg(int reg, UINT32 value, int tag)
108	108	{
109		m_r[reg].w = value;
	109	if((reg == BC) || (reg == IX) || (reg == CC) || (reg == MC))
	110	{
	111	m_r[reg].w = value & 0xffff;
	112	return;
	113	}
	114	m_r[reg].w = value & 0xfffff;
110	115
	116	if(reg == PP)
	117	{
	118	m_r[PP].t = 0;
	119	return;
	120	}
	121
111	122	if (tag != -1)
112	123	m_r[reg].t = tag;
113	124
r26688	r26689
122	133	bool i8089_channel::chained()      { return CC_CHAIN; }
123	134	bool i8089_channel::lock()         { return CC_LOCK; }
124	135
125		UINT16 i8089_channel::displacement(int wb)
	136	INT16 i8089_channel::displacement(int wb)
126	137	{
127		UINT16 displacement = 0;
	138	INT16 displacement = 0;
128	139
129	140	if (wb == 1)
130	141	{
131		displacement = m_iop->read_byte(m_r[TP].w);
	142	displacement = (INT16)((INT8)m_iop->read_byte(m_r[TP].t, m_r[TP].w));
132	143	set_reg(TP, m_r[TP].w + 1);
133	144	}
134	145	else if (wb == 2)
135	146	{
136		displacement = m_iop->read_word(m_r[TP].w);
	147	displacement = (INT16)m_iop->read_word(m_r[TP].t, m_r[TP].w);
137	148	set_reg(TP, m_r[TP].w + 2);
138	149	}
139	150
140	151	return displacement;
141	152	}
142	153
143		UINT8 i8089_channel::offset(int aa)
	154	UINT32 i8089_channel::offset(int aa, int mm, int w)
144	155	{
145		UINT8 offset = 0;
146
147		if (aa == 1)
	156	UINT32 offset = 0;
	157	switch(aa)
148	158	{
149		offset = m_iop->read_byte(m_r[TP].w);
150		set_reg(TP, m_r[TP].w + 1);
	159	case 0:
	160	offset = m_r[mm].w;
	161	break;
	162	case 1:
	163	offset = m_r[mm].w + m_iop->read_byte(m_r[TP].t, m_r[TP].w);
	164	set_reg(TP, m_r[TP].w + 1);
	165	break;
	166	case 2:
	167	offset = m_r[mm].w + m_r[IX].w;
	168	break;
	169	case 3:
	170	offset = m_r[mm].w + m_r[IX].w;
	171	set_reg(IX, m_r[IX].w + (w ? 2 : 1));
	172	break;
151	173	}
152
153		return offset;
	174	return offset & 0xfffff;
154	175	}
155	176
156		UINT8 i8089_channel::imm8()
	177	INT8 i8089_channel::imm8()
157	178	{
158		UINT8 imm8 = m_iop->read_byte(m_r[TP].w);
	179	INT8 imm8 = (INT8)m_iop->read_byte(m_r[TP].t, m_r[TP].w);
159	180	set_reg(TP, m_r[TP].w + 1);
160	181	return imm8;
161	182	}
162	183
163		UINT16 i8089_channel::imm16()
	184	INT16 i8089_channel::imm16()
164	185	{
165		UINT16 imm16 = m_iop->read_word(m_r[TP].w);
	186	INT16 imm16 = (INT16)m_iop->read_word(m_r[TP].t, m_r[TP].w);
166	187	set_reg(TP, m_r[TP].w + 2);
167	188	return imm16;
168	189	}
r26688	r26689
201	222	}
202	223	}
203	224
204		// todo: port transfers
205		if (CC_FUNC != 0x03)
206		fatalerror("%s('%s'): port transfer\n", shortname(), tag());
207
208	225	switch (m_dma_state)
209	226	{
210	227	case DMA_IDLE:
r26688	r26689
229	246	// source is 16-bit?
230	247	if (BIT(m_r[PSW].w, 1))
231	248	{
232		m_dma_value = m_iop->read_word(m_r[GA + CC_SOURCE].w);
233		m_r[GA + CC_SOURCE].w += 2;
	249	m_dma_value = m_iop->read_word(m_r[GA + CC_SOURCE].t, m_r[GA + CC_SOURCE].w);
	250	if(CC_FUNC & 1)
	251	m_r[GA + CC_SOURCE].w += 2;
234	252	m_r[BC].w -= 2;
235	253	}
236	254	// destination is 16-bit, byte count is even
237	255	else if (BIT(m_r[PSW].w, 0) && !(m_r[BC].w & 1))
238	256	{
239		m_dma_value = m_iop->read_byte(m_r[GA + CC_SOURCE].w);
240		m_r[GA + CC_SOURCE].w++;
	257	m_dma_value = m_iop->read_byte(m_r[GA + CC_SOURCE].t, m_r[GA + CC_SOURCE].w);
	258	if(CC_FUNC & 1)
	259	m_r[GA + CC_SOURCE].w++;
241	260	m_r[BC].w--;
242	261	}
243	262	// destination is 16-bit, byte count is odd
244	263	else if (BIT(m_r[PSW].w, 0) && (m_r[BC].w & 1))
245	264	{
246		m_dma_value |= m_iop->read_byte(m_r[GA + CC_SOURCE].w) << 8;
247		m_r[GA + CC_SOURCE].w++;
	265	m_dma_value |= m_iop->read_byte(m_r[GA + CC_SOURCE].t, m_r[GA + CC_SOURCE].w) << 8;
	266	if(CC_FUNC & 1)
	267	m_r[GA + CC_SOURCE].w++;
248	268	m_r[BC].w--;
249	269	}
250	270	// 8-bit transfer
251	271	else
252	272	{
253		m_dma_value = m_iop->read_byte(m_r[GA + CC_SOURCE].w);
254		m_r[GA + CC_SOURCE].w++;
	273	m_dma_value = m_iop->read_byte(m_r[GA + CC_SOURCE].t, m_r[GA + CC_SOURCE].w);
	274	if(CC_FUNC & 1)
	275	m_r[GA + CC_SOURCE].w++;
255	276	m_r[BC].w--;
256	277	}
257	278
r26688	r26689
284	305	// destination is 16-bit?
285	306	if (BIT(m_r[PSW].w, 0))
286	307	{
287		m_iop->write_word(m_r[GB - CC_SOURCE].w, m_dma_value);
288		m_r[GB - CC_SOURCE].w += 2;
	308	m_iop->write_word(m_r[GB - CC_SOURCE].t, m_r[GB - CC_SOURCE].w, m_dma_value);
	309	if(CC_FUNC & 2)
	310	m_r[GB - CC_SOURCE].w += 2;
289	311
290	312	if (VERBOSE_DMA)
291	313	logerror("[ %04x ]\n", m_dma_value);
r26688	r26689
293	315	// destination is 8-bit
294	316	else
295	317	{
296		m_iop->write_byte(m_r[GB - CC_SOURCE].w, m_dma_value & 0xff);
297		m_r[GB - CC_SOURCE].w++;
	318	m_iop->write_byte(m_r[GB - CC_SOURCE].t, m_r[GB - CC_SOURCE].w, m_dma_value & 0xff);
	319	if(CC_FUNC & 2)
	320	m_r[GB - CC_SOURCE].w++;
298	321
299	322	if (VERBOSE_DMA)
300	323	logerror("[ %02x ]\n", m_dma_value & 0xff);
r26688	r26689
323	346	else if (CC_TBC && m_r[BC].w == 0)
324	347	terminate_dma((CC_TBC - 1) * 4);
325	348
326		// terminate on external signal
327		else if (CC_TX)
328		fatalerror("%s('%s'): terminate on external signal not supported\n", shortname(), tag());
329
330	349	// terminate on single transfer
331	350	else if (CC_TS)
332	351	fatalerror("%s('%s'): terminate on single transfer not supported\n", shortname(), tag());
r26688	r26689
350	369	if (VERBOSE_DMA)
351	370	logerror("%s('%s'): entering state: DMA_STORE_BYTE_HIGH[ %02x ]\n", shortname(), tag(), (m_dma_value >> 8) & 0xff);
352	371
353		m_iop->write_byte(m_r[GB - CC_SOURCE].w, (m_dma_value >> 8) & 0xff);
	372	m_iop->write_byte(m_r[GA - CC_SOURCE].t, m_r[GB - CC_SOURCE].w, (m_dma_value >> 8) & 0xff);
354	373	m_r[GB - CC_SOURCE].w++;
355	374	m_dma_state = DMA_TERMINATE;
356	375
r26688	r26689
371	390	m_r[PSW].w |= 1 << 6;
372	391
373	392	// fetch first two instruction bytes
374		UINT16 op = m_iop->read_word(m_r[TP].w);
	393	UINT16 op = m_iop->read_word(m_r[TP].t, m_r[TP].w);
375	394	set_reg(TP, m_r[TP].w + 2);
376	395
377	396	// extract parameters
r26688	r26689
388	407	// fix-up so we can use our register array
389	408	if (mm == BC) mm = PP;
390	409
391		UINT8 o;
	410	UINT32 o;
392	411	UINT16 off, seg;
393	412
394	413	switch (opc)
r26688	r26689
405	424	break;
406	425
407	426	case 0x02: // lpdi
408		off = imm16();
409		seg = imm16();
	427	off = (UINT16)imm16();
	428	seg = (UINT16)imm16();
410	429	lpdi(brp, seg, off);
411	430	break;
412	431
r26688	r26689
415	434	else   addbi_ri(brp, imm8());
416	435	break;
417	436
	437	case 0x09: // or(b)i r, i
	438	if (w) ori_ri(brp, imm16());
	439	else   orbi_ri(brp, imm8());
	440	break;
	441
418	442	case 0x0a: // and(b)i r, i
419	443	if (w) andi_ri(brp, imm16());
420	444	else   andbi_ri(brp, imm8());
421	445	break;
422	446
	447	case 0x0b: // not r
	448	not_r(brp);
	449	break;
	450
423	451	case 0x0c: // mov(b)i r, i
424	452	if (w) movi_ri(brp, imm16());
425	453	else   movbi_ri(brp, imm8());
426	454	break;
427	455
	456	case 0x0e: // inc r
	457	inc_r(brp);
	458	break;
	459
428	460	case 0x0f: // dec r
429	461	dec_r(brp);
430	462	break;
431	463
	464	case 0x10: // jnz r
	465	jnz_r(brp, displacement(wb));
	466	break;
	467
	468	case 0x11: // jz r
	469	jz_r(brp, displacement(wb));
	470	break;
	471
432	472	case 0x12: // hlt
433	473	if (BIT(brp, 0)) hlt();
434	474	else             invalid(opc);
435	475	break;
436	476
	477	case 0x13: // mov(b)i m, i
	478	o = offset(aa, mm, w);
	479	if (w) movi_mi(mm, imm16(), o);
	480	else   movbi_mi(mm, imm8(), o);
	481	break;
	482
	483	case 0x20: // mov(b) r, m
	484	if (w) mov_rm(brp, mm, offset(aa, mm, w));
	485	else   movb_rm(brp, mm, offset(aa, mm, w));
	486	break;
	487
	488	case 0x21: // mov(b) m, r
	489	if (w) mov_mr(mm, brp, offset(aa, mm, w));
	490	else   movb_mr(mm, brp, offset(aa, mm, w));
	491	break;
	492
437	493	case 0x22: // lpd
438		o = offset(aa);
	494	o = offset(aa, mm, w);
439	495	lpd(brp, mm, o);
440	496	break;
441	497
442		case 0x28: // add(b) r, m
443		if (w) add_rm(brp, mm, offset(aa));
444		else   addb_rm(brp, mm, offset(aa));
	498	case 0x23: // movp p, m
	499	movp_pm(brp, mm, offset(aa, mm, w));
445	500	break;
446	501
447		case 0x2a: // and(b) r, m
448		if (w) and_rm(brp, mm, offset(aa));
449		else   andb_rm(brp, mm, offset(aa));
	502	case 0x24: // mov(b) m, m
	503	{
	504	o = offset(aa, mm, w);
	505	UINT16 op2 = m_iop->read_word(m_r[TP].t, m_r[TP].w);
	506	set_reg(TP, m_r[TP].w + 2);
	507	int mm2 = (op2 >> 8) & 0x03;
	508
	509	if (w) mov_mm(mm, mm2, o, offset((op2 >> 1) & 0x03, mm2, w));
	510	else   movb_mm(mm, mm2, o, offset((op2 >> 1) & 0x03, mm2, w));
450	511	break;
	512	}
451	513
	514	case 0x25: // tsl m, i, d
	515	{
	516	o = offset(aa, mm, w);
	517	INT8 i = imm8();
	518	tsl(mm, i, imm8(), o);
	519	break;
	520	}
	521
	522	case 0x26: // movp m, p
	523	movp_mp(mm, brp, offset(aa, mm, w));
	524	break;
	525
452	526	case 0x27: // call
453		o = offset(aa);
	527	o = offset(aa, mm, w);
454	528	call(mm, displacement(wb), o);
455	529	break;
456	530
	531	case 0x28: // add(b) r, m
	532	if (w) add_rm(brp, mm, offset(aa, mm, w));
	533	else   addb_rm(brp, mm, offset(aa, mm, w));
	534	break;
	535
	536	case 0x29: // or(b) r, m
	537	if (w) or_rm(brp, mm, offset(aa, mm, w));
	538	else   orb_rm(brp, mm, offset(aa, mm, w));
	539	break;
	540
	541	case 0x2a: // and(b) r, m
	542	if (w) and_rm(brp, mm, offset(aa, mm, w));
	543	else   andb_rm(brp, mm, offset(aa, mm, w));
	544	break;
	545
	546	case 0x2b: // not(b) r, m
	547	if (w) not_rm(brp, mm, offset(aa, mm, w));
	548	else   notb_rm(brp, mm, offset(aa, mm, w));
	549	break;
	550
	551	case 0x2c: // jmce m, d
	552	o = offset(aa, mm, w);
	553	jmce(mm, displacement(wb), o);
	554	break;
	555
	556	case 0x2d: // jmcne m, d
	557	o = offset(aa, mm, w);
	558	jmcne(mm, displacement(wb), o);
	559	break;
	560
	561	case 0x2e: // jnbt m, b, d
	562	o = offset(aa, mm, w);
	563	jnbt(mm, brp, displacement(wb), o);
	564	break;
	565
	566	case 0x2f: // jbt m, b, d
	567	o = offset(aa, mm, w);
	568	jbt(mm, brp, displacement(wb), o);
	569	break;
	570
457	571	case 0x30: // add(b)i m, i
458		o = offset(aa);
	572	o = offset(aa, mm, w);
459	573	if (w) addi_mi(mm, imm16(), o);
460	574	else   addbi_mi(mm, imm8(), o);
461	575	break;
462	576
	577	case 0x31: // or(b)i m, i
	578	o = offset(aa, mm, w);
	579	if (w) ori_mi(mm, imm16(), o);
	580	else   orbi_mi(mm, imm8(), o);
	581	break;
	582
463	583	case 0x32: // and(b)i m, i
464		o = offset(aa);
	584	o = offset(aa, mm, w);
465	585	if (w) andi_mi(mm, imm16(), o);
466	586	else   andbi_mi(mm, imm8(), o);
467	587	break;
468	588
469	589	case 0x34: // add(b) m, r
470		if (w) add_mr(mm, brp, offset(aa));
471		else   addb_mr(mm, brp, offset(aa));
	590	if (w) add_mr(mm, brp, offset(aa, mm, w));
	591	else   addb_mr(mm, brp, offset(aa, mm, w));
472	592	break;
473	593
	594	case 0x35: // or(b) m, r
	595	if (w) or_mr(mm, brp, offset(aa, mm, w));
	596	else   orb_mr(mm, brp, offset(aa, mm, w));
	597	break;
	598
474	599	case 0x36: // and(b) m, r
475		if (w) and_mr(mm, brp, offset(aa));
476		else   andb_mr(mm, brp, offset(aa));
	600	if (w) and_mr(mm, brp, offset(aa, mm, w));
	601	else   andb_mr(mm, brp, offset(aa, mm, w));
477	602	break;
478	603
	604	case 0x37: // not(b) m
	605	if (w) not_m(mm, offset(aa, mm, w));
	606	else   notb_m(mm, offset(aa, mm, w));
	607	break;
	608
	609	case 0x38: // jnz m
	610	o = offset(aa, mm, w);
	611	if(w) jnz_m(mm, displacement(wb), o);
	612	else jnzb(mm, displacement(wb), o);
	613	break;
	614
	615	case 0x39: // jz m
	616	o = offset(aa, mm, w);
	617	if(w) jz_m(mm, displacement(wb), o);
	618	else jzb(mm, displacement(wb), o);
	619	break;
	620
	621	case 0x3a: // inc(b) m
	622	if (w) inc_m(mm, offset(aa, mm, w));
	623	else   incb(mm, offset(aa, mm, w));
	624	break;
	625
479	626	case 0x3b: // dec(b) m
480		if (w) dec_m(mm, offset(aa));
481		else   decb(mm, offset(aa));
	627	if (w) dec_m(mm, offset(aa, mm, w));
	628	else   decb(mm, offset(aa, mm, w));
482	629	break;
483	630
	631	case 0x3d: // setb
	632	setb(mm, brp, offset(aa, mm, w));
	633	break;
	634
484	635	case 0x3e: // clr
485		clr(mm, brp, offset(aa));
	636	clr(mm, brp, offset(aa, mm, w));
486	637	break;
487	638
488	639	default:
r26688	r26689
526	677	void i8089_channel::attention()
527	678	{
528	679	// examine control byte
529		UINT8 ccw = m_iop->read_byte(m_r[CP].w);
	680	UINT8 ccw = m_iop->read_byte(m_r[CP].t, m_r[CP].w);
530	681
531	682	switch (ccw & 0x07)
532	683	{
r26688	r26689
545	696
546	697	examine_ccw(ccw);
547	698
548		lpd(PP, CP, 2);
549		movp_pm(TP, PP);
	699	lpd(PP, CP, m_r[CP].w + 2);
	700	movp_pm(TP, PP, m_r[PP].w);
550	701	movbi_mi(CP, 0xff, 1);
	702	m_r[TP].t = 1;
551	703
552	704	m_r[PSW].w |= 1 << 2;
553	705
	706	if (VERBOSE)
	707	{
	708	logerror("%s('%s'): ---- starting channel ----\n", shortname(), tag());
	709	logerror("%s('%s'): parameter block address: %06x\n", shortname(), tag(), m_r[PP].w);
	710	logerror("%s('%s'): task pointer: %04x\n", shortname(), tag(), m_r[TP].w);
	711	}
	712
554	713	break;
555	714
556	715	// reserved
r26688	r26689
567	726
568	727	examine_ccw(ccw);
569	728
570		lpd(PP, CP, 2);
571		lpd(TP, PP);
	729	lpd(PP, CP, m_r[CP].w + 2);
	730	lpd(TP, PP, m_r[PP].w);
572	731	movbi_mi(CP, 0xff, 1);
573	732
574	733	m_r[PSW].w |= 1 << 2;
r26688	r26689
594	753	logerror("%s('%s'): command received: continue channel processing\n", shortname(), tag());
595	754
596	755	// restore task pointer and parameter block
597		movp_pm(TP, PP);
598		movb_rm(PSW, PP, 3);
599		movbi_mi(CP, 0xff, 1);
	756	movp_pm(TP, PP, m_r[PP].w);
	757	movb_rm(PSW, PP, m_r[PP].w + 3);
	758	movbi_mi(CP, 0xff, m_r[CP].w + 1);
600	759
601	760	m_r[PSW].w |= 1 << 2;
602	761
r26688	r26689
614	773	logerror("%s('%s'): command received: halt channel and save tp\n", shortname(), tag());
615	774
616	775	// save task pointer and psw to parameter block
617		movp_mp(PP, TP);
618		movb_mr(PP, PSW, 3);
	776	movp_mp(PP, TP, m_r[TP].w);
	777	movb_mr(PP, PSW, m_r[PP].w + 3);
619	778	hlt();
620	779
621	780	break;
r26688	r26689
635	794	{
636	795	if (VERBOSE)
637	796	logerror("%s('%s'): ext_w: %d\n", shortname(), tag(), state);
	797	if(transferring())
	798	terminate_dma((CC_TX - 1) * 4);
638	799	}
639	800
640	801	WRITE_LINE_MEMBER( i8089_channel::drq_w )

trunk/src/emu/cpu/i8089/i8089_channel.h

r26688	r26689
45	45	template<class _sintr> void set_sintr_callback(_sintr sintr) { m_write_sintr.set_callback(sintr); }
46	46
47	47	// set register
48		void set_reg(int reg, int value, int tag = -1);
	48	void set_reg(int reg, UINT32 value, int tag = -1);
49	49
50	50	int execute_run();
51	51	void attention();
r26688	r26689
82	82
83	83	struct
84	84	{
85		int w; // 20-bit address
86		int t; // tag-bit
	85	UINT32 w; // 20-bit address
	86	bool t; // tag-bit
87	87	}
88	88	m_r[11];
89	89
r26688	r26689
95	95	private:
96	96
97	97	// opcodes
98		void add_rm(int r, int m, int o = 0);
99		void add_mr(int m, int r, int o = 0);
100		void addb_rm(int r, int m, int o = 0);
101		void addb_mr(int m, int r, int o = 0);
102		void addbi_ri(int r, int i);
103		void addbi_mi(int m, int i, int o = 0);
104		void addi_ri(int r, int i);
105		void addi_mi(int m, int i, int o = 0);
106		void and_rm(int r, int m, int o = 0);
107		void and_mr(int m, int r, int o = 0);
108		void andb_rm(int r, int m, int o = 0);
109		void andb_mr(int m, int r, int o = 0);
110		void andbi_ri(int r, int i);
111		void andbi_mi(int m, int i, int o = 0);
112		void andi_ri(int r, int i);
113		void andi_mi(int m, int i, int o = 0);
114		void call(int m, int d, int o = 0);
115		void clr(int m, int b, int o = 0);
	98	void add_rm(int r, int m, int o);
	99	void add_mr(int m, int r, int o);
	100	void addb_rm(int r, int m, int o);
	101	void addb_mr(int m, int r, int o);
	102	void addbi_ri(int r, INT8 i);
	103	void addbi_mi(int m, INT8 i, int o);
	104	void addi_ri(int r, INT16 i);
	105	void addi_mi(int m, INT16 i, int o);
	106	void and_rm(int r, int m, int o);
	107	void and_mr(int m, int r, int o);
	108	void andb_rm(int r, int m, int o);
	109	void andb_mr(int m, int r, int o);
	110	void andbi_ri(int r, INT8 i);
	111	void andbi_mi(int m, INT8 i, int o);
	112	void andi_ri(int r, INT16 i);
	113	void andi_mi(int m, INT16 i, int o);
	114	void call(int m, INT16 d, int o);
	115	void clr(int m, int b, int o);
116	116	void dec_r(int r);
117		void dec_m(int m, int o = 0);
118		void decb(int m, int o = 0);
	117	void dec_m(int m, int o);
	118	void decb(int m, int o);
119	119	void hlt();
120	120	void inc_r(int r);
121		void inc_m(int m, int o = 0);
122		void incb(int m, int o = 0);
123		void jbt(int m, int b, int d, int o = 0);
124		void jmce(int m, int d, int o = 0);
125		void jmcne(int m, int d, int o = 0);
126		void jmp(int d);
127		void jnbt(int m, int b, int d, int o = 0);
128		void jnz_r(int r, int d);
129		void jnz_m(int m, int d, int o = 0);
130		void jnzb(int m, int d, int o = 0);
131		void jz_r(int r, int d);
132		void jz_m(int m, int d, int o = 0);
133		void jzb(int m, int d, int o = 0);
134		void lcall(int m, int d, int o = 0);
135		void ljbt(int m, int b, int d, int o = 0);
136		void ljmce(int m, int d, int o = 0);
137		void ljmcne(int m, int d, int o = 0);
138		void ljmp(int d);
139		void ljnbt(int m, int b, int d, int o = 0);
140		void ljnz_r(int r, int d);
141		void ljnz_m(int m, int d, int o = 0);
142		void ljnzb(int m, int d, int o = 0);
143		void ljz_r(int r, int d);
144		void ljz_m(int m, int d, int o = 0);
145		void ljzb(int m, int d, int o = 0);
146		void lpd(int p, int m, int o = 0);
147		void lpdi(int p, int i, int o = 0);
148		void mov_mr(int m, int r, int o = 0);
149		void mov_rm(int r, int m, int o = 0);
150		void mov_mm(int m1, int m2, int o1 = 0, int o2 = 0);
151		void movb_mr(int m, int r, int o = 0);
152		void movb_rm(int r, int m, int o = 0);
153		void movb_mm(int m1, int m2, int o1 = 0, int o2 = 0);
154		void movbi_ri(int r, int i);
155		void movbi_mi(int m, int i, int o = 0);
156		void movi_ri(int r, int i);
157		void movi_mi(int m, int i, int o = 0);
158		void movp_mp(int m, int p, int o = 0);
159		void movp_pm(int p, int m, int o = 0);
	121	void inc_m(int m, int o);
	122	void incb(int m, int o);
	123	void jbt(int m, int b, INT16 d, int o);
	124	void jmce(int m, INT16 d, int o);
	125	void jmcne(int m, INT16 d, int o);
	126	void jnbt(int m, int b, INT16 d, int o);
	127	void jnz_r(int r, INT16 d);
	128	void jnz_m(int m, INT16 d, int o);
	129	void jnzb(int m, INT16 d, int o);
	130	void jz_r(int r, INT16 d);
	131	void jz_m(int m, INT16 d, int o);
	132	void jzb(int m, INT16 d, int o);
	133	void lpd(int p, int m, int o);
	134	void lpdi(int p, int s, int o);
	135	void mov_mr(int m, int r, int o);
	136	void mov_rm(int r, int m, int o);
	137	void mov_mm(int m1, int m2, int o1, int o2);
	138	void movb_mr(int m, int r, int o);
	139	void movb_rm(int r, int m, int o);
	140	void movb_mm(int m1, int m2, int o1, int o2);
	141	void movbi_ri(int r, INT8 i);
	142	void movbi_mi(int m, INT8 i, int o);
	143	void movi_ri(int r, INT16 i);
	144	void movi_mi(int m, INT16 i, int o);
	145	void movp_mp(int m, int p, int o);
	146	void movp_pm(int p, int m, int o);
160	147	void nop();
161	148	void not_r(int r);
162		void not_m(int m, int o = 0);
163		void not_rm(int r, int m, int o = 0);
164		void notb_m(int m, int o = 0);
165		void notb_rm(int r, int m, int o = 0);
166		void or_rm(int r, int m, int o = 0);
167		void or_mr(int m, int r, int o = 0);
168		void orb_rm(int r, int m, int o = 0);
169		void orb_mr(int m, int r, int o = 0);
170		void orbi_ri(int r, int i);
171		void orbi_mi(int m, int i, int o = 0);
172		void ori_ri(int r, int i);
173		void ori_mi(int m, int i, int o = 0);
174		void setb(int m, int b, int o = 0);
	149	void not_m(int m, int o);
	150	void not_rm(int r, int m, int o);
	151	void notb_m(int m, int o);
	152	void notb_rm(int r, int m, int o);
	153	void or_rm(int r, int m, int o);
	154	void or_mr(int m, int r, int o);
	155	void orb_rm(int r, int m, int o);
	156	void orb_mr(int m, int r, int o);
	157	void orbi_ri(int r, INT8 i);
	158	void orbi_mi(int m, INT8 i, int o);
	159	void ori_ri(int r, INT16 i);
	160	void ori_mi(int m, INT16 i, int o);
	161	void setb(int m, int b, int o);
175	162	void sintr();
176		void tsl(int m, int i, int d, int o = 0);
	163	void tsl(int m, INT8 i, INT8 d, int o);
177	164	void wid(int s, int d);
178	165	void xfer();
179	166	void invalid(int opc);
180	167
181	168	// instruction fetch
182		UINT16 displacement(int wb);
183		UINT8 offset(int aa);
184		UINT8 imm8();
185		UINT16 imm16();
	169	INT16 displacement(int wb);
	170	UINT32 offset(int aa, int mm, int w);
	171	INT8 imm8();
	172	INT16 imm16();
186	173
187	174	void examine_ccw(UINT8 ccw);
188	175

trunk/src/emu/cpu/i8089/i8089.c

r26688	r26689
241	241	m_sysbus = m_mem->read_byte(0xffff6);
242	242
243	243	// get system configuration block address
244		UINT16 scb_offset = read_word(0xffff8);
245		UINT16 scb_segment = read_word(0xffffa);
	244	UINT16 scb_offset = read_word(0, 0xffff8);
	245	UINT16 scb_segment = read_word(0, 0xffffa);
246	246	m_scb = ((scb_segment << 4) + scb_offset) & 0x0fffff;
247	247
248	248	// get system operation command
249		m_soc = read_byte(m_scb);
	249	m_soc = read_byte(0, m_scb);
250	250	m_master = !m_sel;
251	251
252	252	// get control block address
253		UINT16 cb_offset = read_word(m_scb + 2);
254		UINT16 cb_segment = read_word(m_scb + 4);
	253	UINT16 cb_offset = read_word(0, m_scb + 2);
	254	UINT16 cb_segment = read_word(0, m_scb + 4);
255	255	offs_t cb_address = ((cb_segment << 4) + cb_offset) & 0x0fffff;
256	256
257	257	// initialize channels
r26688	r26689
259	259	m_ch2->set_reg(i8089_channel::CP, cb_address + 8);
260	260
261	261	// clear busy
262		UINT16 ccw = read_word(cb_address);
263		write_word(cb_address, ccw & 0x00ff);
	262	UINT16 ccw = read_word(0, cb_address);
	263	write_word(0, cb_address, ccw & 0x00ff);
264	264
265	265	// done
266	266	m_initialized = true;
r26688	r26689
278	278	}
279	279	}
280	280
281		UINT8 i8089_device::read_byte(offs_t address)
	281	UINT8 i8089_device::read_byte(bool space, offs_t address)
282	282	{
283		assert(m_initialized);
284		return m_mem->read_byte(address);
	283	return (space ? m_io : m_mem)->read_byte(address);
285	284	}
286	285
287		UINT16 i8089_device::read_word(offs_t address)
	286	UINT16 i8089_device::read_word(bool space, offs_t address)
288	287	{
289		assert(m_initialized);
290
291	288	UINT16 data = 0xffff;
	289	address_space *aspace = (space ? m_io : m_mem);
292	290
293	291	if (sysbus_width() && !(address & 1))
294	292	{
295		data = m_mem->read_word(address);
	293	data = aspace->read_word(address);
296	294	}
297	295	else
298	296	{
299		data  = m_mem->read_byte(address);
300		data |= m_mem->read_byte(address + 1) << 8;
	297	data  = aspace->read_byte(address);
	298	data |= aspace->read_byte(address + 1) << 8;
301	299	}
302	300
303	301	return data;
304	302	}
305	303
306		void i8089_device::write_byte(offs_t address, UINT8 data)
	304	void i8089_device::write_byte(bool space, offs_t address, UINT8 data)
307	305	{
308		assert(m_initialized);
309		m_mem->write_byte(address, data);
	306	(space ? m_io : m_mem)->write_byte(address, data);
310	307	}
311	308
312		void i8089_device::write_word(offs_t address, UINT16 data)
	309	void i8089_device::write_word(bool space, offs_t address, UINT16 data)
313	310	{
314		assert(m_initialized);
	311	address_space *aspace = (space ? m_io : m_mem);
315	312
316	313	if (sysbus_width() && !(address & 1))
317	314	{
318		m_mem->write_word(address, data);
	315	aspace->write_word(address, data);
319	316	}
320	317	else
321	318	{
322		m_mem->write_byte(address, data & 0xff);
323		m_mem->write_byte(address + 1, (data >> 8) & 0xff);
	319	aspace->write_byte(address, data & 0xff);
	320	aspace->write_byte(address + 1, (data >> 8) & 0xff);
324	321	}
325	322	}
326	323

trunk/src/emu/cpu/i8089/i8089_ops.c

r26688	r26689
14	14
15	15	#define UNIMPLEMENTED logerror("%s('%s'): unimplemented opcode: %s\n", shortname(), tag(), __FUNCTION__);
16	16
17		void i8089_channel::add_rm(int r, int m, int o) { UNIMPLEMENTED }
18		void i8089_channel::add_mr(int m, int r, int o) { UNIMPLEMENTED }
19		void i8089_channel::addb_rm(int r, int m, int o) { UNIMPLEMENTED }
20		void i8089_channel::addb_mr(int m, int r, int o) { UNIMPLEMENTED }
21		void i8089_channel::addbi_ri(int r, int i) { UNIMPLEMENTED }
22		void i8089_channel::addbi_mi(int m, int i, int o) { UNIMPLEMENTED }
23		void i8089_channel::addi_ri(int r, int i) { UNIMPLEMENTED }
24		void i8089_channel::addi_mi(int m, int i, int o) { UNIMPLEMENTED }
25		void i8089_channel::and_rm(int r, int m, int o) { UNIMPLEMENTED }
26		void i8089_channel::and_mr(int m, int r, int o) { UNIMPLEMENTED }
27		void i8089_channel::andb_rm(int r, int m, int o) { UNIMPLEMENTED }
28		void i8089_channel::andb_mr(int m, int r, int o) { UNIMPLEMENTED }
29		void i8089_channel::andbi_ri(int r, int i) { UNIMPLEMENTED }
30		void i8089_channel::andbi_mi(int m, int i, int o) { UNIMPLEMENTED }
31		void i8089_channel::andi_ri(int r, int i) { UNIMPLEMENTED }
32		void i8089_channel::andi_mi(int m, int i, int o) { UNIMPLEMENTED }
33		void i8089_channel::call(int m, int d, int o) { UNIMPLEMENTED }
34		void i8089_channel::clr(int m, int b, int o) { UNIMPLEMENTED }
35		void i8089_channel::dec_r(int r) { UNIMPLEMENTED }
36		void i8089_channel::dec_m(int m, int o) { UNIMPLEMENTED }
37		void i8089_channel::decb(int m, int o) { UNIMPLEMENTED }
	17	#define LWR(m, o) ((INT16)m_iop->read_word(m_r[m].t, o))
	18	#define LBR(m, o) ((INT8)m_iop->read_byte(m_r[m].t, o))
	19	#define SWR(m, o, d) (m_iop->write_word(m_r[m].t, o, d))
	20	#define SBR(m, o, d) (m_iop->write_byte(m_r[m].t, o, d))
38	21
	22	void i8089_channel::add_rm(int r, int m, int o)
	23	{
	24	set_reg(r, m_r[r].w + LWR(m, o));
	25	}
	26
	27	void i8089_channel::add_mr(int m, int r, int o)
	28	{
	29	SWR(m, o, LWR(m, o) + m_r[r].w);
	30	}
	31
	32	void i8089_channel::addb_rm(int r, int m, int o)
	33	{
	34	set_reg(r, m_r[r].w + LBR(m, o));
	35	}
	36
	37	void i8089_channel::addb_mr(int m, int r, int o)
	38	{
	39	SBR(m, o, LBR(m, o) + m_r[r].w);
	40	}
	41
	42	void i8089_channel::addbi_ri(int r, INT8 i)
	43	{
	44	set_reg(r, m_r[r].w + i);
	45	}
	46
	47	void i8089_channel::addbi_mi(int m, INT8 i, int o)
	48	{
	49	SBR(m, o, LBR(m, o) + i);
	50	}
	51
	52	void i8089_channel::addi_ri(int r, INT16 i)
	53	{
	54	set_reg(r, m_r[r].w + i);
	55	}
	56
	57	void i8089_channel::addi_mi(int m, INT16 i, int o)
	58	{
	59	SWR(m, o, LWR(m, o) + i);
	60	}
	61
	62	void i8089_channel::and_rm(int r, int m, int o)
	63	{
	64	set_reg(r, m_r[r].w & LWR(m, o));
	65	}
	66
	67	void i8089_channel::and_mr(int m, int r, int o)
	68	{
	69	SWR(m, o, LWR(m, o) & m_r[r].w);
	70	}
	71
	72	void i8089_channel::andb_rm(int r, int m, int o)
	73	{
	74	set_reg(r, m_r[r].w & (INT16)LBR(m, o));
	75	}
	76
	77	void i8089_channel::andb_mr(int m, int r, int o)
	78	{
	79	SBR(m, o, LBR(m, o) & m_r[r].w);
	80	}
	81
	82	void i8089_channel::andbi_ri(int r, INT8 i)
	83	{
	84	set_reg(r, m_r[r].w & (INT16)i);
	85	}
	86
	87	void i8089_channel::andbi_mi(int m, INT8 i, int o)
	88	{
	89	SBR(m, o, LBR(m, o) & i);
	90	}
	91
	92	void i8089_channel::andi_ri(int r, INT16 i)
	93	{
	94	set_reg(r, m_r[r].w & i);
	95	}
	96
	97	void i8089_channel::andi_mi(int m, INT16 i, int o)
	98	{
	99	SWR(m, o, LWR(m, o) & i);
	100	}
	101
	102	void i8089_channel::call(int m, INT16 d, int o)
	103	{
	104	movp_mp(m, TP, o);
	105	set_reg(TP, m_r[TP].w + d);
	106	}
	107
	108	void i8089_channel::clr(int m, int b, int o)
	109	{
	110	SBR(m, o, LBR(m, o) & ~(1<<b));
	111	}
	112
	113	void i8089_channel::dec_r(int r)
	114	{
	115	set_reg(r, m_r[r].w - 1);
	116	}
	117
	118	void i8089_channel::dec_m(int m, int o)
	119	{
	120	SWR(m, o, LWR(m, o) - 1);
	121	}
	122
	123	void i8089_channel::decb(int m, int o)
	124	{
	125	SBR(m, o, LBR(m, o) - 1);
	126	}
	127
39	128	// halt
40	129	void i8089_channel::hlt()
41	130	{
42		movbi_mi(CP, 0x00, 1);
	131	movbi_mi(CP, 0x00, m_r[CP].w + 1);
43	132	m_r[PSW].w &= ~(1 << 2);
44	133	}
45	134
46		void i8089_channel::inc_r(int r) { UNIMPLEMENTED }
47		void i8089_channel::inc_m(int m, int o) { UNIMPLEMENTED }
48		void i8089_channel::incb(int m, int o) { UNIMPLEMENTED }
49		void i8089_channel::jbt(int m, int b, int d, int o) { UNIMPLEMENTED }
50		void i8089_channel::jmce(int m, int d, int o) { UNIMPLEMENTED }
51		void i8089_channel::jmcne(int m, int d, int o) { UNIMPLEMENTED }
52		void i8089_channel::jmp(int d) { UNIMPLEMENTED }
53		void i8089_channel::jnbt(int m, int b, int d, int o) { UNIMPLEMENTED }
54		void i8089_channel::jnz_r(int r, int d) { UNIMPLEMENTED }
55		void i8089_channel::jnz_m(int m, int d, int o) { UNIMPLEMENTED }
56		void i8089_channel::jnzb(int m, int d, int o) { UNIMPLEMENTED }
57		void i8089_channel::jz_r(int r, int d) { UNIMPLEMENTED }
58		void i8089_channel::jz_m(int m, int d, int o) { UNIMPLEMENTED }
59		void i8089_channel::jzb(int m, int d, int o) { UNIMPLEMENTED }
60		void i8089_channel::lcall(int m, int d, int o) { UNIMPLEMENTED }
61		void i8089_channel::ljbt(int m, int b, int d, int o) { UNIMPLEMENTED }
62		void i8089_channel::ljmce(int m, int d, int o) { UNIMPLEMENTED }
63		void i8089_channel::ljmcne(int m, int d, int o) { UNIMPLEMENTED }
64		void i8089_channel::ljmp(int d) { UNIMPLEMENTED }
65		void i8089_channel::ljnbt(int m, int b, int d, int o) { UNIMPLEMENTED }
66		void i8089_channel::ljnz_r(int r, int d) { UNIMPLEMENTED }
67		void i8089_channel::ljnz_m(int m, int d, int o) { UNIMPLEMENTED }
68		void i8089_channel::ljnzb(int m, int d, int o) { UNIMPLEMENTED }
69		void i8089_channel::ljz_r(int r, int d) { UNIMPLEMENTED }
70		void i8089_channel::ljz_m(int m, int d, int o) { UNIMPLEMENTED }
71		void i8089_channel::ljzb(int m, int d, int o) { UNIMPLEMENTED }
	135	void i8089_channel::inc_r(int r)
	136	{
	137	set_reg(r, m_r[r].w + 1);
	138	}
72	139
	140	void i8089_channel::inc_m(int m, int o)
	141	{
	142	SWR(m, o, LWR(m, o) + 1);
	143	}
	144
	145	void i8089_channel::incb(int m, int o)
	146	{
	147	SBR(m, o, LBR(m, o) + 1);
	148	}
	149
	150	void i8089_channel::jbt(int m, int b, INT16 d, int o)
	151	{
	152	if(LBR(m, o) & (1<<b))
	153	set_reg(TP, m_r[TP].w + d);
	154	}
	155
	156	void i8089_channel::jmce(int m, INT16 d, int o)
	157	{
	158	if(!((LBR(m, o) ^ (m_r[MC].w & 0xff)) & (m_r[MC].w >> 8)))
	159	set_reg(TP, m_r[TP].w + d);
	160	}
	161
	162	void i8089_channel::jmcne(int m, INT16 d, int o)
	163	{
	164	if((LBR(m, o) ^ (m_r[MC].w & 0xff)) & (m_r[MC].w >> 8))
	165	set_reg(TP, m_r[TP].w + d);
	166	}
	167
	168	void i8089_channel::jnbt(int m, int b, INT16 d, int o)
	169	{
	170	if(!(LBR(m, o) & (1<<b)))
	171	set_reg(TP, m_r[TP].w + d);
	172	}
	173
	174	void i8089_channel::jnz_r(int r, INT16 d)
	175	{
	176	if(m_r[r].w)
	177	set_reg(TP, m_r[TP].w + d);
	178	}
	179
	180	void i8089_channel::jnz_m(int m, INT16 d, int o)
	181	{
	182	if(LWR(m, o))
	183	set_reg(TP, m_r[TP].w + d);
	184	}
	185
	186	void i8089_channel::jnzb(int m, INT16 d, int o)
	187	{
	188	if(LBR(m, o))
	189	set_reg(TP, m_r[TP].w + d);
	190	}
	191
	192	void i8089_channel::jz_r(int r, INT16 d)
	193	{
	194	if(!m_r[r].w)
	195	set_reg(TP, m_r[TP].w + d);
	196	}
	197
	198	void i8089_channel::jz_m(int m, INT16 d, int o)
	199	{
	200	if(!LWR(m, o))
	201	set_reg(TP, m_r[TP].w + d);
	202	}
	203
	204	void i8089_channel::jzb(int m, INT16 d, int o)
	205	{
	206	if(!LBR(m, o))
	207	set_reg(TP, m_r[TP].w + d);
	208	}
	209
	210
73	211	// load pointer from memory
74	212	void i8089_channel::lpd(int p, int m, int o)
75	213	{
76		UINT16 offset = m_iop->read_word(m_r[m].w + o);
77		UINT16 segment = m_iop->read_word(m_r[m].w + o + 2);
	214	UINT16 offset = m_iop->read_word(m_r[m].t, o);
	215	UINT16 segment = m_iop->read_word(m_r[m].t, o + 2);
78	216
79	217	set_reg(p, ((segment << 4) + offset) & 0xfffff, 0);
80	218	}
81	219
82	220	// load pointer from immediate data
83		void i8089_channel::lpdi(int p, int i, int o)
	221	void i8089_channel::lpdi(int p, int s, int o)
84	222	{
85		set_reg(p, (o << 4) + (i & 0xffff), 0);
	223	set_reg(p, (s << 4) + (o & 0xffff), 0);
86	224	}
87	225
88		void i8089_channel::mov_mr(int m, int r, int o) { UNIMPLEMENTED }
89		void i8089_channel::mov_rm(int r, int m, int o) { UNIMPLEMENTED }
90		void i8089_channel::mov_mm(int m1, int m2, int o1, int o2) { UNIMPLEMENTED }
	226	void i8089_channel::mov_mr(int m, int r, int o)
	227	{
	228	SWR(m, o, m_r[r].w);
	229	}
91	230
	231	void i8089_channel::mov_rm(int r, int m, int o)
	232	{
	233	set_reg(r, LWR(m, o));
	234	}
	235
	236	void i8089_channel::mov_mm(int m1, int m2, int o1, int o2)
	237	{
	238	SWR(m2, o2, LWR(m1, o1));
	239	}
	240
92	241	// move register to memory byte
93	242	void i8089_channel::movb_mr(int m, int r, int o)
94	243	{
95		m_iop->write_byte(m_r[m].w + o, m_r[r].w & 0xff);
	244	m_iop->write_byte(m_r[m].t, o, m_r[r].w & 0xff);
96	245	}
97	246
98	247	// move memory byte to register
99	248	void i8089_channel::movb_rm(int r, int m, int o)
100	249	{
101		UINT8 byte = m_iop->read_byte(m_r[m].w + o);
	250	UINT8 byte = m_iop->read_byte(m_r[m].t, o);
102	251	set_reg(r, (BIT(byte, 7) ? 0xfff00 : 0x00000) | byte, 1);
103	252	}
104	253
105	254	// move memory byte to memory byte
106	255	void i8089_channel::movb_mm(int m1, int m2, int o1, int o2)
107	256	{
108		UINT8 byte = m_iop->read_byte(m_r[m2].w + o2);
109		m_iop->write_byte(m_r[m1].w + o1, byte);
	257	UINT8 byte = m_iop->read_byte(m_r[m1].t, o1);
	258	m_iop->write_byte(m_r[m2].t, o2, byte);
110	259	}
111	260
112	261	// move immediate byte to register
113		void i8089_channel::movbi_ri(int r, int i)
	262	void i8089_channel::movbi_ri(int r, INT8 i)
114	263	{
115	264	set_reg(r, (BIT(i, 7) ? 0xfff00 : 0x00000) | (i & 0xff), 1);
116	265	}
117	266
118	267	// move immediate byte to memory byte
119		void i8089_channel::movbi_mi(int m, int i, int o)
	268	void i8089_channel::movbi_mi(int m, INT8 i, int o)
120	269	{
121		m_iop->write_byte(m_r[m].w + o, i & 0xff);
	270	m_iop->write_byte(m_r[m].t, o, i & 0xff);
122	271	}
123	272
124	273	// move immediate word to register
125		void i8089_channel::movi_ri(int r, int i)
	274	void i8089_channel::movi_ri(int r, INT16 i)
126	275	{
127	276	set_reg(r, (BIT(i, 15) ? 0xf0000 : 0x00000) | (i & 0xffff), 1);
128	277	}
129	278
130	279	// move immediate word to memory word
131		void i8089_channel::movi_mi(int m, int i, int o)
	280	void i8089_channel::movi_mi(int m, INT16 i, int o)
132	281	{
133		m_iop->write_word(m_r[m].w + o, (BIT(i, 15) ? 0xf0000 : 0x00000) | (i & 0xffff));
	282	m_iop->write_word(m_r[m].t, o, (BIT(i, 15) ? 0xf0000 : 0x00000) | (i & 0xffff));
134	283	}
135	284
136	285	// move pointer to memory (store)
137	286	void i8089_channel::movp_mp(int m, int p, int o)
138	287	{
139		m_iop->write_word(m_r[m].w + o, m_r[p].w & 0xffff);
140		m_iop->write_word(m_r[m].w + o + 2, (m_r[p].w >> 12 & 0xf0) | (m_r[p].t << 3 & 0x01));
	288	m_iop->write_word(m_r[m].t, o, m_r[p].w & 0xffff);
	289	m_iop->write_byte(m_r[m].t, o + 2, (m_r[p].w >> 12 & 0xf0) | (m_r[p].t << 3));
141	290	}
142	291
143	292	// move memory to pointer (restore)
144	293	void i8089_channel::movp_pm(int p, int m, int o)
145	294	{
146		UINT16 offset = m_iop->read_word(m_r[m].w + o);
147		UINT16 segment = m_iop->read_word(m_r[m].w + o + 2);
	295	UINT16 offset = m_iop->read_word(m_r[m].t, o);
	296	UINT16 segment = m_iop->read_byte(m_r[m].t, o + 2);
148	297
149	298	set_reg(p, ((segment << 4) + offset) & 0xfffff, segment >> 3 & 0x01);
150	299	}
r26688	r26689
154	303	{
155	304	}
156	305
157		void i8089_channel::not_r(int r) { UNIMPLEMENTED }
158		void i8089_channel::not_m(int m, int o) { UNIMPLEMENTED }
159		void i8089_channel::not_rm(int r, int m, int o) { UNIMPLEMENTED }
160		void i8089_channel::notb_m(int m, int o) { UNIMPLEMENTED }
161		void i8089_channel::notb_rm(int r, int m, int o) { UNIMPLEMENTED }
162		void i8089_channel::or_rm(int r, int m, int o) { UNIMPLEMENTED }
163		void i8089_channel::or_mr(int m, int r, int o) { UNIMPLEMENTED }
164		void i8089_channel::orb_rm(int r, int m, int o) { UNIMPLEMENTED }
165		void i8089_channel::orb_mr(int m, int r, int o) { UNIMPLEMENTED }
166		void i8089_channel::orbi_ri(int r, int i) { UNIMPLEMENTED }
167		void i8089_channel::orbi_mi(int m, int i, int o) { UNIMPLEMENTED }
168		void i8089_channel::ori_ri(int r, int i) { UNIMPLEMENTED }
169		void i8089_channel::ori_mi(int m, int i, int o) { UNIMPLEMENTED }
170		void i8089_channel::setb(int m, int b, int o) { UNIMPLEMENTED }
	306	void i8089_channel::not_r(int r)
	307	{
	308	set_reg(r, ~m_r[r].w);
	309	}
171	310
	311	void i8089_channel::not_m(int m, int o)
	312	{
	313	SWR(m, o, ~LWR(m, o));
	314	}
	315
	316	void i8089_channel::not_rm(int r, int m, int o)
	317	{
	318	set_reg(r, ~LWR(m, o));
	319	}
	320
	321	void i8089_channel::notb_m(int m, int o)
	322	{
	323	SBR(m, o, ~LBR(m, o));
	324	}
	325
	326	void i8089_channel::notb_rm(int r, int m, int o)
	327	{
	328	set_reg(r, ~(INT32)LBR(m, o));
	329	}
	330
	331	void i8089_channel::or_rm(int r, int m, int o)
	332	{
	333	set_reg(r, m_r[r].w | LWR(m, o));
	334	}
	335
	336	void i8089_channel::or_mr(int m, int r, int o)
	337	{
	338	SWR(m, o, LWR(m, o) | m_r[r].w);
	339	}
	340
	341	void i8089_channel::orb_rm(int r, int m, int o)
	342	{
	343	set_reg(r, m_r[r].w | (INT16)LBR(m, o));
	344	}
	345
	346	void i8089_channel::orb_mr(int m, int r, int o)
	347	{
	348	SBR(m, o, LBR(m, o) | m_r[r].w);
	349	}
	350
	351	void i8089_channel::orbi_ri(int r, INT8 i)
	352	{
	353	set_reg(r, m_r[r].w | (INT16)i);
	354	}
	355
	356	void i8089_channel::orbi_mi(int m, INT8 i, int o)
	357	{
	358	SBR(m, o, LBR(m, o) | i);
	359	}
	360
	361	void i8089_channel::ori_ri(int r, INT16 i)
	362	{
	363	set_reg(r, m_r[r].w | i);
	364	}
	365
	366	void i8089_channel::ori_mi(int m, INT16 i, int o)
	367	{
	368	SWR(m, o, LWR(m, o) | i);
	369	}
	370
	371	void i8089_channel::setb(int m, int b, int o)
	372	{
	373	SBR(m, o, LBR(m, o) | (1<<b));
	374	}
	375
	376
172	377	// set interrupt service flip-flop
173	378	void i8089_channel::sintr()
174	379	{
r26688	r26689
179	384	}
180	385	}
181	386
182		void i8089_channel::tsl(int m, int i, int d, int o) { UNIMPLEMENTED }
	387	void i8089_channel::tsl(int m, INT8 i, INT8 d, int o)
	388	{
	389	if(LBR(m, o))
	390	set_reg(TP, m_r[TP].w + d);
	391	else
	392	SBR(m, o, i);
	393	}
183	394
	395
184	396	// set source and destination logical widths
185	397	void i8089_channel::wid(int s, int d)
186	398	{

trunk/src/emu/cpu/i8089/i8089_dasm.c

r26688	r26689
20	20	switch (wb)
21	21	{
22	22	case 1:
23		result = oprom[2 + aa1];
	23	result = (INT16)(INT8)oprom[2 + aa1];
24	24	pc += 1;
25	25	break;
26	26	case 2:
r26688	r26689
104	104	sprintf(buffer, "lpdi %s, %4x %4x", BRP, off, seg);
105	105	break;
106	106	case 0x08:
	107	if(brp == 4)
	108	{
	109	INT16 offset = (w ? IMM16 : (INT8)IMM8);
	110	sprintf(buffer, "jmp %06x", pc + offset);
	111	break;
	112	}
107	113	if (w) sprintf(buffer, "addi %s, %04x", BRP, IMM16);
108	114	else   sprintf(buffer, "addbi %s, %02x", BRP, IMM8);
109	115	break;
r26688	r26689
169	175	else sprintf(buffer, "movb %s, %s", buf, o);
170	176	break;
171	177	}
	178	case 0x25:
	179	{
	180	OFFSET(o);
	181	UINT16 i = IMM16;
	182	sprintf(buffer, "tsl %s, %02x, %06x", o, i & 0xff, pc + (i >> 8));
	183	break;
	184	}
172	185	case 0x26:
173	186	OFFSET(o);
174	187	sprintf(buffer, "movp %s, %s", o, BRP);
r26688	r26689
222	235	case 0x31:
223	236	OFFSET(o);
224	237	if (w) sprintf(buffer, "ori %s, %04x", o, IMM16);
225		else   sprintf(buffer, "ori %s, %02x", o, IMM8);
	238	else   sprintf(buffer, "orib %s, %02x", o, IMM8);
226	239	break;
227	240	case 0x32:
228	241	OFFSET(o);
r26688	r26689
275	288	break;
276	289	case 0x3d:
277	290	OFFSET(o);
278		sprintf(buffer, "set %s, %d", o, brp);
	291	sprintf(buffer, "setb %s, %d", o, brp);
279	292	break;
280	293	case 0x3e:
281	294	OFFSET(o);

trunk/src/emu/cpu/i8089/i8089.h

r26688	r26689
85	85
86	86	// device_disasm_interface overrides
87	87	virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
88		virtual UINT32 disasm_max_opcode_bytes() const { return 6; }
	88	virtual UINT32 disasm_max_opcode_bytes() const { return 7; }
89	89	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
90	90
91	91	// device_state_interface overrides
r26688	r26689
99	99	bool remotebus_width() { return BIT(m_soc, 0); }
100	100	bool request_grant() { return BIT(m_soc, 1); }
101	101
102		UINT8 read_byte(offs_t address);
103		UINT16 read_word(offs_t address);
104		void write_byte(offs_t address, UINT8 data);
105		void write_word(offs_t address, UINT16 data);
	102	UINT8 read_byte(bool space, offs_t address);
	103	UINT16 read_word(bool space, offs_t address);
	104	void write_byte(bool space, offs_t address, UINT8 data);
	105	void write_word(bool space, offs_t address, UINT16 data);
106	106
107	107	required_device<i8089_channel> m_ch1;
108	108	required_device<i8089_channel> m_ch2;

trunk/src/mess/mess.lst

r26688	r26689
764	764	pc2386
765	765
766	766	xtvga    // 198? PC-XT (VGA, MF2 Keyboard)
767		iskr1031
768		iskr1030m
769		iskr3104
	767	zdsupers
	768	m24
	769	m240
	770	olivm15
	771
	772	// Various PC and XT clones produced in ex-USSR and Soviet bloc
770	773	asst128
771	774	ec1840
772	775	ec1841
773	776	ec1845
	777	ec1847
	778	iskr1030m
	779	iskr1031
	780	iskr3104
	781	mc1502
	782	mc1702
774	783	mk88
	784	pk88
775	785	poisk1
776	786	poisk2
777		mc1702
778		mc1502
779		zdsupers
780		m24
781		m240
782		olivm15
783	787
784	788	// AT
785	789	ibm5170   // 1984 IBM PC/AT 5170, original 6 MHz model

trunk/src/mess/mess.mak

r26688	r26689
689	689	$(MESSOBJ)/wang.a \
690	690	$(MESSOBJ)/wavemate.a \
691	691	$(MESSOBJ)/xerox.a \
	692	$(MESSOBJ)/xussrpc.a \
692	693	$(MESSOBJ)/yamaha.a \
693	694	$(MESSOBJ)/zpa.a \
694	695	$(MESSOBJ)/zvt.a \
r26688	r26689
1341	1342	$(MESSOBJ)/intel.a:             \
1342	1343	$(MESS_DRIVERS)/basic52.o   \
1343	1344	$(MESS_DRIVERS)/isbc.o      \
	1345	$(MESS_MACHINE)/isbc_215g.o \
1344	1346	$(MESS_DRIVERS)/ipc.o       \
1345	1347	$(MESS_DRIVERS)/ipds.o      \
1346	1348	$(MESS_DRIVERS)/imds.o      \
r26688	r26689
2104	2106	$(MESS_DRIVERS)/xerox820.o  \
2105	2107	$(MESS_DRIVERS)/bigbord2.o  \
2106	2108
	2109	$(MESSOBJ)/xussrpc.a:            \
	2110	$(MESS_DRIVERS)/ec184x.o    \
	2111	$(MESS_DRIVERS)/iskr103x.o  \
	2112	$(MESS_DRIVERS)/poisk1.o    \
	2113	$(MESS_MACHINE)/p1_fdc.o    \
	2114	$(MESS_MACHINE)/p1_hdc.o    \
	2115	$(MESS_MACHINE)/p1_rom.o    \
	2116	$(MESS_VIDEO)/poisk1.o      \
	2117	$(MESS_DRIVERS)/mc1502.o    \
	2118	$(MESS_MACHINE)/mc1502_fdc.o\
	2119	$(MESS_MACHINE)/mc1502_rom.o\
	2120	$(MESS_MACHINE)/xsu_cards.o \
	2121
2107	2122	$(MESSOBJ)/yamaha.a:            \
2108	2123	$(MESS_DRIVERS)/ymmu100.o   \
2109	2124

trunk/src/mess/drivers/ec184x.c

r0	r26689
	1	/***************************************************************************
	2
	3	drivers/ec184x.c
	4
	5	Driver file for EC-184x series
	6
	7	TODO (ec1840)
	8	- memory bank size is smaller (128K)
	9
	10	TODO (ec1841)
	11	- add chargen upload support for MDA
	12	- hard disk is connected but requires changes to isa_hdc.c
	13
	14	***************************************************************************/
	15
	16
	17	#include "emu.h"
	18
	19	#include "includes/genpc.h"
	20
	21	#include "bus/pc_kbd/keyboards.h"
	22	#include "cpu/i86/i86.h"
	23	#include "machine/ram.h"
	24
	25	#define VERBOSE_DBG 1       /* general debug messages */
	26
	27	#define DBG_LOG(N,M,A) \
	28	do { \
	29	if(VERBOSE_DBG>=N) \
	30	{ \
	31	if( M ) \
	32	logerror("%11.6f at %s: %-24s",machine().time().as_double(),machine().describe_context(),(char*)M ); \
	33	logerror A; \
	34	} \
	35	} while (0)
	36
	37
	38
	39	class ec184x_state : public driver_device
	40	{
	41	public:
	42	ec184x_state(const machine_config &mconfig, device_type type, const char *tag)
	43	: driver_device(mconfig, type, tag) ,
	44	m_maincpu(*this, "maincpu") { }
	45
	46	required_device<cpu_device> m_maincpu;
	47
	48	DECLARE_MACHINE_RESET(ec184x);
	49	DECLARE_DRIVER_INIT(ec184x);
	50
	51	struct {
	52	UINT8 enable[4];
	53	int boards;
	54	int board_size;
	55	} m_memory;
	56
	57	DECLARE_READ8_MEMBER(memboard_r);
	58	DECLARE_WRITE8_MEMBER(memboard_w);
	59	};
	60
	61	/*
	62	* EC-1841 memory controller.  The machine can hold four memory boards;
	63	* each board has a control register, its address is set by a DIP switch
	64	* on the board itself.
	65	*
	66	* Only one board should be enabled for read, and one for write.
	67	* Normally, this is the same board.
	68	*
	69	* Each board is divided into 4 banks, internally numbererd 0..3.
	70	* POST tests each board on startup, and an error (indicated by
	71	* I/O CH CK bus signal) causes it to disable failing bank(s) by writing
	72	* 'reconfiguration code' (inverted number of failing memory bank) to
	73	* the register.
	74
	75	* bit 1-0  'reconfiguration code'
	76	* bit 2    enable read access
	77	* bit 3    enable write access
	78	*/
	79
	80	READ8_MEMBER(ec184x_state::memboard_r)
	81	{
	82	UINT8 data;
	83
	84	data = offset % 4;
	85	if (data > m_memory.boards)
	86	data = 0xff;
	87	else
	88	data = m_memory.enable[data];
	89	DBG_LOG(1,"ec1841_memboard",("R (%d of %d) == %02X\n", offset, m_memory.boards, data ));
	90
	91	return data;
	92	}
	93
	94	WRITE8_MEMBER(ec184x_state::memboard_w)
	95	{
	96	address_space &program = m_maincpu->space(AS_PROGRAM);
	97	ram_device *m_ram = machine().device<ram_device>(RAM_TAG);
	98	UINT8 current;
	99
	100	current = m_memory.enable[offset];
	101
	102	DBG_LOG(1,"ec1841_memboard",("W (%d of %d) <- %02X (%02X)\n", offset, m_memory.boards, data, current));
	103
	104	if (offset > m_memory.boards) {
	105	return;
	106	}
	107
	108	if (BIT(current, 2) && !BIT(data, 2)) {
	109	// disable read access
	110	program.unmap_read(0, m_memory.board_size-1);
	111	DBG_LOG(1,"ec1841_memboard_w",("unmap_read(%d)\n", offset));
	112	}
	113
	114	if (BIT(current, 3) && !BIT(data, 3)) {
	115	// disable write access
	116	program.unmap_write(0, 0x7ffff);
	117	DBG_LOG(1,"ec1841_memboard_w",("unmap_write(%d)\n", offset));
	118	}
	119
	120	if (!BIT(current, 2) && BIT(data, 2)) {
	121	for(int i=0; i<4; i++)
	122	m_memory.enable[i] &= 0xfb;
	123	// enable read access
	124	membank("bank10")->set_base(m_ram->pointer() + offset*0x80000);
	125	program.install_read_bank(0, m_memory.board_size-1, "bank10");
	126	DBG_LOG(1,"ec1841_memboard_w",("map_read(%d)\n", offset));
	127	}
	128
	129	if (!BIT(current, 3) && BIT(data, 3)) {
	130	for(int i=0; i<4; i++)
	131	m_memory.enable[i] &= 0xf7;
	132	// enable write access
	133	membank("bank20")->set_base(m_ram->pointer() + offset*0x80000);
	134	program.install_write_bank(0, m_memory.board_size-1, "bank20");
	135	DBG_LOG(1,"ec1841_memboard_w",("map_write(%d)\n", offset));
	136	}
	137
	138	m_memory.enable[offset] = data;
	139	}
	140
	141	const struct pit8253_interface ec1841_pit8253_config =
	142	{
	143	{
	144	{
	145	XTAL_4MHz/4,                /* heartbeat IRQ */
	146	DEVCB_NULL,
	147	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir0_w)
	148	}, {
	149	XTAL_4MHz/4,                /* dram refresh */
	150	DEVCB_NULL,
	151	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_pit8253_out1_changed)
	152	}, {
	153	XTAL_4MHz/4,                /* pio port c pin 4, and speaker polling enough */
	154	DEVCB_NULL,
	155	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_pit8253_out2_changed)
	156	}
	157	}
	158	};
	159
	160
	161	DRIVER_INIT_MEMBER( ec184x_state, ec184x )
	162	{
	163	address_space &program = m_maincpu->space(AS_PROGRAM);
	164	ram_device *m_ram = machine().device<ram_device>(RAM_TAG);
	165
	166	m_memory.board_size = 512 * 1024; // XXX
	167	m_memory.boards = m_ram->size()/m_memory.board_size - 1;
	168	if (m_memory.boards > 3)
	169	m_memory.boards = 3;
	170
	171	program.install_read_bank(0, m_memory.board_size-1, "bank10");
	172	program.install_write_bank(0, m_memory.board_size-1, "bank20");
	173	membank( "bank10" )->set_base( m_ram->pointer() );
	174	membank( "bank20" )->set_base( m_ram->pointer() );
	175	}
	176
	177	MACHINE_RESET_MEMBER( ec184x_state, ec184x )
	178	{
	179	memset(m_memory.enable, 0, sizeof(m_memory.enable));
	180	// mark 1st board enabled
	181	m_memory.enable[0] = 0xc;
	182	}
	183
	184
	185	static ADDRESS_MAP_START( ec1840_map, AS_PROGRAM, 8, ec184x_state )
	186	ADDRESS_MAP_UNMAP_HIGH
	187	AM_RANGE(0x00000, 0x7ffff) AM_RAM
	188	AM_RANGE(0xa0000, 0xbffff) AM_NOP
	189	AM_RANGE(0xc0000, 0xc7fff) AM_ROM
	190	AM_RANGE(0xc8000, 0xcffff) AM_ROM
	191	AM_RANGE(0xdc000, 0xdffff) AM_RAM
	192	AM_RANGE(0xf0000, 0xfffff) AM_ROM
	193	ADDRESS_MAP_END
	194
	195	static ADDRESS_MAP_START( ec1841_map, AS_PROGRAM, 16, ec184x_state )
	196	ADDRESS_MAP_UNMAP_HIGH
	197	AM_RANGE(0x00000, 0x7ffff) AM_RAM
	198	AM_RANGE(0xa0000, 0xbffff) AM_NOP
	199	AM_RANGE(0xc0000, 0xc7fff) AM_ROM
	200	AM_RANGE(0xc8000, 0xcffff) AM_ROM
	201	AM_RANGE(0xdc000, 0xdffff) AM_RAM       // monochrome chargen
	202	AM_RANGE(0xf0000, 0xfffff) AM_ROM
	203	ADDRESS_MAP_END
	204
	205	static ADDRESS_MAP_START( ec1847_map, AS_PROGRAM, 8, ec184x_state )
	206	ADDRESS_MAP_UNMAP_HIGH
	207	AM_RANGE(0x00000, 0x9ffff) AM_RAMBANK("bank10")
	208	AM_RANGE(0xa0000, 0xbffff) AM_NOP
	209	AM_RANGE(0xc0000, 0xc7fff) AM_ROM
	210	AM_RANGE(0xc8000, 0xcffff) AM_ROM
	211	AM_RANGE(0xdc000, 0xdffff) AM_RAM
	212	AM_RANGE(0xf0000, 0xfffff) AM_ROM
	213	ADDRESS_MAP_END
	214
	215	static ADDRESS_MAP_START( ec1840_io, AS_IO, 8, ec184x_state )
	216	ADDRESS_MAP_UNMAP_HIGH
	217	ADDRESS_MAP_END
	218
	219	static ADDRESS_MAP_START( ec1841_io, AS_IO, 16, ec184x_state )
	220	ADDRESS_MAP_UNMAP_HIGH
	221	AM_RANGE(0x02b0, 0x02b3) AM_READWRITE8(memboard_r, memboard_w, 0xffff);
	222	ADDRESS_MAP_END
	223
	224	static ADDRESS_MAP_START( ec1847_io, AS_IO, 8, ec184x_state )
	225	ADDRESS_MAP_UNMAP_HIGH
	226	//   AM_RANGE(0x0210, 0x021f) AM_RAM // internal (non-standard?) bus extender
	227	ADDRESS_MAP_END
	228
	229
	230	static INPUT_PORTS_START( ec1841 )
	231	INPUT_PORTS_END
	232
	233	static DEVICE_INPUT_DEFAULTS_START( ec1840 )
	234	DEVICE_INPUT_DEFAULTS("DSW0", 0x31, 0x21)
	235	DEVICE_INPUT_DEFAULTS_END
	236
	237	static DEVICE_INPUT_DEFAULTS_START( ec1841 )
	238	DEVICE_INPUT_DEFAULTS("DSW0", 0x31, 0x21)
	239	DEVICE_INPUT_DEFAULTS_END
	240
	241	static DEVICE_INPUT_DEFAULTS_START( ec1847 )
	242	DEVICE_INPUT_DEFAULTS("DSW0", 0x31, 0x31)
	243	DEVICE_INPUT_DEFAULTS_END
	244
	245	// XXX verify everything
	246	static MACHINE_CONFIG_START( ec1840, ec184x_state )
	247	MCFG_CPU_ADD("maincpu", I8088, 4096000)
	248	MCFG_CPU_PROGRAM_MAP(ec1840_map)
	249	MCFG_CPU_IO_MAP(ec1840_io)
	250
	251	MCFG_IBM5150_MOTHERBOARD_ADD("mb","maincpu")
	252	MCFG_DEVICE_INPUT_DEFAULTS(ec1840)
	253
	254	MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", pc_isa8_cards, "mda", false)   // cga is? an option
	255	MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", pc_isa8_cards, "fdc_xt", false)
	256	MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, NULL, false)   // native variant(s?) not emulated
	257	MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", pc_isa8_cards, NULL, false)   // native serial not emulated
	258	MCFG_ISA8_SLOT_ADD("mb:isa", "isa5", pc_isa8_cards, NULL, false)   // native mouse port not emulated
	259	MCFG_ISA8_SLOT_ADD("mb:isa", "isa6", pc_isa8_cards, NULL, false)   // game port is an option
	260
	261	MCFG_SOFTWARE_LIST_ADD("flop_list","ec1841")
	262
	263	MCFG_PC_KBDC_SLOT_ADD("mb:pc_kbdc", "kbd", pc_xt_keyboards, STR_KBD_EC_1841)
	264
	265	MCFG_RAM_ADD(RAM_TAG)
	266	MCFG_RAM_DEFAULT_SIZE("512K")
	267	MACHINE_CONFIG_END
	268
	269	static MACHINE_CONFIG_START( ec1841, ec184x_state )
	270	MCFG_CPU_ADD("maincpu", I8086, 4096000)
	271	MCFG_CPU_PROGRAM_MAP(ec1841_map)
	272	MCFG_CPU_IO_MAP(ec1841_io)
	273
	274	//   MCFG_MACHINE_START_OVERRIDE(ec184x_state, ec184x)
	275	MCFG_MACHINE_RESET_OVERRIDE(ec184x_state, ec184x)
	276
	277	MCFG_EC1841_MOTHERBOARD_ADD("mb", "maincpu")
	278	MCFG_DEVICE_INPUT_DEFAULTS(ec1841)
	279
	280	MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", pc_isa8_cards, "cga_ec1841", false)// mda is an option
	281	MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", pc_isa8_cards, "fdc_xt", false)
	282	MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, NULL, false)   // native variants not emulated
	283	MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", pc_isa8_cards, NULL, false)   // native serial not emulated
	284	MCFG_ISA8_SLOT_ADD("mb:isa", "isa5", pc_isa8_cards, NULL, false)   // native mouse port not emulated
	285	MCFG_ISA8_SLOT_ADD("mb:isa", "isa6", pc_isa8_cards, NULL, false)   // game port is? an option
	286
	287	MCFG_SOFTWARE_LIST_ADD("flop_list","ec1841")
	288
	289	MCFG_PC_KBDC_SLOT_ADD("mb:pc_kbdc", "kbd", pc_xt_keyboards, STR_KBD_EC_1841)
	290
	291	MCFG_RAM_ADD(RAM_TAG)
	292	MCFG_RAM_DEFAULT_SIZE("512K")
	293	MCFG_RAM_EXTRA_OPTIONS("1024K,1576K,2048K")   // 640K variant not emulated
	294	MACHINE_CONFIG_END
	295
	296	// XXX verify everything
	297	static MACHINE_CONFIG_START( ec1847, ec184x_state )
	298	MCFG_CPU_ADD("maincpu", I8088, 4772720)
	299	MCFG_CPU_PROGRAM_MAP(ec1847_map)
	300	MCFG_CPU_IO_MAP(ec1847_io)
	301
	302	MCFG_IBM5160_MOTHERBOARD_ADD("mb","maincpu")
	303	MCFG_DEVICE_INPUT_DEFAULTS(ec1847)
	304
	305	MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", pc_isa8_cards, "hercules", false)   // cga, ega and vga(?) are options too
	306	MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", pc_isa8_cards, "fdc_xt", false)
	307	MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, NULL, false)   // native variant (wd1010 + z80) not emulated
	308	MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", pc_isa8_cards, NULL, false)   // native serial (2x8251) not emulated
	309	MCFG_ISA8_SLOT_ADD("mb:isa", "isa5", pc_isa8_cards, NULL, false)
	310	MCFG_ISA8_SLOT_ADD("mb:isa", "isa6", pc_isa8_cards, NULL, false)
	311
	312	MCFG_PC_KBDC_SLOT_ADD("mb:pc_kbdc", "kbd", pc_xt_keyboards, STR_KBD_KEYTRONIC_PC3270)
	313
	314	MCFG_RAM_ADD(RAM_TAG)
	315	MCFG_RAM_DEFAULT_SIZE("640K")
	316	MACHINE_CONFIG_END
	317
	318	ROM_START( ec1840 )
	319	ROM_REGION16_LE(0x100000,"maincpu", 0)
	320	ROM_SYSTEM_BIOS(0, "v4", "EC-1840.04")
	321	ROMX_LOAD( "000-04-971b.bin", 0xfe000, 0x0800, CRC(06aeaee8) SHA1(9f954e4c48156d573a8e0109e7ca652be9e6036a), ROM_SKIP(1) | ROM_BIOS(1))
	322	ROMX_LOAD( "001-04-92b7.bin", 0xff000, 0x0800, CRC(3fae650a) SHA1(c98b777fdeceadd72d6eb9465b3501b9ead55a08), ROM_SKIP(1) | ROM_BIOS(1))
	323	ROMX_LOAD( "002-04-9e17.bin", 0xfe001, 0x0800, CRC(d59712df) SHA1(02ea1b3ae9662f5c64c58920a32ca9db0f6fbd12), ROM_SKIP(1) | ROM_BIOS(1))
	324	ROMX_LOAD( "003-04-3ccb.bin", 0xff001, 0x0800, CRC(7fc362c7) SHA1(538e13639ad2b4c30bd72582e323181e63513306), ROM_SKIP(1) | ROM_BIOS(1))
	325
	326	ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
	327	ROM_END
	328
	329	ROM_START( ec1841 )
	330	ROM_REGION16_LE(0x100000,"maincpu", 0)
	331	ROM_DEFAULT_BIOS("v2")
	332	ROM_SYSTEM_BIOS(0, "v1", "EC-1841.01")
	333	ROMX_LOAD( "012-01-3107.bin", 0xfc000, 0x0800, CRC(77957396) SHA1(785f1dceb6e2b4618f5c5f0af15eb74a8c951448), ROM_SKIP(1) | ROM_BIOS(1))
	334	ROMX_LOAD( "013-01-203f.bin", 0xfc001, 0x0800, CRC(768bd3d5) SHA1(2e948f2ad262de306d889b7964c3f1aad45ff5bc), ROM_SKIP(1) | ROM_BIOS(1))
	335	ROMX_LOAD( "014-01-fa40.bin", 0xfd000, 0x0800, CRC(47722b58) SHA1(a6339ee8af516f834826b7828a5cf79cb650480c), ROM_SKIP(1) | ROM_BIOS(1))
	336	ROMX_LOAD( "015-01-bf1d.bin", 0xfd001, 0x0800, CRC(b585b5ea) SHA1(d0ebed586eb13031477c2e071c50416682f80489), ROM_SKIP(1) | ROM_BIOS(1))
	337	ROMX_LOAD( "016-01-65f7.bin", 0xfe000, 0x0800, CRC(28a07db4) SHA1(17fbcd60dacd1d3f8d8355db429f97e4d1d1ac88), ROM_SKIP(1) | ROM_BIOS(1))
	338	ROMX_LOAD( "017-01-5be1.bin", 0xfe001, 0x0800, CRC(928bda26) SHA1(ee889184067e2680b29a8ef1c3a76cf5afd4c78d), ROM_SKIP(1) | ROM_BIOS(1))
	339	ROMX_LOAD( "018-01-7090.bin", 0xff000, 0x0800, CRC(75ca7d7e) SHA1(6356426820c5326a7893a437d54b02f250ef8609), ROM_SKIP(1) | ROM_BIOS(1))
	340	ROMX_LOAD( "019-01-0492.bin", 0xff001, 0x0800, CRC(8a9d593e) SHA1(f3936d2cb4e6d130dd732973f126c3aa20612463), ROM_SKIP(1) | ROM_BIOS(1))
	341
	342	ROM_SYSTEM_BIOS(1, "v2", "EC-1841.02")
	343	ROMX_LOAD( "012-02-37f6.bin", 0xfc000, 0x0800, CRC(8f5c6a20) SHA1(874b62f9cee8d3b974f33732f94eff10fc002c44), ROM_SKIP(1) | ROM_BIOS(2))
	344	ROMX_LOAD( "013-02-2552.bin", 0xfc001, 0x0800, CRC(e3c10128) SHA1(d6ed743ebe9c130925c9f17aad1a45db9194c967), ROM_SKIP(1) | ROM_BIOS(2))
	345	ROMX_LOAD( "014-02-0fbe.bin", 0xfd000, 0x0800, CRC(f8517e5e) SHA1(8034cd6ff5778365dc9daa494524f1753a74f1ed), ROM_SKIP(1) | ROM_BIOS(2))
	346	ROMX_LOAD( "015-02-d736.bin", 0xfd001, 0x0800, CRC(8538c52a) SHA1(ee981ce90870b6546a18f2a2e64d71b0038ce0dd), ROM_SKIP(1) | ROM_BIOS(2))
	347	ROMX_LOAD( "016-02-5b2c.bin", 0xfe000, 0x0800, CRC(3d1d1e67) SHA1(c527e29796537787c0f6c329f3c203f6131ca77f), ROM_SKIP(1) | ROM_BIOS(2))
	348	ROMX_LOAD( "017-02-4b9d.bin", 0xfe001, 0x0800, CRC(1b985264) SHA1(5ddcb9c13564be208c5068c105444a87159c67ee), ROM_SKIP(1) | ROM_BIOS(2))
	349	ROMX_LOAD( "018-02-7090.bin", 0xff000, 0x0800, CRC(75ca7d7e) SHA1(6356426820c5326a7893a437d54b02f250ef8609), ROM_SKIP(1) | ROM_BIOS(2))
	350	ROMX_LOAD( "019-02-0493.bin", 0xff001, 0x0800, CRC(61aae23d) SHA1(7b3aa24a63ee31b194297eb1e61c3827edfcb95a), ROM_SKIP(1) | ROM_BIOS(2))
	351
	352	ROM_SYSTEM_BIOS(2, "v3", "EC-1841.03")
	353	ROMX_LOAD( "012-03-37e7.bin", 0xfc000, 0x0800, CRC(49992bd5) SHA1(119121e1b4af1c44b9b8c2edabe7dc1d3019c4a6), ROM_SKIP(1) | ROM_BIOS(3))
	354	ROMX_LOAD( "013-03-2554.bin", 0xfc001, 0x0800, CRC(834bd7d7) SHA1(e37514fc4cb8a5cbe68e7564e0e07d5116c4021a), ROM_SKIP(1) | ROM_BIOS(3))
	355	ROMX_LOAD( "014-03-0fbe.bin", 0xfd000, 0x0800, CRC(f8517e5e) SHA1(8034cd6ff5778365dc9daa494524f1753a74f1ed), ROM_SKIP(1) | ROM_BIOS(3))
	356	ROMX_LOAD( "015-03-d736.bin", 0xfd001, 0x0800, CRC(8538c52a) SHA1(ee981ce90870b6546a18f2a2e64d71b0038ce0dd), ROM_SKIP(1) | ROM_BIOS(3))
	357	ROMX_LOAD( "016-03-5b2c.bin", 0xfe000, 0x0800, CRC(3d1d1e67) SHA1(c527e29796537787c0f6c329f3c203f6131ca77f), ROM_SKIP(1) | ROM_BIOS(3))
	358	ROMX_LOAD( "017-03-4b9d.bin", 0xfe001, 0x0800, CRC(1b985264) SHA1(5ddcb9c13564be208c5068c105444a87159c67ee), ROM_SKIP(1) | ROM_BIOS(3))
	359	ROMX_LOAD( "018-03-7090.bin", 0xff000, 0x0800, CRC(75ca7d7e) SHA1(6356426820c5326a7893a437d54b02f250ef8609), ROM_SKIP(1) | ROM_BIOS(3))
	360	ROMX_LOAD( "019-03-0493.bin", 0xff001, 0x0800, CRC(61aae23d) SHA1(7b3aa24a63ee31b194297eb1e61c3827edfcb95a), ROM_SKIP(1) | ROM_BIOS(3))
	361	ROM_END
	362
	363	ROM_START( ec1845 )
	364	ROM_REGION16_LE(0x100000,"maincpu", 0)
	365	ROMX_LOAD( "184500.bin", 0xfc000, 0x0800, CRC(7c472ef7) SHA1(3af53f27b49bbc731bf51f9300fbada23a1bfcfc), ROM_SKIP(1))
	366	ROMX_LOAD( "184501.bin", 0xfc001, 0x0800, CRC(db240dc6) SHA1(d7bb022213d09bbf2a8107fe4f1cd27b23939e18), ROM_SKIP(1))
	367	ROMX_LOAD( "184502.bin", 0xfd000, 0x0800, CRC(149e7e29) SHA1(7f2a297588fef1bc750c57e6ae0d5acf3d27c486), ROM_SKIP(1))
	368	ROMX_LOAD( "184503.bin", 0xfd001, 0x0800, CRC(e28cbd74) SHA1(cf1fba4e67c8e1dd8cdda547118e84b704029b03), ROM_SKIP(1))
	369	ROMX_LOAD( "184504.bin", 0xfe000, 0x0800, CRC(55fa7a1d) SHA1(58f7abab08b9d2f0a1c1636e11bb72af2694c95f), ROM_SKIP(1))
	370	ROMX_LOAD( "184505.bin", 0xfe001, 0x0800, CRC(c807e3f5) SHA1(08117e449f0d04f96041cff8d34893f500f3760d), ROM_SKIP(1))
	371	ROMX_LOAD( "184506.bin", 0xff000, 0x0800, CRC(24f5c27c) SHA1(7822dd7f715ef00ccf6d8408be8bbfe01c2eba20), ROM_SKIP(1))
	372	ROMX_LOAD( "184507.bin", 0xff001, 0x0800, CRC(75122203) SHA1(7b0fbdf1315230633e39574ac7360163bc7361e1), ROM_SKIP(1))
	373	ROM_END
	374
	375	ROM_START( ec1847 )
	376	ROM_REGION16_LE(0x100000,"maincpu", 0)
	377	ROM_SYSTEM_BIOS(0, "vXXX", "EC-1847.0x")
	378	ROMX_LOAD( "308_d47_2764.bin", 0xc8000, 0x2000, CRC(f06924f2) SHA1(83a5dedf1c06f875c598f087bbc087524bc9bfa3), ROM_BIOS(1))
	379	ROMX_LOAD( "188m_d47_2764.bin", 0xf4000, 0x2000, CRC(bc8742c7) SHA1(3af09d14e891e976b7a9a2a6e1af63f0eabe5426), ROM_BIOS(1))
	380	ROMX_LOAD( "188m_d48_2764.bin", 0xfe000, 0x2000, CRC(7d290e95) SHA1(e73e6c8e19477fce5de3f95b89693dc6ad6781ab), ROM_BIOS(1))
	381
	382	ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
	383	ROM_LOAD( "317_d28_2732.bin", 0x00000, 0x1000, CRC(8939599b) SHA1(53d02460cf93596882a96758ef4bac5fa1ce55b2)) // monochrome font
	384	ROM_END
	385
	386	/***************************************************************************
	387
	388	Game driver(s)
	389
	390	***************************************************************************/
	391
	392	/*     YEAR     ROM NAME    PARENT      COMPAT  MACHINE     INPUT                       INIT        COMPANY     FULLNAME */
	393	COMP ( 1987,    ec1840,     ibm5150,    0,      ec1840,     ec1841,   ec184x_state,     ec184x,     "<unknown>",  "EC-1840", GAME_NOT_WORKING)
	394	COMP ( 1987,    ec1841,     ibm5150,    0,      ec1841,     ec1841,   ec184x_state,     ec184x,     "<unknown>",  "EC-1841", 0)
	395	COMP ( 1989,    ec1845,     ibm5150,    0,      ec1841,     ec1841,   ec184x_state,     ec184x,     "<unknown>",  "EC-1845", GAME_NOT_WORKING)
	396	COMP ( 1990,    ec1847,     ibm5150,    0,      ec1847,     ec1841,   driver_device,    0,          "<unknown>",  "EC-1847", GAME_NOT_WORKING)

Property changes on: trunk/src/mess/drivers/ec184x.c

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/mess/drivers/isbc.c

r26688	r26689
24	24	#include "machine/serial.h"
25	25	#include "bus/centronics/ctronics.h"
26	26	#include "bus/isbx/isbx.h"
	27	#include "machine/isbc_215g.h"
27	28
28	29	class isbc_state : public driver_device
29	30	{
r26688	r26689
100	101	AM_RANGE(0x00c8, 0x00cf) AM_DEVREADWRITE8("ppi", i8255_device, read, write, 0x00ff)
101	102	AM_RANGE(0x00d0, 0x00d7) AM_DEVREADWRITE8("pit", pit8254_device, read, write, 0x00ff)
102	103	AM_RANGE(0x00d8, 0x00df) AM_DEVREADWRITE8("uart8274", i8274_device, cd_ba_r, cd_ba_w, 0x00ff)
	104	AM_RANGE(0x0100, 0x0101) AM_DEVWRITE8("isbc_215g", isbc_215g_device, write, 0x00ff)
103	105	ADDRESS_MAP_END
104	106
105	107	static ADDRESS_MAP_START(isbc286_mem, AS_PROGRAM, 16, isbc_state)
r26688	r26689
324	326	MCFG_ISBX_SLOT_MINTR0_CALLBACK(DEVWRITELINE("pic_1", pic8259_device, ir5_w))
325	327	MCFG_ISBX_SLOT_MINTR1_CALLBACK(DEVWRITELINE("pic_1", pic8259_device, ir6_w))
326	328
	329	MCFG_ISBC_215_ADD("isbc_215g", 0x100, "maincpu")
	330	MCFG_ISBC_215_IRQ(DEVWRITELINE("pic_0", pic8259_device, ir5_w))
	331
327	332	/* video hardware */
328	333	MCFG_SERIAL_TERMINAL_ADD("terminal", terminal_intf, 9600)
329	334	MCFG_DEVICE_INPUT_DEFAULTS(isbc286_terminal)
r26688	r26689
347	352	ROM_REGION( 0x20000, "user1", ROMREGION_ERASEFF )
348	353	ROM_LOAD16_BYTE( "u79.bin", 0x00001, 0x10000, CRC(144182ea) SHA1(4620ca205a6ac98fe2636183eaead7c4bfaf7a72))
349	354	ROM_LOAD16_BYTE( "u36.bin", 0x00000, 0x10000, CRC(22db075f) SHA1(fd29ea77f5fc0697c8f8b66aca549aad5b9db3ea))
350		ROM_REGION( 0x4000, "isbc215", ROMREGION_ERASEFF )
351		ROM_LOAD16_BYTE( "174581.001.bin", 0x0000, 0x2000, CRC(ccdbc7ab) SHA1(5c2ebdde1b0252124177221ba9cacdb6d925a24d))
352		ROM_LOAD16_BYTE( "174581.002.bin", 0x0001, 0x2000, CRC(6190fa67) SHA1(295dd4e75f699aaf93227cc4876cee8accae383a))
	355	//   ROM_REGION( 0x4000, "isbc215", ROMREGION_ERASEFF )
	356	//   ROM_LOAD16_BYTE( "174581.001.bin", 0x0000, 0x2000, CRC(ccdbc7ab) SHA1(5c2ebdde1b0252124177221ba9cacdb6d925a24d))
	357	//   ROM_LOAD16_BYTE( "174581.002.bin", 0x0001, 0x2000, CRC(6190fa67) SHA1(295dd4e75f699aaf93227cc4876cee8accae383a))
353	358	ROM_END
354	359
355	360	ROM_START( isbc2861 )

trunk/src/mess/drivers/pc.c

r26688	r26689
66	66
67	67	#include "machine/i8255.h"
68	68	#include "machine/ins8250.h"
69		#include "machine/i8251.h"
70	69	#include "machine/mc146818.h"
71	70	#include "machine/pic8259.h"
72	71
r26688	r26689
100	99	#include "sound/sn76496.h"
101	100
102	101	#include "machine/wd_fdc.h"
103		#include "machine/kb_7007_3.h"
104	102
105	103	#include "machine/ram.h"
106	104	#include "bus/pc_kbd/keyboards.h"
r26688	r26689
128	126	AM_RANGE(0xf0000, 0xfffff) AM_ROM
129	127	ADDRESS_MAP_END
130	128
131		static ADDRESS_MAP_START( iskr1031_map, AS_PROGRAM, 16, pc_state )
	129	static ADDRESS_MAP_START( asst128_map, AS_PROGRAM, 16, pc_state )
132	130	ADDRESS_MAP_UNMAP_HIGH
133	131	AM_RANGE(0x00000, 0x7ffff) AM_RAMBANK("bank10")
134	132	AM_RANGE(0xa0000, 0xbffff) AM_NOP
r26688	r26689
138	136	AM_RANGE(0xf0000, 0xfffff) AM_ROM
139	137	ADDRESS_MAP_END
140	138
141		static ADDRESS_MAP_START( ec1841_map, AS_PROGRAM, 16, pc_state )
142		ADDRESS_MAP_UNMAP_HIGH
143		AM_RANGE(0x00000, 0x7ffff) AM_RAM
144		AM_RANGE(0xa0000, 0xbffff) AM_NOP
145		AM_RANGE(0xc0000, 0xc7fff) AM_ROM
146		AM_RANGE(0xc8000, 0xcffff) AM_ROM
147		AM_RANGE(0xdc000, 0xdffff) AM_RAM       // monochrome chargen
148		AM_RANGE(0xf0000, 0xfffff) AM_ROM
149		ADDRESS_MAP_END
150
151		static ADDRESS_MAP_START( mc1502_map, AS_PROGRAM, 8, pc_state )
152		ADDRESS_MAP_UNMAP_HIGH
153		AM_RANGE(0x00000, 0x97fff) AM_RAMBANK("bank10") /* 96K on mainboard + 512K on extension card */
154		AM_RANGE(0xe8000, 0xeffff) AM_ROM       /* BASIC */
155		AM_RANGE(0xfc000, 0xfffff) AM_ROM
156		ADDRESS_MAP_END
157
158		static ADDRESS_MAP_START(mc1502_io, AS_IO, 8, pc_state )
159		AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE("pic8259", pic8259_device, read, write)
160		AM_RANGE(0x0028, 0x0028) AM_DEVREADWRITE("upd8251", i8251_device, data_r, data_w)   // not working yet
161		AM_RANGE(0x0029, 0x0029) AM_DEVREADWRITE("upd8251", i8251_device, status_r, control_w)
162		AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE("pit8253", pit8253_device, read, write)
163		// BIOS 5.31, 5.33
164		AM_RANGE(0x004c, 0x004c) AM_READWRITE(mc1502_wd17xx_aux_r, mc1502_wd17xx_aux_w)
165		AM_RANGE(0x004d, 0x004d) AM_READ(mc1502_wd17xx_motor_r)
166		AM_RANGE(0x004e, 0x004e) AM_READ(mc1502_wd17xx_drq_r)           // blocking read!
167		AM_RANGE(0x0048, 0x004b) AM_DEVREADWRITE("vg93", fd1793_t, read, write)
168		AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE("ppi8255", i8255_device, read, write)
169		AM_RANGE(0x0068, 0x006B) AM_DEVREADWRITE("ppi8255n2", i8255_device, read, write)    // keyboard poll
170		// BIOS 5.0, 5.2
171		AM_RANGE(0x0100, 0x0100) AM_READWRITE(mc1502_wd17xx_aux_r, mc1502_wd17xx_aux_w)
172		AM_RANGE(0x0108, 0x0108) AM_READ(mc1502_wd17xx_drq_r)           // blocking read!
173		AM_RANGE(0x010a, 0x010a) AM_READ(mc1502_wd17xx_motor_r)
174		AM_RANGE(0x010c, 0x010f) AM_DEVREADWRITE("vg93", fd1793_t, read, write)
175		ADDRESS_MAP_END
176
177	139	static ADDRESS_MAP_START( zenith_map, AS_PROGRAM, 8, pc_state )
178	140	ADDRESS_MAP_UNMAP_HIGH
179	141	AM_RANGE(0x00000, 0x9ffff) AM_RAMBANK("bank10")
r26688	r26689
245	207	ADDRESS_MAP_END
246	208
247	209
248		static ADDRESS_MAP_START(ec1841_io, AS_IO, 16, pc_state)
249		ADDRESS_MAP_UNMAP_HIGH
250		AM_RANGE(0x0000, 0x000f) AM_DEVREADWRITE8("dma8237", am9517a_device, read, write, 0xffff)
251		AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE8("pic8259", pic8259_device, read, write, 0xffff)
252		AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xffff)
253		AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("ppi8255", i8255_device, read, write, 0xffff)
254		AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r,               pc_page_w, 0xffff)
255		AM_RANGE(0x00a0, 0x00a1) AM_WRITE8( pc_nmi_enable_w, 0x00ff )
256		AM_RANGE(0x0210, 0x0217) AM_NOP // expansion chassis interface
257		//  AM_RANGE(0x0230, 0x021f)    // mouse
258		AM_RANGE(0x0240, 0x0257) AM_READWRITE8(pc_rtc_r,                pc_rtc_w, 0xffff)
259		AM_RANGE(0x02b0, 0x02b3) AM_READWRITE8(ec1841_memboard_r, ec1841_memboard_w, 0xffff);
260		//  AM_RANGE(0x02f8, 0x02f8) AM_DEVREADWRITE8("upd8251_1", i8251_device, data_r, data_w, 0x00ff)
261		//  AM_RANGE(0x02f9, 0x02f9) AM_DEVREADWRITE8("upd8251_1", i8251_device, status_r, control_w, 0xff00)
262		AM_RANGE(0x0378, 0x037f) AM_DEVREADWRITE8("lpt_0", pc_lpt_device, read, write, 0xffff)
263		AM_RANGE(0x03f0, 0x03f7) AM_DEVICE8("fdc", pc_fdc_interface, map, 0xffff)
264		//  AM_RANGE(0x03f8, 0x03f9) AM_DEVREADWRITE8("upd8251_0", i8251_device, data_r, data_w, 0x00ff)
265		//  AM_RANGE(0x03f8, 0x03f9) AM_DEVREADWRITE8("upd8251_0", i8251_device, status_r, control_w, 0xff00)
266		ADDRESS_MAP_END
267
268
269		static ADDRESS_MAP_START(iskr1031_io, AS_IO, 16, pc_state)
270		ADDRESS_MAP_UNMAP_HIGH
271		AM_RANGE(0x0000, 0x000f) AM_DEVREADWRITE8("dma8237", am9517a_device, read, write, 0xffff)
272		AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE8("pic8259", pic8259_device, read, write, 0xffff)
273		AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xffff)
274		AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("ppi8255", i8255_device, read, write, 0xffff)
275		AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r,               pc_page_w, 0xffff)
276		AM_RANGE(0x00a0, 0x00a1) AM_WRITE8( pc_nmi_enable_w, 0x00ff )
277		//  AM_RANGE(0x0200, 0x0207) AM_DEVREADWRITE8("pc_joy", pc_joy_device, joy_port_r, joy_port_w, 0xffff)
278		AM_RANGE(0x0240, 0x0257) AM_READWRITE8(pc_rtc_r,                pc_rtc_w, 0xffff)
279		//  AM_RANGE(0x02e8, 0x02ef) AM_DEVREADWRITE8("ins8250_3", ins8250_device, ins8250_r, ins8250_w, 0xffff)
280		AM_RANGE(0x02f8, 0x02ff) AM_DEVREADWRITE8("ins8250_1", ins8250_device, ins8250_r, ins8250_w, 0xffff)
281		AM_RANGE(0x0340, 0x0357) AM_NOP /* anonymous bios should not recogniced realtimeclock */
282		AM_RANGE(0x0378, 0x037f) AM_DEVREADWRITE8("lpt_0", pc_lpt_device, read, write, 0xffff)
283		//  AM_RANGE(0x03e8, 0x03ef) AM_DEVREADWRITE8("ins8250_2", ins8250_device, ins8250_r, ins8250_w, 0xffff)
284		AM_RANGE(0x03f0, 0x03f7) AM_DEVICE8("fdc", pc_fdc_interface, map, 0xffff)
285		AM_RANGE(0x03f8, 0x03ff) AM_DEVREADWRITE8("ins8250_0", ins8250_device, ins8250_r, ins8250_w, 0xffff)
286		ADDRESS_MAP_END
287
288	210	static ADDRESS_MAP_START(asst128_io, AS_IO, 16, pc_state)
289	211	ADDRESS_MAP_UNMAP_HIGH
290	212	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE8("pic8259", pic8259_device, read, write, 0xffff)
r26688	r26689
813	735	PORT_BIT ( 0x08, 0x08,   IPT_CUSTOM ) PORT_VBLANK("pcvideo_pcjr:screen")
814	736	INPUT_PORTS_END
815	737
816		static INPUT_PORTS_START( mc1502 )          /* fix */
817		PORT_START("IN0") /* IN0 */
818		PORT_BIT ( 0xf0, 0xf0,   IPT_UNUSED )
819		PORT_BIT ( 0x08, 0x08,   IPT_CUSTOM ) PORT_VBLANK("screen")
820		PORT_BIT ( 0x07, 0x07,   IPT_UNUSED )
821	738
822		PORT_START("DSW0") /* IN1 */
823		PORT_DIPNAME( 0xc0, 0x40, "Number of floppy drives")
824		PORT_DIPSETTING(    0x00, "1" )
825		PORT_DIPSETTING(    0x40, "2" )
826		PORT_DIPSETTING(    0x80, "3" )
827		PORT_DIPSETTING(    0xc0, "4" )
828		PORT_DIPNAME( 0x30, 0x20, "Graphics adapter")
829		PORT_DIPSETTING(    0x00, "EGA/VGA" )
830		PORT_DIPSETTING(    0x10, "Color 40x25" )
831		PORT_DIPSETTING(    0x20, "Color 80x25" )
832		PORT_DIPSETTING(    0x30, "Monochrome" )
833		PORT_DIPNAME( 0x0c, 0x0c, "RAM banks")
834		PORT_DIPSETTING(    0x00, "1 - 16  64 256K" )
835		PORT_DIPSETTING(    0x04, "2 - 32 128 512K" )
836		PORT_DIPSETTING(    0x08, "3 - 48 192 576K" )
837		PORT_DIPSETTING(    0x0c, "4 - 64 256 640K" )
838		PORT_DIPNAME( 0x02, 0x00, "80387 installed")
839		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
840		PORT_DIPSETTING(    0x02, DEF_STR( Yes ) )
841		PORT_DIPNAME( 0x01, 0x01, "Floppy installed")
842		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
843		PORT_DIPSETTING(    0x01, DEF_STR( Yes ) )
844	739
845		PORT_START("DSW1") /* IN2 */
846		PORT_DIPNAME( 0x80, 0x80, "COM1: enable")
847		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
848		PORT_DIPSETTING(    0x80, DEF_STR( Yes ) )
849		PORT_DIPNAME( 0x40, 0x40, "COM2: enable")
850		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
851		PORT_DIPSETTING(    0x40, DEF_STR( Yes ) )
852		PORT_DIPNAME( 0x20, 0x00, "COM3: enable")
853		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
854		PORT_DIPSETTING(    0x20, DEF_STR( Yes ) )
855		PORT_DIPNAME( 0x10, 0x00, "COM4: enable")
856		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
857		PORT_DIPSETTING(    0x10, DEF_STR( Yes ) )
858		PORT_DIPNAME( 0x08, 0x08, "LPT1: enable")
859		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
860		PORT_DIPSETTING(    0x08, DEF_STR( Yes ) )
861		PORT_DIPNAME( 0x04, 0x00, "LPT2: enable")
862		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
863		PORT_DIPSETTING(    0x04, DEF_STR( Yes ) )
864		PORT_DIPNAME( 0x02, 0x00, "LPT3: enable")
865		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
866		PORT_DIPSETTING(    0x02, DEF_STR( Yes ) )
867		PORT_DIPNAME( 0x01, 0x00, "Game port enable")
868		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
869		PORT_DIPSETTING(    0x01, DEF_STR( Yes ) )
870
871		PORT_START("DSW2") /* IN3 */
872		PORT_DIPNAME( 0xf0, 0x80, "Serial mouse")
873		PORT_DIPSETTING(    0x80, "COM1" )
874		PORT_DIPSETTING(    0x40, "COM2" )
875		PORT_DIPSETTING(    0x20, "COM3" )
876		PORT_DIPSETTING(    0x10, "COM4" )
877		PORT_DIPSETTING(    0x00, DEF_STR( None ) )
878		PORT_DIPNAME( 0x08, 0x08, "HDC1 (C800:0 port 320-323)")
879		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
880		PORT_DIPSETTING(    0x08, DEF_STR( Yes ) )
881		PORT_DIPNAME( 0x04, 0x04, "HDC2 (CA00:0 port 324-327)")
882		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
883		PORT_DIPSETTING(    0x04, DEF_STR( Yes ) )
884		PORT_BIT( 0x02, 0x02,   IPT_UNUSED ) /* no turbo switch */
885		PORT_BIT( 0x01, 0x01,   IPT_UNUSED )
886
887		PORT_INCLUDE( mc7007_3_keyboard )
888		PORT_INCLUDE( pcvideo_mc1502 )
889		INPUT_PORTS_END
890
891		static INPUT_PORTS_START( ec1841 )
892		PORT_START("DSW0") /* SA1 */
893		PORT_DIPNAME( 0xc0, 0x40, "Number of floppy drives")
894		PORT_DIPSETTING(    0x00, "1" )
895		PORT_DIPSETTING(    0x40, "2" )
896		PORT_DIPSETTING(    0x80, "3" )
897		PORT_DIPSETTING(    0xc0, "4" )
898		PORT_DIPNAME( 0x30, 0x20, "Graphics adapter")
899		PORT_DIPSETTING(    0x00, "Reserved" )
900		PORT_DIPSETTING(    0x10, "Color 40x25" )
901		PORT_DIPSETTING(    0x20, "Color 80x25" )
902		PORT_DIPSETTING(    0x30, "Monochrome" )
903		PORT_BIT(     0x08, 0x08, IPT_UNUSED )
904		PORT_DIPNAME( 0x04, 0x04, "Floppy type")
905		PORT_DIPSETTING(    0x00, "80 tracks" )
906		PORT_DIPSETTING(    0x04, "40 tracks" )
907		PORT_DIPNAME( 0x02, 0x00, "8087 installed")
908		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
909		PORT_DIPSETTING(    0x02, DEF_STR( Yes ) )
910		PORT_DIPNAME( 0x01, 0x01, "Boot from floppy")
911		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
912		PORT_DIPSETTING(    0x01, DEF_STR( Yes ) )
913
914		//  PORT_START("DSW1") /* SA2 */
915
916		PORT_INCLUDE( pcvideo_cga )
917		INPUT_PORTS_END
918
919
920
921	740	static const pc_lpt_interface pc_lpt_config =
922	741	{
923	742	DEVCB_CPU_INPUT_LINE("maincpu", 0)
r26688	r26689
940	759	SLOT_INTERFACE( "525ssqd", FLOPPY_525_SSQD )
941	760	SLOT_INTERFACE_END
942	761
943		static SLOT_INTERFACE_START( mc1502_floppies )
944		SLOT_INTERFACE( "525qd", FLOPPY_525_QD )
945		SLOT_INTERFACE_END
946
947	762	static SLOT_INTERFACE_START(ibm5150_com)
948	763	SLOT_INTERFACE("microsoft_mouse", MSFT_SERIAL_MOUSE)
949	764	SLOT_INTERFACE("mouse_systems_mouse", MSYSTEM_SERIAL_MOUSE)
r26688	r26689
1481	1296	NULL
1482	1297	};
1483	1298
1484		static const serial_image_interface mc1502_serial =
1485		{
1486		9600, 8, 1, device_serial_interface::PARITY_NONE, 1, "upd8251"
1487		};
1488
1489	1299	static MACHINE_CONFIG_START( ibmpcjr, tandy_pc_state )
1490	1300	/* basic machine hardware */
1491	1301	MCFG_CPU_ADD("maincpu", I8088, 4900000)   \
r26688	r26689
1586	1396	MACHINE_CONFIG_END
1587	1397
1588	1398
1589		static MACHINE_CONFIG_START( mc1502, pc_state )
	1399	static MACHINE_CONFIG_START( asst128, pc_state )
1590	1400	/* basic machine hardware */
1591		MCFG_CPU_ADD("maincpu", I8088, XTAL_16MHz/3)
1592		MCFG_CPU_PROGRAM_MAP(mc1502_map)
1593		MCFG_CPU_IO_MAP(mc1502_io)
	1401	MCFG_CPU_PC(asst128, asst128, I8086, 4772720, pc_frame_interrupt)
1594	1402
1595		MCFG_MACHINE_START_OVERRIDE(pc_state,mc1502)
1596		MCFG_MACHINE_RESET_OVERRIDE(pc_state,pc)
1597
1598		MCFG_PIT8253_ADD( "pit8253", mc1502_pit8253_config )
1599
1600		MCFG_PIC8259_ADD( "pic8259", INPUTLINE("maincpu", 0), VCC, NULL )
1601
1602		MCFG_I8255_ADD( "ppi8255", mc1502_ppi8255_interface )       /* not complete */
1603		MCFG_I8255_ADD( "ppi8255n2", mc1502_ppi8255_interface_2 )   /* not complete */
1604
1605		MCFG_I8251_ADD( "upd8251", mc1502_i8251_interface )
1606		MCFG_SERIAL_ADD("irps", mc1502_serial)
1607
1608		/* video hardware (only 1 chargen in ROM; CGA_FONT dip always 1 */
1609		MCFG_FRAGMENT_ADD( pcvideo_mc1502 )
1610		MCFG_GFXDECODE(ibmpcjr)
1611
1612		/* sound hardware */
1613		MCFG_SPEAKER_STANDARD_MONO("mono")
1614		MCFG_SOUND_WAVE_ADD(WAVE_TAG, "cassette")
1615		MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
1616		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80)
1617
1618		MCFG_CENTRONICS_PRINTER_ADD("centronics", standard_centronics)
1619		MCFG_CASSETTE_ADD( "cassette", mc1502_cassette_interface )
1620
1621		MCFG_FD1793x_ADD("vg93", XTAL_16MHz / 16)
1622		MCFG_FLOPPY_DRIVE_ADD("fd0", mc1502_floppies, "525qd", pc_state::floppy_formats)
1623		MCFG_FLOPPY_DRIVE_ADD("fd1", mc1502_floppies, "525qd", pc_state::floppy_formats)
1624
1625		MCFG_SOFTWARE_LIST_ADD("flop_list","mc1502_flop")
1626		//  MCFG_SOFTWARE_LIST_ADD("cass_list","mc1502_cass")
1627
1628		/* internal ram */
1629		MCFG_RAM_ADD(RAM_TAG)
1630		MCFG_RAM_DEFAULT_SIZE("608K")                   /* 96 base + 512 on expansion card */
1631		MACHINE_CONFIG_END
1632
1633
1634		static MACHINE_CONFIG_START( ec1841, pc_state )
1635		/* basic machine hardware */
1636		MCFG_CPU_PC(ec1841, ec1841, I8086, 4096000, pc_frame_interrupt) // correct but slow
1637		//  MCFG_CPU_PC(ec1841, ec1841, I8086, 4772720, pc_frame_interrupt)
1638
1639	1403	MCFG_QUANTUM_TIME(attotime::from_hz(60))
1640	1404
1641	1405	MCFG_MACHINE_START_OVERRIDE(pc_state,pc)
1642	1406	MCFG_MACHINE_RESET_OVERRIDE(pc_state,pc)
1643	1407
1644		MCFG_PIT8253_ADD( "pit8253", ibm5150_pit8253_config )
	1408	MCFG_PIT8253_ADD( "pit8253", pcjr_pit8253_config )
1645	1409
1646		// maybe XTAL_12_288MHz
1647		MCFG_I8237_ADD( "dma8237", XTAL_14_31818MHz/3, ibm5150_dma8237_config )
1648
1649	1410	MCFG_PIC8259_ADD( "pic8259", INPUTLINE("maincpu", 0), VCC, NULL )
1650	1411
1651	1412	MCFG_I8255_ADD( "ppi8255", ibm5160_ppi8255_interface )
1652	1413
1653		//  MCFG_I8251_ADD( "upd8251_0", default_i8251_interface )  // modeled after BSC adapter?
1654		//  MCFG_I8251_ADD( "upd8251_1", default_i8251_interface )
1655
1656		/* video hardware -- supports font uploads */
1657		MCFG_FRAGMENT_ADD( pcvideo_cga )
1658		MCFG_GFXDECODE(ibm5150)
1659
1660		/* sound hardware */
1661		MCFG_SPEAKER_STANDARD_MONO("mono")
1662		MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
1663		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80)
1664
1665		/* printer */
1666		MCFG_PC_LPT_ADD("lpt_0", pc_lpt_config)
1667
1668		MCFG_PC_FDC_XT_ADD("fdc")
1669
1670		MCFG_FLOPPY_DRIVE_ADD("fdc:0", ibmpc_floppies, "525dd", pc_state::floppy_formats)
1671		MCFG_FLOPPY_DRIVE_ADD("fdc:1", ibmpc_floppies, "525dd", pc_state::floppy_formats)
1672
1673		MCFG_SOFTWARE_LIST_ADD("flop_list","ec1841")
1674
1675		MCFG_PC_KBDC_ADD("pc_kbdc", pc_kbdc_intf)
1676		MCFG_PC_KBDC_SLOT_ADD("pc_kbdc", "kbd", pc_xt_keyboards, STR_KBD_EC_1841)
1677
1678		/* internal ram -- up to 4 banks of 512K */
1679		MCFG_RAM_ADD(RAM_TAG)
1680		MCFG_RAM_DEFAULT_SIZE("512K")
1681		MCFG_RAM_EXTRA_OPTIONS("1024K,1576K,2048K")
1682		MACHINE_CONFIG_END
1683
1684
1685		static MACHINE_CONFIG_START( iskr1031, pc_state )
1686		/* basic machine hardware */
1687		MCFG_CPU_PC(iskr1031, iskr1031, I8086, 4772720, pc_frame_interrupt)
1688
1689		MCFG_QUANTUM_TIME(attotime::from_hz(60))
1690
1691		MCFG_MACHINE_START_OVERRIDE(pc_state,pc)
1692		MCFG_MACHINE_RESET_OVERRIDE(pc_state,pc)
1693
1694		MCFG_PIT8253_ADD( "pit8253", ibm5150_pit8253_config )
1695
1696		MCFG_I8237_ADD( "dma8237", XTAL_14_31818MHz/3, ibm5150_dma8237_config )
1697
1698		MCFG_PIC8259_ADD( "pic8259", INPUTLINE("maincpu", 0), VCC, NULL )
1699
1700		MCFG_I8255_ADD( "ppi8255", ibm5160_ppi8255_interface )
1701
1702		MCFG_INS8250_ADD( "ins8250_0", ibm5150_com_interface[0], XTAL_1_8432MHz )   /* TODO: Verify model */
1703		MCFG_INS8250_ADD( "ins8250_1", ibm5150_com_interface[1], XTAL_1_8432MHz )   /* TODO: Verify model */
1704		MCFG_INS8250_ADD( "ins8250_2", ibm5150_com_interface[2], XTAL_1_8432MHz )   /* TODO: Verify model */
1705		MCFG_INS8250_ADD( "ins8250_3", ibm5150_com_interface[3], XTAL_1_8432MHz )   /* TODO: Verify model */
1706
1707		MCFG_RS232_PORT_ADD( "serport0", ibm5150_com, NULL )
1708		MCFG_SERIAL_OUT_RX_HANDLER(DEVWRITELINE("ins8250_0", ins8250_uart_device, rx_w))
1709		MCFG_RS232_OUT_DCD_HANDLER(DEVWRITELINE("ins8250_0", ins8250_uart_device, dcd_w))
1710		MCFG_RS232_OUT_DSR_HANDLER(DEVWRITELINE("ins8250_0", ins8250_uart_device, dsr_w))
1711		MCFG_RS232_OUT_RI_HANDLER(DEVWRITELINE("ins8250_0", ins8250_uart_device, ri_w))
1712		MCFG_RS232_OUT_CTS_HANDLER(DEVWRITELINE("ins8250_0", ins8250_uart_device, cts_w))
1713
1714		MCFG_RS232_PORT_ADD( "serport1", ibm5150_com, NULL )
1715		MCFG_SERIAL_OUT_RX_HANDLER(DEVWRITELINE("ins8250_1", ins8250_uart_device, rx_w))
1716		MCFG_RS232_OUT_DCD_HANDLER(DEVWRITELINE("ins8250_1", ins8250_uart_device, dcd_w))
1717		MCFG_RS232_OUT_DSR_HANDLER(DEVWRITELINE("ins8250_1", ins8250_uart_device, dsr_w))
1718		MCFG_RS232_OUT_RI_HANDLER(DEVWRITELINE("ins8250_1", ins8250_uart_device, ri_w))
1719		MCFG_RS232_OUT_CTS_HANDLER(DEVWRITELINE("ins8250_1", ins8250_uart_device, cts_w))
1720
1721		MCFG_RS232_PORT_ADD( "serport2", ibm5150_com, NULL )
1722		MCFG_SERIAL_OUT_RX_HANDLER(DEVWRITELINE("ins8250_2", ins8250_uart_device, rx_w))
1723		MCFG_RS232_OUT_DCD_HANDLER(DEVWRITELINE("ins8250_2", ins8250_uart_device, dcd_w))
1724		MCFG_RS232_OUT_DSR_HANDLER(DEVWRITELINE("ins8250_2", ins8250_uart_device, dsr_w))
1725		MCFG_RS232_OUT_RI_HANDLER(DEVWRITELINE("ins8250_2", ins8250_uart_device, ri_w))
1726		MCFG_RS232_OUT_CTS_HANDLER(DEVWRITELINE("ins8250_2", ins8250_uart_device, cts_w))
1727
1728		MCFG_RS232_PORT_ADD( "serport3", ibm5150_com, NULL )
1729		MCFG_SERIAL_OUT_RX_HANDLER(DEVWRITELINE("ins8250_3", ins8250_uart_device, rx_w))
1730		MCFG_RS232_OUT_DCD_HANDLER(DEVWRITELINE("ins8250_3", ins8250_uart_device, dcd_w))
1731		MCFG_RS232_OUT_DSR_HANDLER(DEVWRITELINE("ins8250_3", ins8250_uart_device, dsr_w))
1732		MCFG_RS232_OUT_RI_HANDLER(DEVWRITELINE("ins8250_3", ins8250_uart_device, ri_w))
1733		MCFG_RS232_OUT_CTS_HANDLER(DEVWRITELINE("ins8250_3", ins8250_uart_device, cts_w))
1734
1735	1414	/* video hardware */
1736		MCFG_FRAGMENT_ADD( pcvideo_cga )
1737		MCFG_GFXDECODE(ibm5150)
	1415	MCFG_FRAGMENT_ADD( pcvideo_mc1502 )
	1416	MCFG_GFXDECODE(ibmpcjr)
1738	1417
1739	1418	/* sound hardware */
1740	1419	MCFG_SPEAKER_STANDARD_MONO("mono")
r26688	r26689
1750	1429	MCFG_PC_LPT_ADD("lpt_1", pc_lpt_config)
1751	1430	MCFG_PC_LPT_ADD("lpt_2", pc_lpt_config)
1752	1431
	1432	MCFG_CASSETTE_ADD( "cassette", mc1502_cassette_interface )
	1433
1753	1434	MCFG_PC_FDC_XT_ADD("fdc")
1754	1435
1755		MCFG_FLOPPY_DRIVE_ADD("fdc:0", ibmpc_floppies, "525dd", pc_state::floppy_formats)
1756		MCFG_FLOPPY_DRIVE_ADD("fdc:1", ibmpc_floppies, "525dd", pc_state::floppy_formats)
	1436	MCFG_FLOPPY_DRIVE_ADD("fdc:0", asst128_floppies, "525ssqd", pc_state::asst128_formats)
	1437	MCFG_FLOPPY_DRIVE_ADD("fdc:1", asst128_floppies, "525ssqd", pc_state::asst128_formats)
1757	1438
1758	1439	/* internal ram */
1759	1440	MCFG_RAM_ADD(RAM_TAG)
1760	1441	MCFG_RAM_DEFAULT_SIZE("640K")
1761	1442	MACHINE_CONFIG_END
1762	1443
1763		static MACHINE_CONFIG_DERIVED( asst128, iskr1031 )
1764		MCFG_CPU_REPLACE("maincpu", I8086, 4772720)
1765		MCFG_CPU_PROGRAM_MAP(iskr1031_map)
1766		MCFG_CPU_IO_MAP(asst128_io)
1767
1768		MCFG_DEVICE_REMOVE("dma8237")
1769		MCFG_DEVICE_REMOVE("fdc:0")
1770		MCFG_DEVICE_REMOVE("fdc:1")
1771		MCFG_DEVICE_REMOVE("pit8253")
1772
1773		MCFG_PIT8253_ADD( "pit8253", pcjr_pit8253_config )
1774
1775		MCFG_FLOPPY_DRIVE_ADD("fdc:0", asst128_floppies, "525ssqd", pc_state::asst128_formats)
1776		MCFG_FLOPPY_DRIVE_ADD("fdc:1", asst128_floppies, "525ssqd", pc_state::asst128_formats)
1777
1778		MCFG_DEVICE_REMOVE(CGA_SCREEN_NAME)
1779		MCFG_DEVICE_REMOVE(CGA_MC6845_NAME)
1780
1781		MCFG_FRAGMENT_ADD( pcvideo_mc1502 )
1782		MCFG_GFXDECODE(ibmpcjr)
1783		MACHINE_CONFIG_END
1784
1785	1444	static MACHINE_CONFIG_START( iskr3104, pc_state )
1786	1445	/* basic machine hardware */
1787	1446	MCFG_CPU_PC(pc16, pc16, I8086, 4772720, pc_frame_interrupt)
r26688	r26689
2486	2145	ROM_LOAD("5788005.u33", 0x00000, 0x2000, CRC(0bf56d70) SHA1(c2a8b10808bf51a3c123ba3eb1e9dd608231916f)) /* "AMI 8412PI // 5788005 // (C) IBM CORP. 1981 // KOREA" */
2487	2146	ROM_END
2488	2147
2489		ROM_START( iskr1031 )
2490		ROM_REGION16_LE(0x100000,"maincpu", 0)
2491		ROM_SYSTEM_BIOS(0, "v1", "v1")
2492		ROMX_LOAD( "150-02.bin", 0xfc000, 0x2000, CRC(e33fb974) SHA1(f5f3ece67c025c0033716ff516e1a34fbeb32749), ROM_SKIP(1) | ROM_BIOS(1))
2493		ROMX_LOAD( "150-03.bin", 0xfc001, 0x2000, CRC(8c482258) SHA1(90ef48955e0df556dc06a000a797ef42ccf430c5), ROM_SKIP(1) | ROM_BIOS(1))
2494		ROM_SYSTEM_BIOS(1, "v2", "v2")
2495		ROMX_LOAD( "150-06.bin", 0xfc000, 0x2000, CRC(1adbf969) SHA1(08c0a0fc50a75e6207b1987bae389cca60893eac), ROM_SKIP(1) | ROM_BIOS(2))
2496		ROMX_LOAD( "150-07.bin", 0xfc001, 0x2000, CRC(0dc4b65a) SHA1(c96f066251a7343eac8113ea9dcb2cb12d0334d5), ROM_SKIP(1) | ROM_BIOS(2))
2497
2498		ROM_REGION(0x2000,"gfx1", 0)
2499		ROM_LOAD( "iskra-1031_font.bin", 0x0000, 0x2000, CRC(f4d62e80) SHA1(ad7e81a0c9abc224671422bbcf6f6262da92b510))
2500		ROM_END
2501
2502		ROM_START( iskr1030m )
2503		ROM_REGION16_LE(0x100000,"maincpu", 0)
2504		ROMX_LOAD( "iskra-1030m_0.rom", 0xfc000, 0x2000, CRC(0d698e19) SHA1(2fe117c9f4f8c4b59085d5a41f919d743c425fdd), ROM_SKIP(1))
2505		ROMX_LOAD( "iskra-1030m_1.rom", 0xfc001, 0x2000, CRC(fe808337) SHA1(b0b7ebe14324ada8aa9a6926a82b18e80f78a257), ROM_SKIP(1))
2506		ROM_REGION(0x2000,"gfx1", 0)
2507		ROM_LOAD( "iskra-1030m.chr", 0x0000, 0x2000, CRC(50b162eb) SHA1(5bd7cb1705a69bd16115a4c9ed1c2748a5c8ad51))
2508		ROM_END
2509
2510		ROM_START( ec1840 )
2511		ROM_REGION16_LE(0x100000,"maincpu", 0)
2512		ROM_SYSTEM_BIOS(0, "v4", "EC-1840.04")
2513		ROMX_LOAD( "000-04-971b.bin", 0xfe000, 0x0800, CRC(06aeaee8) SHA1(9f954e4c48156d573a8e0109e7ca652be9e6036a), ROM_SKIP(1) | ROM_BIOS(1))
2514		ROMX_LOAD( "001-04-92b7.bin", 0xff000, 0x0800, CRC(3fae650a) SHA1(c98b777fdeceadd72d6eb9465b3501b9ead55a08), ROM_SKIP(1) | ROM_BIOS(1))
2515		ROMX_LOAD( "002-04-9e17.bin", 0xfe001, 0x0800, CRC(d59712df) SHA1(02ea1b3ae9662f5c64c58920a32ca9db0f6fbd12), ROM_SKIP(1) | ROM_BIOS(1))
2516		ROMX_LOAD( "003-04-3ccb.bin", 0xff001, 0x0800, CRC(7fc362c7) SHA1(538e13639ad2b4c30bd72582e323181e63513306), ROM_SKIP(1) | ROM_BIOS(1))
2517
2518		ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
2519		ROM_END
2520
2521		ROM_START( ec1841 )
2522		ROM_REGION16_LE(0x100000,"maincpu", 0)
2523		ROM_DEFAULT_BIOS("v2")
2524		ROM_SYSTEM_BIOS(0, "v1", "EC-1841.01")
2525		ROMX_LOAD( "012-01-3107.bin", 0xfc000, 0x0800, CRC(77957396) SHA1(785f1dceb6e2b4618f5c5f0af15eb74a8c951448), ROM_SKIP(1) | ROM_BIOS(1))
2526		ROMX_LOAD( "013-01-203f.bin", 0xfc001, 0x0800, CRC(768bd3d5) SHA1(2e948f2ad262de306d889b7964c3f1aad45ff5bc), ROM_SKIP(1) | ROM_BIOS(1))
2527		ROMX_LOAD( "014-01-fa40.bin", 0xfd000, 0x0800, CRC(47722b58) SHA1(a6339ee8af516f834826b7828a5cf79cb650480c), ROM_SKIP(1) | ROM_BIOS(1))
2528		ROMX_LOAD( "015-01-bf1d.bin", 0xfd001, 0x0800, CRC(b585b5ea) SHA1(d0ebed586eb13031477c2e071c50416682f80489), ROM_SKIP(1) | ROM_BIOS(1))
2529		ROMX_LOAD( "016-01-65f7.bin", 0xfe000, 0x0800, CRC(28a07db4) SHA1(17fbcd60dacd1d3f8d8355db429f97e4d1d1ac88), ROM_SKIP(1) | ROM_BIOS(1))
2530		ROMX_LOAD( "017-01-5be1.bin", 0xfe001, 0x0800, CRC(928bda26) SHA1(ee889184067e2680b29a8ef1c3a76cf5afd4c78d), ROM_SKIP(1) | ROM_BIOS(1))
2531		ROMX_LOAD( "018-01-7090.bin", 0xff000, 0x0800, CRC(75ca7d7e) SHA1(6356426820c5326a7893a437d54b02f250ef8609), ROM_SKIP(1) | ROM_BIOS(1))
2532		ROMX_LOAD( "019-01-0492.bin", 0xff001, 0x0800, CRC(8a9d593e) SHA1(f3936d2cb4e6d130dd732973f126c3aa20612463), ROM_SKIP(1) | ROM_BIOS(1))
2533
2534		ROM_SYSTEM_BIOS(1, "v2", "EC-1841.02")
2535		ROMX_LOAD( "012-02-37f6.bin", 0xfc000, 0x0800, CRC(8f5c6a20) SHA1(874b62f9cee8d3b974f33732f94eff10fc002c44), ROM_SKIP(1) | ROM_BIOS(2))
2536		ROMX_LOAD( "013-02-2552.bin", 0xfc001, 0x0800, CRC(e3c10128) SHA1(d6ed743ebe9c130925c9f17aad1a45db9194c967), ROM_SKIP(1) | ROM_BIOS(2))
2537		ROMX_LOAD( "014-02-0fbe.bin", 0xfd000, 0x0800, CRC(f8517e5e) SHA1(8034cd6ff5778365dc9daa494524f1753a74f1ed), ROM_SKIP(1) | ROM_BIOS(2))
2538		ROMX_LOAD( "015-02-d736.bin", 0xfd001, 0x0800, CRC(8538c52a) SHA1(ee981ce90870b6546a18f2a2e64d71b0038ce0dd), ROM_SKIP(1) | ROM_BIOS(2))
2539		ROMX_LOAD( "016-02-5b2c.bin", 0xfe000, 0x0800, CRC(3d1d1e67) SHA1(c527e29796537787c0f6c329f3c203f6131ca77f), ROM_SKIP(1) | ROM_BIOS(2))
2540		ROMX_LOAD( "017-02-4b9d.bin", 0xfe001, 0x0800, CRC(1b985264) SHA1(5ddcb9c13564be208c5068c105444a87159c67ee), ROM_SKIP(1) | ROM_BIOS(2))
2541		ROMX_LOAD( "018-02-7090.bin", 0xff000, 0x0800, CRC(75ca7d7e) SHA1(6356426820c5326a7893a437d54b02f250ef8609), ROM_SKIP(1) | ROM_BIOS(2))
2542		ROMX_LOAD( "019-02-0493.bin", 0xff001, 0x0800, CRC(61aae23d) SHA1(7b3aa24a63ee31b194297eb1e61c3827edfcb95a), ROM_SKIP(1) | ROM_BIOS(2))
2543
2544		ROM_SYSTEM_BIOS(2, "v3", "EC-1841.03")
2545		ROMX_LOAD( "012-03-37e7.bin", 0xfc000, 0x0800, CRC(49992bd5) SHA1(119121e1b4af1c44b9b8c2edabe7dc1d3019c4a6), ROM_SKIP(1) | ROM_BIOS(3))
2546		ROMX_LOAD( "013-03-2554.bin", 0xfc001, 0x0800, CRC(834bd7d7) SHA1(e37514fc4cb8a5cbe68e7564e0e07d5116c4021a), ROM_SKIP(1) | ROM_BIOS(3))
2547		ROMX_LOAD( "014-03-0fbe.bin", 0xfd000, 0x0800, CRC(f8517e5e) SHA1(8034cd6ff5778365dc9daa494524f1753a74f1ed), ROM_SKIP(1) | ROM_BIOS(3))
2548		ROMX_LOAD( "015-03-d736.bin", 0xfd001, 0x0800, CRC(8538c52a) SHA1(ee981ce90870b6546a18f2a2e64d71b0038ce0dd), ROM_SKIP(1) | ROM_BIOS(3))
2549		ROMX_LOAD( "016-03-5b2c.bin", 0xfe000, 0x0800, CRC(3d1d1e67) SHA1(c527e29796537787c0f6c329f3c203f6131ca77f), ROM_SKIP(1) | ROM_BIOS(3))
2550		ROMX_LOAD( "017-03-4b9d.bin", 0xfe001, 0x0800, CRC(1b985264) SHA1(5ddcb9c13564be208c5068c105444a87159c67ee), ROM_SKIP(1) | ROM_BIOS(3))
2551		ROMX_LOAD( "018-03-7090.bin", 0xff000, 0x0800, CRC(75ca7d7e) SHA1(6356426820c5326a7893a437d54b02f250ef8609), ROM_SKIP(1) | ROM_BIOS(3))
2552		ROMX_LOAD( "019-03-0493.bin", 0xff001, 0x0800, CRC(61aae23d) SHA1(7b3aa24a63ee31b194297eb1e61c3827edfcb95a), ROM_SKIP(1) | ROM_BIOS(3))
2553
2554		ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
2555		ROM_END
2556
2557		ROM_START( ec1845 )
2558		ROM_REGION16_LE(0x100000,"maincpu", 0)
2559		ROMX_LOAD( "184500.bin", 0xfc000, 0x0800, CRC(7c472ef7) SHA1(3af53f27b49bbc731bf51f9300fbada23a1bfcfc), ROM_SKIP(1))
2560		ROMX_LOAD( "184501.bin", 0xfc001, 0x0800, CRC(db240dc6) SHA1(d7bb022213d09bbf2a8107fe4f1cd27b23939e18), ROM_SKIP(1))
2561		ROMX_LOAD( "184502.bin", 0xfd000, 0x0800, CRC(149e7e29) SHA1(7f2a297588fef1bc750c57e6ae0d5acf3d27c486), ROM_SKIP(1))
2562		ROMX_LOAD( "184503.bin", 0xfd001, 0x0800, CRC(e28cbd74) SHA1(cf1fba4e67c8e1dd8cdda547118e84b704029b03), ROM_SKIP(1))
2563		ROMX_LOAD( "184504.bin", 0xfe000, 0x0800, CRC(55fa7a1d) SHA1(58f7abab08b9d2f0a1c1636e11bb72af2694c95f), ROM_SKIP(1))
2564		ROMX_LOAD( "184505.bin", 0xfe001, 0x0800, CRC(c807e3f5) SHA1(08117e449f0d04f96041cff8d34893f500f3760d), ROM_SKIP(1))
2565		ROMX_LOAD( "184506.bin", 0xff000, 0x0800, CRC(24f5c27c) SHA1(7822dd7f715ef00ccf6d8408be8bbfe01c2eba20), ROM_SKIP(1))
2566		ROMX_LOAD( "184507.bin", 0xff001, 0x0800, CRC(75122203) SHA1(7b0fbdf1315230633e39574ac7360163bc7361e1), ROM_SKIP(1))
2567		ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
2568		ROM_END
2569
2570	2148	ROM_START( asst128 )
2571	2149	ROM_REGION16_LE(0x100000,"maincpu", 0)
	2150	ROM_DEFAULT_BIOS("floppy")
2572	2151	/* BASIC ROM taken from IBM 5150 and needs dumping */
2573	2152	ROM_LOAD( "basic-1.10.rom",    0xf6000, 0x8000, CRC(ebacb791) SHA1(07449ebca18f979b9ab748582b736e402f2bf940))
2574	2153	ROM_LOAD( "asf400-f600.bin",   0xf4000, 0x2000, CRC(e3bf22de) SHA1(d4319edc82c0015ca0adc6c8771e887659717e62))
2575		ROM_LOAD( "asfc00-ff00.bin",   0xfc000, 0x4000, CRC(0cb6401c) SHA1(70c4da47700f9925fd04049f16d54610c743ed8b))
	2154	ROM_SYSTEM_BIOS(0, "floppy", "3rd party floppy support")
	2155	ROMX_LOAD( "rombios7.bin",     0xfc001, 0x2000, CRC(7d7c8d6a) SHA1(a731a65ee547f1d78cfc91461f38166da014f3dc), ROM_SKIP(1) | ROM_BIOS(1))
	2156	ROMX_LOAD( "rombios8.bin",     0xfc000, 0x2000, CRC(ba304663) SHA1(b2533b8f8240f72b7315f27c7b64f95ac52687ca), ROM_SKIP(1) | ROM_BIOS(1))
	2157	ROM_SYSTEM_BIOS(1, "stock", "cassette-only BIOS?")
	2158	ROMX_LOAD( "mainbios.bin",     0xfe000, 0x2000, CRC(8426cbf5) SHA1(41d14137ffa651977041da22aa8071c0f7854158), ROM_BIOS(2))
2576	2159	ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
2577	2160	ROM_COPY( "maincpu", 0xffa6e, 0x0800, 0x0400 )
2578	2161	ROM_COPY( "maincpu", 0xfc000, 0x0c00, 0x0400 )
r26688	r26689
2605	2188	ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
2606	2189	ROM_END
2607	2190
2608		ROM_START( poisk1 )
2609		ROM_REGION16_LE(0x100000,"maincpu", 0)
2610		ROM_LOAD( "b_hd_v11.rf2", 0xc8000, 0x0800, CRC(a19c39b2) SHA1(57faa56b320abf801fedbed578cf97d253e5b777)) // HDD controller ver 1.1
2611		ROM_LOAD( "b942_5mb.bin", 0x00000, 0x0800, CRC(a3cfa240) SHA1(0b0aa1ce839a957153bfbbe70310480ca9fe21b6)) // HDD controller ver 1.4
2612
2613		ROM_LOAD( "b_ngmd_n.rf2", 0x0000, 0x0800, CRC(967e172a) SHA1(95117c40fd9f624fee08ccf37f615b16ff249688)) // Floppy
2614		ROM_LOAD( "b_ngmd_t.rf2", 0x0000, 0x0800, CRC(630010b1) SHA1(50876fe4f5f4f32a242faa70f9154574cd315ec4)) // Floppy
2615		ROM_SYSTEM_BIOS(0, "v89", "1989")
2616		ROMX_LOAD( "biosp1s.rf4",    0xfe000, 0x2000, CRC(1a85f671) SHA1(f0e59b2c4d92164abca55a96a58071ce869ff988), ROM_BIOS(1)) // Main BIOS
2617		ROM_SYSTEM_BIOS(1, "v91", "1991")
2618		ROMX_LOAD( "poisk_1991.bin", 0xfe000, 0x2000, CRC(d61c56fd) SHA1(de202e1f7422d585a1385a002a4fcf9d756236e5), ROM_BIOS(2))
2619		ROM_SYSTEM_BIOS(2, "t1", "Test I/O")
2620		ROMX_LOAD( "p1_t_i_o.rf4", 0xfe000, 0x2000, CRC(18a781de) SHA1(7267970ee27e3ea1d972bee8e74b17bac1051619), ROM_BIOS(3))
2621		ROM_SYSTEM_BIOS(3, "t2", "Test MB")
2622		ROMX_LOAD( "p1_t_pls.rf4", 0xfe000, 0x2000, CRC(c8210ffb) SHA1(f2d1a6c90e4708bcc56186b2fb906fa852667084), ROM_BIOS(4))
2623		ROM_SYSTEM_BIOS(4, "t3", "Test RAM")
2624		ROMX_LOAD( "p1_t_ram.rf4", 0xfe000, 0x2000, CRC(e42f5a61) SHA1(ce2554eae8f0d2b6d482890dd198cf7e2d29c655), ROM_BIOS(5))
2625
2626		ROM_LOAD( "boot_net.rf4", 0x0000, 0x2000, CRC(316c2030) SHA1(d043325596455772252e465b85321f1b5c529d0b)) // NET BUIS
2627		ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
2628		ROM_LOAD( "poisk.cga", 0x0000, 0x0800, CRC(f6eb39f0) SHA1(0b788d8d7a8e92cc612d044abcb2523ad964c200))
2629		ROM_END
2630
2631	2191	ROM_START( poisk2 )
2632	2192	ROM_REGION16_LE(0x100000,"maincpu", 0)
2633	2193	ROM_SYSTEM_BIOS(0, "v20", "v2.0")
r26688	r26689
2664	2224	ROM_END
2665	2225
2666	2226
2667		ROM_START( mc1502 )
2668		ROM_REGION16_LE(0x100000,"maincpu", 0)
2669		ROM_DEFAULT_BIOS("v52")
2670		ROM_LOAD( "basic.rom",        0xe8000, 0x8000, CRC(173d69fa) SHA1(003f872e12f00800e22ab6bbc009d36bfde67b9d))
2671		ROM_SYSTEM_BIOS(0, "v50", "v5.0")
2672		ROMX_LOAD( "monitor_5_0.rom",  0xfc000, 0x4000, CRC(9e97c6a0) SHA1(16a304e8de69ec4d8b92acda6bf28454c361a24f),ROM_BIOS(1))
2673		ROM_SYSTEM_BIOS(1, "v52", "v5.2")
2674		ROMX_LOAD( "monitor_5_2.rom",  0xfc000, 0x4000, CRC(0e65491e) SHA1(8a4d556473b5e0e59b05fab77c79c29f4d562412),ROM_BIOS(2))
2675		ROM_SYSTEM_BIOS(2, "v531", "v5.31")
2676		ROMX_LOAD( "monitor_5_31.rom", 0xfc000, 0x4000, CRC(a48295d5) SHA1(6f38977c22f9cc6c2bc6f6e53edc4048ca6b6721),ROM_BIOS(3))
2677		ROM_SYSTEM_BIOS(3, "v533", "v5.33")
2678		ROMX_LOAD( "0_(cbc0).bin", 0xfc000, 0x2000, CRC(9a55bc4f) SHA1(81da44eec2e52cf04b1fc7053502270f51270590),ROM_BIOS(4))
2679		ROMX_LOAD( "1_(dfe2).bin", 0xfe000, 0x2000, CRC(8dec077a) SHA1(d6f6d7cc2183abc77fbd9cd59132de5766f7c458),ROM_BIOS(4))
2680		ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
2681		ROM_LOAD( "symgen.rom", 0x0000, 0x2000, CRC(b2747a52) SHA1(6766d275467672436e91ac2997ac6b77700eba1e))
2682		ROM_END
2683
2684	2227	ROM_START( m24 )
2685	2228	ROM_REGION16_LE(0x100000,"maincpu", 0)
2686	2229	ROMX_LOAD("olivetti_m24_version_1.43_high.bin",0xfc001, 0x2000, CRC(04e697ba) SHA1(1066dcc849e6289b5ac6372c84a590e456d497a6), ROM_SKIP(1))
r26688	r26689
2827	2370	COMP( 1989, t1000tl2,   ibm5150,    0,          t1000_286,  tandy1t, tandy_pc_state,    t1000hx,    "Tandy Radio Shack", "Tandy 1000 TL/2", 0)
2828	2371	COMP( 1988, t1000sl2,   ibm5150,    0,          t1000_16_8, tandy1t, tandy_pc_state,    t1000sl,    "Tandy Radio Shack", "Tandy 1000 SL/2", GAME_NOT_WORKING)
2829	2372
2830		COMP( 1989, iskr1031,   ibm5150,    0,          iskr1031,   pccga, pc_state,      pccga,      "Schetmash", "Iskra 1031", GAME_NOT_WORKING)
2831		COMP( 1989, iskr1030m,  ibm5150,    0,          iskr1031,   pccga, pc_state,      pccga,      "Schetmash", "Iskra 1030M", GAME_NOT_WORKING)
2832	2373	COMP( 1992, iskr3104,   ibm5150,    0,          iskr3104,   pcega, pc_state,      pccga,      "Schetmash", "Iskra 3104", GAME_NOT_WORKING)
2833	2374	COMP( 198?, asst128,    ibm5150,    0,          asst128,    pccga, pc_state,      pccga,      "Schetmash", "Assistent 128", GAME_NOT_WORKING)
2834		COMP( 1987, ec1840,     ibm5150,    0,          iskr1031,   pccga, pc_state,      pccga,      "<unknown>", "EC-1840", GAME_NOT_WORKING)
2835		COMP( 1987, ec1841,     ibm5150,    0,          ec1841,     ec1841, pc_state,     ec1841,     "<unknown>", "EC-1841", GAME_NOT_WORKING)
2836		COMP( 1989, ec1845,     ibm5150,    0,          iskr1031,   pccga, pc_state,      pccga,      "<unknown>", "EC-1845", GAME_NOT_WORKING)
2837		COMP( 1989, mk88,       ibm5150,    0,          iskr1031,   pccga, pc_state,      pccga,      "<unknown>", "MK-88", GAME_NOT_WORKING)
2838		COMP( 1990, poisk1,     ibm5150,    0,          iskr1031,   pccga, pc_state,      pccga,      "<unknown>", "Poisk-1", GAME_NOT_WORKING)
	2375	COMP( 1989, mk88,       ibm5150,    0,          iskr3104,   pccga, pc_state,      pccga,      "<unknown>", "MK-88", GAME_NOT_WORKING)
2839	2376	COMP( 1991, poisk2,     ibm5150,    0,          poisk2,     pccga, pc_state,      pccga,      "<unknown>", "Poisk-2", GAME_NOT_WORKING)
2840	2377	COMP( 1990, mc1702,     ibm5150,    0,          pccga,      pccga, pc_state,      pccga,      "<unknown>", "Elektronika MC-1702", GAME_NOT_WORKING)
2841		COMP( 1989, mc1502,     ibm5150,    0,          mc1502,     mc1502, pc_state,     mc1502,     "NPO Microprocessor", "Elektronika MC-1502", GAME_NOT_WORKING | GAME_NO_SOUND)
2842	2378
2843	2379	COMP( 1987, zdsupers,   ibm5150,    0,          zenith,     pccga, pc_state,      pccga,      "Zenith Data Systems", "SuperSport", 0)
2844	2380

trunk/src/mess/drivers/mc1502.c

r0	r26689
	1	/***************************************************************************
	2
	3	drivers/mc1502.c
	4
	5	Driver file for Electronika MC 1502
	6
	7	***************************************************************************/
	8
	9	#include "emu.h"
	10
	11	#include "includes/mc1502.h"
	12
	13	#include "cpu/i86/i86.h"
	14	#include "imagedev/serial.h"
	15	#include "machine/kb_7007_3.h"
	16	#include "sound/speaker.h"
	17	#include "sound/wave.h"
	18	#include "video/pc_cga.h"
	19
	20	#define VERBOSE_DBG 0
	21
	22	#define DBG_LOG(N,M,A) \
	23	do { \
	24	if(VERBOSE_DBG>=N) \
	25	{ \
	26	if( M ) \
	27	logerror("%11.6f: %-24s",machine().time().as_double(),(char*)M ); \
	28	logerror A; \
	29	} \
	30	} while (0)
	31
	32	/*
	33	* onboard devices:
	34	*/
	35
	36	static const cassette_interface mc1502_cassette_interface =
	37	{
	38	cassette_default_formats,
	39	NULL,
	40	(cassette_state)(CASSETTE_STOPPED | CASSETTE_MOTOR_ENABLED | CASSETTE_SPEAKER_ENABLED),
	41	NULL,
	42	NULL
	43	};
	44
	45	static const serial_image_interface mc1502_serial =
	46	{
	47	9600, 8, 1, device_serial_interface::PARITY_NONE, 1, "upd8251"
	48	};
	49
	50	// Timer
	51
	52	static const isa8bus_interface mc1502_isabus_intf =
	53	{
	54	// interrupts
	55	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir2_w),
	56	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir3_w),
	57	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir4_w),
	58	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir5_w),
	59	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir6_w),
	60	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir7_w),
	61
	62	// dma request
	63	DEVCB_NULL,
	64	DEVCB_NULL,
	65	DEVCB_NULL,
	66	};
	67
	68	/* check if any keys are pressed, raise IRQ1 if so */
	69
	70	TIMER_CALLBACK_MEMBER(mc1502_state::keyb_signal_callback)
	71	{
	72	UINT8 key = 0;
	73
	74	key |= ioport("Y1")->read();
	75	key |= ioport("Y2")->read();
	76	key |= ioport("Y3")->read();
	77	key |= ioport("Y4")->read();
	78	key |= ioport("Y5")->read();
	79	key |= ioport("Y6")->read();
	80	key |= ioport("Y7")->read();
	81	key |= ioport("Y8")->read();
	82	key |= ioport("Y9")->read();
	83	key |= ioport("Y10")->read();
	84	key |= ioport("Y11")->read();
	85	key |= ioport("Y12")->read();
	86	//   DBG_LOG(1,"mc1502_k_s_c",("= %02X (%d) %s\n", key, m_kbd.pulsing,
	87	//         (key || m_kbd.pulsing) ? " will IRQ" : ""));
	88
	89	/*
	90	If a key is pressed and we're not pulsing yet, start pulsing the IRQ1;
	91	keep pulsing while any key is pressed, and pulse one time after all keys
	92	are released.
	93	*/
	94	if (key) {
	95	if (m_kbd.pulsing < 2) {
	96	m_kbd.pulsing += 2;
	97	}
	98	}
	99
	100	if (m_kbd.pulsing) {
	101	m_pic8259->ir1_w(m_kbd.pulsing & 1);
	102	m_kbd.pulsing--;
	103	}
	104	}
	105
	106	WRITE8_MEMBER(mc1502_state::mc1502_ppi_porta_w)
	107	{
	108	m_centronics->write(space, 0, data);
	109	}
	110
	111	WRITE8_MEMBER(mc1502_state::mc1502_ppi_portb_w)
	112	{
	113	//   DBG_LOG(2,"mc1502_ppi_portb_w",("( %02X )\n", data));
	114	m_ppi_portb = data;
	115	machine().device<pit8253_device>("pit8253")->gate2_w(BIT(data, 0));
	116	//   mc1502_speaker_set_spkrdata(BIT(data, 1));
	117	m_centronics->strobe_w(BIT(data, 2));
	118	m_centronics->autofeed_w(BIT(data, 3));
	119	m_centronics->init_prime_w(BIT(data, 4));
	120	}
	121
	122	// bit 0: parallel port data transfer direction (default = 0 = out)
	123	// bits 1-2: CGA_FONT (default = 01)
	124	// bit 3: i8251 SYNDET pin triggers NMI (default = 1 = no)
	125	WRITE8_MEMBER(mc1502_state::mc1502_ppi_portc_w)
	126	{
	127	//   DBG_LOG(2,"mc1502_ppi_portc_w",("( %02X )\n", data));
	128	m_ppi_portc = data & 15;
	129	}
	130
	131	READ8_MEMBER(mc1502_state::mc1502_kppi_portc_r)
	132	{
	133	UINT8 data = 0;
	134
	135	data |= m_centronics->fault_r() << 4;
	136	data |= m_centronics->pe_r() << 5;
	137	data |= m_centronics->ack_r() << 6;
	138	data |= m_centronics->busy_r() << 7;
	139
	140	return data;
	141	}
	142
	143	//  0x80 -- serial RxD
	144	//  0x40 -- CASS IN, also loops back T2OUT (gated by CASWR)
	145	//  0x20 -- T2OUT
	146	//  0x10 -- SNDOUT
	147	READ8_MEMBER(mc1502_state::mc1502_ppi_portc_r)
	148	{
	149	int timer2_output = machine().device<pit8253_device>("pit8253")->get_output(2);
	150	int data = 0xff;
	151	double tap_val = m_cassette->input();
	152
	153	data = ( data & ~0x40 ) | ( tap_val < 0 ? 0x40 : 0x00 ) | ( (BIT(m_ppi_portb, 7) && timer2_output) ? 0x40 : 0x00 );
	154	data = ( data & ~0x20 ) | ( timer2_output ? 0x20 : 0x00 );
	155	data = ( data & ~0x10 ) | ( (BIT(m_ppi_portb, 1) && timer2_output) ? 0x10 : 0x00 );
	156
	157	//   DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
	158	//         data, tap_val, timer2_output, machine().describe_context()));
	159	return data;
	160	}
	161
	162	READ8_MEMBER(mc1502_state::mc1502_kppi_porta_r)
	163	{
	164	UINT8 key = 0;
	165
	166	if (m_kbd.mask & 0x0001) { key |= ioport("Y1")->read(); }
	167	if (m_kbd.mask & 0x0002) { key |= ioport("Y2")->read(); }
	168	if (m_kbd.mask & 0x0004) { key |= ioport("Y3")->read(); }
	169	if (m_kbd.mask & 0x0008) { key |= ioport("Y4")->read(); }
	170	if (m_kbd.mask & 0x0010) { key |= ioport("Y5")->read(); }
	171	if (m_kbd.mask & 0x0020) { key |= ioport("Y6")->read(); }
	172	if (m_kbd.mask & 0x0040) { key |= ioport("Y7")->read(); }
	173	if (m_kbd.mask & 0x0080) { key |= ioport("Y8")->read(); }
	174	if (m_kbd.mask & 0x0100) { key |= ioport("Y9")->read(); }
	175	if (m_kbd.mask & 0x0200) { key |= ioport("Y10")->read(); }
	176	if (m_kbd.mask & 0x0400) { key |= ioport("Y11")->read(); }
	177	if (m_kbd.mask & 0x0800) { key |= ioport("Y12")->read(); }
	178	key ^= 0xff;
	179	//   DBG_LOG(2,"mc1502_kppi_porta_r",("= %02X\n", key));
	180	return key;
	181	}
	182
	183	WRITE8_MEMBER(mc1502_state::mc1502_kppi_portb_w)
	184	{
	185	m_kbd.mask &= ~255;
	186	m_kbd.mask |= data ^ 255;
	187	if (!BIT(data, 0))
	188	m_kbd.mask |= 1 << 11;
	189	else
	190	m_kbd.mask &= ~(1 << 11);
	191	//   DBG_LOG(2,"mc1502_kppi_portb_w",("( %02X -> %04X )\n", data, m_kbd.mask));
	192	}
	193
	194	WRITE8_MEMBER(mc1502_state::mc1502_kppi_portc_w)
	195	{
	196	m_kbd.mask &= ~(7 << 8);
	197	m_kbd.mask |= ((data ^ 7) & 7) << 8;
	198	//   DBG_LOG(2,"mc1502_kppi_portc_w",("( %02X -> %04X )\n", data, m_kbd.mask));
	199	}
	200
	201	I8255_INTERFACE( mc1502_ppi8255_interface_1 )
	202	{
	203	DEVCB_NULL,
	204	DEVCB_DRIVER_MEMBER(mc1502_state,mc1502_ppi_porta_w),
	205	DEVCB_NULL,
	206	DEVCB_DRIVER_MEMBER(mc1502_state,mc1502_ppi_portb_w),
	207	DEVCB_DRIVER_MEMBER(mc1502_state,mc1502_ppi_portc_r),
	208	DEVCB_DRIVER_MEMBER(mc1502_state,mc1502_ppi_portc_w)
	209	};
	210
	211	I8255_INTERFACE( mc1502_ppi8255_interface_2 )
	212	{
	213	DEVCB_DRIVER_MEMBER(mc1502_state,mc1502_kppi_porta_r),
	214	DEVCB_NULL,
	215	DEVCB_NULL,
	216	DEVCB_DRIVER_MEMBER(mc1502_state,mc1502_kppi_portb_w),
	217	DEVCB_DRIVER_MEMBER(mc1502_state,mc1502_kppi_portc_r),
	218	DEVCB_DRIVER_MEMBER(mc1502_state,mc1502_kppi_portc_w)
	219	};
	220
	221	const i8251_interface mc1502_i8251_interface =
	222	{
	223	/* XXX RxD data are accessible via PPI port C, bit 7 */
	224	DEVCB_NULL,
	225	DEVCB_NULL,
	226	DEVCB_NULL,
	227	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir7_w), /* default handler does nothing */
	228	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir7_w),
	229	DEVCB_NULL,
	230	DEVCB_DRIVER_LINE_MEMBER(mc1502_state, mc1502_i8251_syndet)
	231	};
	232
	233	WRITE_LINE_MEMBER(mc1502_state::mc1502_i8251_syndet)
	234	{
	235	if (!BIT(m_ppi_portc,3))
	236	machine().firstcpu->set_input_line(INPUT_LINE_NMI, state ? ASSERT_LINE : CLEAR_LINE);
	237	}
	238
	239	WRITE_LINE_MEMBER(mc1502_state::mc1502_pit8253_out1_changed)
	240	{
	241	machine().device<i8251_device>("upd8251")->txc_w(state);
	242	machine().device<i8251_device>("upd8251")->rxc_w(state);
	243	}
	244
	245	WRITE_LINE_MEMBER(mc1502_state::mc1502_pit8253_out2_changed)
	246	{
	247	//   mc1502_speaker_set_input( state );
	248	m_cassette->output(state ? 1 : -1);
	249	}
	250
	251	const struct pit8253_interface mc1502_pit8253_config =
	252	{
	253	{
	254	{
	255	XTAL_15MHz/12,              /* heartbeat IRQ */
	256	DEVCB_NULL,
	257	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir0_w)
	258	}, {
	259	XTAL_16MHz/12,              /* serial port */
	260	DEVCB_NULL,
	261	DEVCB_DRIVER_LINE_MEMBER(mc1502_state,mc1502_pit8253_out1_changed)
	262	}, {
	263	XTAL_16MHz/12,              /* pio port c pin 4, and speaker polling enough */
	264	DEVCB_NULL,
	265	DEVCB_DRIVER_LINE_MEMBER(mc1502_state,mc1502_pit8253_out2_changed)
	266	}
	267	}
	268	};
	269
	270	IRQ_CALLBACK_MEMBER( mc1502_state::mc1502_irq_callback )
	271	{
	272	return m_pic8259->acknowledge();
	273	}
	274
	275	DRIVER_INIT_MEMBER( mc1502_state, mc1502 )
	276	{
	277	address_space &program = m_maincpu->space(AS_PROGRAM);
	278
	279	DBG_LOG(0,"init",("driver_init()\n"));
	280
	281	program.unmap_readwrite(0, 0x7ffff);
	282	program.install_readwrite_bank(0, m_ram->size()-1, "bank10");
	283	membank( "bank10" )->set_base( m_ram->pointer() );
	284	}
	285
	286	MACHINE_START_MEMBER( mc1502_state, mc1502 )
	287	{
	288	DBG_LOG(0,"init",("machine_start()\n"));
	289
	290	m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(mc1502_state::mc1502_irq_callback),this));
	291	/*
	292	Keyboard polling circuit holds IRQ1 high until a key is
	293	pressed, then it starts a timer that pulses IRQ1 low each
	294	40ms (check) for 20ms (check) until all keys are released.
	295	Last pulse causes BIOS to write a 'break' scancode into port 60h.
	296	*/
	297	m_pic8259->ir1_w(1);
	298	memset(&m_kbd, 0, sizeof(m_kbd));
	299	m_kbd.keyb_signal_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc1502_state::keyb_signal_callback),this));
	300	m_kbd.keyb_signal_timer->adjust( attotime::from_msec(20), 0, attotime::from_msec(20) );
	301	}
	302
	303	MACHINE_RESET_MEMBER( mc1502_state, mc1502 )
	304	{
	305	DBG_LOG(0,"init",("machine_reset()\n"));
	306	}
	307
	308	/*
	309	* macros
	310	*/
	311
	312	static ADDRESS_MAP_START( mc1502_map, AS_PROGRAM, 8, mc1502_state )
	313	ADDRESS_MAP_UNMAP_HIGH
	314	AM_RANGE(0x00000, 0x97fff) AM_RAM   /* 96K on mainboard + 512K on extension card */
	315	AM_RANGE(0xc0000, 0xfbfff) AM_NOP
	316	//   AM_RANGE(0xe8000, 0xeffff) AM_ROM       /* BASIC */
	317	AM_RANGE(0xfc000, 0xfffff) AM_ROM
	318	ADDRESS_MAP_END
	319
	320	static ADDRESS_MAP_START( pk88_map, AS_PROGRAM, 8, mc1502_state )
	321	ADDRESS_MAP_UNMAP_HIGH
	322	AM_RANGE(0x00000, 0x1ffff) AM_RAMBANK("bank10") /* 96K on mainboard */
	323	AM_RANGE(0xf0000, 0xf7fff) AM_ROM       /* BASIC */
	324	AM_RANGE(0xfc000, 0xfffff) AM_ROM
	325	ADDRESS_MAP_END
	326
	327	static ADDRESS_MAP_START(mc1502_io, AS_IO, 8, mc1502_state )
	328	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE("pic8259", pic8259_device, read, write)
	329	AM_RANGE(0x0028, 0x0028) AM_DEVREADWRITE("upd8251", i8251_device, data_r, data_w)   // not working yet
	330	AM_RANGE(0x0029, 0x0029) AM_DEVREADWRITE("upd8251", i8251_device, status_r, control_w)
	331	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE("pit8253", pit8253_device, read, write)
	332	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE("ppi8255n1", i8255_device, read, write)
	333	AM_RANGE(0x0068, 0x006B) AM_DEVREADWRITE("ppi8255n2", i8255_device, read, write)    // keyboard poll
	334	ADDRESS_MAP_END
	335
	336	static INPUT_PORTS_START( mc1502 )
	337	PORT_START("IN0") /* IN0 */
	338	PORT_BIT ( 0xf0, 0xf0,   IPT_UNUSED )
	339	PORT_BIT ( 0x08, 0x08,   IPT_CUSTOM ) PORT_VBLANK("screen")
	340	PORT_BIT ( 0x07, 0x07,   IPT_UNUSED )
	341
	342	PORT_INCLUDE( mc7007_3_keyboard )
	343	PORT_INCLUDE( pcvideo_mc1502 )
	344	INPUT_PORTS_END
	345
	346	static MACHINE_CONFIG_START( mc1502, mc1502_state )
	347	/* basic machine hardware */
	348	MCFG_CPU_ADD("maincpu", I8088, XTAL_16MHz/3)
	349	MCFG_CPU_PROGRAM_MAP(mc1502_map)
	350	MCFG_CPU_IO_MAP(mc1502_io)
	351
	352	MCFG_MACHINE_START_OVERRIDE( mc1502_state, mc1502 )
	353	MCFG_MACHINE_RESET_OVERRIDE( mc1502_state, mc1502 )
	354
	355	MCFG_PIT8253_ADD( "pit8253", mc1502_pit8253_config )
	356
	357	MCFG_PIC8259_ADD( "pic8259", INPUTLINE("maincpu", 0), VCC, NULL )
	358
	359	MCFG_I8255_ADD( "ppi8255n1", mc1502_ppi8255_interface_1 )
	360	MCFG_I8255_ADD( "ppi8255n2", mc1502_ppi8255_interface_2 )
	361
	362	MCFG_I8251_ADD( "upd8251", mc1502_i8251_interface )
	363	MCFG_SERIAL_ADD( "irps", mc1502_serial )
	364
	365	MCFG_ISA8_BUS_ADD("isa", ":maincpu", mc1502_isabus_intf)
	366	MCFG_ISA8_SLOT_ADD("isa", "isa1", mc1502_isa8_cards, "fdc", false)
	367	MCFG_ISA8_SLOT_ADD("isa", "isa2", mc1502_isa8_cards, "rom", false)
	368
	369	/* video hardware (only 1 chargen in ROM; CGA_FONT dip always 1 */
	370	MCFG_FRAGMENT_ADD( pcvideo_mc1502 )
	371
	372	/* sound hardware */
	373	MCFG_SPEAKER_STANDARD_MONO("mono")
	374	MCFG_SOUND_WAVE_ADD(WAVE_TAG, "cassette")
	375	MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
	376	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80)
	377
	378	MCFG_CENTRONICS_PRINTER_ADD( "centronics", standard_centronics )
	379	MCFG_CASSETTE_ADD( "cassette", mc1502_cassette_interface )
	380
	381	MCFG_SOFTWARE_LIST_ADD("flop_list","mc1502_flop")
	382	//   MCFG_SOFTWARE_LIST_ADD("cass_list","mc1502_cass")
	383
	384	/* internal ram */
	385	MCFG_RAM_ADD(RAM_TAG)
	386	MCFG_RAM_DEFAULT_SIZE("608K")                   /* 96 base + 512 on expansion card */
	387	MCFG_RAM_EXTRA_OPTIONS("96K")
	388	MACHINE_CONFIG_END
	389
	390	static MACHINE_CONFIG_DERIVED( pk88, mc1502 )
	391	MCFG_CPU_REPLACE("maincpu", I8088, XTAL_16MHz/3)
	392	MCFG_CPU_PROGRAM_MAP(pk88_map)
	393	MCFG_CPU_IO_MAP(mc1502_io)
	394	MACHINE_CONFIG_END
	395
	396
	397	ROM_START( mc1502 )
	398	ROM_REGION16_LE(0x100000,"maincpu", 0)
	399
	400	ROM_DEFAULT_BIOS("v52")
	401	ROM_SYSTEM_BIOS(0, "v50", "v5.0")
	402	ROMX_LOAD( "monitor_5_0.rom",  0xfc000, 0x4000, CRC(9e97c6a0) SHA1(16a304e8de69ec4d8b92acda6bf28454c361a24f),ROM_BIOS(1))
	403	ROM_SYSTEM_BIOS(1, "v52", "v5.2")
	404	ROMX_LOAD( "monitor_5_2.rom",  0xfc000, 0x4000, CRC(0e65491e) SHA1(8a4d556473b5e0e59b05fab77c79c29f4d562412),ROM_BIOS(2))
	405	ROM_SYSTEM_BIOS(2, "v531", "v5.31")
	406	ROMX_LOAD( "monitor_5_31.rom", 0xfc000, 0x4000, CRC(a48295d5) SHA1(6f38977c22f9cc6c2bc6f6e53edc4048ca6b6721),ROM_BIOS(3))
	407	ROM_SYSTEM_BIOS(3, "v533", "v5.33")
	408	ROMX_LOAD( "0_(cbc0).bin", 0xfc000, 0x2000, CRC(9a55bc4f) SHA1(81da44eec2e52cf04b1fc7053502270f51270590),ROM_BIOS(4))
	409	ROMX_LOAD( "1_(dfe2).bin", 0xfe000, 0x2000, CRC(8dec077a) SHA1(d6f6d7cc2183abc77fbd9cd59132de5766f7c458),ROM_BIOS(4))
	410
	411	ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
	412	ROM_LOAD( "symgen.rom", 0x0000, 0x2000, CRC(b2747a52) SHA1(6766d275467672436e91ac2997ac6b77700eba1e))
	413	ROM_END
	414
	415	ROM_START( pk88 )
	416	ROM_REGION16_LE(0x100000,"maincpu", 0)
	417
	418	ROM_LOAD( "b0.064", 0xf0000, 0x2000, CRC(80d3cf5d) SHA1(64769b7a8b60ffeefa04e4afbec778069a2840c9))
	419	ROM_LOAD( "b1.064", 0xf2000, 0x2000, CRC(673a4acc) SHA1(082ae803994048e225150f771794ca305f73d731))
	420	ROM_LOAD( "b2.064", 0xf4000, 0x2000, CRC(1ee66152) SHA1(7ed8c4c6c582487e802beabeca5b86702e5083e8))
	421	ROM_LOAD( "b3.064", 0xf6000, 0x2000, CRC(3062b3fc) SHA1(5134dd64721cbf093d059ee5d3fd09c7f86604c7))
	422	ROM_LOAD( "pk88-0.064", 0xfc000, 0x2000, CRC(1e4666cf) SHA1(6364c5241f2792909ff318194161eb2c29737546))
	423	ROM_LOAD( "pk88-1.064", 0xfe000, 0x2000, CRC(6fa7e7ef) SHA1(d68bc273baa46ba733ac6ad4df7569dd70cf60dd))
	424
	425	ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
	426	// taken from mc1502
	427	ROM_LOAD( "symgen.rom", 0x0000, 0x2000, CRC(b2747a52) SHA1(6766d275467672436e91ac2997ac6b77700eba1e))
	428	ROM_END
	429
	430	/***************************************************************************
	431
	432	Game driver(s)
	433
	434	***************************************************************************/
	435
	436	/*     YEAR     NAME        PARENT      COMPAT  MACHINE     INPUT       INIT                COMPANY       FULLNAME */
	437	COMP ( 1989,    mc1502,     ibm5150,    0,      mc1502,     mc1502,     mc1502_state, mc1502,   "NPO Microprocessor", "Elektronika MC-1502", 0)
	438	COMP ( 1990,    pk88,       ibm5150,    0,      pk88,       mc1502,     mc1502_state, mc1502,   "NPO Microprocessor", "Elektronika PK-88", GAME_NOT_WORKING | GAME_NO_SOUND)

Property changes on: trunk/src/mess/drivers/mc1502.c

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/mess/drivers/poisk1.c

r0	r26689
	1	/***************************************************************************
	2
	3	drivers/poisk1.c
	4
	5	Driver file for Poisk-1
	6
	7	***************************************************************************/
	8
	9	#include "emu.h"
	10
	11	#include "includes/poisk1.h"
	12	#include "machine/kb_poisk1.h"
	13
	14	#include "cpu/i86/i86.h"
	15
	16	#define CGA_PALETTE_SETS 83
	17	/* one for colour, one for mono, 81 for colour composite */
	18
	19	#include "drivlgcy.h"
	20	#include "scrlegcy.h"
	21
	22	#define VERBOSE_DBG 0
	23
	24	#define DBG_LOG(N,M,A) \
	25	do { \
	26	if(VERBOSE_DBG>=N) \
	27	{ \
	28	if( M ) \
	29	logerror("%11.6f: %-24s",machine().time().as_double(),(char*)M ); \
	30	logerror A; \
	31	} \
	32	} while (0)
	33
	34	/*
	35	* onboard devices:
	36	*/
	37
	38	// Timer.  Poisk-1 uses single XTAL for everything? -- check
	39
	40	WRITE_LINE_MEMBER( p1_state::p1_speaker_set_spkrdata )
	41	{
	42	m_p1_spkrdata = state ? 1 : 0;
	43	m_speaker->level_w(m_p1_spkrdata & m_p1_input);
	44	}
	45
	46	WRITE_LINE_MEMBER( p1_state::p1_pit8253_out2_changed )
	47	{
	48	m_p1_input = state ? 1 : 0;
	49	m_speaker->level_w(m_p1_spkrdata & m_p1_input);
	50	}
	51
	52	const struct pit8253_interface p1_pit8253_config =
	53	{
	54	{
	55	{
	56	XTAL_15MHz/12,              /* heartbeat IRQ */
	57	DEVCB_NULL,
	58	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir0_w)
	59	}, {
	60	XTAL_15MHz/12,              /* keyboard poll -- XXX edge or level triggered? */
	61	DEVCB_NULL,
	62	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir6_w)
	63	}, {
	64	XTAL_15MHz/12,              /* pio port c pin 4, and speaker polling enough */
	65	DEVCB_NULL,
	66	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, p1_state, p1_pit8253_out2_changed)
	67	}
	68	}
	69	};
	70
	71	// Keyboard (via PPI)
	72
	73	WRITE8_MEMBER(p1_state::p1_ppi_porta_w)
	74	{
	75	m_kbpoll_mask = data;
	76	DBG_LOG(2,"p1_ppi_porta_w",("( %02X -> %02X )\n", data, m_kbpoll_mask));
	77	}
	78
	79	READ8_MEMBER(p1_state::p1_ppi_porta_r)
	80	{
	81	UINT8 ret;
	82
	83	ret = m_kbpoll_mask;
	84	DBG_LOG(1,"p1_ppi_porta_r",("= %02X\n", ret));
	85	return ret;
	86	}
	87
	88	READ8_MEMBER(p1_state::p1_ppi_portb_r)
	89	{
	90	UINT16 key = 0xffff;
	91	UINT8 ret = 0;
	92
	93	if (m_kbpoll_mask & 0x01) { key &= ioport("Y1")->read(); }
	94	if (m_kbpoll_mask & 0x02) { key &= ioport("Y2")->read(); }
	95	if (m_kbpoll_mask & 0x04) { key &= ioport("Y3")->read(); }
	96	if (m_kbpoll_mask & 0x08) { key &= ioport("Y4")->read(); }
	97	if (m_kbpoll_mask & 0x10) { key &= ioport("Y5")->read(); }
	98	if (m_kbpoll_mask & 0x20) { key &= ioport("Y6")->read(); }
	99	if (m_kbpoll_mask & 0x40) { key &= ioport("Y7")->read(); }
	100	if (m_kbpoll_mask & 0x80) { key &= ioport("Y8")->read(); }
	101	ret = key & 0xff;
	102	//   DBG_LOG(1,"p1_ppi_portb_r",("= %02X\n", ret));
	103	return ret;
	104	}
	105
	106	READ8_MEMBER(p1_state::p1_ppi_portc_r)
	107	{
	108	UINT16 key = 0xffff;
	109	UINT8 ret = 0;
	110
	111	if (m_kbpoll_mask & 0x01) { key &= ioport("Y1")->read(); }
	112	if (m_kbpoll_mask & 0x02) { key &= ioport("Y2")->read(); }
	113	if (m_kbpoll_mask & 0x04) { key &= ioport("Y3")->read(); }
	114	if (m_kbpoll_mask & 0x08) { key &= ioport("Y4")->read(); }
	115	if (m_kbpoll_mask & 0x10) { key &= ioport("Y5")->read(); }
	116	if (m_kbpoll_mask & 0x20) { key &= ioport("Y6")->read(); }
	117	if (m_kbpoll_mask & 0x40) { key &= ioport("Y7")->read(); }
	118	if (m_kbpoll_mask & 0x80) { key &= ioport("Y8")->read(); }
	119	ret = (key >> 8) & 0xff;
	120	DBG_LOG(2,"p1_ppi_portc_r",("= %02X\n", ret));
	121	return ret;
	122	}
	123
	124	// XXX
	125
	126	READ8_MEMBER(p1_state::p1_ppi2_portc_r)
	127	{
	128	int data = 0xff;
	129	double tap_val = m_cassette->input();
	130
	131	data = ( data & ~0x10 ) | ( tap_val < 0 ? 0x10 : 0x00 );
	132
	133	DBG_LOG(2,"p1_ppi_portc_r",("= %02X (tap_val %f) at %s\n",
	134	data, tap_val, machine().describe_context()));
	135	return data;
	136	}
	137
	138	WRITE8_MEMBER(p1_state::p1_ppi2_portb_w)
	139	{
	140	m_pit8253->gate2_w(BIT(data, 0));
	141	p1_speaker_set_spkrdata( data & 0x02 );
	142	}
	143
	144	I8255_INTERFACE( p1_ppi8255_interface_1 )
	145	{
	146	/*60H*/   DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, p1_state, p1_ppi_porta_r),
	147	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, p1_state, p1_ppi_porta_w),
	148	/*69H*/   DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, p1_state, p1_ppi_portb_r),
	149	DEVCB_NULL,
	150	/*6AH*/   DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, p1_state, p1_ppi_portc_r),
	151	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, p1_state, p1_ppi_portc_w)
	152	};
	153
	154	I8255_INTERFACE( p1_ppi8255_interface_2 )
	155	{
	156	/*68H*/   DEVCB_NULL,
	157	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, p1_state, p1_ppi2_porta_w),
	158	/*61H*/   DEVCB_NULL,
	159	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, p1_state, p1_ppi2_portb_w),
	160	/*62H*/   DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, p1_state, p1_ppi2_portc_r),
	161	DEVCB_NULL
	162	};
	163
	164	READ8_MEMBER(p1_state::p1_ppi_r)
	165	{
	166	//   DBG_LOG(1,"p1ppi",("R %.2x\n", 0x60+offset));
	167	switch (offset) {
	168	case 0:
	169	return m_ppi8255n1->read(space, 0);
	170	case 9:
	171	case 10:
	172	case 11:
	173	return m_ppi8255n1->read(space, offset - 8);
	174	case 8:
	175	return m_ppi8255n2->read(space, 0);
	176	case 1:
	177	case 2:
	178	case 3:
	179	return m_ppi8255n2->read(space, offset);
	180	default:
	181	DBG_LOG(1,"p1ppi",("R %.2x (unimp)\n", 0x60+offset));
	182	return 0xff;
	183	}
	184	}
	185
	186	WRITE8_MEMBER(p1_state::p1_ppi_w)
	187	{
	188	//   DBG_LOG(1,"p1ppi",("W %.2x $%02x\n", 0x60+offset, data));
	189	switch (offset) {
	190	case 0:
	191	return m_ppi8255n1->write(space, 0, data);
	192	case 9:
	193	case 10:
	194	case 11:
	195	return m_ppi8255n1->write(space, offset - 8, data);
	196	case 8:
	197	return m_ppi8255n2->write(space, 0, data);
	198	case 1:
	199	case 2:
	200	case 3:
	201	return m_ppi8255n2->write(space, offset, data);
	202	default:
	203	DBG_LOG(1,"p1ppi",("W %.2x $%02x (unimp)\n", 0x60+offset, data));
	204	return;
	205	}
	206	}
	207
	208	/**********************************************************
	209	*
	210	* NMI handling
	211	*
	212	**********************************************************/
	213
	214	static const isa8bus_interface p1_isabus_intf =
	215	{
	216	// interrupts
	217	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir2_w),
	218	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir3_w),
	219	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir4_w),
	220	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir5_w),
	221	DEVCB_NULL,
	222	DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir7_w),
	223
	224	// dma request
	225	DEVCB_NULL,
	226	DEVCB_NULL,
	227	DEVCB_NULL,
	228	};
	229
	230	static const cassette_interface p1_cassette_interface =
	231	{
	232	cassette_default_formats,
	233	NULL,
	234	(cassette_state)(CASSETTE_PLAY | CASSETTE_MOTOR_DISABLED | CASSETTE_SPEAKER_ENABLED),
	235	NULL,
	236	NULL
	237	};
	238
	239	IRQ_CALLBACK_MEMBER( p1_state::p1_irq_callback )
	240	{
	241	return m_pic8259->acknowledge();
	242	}
	243
	244	DRIVER_INIT_MEMBER( p1_state, poisk1 )
	245	{
	246	address_space &program = m_maincpu->space(AS_PROGRAM);
	247
	248	DBG_LOG(0,"init",("driver_init()\n"));
	249
	250	program.unmap_readwrite(0, 0x7ffff);
	251	program.install_readwrite_bank(0, m_ram->size()-1, "bank10");
	252	membank( "bank10" )->set_base( m_ram->pointer() );
	253	}
	254
	255	MACHINE_START_MEMBER( p1_state, poisk1 )
	256	{
	257	DBG_LOG(0,"init",("machine_start()\n"));
	258
	259	m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(p1_state::p1_irq_callback),this));
	260	}
	261
	262	MACHINE_RESET_MEMBER( p1_state, poisk1 )
	263	{
	264	DBG_LOG(0,"init",("machine_reset()\n"));
	265
	266	m_kbpoll_mask = 0;
	267	}
	268
	269	/*
	270	* macros
	271	*/
	272
	273	static ADDRESS_MAP_START( poisk1_map, AS_PROGRAM, 8, p1_state )
	274	ADDRESS_MAP_UNMAP_HIGH
	275	AM_RANGE(0x00000, 0x7ffff) AM_RAM
	276	AM_RANGE(0xc0000, 0xc1fff) AM_ROM
	277	AM_RANGE(0xc0000, 0xfbfff) AM_NOP
	278	AM_RANGE(0xfc000, 0xfffff) AM_ROM
	279	ADDRESS_MAP_END
	280
	281	static ADDRESS_MAP_START( poisk1_io, AS_IO, 8, p1_state )
	282	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE("pic8259", pic8259_device, read, write)
	283	AM_RANGE(0x0028, 0x002B) AM_READWRITE(p1_trap_r, p1_trap_w)
	284	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE("pit8253", pit8253_device, read, write)
	285	// can't use regular AM_DEVREADWRITE, because THIS IS SPARTA!
	286	// 1st PPI occupies ports 60, 69, 6A and 6B; 2nd PPI -- 68, 61, 62 and 63.
	287	AM_RANGE(0x0060, 0x006F) AM_READWRITE(p1_ppi_r, p1_ppi_w)
	288	AM_RANGE(0x03D0, 0x03DF) AM_READWRITE(p1_cga_r, p1_cga_w)
	289	ADDRESS_MAP_END
	290
	291	static INPUT_PORTS_START( poisk1 )
	292	PORT_INCLUDE( poisk1_keyboard_v91 )
	293	INPUT_PORTS_END
	294
	295	static MACHINE_CONFIG_START( poisk1, p1_state )
	296	/* basic machine hardware */
	297	MCFG_CPU_ADD("maincpu", I8088, 5000000)
	298	MCFG_CPU_PROGRAM_MAP(poisk1_map)
	299	MCFG_CPU_IO_MAP(poisk1_io)
	300
	301	MCFG_MACHINE_START_OVERRIDE( p1_state, poisk1 )
	302	MCFG_MACHINE_RESET_OVERRIDE( p1_state, poisk1 )
	303
	304	MCFG_PIT8253_ADD( "pit8253", p1_pit8253_config )
	305
	306	MCFG_PIC8259_ADD( "pic8259", INPUTLINE(":maincpu", 0), VCC, NULL )
	307
	308	MCFG_I8255A_ADD( "ppi8255n1", p1_ppi8255_interface_1 )
	309	MCFG_I8255A_ADD( "ppi8255n2", p1_ppi8255_interface_2 )
	310
	311	MCFG_ISA8_BUS_ADD("isa", ":maincpu", p1_isabus_intf)
	312	MCFG_ISA8_SLOT_ADD("isa", "isa1", p1_isa8_cards, "fdc", false)
	313	MCFG_ISA8_SLOT_ADD("isa", "isa2", p1_isa8_cards, NULL, false)
	314	MCFG_ISA8_SLOT_ADD("isa", "isa3", p1_isa8_cards, NULL, false)
	315	MCFG_ISA8_SLOT_ADD("isa", "isa4", p1_isa8_cards, NULL, false)
	316
	317	MCFG_CASSETTE_ADD( "cassette", p1_cassette_interface )
	318
	319	MCFG_SPEAKER_STANDARD_MONO( "mono" )
	320	MCFG_SOUND_ADD( "speaker", SPEAKER_SOUND, 0 )
	321	MCFG_SOUND_ROUTE( ALL_OUTPUTS, "mono", 1.00 )
	322
	323	MCFG_SCREEN_ADD( "screen", RASTER )
	324	MCFG_SCREEN_RAW_PARAMS( XTAL_15MHz, 912,0,640, 262,0,200 )
	325	MCFG_SCREEN_UPDATE_DRIVER( p1_state, screen_update )
	326
	327	/* XXX verify palette */
	328	MCFG_PALETTE_LENGTH( CGA_PALETTE_SETS * 16 )
	329
	330	/* internal ram */
	331	MCFG_RAM_ADD(RAM_TAG)
	332	MCFG_RAM_DEFAULT_SIZE("512K")
	333	MACHINE_CONFIG_END
	334
	335	ROM_START( poisk1 )
	336	ROM_REGION16_LE(0x100000,"maincpu", 0)
	337
	338	ROM_DEFAULT_BIOS("v91")
	339	ROM_SYSTEM_BIOS(0, "v89", "1989")
	340	ROMX_LOAD( "biosp1s.rf4", 0xfe000, 0x2000, CRC(1a85f671) SHA1(f0e59b2c4d92164abca55a96a58071ce869ff988), ROM_BIOS(1))
	341	ROM_SYSTEM_BIOS(1, "v91", "1991")
	342	ROMX_LOAD( "poisk_1991.bin", 0xfe000, 0x2000, CRC(d61c56fd) SHA1(de202e1f7422d585a1385a002a4fcf9d756236e5), ROM_BIOS(2))
	343	ROM_SYSTEM_BIOS(2, "v91r2", "1991r2")
	344	ROMX_LOAD( "p_bios_nm.bin", 0xfe000, 0x2000, CRC(84430b4f) SHA1(3e477962be3cea09662cb2e3ad9966ad01c7455d), ROM_BIOS(3))
	345
	346	// 0xc0000, sets 80x25 text and loops asking for 'Boot from hard disk (Y or N)?'
	347	ROM_LOAD( "boot_net.rf4", 0x00000, 0x2000, CRC(316c2030) SHA1(d043325596455772252e465b85321f1b5c529d0b)) // NET BIOS
	348	// 0xc0000, accesses ports 0x90..0x97
	349	ROM_LOAD( "pois_net.bin", 0x00000, 0x2000, CRC(cf9dd80a) SHA1(566bcb40c0cb2c8bfd5b485f0db689fdeaca3e86)) // ??? BIOS
	350
	351	ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
	352	ROM_LOAD( "poisk.cga", 0x0000, 0x0800, CRC(f6eb39f0) SHA1(0b788d8d7a8e92cc612d044abcb2523ad964c200))
	353	ROM_END
	354
	355	/***************************************************************************
	356
	357	Game driver(s)
	358
	359	***************************************************************************/
	360
	361	/*     YEAR     NAME        PARENT      COMPAT  MACHINE     INPUT       INIT                COMPANY       FULLNAME */
	362	COMP ( 1989,    poisk1,    ibm5150,    0,      poisk1,    poisk1,    p1_state, poisk1,   "Electronmash",  "Poisk-1", 0)

Property changes on: trunk/src/mess/drivers/poisk1.c

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/mess/drivers/iskr103x.c

r0	r26689
	1	/***************************************************************************
	2
	3	drivers/iskr103x.c
	4
	5	Driver file for Iskra-1030, 1031
	6
	7	TODO
	8	- fix cyrillic chargen upload for CGA and MDA
	9	- replace DIP switch definition
	10	- keyboard test is not passing (code 301)
	11	- hard disk is connected but untested
	12
	13	***************************************************************************/
	14
	15
	16	#include "emu.h"
	17
	18	#include "includes/genpc.h"
	19
	20	#include "cpu/nec/nec.h"
	21	#include "cpu/i86/i86.h"
	22	#include "machine/pc_lpt.h"
	23	#include "bus/pc_kbd/keyboards.h"
	24	#include "machine/ram.h"
	25
	26	#define DBG_LOG(a,b,c)
	27
	28	class iskr103x_state : public driver_device
	29	{
	30	public:
	31	iskr103x_state(const machine_config &mconfig, device_type type, const char *tag)
	32	: driver_device(mconfig, type, tag) ,
	33	m_maincpu(*this, "maincpu") { }
	34
	35	required_device<cpu_device> m_maincpu;
	36	};
	37
	38	static ADDRESS_MAP_START( iskr1031_map, AS_PROGRAM, 16, iskr103x_state )
	39	ADDRESS_MAP_UNMAP_HIGH
	40	AM_RANGE(0x00000, 0x7ffff) AM_RAMBANK("bank10")
	41	AM_RANGE(0xa0000, 0xbffff) AM_NOP
	42	AM_RANGE(0xc0000, 0xc7fff) AM_ROM
	43	AM_RANGE(0xc8000, 0xcffff) AM_ROM
	44	AM_RANGE(0xd0000, 0xeffff) AM_NOP
	45	AM_RANGE(0xf0000, 0xfffff) AM_ROM
	46	ADDRESS_MAP_END
	47
	48
	49	static ADDRESS_MAP_START(iskr1031_io, AS_IO, 16, iskr103x_state)
	50	ADDRESS_MAP_UNMAP_HIGH
	51	ADDRESS_MAP_END
	52
	53
	54	static INPUT_PORTS_START( iskr1030m )
	55	INPUT_PORTS_END
	56
	57	static INPUT_PORTS_START( iskr1031 )
	58	INPUT_PORTS_END
	59
	60	static DEVICE_INPUT_DEFAULTS_START(iskr1030m)
	61	DEVICE_INPUT_DEFAULTS("DSW0", 0x31, 0x21)
	62	DEVICE_INPUT_DEFAULTS_END
	63
	64	static DEVICE_INPUT_DEFAULTS_START(iskr1031)
	65	DEVICE_INPUT_DEFAULTS("DSW0", 0x30, 0x20)
	66	DEVICE_INPUT_DEFAULTS_END
	67
	68	// XXX
	69	static MACHINE_CONFIG_START( iskr1030m, iskr103x_state )
	70	/* basic machine hardware */
	71	MCFG_CPU_ADD("maincpu",  I8086, 4772720)
	72	MCFG_CPU_PROGRAM_MAP(iskr1031_map)
	73	MCFG_CPU_IO_MAP(iskr1031_io)
	74
	75	MCFG_IBM5160_MOTHERBOARD_ADD("mb","maincpu")
	76	MCFG_DEVICE_INPUT_DEFAULTS(iskr1030m)
	77
	78	MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", pc_isa8_cards, "mda", false)
	79	MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", pc_isa8_cards, "fdc_xt", false)
	80	MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, NULL, false) // hdc is WIP
	81	MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", pc_isa8_cards, NULL, false)
	82	MCFG_ISA8_SLOT_ADD("mb:isa", "isa5", pc_isa8_cards, NULL, false)
	83	MCFG_ISA8_SLOT_ADD("mb:isa", "isa6", pc_isa8_cards, NULL, false)
	84
	85	MCFG_PC_KBDC_SLOT_ADD("mb:pc_kbdc", "kbd", pc_xt_keyboards, STR_KBD_EC_1841)
	86	//   MCFG_PC_KBDC_SLOT_ADD("mb:pc_kbdc", "kbd", pc_xt_keyboards, STR_KBD_ISKR_1030)
	87
	88	MCFG_RAM_ADD(RAM_TAG)
	89	MCFG_RAM_DEFAULT_SIZE("640K")
	90	MACHINE_CONFIG_END
	91
	92	static MACHINE_CONFIG_START( iskr1031, iskr103x_state )
	93	/* basic machine hardware */
	94	MCFG_CPU_ADD("maincpu",  I8086, 4772720)
	95	MCFG_CPU_PROGRAM_MAP(iskr1031_map)
	96	MCFG_CPU_IO_MAP(iskr1031_io)
	97
	98	MCFG_IBM5160_MOTHERBOARD_ADD("mb","maincpu")
	99	MCFG_DEVICE_INPUT_DEFAULTS(iskr1031)
	100
	101	MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", pc_isa8_cards, "cga", false)
	102	MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", pc_isa8_cards, "fdc_xt", false)
	103	MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, NULL, false) // hdc is WIP
	104	MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", pc_isa8_cards, NULL, false)
	105	MCFG_ISA8_SLOT_ADD("mb:isa", "isa5", pc_isa8_cards, NULL, false)
	106	MCFG_ISA8_SLOT_ADD("mb:isa", "isa6", pc_isa8_cards, NULL, false)
	107
	108	//   MCFG_SOFTWARE_LIST_ADD("flop_list", "iskr1031")
	109
	110	MCFG_PC_KBDC_SLOT_ADD("mb:pc_kbdc", "kbd", pc_xt_keyboards, STR_KBD_EC_1841)
	111	//   MCFG_PC_KBDC_SLOT_ADD("mb:pc_kbdc", "kbd", pc_xt_keyboards, STR_KBD_ISKR_1030)
	112
	113	MCFG_RAM_ADD(RAM_TAG)
	114	MCFG_RAM_DEFAULT_SIZE("640K")
	115	MACHINE_CONFIG_END
	116
	117	ROM_START( iskr1030m )
	118	ROM_REGION16_LE(0x100000,"maincpu", 0)
	119	ROMX_LOAD( "iskra-1030m_0.rom", 0xfc000, 0x2000, CRC(0d698e19) SHA1(2fe117c9f4f8c4b59085d5a41f919d743c425fdd), ROM_SKIP(1))
	120	ROMX_LOAD( "iskra-1030m_1.rom", 0xfc001, 0x2000, CRC(fe808337) SHA1(b0b7ebe14324ada8aa9a6926a82b18e80f78a257), ROM_SKIP(1))
	121
	122	ROM_REGION(0x2000,"gfx1", 0)
	123	ROM_LOAD( "iskra-1030m.chr", 0x0000, 0x2000, CRC(50b162eb) SHA1(5bd7cb1705a69bd16115a4c9ed1c2748a5c8ad51))
	124	ROM_END
	125
	126	ROM_START( iskr1031 )
	127	ROM_REGION16_LE(0x100000,"maincpu", 0)
	128	ROM_SYSTEM_BIOS(0, "v1", "v1")
	129	ROMX_LOAD( "150-02.bin", 0xfc000, 0x2000, CRC(e33fb974) SHA1(f5f3ece67c025c0033716ff516e1a34fbeb32749), ROM_SKIP(1) | ROM_BIOS(1))
	130	ROMX_LOAD( "150-03.bin", 0xfc001, 0x2000, CRC(8c482258) SHA1(90ef48955e0df556dc06a000a797ef42ccf430c5), ROM_SKIP(1) | ROM_BIOS(1))
	131	ROM_SYSTEM_BIOS(1, "v2", "v2")
	132	ROMX_LOAD( "150-06.bin", 0xfc000, 0x2000, CRC(1adbf969) SHA1(08c0a0fc50a75e6207b1987bae389cca60893eac), ROM_SKIP(1) | ROM_BIOS(2))
	133	ROMX_LOAD( "150-07.bin", 0xfc001, 0x2000, CRC(0dc4b65a) SHA1(c96f066251a7343eac8113ea9dcb2cb12d0334d5), ROM_SKIP(1) | ROM_BIOS(2))
	134
	135	ROM_REGION(0x2000,"gfx1", 0)
	136	ROM_LOAD( "iskra-1031_font.bin", 0x0000, 0x2000, CRC(f4d62e80) SHA1(ad7e81a0c9abc224671422bbcf6f6262da92b510))
	137	ROM_END
	138
	139	/***************************************************************************
	140
	141	Game driver(s)
	142
	143	***************************************************************************/
	144
	145	/*     YEAR     NAME        PARENT      COMPAT  MACHINE     INPUT                       INIT        COMPANY     FULLNAME */
	146	COMP ( 1989,    iskr1030m,  ibm5150,    0,      iskr1030m,  iskr1030m, driver_device,   0,          "Schetmash", "Iskra 1030M", GAME_NOT_WORKING)
	147	COMP ( 1989,    iskr1031,   ibm5150,    0,      iskr1031,   iskr1031,  driver_device,   0,          "<unknown>", "Iskra 1031", 0)

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trunk/src/mess/machine/xsu_cards.c

r0	r26689
	1	/**********************************************************************
	2
	3	ISA bus cards for ex-USSR PC clones
	4
	5	license: MAME, GPL-2.0+
	6	copyright-holders: XXX
	7
	8	**********************************************************************/
	9
	10	#include "xsu_cards.h"
	11
	12	SLOT_INTERFACE_START( p1_isa8_cards )
	13	SLOT_INTERFACE("rom", P1_ROM)
	14	SLOT_INTERFACE("fdc", P1_FDC)      // B504
	15	SLOT_INTERFACE("hdc", P1_HDC)      // B942
	16	/*
	17	SLOT_INTERFACE("comlpt", P1_COMLPT)   // B620
	18	SLOT_INTERFACE("joy", P1_JOY)      // B621
	19	SLOT_INTERFACE("mouse", P1_MOUSE)   // B943
	20	SLOT_INTERFACE("lan", P1_LAN)      // B944
	21	*/
	22	SLOT_INTERFACE("pccom", ISA8_COM)
	23	SLOT_INTERFACE("pclpt", ISA8_LPT)
	24	SLOT_INTERFACE("xtide", ISA8_XTIDE)
	25	SLOT_INTERFACE_END
	26
	27	SLOT_INTERFACE_START( mc1502_isa8_cards )
	28	SLOT_INTERFACE("rom", MC1502_ROM)
	29	SLOT_INTERFACE("fdc", MC1502_FDC)
	30	/*
	31	SLOT_INTERFACE("hdc", MC1502_HDC)
	32	*/
	33	SLOT_INTERFACE("pccom", ISA8_COM)
	34	SLOT_INTERFACE("pclpt", ISA8_LPT)
	35	SLOT_INTERFACE("xtide", ISA8_XTIDE)
	36	SLOT_INTERFACE_END

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trunk/src/mess/machine/xsu_cards.h

r0	r26689
	1	/**********************************************************************
	2
	3	ISA bus cards for ex-USSR PC clones
	4
	5	license: MAME, GPL-2.0+
	6	copyright-holders: XXX
	7
	8	**********************************************************************/
	9
	10	#pragma once
	11
	12	#ifndef __XSU_CARDS_H__
	13	#define __XSU_CARDS_H__
	14
	15	#include "emu.h"
	16
	17	// storage
	18	#include "machine/mc1502_fdc.h"
	19	#include "machine/p1_fdc.h"
	20	#include "machine/p1_hdc.h"
	21
	22	// misc
	23	#include "machine/mc1502_rom.h"
	24	#include "machine/p1_rom.h"
	25
	26	// non-native
	27	#include "machine/isa_com.h"
	28	#include "machine/isa_xtide.h"
	29	#include "machine/pc_lpt.h"
	30
	31	// supported devices
	32	SLOT_INTERFACE_EXTERN( p1_isa8_cards );
	33	SLOT_INTERFACE_EXTERN( mc1502_isa8_cards );
	34
	35	#endif // __XSU_CARDS_H__

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trunk/src/mess/machine/p1_fdc.c

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	Poisk-1 FDC device (model B504)
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#include "p1_fdc.h"
	13
	14	#include "cpu/i86/i86.h"
	15	#include "formats/dsk_dsk.h"
	16	#include "formats/pc_dsk.h"
	17
	18	#define VERBOSE_DBG 0
	19
	20	#define DBG_LOG(N,M,A) \
	21	do { \
	22	if(VERBOSE_DBG>=N) \
	23	{ \
	24	if( M ) \
	25	logerror("%11.6f: %-24s",machine().time().as_double(),(char*)M ); \
	26	logerror A; \
	27	} \
	28	} while (0)
	29
	30
	31	//**************************************************************************
	32	//  DEVICE DEFINITIONS
	33	//**************************************************************************
	34
	35	const device_type P1_FDC = &device_creator<p1_fdc_device>;
	36
	37	static DECLARE_READ8_DEVICE_HANDLER(p1_FDC_r);
	38	static DECLARE_WRITE8_DEVICE_HANDLER(p1_FDC_w);
	39
	40	FLOPPY_FORMATS_MEMBER( p1_fdc_device::floppy_formats )
	41	FLOPPY_PC_FORMAT,
	42	FLOPPY_DSK_FORMAT
	43	FLOPPY_FORMATS_END
	44
	45	static SLOT_INTERFACE_START( poisk1_floppies )
	46	SLOT_INTERFACE( "525qd", FLOPPY_525_QD )
	47	SLOT_INTERFACE_END
	48
	49	static MACHINE_CONFIG_FRAGMENT( fdc_b504 )
	50	MCFG_FD1793x_ADD("fdc", XTAL_16MHz / 16)
	51	MCFG_FLOPPY_DRIVE_ADD("fdc:0", poisk1_floppies, "525qd", p1_fdc_device::floppy_formats)
	52	MCFG_FLOPPY_DRIVE_ADD("fdc:1", poisk1_floppies, "525qd", p1_fdc_device::floppy_formats)
	53	MACHINE_CONFIG_END
	54
	55	//-------------------------------------------------
	56	//  ROM( p1_fdc )
	57	//-------------------------------------------------
	58
	59	ROM_START( p1_fdc )
	60	ROM_REGION( 0x0800, "p1_fdc", 0 )
	61	ROM_DEFAULT_BIOS("a302")
	62	ROM_SYSTEM_BIOS(0, "normal", "B504 standard ROM")
	63	ROMX_LOAD( "b_ngmd_n.rf2", 0x00000, 0x0800, CRC(967e172a) SHA1(95117c40fd9f624fee08ccf37f615b16ff249688), ROM_BIOS(1))
	64	ROM_SYSTEM_BIOS(1, "a302", "v3.02") // Additional ROM BIOS v3.02 for DISKETTE service (c) Moscow 1991
	65	ROMX_LOAD( "b_ngmd_t.rf2", 0x00000, 0x0800, CRC(630010b1) SHA1(50876fe4f5f4f32a242faa70f9154574cd315ec4), ROM_BIOS(2))
	66	ROM_SYSTEM_BIOS(2, "ae304", "v3.04") // Additional enhanced ROM BIOS v3.04 for DISKETTE service (c) V.Rusakow Moscow 1992
	67	ROMX_LOAD( "p_fdd_nm.bin", 0x00000, 0x0800, CRC(0b7f867d) SHA1(9fe7e0ab2242e50394d1162cf1a619b6f2994bfb), ROM_BIOS(3))
	68	ROM_SYSTEM_BIOS(3, "ae308", "v3.08") // Additional enhanced ROM BIOS v3.08 for DISKETTE service (c) V.Rusakov Tarasovka 1992
	69	ROMX_LOAD( "p_fdd_my.bin", 0x00000, 0x0800, CRC(da5d0eaf) SHA1(b188ba856bd28e4964a88feb0b0b2ba7eb320efc), ROM_BIOS(4))
	70	ROM_END
	71
	72
	73	//-------------------------------------------------
	74	//  machine_config_additions - device-specific
	75	//  machine configurations
	76	//-------------------------------------------------
	77
	78	machine_config_constructor p1_fdc_device::device_mconfig_additions() const
	79	{
	80	return MACHINE_CONFIG_NAME( fdc_b504 );
	81	}
	82
	83	//-------------------------------------------------
	84	//  rom_region - device-specific ROM region
	85	//-------------------------------------------------
	86
	87	const rom_entry *p1_fdc_device::device_rom_region() const
	88	{
	89	return ROM_NAME( p1_fdc );
	90	}
	91
	92
	93	//**************************************************************************
	94	//  LIVE DEVICE
	95	//**************************************************************************
	96
	97	UINT8 p1_fdc_device::p1_wd17xx_motor_r()
	98	{
	99	DBG_LOG(1,"p1_fdc_motor_r",("R = $%02x\n", 0));
	100	// XXX always on for now
	101	return 0;
	102	}
	103
	104	UINT8 p1_fdc_device::p1_wd17xx_aux_r()
	105	{
	106	cpu_device *maincpu = machine().device<cpu_device>("maincpu");
	107
	108	if (!m_fdc->drq_r() && !m_fdc->intrq_r()) {
	109	// fake cpu wait by resetting PC one insn back
	110	maincpu->set_state_int(I8086_IP, maincpu->state_int(I8086_IP) - 2);
	111	maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	112	}
	113
	114	return m_fdc->drq_r();
	115	}
	116
	117	/*
	118	;       D0 - DRIVE SELECT 0
	119	;       D1 - DRIVE SELECT 1
	120	;       D2 - MOTOR ON 0
	121	;       D3 - MOTOR ON 1
	122	;       D4 - SIDE (HEAD) SELECT
	123	;       D5 - DOUBLE DENSITY
	124	;       D6 - FDC RESET
	125	;       D7 - NO USE
	126	*/
	127	void p1_fdc_device::p1_wd17xx_aux_w(int data)
	128	{
	129	DBG_LOG(1,"p1_fdc_aux_w",("W $%02x\n", data));
	130
	131	floppy_image_device *floppy0 = m_fdc->subdevice<floppy_connector>("0")->get_device();
	132	floppy_image_device *floppy1 = m_fdc->subdevice<floppy_connector>("1")->get_device();
	133	floppy_image_device *floppy = ((data & 2)?floppy1:floppy0);
	134
	135	if(!BIT(data, 6))
	136	m_fdc->reset();
	137
	138	m_fdc->set_floppy(floppy);
	139
	140	floppy->ss_w(BIT(data, 4));
	141	m_fdc->dden_w(BIT(data, 5));
	142
	143	floppy0->mon_w(!(data & 4));
	144	floppy1->mon_w(!(data & 8));
	145	}
	146
	147	void p1_fdc_device::p1_fdc_irq_drq(bool state)
	148	{
	149	cpu_device *maincpu = machine().device<cpu_device>("maincpu");
	150
	151	if(state)
	152	maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	153	}
	154
	155	static READ8_DEVICE_HANDLER( p1_FDC_r )
	156	{
	157	UINT8 data = 0xff;
	158	p1_fdc_device *fdc  = downcast<p1_fdc_device *>(device);
	159
	160	switch( offset )
	161	{
	162	case 0: data = fdc->p1_wd17xx_aux_r();     break;
	163	case 2: data = fdc->p1_wd17xx_motor_r();   break;
	164	}
	165
	166	return data;
	167	}
	168
	169	static WRITE8_DEVICE_HANDLER( p1_FDC_w )
	170	{
	171	p1_fdc_device *fdc  = downcast<p1_fdc_device *>(device);
	172
	173	switch( offset )
	174	{
	175	case 0: fdc->p1_wd17xx_aux_w(data);    break;
	176	}
	177	}
	178
	179	//-------------------------------------------------
	180	//  p1_fdc_device - constructor
	181	//-------------------------------------------------
	182
	183	p1_fdc_device::p1_fdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	184	device_t(mconfig, P1_FDC, "Poisk-1 floppy B504", tag, owner, clock, "p1_fdc", __FILE__),
	185	device_isa8_card_interface( mconfig, *this ),
	186	m_fdc(*this, "fdc")
	187	{
	188	}
	189
	190
	191	//-------------------------------------------------
	192	//  device_start - device-specific startup
	193	//-------------------------------------------------
	194
	195	void p1_fdc_device::device_start()
	196	{
	197	set_isa_device();
	198	m_isa->install_rom(this, 0xe0000, 0xe07ff, 0, 0, "XXX", "p1_fdc");
	199	m_isa->install_device(0x00c0, 0x00c3, 0, 0,
	200	READ8_DEVICE_DELEGATE(m_fdc, fd1793_t, read),
	201	WRITE8_DEVICE_DELEGATE(m_fdc, fd1793_t, write) );
	202	m_isa->install_device(this, 0x00c4, 0x00c7, 0, 0, FUNC(p1_FDC_r), FUNC(p1_FDC_w) );
	203	m_fdc->setup_drq_cb(fd1793_t::line_cb(FUNC(p1_fdc_device::p1_fdc_irq_drq), this));
	204	m_fdc->setup_intrq_cb(fd1793_t::line_cb(FUNC(p1_fdc_device::p1_fdc_irq_drq), this));
	205	}
	206
	207
	208	//-------------------------------------------------
	209	//  device_reset - device-specific reset
	210	//-------------------------------------------------
	211
	212	void p1_fdc_device::device_reset()
	213	{
	214	}

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trunk/src/mess/machine/p1_fdc.h

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	Poisk-1 FDC device (model B504)
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#pragma once
	13
	14	#ifndef __P1_FDC__
	15	#define __P1_FDC__
	16
	17	#include "emu.h"
	18
	19	#include "imagedev/flopdrv.h"
	20	#include "machine/isa.h"
	21	#include "machine/wd_fdc.h"
	22
	23	//**************************************************************************
	24	//  TYPE DEFINITIONS
	25	//**************************************************************************
	26
	27	class p1_fdc_device : public device_t,
	28	public device_isa8_card_interface
	29	{
	30	public:
	31	// construction/destruction
	32	p1_fdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	33
	34	// optional information overrides
	35	virtual machine_config_constructor device_mconfig_additions() const;
	36	virtual const rom_entry *device_rom_region() const;
	37
	38	DECLARE_FLOPPY_FORMATS( floppy_formats );
	39
	40	protected:
	41	// device-level overrides
	42	virtual void device_start();
	43	virtual void device_reset();
	44
	45	private:
	46	required_device<fd1793_t> m_fdc;
	47
	48	public:
	49	void p1_wd17xx_aux_w(int data);
	50	UINT8 p1_wd17xx_aux_r();
	51	UINT8 p1_wd17xx_motor_r();
	52	void p1_fdc_irq_drq(bool state);
	53
	54	};
	55
	56
	57	// device type definition
	58	extern const device_type P1_FDC;
	59
	60
	61	#endif

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trunk/src/mess/machine/mc1502_rom.c

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	MC-1502 ROM cartridge device
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#include "mc1502_rom.h"
	13
	14
	15	//**************************************************************************
	16	//  DEVICE DEFINITIONS
	17	//**************************************************************************
	18
	19	const device_type MC1502_ROM = &device_creator<mc1502_rom_device>;
	20
	21
	22	//-------------------------------------------------
	23	//  ROM( mc1502_rom )
	24	//-------------------------------------------------
	25
	26	ROM_START( mc1502_rom )
	27	ROM_REGION( 0x8000, "mc1502_rom", 0 )
	28	ROM_LOAD( "basic.rom", 0x00000, 0x8000, CRC(173d69fa) SHA1(003f872e12f00800e22ab6bbc009d36bfde67b9d))
	29	ROM_END
	30
	31
	32	//-------------------------------------------------
	33	//  rom_region - device-specific ROM region
	34	//-------------------------------------------------
	35
	36	const rom_entry *mc1502_rom_device::device_rom_region() const
	37	{
	38	return ROM_NAME( mc1502_rom );
	39	}
	40
	41
	42	//**************************************************************************
	43	//  LIVE DEVICE
	44	//**************************************************************************
	45
	46	//-------------------------------------------------
	47	//  mc1502_rom_device - constructor
	48	//-------------------------------------------------
	49
	50	mc1502_rom_device::mc1502_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	51	device_t(mconfig, MC1502_ROM, "MC-1502 ROM cart", tag, owner, clock, "mc1502_rom", __FILE__),
	52	device_isa8_card_interface( mconfig, *this )
	53	{
	54	}
	55
	56
	57	//-------------------------------------------------
	58	//  device_start - device-specific startup
	59	//-------------------------------------------------
	60
	61	void mc1502_rom_device::device_start()
	62	{
	63	set_isa_device();
	64	m_isa->install_rom(this, 0xe8000, 0xeffff, 0, 0, "XXX", "mc1502_rom");
	65	}
	66
	67
	68	//-------------------------------------------------
	69	//  device_reset - device-specific reset
	70	//-------------------------------------------------
	71
	72	void mc1502_rom_device::device_reset()
	73	{
	74	}

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trunk/src/mess/machine/mc1502_rom.h

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	MC-1502 ROM cartridge device
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#pragma once
	13
	14	#ifndef __MC1502_ROM__
	15	#define __MC1502_ROM__
	16
	17	#include "emu.h"
	18	#include "machine/isa.h"
	19
	20	//**************************************************************************
	21	//  TYPE DEFINITIONS
	22	//**************************************************************************
	23
	24	class mc1502_rom_device : public device_t,
	25	public device_isa8_card_interface
	26	{
	27	public:
	28	// construction/destruction
	29	mc1502_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	30
	31	// optional information overrides
	32	virtual const rom_entry *device_rom_region() const;
	33
	34	protected:
	35	// device-level overrides
	36	virtual void device_start();
	37	virtual void device_reset();
	38	};
	39
	40
	41	// device type definition
	42	extern const device_type MC1502_ROM;
	43
	44
	45	#endif

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trunk/src/mess/machine/p1_rom.c

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	Poisk-1 ROM cartridge device
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#include "p1_rom.h"
	13
	14
	15	//**************************************************************************
	16	//  DEVICE DEFINITIONS
	17	//**************************************************************************
	18
	19	const device_type P1_ROM = &device_creator<p1_rom_device>;
	20
	21
	22	//-------------------------------------------------
	23	//  ROM( p1_rom )
	24	//-------------------------------------------------
	25
	26	ROM_START( p1_rom )
	27	ROM_REGION( 0x2000, "p1_rom", 0 )
	28	ROM_SYSTEM_BIOS(0, "ram", "Test 3 -- RAM test")
	29	ROMX_LOAD( "p1_t_ram.rf4", 0x00000, 0x2000, CRC(e42f5a61) SHA1(ce2554eae8f0d2b6d482890dd198cf7e2d29c655), ROM_BIOS(1))
	30	ROM_SYSTEM_BIOS(1, "io", "Test 4 -- I/O test")
	31	ROMX_LOAD( "p1_t_i_o.rf4", 0x00000, 0x2000, CRC(18a781de) SHA1(7267970ee27e3ea1d972bee8e74b17bac1051619), ROM_BIOS(2))
	32	ROM_SYSTEM_BIOS(2, "pls", "\"MB test\"")
	33	ROMX_LOAD( "p1_t_pls.rf4", 0x00000, 0x2000, CRC(c8210ffb) SHA1(f2d1a6c90e4708bcc56186b2fb906fa852667084), ROM_BIOS(3))
	34	ROM_END
	35
	36
	37	//-------------------------------------------------
	38	//  rom_region - device-specific ROM region
	39	//-------------------------------------------------
	40
	41	const rom_entry *p1_rom_device::device_rom_region() const
	42	{
	43	return ROM_NAME( p1_rom );
	44	}
	45
	46
	47	//**************************************************************************
	48	//  LIVE DEVICE
	49	//**************************************************************************
	50
	51	//-------------------------------------------------
	52	//  p1_rom_device - constructor
	53	//-------------------------------------------------
	54
	55	p1_rom_device::p1_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	56	device_t(mconfig, P1_ROM, "Poisk-1 ROM cart", tag, owner, clock, "p1_rom", __FILE__),
	57	device_isa8_card_interface( mconfig, *this )
	58	{
	59	}
	60
	61
	62	//-------------------------------------------------
	63	//  device_start - device-specific startup
	64	//-------------------------------------------------
	65
	66	void p1_rom_device::device_start()
	67	{
	68	set_isa_device();
	69	m_isa->install_rom(this, 0xc0000, 0xc1fff, 0, 0, "XXX", "p1_rom");
	70	}
	71
	72
	73	//-------------------------------------------------
	74	//  device_reset - device-specific reset
	75	//-------------------------------------------------
	76
	77	void p1_rom_device::device_reset()
	78	{
	79	}

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trunk/src/mess/machine/p1_rom.h

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	Poisk-1 ROM cartridge device
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#pragma once
	13
	14	#ifndef __P1_ROM__
	15	#define __P1_ROM__
	16
	17	#include "emu.h"
	18	#include "machine/isa.h"
	19
	20	//**************************************************************************
	21	//  TYPE DEFINITIONS
	22	//**************************************************************************
	23
	24	class p1_rom_device : public device_t,
	25	public device_isa8_card_interface
	26	{
	27	public:
	28	// construction/destruction
	29	p1_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	30
	31	// optional information overrides
	32	virtual const rom_entry *device_rom_region() const;
	33
	34	protected:
	35	// device-level overrides
	36	virtual void device_start();
	37	virtual void device_reset();
	38	};
	39
	40
	41	// device type definition
	42	extern const device_type P1_ROM;
	43
	44
	45	#endif

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trunk/src/mess/machine/isa_cards.c

r26688	r26689
12	12	SLOT_INTERFACE_START( pc_isa8_cards )
13	13	SLOT_INTERFACE("mda", ISA8_MDA)
14	14	SLOT_INTERFACE("cga", ISA8_CGA)
	15	SLOT_INTERFACE("cga_ec1841", ISA8_EC1841_0002)
15	16	SLOT_INTERFACE("ega", ISA8_EGA)
16	17	SLOT_INTERFACE("svga_et4k", ISA8_SVGA_ET4K)
17	18	SLOT_INTERFACE("com", ISA8_COM)

trunk/src/mess/machine/p1_hdc.c

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	Poisk-1 HDC device (model B942)
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#include "p1_hdc.h"
	13
	14
	15	//**************************************************************************
	16	//  MACROS / CONSTANTS
	17	//**************************************************************************
	18
	19	#define VERBOSE_DBG 1
	20
	21	#define DBG_LOG(N,M,A) \
	22	do { \
	23	if(VERBOSE_DBG>=N) \
	24	{ \
	25	if( M ) \
	26	logerror("%11.6f: %-24s",machine().time().as_double(),(char*)M ); \
	27	logerror A; \
	28	} \
	29	} while (0)
	30
	31	#define KM1809VG7_TAG   "d17"
	32
	33
	34	//**************************************************************************
	35	//  DEVICE DEFINITIONS
	36	//**************************************************************************
	37
	38	const device_type P1_HDC = &device_creator<p1_hdc_device>;
	39
	40	static WD2010_INTERFACE( hdc_intf )
	41	{
	42	DEVCB_NULL,
	43	DEVCB_NULL,
	44	DEVCB_NULL,
	45	DEVCB_NULL,
	46	DEVCB_NULL,
	47	DEVCB_NULL,
	48	DEVCB_NULL,
	49	DEVCB_NULL,
	50	DEVCB_LINE_VCC,
	51	DEVCB_LINE_VCC,
	52	DEVCB_LINE_VCC,
	53	DEVCB_LINE_VCC,
	54	DEVCB_LINE_VCC
	55	};
	56
	57	static MACHINE_CONFIG_FRAGMENT( hdc_b942 )
	58	MCFG_WD2010_ADD(KM1809VG7_TAG, 5000000, hdc_intf) // XXX clock?
	59
	60	MCFG_HARDDISK_ADD("hard0")
	61	MCFG_HARDDISK_ADD("hard1")
	62	MACHINE_CONFIG_END
	63
	64
	65	//-------------------------------------------------
	66	//  ROM( p1_hdc )
	67	//-------------------------------------------------
	68
	69	ROM_START( p1_hdc )
	70	ROM_REGION( 0x0800, "p1_hdc", 0 )
	71	ROM_DEFAULT_BIOS("v14")
	72	ROM_SYSTEM_BIOS(0, "v11", "ver 1.1")
	73	ROMX_LOAD( "b_hd_v11.rf2", 0x00000, 0x0800, CRC(a19c39b2) SHA1(57faa56b320abf801fedbed578cf97d253e5b777), ROM_BIOS(1))
	74	ROM_SYSTEM_BIOS(1, "v12", "ver 1.2")
	75	ROMX_LOAD( "p_hdd_nm.bin", 0x00000, 0x0800, CRC(d5f8e4cc) SHA1(5b533642df30958539715f87a7f25b0d66dd0861), ROM_BIOS(2))
	76	ROM_SYSTEM_BIOS(2, "v14", "ver 1.4") // (c) `.lesnyh. , 1992
	77	ROMX_LOAD( "b942_5mb.bin", 0x00000, 0x0800, CRC(a3cfa240) SHA1(0b0aa1ce839a957153bfbbe70310480ca9fe21b6), ROM_BIOS(3))
	78	ROM_END
	79
	80
	81	//-------------------------------------------------
	82	//  machine_config_additions - device-specific
	83	//  machine configurations
	84	//-------------------------------------------------
	85
	86	machine_config_constructor p1_hdc_device::device_mconfig_additions() const
	87	{
	88	return MACHINE_CONFIG_NAME( hdc_b942 );
	89	}
	90
	91
	92	//-------------------------------------------------
	93	//  rom_region - device-specific ROM region
	94	//-------------------------------------------------
	95
	96	const rom_entry *p1_hdc_device::device_rom_region() const
	97	{
	98	return ROM_NAME( p1_hdc );
	99	}
	100
	101
	102	//**************************************************************************
	103	//  LIVE DEVICE
	104	//**************************************************************************
	105
	106
	107	READ8_MEMBER(p1_hdc_device::p1_HDC_r)
	108	{
	109	UINT8 data = 0x00;
	110
	111	switch (offset >> 8) {
	112	case 8:      data = m_hdc->read(space, offset & 255);
	113	}
	114	DBG_LOG(1,"hdc",("R $%04x == $%02x\n", offset, data));
	115
	116	return data;
	117	}
	118
	119	WRITE8_MEMBER(p1_hdc_device::p1_HDC_w)
	120	{
	121	DBG_LOG(1,"hdc",("W $%04x <- $%02x\n", offset, data));
	122	switch (offset >> 8) {
	123	case 8:      m_hdc->write(space, offset & 255, data, 0);
	124	}
	125	}
	126
	127	//-------------------------------------------------
	128	//  p1_hdc_device - constructor
	129	//-------------------------------------------------
	130
	131	p1_hdc_device::p1_hdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	132	device_t(mconfig, P1_HDC, "Poisk-1 MFM disk B942", tag, owner, clock, "p1_hdc", __FILE__),
	133	device_isa8_card_interface( mconfig, *this ),
	134	m_hdc(*this, KM1809VG7_TAG)
	135	{
	136	}
	137
	138
	139	//-------------------------------------------------
	140	//  device_start - device-specific startup
	141	//-------------------------------------------------
	142
	143	void p1_hdc_device::device_start()
	144	{
	145	set_isa_device();
	146	m_isa->install_rom(this, 0xe2000, 0xe27ff, 0, 0, "XXX", "p1_hdc");
	147	m_isa->install_memory(0xd0000, 0xd0fff, 0, 0,
	148	READ8_DELEGATE(p1_hdc_device, p1_HDC_r),
	149	WRITE8_DELEGATE(p1_hdc_device, p1_HDC_w) );
	150	}
	151
	152
	153	//-------------------------------------------------
	154	//  device_reset - device-specific reset
	155	//-------------------------------------------------
	156
	157	void p1_hdc_device::device_reset()
	158	{
	159	}

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trunk/src/mess/machine/p1_hdc.h

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	Poisk-1 HDC device (model B942)
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#pragma once
	13
	14	#ifndef __P1_HDC__
	15	#define __P1_HDC__
	16
	17	#include "emu.h"
	18
	19	#include "imagedev/harddriv.h"
	20	#include "machine/isa.h"
	21	#include "machine/wd2010.h"
	22
	23	//**************************************************************************
	24	//  TYPE DEFINITIONS
	25	//**************************************************************************
	26
	27	class p1_hdc_device : public device_t,
	28	public device_isa8_card_interface
	29	{
	30	public:
	31	// construction/destruction
	32	p1_hdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	33
	34	// optional information overrides
	35	virtual machine_config_constructor device_mconfig_additions() const;
	36	virtual const rom_entry *device_rom_region() const;
	37
	38	protected:
	39	// device-level overrides
	40	virtual void device_start();
	41	virtual void device_reset();
	42
	43	private:
	44	required_device<wd2010_device> m_hdc;
	45
	46	UINT8 m_ram[0x800];
	47
	48	public:
	49	DECLARE_READ8_MEMBER(p1_HDC_r);
	50	DECLARE_WRITE8_MEMBER(p1_HDC_w);
	51	};
	52
	53
	54	// device type definition
	55	extern const device_type P1_HDC;
	56
	57
	58	#endif

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trunk/src/mess/machine/kb_poisk1.h

r0	r26689
	1	/*
	2	* Poisk-1 keyboard
	3	*
	4	* F4 - toggles key click
	5	* RCtrl - toggles Latin/Cyrillic layout
	6	* Keypad / - Pause key
	7	* F11 - XXX
	8	* F12 - XXX
	9	*/
	10
	11	INPUT_PORTS_START( poisk1_keyboard_v89 )
	12	PORT_START("Y1")
	13	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}') // 0x55
	14	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 5") PORT_CODE(KEYCODE_5_PAD)
	15	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_UNUSED )
	16	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?56?") // 0x56
	17	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
	18	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Enter") PORT_CODE(KEYCODE_ENTER) PORT_CHAR('\r')
	19	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 8") PORT_CODE(KEYCODE_8_PAD) PORT_CODE(KEYCODE_UP)
	20	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 2") PORT_CODE(KEYCODE_2_PAD) PORT_CODE(KEYCODE_DOWN)
	21	/*-12*/   PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-12 - ?") /* PORT_CODE(KEYCODE_SLASH) PORT_CHAR('?') PORT_CHAR('/') */
	22	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
	23	/*-11*/   PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-11 - %") /* PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%') */
	24	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F11") PORT_CODE(KEYCODE_F11) PORT_CHAR(UCHAR_MAMEKEY(F11))
	25
	26	PORT_START("Y2")
	27	/*-15*/   PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-15 - !") /* PORT_CODE(KEYCODE_1) PORT_CHAR('!') PORT_CHAR('1') */
	28	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 4") PORT_CODE(KEYCODE_4_PAD) PORT_CODE(KEYCODE_LEFT)
	29	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 0") PORT_CODE(KEYCODE_0_PAD) PORT_CODE(KEYCODE_INSERT) /* ??? */
	30	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F7") PORT_CODE(KEYCODE_F7) PORT_CHAR(UCHAR_MAMEKEY(F7))
	31	/*-13*/   PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-13 - ;") /* PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':') */
	32	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_LEFT) PORT_CODE(KEYCODE_BACKSPACE)
	33	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 7") PORT_CODE(KEYCODE_7_PAD) PORT_CODE(KEYCODE_HOME)
	34	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 1") PORT_CODE(KEYCODE_1_PAD) PORT_CODE(KEYCODE_END)
	35	/*-2*/   PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-2 - .") /* PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>') */
	36	/*-3*/   PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-3 - _") /* PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('_') */
	37	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
	38	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{') // 0x54
	39
	40	PORT_START("Y3")
	41	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
	42	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 9") PORT_CODE(KEYCODE_9_PAD) PORT_CODE(KEYCODE_PGUP)
	43	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 3") PORT_CODE(KEYCODE_3_PAD) PORT_CODE(KEYCODE_PGDN)
	44	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')
	45	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
	46	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
	47	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
	48	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_UNUSED )
	49	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')
	50	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
	51	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
	52	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
	53
	54	PORT_START("Y4")
	55	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F3") PORT_CODE(KEYCODE_F3) PORT_CHAR(UCHAR_MAMEKEY(F3))
	56	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_UNUSED )
	57	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_UNUSED )
	58	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F6") PORT_CODE(KEYCODE_F6) PORT_CHAR(UCHAR_MAMEKEY(F6))
	59	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F2") PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F2))
	60	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F1") PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1))
	61	/*-1*/   PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-1 - *") /* PORT_CODE(KEYCODE_8) PORT_CHAR('*') PORT_CHAR('8') */
	62	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Esc") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC)) /* ??2 */
	63	/*-9*/   PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-9 - :") /* PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':') */
	64	/*-10*/   PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-10 - ,") /* PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<') */
	65	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F5") PORT_CODE(KEYCODE_F5) PORT_CHAR(UCHAR_MAMEKEY(F5))
	66	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F4") PORT_CODE(KEYCODE_F4) PORT_CHAR(UCHAR_MAMEKEY(F4))
	67
	68	PORT_START("Y5")
	69	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
	70	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_UNUSED )
	71	/*?*/   PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_MAMEKEY(RCONTROL))
	72	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
	73	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
	74	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
	75	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
	76	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Caps Lock") PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))    /* ???? */
	77	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
	78	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
	79	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
	80	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
	81
	82	PORT_START("Y6")
	83	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Left Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
	84	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad *") PORT_CODE(KEYCODE_ASTERISK) PORT_CHAR(UCHAR_MAMEKEY(ASTERISK))
	85	/*?*/   PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Alt") PORT_CODE(KEYCODE_RALT)
	86	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
	87	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
	88	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?dc?") // 0xdc = SHIFT2
	89	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Rus/Lat") PORT_CODE(KEYCODE_RALT) // 0xdb = Rus/Lat
	90	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Right Shift") PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
	91	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F12") PORT_CODE(KEYCODE_F12) PORT_CHAR(UCHAR_MAMEKEY(F12))
	92	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?59?") // 0x59
	93	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
	94	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Space") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
	95
	96	PORT_START("Y7")
	97	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_UNUSED )
	98	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("NumLock") PORT_CODE(KEYCODE_NUMLOCK)
	99	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad . Del") PORT_CODE(KEYCODE_DEL_PAD) PORT_CHAR(UCHAR_MAMEKEY(DEL_PAD))
	100	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_UNUSED )
	101	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
	102	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F10") PORT_CODE(KEYCODE_F10) PORT_CHAR(UCHAR_MAMEKEY(F10))
	103	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad +") PORT_CODE(KEYCODE_PLUS_PAD)
	104	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 6") PORT_CODE(KEYCODE_6_PAD) PORT_CODE(KEYCODE_RIGHT)
	105	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
	106	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F8") PORT_CODE(KEYCODE_F8) PORT_CHAR(UCHAR_MAMEKEY(F8))
	107	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?5a?") // 0x5a
	108	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F9") PORT_CODE(KEYCODE_F9) PORT_CHAR(UCHAR_MAMEKEY(F9))
	109
	110	PORT_START("Y8")
	111	/*-6*/   PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-6 - -") /* PORT_CODE(KEYCODE_MINUS)     PORT_CHAR('-') PORT_CHAR('_') */
	112	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad -") PORT_CODE(KEYCODE_MINUS_PAD)
	113	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Tab") PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t')  /* ??? */
	114	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
	115	/*-7*/   PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-7 - )") /* PORT_CODE(KEYCODE_0) PORT_CHAR(')') PORT_CHAR('0') */
	116	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Scroll Lock")
	117	/*-4*/   PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-4 - (") /* PORT_CODE(KEYCODE_9) PORT_CHAR('(') PORT_CHAR('9') */
	118	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|')
	119	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_UNUSED )
	120	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
	121	/*-5*/   PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-5 - \"") /* PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('"') PORT_CHAR('\'') */
	122	/*-8*/   PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("?-8 - /") /* PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') */
	123
	124	#if 0
	125	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Delete") PORT_CODE(KEYCODE_DEL_PAD)
	126	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("* PrtSc") PORT_CODE(KEYCODE_PRTSCR)
	127	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('@')
	128	PORT_BIT( 0x000, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
	129	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
	130	PORT_BIT( 0x000, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('^')
	131	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&')
	132	PORT_BIT( 0x000, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TILDE) PORT_CHAR('`') PORT_CHAR('~')
	133	PORT_BIT( 0x000, IP_ACTIVE_LOW, IPT_KEYBOARD )
	134	#endif
	135
	136	INPUT_PORTS_END
	137
	138	INPUT_PORTS_START( poisk1_keyboard_v91 )
	139	PORT_START("Y1")
	140	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}')
	141	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 5") PORT_CODE(KEYCODE_5_PAD)
	142	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_UNUSED )
	143	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(";") PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
	144	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("+ / CYRILLIC YO") PORT_CODE(KEYCODE_PLUS_PAD)
	145	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Enter") PORT_CODE(KEYCODE_ENTER) PORT_CHAR('\r')
	146	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 8") PORT_CODE(KEYCODE_8_PAD) PORT_CODE(KEYCODE_UP)
	147	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 2") PORT_CODE(KEYCODE_2_PAD) PORT_CODE(KEYCODE_DOWN)
	148	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(")") PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(')')
	149	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
	150	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("-") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('_')
	151	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("'") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('\'') PORT_CHAR('"')
	152
	153	PORT_START("Y2")
	154	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('+')
	155	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 4") PORT_CODE(KEYCODE_4_PAD) PORT_CODE(KEYCODE_LEFT)
	156	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 0") PORT_CODE(KEYCODE_0_PAD) PORT_CODE(KEYCODE_INSERT)
	157	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F6") PORT_CODE(KEYCODE_F6) PORT_CHAR(UCHAR_MAMEKEY(F6))
	158	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|')
	159	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_LEFT) PORT_CODE(KEYCODE_BACKSPACE)
	160	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 7") PORT_CODE(KEYCODE_7_PAD) PORT_CODE(KEYCODE_HOME)
	161	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 1") PORT_CODE(KEYCODE_1_PAD) PORT_CODE(KEYCODE_END)
	162	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("*") PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('*')
	163	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("(") PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR('(')
	164	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
	165	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
	166
	167	PORT_START("Y3")
	168	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
	169	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 9") PORT_CODE(KEYCODE_9_PAD) PORT_CODE(KEYCODE_PGUP)
	170	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 3") PORT_CODE(KEYCODE_3_PAD) PORT_CODE(KEYCODE_PGDN)
	171	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')
	172	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
	173	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
	174	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
	175	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_UNUSED )
	176	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')
	177	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
	178	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
	179	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
	180
	181	PORT_START("Y4")
	182	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F2") PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F2))
	183	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_UNUSED )
	184	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_UNUSED )
	185	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F5") PORT_CODE(KEYCODE_F5) PORT_CHAR(UCHAR_MAMEKEY(F5))
	186	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F1") PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1))
	187	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Esc") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
	188	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TILDE) PORT_CHAR('`') PORT_CHAR('~')
	189	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Pause") PORT_CODE(KEYCODE_SLASH_PAD) PORT_CHAR(UCHAR_MAMEKEY(SLASH_PAD))
	190	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('^')
	191	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&')
	192	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F4") PORT_CODE(KEYCODE_F4) PORT_CHAR(UCHAR_MAMEKEY(F4))
	193	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F3") PORT_CODE(KEYCODE_F3) PORT_CHAR(UCHAR_MAMEKEY(F3))
	194
	195	PORT_START("Y5")
	196	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
	197	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_UNUSED )
	198	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Caps Lock") PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
	199	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
	200	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
	201	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
	202	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
	203	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UKRAINIAN XXX") PORT_CODE(KEYCODE_F12) PORT_CHAR(UCHAR_MAMEKEY(F12))
	204	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
	205	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
	206	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
	207	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
	208
	209	PORT_START("Y6")
	210	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Left Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
	211	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Right Ctrl/Cyril") PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_MAMEKEY(RCONTROL))
	212	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Left Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_MAMEKEY(LCONTROL))
	213	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
	214	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
	215	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Left Alt") PORT_CODE(KEYCODE_LALT)
	216	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Right Alt") PORT_CODE(KEYCODE_RALT)
	217	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Right Shift") PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
	218	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(".") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
	219	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(",") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
	220	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
	221	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Space") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
	222
	223	PORT_START("Y7")
	224	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_UNUSED )
	225	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("NumLock") PORT_CODE(KEYCODE_NUMLOCK)
	226	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad . Del") PORT_CODE(KEYCODE_DEL_PAD) PORT_CHAR(UCHAR_MAMEKEY(DEL_PAD))
	227	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_UNUSED )
	228	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("- / UKRAINIAN XXX") PORT_CODE(KEYCODE_MINUS_PAD)
	229	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F9") PORT_CODE(KEYCODE_F9) PORT_CHAR(UCHAR_MAMEKEY(F9))
	230	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Scroll Lock")
	231	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 6") PORT_CODE(KEYCODE_6_PAD) PORT_CODE(KEYCODE_RIGHT)
	232	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
	233	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F7") PORT_CODE(KEYCODE_F7) PORT_CHAR(UCHAR_MAMEKEY(F7))
	234	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("/") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
	235	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F8") PORT_CODE(KEYCODE_F8) PORT_CHAR(UCHAR_MAMEKEY(F8))
	236
	237	PORT_START("Y8")
	238	PORT_BIT( 0x001, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
	239	PORT_BIT( 0x002, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("* PrtSc") PORT_CODE(KEYCODE_ASTERISK) PORT_CHAR(UCHAR_MAMEKEY(ASTERISK))
	240	PORT_BIT( 0x004, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Tab") PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t')  /* ??? */
	241	PORT_BIT( 0x008, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
	242	PORT_BIT( 0x010, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('@')
	243	PORT_BIT( 0x020, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F10") PORT_CODE(KEYCODE_F10) PORT_CHAR(UCHAR_MAMEKEY(F10))
	244	PORT_BIT( 0x040, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("!") PORT_CODE(KEYCODE_1) PORT_CHAR('!') PORT_CHAR('1')
	245	PORT_BIT( 0x080, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UKRAINIAN XXX") PORT_CODE(KEYCODE_F11) PORT_CHAR(UCHAR_MAMEKEY(F11))
	246	PORT_BIT( 0x100, IP_ACTIVE_LOW, IPT_UNUSED )
	247	PORT_BIT( 0x200, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
	248	PORT_BIT( 0x400, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("%") PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
	249	PORT_BIT( 0x800, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
	250	INPUT_PORTS_END

Property changes on: trunk/src/mess/machine/kb_poisk1.h

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/mess/machine/pc.c

r26688	r26689
17	17
18	18	#include "machine/i8255.h"
19	19	#include "machine/ins8250.h"
20		#include "machine/i8251.h"
21	20	#include "machine/mc146818.h"
22	21	#include "machine/pic8259.h"
23	22
r26688	r26689
66	65	} \
67	66	} while (0)
68	67
69		/*
70		* EC-1841 memory controller.  The machine can hold four memory boards;
71		* each board has a control register, its address is set by a DIP switch
72		* on the board itself.
73		*
74		* Only one board should be enabled for read, and one for write.
75		* Normally, this is the same board.
76		*
77		* Each board is divided into 4 banks, internally numbererd 0..3.
78		* POST tests each board on startup, and an error (indicated by
79		* I/O CH CK bus signal) causes it to disable failing bank(s) by writing
80		* 'reconfiguration code' (inverted number of failing memory bank) to
81		* the register.
82
83		* bit 1-0  'reconfiguration code'
84		* bit 2    enable read access
85		* bit 3    enable write access
86		*/
87
88		READ8_MEMBER(pc_state::ec1841_memboard_r)
89		{
90		pc_state *st = space.machine().driver_data<pc_state>();
91		UINT8 data;
92
93		data = offset % 4;
94		if (data > m_memboards)
95		data = 0xff;
96		else
97		data = st->m_memboard[data];
98		DBG_LOG(1,"ec1841_memboard",("R (%d of %d) == %02X\n", offset, m_memboards, data ));
99
100		return data;
101		}
102
103		WRITE8_MEMBER(pc_state::ec1841_memboard_w)
104		{
105		pc_state *st = space.machine().driver_data<pc_state>();
106		address_space &program = st->m_maincpu->space(AS_PROGRAM);
107		UINT8 current;
108
109		current = st->m_memboard[offset];
110
111		DBG_LOG(1,"ec1841_memboard",("W (%d of %d) <- %02X (%02X)\n", offset, m_memboards, data, current));
112
113		if (offset > m_memboards) {
114		return;
115		}
116
117		if (BIT(current, 2) && !BIT(data, 2)) {
118		// disable read access
119		program.unmap_read(0, 0x7ffff);
120		DBG_LOG(1,"ec1841_memboard_w",("unmap_read(%d)\n", offset));
121		}
122
123		if (BIT(current, 3) && !BIT(data, 3)) {
124		// disable write access
125		program.unmap_write(0, 0x7ffff);
126		DBG_LOG(1,"ec1841_memboard_w",("unmap_write(%d)\n", offset));
127		}
128
129		if (!BIT(current, 2) && BIT(data, 2)) {
130		for(int i=0; i<4; i++)
131		st->m_memboard[i] &= 0xfb;
132		// enable read access
133		membank("bank10")->set_base(m_ram->pointer() + offset*0x80000);
134		program.install_read_bank(0, 0x7ffff, "bank10");
135		DBG_LOG(1,"ec1841_memboard_w",("map_read(%d)\n", offset));
136		}
137
138		if (!BIT(current, 3) && BIT(data, 3)) {
139		for(int i=0; i<4; i++)
140		st->m_memboard[i] &= 0xf7;
141		// enable write access
142		membank("bank20")->set_base(m_ram->pointer() + offset*0x80000);
143		program.install_write_bank(0, 0x7ffff, "bank20");
144		DBG_LOG(1,"ec1841_memboard_w",("map_write(%d)\n", offset));
145		}
146
147		st->m_memboard[offset] = data;
148		}
149
150	68	/*************************************************************************
151	69	*
152	70	*      PC DMA stuff
r26688	r26689
421	339	}
422	340	};
423	341
424		/* MC1502 uses single XTAL for everything -- incl. CGA? check */
425
426		const i8251_interface mc1502_i8251_interface =
427		{
428		/* XXX RxD data are accessible via PPI port C, bit 7 */
429		DEVCB_NULL,
430		DEVCB_NULL,
431		DEVCB_NULL,
432		DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir7_w), /* default handler does nothing */
433		DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir7_w),
434		DEVCB_NULL,
435		DEVCB_NULL  /* XXX SYNDET triggers NMI */
436		};
437
438		WRITE_LINE_MEMBER(pc_state::mc1502_pit8253_out1_changed)
439		{
440		machine().device<i8251_device>("upd8251")->txc_w(state);
441		machine().device<i8251_device>("upd8251")->rxc_w(state);
442		}
443
444		WRITE_LINE_MEMBER(pc_state::mc1502_pit8253_out2_changed)
445		{
446		pc_speaker_set_input( state );
447		m_cassette->output(state ? 1 : -1);
448		}
449
450		const struct pit8253_interface mc1502_pit8253_config =
451		{
452		{
453		{
454		XTAL_16MHz/12,              /* heartbeat IRQ */
455		DEVCB_NULL,
456		DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir0_w)
457		}, {
458		XTAL_16MHz/12,              /* serial port */
459		DEVCB_NULL,
460		DEVCB_DRIVER_LINE_MEMBER(pc_state,mc1502_pit8253_out1_changed)
461		}, {
462		XTAL_16MHz/12,              /* pio port c pin 4, and speaker polling enough */
463		DEVCB_NULL,
464		DEVCB_DRIVER_LINE_MEMBER(pc_state,mc1502_pit8253_out2_changed)
465		}
466		}
467		};
468
469	342	/**********************************************************
470	343	*
471	344	* COM hardware
r26688	r26689
890	763	};
891	764
892	765
893		static struct {
894		UINT8       pulsing;
895		UINT16      mask;       /* input lines */
896		emu_timer   *keyb_signal_timer;
897		} mc1502_keyb;
898
899
900		/* check if any keys are pressed, raise IRQ1 if so */
901
902		TIMER_CALLBACK_MEMBER(pc_state::mc1502_keyb_signal_callback)
903		{
904		UINT8 key = 0;
905
906		key |= ioport("Y1")->read();
907		key |= ioport("Y2")->read();
908		key |= ioport("Y3")->read();
909		key |= ioport("Y4")->read();
910		key |= ioport("Y5")->read();
911		key |= ioport("Y6")->read();
912		key |= ioport("Y7")->read();
913		key |= ioport("Y8")->read();
914		key |= ioport("Y9")->read();
915		key |= ioport("Y10")->read();
916		key |= ioport("Y11")->read();
917		key |= ioport("Y12")->read();
918		//  DBG_LOG(1,"mc1502_k_s_c",("= %02X (%d) %s\n", key, mc1502_keyb.pulsing,
919		//      (key || mc1502_keyb.pulsing) ? " will IRQ" : ""));
920
921		/*
922		If a key is pressed and we're not pulsing yet, start pulsing the IRQ1;
923		keep pulsing while any key is pressed, and pulse one time after all keys
924		are released.
925		*/
926		if (key) {
927		if (mc1502_keyb.pulsing < 2) {
928		mc1502_keyb.pulsing += 2;
929		}
930		}
931
932		if (mc1502_keyb.pulsing) {
933		m_pic8259->ir1_w(mc1502_keyb.pulsing & 1);
934		mc1502_keyb.pulsing--;
935		}
936		}
937
938		WRITE8_MEMBER(pc_state::mc1502_ppi_porta_w)
939		{
940		m_centronics->write(space, 0, data);
941		}
942
943		WRITE8_MEMBER(pc_state::mc1502_ppi_portb_w)
944		{
945		//  DBG_LOG(2,"mc1502_ppi_portb_w",("( %02X )\n", data));
946		m_ppi_portb = data;
947		machine().device<pit8253_device>("pit8253")->gate2_w(BIT(data, 0));
948		pc_speaker_set_spkrdata(BIT(data, 1));
949		m_centronics->strobe_w(BIT(data, 2));
950		m_centronics->autofeed_w(BIT(data, 3));
951		m_centronics->init_prime_w(BIT(data, 4));
952		}
953
954		READ8_MEMBER(pc_state::mc1502_kppi_portc_r)
955		{
956		UINT8 data = 0;
957
958		data |= m_centronics->fault_r() << 4;
959		data |= m_centronics->pe_r() << 5;
960		data |= m_centronics->ack_r() << 6;
961		data |= m_centronics->busy_r() << 7;
962
963		return data;
964		}
965
966		READ8_MEMBER(pc_state::mc1502_ppi_portc_r)
967		{
968		int timer2_output = machine().device<pit8253_device>("pit8253")->get_output(2);
969		int data = 0xff;
970		double tap_val = m_cassette->input();
971
972		//  0x80 -- serial RxD
973		//  0x40 -- CASS IN, also loops back T2OUT (gated by CASWR)
974		data = ( data & ~0x40 ) | ( tap_val < 0 ? 0x40 : 0x00 ) | ( (BIT(m_ppi_portb, 7) && timer2_output) ? 0x40 : 0x00 );
975		//  0x20 -- T2OUT
976		data = ( data & ~0x20 ) | ( timer2_output ? 0x20 : 0x00 );
977		//  0x10 -- SNDOUT
978		data = ( data & ~0x10 ) | ( (BIT(m_ppi_portb, 1) && timer2_output) ? 0x10 : 0x00 );
979
980		//  DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
981		//      data, tap_val, timer2_output, machine().describe_context()));
982		return data;
983		}
984
985		READ8_MEMBER(pc_state::mc1502_kppi_porta_r)
986		{
987		UINT8 key = 0;
988
989		if (mc1502_keyb.mask & 0x0001) { key |= ioport("Y1")->read(); }
990		if (mc1502_keyb.mask & 0x0002) { key |= ioport("Y2")->read(); }
991		if (mc1502_keyb.mask & 0x0004) { key |= ioport("Y3")->read(); }
992		if (mc1502_keyb.mask & 0x0008) { key |= ioport("Y4")->read(); }
993		if (mc1502_keyb.mask & 0x0010) { key |= ioport("Y5")->read(); }
994		if (mc1502_keyb.mask & 0x0020) { key |= ioport("Y6")->read(); }
995		if (mc1502_keyb.mask & 0x0040) { key |= ioport("Y7")->read(); }
996		if (mc1502_keyb.mask & 0x0080) { key |= ioport("Y8")->read(); }
997		if (mc1502_keyb.mask & 0x0100) { key |= ioport("Y9")->read(); }
998		if (mc1502_keyb.mask & 0x0200) { key |= ioport("Y10")->read(); }
999		if (mc1502_keyb.mask & 0x0400) { key |= ioport("Y11")->read(); }
1000		if (mc1502_keyb.mask & 0x0800) { key |= ioport("Y12")->read(); }
1001		key ^= 0xff;
1002		//  DBG_LOG(2,"mc1502_kppi_porta_r",("= %02X\n", key));
1003		return key;
1004		}
1005
1006		WRITE8_MEMBER(pc_state::mc1502_kppi_portb_w)
1007		{
1008		mc1502_keyb.mask &= ~255;
1009		mc1502_keyb.mask |= data ^ 255;
1010		if (!BIT(data, 0))
1011		mc1502_keyb.mask |= 1 << 11;
1012		else
1013		mc1502_keyb.mask &= ~(1 << 11);
1014		//  DBG_LOG(2,"mc1502_kppi_portb_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
1015		}
1016
1017		WRITE8_MEMBER(pc_state::mc1502_kppi_portc_w)
1018		{
1019		mc1502_keyb.mask &= ~(7 << 8);
1020		mc1502_keyb.mask |= ((data ^ 7) & 7) << 8;
1021		//  DBG_LOG(2,"mc1502_kppi_portc_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
1022		}
1023
1024
1025	766	WRITE8_MEMBER(pc_state::pcjr_ppi_portb_w)
1026	767	{
1027	768	/* KB controller port B */
r26688	r26689
1105	846	DEVCB_NULL
1106	847	};
1107	848
1108		I8255_INTERFACE( mc1502_ppi8255_interface )
1109		{
1110		DEVCB_NULL,
1111		DEVCB_DRIVER_MEMBER(pc_state,mc1502_ppi_porta_w),
1112		DEVCB_NULL,
1113		DEVCB_DRIVER_MEMBER(pc_state,mc1502_ppi_portb_w),
1114		DEVCB_DRIVER_MEMBER(pc_state,mc1502_ppi_portc_r),
1115		DEVCB_NULL
1116		};
1117	849
1118		I8255_INTERFACE( mc1502_ppi8255_interface_2 )
1119		{
1120		DEVCB_DRIVER_MEMBER(pc_state,mc1502_kppi_porta_r),
1121		DEVCB_NULL,
1122		DEVCB_NULL,
1123		DEVCB_DRIVER_MEMBER(pc_state,mc1502_kppi_portb_w),
1124		DEVCB_DRIVER_MEMBER(pc_state,mc1502_kppi_portc_r),
1125		DEVCB_DRIVER_MEMBER(pc_state,mc1502_kppi_portc_w)
1126		};
1127
1128
1129	850	/**********************************************************
1130	851	*
1131	852	* NEC uPD765 floppy interface
r26688	r26689
1247	968	return 0x60; // expansion?
1248	969	}
1249	970
1250		/*
1251		* MC1502 uses a FD1793 clone instead of uPD765
1252		*/
1253
1254		READ8_MEMBER(pc_state::mc1502_wd17xx_aux_r)
1255		{
1256		UINT8 data;
1257
1258		data = 0;
1259
1260		return data;
1261		}
1262
1263		WRITE8_MEMBER(pc_state::mc1502_wd17xx_aux_w)
1264		{
1265		fd1793_t *fdc = machine().device<fd1793_t>("vg93");
1266		floppy_image_device *floppy0 = machine().device<floppy_connector>("fd0")->get_device();
1267		floppy_image_device *floppy1 = machine().device<floppy_connector>("fd1")->get_device();
1268		floppy_image_device *floppy = ((data & 0x10)?floppy1:floppy0);
1269		fdc->set_floppy(floppy);
1270
1271		// master reset
1272		if((data & 1) == 0)
1273		fdc->reset();
1274
1275		// SIDE ONE
1276		floppy->ss_w((data & 2)?1:0);
1277
1278		// bits 2, 3 -- motor on (drive 0, 1)
1279		floppy0->mon_w(!(data & 4));
1280		floppy1->mon_w(!(data & 8));
1281		}
1282
1283		/*
1284		* Accesses to this port block (halt the CPU until DRQ, INTRQ or MOTOR ON)
1285		*/
1286		READ8_MEMBER(pc_state::mc1502_wd17xx_drq_r)
1287		{
1288		fd1793_t *fdc = machine().device<fd1793_t>("vg93");
1289
1290		if (!fdc->drq_r() && !fdc->intrq_r()) {
1291		/* fake cpu wait by resetting PC one insn back */
1292		m_maincpu->set_state_int(I8086_IP, m_maincpu->state_int(I8086_IP) - 1);
1293		m_maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
1294		}
1295
1296		return fdc->drq_r();
1297		}
1298
1299		void pc_state::mc1502_fdc_irq_drq(bool state)
1300		{
1301		if(state)
1302		m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
1303		}
1304
1305		READ8_MEMBER(pc_state::mc1502_wd17xx_motor_r)
1306		{
1307		UINT8 data;
1308
1309		/* fake motor being always on */
1310		data = 1;
1311
1312		return data;
1313		}
1314
1315	971	WRITE8_MEMBER(pc_state::asst128_fdc_dor_w)
1316	972	{
1317	973	pc_fdc_xt_device *fdc = machine().device<pc_fdc_xt_device>("fdc");
r26688	r26689
1445	1101	mess_init_pc_common(pcjr_set_keyb_int);
1446	1102	}
1447	1103
1448		DRIVER_INIT_MEMBER(pc_state,mc1502)
1449		{
1450		mess_init_pc_common(NULL);
1451		}
1452	1104
1453		DRIVER_INIT_MEMBER(pc_state,ec1841)
1454		{
1455		address_space &program = m_maincpu->space(AS_PROGRAM);
1456
1457		program.install_read_bank(0, 0x7ffff, "bank10");
1458		program.install_write_bank(0, 0x7ffff, "bank20");
1459		membank( "bank10" )->set_base( m_ram->pointer() );
1460		membank( "bank20" )->set_base( m_ram->pointer() );
1461
1462		pc_rtc_init();
1463		}
1464
1465
1466	1105	IRQ_CALLBACK_MEMBER(pc_state::pc_irq_callback)
1467	1106	{
1468	1107	return m_pic8259->acknowledge();
r26688	r26689
1499	1138	m_ppi_shift_enable = 0;
1500	1139
1501	1140	m_speaker->level_w(0);
1502
1503		// ec1841-specific code
1504		m_memboards = m_ram->size()/(512*1024) - 1;
1505		if (m_memboards > 3)
1506		m_memboards = 3;
1507		memset(m_memboard,0,sizeof(m_memboard));
1508		// mark 1st board enabled
1509		m_memboard[0]=0xc;
1510	1141	}
1511	1142
1512	1143
1513		MACHINE_START_MEMBER(pc_state,mc1502)
1514		{
1515		m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(pc_state::pc_irq_callback),this));
1516
1517		/*
1518		Keyboard polling circuit holds IRQ1 high until a key is
1519		pressed, then it starts a timer that pulses IRQ1 low each
1520		40ms (check) for 20ms (check) until all keys are released.
1521		Last pulse causes BIOS to write a 'break' scancode into port 60h.
1522		*/
1523		m_pic8259->ir1_w(1);
1524		memset(&mc1502_keyb, 0, sizeof(mc1502_keyb));
1525		mc1502_keyb.keyb_signal_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pc_state::mc1502_keyb_signal_callback),this));
1526		mc1502_keyb.keyb_signal_timer->adjust( attotime::from_msec(20), 0, attotime::from_msec(20) );
1527
1528		fd1793_t *fdc = machine().device<fd1793_t>("vg93");
1529		fdc->setup_drq_cb(fd1793_t::line_cb(FUNC(pc_state::mc1502_fdc_irq_drq), this));
1530		fdc->setup_intrq_cb(fd1793_t::line_cb(FUNC(pc_state::mc1502_fdc_irq_drq), this));
1531		}
1532
1533
1534	1144	MACHINE_START_MEMBER(pc_state,pcjr)
1535	1145	{
1536	1146	pc_int_delay_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pc_state::pcjr_delayed_pic8259_irq),this));

trunk/src/mess/machine/genpc.c

r26688	r26689
879	879	m_ppi_clock_signal = ( m_ppi_keyb_clock ) ? 1 : 0;
880	880	m_pc_kbdc->clock_write_from_mb(m_ppi_clock_signal);
881	881	}
	882
	883	//**************************************************************************
	884	//  GLOBAL VARIABLES
	885	//**************************************************************************
	886
	887	const device_type EC1841_MOTHERBOARD = &device_creator<ec1841_mb_device>;
	888
	889	static MACHINE_CONFIG_FRAGMENT( ec1841_mb_config )
	890	MCFG_FRAGMENT_ADD(ibm5160_mb_config)
	891
	892	MCFG_DEVICE_REMOVE("pc_kbdc")
	893	MCFG_PC_KBDC_ADD("pc_kbdc", pc_kbdc_intf_5150)
	894	MACHINE_CONFIG_END
	895
	896
	897	//-------------------------------------------------
	898	//  machine_config_additions - device-specific
	899	//  machine configurations
	900	//-------------------------------------------------
	901
	902	machine_config_constructor ec1841_mb_device::device_mconfig_additions() const
	903	{
	904	return MACHINE_CONFIG_NAME( ec1841_mb_config );
	905	}
	906
	907	static INPUT_PORTS_START( ec1841_mb )
	908	PORT_START("DSW0") /* SA1 */
	909	PORT_DIPNAME( 0xc0, 0x40, "Number of floppy drives")
	910	PORT_DIPSETTING(    0x00, "1" )
	911	PORT_DIPSETTING(    0x40, "2" )
	912	PORT_DIPSETTING(    0x80, "3" )
	913	PORT_DIPSETTING(    0xc0, "4" )
	914	PORT_DIPNAME( 0x30, 0x20, "Graphics adapter")
	915	PORT_DIPSETTING(    0x00, "Reserved" )
	916	PORT_DIPSETTING(    0x10, "Color 40x25" )
	917	PORT_DIPSETTING(    0x20, "Color 80x25" )
	918	PORT_DIPSETTING(    0x30, "Monochrome" )
	919	PORT_BIT(     0x08, 0x08, IPT_UNUSED )
	920	/* BIOS does not support booting from QD floppies */
	921	PORT_DIPNAME( 0x04, 0x04, "Floppy type")
	922	PORT_DIPSETTING(    0x00, "80 tracks" )
	923	PORT_DIPSETTING(    0x04, "40 tracks" )
	924	PORT_DIPNAME( 0x02, 0x00, "8087 installed")
	925	PORT_DIPSETTING(    0x00, DEF_STR(No) )
	926	PORT_DIPSETTING(    0x02, DEF_STR(Yes) )
	927	PORT_DIPNAME( 0x01, 0x01, "Boot from floppy")
	928	PORT_DIPSETTING(    0x01, DEF_STR(Yes) )
	929	PORT_DIPSETTING(    0x00, DEF_STR(No) )
	930
	931	PORT_START("SA2")
	932	PORT_DIPNAME( 0x04, 0x04, "Speech synthesizer")
	933	PORT_DIPSETTING(    0x00, "Installed" )
	934	PORT_DIPSETTING(    0x04, "Not installed" )
	935	INPUT_PORTS_END
	936
	937	//-------------------------------------------------
	938	//  input_ports - device-specific input ports
	939	//-------------------------------------------------
	940
	941	ioport_constructor ec1841_mb_device::device_input_ports() const
	942	{
	943	return INPUT_PORTS_NAME( ec1841_mb );
	944	}
	945
	946	//**************************************************************************
	947	//  LIVE DEVICE
	948	//**************************************************************************
	949
	950	//-------------------------------------------------
	951	//  ec1841_mb_device - constructor
	952	//-------------------------------------------------
	953
	954	ec1841_mb_device::ec1841_mb_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	955	: ibm5160_mb_device(mconfig, tag, owner, clock)
	956	{
	957	}
	958
	959	void ec1841_mb_device::device_start()
	960	{
	961	ibm5160_mb_device::device_start();
	962	}
	963	void ec1841_mb_device::device_reset()
	964	{
	965	ibm5160_mb_device::device_reset();
	966	}
	967
	968	// kbd interface is 5150-like but PB2 controls access to second bank of DIP switches (SA2).
	969	WRITE8_MEMBER( ec1841_mb_device::pc_ppi_portb_w )
	970	{
	971	/* KB controller port B */
	972	m_ppi_portb = data;
	973	m_ppi_portc_switch_high = data & 0x04;
	974	m_ppi_keyboard_clear = data & 0x80;
	975	m_ppi_keyb_clock = data & 0x40;
	976	m_pit8253->gate2_w(BIT(data, 0));
	977	pc_speaker_set_spkrdata( data & 0x02 );
	978
	979	/* If PB7 is set clear the shift register and reset the IRQ line */
	980	if ( m_ppi_keyboard_clear )
	981	{
	982	m_ppi_shift_register = 0;
	983	m_ppi_shift_enable = 0;
	984	m_pic8259->ir1_w(m_ppi_shift_enable);
	985	}
	986
	987	m_pc_kbdc->data_write_from_mb(!m_ppi_shift_enable);
	988	m_ppi_clock_signal = ( m_ppi_keyb_clock ) ? 1 : 0;
	989	m_pc_kbdc->clock_write_from_mb(m_ppi_clock_signal);
	990	}
	991
	992	READ8_MEMBER ( ec1841_mb_device::pc_ppi_portc_r )
	993	{
	994	int timer2_output = m_pit8253->get_output(2);
	995	int data=0xff;
	996
	997	data&=~0x80; // no parity error
	998	data&=~0x40; // no error on expansion board
	999
	1000	if (m_ppi_portc_switch_high)
	1001	{
	1002	data = (data & 0xf0) | (ioport("SA2")->read() & 0x0f);
	1003	}
	1004
	1005	data = ( data & ~0x20 ) | ( timer2_output ? 0x20 : 0x00 );
	1006
	1007	return data;
	1008	}

trunk/src/mess/machine/isbc_215g.c

r0	r26689
	1	// license:BSD-3-Clause
	2
	3	// TODO: multibus
	4
	5	#include "isbc_215g.h"
	6
	7	const device_type ISBC_215G = &device_creator<isbc_215g_device>;
	8
	9	isbc_215g_device::isbc_215g_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	10	device_t(mconfig, ISBC_215G, "ISBC 215G Winchester Disk Controller", tag, owner, clock, "isbc_215g", __FILE__),
	11	m_dmac(*this, "u84"),
	12	m_hdd0(*this, "drive0"),
	13	m_hdd1(*this, "drive1"),
	14	m_out_irq_func(*this)
	15	{
	16	}
	17
	18	void isbc_215g_device::find_sector()
	19	{
	20	//sector id
	21	// 0/6-7: sector type - 0-data, 1-alternate, 2-bad, 3-invalid
	22	// 0/4-5: size - 128<<n
	23	// 0/0-3: cyl high
	24	// 1:     cyl low
	25	// 2:     head
	26	// 3:     sector
	27	UINT16 cyl = ((m_idcompare[0] & 0xf) << 8) | m_idcompare[1];
	28	harddisk_image_device *drive = (m_drive ? m_hdd1 : m_hdd0);
	29	UINT16 bps = 128 << ((m_idcompare[0] >> 4) & 3);
	30
	31	if(!m_geom[m_drive])
	32	return;
	33
	34	if(m_cyl[m_drive] != cyl)
	35	return;
	36
	37	if((m_idcompare[3] != m_head) || (m_head > m_geom[m_drive]->heads))
	38	return;
	39
	40	if(m_idcompare[2] > m_geom[m_drive]->sectors)
	41	return;
	42
	43	if(bps != m_geom[m_drive]->sectorbytes)
	44	return;
	45
	46	if(m_idcompare[0] >> 6)
	47	return;
	48
	49	m_idfound = true;
	50	hard_disk_read(drive->get_hard_disk_file(), (cyl * m_geom[m_drive]->heads + m_head) * m_geom[m_drive]->sectors + m_idcompare[2], m_sector);
	51	m_secoffset = 0;
	52	return;
	53	}
	54
	55	UINT16 isbc_215g_device::read_sector()
	56	{
	57	UINT16 bps = 64 << ((m_idcompare[0] >> 4) & 3);
	58	if(m_secoffset >= bps)
	59	return 0;
	60	return m_sector[m_secoffset++];
	61	}
	62
	63	READ16_MEMBER(isbc_215g_device::io_r)
	64	{
	65	UINT16 data = 0;
	66	switch(offset)
	67	{
	68	case 0x00:
	69	//read status
	70	// 0: gnd
	71	// 1: drive ready
	72	// 2: seek done
	73	// 3: sector sync found
	74	// 4: fault
	75	// 5: bus ack
	76	// 6: sector id not found or bad ecc
	77	// 7: timeout
	78	// 8: sbx 1 present
	79	// 9: sbx 1 int 0
	80	// a: sbx 1 int 1
	81	// b: sbx 1 opt 0
	82	// c: sbx 1 opt 1
	83	// d: illegal req/vendor 2
	84	// e: drive req
	85	// f: index latch
	86	data |= (!m_idfound) << 6;
	87	data |= m_index << 15;
	88	break;
	89	case 0x04:
	90	//read status 2
	91	// 0: sbx 2 present
	92	// 1: sbx 2 int 0
	93	// 2: sbx 2 int 1
	94	// 3: sbx 2 opt 0
	95	// 4: sbx 2 opt 1
	96	// 5: vendor bit 0
	97	// 6: track 0/busy
	98	// 7: wp
	99	data |= (!m_cyl[m_drive]) ? 0 : 0x40;
	100	break;
	101	case 0x08:
	102	//cmd data bus
	103	break;
	104	case 0x0c:
	105	// reset channel 2
	106	if(space.debugger_access()) // reading this is bad
	107	break;
	108	m_dmac->sel_w(1);
	109	m_dmac->ca_w(1);
	110	m_dmac->ca_w(0);
	111	m_dmac->sel_w(0);
	112	break;
	113	case 0x10:
	114	//pit ch 0
	115	break;
	116	case 0x11:
	117	//pit ch 1
	118	break;
	119	case 0x12:
	120	//pit ch 2
	121	break;
	122	case 0x14:
	123	//read buffer
	124	if(m_rdgate && !m_amsrch && m_geom[m_drive])
	125	data = read_sector();
	126	break;
	127	case 0x18:
	128	//vendor bit 1,3-4
	129	data |= 3<<4 | 2;
	130	break;
	131	default:
	132	logerror("isbc_215g: invalid port read 0x80%02x\n", offset*2);
	133	break;
	134	}
	135	return data;
	136	}
	137
	138	WRITE16_MEMBER(isbc_215g_device::io_w)
	139	{
	140	switch(offset)
	141	{
	142	case 0x00:
	143	//control, 0x8002 doesn't set gates or search
	144	// 0: wr gate
	145	// 1: rd gate
	146	// 2: address mark search
	147	// 3: cmd bus enable
	148	// 4: drive sel/head sel 2
	149	// 5: safe/head sel 1
	150	// 6: b ack
	151	// 7: drive reg addr 0/step dir
	152	// 8: drive reg addr 1
	153	// 9: cmd/rd
	154	// a: para/head sel 0
	155	m_wrgate = data & 1;
	156	m_rdgate = (data >> 1) & 1;
	157	m_amsrch = (data >> 2) & 1;
	158	if(m_wrgate && (m_rdgate || m_amsrch))
	159	logerror("isbc_215g: both write gate and read gate and/or address search enabled\n");
	160	else if(m_rdgate && m_amsrch)
	161	find_sector();
	162	else if(m_amsrch)
	163	logerror("isbc_215g: address search without read gate\n");
	164	case 0x01:
	165	m_stepdir = (data & 0x80) ? 0 : 1;
	166	break;
	167	case 0x04:
	168	//clear index and id latch
	169	m_index = false;
	170	m_idfound = false;
	171	break;
	172	case 0x08:
	173	//cmd data bus/head sel
	174	m_head = data & 3;
	175	m_out_irq_func((data & 0x100) ? 1 : 0);
	176	break;
	177	case 0x0c:
	178	//unit select
	179	// 0: step/wr
	180	// 1: sbx 1 opt 0/1
	181	// 2: sbx 2 opt 0/1
	182	// 3: unit select 0
	183	// 4: unit select 1
	184	// 5: extr 2
	185	// 6: format
	186	// 7: format wr gate
	187	m_drive = (data >> 3) & 1; // st406 two drives only
	188	break;
	189	case 0x10:
	190	//pit ch 0
	191	break;
	192	case 0x11:
	193	//pit ch 1
	194	break;
	195	case 0x12:
	196	//pit ch 2
	197	break;
	198	case 0x13:
	199	//pit control
	200	break;
	201	case 0x14:
	202	//write buffer
	203	break;
	204	case 0x18:
	205	//sector id/format
	206	m_idcompare[1] = data & 0xff;
	207	m_idcompare[0] = data >> 8;
	208	break;
	209	case 0x1c:
	210	//sector id low
	211	m_idcompare[3] = data & 0xff;
	212	m_idcompare[2] = data >> 8;
	213	break;
	214	default:
	215	logerror("isbc_215g: invalid port write 0x80%02x\n", offset*2);
	216	break;
	217	}
	218	}
	219
	220	READ16_MEMBER(isbc_215g_device::mem_r)
	221	{
	222	// XXX: hack to permit debugger to disassemble rom
	223	if(space.debugger_access() && (offset < 0x1fff))
	224	return m_dmac->space(AS_IO).read_word_unaligned(offset*2);
	225
	226	switch(offset)
	227	{
	228	case 0x7fffb:
	229	return 1;
	230	case 0x7fffc:
	231	return 0;
	232	case 0x7fffd:
	233	return m_wakeup;
	234	default:
	235	return m_maincpu_mem->read_word_unaligned(offset*2, mem_mask);
	236	}
	237	}
	238
	239	WRITE16_MEMBER(isbc_215g_device::mem_w)
	240	{
	241	m_maincpu_mem->write_word_unaligned(offset*2, data, mem_mask);
	242	}
	243
	244	static ADDRESS_MAP_START(isbc_215g_mem, AS_PROGRAM, 16, isbc_215g_device)
	245	AM_RANGE(0x00000, 0xfffff) AM_READWRITE(mem_r, mem_w)
	246	ADDRESS_MAP_END
	247
	248	static ADDRESS_MAP_START(isbc_215g_io, AS_IO, 16, isbc_215g_device)
	249	AM_RANGE(0x0000, 0x3fff) AM_ROM AM_REGION("i8089", 0)
	250	AM_RANGE(0x4000, 0x47ff) AM_MIRROR(0x3800) AM_RAM
	251	AM_RANGE(0x8000, 0x8039) AM_MIRROR(0x3fc0) AM_READWRITE(io_r, io_w)
	252	AM_RANGE(0xc070, 0xc08f) AM_DEVREADWRITE8("sbx1", isbx_slot_device, mcs0_r, mcs0_w, 0x00ff)
	253	AM_RANGE(0xc0b0, 0xc0bf) AM_DEVREADWRITE8("sbx1", isbx_slot_device, mcs1_r, mcs1_w, 0x00ff)
	254	AM_RANGE(0xc0d0, 0xc0df) AM_DEVREADWRITE8("sbx2", isbx_slot_device, mcs0_r, mcs0_w, 0x00ff)
	255	AM_RANGE(0xc0e0, 0xc0ef) AM_DEVREADWRITE8("sbx2", isbx_slot_device, mcs1_r, mcs1_w, 0x00ff)
	256	ADDRESS_MAP_END
	257
	258	static MACHINE_CONFIG_FRAGMENT( isbc_215g )
	259	MCFG_CPU_ADD("u84", I8089, XTAL_15MHz / 3)
	260	MCFG_CPU_PROGRAM_MAP(isbc_215g_mem)
	261	MCFG_CPU_IO_MAP(isbc_215g_io)
	262	MCFG_I8089_DATABUS_WIDTH(16)
	263
	264	MCFG_HARDDISK_ADD("drive0")
	265	MCFG_HARDDISK_ADD("drive1")
	266
	267	MCFG_ISBX_SLOT_ADD("sbx1", 0, isbx_cards, NULL)
	268	MCFG_ISBX_SLOT_ADD("sbx2", 0, isbx_cards, NULL)
	269	MACHINE_CONFIG_END
	270
	271	machine_config_constructor isbc_215g_device::device_mconfig_additions() const
	272	{
	273	return MACHINE_CONFIG_NAME( isbc_215g );
	274	}
	275
	276	ROM_START( isbc_215g )
	277	ROM_REGION( 0x4000, "i8089", ROMREGION_ERASEFF )
	278	ROM_LOAD16_BYTE( "174581.001.bin", 0x0000, 0x2000, CRC(ccdbc7ab) SHA1(5c2ebdde1b0252124177221ba9cacdb6d925a24d))
	279	ROM_LOAD16_BYTE( "174581.002.bin", 0x0001, 0x2000, CRC(6190fa67) SHA1(295dd4e75f699aaf93227cc4876cee8accae383a))
	280	ROM_END
	281
	282	const rom_entry *isbc_215g_device::device_rom_region() const
	283	{
	284	return ROM_NAME( isbc_215g );
	285	}
	286
	287	void isbc_215g_device::device_reset()
	288	{
	289	if(m_hdd0->get_hard_disk_file())
	290	m_geom[0] = hard_disk_get_info(m_hdd0->get_hard_disk_file());
	291	else
	292	m_geom[0] = 0;
	293	if(m_hdd1->get_hard_disk_file())
	294	m_geom[1] = hard_disk_get_info(m_hdd1->get_hard_disk_file());
	295	else
	296	m_geom[1] = 0;
	297	}
	298
	299	void isbc_215g_device::device_start()
	300	{
	301	m_maincpu_mem = &machine().device<cpu_device>(m_maincpu_tag)->space(AS_PROGRAM);
	302	m_cyl[0] = m_cyl[1] = 0;
	303	m_idcompare[0] = m_idcompare[1] = m_idcompare[2] = m_idcompare[3] = 0;
	304	m_index = false;
	305	m_idfound = false;
	306	m_drive = 0;
	307	m_head = 0;
	308	m_stepdir = false;
	309	m_out_irq_func.resolve_safe();
	310	}
	311
	312	WRITE8_MEMBER(isbc_215g_device::write)
	313	{
	314	if(!offset)
	315	{
	316	if(!data && (m_reset == 2))
	317	m_dmac->reset();
	318	m_out_irq_func(0);
	319	m_dmac->ca_w(data != 2);
	320	m_dmac->ca_w(0);
	321	m_reset = data;
	322	}
	323	}

Property changes on: trunk/src/mess/machine/isbc_215g.c

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trunk/src/mess/machine/isbc_215g.h

r0	r26689
	1	// license:BSD-3-Clause
	2
	3	#ifndef ISBC_215G_H_
	4	#define ISBC_215G_H_
	5
	6	#include "emu.h"
	7	#include "cpu/i8089/i8089.h"
	8	#include "bus/isbx/isbx.h"
	9	#include "imagedev/harddriv.h"
	10
	11	class isbc_215g_device : public device_t
	12	{
	13	public:
	14	isbc_215g_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	15
	16	virtual machine_config_constructor device_mconfig_additions() const;
	17	const rom_entry *device_rom_region() const;
	18
	19	DECLARE_WRITE8_MEMBER(write);
	20	DECLARE_READ16_MEMBER(io_r);
	21	DECLARE_WRITE16_MEMBER(io_w);
	22	DECLARE_READ16_MEMBER(mem_r);
	23	DECLARE_WRITE16_MEMBER(mem_w);
	24
	25	static void static_set_wakeup_addr(device_t &device, UINT32 wakeup) { downcast<isbc_215g_device &>(device).m_wakeup = wakeup; }
	26	static void static_set_maincpu_tag(device_t &device, const char *maincpu_tag) { downcast<isbc_215g_device &>(device).m_maincpu_tag = maincpu_tag; }
	27	template<class _Object> static devcb2_base &static_set_irq_callback(device_t &device, _Object object) { return downcast<isbc_215g_device &>(device).m_out_irq_func.set_callback(object); }
	28
	29	protected:
	30	virtual void device_start();
	31	virtual void device_reset();
	32
	33	private:
	34	void find_sector();
	35	UINT16 read_sector();
	36
	37	required_device<i8089_device> m_dmac;
	38	required_device<harddisk_image_device> m_hdd0;
	39	required_device<harddisk_image_device> m_hdd1;
	40	devcb2_write_line m_out_irq_func;
	41
	42	int m_reset;
	43	UINT16 m_wakeup, m_secoffset, m_sector[512];
	44	const char *m_maincpu_tag;
	45	address_space *m_maincpu_mem;
	46	UINT16 m_cyl[2];
	47	UINT8 m_idcompare[4], m_drive, m_head;
	48	bool m_idfound, m_index, m_stepdir, m_wrgate, m_rdgate, m_amsrch;
	49
	50	const struct hard_disk_info* m_geom[2];
	51	};
	52
	53	#define MCFG_ISBC_215_ADD(_tag, _wakeup, _maincpu_tag) \
	54	MCFG_DEVICE_ADD(_tag, ISBC_215G, 0) \
	55	isbc_215g_device::static_set_wakeup_addr(*device, _wakeup); \
	56	isbc_215g_device::static_set_maincpu_tag(*device, _maincpu_tag);
	57
	58	#define MCFG_ISBC_215_IRQ(_irq_line) \
	59	devcb = &isbc_215g_device::static_set_irq_callback(*device, DEVCB2_##_irq_line);
	60
	61	extern const device_type ISBC_215G;
	62
	63	#endif /* ISBC_215G_H_ */

Property changes on: trunk/src/mess/machine/isbc_215g.h

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trunk/src/mess/machine/mc1502_fdc.c

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	Electronika MC 1502 FDC device
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#include "mc1502_fdc.h"
	13
	14	#include "cpu/i86/i86.h"
	15	#include "formats/dsk_dsk.h"
	16	#include "formats/pc_dsk.h"
	17
	18	#define VERBOSE_DBG 0
	19
	20	#define DBG_LOG(N,M,A) \
	21	do { \
	22	if(VERBOSE_DBG>=N) \
	23	{ \
	24	if( M ) \
	25	logerror("%11.6f: %-24s",machine().time().as_double(),(char*)M ); \
	26	logerror A; \
	27	} \
	28	} while (0)
	29
	30
	31	//**************************************************************************
	32	//  DEVICE DEFINITIONS
	33	//**************************************************************************
	34
	35	const device_type MC1502_FDC = &device_creator<mc1502_fdc_device>;
	36
	37	static DECLARE_READ8_DEVICE_HANDLER(mc1502_FDC_r);
	38	static DECLARE_WRITE8_DEVICE_HANDLER(mc1502_FDC_w);
	39
	40	FLOPPY_FORMATS_MEMBER( mc1502_fdc_device::floppy_formats )
	41	FLOPPY_PC_FORMAT,
	42	FLOPPY_DSK_FORMAT
	43	FLOPPY_FORMATS_END
	44
	45	static SLOT_INTERFACE_START( mc1502_floppies )
	46	SLOT_INTERFACE( "525qd", FLOPPY_525_QD )
	47	SLOT_INTERFACE_END
	48
	49	static MACHINE_CONFIG_FRAGMENT( mc1502_fdc )
	50	MCFG_FD1793x_ADD("fdc", XTAL_16MHz / 16)
	51	MCFG_FLOPPY_DRIVE_ADD("fdc:0", mc1502_floppies, "525qd", mc1502_fdc_device::floppy_formats)
	52	MCFG_FLOPPY_DRIVE_ADD("fdc:1", mc1502_floppies, "525qd", mc1502_fdc_device::floppy_formats)
	53	MACHINE_CONFIG_END
	54
	55	//-------------------------------------------------
	56	//  ROM( mc1502_fdc )
	57	//-------------------------------------------------
	58
	59	ROM_START( mc1502_fdc )
	60	ROM_END
	61
	62
	63	//-------------------------------------------------
	64	//  machine_config_additions - device-specific
	65	//  machine configurations
	66	//-------------------------------------------------
	67
	68	machine_config_constructor mc1502_fdc_device::device_mconfig_additions() const
	69	{
	70	return MACHINE_CONFIG_NAME( mc1502_fdc );
	71	}
	72
	73	//-------------------------------------------------
	74	//  rom_region - device-specific ROM region
	75	//-------------------------------------------------
	76
	77	const rom_entry *mc1502_fdc_device::device_rom_region() const
	78	{
	79	return ROM_NAME( mc1502_fdc );
	80	}
	81
	82
	83	//**************************************************************************
	84	//  LIVE DEVICE
	85	//**************************************************************************
	86
	87	TIMER_CALLBACK_MEMBER(mc1502_fdc_device::motor_callback)
	88	{
	89	m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(ASSERT_LINE);
	90	m_fdc->subdevice<floppy_connector>("1")->get_device()->mon_w(ASSERT_LINE);
	91	motor_on = 0;
	92	}
	93
	94	UINT8 mc1502_fdc_device::mc1502_wd17xx_aux_r()
	95	{
	96	UINT8 data;
	97
	98	data = 0;
	99
	100	return data;
	101	}
	102
	103	void mc1502_fdc_device::mc1502_wd17xx_aux_w(UINT8 data)
	104	{
	105	floppy_image_device *floppy0 = m_fdc->subdevice<floppy_connector>("0")->get_device();
	106	floppy_image_device *floppy1 = m_fdc->subdevice<floppy_connector>("1")->get_device();
	107	floppy_image_device *floppy = ((data & 0x10)?floppy1:floppy0);
	108
	109	// master reset
	110	if((data & 1) == 0)
	111	m_fdc->reset();
	112
	113	m_fdc->set_floppy(floppy);
	114
	115	// SIDE ONE
	116	floppy->ss_w((data & 2)?1:0);
	117
	118	// bits 2, 3 -- motor on (drive 0, 1)
	119	floppy0->mon_w(!(data & 4));
	120	floppy1->mon_w(!(data & 8));
	121
	122	if (data & 12) {
	123	motor_timer->adjust(attotime::from_msec( 3000 ));
	124	motor_on = 1;
	125	}
	126
	127	}
	128
	129	/*
	130	* Accesses to this port block (halt the CPU until DRQ, INTRQ or MOTOR ON)
	131	*/
	132	UINT8 mc1502_fdc_device::mc1502_wd17xx_drq_r()
	133	{
	134	cpu_device *maincpu = machine().device<cpu_device>("maincpu");
	135
	136	if (!m_fdc->drq_r() && !m_fdc->intrq_r()) {
	137	// fake cpu wait by resetting PC one insn back
	138	maincpu->set_state_int(I8086_IP, maincpu->state_int(I8086_IP) - 1);
	139	maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	140	}
	141
	142	return m_fdc->drq_r();
	143	}
	144
	145	UINT8 mc1502_fdc_device::mc1502_wd17xx_motor_r()
	146	{
	147	return motor_on;
	148	}
	149
	150	void mc1502_fdc_device::mc1502_fdc_irq_drq(bool state)
	151	{
	152	cpu_device *maincpu = machine().device<cpu_device>("maincpu");
	153
	154	if(state)
	155	maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	156	}
	157
	158	static READ8_DEVICE_HANDLER( mc1502_FDC_r )
	159	{
	160	UINT8 data = 0xff;
	161	mc1502_fdc_device *fdc  = downcast<mc1502_fdc_device *>(device);
	162
	163	switch( offset )
	164	{
	165	case 0: data = fdc->mc1502_wd17xx_aux_r();     break;
	166	case 8: data = fdc->mc1502_wd17xx_drq_r();     break;
	167	case 10: data = fdc->mc1502_wd17xx_motor_r();   break;
	168	}
	169
	170	return data;
	171	}
	172
	173	static WRITE8_DEVICE_HANDLER( mc1502_FDC_w )
	174	{
	175	mc1502_fdc_device *fdc  = downcast<mc1502_fdc_device *>(device);
	176
	177	switch( offset )
	178	{
	179	case 0: fdc->mc1502_wd17xx_aux_w(data);    break;
	180	}
	181	}
	182
	183	//-------------------------------------------------
	184	//  mc1502_fdc_device - constructor
	185	//-------------------------------------------------
	186
	187	mc1502_fdc_device::mc1502_fdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	188	device_t(mconfig, MC1502_FDC, "MC-1502 floppy", tag, owner, clock, "mc1502_fdc", __FILE__),
	189	device_isa8_card_interface( mconfig, *this ),
	190	m_fdc(*this, "fdc")
	191	{
	192	}
	193
	194	#if 0
	195	AM_RANGE(0x004c, 0x004c) AM_READWRITE(mc1502_wd17xx_aux_r, mc1502_wd17xx_aux_w)
	196	AM_RANGE(0x004d, 0x004d) AM_READ(mc1502_wd17xx_motor_r)
	197	AM_RANGE(0x004e, 0x004e) AM_READ(mc1502_wd17xx_drq_r)           // blocking read!
	198	AM_RANGE(0x0048, 0x004b) AM_DEVREADWRITE("vg93", fd1793_t, read, write)
	199
	200	AM_RANGE(0x0100, 0x0100) AM_READWRITE(mc1502_wd17xx_aux_r, mc1502_wd17xx_aux_w)
	201	AM_RANGE(0x0108, 0x0108) AM_READ(mc1502_wd17xx_drq_r)           // blocking read!
	202	AM_RANGE(0x010a, 0x010a) AM_READ(mc1502_wd17xx_motor_r)
	203	AM_RANGE(0x010c, 0x010f) AM_DEVREADWRITE("vg93", fd1793_t, read, write)
	204	#endif
	205
	206	//-------------------------------------------------
	207	//  device_start - device-specific startup
	208	//-------------------------------------------------
	209
	210	void mc1502_fdc_device::device_start()
	211	{
	212	set_isa_device();
	213
	214	// BIOS 5.0, 5.2
	215	m_isa->install_device(0x010c, 0x010f, 0, 0,
	216	READ8_DEVICE_DELEGATE(m_fdc, fd1793_t, read),
	217	WRITE8_DEVICE_DELEGATE(m_fdc, fd1793_t, write) );
	218	m_isa->install_device(this, 0x0100, 0x010b, 0, 0, FUNC(mc1502_FDC_r), FUNC(mc1502_FDC_w) );
	219	// BIOS 5.31, 5.33
	220	/*
	221	m_isa->install_device(0x010c, 0x010f, 0, 0,
	222	READ8_DEVICE_DELEGATE(m_fdc, fd1793_t, read),
	223	WRITE8_DEVICE_DELEGATE(m_fdc, fd1793_t, write) );
	224	m_isa->install_device(this, 0x0100, 0x010b, 0, 0, FUNC(mc1502_FDC_r), FUNC(mc1502_FDC_w) );
	225	*/
	226	m_fdc->setup_drq_cb(fd1793_t::line_cb(FUNC(mc1502_fdc_device::mc1502_fdc_irq_drq), this));
	227	m_fdc->setup_intrq_cb(fd1793_t::line_cb(FUNC(mc1502_fdc_device::mc1502_fdc_irq_drq), this));
	228
	229	motor_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc1502_fdc_device::motor_callback),this));
	230	motor_on = 0;
	231	}
	232
	233
	234	//-------------------------------------------------
	235	//  device_reset - device-specific reset
	236	//-------------------------------------------------
	237
	238	void mc1502_fdc_device::device_reset()
	239	{
	240	}

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trunk/src/mess/machine/mc1502_fdc.h

r0	r26689
	1	// license:BSD-3-Clause
	2	// copyright-holders:XXX
	3	/**********************************************************************
	4
	5	Electronika MC 1502 FDC device
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#pragma once
	13
	14	#ifndef __MC1502_FDC__
	15	#define __MC1502_FDC__
	16
	17	#include "emu.h"
	18
	19	#include "imagedev/flopdrv.h"
	20	#include "machine/isa.h"
	21	#include "machine/wd_fdc.h"
	22
	23	//**************************************************************************
	24	//  TYPE DEFINITIONS
	25	//**************************************************************************
	26
	27	class mc1502_fdc_device : public device_t,
	28	public device_isa8_card_interface
	29	{
	30	public:
	31	// construction/destruction
	32	mc1502_fdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	33
	34	// optional information overrides
	35	virtual machine_config_constructor device_mconfig_additions() const;
	36	virtual const rom_entry *device_rom_region() const;
	37
	38	DECLARE_FLOPPY_FORMATS( floppy_formats );
	39	TIMER_CALLBACK_MEMBER( motor_callback );
	40
	41
	42	protected:
	43	// device-level overrides
	44	virtual void device_start();
	45	virtual void device_reset();
	46
	47	private:
	48	required_device<fd1793_t> m_fdc;
	49	int motor_on;
	50	emu_timer *motor_timer;
	51
	52	public:
	53	void mc1502_wd17xx_aux_w(UINT8 data);
	54	UINT8 mc1502_wd17xx_aux_r();
	55	UINT8 mc1502_wd17xx_drq_r();
	56	UINT8 mc1502_wd17xx_motor_r();
	57	void mc1502_fdc_irq_drq(bool state);
	58
	59	};
	60
	61
	62	// device type definition
	63	extern const device_type MC1502_FDC;
	64
	65
	66	#endif

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trunk/src/mess/video/poisk1.h

r0	r26689
	1	#include "emu.h"
	2
	3	#define CGA_PALETTE_SETS 83
	4	/* one for colour, one for mono, 81 for colour composite */
	5
	6	INPUT_PORTS_EXTERN( pcvideo_poisk1 );
	7
	8	MACHINE_CONFIG_EXTERN( pcvideo_poisk1 );

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trunk/src/mess/video/isa_cga.c

r26688	r26689
762	762	***************************************************************************/
763	763
764	764
765		const device_type ISA8_CGA_MC1502 = &device_creator<isa8_cga_mc1502_device>;
766
767		//-------------------------------------------------
768		//  isa8_cga_mc1502_device - constructor
769		//-------------------------------------------------
770
771		isa8_cga_mc1502_device::isa8_cga_mc1502_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
772		isa8_cga_device( mconfig, ISA8_CGA_MC1502, "ISA8_CGA_MC1502", tag, owner, clock, "cga_mc1502", __FILE__)
773		{
774		m_vram_size = 0x8000;
775		}
776
777
778		ROM_START( mc1502 )
779		ROM_REGION(0x2000,"gfx1", 0)
780		ROM_LOAD( "symgen.rom", 0x0000, 0x2000, CRC(b2747a52) SHA1(6766d275467672436e91ac2997ac6b77700eba1e))
781		ROM_END
782
783		//-------------------------------------------------
784		//  rom_region - device-specific ROM region
785		//-------------------------------------------------
786
787		const rom_entry *isa8_cga_mc1502_device::device_rom_region() const
788		{
789		return ROM_NAME( mc1502 );
790		}
791
792	765	UINT32 isa8_cga_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
793	766	{
794	767	mc6845_device *mc6845 = subdevice<mc6845_device>(CGA_MC6845_NAME);
r26688	r26689
815	788	}
816	789
817	790
818		const device_type ISA8_CGA_POISK1 = &device_creator<isa8_cga_poisk1_device>;
819
820		//-------------------------------------------------
821		//  isa8_cga_poisk1_device - constructor
822		//-------------------------------------------------
823
824		isa8_cga_poisk1_device::isa8_cga_poisk1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
825		isa8_cga_device( mconfig, ISA8_CGA_POISK1, "ISA8_CGA_POISK1", tag, owner, clock, "cga_poisk1", __FILE__)
826		{
827		m_chr_gen_offset[0] = 0x0000;
828		m_font_selection_mask = 0;
829		}
830
831		ROM_START( cga_poisk1 )
832		ROM_REGION(0x2000,"gfx1", 0)
833		ROM_LOAD( "poisk.cga", 0x0000, 0x0800, CRC(f6eb39f0) SHA1(0b788d8d7a8e92cc612d044abcb2523ad964c200))
834		ROM_END
835
836		//-------------------------------------------------
837		//  rom_region - device-specific ROM region
838		//-------------------------------------------------
839
840		const rom_entry *isa8_cga_poisk1_device::device_rom_region() const
841		{
842		return ROM_NAME( cga_poisk1 );
843		}
844
845
846	791	const device_type ISA8_CGA_POISK2 = &device_creator<isa8_cga_poisk2_device>;
847	792
848	793	//-------------------------------------------------
r26688	r26689
1533	1478	*
1534	1479	*************************************************************************/
1535	1480
1536		WRITE8_MEMBER( isa8_cga_device::char_ram_write )
1537		{
1538		logerror("write char ram %04x %02x\n",offset,data);
1539		m_chr_gen_base[offset + 0x0000] = data;
1540		m_chr_gen_base[offset + 0x0800] = data;
1541		m_chr_gen_base[offset + 0x1000] = data;
1542		m_chr_gen_base[offset + 0x1800] = data;
1543		}
1544	1481
1545
1546		READ8_MEMBER( isa8_cga_device::char_ram_read )
1547		{
1548		return m_chr_gen_base[offset];
1549		}
1550
1551
1552	1482	READ8_MEMBER( isa8_cga_device::io_read )
1553	1483	{
1554	1484	mc6845_device *mc6845 = subdevice<mc6845_device>(CGA_MC6845_NAME);
r26688	r26689
1565	1495	case 10:
1566	1496	data = m_vsync | ( ( data & 0x40 ) >> 4 ) | m_hsync;
1567	1497	break;
1568		case 0x0f:
1569		data = m_p3df;
1570		break;
1571	1498	}
1572	1499	return data;
1573	1500	}
r26688	r26689
1595	1522	case 0x0d:
1596	1523	plantronics_w(data);
1597	1524	break;
1598		case 0x0f:
1599		// Not sure if some all CGA cards have ability to upload char definition
1600		// The original CGA card had a char rom
1601		// TODO: This should be moved to card implementations that actually had this feature
1602		m_p3df = data;
1603		if (data & 1) {
1604		address_space &space_prg = machine().firstcpu->space(AS_PROGRAM);
1605
1606		space_prg.install_readwrite_handler(0xb8000, 0xb87ff, read8_delegate( FUNC(isa8_cga_device::char_ram_read), this), write8_delegate(FUNC(isa8_cga_device::char_ram_write), this) );
1607		} else {
1608		m_isa->install_bank(0xb8000, 0xb8000 + MIN(0x8000,m_vram_size) - 1, 0, m_vram_size & 0x4000, "bank_cga", m_vram);
1609		}
1610		break;
1611
1612	1525	}
1613	1526	}
1614	1527
r26688	r26689
2195	2108	}
2196	2109	return 0;
2197	2110	}
	2111
	2112
	2113	const device_type ISA8_EC1841_0002 = &device_creator<isa8_ec1841_0002_device>;
	2114
	2115	//-------------------------------------------------
	2116	//  isa8_ec1841_0002_device - constructor
	2117	//-------------------------------------------------
	2118
	2119	isa8_ec1841_0002_device::isa8_ec1841_0002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	2120	isa8_cga_device( mconfig, ISA8_EC1841_0002, "EC 1841.0002 (CGA)", tag, owner, clock, "ec1841_0002", __FILE__)
	2121	{
	2122	}
	2123
	2124	//-------------------------------------------------
	2125	//  device_start - device-specific startup
	2126	//-------------------------------------------------
	2127
	2128	void isa8_ec1841_0002_device::device_start()
	2129	{
	2130	isa8_cga_device::device_start();
	2131
	2132	m_isa->install_device(0x3d0, 0x3df, 0, 0, read8_delegate( FUNC(isa8_ec1841_0002_device::io_read), this ), write8_delegate( FUNC(isa8_ec1841_0002_device::io_write), this ) );
	2133	}
	2134
	2135	void isa8_ec1841_0002_device::device_reset()
	2136	{
	2137	isa8_cga_device::device_reset();
	2138	m_p3df = 0;
	2139	}
	2140
	2141	ROM_START( iskr1031 )
	2142	ROM_REGION(0x2000,"gfx1", 0)
	2143	ROM_LOAD( "iskra-1031_font.bin", 0x0000, 0x2000, CRC(f4d62e80) SHA1(ad7e81a0c9abc224671422bbcf6f6262da92b510))
	2144	ROM_END
	2145
	2146	const rom_entry *isa8_ec1841_0002_device::device_rom_region() const
	2147	{
	2148	return ROM_NAME( iskr1031 );
	2149	}
	2150
	2151	WRITE8_MEMBER( isa8_ec1841_0002_device::char_ram_write )
	2152	{
	2153	offset ^= BIT(offset, 12);
	2154	//   logerror("write char ram %04x %02x\n",offset,data);
	2155	m_chr_gen_base[offset + 0x0000] = data;
	2156	m_chr_gen_base[offset + 0x0800] = data;
	2157	m_chr_gen_base[offset + 0x1000] = data;
	2158	m_chr_gen_base[offset + 0x1800] = data;
	2159	}
	2160
	2161	READ8_MEMBER( isa8_ec1841_0002_device::char_ram_read )
	2162	{
	2163	offset ^= BIT(offset, 12);
	2164	return m_chr_gen_base[offset];
	2165	}
	2166
	2167	WRITE8_MEMBER( isa8_ec1841_0002_device::io_write )
	2168	{
	2169	switch (offset)
	2170	{
	2171	case 0x0f:
	2172	m_p3df = data;
	2173	if (data & 1) {
	2174	m_isa->install_memory(0xb8000, 0xb9fff, 0, m_vram_size & 0x4000,
	2175	read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
	2176	write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
	2177	} else {
	2178	m_isa->install_bank(0xb8000, 0xb8000 + MIN(0x8000,m_vram_size) - 1, 0, m_vram_size & 0x4000, "bank_cga", m_vram);
	2179	}
	2180	break;
	2181	default:
	2182	isa8_cga_device::io_write(space, offset, data);
	2183	break;
	2184	}
	2185	}
	2186
	2187	READ8_MEMBER( isa8_ec1841_0002_device::io_read )
	2188	{
	2189	UINT8 data;
	2190
	2191	switch (offset)
	2192	{
	2193	case 0x0f:
	2194	data = m_p3df;
	2195	break;
	2196	default:
	2197	data = isa8_cga_device::io_read(space, offset);
	2198	break;
	2199	}
	2200	return data;
	2201	}

trunk/src/mess/video/isa_cga.h

r26688	r26689
18	18	public device_isa8_card_interface
19	19	{
20	20	friend class isa8_cga_superimpose_device;
21		friend class isa8_cga_mc1502_device;
22		friend class isa8_cga_poisk1_device;
	21	//   friend class isa8_ec1841_0002_device;
23	22	friend class isa8_cga_poisk2_device;
24	23	friend class isa8_cga_pc1512_device;
25	24
r26688	r26689
45	44	void plantronics_w(UINT8 data);
46	45	virtual DECLARE_READ8_MEMBER( io_read );
47	46	virtual DECLARE_WRITE8_MEMBER( io_write );
48		DECLARE_READ8_MEMBER( char_ram_read );
49		DECLARE_WRITE8_MEMBER( char_ram_write );
50	47	DECLARE_WRITE_LINE_MEMBER( hsync_changed );
51	48	DECLARE_WRITE_LINE_MEMBER( vsync_changed );
52	49	virtual UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
r26688	r26689
69	66	size_t  m_vram_size;
70	67	UINT8   *m_vram;
71	68	bool    m_superimpose;
72		UINT8   m_p3df; /* This should be moved into the appropriate subclass */
73	69	UINT8   m_plantronics; /* This should be moved into the appropriate subclass */
74	70	offs_t  m_start_offset;
75	71	};
r26688	r26689
92	88	extern const device_type ISA8_CGA_SUPERIMPOSE;
93	89
94	90
95		// ======================> isa8_cga_mc1502_device
96
97		class isa8_cga_mc1502_device :
98		public isa8_cga_device
99		{
100		public:
101		// construction/destruction
102		isa8_cga_mc1502_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
103		// optional information overrides
104		virtual const rom_entry *device_rom_region() const;
105		};
106
107		// device type definition
108		extern const device_type ISA8_CGA_MC1502;
109
110
111		// ======================> isa8_poisk1_device
112
113		class isa8_cga_poisk1_device :
114		public isa8_cga_device
115		{
116		public:
117		// construction/destruction
118		isa8_cga_poisk1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
119		// optional information overrides
120		virtual const rom_entry *device_rom_region() const;
121		};
122
123		// device type definition
124		extern const device_type ISA8_CGA_POISK1;
125
126
127	91	// ======================> isa8_poisk2_device
128	92
129	93	class isa8_cga_poisk2_device :
r26688	r26689
209	173	// device type definition
210	174	extern const device_type ISA8_WYSE700;
211	175
	176	// ======================> isa8_ec1841_0002_device
	177
	178	class isa8_ec1841_0002_device :
	179	public isa8_cga_device
	180	{
	181	public:
	182	// construction/destruction
	183	isa8_ec1841_0002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	184	// optional information overrides
	185	virtual const rom_entry *device_rom_region() const;
	186
	187	protected:
	188	// device-level overrides
	189	virtual void device_start();
	190	virtual void device_reset();
	191
	192	public:
	193	virtual DECLARE_READ8_MEMBER( io_read );
	194	virtual DECLARE_WRITE8_MEMBER( io_write );
	195
	196	UINT8   m_p3df;
	197	DECLARE_READ8_MEMBER( char_ram_read );
	198	DECLARE_WRITE8_MEMBER( char_ram_write );
	199	};
	200
	201	// device type definition
	202	extern const device_type ISA8_EC1841_0002;
	203
	204
212	205	#endif  /* __ISA_CGA_H__ */

trunk/src/mess/video/poisk1.c

r0	r26689
	1	/*
	2	* Poisk-1 does not have a real mc6845 and always runs in graphics mode.
	3	* Text mode is emulated by BIOS.
	4	* Video RAM in native graphics mode starts at 0xB8000, in emulated text mode -- at 0xBC000.
	5	*/
	6
	7	#include "emu.h"
	8
	9	#include "includes/poisk1.h"
	10
	11	#define CGA_PALETTE_SETS 83
	12	/* one for colour, one for mono, 81 for colour composite */
	13
	14	#include "video/cgapal.h"
	15
	16	#define BG_COLOR(x) (((x) & 7)|(((x) & 0x10) >> 1))
	17
	18	#define VERBOSE_DBG 0
	19
	20	#define DBG_LOG(N,M,A) \
	21	do { \
	22	if(VERBOSE_DBG>=N) \
	23	{ \
	24	if( M ) \
	25	logerror("%11.6f: %-24s",machine().time().as_double(),(char*)M ); \
	26	logerror A; \
	27	} \
	28	} while (0)
	29
	30	//
	31
	32	/*
	33	* Poisk-1 doesn't have a mc6845 and always runs in graphics mode.  Text mode is emulated by BIOS;
	34	* NMI is triggered on access to video memory and to mc6845 ports.  Address and data are latched into:
	35	*
	36	* Port 28H (offset 0) -- lower 8 bits of address
	37	* Port 29H (offset 1) -- high  -//- and mode bits
	38	* Port 2AH (offset 2) -- data
	39	*/
	40
	41	READ8_MEMBER(p1_state::p1_trap_r)
	42	{
	43	UINT8 data = m_video.trap[offset];
	44	DBG_LOG(1,"trap",("R %.2x $%02x\n", 0x28+offset, data));
	45	if (offset == 0)
	46	space.machine().firstcpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
	47	return data;
	48	}
	49
	50	WRITE8_MEMBER(p1_state::p1_trap_w)
	51	{
	52	DBG_LOG(1,"trap",("W %.2x $%02x\n", 0x28+offset, data));
	53	}
	54
	55	READ8_MEMBER(p1_state::p1_cga_r)
	56	{
	57	space.machine().firstcpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
	58	return 0;
	59	}
	60
	61	WRITE8_MEMBER(p1_state::p1_cga_w)
	62	{
	63	UINT16 port = offset + 0x3d0;
	64
	65	DBG_LOG(1,"cga",("W %.4x $%02x\n", port, data));
	66	m_video.trap[2] = data;
	67	m_video.trap[1] = 0xC0 | ((port >> 8) & 0x3f);
	68	m_video.trap[0] = port & 255;
	69	space.machine().firstcpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
	70	}
	71
	72	WRITE8_MEMBER(p1_state::p1_vram_w)
	73	{
	74	DBG_LOG(1,"vram",("W %.4x $%02x\n", offset, data));
	75	if (m_video.videoram_base)
	76	m_video.videoram_base[offset] = data;
	77	m_video.trap[2] = data;
	78	m_video.trap[1] = 0x80 | ((offset >> 8) & 0x3f);
	79	m_video.trap[0] = offset & 255;
	80	space.machine().firstcpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
	81	}
	82
	83	// CGA emulator
	84	/*
	85	068h   D42   0..2   R, G, B      XXX Foreground/Background color
	86	3   NMI DISABLE   NMI trap  1: Disabled  0: Enabled
	87	4   PALETTE      XXX Colour palette  0: XXX  1: XXX
	88	5   I (INTENS)   XXX Foreground/Background color intensity
	89	6   DISPLAY BANK   XXX Video RAM page
	90	7   HIRES      1: 640x200  0: 320x200
	91	*/
	92
	93	WRITE8_MEMBER(p1_state::p1_ppi2_porta_w)
	94	{
	95	address_space &space_prg = machine().firstcpu->space(AS_PROGRAM);
	96	rectangle visarea;
	97
	98	DBG_LOG(1,"color_select_68",("W $%02x\n", data));
	99
	100	// NMI DISABLE
	101	if (BIT(data, 3) != BIT(m_video.color_select_68, 3)) {
	102	if (BIT(data, 3)) {
	103	space_prg.install_readwrite_bank( 0xb8000, 0xbbfff, "bank11" );
	104	} else {
	105	space_prg.install_read_bank( 0xb8000, 0xbbfff, "bank11" );
	106	space_prg.install_write_handler( 0xb8000, 0xbbfff, WRITE8_DELEGATE(p1_state, p1_vram_w) );
	107	}
	108	}
	109	// DISPLAY BANK
	110	if (BIT(data, 6) != BIT(m_video.color_select_68, 6)) {
	111	if (BIT(data, 6))
	112	m_video.videoram = m_video.videoram_base + 0x4000;
	113	else
	114	m_video.videoram = m_video.videoram_base;
	115	}
	116	// HIRES -- XXX
	117	if (BIT(data, 7) != BIT(m_video.color_select_68, 7)) {
	118	if (BIT(data, 7))
	119	machine().primary_screen->set_visible_area(0, 640-1, 0, 200-1);
	120	else
	121	machine().primary_screen->set_visible_area(0, 320-1, 0, 200-1);
	122	}
	123	m_video.color_select_68 = data;
	124	set_palette_luts();
	125	}
	126
	127	/*
	128	06Ah   Dxx   6   Enable/Disable color burst (?)
	129	7   Enable/Disable D7H/D7L
	130	*/
	131
	132	WRITE8_MEMBER(p1_state::p1_ppi_portc_w)
	133	{
	134	DBG_LOG(1,"mode_control_6a",("W $%02x\n", data));
	135
	136	m_video.mode_control_6a = data;
	137	set_palette_luts();
	138	}
	139
	140	void p1_state::set_palette_luts(void)
	141	{
	142	/* Setup 2bpp palette lookup table */
	143	// HIRES
	144	if ( m_video.color_select_68 & 0x80 )
	145	{
	146	m_video.palette_lut_2bpp[0] = 0;
	147	}
	148	else
	149	{
	150	m_video.palette_lut_2bpp[0] = BG_COLOR(m_video.color_select_68);
	151	}
	152	// B&W -- XXX
	153	/*
	154	if ( m_video.mode_control_6a & 0x40 )
	155	{
	156	m_video.palette_lut_2bpp[1] = ( ( m_video.color_select_68 & 0x20 ) >> 2 ) | 3;
	157	m_video.palette_lut_2bpp[2] = ( ( m_video.color_select_68 & 0x20 ) >> 2 ) | 4;
	158	m_video.palette_lut_2bpp[3] = ( ( m_video.color_select_68 & 0x20 ) >> 2 ) | 7;
	159	}
	160	else
	161	*/
	162	{
	163	// PALETTE
	164	if ( m_video.color_select_68 & 0x20 )
	165	{
	166	m_video.palette_lut_2bpp[1] = ( ( m_video.color_select_68 & 0x20 ) >> 2 ) | 3;
	167	m_video.palette_lut_2bpp[2] = ( ( m_video.color_select_68 & 0x20 ) >> 2 ) | 5;
	168	m_video.palette_lut_2bpp[3] = ( ( m_video.color_select_68 & 0x20 ) >> 2 ) | 7;
	169	}
	170	else
	171	{
	172	m_video.palette_lut_2bpp[1] = ( ( m_video.color_select_68 & 0x20 ) >> 2 ) | 2;
	173	m_video.palette_lut_2bpp[2] = ( ( m_video.color_select_68 & 0x20 ) >> 2 ) | 4;
	174	m_video.palette_lut_2bpp[3] = ( ( m_video.color_select_68 & 0x20 ) >> 2 ) | 6;
	175	}
	176	}
	177	}
	178
	179	/***************************************************************************
	180	Draw graphics mode with 320x200 pixels (default) with 2 bits/pixel.
	181	Even scanlines are from CGA_base + 0x0000, odd from CGA_base + 0x2000
	182	cga fetches 2 byte per mc6845 access.
	183	***************************************************************************/
	184
	185	POISK1_UPDATE_ROW( p1_state::cga_gfx_2bpp_update_row )
	186	{
	187	const rgb_t *palette = palette_entry_list_raw(bitmap.palette());
	188	UINT32  *p = &bitmap.pix32(ra);
	189	UINT16  odd, offset;
	190	int i;
	191
	192	if ( ra == 0 ) DBG_LOG(1,"cga_gfx_2bpp_update_row",("\n"));
	193	odd = ( ra & 1 ) << 13;
	194	offset = ( ma & 0x1fff ) | odd;
	195	for ( i = 0; i < stride; i++ )
	196	{
	197	UINT8 data = videoram[ offset++ ];
	198
	199	*p = palette[m_video.palette_lut_2bpp[ ( data >> 6 ) & 0x03 ]]; p++;
	200	*p = palette[m_video.palette_lut_2bpp[ ( data >> 4 ) & 0x03 ]]; p++;
	201	*p = palette[m_video.palette_lut_2bpp[ ( data >> 2 ) & 0x03 ]]; p++;
	202	*p = palette[m_video.palette_lut_2bpp[   data        & 0x03 ]]; p++;
	203	}
	204	}
	205
	206	/***************************************************************************
	207	Draw graphics mode with 640x200 pixels (default).
	208	The cell size is 1x1 (1 scanline is the real default)
	209	Even scanlines are from CGA_base + 0x0000, odd from CGA_base + 0x2000
	210	***************************************************************************/
	211
	212	POISK1_UPDATE_ROW( p1_state::cga_gfx_1bpp_update_row )
	213	{
	214	const rgb_t *palette = palette_entry_list_raw(bitmap.palette());
	215	UINT32  *p = &bitmap.pix32(ra);
	216	UINT8   fg = 15, bg = BG_COLOR(m_video.color_select_68);
	217	UINT16  odd, offset;
	218	int i;
	219
	220	if ( ra == 0 ) DBG_LOG(1,"cga_gfx_1bpp_update_row",("bg %d\n", bg));
	221	odd = ( ra & 1 ) << 13;
	222	offset = ( ma & 0x1fff ) | odd;
	223	for ( i = 0; i < stride; i++ )
	224	{
	225	UINT8 data = videoram[ offset++ ];
	226
	227	*p = palette[( data & 0x80 ) ? fg : bg ]; p++;
	228	*p = palette[( data & 0x40 ) ? fg : bg ]; p++;
	229	*p = palette[( data & 0x20 ) ? fg : bg ]; p++;
	230	*p = palette[( data & 0x10 ) ? fg : bg ]; p++;
	231	*p = palette[( data & 0x08 ) ? fg : bg ]; p++;
	232	*p = palette[( data & 0x04 ) ? fg : bg ]; p++;
	233	*p = palette[( data & 0x02 ) ? fg : bg ]; p++;
	234	*p = palette[( data & 0x01 ) ? fg : bg ]; p++;
	235	}
	236	}
	237
	238	/***************************************************************************
	239	Draw graphics mode with 640x200 pixels + extra highlight color for text
	240	mode emulation
	241	Even scanlines are from CGA_base + 0x0000, odd from CGA_base + 0x2000
	242	***************************************************************************/
	243
	244	POISK1_UPDATE_ROW( p1_state::poisk1_gfx_1bpp_update_row )
	245	{
	246	const rgb_t *palette = palette_entry_list_raw(bitmap.palette());
	247	UINT32  *p = &bitmap.pix32(ra);
	248	UINT8   fg, bg = BG_COLOR(m_video.color_select_68);
	249	UINT16  odd, offset;
	250	int i;
	251
	252	if ( ra == 0 ) DBG_LOG(1,"poisk1_gfx_1bpp_update_row",("bg %d\n", bg));
	253	odd = ( ra & 1 ) << 13;
	254	offset = ( ma & 0x1fff ) | odd;
	255	for ( i = 0; i < stride; i++ )
	256	{
	257	UINT8 data = videoram[ offset++ ];
	258
	259	fg = (data & 0x80) ? ( (m_video.color_select_68 & 0x20) ? 10 : 11 ) : 15; // XXX
	260	*p = palette[bg]; p++;
	261	*p = palette[( data & 0x40 ) ? fg : bg ]; p++;
	262	*p = palette[( data & 0x20 ) ? fg : bg ]; p++;
	263	*p = palette[( data & 0x10 ) ? fg : bg ]; p++;
	264	*p = palette[( data & 0x08 ) ? fg : bg ]; p++;
	265	*p = palette[( data & 0x04 ) ? fg : bg ]; p++;
	266	*p = palette[( data & 0x02 ) ? fg : bg ]; p++;
	267	*p = palette[( data & 0x01 ) ? fg : bg ]; p++;
	268	}
	269	}
	270
	271	/* Initialise the cga palette */
	272	void p1_state::palette_init()
	273	{
	274	int i;
	275
	276	DBG_LOG(0,"init",("palette_init()\n"));
	277
	278	for ( i = 0; i < CGA_PALETTE_SETS * 16; i++ )
	279	{
	280	palette_set_color_rgb( machine(), i, cga_palette[i][0], cga_palette[i][1], cga_palette[i][2] );
	281	}
	282	}
	283
	284	void p1_state::video_start()
	285	{
	286	address_space &space = machine().firstcpu->space( AS_PROGRAM );
	287
	288	DBG_LOG(0,"init",("video_start()\n"));
	289
	290	memset(&m_video, 0, sizeof(m_video));
	291	m_video.videoram = m_video.videoram_base = auto_alloc_array(machine(), UINT8, 0x8000);
	292	m_video.stride = 80;
	293
	294	space.install_readwrite_bank(0xb8000, 0xbffff, "bank11" );
	295	machine().root_device().membank("bank11")->set_base(m_video.videoram);
	296	}
	297
	298	UINT32 p1_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	299	{
	300	UINT16 ra, ma = 0;
	301
	302	if (!m_video.stride || !m_video.videoram) return 0;
	303
	304	// bit 6 of 6Ah disables color burst -- not implemented
	305	for (ra = cliprect.min_y; ra <= cliprect.max_y; ra++)
	306	{
	307	if (BIT(m_video.color_select_68, 7)) {
	308	if (BIT(m_video.mode_control_6a, 7)) {
	309	cga_gfx_1bpp_update_row(bitmap, cliprect, m_video.videoram, ma, ra, m_video.stride);
	310	} else {
	311	poisk1_gfx_1bpp_update_row(bitmap, cliprect, m_video.videoram, ma, ra, m_video.stride);
	312	}
	313	} else {
	314	cga_gfx_2bpp_update_row(bitmap, cliprect, m_video.videoram, ma, ra, m_video.stride);
	315	}
	316	if (ra & 1) ma += m_video.stride;
	317	}
	318
	319	return 0;
	320	}

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trunk/src/mess/includes/poisk1.h

r0	r26689
	1	/*****************************************************************************
	2	*
	3	* includes/poisk1.h
	4	*
	5	****************************************************************************/
	6
	7	#ifndef POISK1_H_
	8	#define POISK1_H_
	9
	10	#include "imagedev/cassette.h"
	11	#include "machine/i8255.h"
	12	#include "machine/isa.h"
	13	#include "machine/pic8259.h"
	14	#include "machine/pit8253.h"
	15	#include "machine/ram.h"
	16	#include "machine/xsu_cards.h"
	17	#include "sound/speaker.h"
	18
	19	#define POISK1_UPDATE_ROW(name)   \
	20	void name(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT8 *videoram, UINT16 ma, UINT8 ra, UINT8 stride)
	21
	22	class p1_state : public driver_device
	23	{
	24	public:
	25	p1_state(const machine_config &mconfig, device_type type, const char *tag)
	26	: driver_device(mconfig, type, tag),
	27	m_maincpu(*this, "maincpu"),
	28	m_pic8259(*this, "pic8259"),
	29	m_pit8253(*this, "pit8253"),
	30	m_ppi8255n1(*this, "ppi8255n1"),
	31	m_ppi8255n2(*this, "ppi8255n2"),
	32	m_isabus(*this, "isa"),
	33	m_speaker(*this, "speaker"),
	34	m_cassette(*this, "cassette"),
	35	m_ram(*this, RAM_TAG) { }
	36
	37	required_device<cpu_device>  m_maincpu;
	38	required_device<pic8259_device>  m_pic8259;
	39	required_device<pit8253_device>  m_pit8253;
	40	required_device<i8255_device>  m_ppi8255n1;
	41	required_device<i8255_device>  m_ppi8255n2;
	42	required_device<isa8_device>  m_isabus;
	43	required_device<speaker_sound_device>  m_speaker;
	44	required_device<cassette_image_device>  m_cassette;
	45	required_device<ram_device> m_ram;
	46
	47	DECLARE_DRIVER_INIT(poisk1);
	48	DECLARE_MACHINE_START(poisk1);
	49	DECLARE_MACHINE_RESET(poisk1);
	50
	51	IRQ_CALLBACK_MEMBER(p1_irq_callback);
	52
	53	virtual void palette_init();
	54	virtual void video_start();
	55	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	56	void set_palette_luts();
	57	POISK1_UPDATE_ROW(cga_gfx_2bpp_update_row);
	58	POISK1_UPDATE_ROW(cga_gfx_1bpp_update_row);
	59	POISK1_UPDATE_ROW(poisk1_gfx_1bpp_update_row);
	60
	61	DECLARE_WRITE_LINE_MEMBER(p1_pit8253_out2_changed);
	62	DECLARE_WRITE_LINE_MEMBER(p1_speaker_set_spkrdata);
	63	UINT8 m_p1_spkrdata;
	64	UINT8 m_p1_input;
	65
	66	UINT8 m_kbpoll_mask;
	67
	68	struct
	69	{
	70	UINT8 trap[4];
	71	UINT8 *videoram_base;
	72	UINT8 *videoram;
	73	UINT8 mode_control_6a;
	74	UINT8 color_select_68;
	75	UINT8 palette_lut_2bpp[4];
	76	int stride;
	77	void *update_row(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT8 *videoram, UINT16 ma, UINT8 ra, UINT8 stride);
	78	} m_video;
	79
	80	DECLARE_READ8_MEMBER(p1_trap_r);
	81	DECLARE_WRITE8_MEMBER(p1_trap_w);
	82	DECLARE_READ8_MEMBER(p1_cga_r);
	83	DECLARE_WRITE8_MEMBER(p1_cga_w);
	84	DECLARE_WRITE8_MEMBER(p1_vram_w);
	85
	86	DECLARE_READ8_MEMBER(p1_ppi_r);
	87	DECLARE_WRITE8_MEMBER(p1_ppi_w);
	88	DECLARE_WRITE8_MEMBER(p1_ppi_porta_w);
	89	DECLARE_READ8_MEMBER(p1_ppi_porta_r);
	90	DECLARE_READ8_MEMBER(p1_ppi_portb_r);
	91	DECLARE_READ8_MEMBER(p1_ppi_portc_r);
	92	DECLARE_WRITE8_MEMBER(p1_ppi_portc_w);
	93	DECLARE_WRITE8_MEMBER(p1_ppi2_porta_w);
	94	DECLARE_WRITE8_MEMBER(p1_ppi2_portb_w);
	95	DECLARE_READ8_MEMBER(p1_ppi2_portc_r);
	96
	97	const char *m_cputag;
	98	};
	99
	100	#endif /* POISK1_H_ */

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trunk/src/mess/includes/genpc.h

r26688	r26689
149	149	// device type definition
150	150	extern const device_type IBM5150_MOTHERBOARD;
151	151
	152
	153	#define MCFG_EC1841_MOTHERBOARD_ADD(_tag, _cputag) \
	154	MCFG_DEVICE_ADD(_tag, EC1841_MOTHERBOARD, 0) \
	155	ec1841_mb_device::static_set_cputag(*device, _cputag);
	156
	157	// ======================> ibm5150_mb_device
	158	class ec1841_mb_device : public ibm5160_mb_device
	159	{
	160	public:
	161	// construction/destruction
	162	ec1841_mb_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	163
	164	// optional information overrides
	165	virtual machine_config_constructor device_mconfig_additions() const;
	166	virtual ioport_constructor device_input_ports() const;
	167
	168	protected:
	169	// device-level overrides
	170	virtual void device_start();
	171	virtual void device_reset();
	172
	173	public:
	174	virtual DECLARE_READ8_MEMBER ( pc_ppi_portc_r );
	175	virtual DECLARE_WRITE8_MEMBER( pc_ppi_portb_w );
	176	};
	177
	178
	179	// device type definition
	180	extern const device_type EC1841_MOTHERBOARD;
	181
152	182	#endif /* GENPC_H_ */

trunk/src/mess/includes/ec184x.h

r0	r26689
	1	/*****************************************************************************
	2	*
	3	* includes/ec184x.h
	4	*
	5	****************************************************************************/
	6
	7	#ifndef EC184X_H_
	8	#define EC184X_H_
	9
	10	#include "includes/genpc.h"
	11
	12	#define MCFG_EC1841_MOTHERBOARD_ADD(_tag, _cputag) \
	13	MCFG_DEVICE_ADD(_tag, EC1841_MOTHERBOARD, 0) \
	14	ec1841_mb_device::static_set_cputag(*device, _cputag);
	15
	16	// ======================> ibm5150_mb_device
	17	class ec1841_mb_device : public ibm5160_mb_device
	18	{
	19	public:
	20	// construction/destruction
	21	ec1841_mb_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	22
	23	// optional information overrides
	24	virtual machine_config_constructor device_mconfig_additions() const;
	25	virtual ioport_constructor device_input_ports() const;
	26
	27	protected:
	28	// device-level overrides
	29	virtual void device_start();
	30	virtual void device_reset();
	31
	32	public:
	33	virtual DECLARE_READ8_MEMBER ( pc_ppi_portc_r );
	34	virtual DECLARE_WRITE8_MEMBER( pc_ppi_portb_w );
	35	};
	36
	37
	38	// device type definition
	39	extern const device_type EC1841_MOTHERBOARD;
	40
	41	#endif /* EC184X_H_ */

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trunk/src/mess/includes/mc1502.h

r0	r26689
	1	/*****************************************************************************
	2	*
	3	* includes/mc1502.h
	4	*
	5	****************************************************************************/
	6
	7	#ifndef MC1502_H_
	8	#define MC1502_H_
	9
	10	#include "imagedev/cassette.h"
	11	#include "machine/i8251.h"
	12	#include "machine/i8255.h"
	13	#include "machine/isa.h"
	14	#include "machine/pic8259.h"
	15	#include "machine/pit8253.h"
	16	#include "machine/ram.h"
	17	#include "machine/serial.h"
	18	#include "machine/xsu_cards.h"
	19	#include "sound/speaker.h"
	20
	21	class mc1502_state : public driver_device
	22	{
	23	public:
	24	mc1502_state(const machine_config &mconfig, device_type type, const char *tag)
	25	: driver_device(mconfig, type, tag),
	26	m_maincpu(*this, "maincpu"),
	27	m_pic8259(*this, "pic8259"),
	28	m_pit8253(*this, "pit8253"),
	29	m_ppi8255n1(*this, "ppi8255n1"),
	30	m_ppi8255n2(*this, "ppi8255n2"),
	31	m_isabus(*this, "isa"),
	32	m_speaker(*this, "speaker"),
	33	m_cassette(*this, "cassette"),
	34	m_centronics(*this, "centronics"),
	35	m_ram(*this, RAM_TAG) { }
	36
	37	required_device<cpu_device>  m_maincpu;
	38	required_device<pic8259_device>  m_pic8259;
	39	required_device<pit8253_device>  m_pit8253;
	40	required_device<i8255_device>  m_ppi8255n1;
	41	required_device<i8255_device>  m_ppi8255n2;
	42	required_device<isa8_device>  m_isabus;
	43	required_device<speaker_sound_device>  m_speaker;
	44	required_device<cassette_image_device>  m_cassette;
	45	required_device<centronics_device> m_centronics;
	46	required_device<ram_device> m_ram;
	47
	48	DECLARE_DRIVER_INIT(mc1502);
	49	DECLARE_MACHINE_START(mc1502);
	50	DECLARE_MACHINE_RESET(mc1502);
	51
	52	IRQ_CALLBACK_MEMBER(mc1502_irq_callback);
	53	TIMER_CALLBACK_MEMBER(keyb_signal_callback);
	54
	55	struct {
	56	UINT8       pulsing;
	57	UINT16      mask;       /* input lines */
	58	emu_timer   *keyb_signal_timer;
	59	} m_kbd;
	60
	61	UINT8                   m_ppi_portb;
	62	UINT8                   m_ppi_portc;
	63	UINT8 m_mc1502_spkrdata;
	64	UINT8 m_mc1502_input;
	65
	66	DECLARE_WRITE_LINE_MEMBER(mc1502_pit8253_out1_changed);
	67	DECLARE_WRITE_LINE_MEMBER(mc1502_pit8253_out2_changed);
	68	DECLARE_WRITE_LINE_MEMBER(mc1502_speaker_set_spkrdata);
	69	DECLARE_WRITE_LINE_MEMBER(mc1502_i8251_syndet);
	70
	71	DECLARE_WRITE8_MEMBER(mc1502_ppi_porta_w);
	72	DECLARE_WRITE8_MEMBER(mc1502_ppi_portb_w);
	73	DECLARE_WRITE8_MEMBER(mc1502_ppi_portc_w);
	74	DECLARE_READ8_MEMBER(mc1502_ppi_portc_r);
	75	DECLARE_READ8_MEMBER(mc1502_kppi_porta_r);
	76	DECLARE_READ8_MEMBER(mc1502_kppi_portc_r);
	77	DECLARE_WRITE8_MEMBER(mc1502_kppi_portb_w);
	78	DECLARE_WRITE8_MEMBER(mc1502_kppi_portc_w);
	79	/*
	80	TIMER_CALLBACK_MEMBER(fdc_motor_callback);
	81	static struct {
	82	int         fdc_motor_on;
	83	emu_timer   *fdc_motor_timer;
	84	} m_motor;
	85	*/
	86	const char *m_cputag;
	87	};
	88
	89	#endif /* MC1502_H_ */

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trunk/src/mess/includes/pc.h

r26688	r26689
8	8	#define PC_H_
9	9
10	10	#include "machine/ins8250.h"
11		#include "machine/i8251.h"
12	11	#include "machine/i8255.h"
13	12	#include "machine/am9517a.h"
14	13	#include "machine/serial.h"
r26688	r26689
51	50	/* Q2 is set by OUT1 from the 8253 and goes to DRQ1 on the 8237 */
52	51	UINT8   m_u73_q2;
53	52	UINT8   m_out1;
54		UINT8   m_memboard[4];      /* used only by ec1840 and ec1841 */
55		int m_memboards;
56	53	int m_dma_channel;
57	54	UINT8 m_dma_offset[2][4];
58	55	int m_cur_eop;
r26688	r26689
90	87	DECLARE_WRITE8_MEMBER(pc_EXP_w);
91	88	DECLARE_READ8_MEMBER(pc_EXP_r);
92	89	DECLARE_READ8_MEMBER(unk_r);
93		DECLARE_READ8_MEMBER(ec1841_memboard_r);
94		DECLARE_WRITE8_MEMBER(ec1841_memboard_w);
95		DECLARE_DRIVER_INIT(ec1841);
96		DECLARE_DRIVER_INIT(mc1502);
97	90	DECLARE_DRIVER_INIT(bondwell);
98	91	DECLARE_DRIVER_INIT(pcjr);
99	92	DECLARE_DRIVER_INIT(pccga);
r26688	r26689
103	96	DECLARE_MACHINE_RESET(pc);
104	97	DECLARE_MACHINE_START(pcjr);
105	98	DECLARE_MACHINE_RESET(pcjr);
106		DECLARE_MACHINE_START(mc1502);
107	99	TIMER_CALLBACK_MEMBER(pcjr_delayed_pic8259_irq);
108	100	TIMER_CALLBACK_MEMBER(pcjr_keyb_signal_callback);
109	101	TIMER_CALLBACK_MEMBER(pcjr_fdc_watchdog);
110		TIMER_CALLBACK_MEMBER(mc1502_keyb_signal_callback);
111	102	TIMER_CALLBACK_MEMBER(pc_rtc_timer);
112	103	TIMER_DEVICE_CALLBACK_MEMBER(pc_frame_interrupt);
113	104	TIMER_DEVICE_CALLBACK_MEMBER(pc_vga_frame_interrupt);
r26688	r26689
126	117	DECLARE_WRITE_LINE_MEMBER(pcjr_pic8259_set_int_line);
127	118	DECLARE_WRITE_LINE_MEMBER(ibm5150_pit8253_out1_changed);
128	119	DECLARE_WRITE_LINE_MEMBER(ibm5150_pit8253_out2_changed);
129		DECLARE_WRITE_LINE_MEMBER(mc1502_pit8253_out1_changed);
130		DECLARE_WRITE_LINE_MEMBER(mc1502_pit8253_out2_changed);
131	120	DECLARE_WRITE_LINE_MEMBER(pc_com_interrupt_1);
132	121	DECLARE_WRITE_LINE_MEMBER(pc_com_interrupt_2);
133	122	DECLARE_READ8_MEMBER(ibm5160_ppi_porta_r);
r26688	r26689
135	124	DECLARE_WRITE8_MEMBER(ibm5160_ppi_portb_w);
136	125	DECLARE_READ8_MEMBER(pc_ppi_porta_r);
137	126	DECLARE_WRITE8_MEMBER(pc_ppi_portb_w);
138		DECLARE_WRITE8_MEMBER(mc1502_ppi_porta_w);
139		DECLARE_WRITE8_MEMBER(mc1502_ppi_portb_w);
140		DECLARE_READ8_MEMBER(mc1502_ppi_portc_r);
141		DECLARE_READ8_MEMBER(mc1502_kppi_porta_r);
142		DECLARE_READ8_MEMBER(mc1502_kppi_portc_r);
143		DECLARE_WRITE8_MEMBER(mc1502_kppi_portb_w);
144		DECLARE_WRITE8_MEMBER(mc1502_kppi_portc_w);
145	127	DECLARE_WRITE8_MEMBER(pcjr_ppi_portb_w);
146	128	DECLARE_READ8_MEMBER(pcjr_ppi_porta_r);
147	129	DECLARE_READ8_MEMBER(pcjr_ppi_portc_r);
148		DECLARE_READ8_MEMBER(mc1502_wd17xx_aux_r);
149		DECLARE_WRITE8_MEMBER(mc1502_wd17xx_aux_w);
150		DECLARE_READ8_MEMBER(mc1502_wd17xx_drq_r);
151		DECLARE_READ8_MEMBER(mc1502_wd17xx_motor_r);
152	130	DECLARE_WRITE8_MEMBER(pcjr_fdc_dor_w);
153	131	DECLARE_READ8_MEMBER(pcjx_port_1ff_r);
154	132	DECLARE_WRITE8_MEMBER(pcjx_port_1ff_w);
r26688	r26689
159	137	void fdc_dma_drq(bool state);
160	138	void pc_select_dma_channel(int channel, bool state);
161	139	void pc_eop_w(int channel, bool state);
162		void mc1502_fdc_irq_drq(bool state);
163	140	DECLARE_FLOPPY_FORMATS( floppy_formats );
164	141	DECLARE_FLOPPY_FORMATS( asst128_formats );
165	142	IRQ_CALLBACK_MEMBER(pc_irq_callback);
r26688	r26689
201	178	extern const struct am9517a_interface ibm5150_dma8237_config;
202	179	extern const struct pit8253_interface ibm5150_pit8253_config;
203	180	extern const struct pit8253_interface pcjr_pit8253_config;
204		extern const struct pit8253_interface mc1502_pit8253_config;
205	181	extern const ins8250_interface ibm5150_com_interface[4];
206	182	extern const i8255_interface ibm5160_ppi8255_interface;
207	183	extern const i8255_interface pc_ppi8255_interface;
208	184	extern const i8255_interface pcjr_ppi8255_interface;
209		extern const i8251_interface mc1502_i8251_interface;
210		extern const i8255_interface mc1502_ppi8255_interface;
211		extern const i8255_interface mc1502_ppi8255_interface_2;
212	185
213	186	#endif /* PC_H_ */

trunk/hash/ec1841.xml

r26688	r26689
64	64	<year>1988</year>
65	65	<publisher>MPO VT</publisher>
66	66	<part name="flop1" interface="floppy_5_25">
67		<dataarea name="flop" size="368640">
	67	<dataarea name="flop" size="327680">
68	68	<rom name="ec1841-demo.ima" size="327680" sha1="692fc2c01ba1dbceb5626cd3c593ebf8c79d62c3" crc="c273098d" offset="0" />
69	69	</dataarea>
70	70	</part>
71	71	</software>
72	72
	73	<software name="m86v32">
	74	<description>Demo disk</description>
	75	<year>1988</year>
	76	<publisher>MPO VT</publisher>
	77	<part name="flop1" interface="floppy_5_25">
	78	<dataarea name="flop" size="327680">
	79	<rom name="ec1841-m86-3.2.ima" size="327680" sha1="a51bf73114f9178348d0eda0db936fc1f3bd5aa0" crc="69ce32e4" offset="0" />
	80	</dataarea>
	81	</part>
	82	</software>
	83
73	84	<software name="tps2214">
74	85	<description>TPS release 2.2 changeset 14</description>
75	86	<year>1988</year>

trunk/hash/mc1502_flop.xml

r26688	r26689
13	13	</software>
14	14	XXX
15	15	-->
16		<softwarelist name="mc1502_flop" description="MC 1502 disk images">
	16	<softwarelist name="mc1502_flop" description="MC-1502 disk images">
17	17
18	18	<software name="sfdos">
19	19	<description>Sigma Four DOS (modified MS-DOS x.xx)</description>
r26688	r26689
26	26	</part>
27	27	</software>
28	28
29		<software name="ots">
30		<description>One Track System (alternate OS)</description>
31		<year>19??</year>
	29	<software name="ots14">
	30	<description>One Track System 1.4 (alternate OS)</description>
	31	<year>1991</year>
32	32	<publisher>MMV</publisher>
33	33	<part name="flop1" interface="floppy_5_25">
34		<dataarea name="flop" size="737280">
35		<rom name="one-track-system.ima" size="737280" sha1="d7cdb37c00580fe9b4595bac1db588687d187590" crc="33831462" offset="0" />
	34	<dataarea name="flop" size="694040">
	35	<rom name="one-track-system.imd" size="694040" sha1="962e15ec0501d1bd249d05984efd9e9871fa2ce9" crc="62d4ef70" offset="0" />
36	36	</dataarea>
37	37	</part>
38	38	</software>

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