trunk/src/mess/machine/ti99/ti_fdc.c
| r26600 | r26601 | |
|---|
| 78 | 78 | { |
| 79 | 79 | // This is the wait state logic |
| 80 | 80 | if (TRACE_SIGNALS) logerror("tifdc: address=%04x, DRQ=%d, INTRQ=%d, MOTOR=%d\n", m_address & 0xffff, m_DRQ, m_IRQ, m_DVENA); |
| 81 | | line_state nready = (m_WDsel && // Are we accessing 5ffx? |
| 81 | line_state nready = (m_WDsel && // Are we accessing 5ffx (even addr)? |
| 82 | 82 | m_WAITena && // and the wait state generation is active (SBO 2) |
| 83 | 83 | (m_DRQ==CLEAR_LINE) && // and we are waiting for a byte |
| 84 | 84 | (m_IRQ==CLEAR_LINE) && // and there is no interrupt yet |
| 85 | 85 | (m_DVENA==ASSERT_LINE) // and the motor is turning? |
| 86 | 86 | )? ASSERT_LINE : CLEAR_LINE; // In that case, clear READY and thus trigger wait states |
| 87 | 87 | |
| 88 | | if (TRACE_READY) if (nready==ASSERT_LINE) logerror("tifdc: READY line = %d\n", (nready==CLEAR_LINE)? 1:0); |
| 88 | if (TRACE_READY) logerror("tifdc: READY line = %d\n", (nready==CLEAR_LINE)? 1:0); |
| 89 | 89 | m_slot->set_ready((nready==CLEAR_LINE)? ASSERT_LINE : CLEAR_LINE); |
| 90 | 90 | } |
| 91 | 91 | |
| r26600 | r26601 | |
|---|
| 102 | 102 | if (TRACE_ADDRESS) logerror("tifdc: set address = %04x\n", offset & 0xffff); |
| 103 | 103 | |
| 104 | 104 | // Is the WD chip on the card being selected? |
| 105 | | m_WDsel = m_inDsrArea && ((m_address & 0x1ff0)==0x1ff0); |
| 105 | m_WDsel = m_inDsrArea && ((m_address & 0x1ff1)==0x1ff0); |
| 106 | 106 | |
| 107 | 107 | // Clear or assert the outgoing READY line |
| 108 | 108 | set_ready_line(); |