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r26579 Tuesday 10th December, 2013 at 22:11:44 UTC by Angelo Salese
Checkpoint
[src/mame/drivers]hng64.c
[src/mame/includes]hng64.h
[src/mame/video]hng64.c

trunk/src/mame/drivers/hng64.c
r26578r26579
487487   COMBINE_DATA(&m_com_ram[offset]);
488488}
489489
490WRITE32_MEMBER(hng64_state::hng64_com_share_w)
490/* TODO: fully understand this */
491WRITE8_MEMBER(hng64_state::hng64_com_share_mips_w)
491492{
492   logerror("commw  (PC=%08x): %08x %08x %08x\n", space.device().safe_pc(), data, (offset*4)+0xc0001000, mem_mask);
493   m_com_shared[offset ^ 3] = data;
494}
493495
494   if (offset == 0x0) COMBINE_DATA(&m_com_shared_a);
495   if (offset == 0x1) COMBINE_DATA(&m_com_shared_b);
496READ8_MEMBER(hng64_state::hng64_com_share_mips_r)
497{
498   return m_com_shared[offset];
496499}
497500
498READ32_MEMBER(hng64_state::hng64_com_share_r)
501WRITE8_MEMBER(hng64_state::hng64_com_share_w)
499502{
500   logerror("commr  (PC=%08x): %08x %08x\n", space.device().safe_pc(), (offset*4)+0xc0001000, mem_mask);
503   m_com_shared[offset] = data;
504}
501505
502   //if(offset == 0x0) return m_com_shared_a;
503   //if(offset == 0x1) return m_com_shared_b;
506READ8_MEMBER(hng64_state::hng64_com_share_r)
507{
508   if(offset == 4)
509      return m_com_shared[offset] | 1; // some busy flag?
504510
505   if(offset==0x0) return 0x0000aaaa;
506   if(offset==0x1) return 0x00030000;      // fatfurwa : at bfc06624 it wants a 01 : at bfc06650 it wants a 02
507
508   return 0x00;
511   return m_com_shared[offset];
509512}
510513
511514WRITE32_MEMBER(hng64_state::hng64_pal_w)
r26578r26579
859862}
860863#endif
861864
862// Some kind of buffering of the display lists, or 'render current buffer' write?
863WRITE32_MEMBER(hng64_state::dl_control_w)
865WRITE32_MEMBER(hng64_state::dl_upload_w)
864866{
865//  printf("\n");   // Debug - ajg
866   // TODO: put this back in.
867   /*
868   if (activeBuffer==0 || activeBuffer==1)
869       memcpy(&hng64_dls[activeBuffer][0],&hng64_dl[0],0x200);
867   // this handles 3d to fb upload
868#if 0
869   UINT16 packet3d[16];
870870
871   // Only if it's VALID (hack)
872   if (data & 1)
873       activeBuffer = 0;
874   if (data & 2)
875       activeBuffer = 1;
876   */
871   for(int packetStart=0;packetStart<0x200/4;packetStart+=8)
872   {
873      // Create a 3d packet
874      //UINT16 packetStart = offset - 0x08;
875      //if (offset == 0x7f) packetStart += 1;
876
877      for (int i = 0; i < 0x08; i++)
878      {
879         packet3d[i*2+0] = (m_dl[packetStart+i] & 0xffff0000) >> 16;
880         packet3d[i*2+1] = (m_dl[packetStart+i] & 0x0000ffff);
881      }
882
883      // Send it off to the 3d subsystem.
884      hng64_command3d(machine(), packet3d);
885   }
886#endif
877887}
878888
889WRITE32_MEMBER(hng64_state::dl_control_w) // This handles framebuffers
890{
891   if(data & 2) // clear current buffer
892      clear3d();
893
894//   if(data & 1) // swap buffers
895
896//  if(data & 4) // reset buffer count
897}
898
879899#ifdef UNUSED_FUNCTION
880900WRITE32_MEMBER(hng64_state::activate_3d_buffer)
881901{
r26578r26579
11411161   AM_RANGE(0x20200000, 0x20203fff) AM_RAM_WRITE(hng64_pal_w) AM_SHARE("paletteram")
11421162   AM_RANGE(0x20208000, 0x2020805f) AM_READWRITE(tcram_r, tcram_w) AM_SHARE("tcram")   // Transition Control
11431163   AM_RANGE(0x20300000, 0x203001ff) AM_RAM_WRITE(dl_w) AM_SHARE("dl")  // 3d Display List
1144//  AM_RANGE(0x20300200, 0x20300213) AM_RAM_WRITE(xxxx) AM_SHARE("xxxxxxxx")  // 3d Display List Upload?
1164   AM_RANGE(0x20300200, 0x20300213) AM_WRITE(dl_upload_w)  // 3d Display List Upload
11451165   AM_RANGE(0x20300214, 0x20300217) AM_WRITE(dl_control_w)
11461166   AM_RANGE(0x20300218, 0x2030021b) AM_READ(unk_vreg_r)
11471167
r26578r26579
11621182
11631183   // Communications
11641184   AM_RANGE(0xc0000000, 0xc0000fff) AM_READWRITE(hng64_com_r, hng64_com_w) AM_SHARE("com_ram")
1165   AM_RANGE(0xc0001000, 0xc0001007) AM_READWRITE(hng64_com_share_r, hng64_com_share_w)
1185   AM_RANGE(0xc0001000, 0xc0001007) AM_READWRITE8(hng64_com_share_mips_r, hng64_com_share_mips_w,0xffffffff)
11661186
11671187   /* 6e000000-6fffffff */
11681188   /* 80000000-81ffffff */
r26578r26579
11721192   /* a0000000-a3ffffff */
11731193ADDRESS_MAP_END
11741194
1175/**************/
1176/** COMM CPU **/
1177/**************/
1178#define KL5C_MMU_A(xxx) ( (xxx == 0) ? 0x0000 : (state->m_com_mmu_mem[((xxx-1)*2)+1] << 2) | ((state->m_com_mmu_mem[(xxx-1)*2] & 0xc0) >> 6) )
1179#define KL5C_MMU_B(xxx) ( (xxx == 0) ? 0x0000 : (state->m_com_mmu_mem[(xxx-1)*2] & 0x3f) )
1195/*
11960x6010: tests RAM at [3]8000
11801197
1181DIRECT_UPDATE_MEMBER(hng64_state::KL5C80_direct_handler)
1198*/
1199
1200UINT8 hng64_state::read_comm_data(UINT32 offset)
11821201{
1183   direct.explicit_configure(0x0000, 0xffff, 0xffff, m_com_op_base);
1184   return ~0;
1202   if((offset & 0x10000) == 0)
1203      return m_comm_rom[offset & 0xffff];
1204
1205   if(offset & 0x10000)
1206      return m_comm_ram[(offset & 0xffff)];
1207
1208   printf("%08x\n",offset);
1209   return 0xff;
11851210}
11861211
1187static UINT32 KL5C80_translate_address(hng64_state *state, UINT16 vAddr)
1212void hng64_state::write_comm_data(UINT32 offset,UINT8 data)
11881213{
1189   int i;
1190   UINT8 bNum = 4;
1191
1192   /* Determine what B the vAddr is in */
1193   for (i = 1; i < 5; i++)
1214   if((offset & 0x10000) == 0)
11941215   {
1195      if ( ((KL5C_MMU_B(i)+1)*0x400) > vAddr)
1196      {
1197         bNum = i-1;
1198         break;
1199      }
1216      //m_comm_rom[offset];
1217      return;
12001218   }
1201
1202   /* Calculate the full address and return */
1203   if (bNum == 0)
1219   if(offset & 0x10000)
12041220   {
1205      return vAddr;
1221      m_comm_ram[offset & 0xffff] = data;
1222      return;
12061223   }
1207   else
1208   {   /* the offset to the base physical address plus the vAddr's offset from the virtual base */
1209      return ((KL5C_MMU_A(bNum) + (KL5C_MMU_B(bNum)+1)) * 0x400) + (vAddr - ((KL5C_MMU_B(bNum)+1) * 0x400));
1210   }
1211}
12121224
1213static void KL5C80_virtual_mem_sync(hng64_state *state)
1214{
1215   /* The KL5C80 maps each progressive chunk from the beginning of the
1216      virtual region until the beginning of the next virtual region.
1217      This is implemented here in a lame way to simplify the code.  */
12181225
1219   int i,region;
1226   printf("%08x %02x\n",offset,data);
12201227
1221   for (region = 0; region < 5; region++)
1222   {
1223      int logical_offset  = (KL5C_MMU_B(region)+1) * 0x400;
1224      int physical_offset = (KL5C_MMU_A(region) + (KL5C_MMU_B(region)+1)) * 0x400;
1225
1226      /* The first MMU region is a special case */
1227      if (region == 0)
1228      {
1229         logical_offset  = 0x0000;
1230         physical_offset = 0x00000;
1231      }
1232
1233      logerror("Now copying 0x%x to 0x%x\n", physical_offset, logical_offset);
1234      for (i = logical_offset; i <= 0xffff; i++)
1235      {
1236         if (physical_offset+i <= 0xfffff)
1237            state->m_com_op_base[i] = state->m_com_virtual_mem[physical_offset+i];
1238      }
1239   }
12401228}
12411229
1242static void KL5C80_init(hng64_state *state)
1230READ8_MEMBER(hng64_state::hng64_comm_space_r)
12431231{
1244   UINT8 *hng64_com_mmu_mem = state->m_com_mmu_mem;
1232   if((offset & 0xfc00) == 0) // B0 is fixed at 0-0x3ff
1233      return m_comm_rom[offset];
12451234
1246   /* init the MMU */
1247   hng64_com_mmu_mem[0] =
1248   hng64_com_mmu_mem[2] =
1249   hng64_com_mmu_mem[4] =
1250   hng64_com_mmu_mem[6] = 0x3f;
1235   for(int i=0;i<5;i++)
1236   {
1237      if(offset >= m_mmub[i] && offset <= m_mmub[i+1]-1)
1238         return read_comm_data(m_mmua[i]|offset);
1239   }
12511240
1252   hng64_com_mmu_mem[1] =
1253   hng64_com_mmu_mem[3] =
1254   hng64_com_mmu_mem[5] = 0x00;
1255   hng64_com_mmu_mem[7] = 0xf0;
1241   return 0xff;
12561242}
12571243
1258READ8_MEMBER(hng64_state::hng64_comm_memory_r)
1244WRITE8_MEMBER(hng64_state::hng64_comm_space_w)
12591245{
1260   hng64_state *state = machine().driver_data<hng64_state>();
1261   UINT32 physical_address = KL5C80_translate_address(state, offset);
1262   logerror("READING 0x%02x from 0x%04x (0x%05x)\n", m_com_virtual_mem[physical_address], offset, physical_address);
1246   if((offset & 0xfc00) == 0) // B0 is fixed at 0-0x3ff
1247      return;// m_comm_rom[offset];
12631248
1264   /* Custom "virtual" memory map */
1265   if (physical_address >= 0x26000 && physical_address <= 0x28000)
1249   for(int i=0;i<5;i++)
12661250   {
1267      /* May very well be shared memory - it reads 16 bits from it at 0x309 */
1251      if(offset >= m_mmub[i] && offset <= m_mmub[i+1]-1)
1252      {
1253         write_comm_data(m_mmua[i]|offset,data);
1254         return;
1255      }
12681256   }
1269
1270
1271   return m_com_virtual_mem[physical_address];
12721257}
12731258
1274WRITE8_MEMBER(hng64_state::hng64_comm_memory_w)
1259READ8_MEMBER(hng64_state::hng64_comm_mmu_r)
12751260{
1276   // Write to both virtual and physical memory
1277//  UINT32 physical_address = KL5C80_translate_address(offset);
1278//  logerror("WRITING 0x%02x to 0x%04x (0x%05x)\n", hng64_com_virtual_mem[physical_address], offset, physical_address);
1261   return m_mmu_regs[offset];
12791262}
12801263
1281/* KL5C80 I/O handlers */
1282WRITE8_MEMBER(hng64_state::hng64_comm_io_mmu)
1283{
1284   m_com_mmu_mem[offset] = data;
1264#define MMUA (m_mmu_regs[(offset&~1)+0]>>6)|(m_mmu_regs[(offset&~1)+1]<<2)
1265#define MMUB (m_mmu_regs[(offset&~1)+0]&0x3f)
12851266
1286   /* Debugging - you can't change A4 - the hardware doesn't let you */
1287   if (m_com_mmu_mem[7] != 0xf0 || ((m_com_mmu_mem[6] & 0xc0) != 0x00))
1288      logerror("KL5C MMU error !!! Code is trying to change A4!\n");
1289
1290   hng64_state *state = machine().driver_data<hng64_state>();
1291   logerror("COMM CPU MMU WRITE : ");
1292   logerror("B : %02x %02x %02x %02x  A : %03x %03x %03x %03x\n", KL5C_MMU_B(1), KL5C_MMU_B(2), KL5C_MMU_B(3), KL5C_MMU_B(4),
1293                                                   KL5C_MMU_A(1), KL5C_MMU_A(2), KL5C_MMU_A(3), KL5C_MMU_A(4));
1294   KL5C80_virtual_mem_sync(state);
1295}
1296
1297#ifdef UNUSED_FUNCTION
1298READ8_MEMBER(hng64_state::hng64_comm_shared_r)
1267WRITE8_MEMBER(hng64_state::hng64_comm_mmu_w)
12991268{
1300   // I'm thinking 0x54 comes from an interrupt on the MIPS CPU?  Or maybe the Toshiba one?
1301   // Nothing from CPU0 seems to ping the COM CPU as often as it reads 0x54.
1302   // Sometimes it wants 0x54 to be a 0x01 and sometimes it wants a 0x02.
1269   m_mmu_regs[offset] = data;
13031270
1304   // It's not an interrupt on the KL5C80 because they aren't enabled before 0x54 is ping'ed
1305   // There is a special onboard interrupt handler for the KL5C80 though...
1271   /* cheap: avoid to overwrite read only params*/
1272   if((offset & 6) == 6)
1273   {
1274      m_mmu_regs[6] = m_mmu_regs[6] & 0x3f;
1275      m_mmu_regs[7] = 0xf0;
13061276
1307   if (offset==0x00) logerror("COM CPU reading from 0x50.\n");
1308   if (offset==0x01) logerror("COM CPU reading from 0x51.\n");
1309   if (offset==0x02) logerror("COM CPU reading from 0x52.\n");
1310   if (offset==0x03) logerror("COM CPU reading from 0x53.\n");
1311   if (offset==0x04) (hng64_com_shared_b & 0x000000ff) ? return 0xff : return 0x00;
1312}
1277   }
13131278
1314WRITE8_MEMBER(hng64_state::hng64_comm_shared_w)
1315{
1316   if (offset==0x00) hng64_com_shared_a = (hng64_com_shared_a & 0x00ffffff) | (data << 24);
1317   if (offset==0x01) hng64_com_shared_a = (hng64_com_shared_a & 0xff00ffff) | (data << 16);
1318   if (offset==0x02) hng64_com_shared_a = (hng64_com_shared_a & 0xffff00ff) | (data <<  8);
1319   if (offset==0x03) hng64_com_shared_a = (hng64_com_shared_a & 0xffffff00) | (data <<  0);
1320   if (offset==0x04) logerror("COM CPU writing to 0x54.\n");
1321
1322   logerror("COM CPU wrote to com_shared_a : %08x\n", hng64_com_shared_a);
1279   {
1280      m_mmua[offset/2+1] = (m_mmu_regs[(offset&~1)+0]>>6)|(m_mmu_regs[(offset&~1)+1]<<2);
1281      m_mmua[offset/2+1]*= 0x400;
1282      m_mmub[offset/2+1] = (m_mmu_regs[(offset&~1)+0]&0x3f);
1283      m_mmub[offset/2+1]++;
1284      m_mmub[offset/2+1]*= 0x400;
1285      //printf("%d A %08x B %04x\n",offset/2,m_mmua[offset/2],m_mmub[offset/2]);
1286      //printf("A %04x B %02x\n",MMUA,MMUB);
1287   }
13231288}
1324#endif
13251289
13261290static ADDRESS_MAP_START( hng_comm_map, AS_PROGRAM, 8, hng64_state )
1327   AM_RANGE(0x0000,0xffff) AM_READWRITE(hng64_comm_memory_r, hng64_comm_memory_w )
1291   AM_RANGE(0x0000,0xffff) AM_READWRITE(hng64_comm_space_r, hng64_comm_space_w )
13281292ADDRESS_MAP_END
13291293
13301294static ADDRESS_MAP_START( hng_comm_io_map, AS_IO, 8, hng64_state )
13311295   ADDRESS_MAP_GLOBAL_MASK(0xff)
13321296   /* Reserved for the KL5C80 internal hardware */
1333   AM_RANGE(0x00, 0x07) AM_WRITE(hng64_comm_io_mmu ) AM_SHARE("com_mmu_mem")
1297   AM_RANGE(0x00, 0x07) AM_READWRITE(hng64_comm_mmu_r,hng64_comm_mmu_w )
13341298//  AM_RANGE(0x08,0x1f) AM_NOP              /* Reserved */
13351299//  AM_RANGE(0x20,0x25) AM_READWRITE        /* Timer/Counter B */           /* hng64 writes here */
13361300//  AM_RANGE(0x27,0x27) AM_NOP              /* Reserved */
r26578r26579
13431307//  AM_RANGE(0x3c,0x3f) AM_NOP              /* Reserved */
13441308
13451309   /* General IO */
1346   AM_RANGE(0x50,0x54) AM_NOP // AM_WRITE(hng64_comm_shared_r, hng64_comm_shared_w)
1310   AM_RANGE(0x50,0x57) AM_READWRITE(hng64_com_share_r, hng64_com_share_w)
13471311//  AM_RANGE(0x72,0x72) AM_WRITE            /* dunno yet */
13481312ADDRESS_MAP_END
13491313
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17481712      case 224*2: m_set_irq(0x0001);  break; // lv 0 vblank irq
17491713      //case 0*2:   m_set_irq(0x0002);  break; // lv 1
17501714      //case 64*2:  m_set_irq(0x0004);  break; // lv 2
1751      case 128*2: m_set_irq(0x0800);  break; // lv 11 network irq?
1715      case 128*2:   m_set_irq(0x0800);  break; // lv 11 network irq?
17521716   }
17531717}
17541718
r26578r26579
17621726   mips3drc_add_fastram(m_maincpu, 0x00000000, 0x00ffffff, FALSE, m_mainram);
17631727   mips3drc_add_fastram(m_maincpu, 0x04000000, 0x05ffffff, TRUE,  m_cart);
17641728   mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
1729
1730   m_comm_rom = memregion("user2")->base();
1731   m_comm_ram = auto_alloc_array(machine(),UINT8,0x10000);
17651732}
17661733
17671734
17681735void hng64_state::machine_reset()
17691736{
1770   int i;
1771   const UINT8 *rom = memregion("user2")->base();
1772
17731737   /* Sound CPU */
17741738   UINT8 *RAM = (UINT8*)m_soundram;
17751739   membank("bank1")->set_base(&RAM[0x1f0000]); // allows us to boot
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17771741   m_audiocpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
17781742   m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
17791743
1780   /* Comm CPU */
1781   KL5C80_init(this);
1782
1783   /* Fill up virtual memory with ROM */
1784   for (i = 0x0; i < 0x100000; i++)
1785      m_com_virtual_mem[i] = rom[i];
1786
1787   KL5C80_virtual_mem_sync(this);
1788
1789   address_space &space = m_comm->space(AS_PROGRAM);
1790   space.set_direct_update_handler(direct_update_delegate(FUNC(hng64_state::KL5C80_direct_handler), this));
1791
1792   m_comm->set_input_line(INPUT_LINE_RESET, PULSE_LINE);     // reset the CPU and let 'er rip
1744//   m_comm->set_input_line(INPUT_LINE_RESET, PULSE_LINE);     // reset the CPU and let 'er rip
17931745//  m_comm->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);     // hold on there pardner...
17941746
17951747   // "Display List" init - ugly
1796   m_activeBuffer = 0;
1748//   m_activeBuffer = 0;
17971749
17981750   /* For simulate MCU stepping */
17991751   m_mcu_fake_time = 0;
18001752   m_mcu_en = 0;
1753
1754   m_mmub[0] = 0;
1755   m_mmub[5] = 0; // rolls back to 0xffff
18011756}
18021757
18031758
trunk/src/mame/includes/hng64.h
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2828      m_3dregs(*this, "3dregs"),
2929      m_3d_1(*this, "3d_1"),
3030      m_3d_2(*this, "3d_2"),
31      m_com_ram(*this, "com_ram"),
32      m_com_mmu_mem(*this, "com_mmu_mem"){ }
31      m_com_ram(*this, "com_ram")
32      { }
3333
3434   required_device<cpu_device> m_maincpu;
3535   required_device<cpu_device> m_audiocpu;
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5252   required_shared_ptr<UINT32> m_3d_2;
5353
5454   required_shared_ptr<UINT32> m_com_ram;
55   required_shared_ptr<UINT8> m_com_mmu_mem;
55   //required_shared_ptr<UINT8> m_com_mmu_mem;
5656
5757
5858   int m_mcu_type;
r26578r26579
6363   /* Communications stuff */
6464   UINT8  *m_com_op_base;
6565   UINT8  *m_com_virtual_mem;
66   UINT32 m_com_shared_a;
67   UINT32 m_com_shared_b;
66   UINT8 m_com_shared[8];
6867
6968   INT32 m_dma_start;
7069   INT32 m_dma_dst;
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126125   DECLARE_READ32_MEMBER(hng64_random_read);
127126   DECLARE_READ32_MEMBER(hng64_com_r);
128127   DECLARE_WRITE32_MEMBER(hng64_com_w);
129   DECLARE_WRITE32_MEMBER(hng64_com_share_w);
130   DECLARE_READ32_MEMBER(hng64_com_share_r);
128   DECLARE_WRITE8_MEMBER(hng64_com_share_w);
129   DECLARE_READ8_MEMBER(hng64_com_share_r);
130   DECLARE_WRITE8_MEMBER(hng64_com_share_mips_w);
131   DECLARE_READ8_MEMBER(hng64_com_share_mips_r);
131132   DECLARE_WRITE32_MEMBER(hng64_pal_w);
132133   DECLARE_READ32_MEMBER(hng64_sysregs_r);
133134   DECLARE_WRITE32_MEMBER(hng64_sysregs_w);
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143144   DECLARE_WRITE32_MEMBER(dl_w);
144145   DECLARE_READ32_MEMBER(dl_r);
145146   DECLARE_WRITE32_MEMBER(dl_control_w);
147   DECLARE_WRITE32_MEMBER(dl_upload_w);
146148   DECLARE_WRITE32_MEMBER(tcram_w);
147149   DECLARE_READ32_MEMBER(tcram_r);
148150   DECLARE_READ32_MEMBER(unk_vreg_r);
149151   DECLARE_WRITE32_MEMBER(hng64_soundram_w);
150
151152   DECLARE_READ32_MEMBER(hng64_soundram_r);
152153
153154   // not actually used, but left in code so you can turn it and see the (possibly undesired?) behavior, see notes in memory map
r26578r26579
158159
159160   DECLARE_WRITE32_MEMBER(hng64_sprite_clear_even_w);
160161   DECLARE_WRITE32_MEMBER(hng64_sprite_clear_odd_w);
161   DECLARE_READ8_MEMBER(hng64_comm_memory_r);
162   DECLARE_WRITE8_MEMBER(hng64_comm_memory_w);
163   DECLARE_WRITE8_MEMBER(hng64_comm_io_mmu);
164162   DECLARE_WRITE32_MEMBER(trap_write);
165163   DECLARE_WRITE32_MEMBER(hng64_3d_1_w);
166164   DECLARE_WRITE32_MEMBER(activate_3d_buffer);
167165   DECLARE_READ8_MEMBER(hng64_comm_shared_r);
168166   DECLARE_WRITE8_MEMBER(hng64_comm_shared_w);
169167   DECLARE_WRITE32_MEMBER(hng64_videoram_w);
170   DECLARE_DIRECT_UPDATE_MEMBER(KL5C80_direct_handler);
168   DECLARE_READ8_MEMBER(hng64_comm_space_r);
169   DECLARE_WRITE8_MEMBER(hng64_comm_space_w);
170   DECLARE_READ8_MEMBER(hng64_comm_mmu_r);
171   DECLARE_WRITE8_MEMBER(hng64_comm_mmu_w);
171172   DECLARE_DRIVER_INIT(hng64_race);
172173   DECLARE_DRIVER_INIT(fatfurwa);
173174   DECLARE_DRIVER_INIT(hng64);
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178179
179180   void m_set_irq(UINT32 irq_vector);
180181   UINT32 m_irq_pending;
182   UINT8 *m_comm_rom;
183   UINT8 *m_comm_ram;
184   UINT8 m_mmu_regs[8];
185   UINT32 m_mmua[6];
186   UINT16 m_mmub[6];
187   UINT8 read_comm_data(UINT32 offset);
188   void write_comm_data(UINT32 offset,UINT8 data);
181189   int m_irq_level;
182190   TILE_GET_INFO_MEMBER(get_hng64_tile0_8x8_info);
183191   TILE_GET_INFO_MEMBER(get_hng64_tile0_16x16_info);
r26578r26579
193201   UINT32 screen_update_hng64(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
194202   void screen_eof_hng64(screen_device &screen, bool state);
195203   TIMER_DEVICE_CALLBACK_MEMBER(hng64_irq);
204
205   void clear3d();
206
196207};
197208
198209/*----------- defined in video/hng64.c -----------*/
trunk/src/mame/video/hng64.c
r26578r26579
55#define MAKE_MAME_REEEEAAALLLL_SLOW 0
66
77
8static void clear3d(running_machine &machine);  // TODO: Inline
98
109
1110static void hng64_mark_all_tiles_dirty( hng64_state *state, int tilemap )
r26578r26579
16331632void hng64_state::screen_eof_hng64(screen_device &screen, bool state)
16341633{
16351634   // rising edge
1636   if (state)
1637      clear3d(machine());
1635   //if (state)
1636   //   clear3d();
16381637}
16391638
16401639void hng64_state::video_start()
r26578r26579
25142513   int numPolys = 0;
25152514   struct polygon* polys = auto_alloc_array(machine, struct polygon, 1024*5);
25162515
2517   //printf("packet type : %04x\n", packet[0]);
2516   //printf("packet type : %04x %04x|%04x %04x|%04x %04x|%04x %04x\n", packet[0],packet[1],packet[2],packet[3],packet[4],packet[5],packet[6],packet[7]);
25182517   switch (packet[0])
25192518   {
25202519   case 0x0000:    // Appears to be a NOP.
r26578r26579
26012600   auto_free(machine, polys);
26022601}
26032602
2604static void clear3d(running_machine &machine)
2603void hng64_state::clear3d()
26052604{
2606   hng64_state *state = machine.driver_data<hng64_state>();
26072605   int i;
26082606
2609   const rectangle &visarea = machine.primary_screen->visible_area();
2607   const rectangle &visarea = machine().primary_screen->visible_area();
26102608
26112609   // Clear each of the display list buffers after drawing - todo: kill!
26122610   for (i = 0; i < 0x81; i++)
26132611   {
2614      state->m_dls[0][i] = 0;
2615      state->m_dls[1][i] = 0;
2612      m_dls[0][i] = 0;
2613      m_dls[1][i] = 0;
26162614   }
26172615
26182616   // Reset the buffers...
26192617   for (i = 0; i < (visarea.max_x)*(visarea.max_y); i++)
26202618   {
2621      state->m_depthBuffer3d[i] = 100.0f;
2622      state->m_colorBuffer3d[i] = MAKE_ARGB(0, 0, 0, 0);
2619      m_depthBuffer3d[i] = 100.0f;
2620      m_colorBuffer3d[i] = MAKE_ARGB(0, 0, 0, 0);
26232621   }
26242622
26252623   // Set some matrices to the identity...
2626   setIdentity(state->m_projectionMatrix);
2627   setIdentity(state->m_modelViewMatrix);
2628   setIdentity(state->m_cameraMatrix);
2624   setIdentity(m_projectionMatrix);
2625   setIdentity(m_modelViewMatrix);
2626   setIdentity(m_cameraMatrix);
26292627}
26302628
26312629/* 3D/framebuffer video registers
r26578r26579
26342632 * UINT32 | Bits                                    | Use
26352633 *        | 3322 2222 2222 1111 1111 11             |
26362634 * -------+-1098-7654-3210-9876-5432-1098-7654-3210-+----------------
2635 *      0 | ---- --x- ---- ---- ---- ---- ---- ---- | Reads in Fatal Fury WA, if on then there isn't a 3d refresh (busy flag?).
2636 *      0 | ---- ---x ---- ---- ---- ---- ---- ---- | set at POST, probably 3d disable
26372637 *      0 | ???? ???? ???? ???? ccc? ???? ???? ???? | framebuffer color base, 0x311800 in Fatal Fury WA, 0x313800 in Buriki One
26382638 *      1 |                                         |
26392639 *      2 | ???? ???? ???? ???? ???? ???? ???? ???? | camera / framebuffer global x/y? Actively used by Samurai Shodown 64 2

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