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r26544 Sunday 8th December, 2013 at 17:25:42 UTC by Angelo Salese
Merged othldrby.c with toaplan2.c driver [Angelo Salese]
[src/mame]mame.mak
[src/mame/drivers]othldrby.c toaplan2.c
[src/mame/includes]othldrby.h toaplan2.h
[src/mame/video]othldrby.c

trunk/src/mame/drivers/othldrby.c
r26543r26544
1/***************************************************************************
2
3Othello Derby
4
5driver by Nicola Salmoria
6
7Video IC is S951060-VGP
8
9TODO:
10- a PCB pic is needed in order to identify the RTC used by this.
11
12Notes:
13- Sprite/tile priorities are NOT orthogonal to sprite/sprite priorities:
14  sprites with a higher priority appear over sprites with a lower priority,
15  regardless of their order in the sprite list. Therefore, the current
16  implementation is correct.
17
18***************************************************************************/
19
20#include "emu.h"
21#include "cpu/m68000/m68000.h"
22#include "sound/okim6295.h"
23#include "includes/othldrby.h"
24
25
26/* Guess: reads when doing r/w to video device */
27READ16_MEMBER(othldrby_state::othldrby_scanline_r)
28{
29   return m_screen->vpos();
30}
31
32
33WRITE16_MEMBER(othldrby_state::oki_bankswitch_w)
34{
35   if (ACCESSING_BITS_0_7)
36      m_oki->set_bank_base((data & 1) * 0x40000);
37}
38
39WRITE16_MEMBER(othldrby_state::coinctrl_w)
40{
41   if (ACCESSING_BITS_0_7)
42   {
43      coin_counter_w(machine(), 0, data & 1);
44      coin_counter_w(machine(), 1, data & 2);
45      coin_lockout_w(machine(), 0, ~data & 4);
46      coin_lockout_w(machine(), 1, ~data & 8);
47   }
48}
49
50WRITE16_MEMBER(othldrby_state::calendar_w)
51{
52}
53
54READ16_MEMBER(othldrby_state::calendar_r)
55{
56   system_time systime;
57
58   machine().base_datetime(systime);
59
60   switch (offset)
61   {
62      case 0:
63         return ((systime.local_time.second/10)<<4) + (systime.local_time.second%10);
64      case 1:
65         return ((systime.local_time.minute/10)<<4) + (systime.local_time.minute%10);
66      case 2:
67         return ((systime.local_time.hour/10)<<4) + (systime.local_time.hour%10);
68      case 3:
69         return systime.local_time.weekday;
70      case 4:
71         return ((systime.local_time.mday/10)<<4) + (systime.local_time.mday%10);
72      case 5:
73         return (systime.local_time.month + 1);
74      case 6:
75         return (((systime.local_time.year%100)/10)<<4) + (systime.local_time.year%10);
76      case 7:
77      default:
78         return 0;   /* status? the other registers are read only when bit 0 is clear */
79   }
80}
81
82
83static ADDRESS_MAP_START( othldrby_map, AS_PROGRAM, 16, othldrby_state )
84   AM_RANGE(0x000000, 0x07ffff) AM_ROM
85   AM_RANGE(0x100000, 0x10ffff) AM_RAM
86   AM_RANGE(0x200000, 0x20000f) AM_READWRITE(calendar_r, calendar_w)
87   AM_RANGE(0x300000, 0x300001) AM_WRITE(othldrby_videoram_addr_w)
88   AM_RANGE(0x300004, 0x300007) AM_READWRITE(othldrby_videoram_r, othldrby_videoram_w)
89   AM_RANGE(0x300008, 0x300009) AM_WRITE(othldrby_vreg_addr_w)
90   AM_RANGE(0x30000c, 0x30000d) AM_READ_PORT("VBLANK")
91   AM_RANGE(0x30000c, 0x30000f) AM_WRITE(othldrby_vreg_w)
92   AM_RANGE(0x400000, 0x400fff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")
93   AM_RANGE(0x600000, 0x600001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
94   AM_RANGE(0x700000, 0x700001) AM_READ(othldrby_scanline_r)
95   AM_RANGE(0x700004, 0x700005) AM_READ_PORT("DSW1")
96   AM_RANGE(0x700008, 0x700009) AM_READ_PORT("DSW2")
97   AM_RANGE(0x70000c, 0x70000d) AM_READ_PORT("P1")
98   AM_RANGE(0x700010, 0x700011) AM_READ_PORT("P2")
99   AM_RANGE(0x70001c, 0x70001d) AM_READ_PORT("SYSTEM")
100   AM_RANGE(0x700030, 0x700031) AM_WRITE(oki_bankswitch_w)
101   AM_RANGE(0x700034, 0x700035) AM_WRITE(coinctrl_w)
102ADDRESS_MAP_END
103
104
105static INPUT_PORTS_START( othldrby )
106   PORT_START("VBLANK")
107   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_VBLANK("screen")
108
109   PORT_START("DSW1")
110   PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
111   PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
112   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
113   PORT_DIPNAME( 0x02, 0x00, DEF_STR( Flip_Screen ) )
114   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
115   PORT_DIPSETTING(    0x02, DEF_STR( On ) )
116   PORT_SERVICE( 0x04, IP_ACTIVE_HIGH )
117   PORT_DIPNAME( 0x08, 0x00, DEF_STR( Allow_Continue ) )
118   PORT_DIPSETTING(    0x08, DEF_STR( No ) )
119   PORT_DIPSETTING(    0x00, DEF_STR( Yes ) )
120   PORT_DIPNAME( 0x30, 0x00, DEF_STR( Coin_A ) )
121   PORT_DIPSETTING(    0x30, DEF_STR( 3C_1C ) )
122   PORT_DIPSETTING(    0x20, DEF_STR( 2C_1C ) )
123   PORT_DIPSETTING(    0x00, DEF_STR( 1C_1C ) )
124   PORT_DIPSETTING(    0x10, DEF_STR( 1C_2C ) )
125   PORT_DIPNAME( 0xc0, 0x00, DEF_STR( Coin_B ) )
126   PORT_DIPSETTING(    0xc0, DEF_STR( 3C_1C ) )
127   PORT_DIPSETTING(    0x80, DEF_STR( 2C_1C ) )
128   PORT_DIPSETTING(    0x00, DEF_STR( 1C_1C ) )
129   PORT_DIPSETTING(    0x40, DEF_STR( 1C_2C ) )
130
131   PORT_START("DSW2")
132   PORT_DIPNAME( 0x03, 0x00, DEF_STR( Difficulty ) )
133   PORT_DIPSETTING(    0x01, DEF_STR( Easy ) )
134   PORT_DIPSETTING(    0x00, DEF_STR( Normal ) )
135   PORT_DIPSETTING(    0x02, DEF_STR( Hard ) )
136   PORT_DIPSETTING(    0x03, DEF_STR( Very_Hard ) )
137   PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unused ) )
138   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
139   PORT_DIPSETTING(    0x04, DEF_STR( On ) )
140   PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unused ) )
141   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
142   PORT_DIPSETTING(    0x08, DEF_STR( On ) )
143   PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unused ) )
144   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
145   PORT_DIPSETTING(    0x10, DEF_STR( On ) )
146   PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unused ) )
147   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
148   PORT_DIPSETTING(    0x20, DEF_STR( On ) )
149   PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unused ) )
150   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
151   PORT_DIPSETTING(    0x40, DEF_STR( On ) )
152   PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unused ) )
153   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
154   PORT_DIPSETTING(    0x80, DEF_STR( On ) )
155
156   PORT_START("P1")
157   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
158   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
159   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
160   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
161   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(1)
162   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(1)
163   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(1)
164   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
165
166   PORT_START("P2")
167   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
168   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
169   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
170   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
171   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2)
172   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(2)
173   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(2)
174   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
175
176   PORT_START("SYSTEM")
177   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SERVICE1 )
178   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN )
179   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SERVICE2 )  /* TEST */
180   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
181   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_IMPULSE(1)
182   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_START1 )
183   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START2 )
184   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
185INPUT_PORTS_END
186
187
188
189static const gfx_layout spritelayout =
190{
191   8,8,
192   RGN_FRAC(1,2),
193   4,
194   { RGN_FRAC(1,2)+8, RGN_FRAC(1,2)+0, RGN_FRAC(0,2)+8, RGN_FRAC(0,2)+0 },
195   { 0, 1, 2, 3, 4, 5, 6, 7 },
196   { 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16 },
197   16*8
198};
199
200static const gfx_layout tilelayout =
201{
202   16,16,
203   RGN_FRAC(1,2),
204   4,
205   { RGN_FRAC(1,2)+8, RGN_FRAC(1,2)+0, RGN_FRAC(0,2)+8, RGN_FRAC(0,2)+0 },
206   { 0, 1, 2, 3, 4, 5, 6, 7,
207         16*8+0, 16*8+1, 16*8+2, 16*8+3, 16*8+4, 16*8+5, 16*8+6, 16*8+7 },
208   { 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
209         16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16 },
210   16*32
211};
212
213static GFXDECODE_START( othldrby )
214   GFXDECODE_ENTRY( "gfx1", 0, spritelayout, 0, 0x80 )
215   GFXDECODE_ENTRY( "gfx1", 0, tilelayout,   0, 0x80 )
216GFXDECODE_END
217
218
219
220void othldrby_state::machine_start()
221{
222   save_item(NAME(m_toggle));
223   save_item(NAME(m_vram_addr));
224   save_item(NAME(m_vreg_addr));
225   save_item(NAME(m_vreg));
226}
227
228void othldrby_state::machine_reset()
229{
230   m_toggle = 0xff;
231   m_vram_addr = 0;
232   m_vreg_addr = 0;
233
234   memset(m_vreg, 0, sizeof(m_vreg));
235}
236
237static MACHINE_CONFIG_START( othldrby, othldrby_state )
238
239   /* basic machine hardware */
240   MCFG_CPU_ADD("maincpu", M68000, 16000000)
241   MCFG_CPU_PROGRAM_MAP(othldrby_map)
242   MCFG_CPU_VBLANK_INT_DRIVER("screen", othldrby_state,  irq4_line_hold)
243
244
245   /* video hardware */
246   MCFG_SCREEN_ADD("screen", RASTER)
247   MCFG_SCREEN_REFRESH_RATE(60)
248   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
249   MCFG_SCREEN_SIZE(64*8, 32*8)
250   MCFG_SCREEN_VISIBLE_AREA(12*8, (64-12)*8-1, 1*8, 31*8-1 )
251   MCFG_SCREEN_UPDATE_DRIVER(othldrby_state, screen_update_othldrby)
252   MCFG_SCREEN_VBLANK_DRIVER(othldrby_state, screen_eof_othldrby)
253
254   MCFG_GFXDECODE(othldrby)
255   MCFG_PALETTE_LENGTH(0x800)
256
257
258   /* sound hardware */
259   MCFG_SPEAKER_STANDARD_MONO("mono")
260
261   MCFG_OKIM6295_ADD("oki", 1584000, OKIM6295_PIN7_HIGH) // clock frequency & pin 7 not verified
262   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
263MACHINE_CONFIG_END
264
265
266
267/***************************************************************************
268
269  Game driver(s)
270
271***************************************************************************/
272
273ROM_START( othldrby )
274   ROM_REGION( 0x080000, "maincpu", 0 )
275   ROM_LOAD16_WORD_SWAP( "db0.1",        0x00000, 0x80000, CRC(6b4008d3) SHA1(4cf838c47563ba482be8364b2e115569a4a06c83) )
276
277   ROM_REGION( 0x400000, "gfx1", 0 )
278   ROM_LOAD( "db0-r2",       0x000000, 0x200000, CRC(4efff265) SHA1(4cd239ff42f532495946cb52bd1fee412f84e192) )
279   ROM_LOAD( "db0-r3",       0x200000, 0x200000, CRC(5c142b38) SHA1(5466a8b061a0f2545493de0f96fd4387beea276a) )
280
281   ROM_REGION( 0x080000, "oki", 0 )    /* OKIM6295 samples */
282   ROM_LOAD( "db0.4",        0x00000, 0x80000, CRC(a9701868) SHA1(9ee89556666d358e8d3915622573b3ba660048b8) )
283ROM_END
284
285GAME( 1995, othldrby, 0, othldrby, othldrby, driver_device, 0, ROT0, "Sunwise", "Othello Derby (Japan)", GAME_SUPPORTS_SAVE )
trunk/src/mame/drivers/toaplan2.c
r26543r26544
44        Raizing/8ing game hardware from 1993 onwards
55        -------------------------------------------------
66        Driver by: Quench and Yochizo
7        Original othldrby.c by Nicola Salmoria
78
89   Raizing games and Truxton 2 are heavily dependent on the Raine source -
910   many thanks to Richard Bush and the Raine team. [Yochizo]
r26543r26544
3536    batsugun    TP-030        Toaplan       Batsugun
3637    batsuguna   TP-030        Toaplan       Batsugun (older)
3738    batsugunsp  TP-030        Toaplan       Batsugun (Special Version)
38    pwrkick     ??????        Sunwise       Power Kick
3939    snowbro2    ??????        Hanafram      Snow Bros. 2 - With New Elves
4040
4141    * This version of Whoopee!! is on a board labeled TP-020
r26543r26544
343343    - Need to sort out the video status register.
344344    - Find out how exactly how sound CPU communication really works in bgaregga/batrider/bbakraid
345345        current emulation seems to work (plays all sounds), but there are still some unknown reads/writes
346    - Write a RTC core for uPD4992, needed by Othello Derby and Power Kick
346347
347
348348*****************************************************************************/
349349
350350
r26543r26544
12051205   AM_RANGE(0x700000, 0x700001) AM_READ(video_count_r)
12061206ADDRESS_MAP_END
12071207
1208/* TODO: write in a proper core */
1209WRITE8_MEMBER(toaplan2_state::upd4992_calendar_w)
1210{
1211}
1212
1213READ8_MEMBER(toaplan2_state::upd4992_calendar_r)
1214{
1215   system_time systime;
1216
1217   machine().base_datetime(systime);
1218
1219   switch (offset)
1220   {
1221      case 0:
1222         return ((systime.local_time.second/10)<<4) + (systime.local_time.second%10);
1223      case 1:
1224         return ((systime.local_time.minute/10)<<4) + (systime.local_time.minute%10);
1225      case 2:
1226         return ((systime.local_time.hour/10)<<4) + (systime.local_time.hour%10);
1227      case 3:
1228         return systime.local_time.weekday;
1229      case 4:
1230         return ((systime.local_time.mday/10)<<4) + (systime.local_time.mday%10);
1231      case 5:
1232         return (systime.local_time.month + 1);
1233      case 6:
1234         return (((systime.local_time.year%100)/10)<<4) + (systime.local_time.year%10);
1235      case 7:
1236      default:
1237         return 0;   /* status? the other registers are read only when bit 0 is clear */
1238   }
1239}
1240
12081241static ADDRESS_MAP_START( pwrkick_68k_mem, AS_PROGRAM, 16, toaplan2_state )
12091242   AM_RANGE(0x000000, 0x07ffff) AM_ROM
12101243   AM_RANGE(0x100000, 0x10ffff) AM_RAM
1211   AM_RANGE(0x200000, 0x20000f) AM_RAM // uPD4992 RTC
1244   AM_RANGE(0x200000, 0x20000f) AM_READWRITE8(upd4992_calendar_r,upd4992_calendar_w,0x00ff)
12121245   AM_RANGE(0x300000, 0x30000d) AM_DEVREADWRITE("gp9001vdp0", gp9001vdp_device, gp9001_vdp_r, gp9001_vdp_w)
12131246   AM_RANGE(0x400000, 0x400fff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")
12141247   AM_RANGE(0x600000, 0x600001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
1215   AM_RANGE(0x700000, 0x700001) AM_READ(video_count_r) // check me
1248
1249   AM_RANGE(0x700000, 0x700001) AM_READ(video_count_r)
12161250   AM_RANGE(0x700004, 0x700005) AM_READ_PORT("DSWA")
12171251   AM_RANGE(0x700008, 0x700009) AM_READ_PORT("DSWB")
12181252   AM_RANGE(0x70000c, 0x70000d) AM_READ_PORT("IN1")
r26543r26544
12241258   AM_RANGE(0x700038, 0x700039) AM_WRITENOP // lamps?
12251259ADDRESS_MAP_END
12261260
1261static ADDRESS_MAP_START( othldrby_68k_mem, AS_PROGRAM, 16, toaplan2_state )
1262   AM_RANGE(0x000000, 0x07ffff) AM_ROM
1263   AM_RANGE(0x100000, 0x10ffff) AM_RAM
1264   AM_RANGE(0x200000, 0x20000f) AM_READWRITE8(upd4992_calendar_r,upd4992_calendar_w,0x00ff)
1265   AM_RANGE(0x300000, 0x30000d) AM_DEVREADWRITE("gp9001vdp0", gp9001vdp_device, gp9001_vdp_r, gp9001_vdp_w)
1266   AM_RANGE(0x400000, 0x400fff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")
1267   AM_RANGE(0x600000, 0x600001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
12271268
1269   AM_RANGE(0x700000, 0x700001) AM_READ(video_count_r)
1270   AM_RANGE(0x700004, 0x700005) AM_READ_PORT("DSWA")
1271   AM_RANGE(0x700008, 0x700009) AM_READ_PORT("DSWB")
1272   AM_RANGE(0x70000c, 0x70000d) AM_READ_PORT("IN1")
1273   AM_RANGE(0x700010, 0x700011) AM_READ_PORT("IN2")
1274   AM_RANGE(0x70001c, 0x70001d) AM_READ_PORT("SYS")
1275   AM_RANGE(0x700030, 0x700031) AM_WRITE(oki_bankswitch_w)
1276   AM_RANGE(0x700034, 0x700035) AM_WRITE(toaplan2_coin_word_w)
1277ADDRESS_MAP_END
1278
1279
1280
12281281static ADDRESS_MAP_START( snowbro2_68k_mem, AS_PROGRAM, 16, toaplan2_state )
12291282   AM_RANGE(0x000000, 0x07ffff) AM_ROM
12301283   AM_RANGE(0x100000, 0x10ffff) AM_RAM
r26543r26544
24442497   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 )
24452498INPUT_PORTS_END
24462499
2500static INPUT_PORTS_START( othldrby )
2501   PORT_INCLUDE( toaplan2_3b )
2502
2503   PORT_MODIFY("SYS")
2504   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
2505   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_IMPULSE(1)
2506
2507   PORT_MODIFY("DSWA")
2508   PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
2509   PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
2510   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
2511   PORT_DIPNAME( 0x02, 0x00, DEF_STR( Flip_Screen ) )
2512   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
2513   PORT_DIPSETTING(    0x02, DEF_STR( On ) )
2514   PORT_SERVICE( 0x04, IP_ACTIVE_HIGH )
2515   PORT_DIPNAME( 0x08, 0x00, DEF_STR( Allow_Continue ) )
2516   PORT_DIPSETTING(    0x08, DEF_STR( No ) )
2517   PORT_DIPSETTING(    0x00, DEF_STR( Yes ) )
2518   PORT_DIPNAME( 0x30, 0x00, DEF_STR( Coin_A ) )
2519   PORT_DIPSETTING(    0x30, DEF_STR( 3C_1C ) )
2520   PORT_DIPSETTING(    0x20, DEF_STR( 2C_1C ) )
2521   PORT_DIPSETTING(    0x00, DEF_STR( 1C_1C ) )
2522   PORT_DIPSETTING(    0x10, DEF_STR( 1C_2C ) )
2523   PORT_DIPNAME( 0xc0, 0x00, DEF_STR( Coin_B ) )
2524   PORT_DIPSETTING(    0xc0, DEF_STR( 3C_1C ) )
2525   PORT_DIPSETTING(    0x80, DEF_STR( 2C_1C ) )
2526   PORT_DIPSETTING(    0x00, DEF_STR( 1C_1C ) )
2527   PORT_DIPSETTING(    0x40, DEF_STR( 1C_2C ) )
2528
2529   PORT_MODIFY("DSWB")
2530   PORT_DIPNAME( 0x03, 0x00, DEF_STR( Difficulty ) )
2531   PORT_DIPSETTING(    0x01, DEF_STR( Easy ) )
2532   PORT_DIPSETTING(    0x00, DEF_STR( Normal ) )
2533   PORT_DIPSETTING(    0x02, DEF_STR( Hard ) )
2534   PORT_DIPSETTING(    0x03, DEF_STR( Very_Hard ) )
2535   PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unused ) )
2536   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
2537   PORT_DIPSETTING(    0x04, DEF_STR( On ) )
2538   PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unused ) )
2539   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
2540   PORT_DIPSETTING(    0x08, DEF_STR( On ) )
2541   PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unused ) )
2542   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
2543   PORT_DIPSETTING(    0x10, DEF_STR( On ) )
2544   PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unused ) )
2545   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
2546   PORT_DIPSETTING(    0x20, DEF_STR( On ) )
2547   PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unused ) )
2548   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
2549   PORT_DIPSETTING(    0x40, DEF_STR( On ) )
2550   PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unused ) )
2551   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
2552   PORT_DIPSETTING(    0x80, DEF_STR( On ) )
2553INPUT_PORTS_END
2554
24472555static INPUT_PORTS_START( snowbro2 )
24482556   PORT_INCLUDE( toaplan2_2b )
24492557
r26543r26544
36193727   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.5)
36203728MACHINE_CONFIG_END
36213729
3730/* TODO: clocks */
36223731static MACHINE_CONFIG_START( pwrkick, toaplan2_state )
36233732
36243733   /* basic machine hardware */
3625   MCFG_CPU_ADD("maincpu", M68000, XTAL_16MHz)           /* 16MHz , 16MHz Oscillator */
3734   MCFG_CPU_ADD("maincpu", M68000, XTAL_16MHz)
36263735   MCFG_CPU_PROGRAM_MAP(pwrkick_68k_mem)
36273736   MCFG_CPU_VBLANK_INT_DRIVER("screen", toaplan2_state,  toaplan2_vblank_irq4)
36283737
r26543r26544
36473756
36483757   /* sound hardware */
36493758   MCFG_SPEAKER_STANDARD_MONO("mono")
3650
3651   MCFG_YM2151_ADD("ymsnd", XTAL_27MHz/8)
3759   /* empty YM2151 socket*/
3760   MCFG_OKIM6295_ADD("oki", XTAL_27MHz/8, OKIM6295_PIN7_HIGH)
36523761   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.5)
3762MACHINE_CONFIG_END
36533763
3654   MCFG_OKIM6295_ADD("oki", XTAL_16MHz/4, OKIM6295_PIN7_LOW)
3764static MACHINE_CONFIG_START( othldrby, toaplan2_state )
3765   /* basic machine hardware */
3766   MCFG_CPU_ADD("maincpu", M68000, XTAL_16MHz)
3767   MCFG_CPU_PROGRAM_MAP(othldrby_68k_mem)
3768   MCFG_CPU_VBLANK_INT_DRIVER("screen", toaplan2_state,  toaplan2_vblank_irq4)
3769
3770   MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
3771
3772   /* video hardware */
3773   MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
3774
3775   MCFG_SCREEN_ADD("screen", RASTER)
3776   MCFG_SCREEN_REFRESH_RATE(60)
3777   MCFG_SCREEN_SIZE(432, 262)
3778   MCFG_SCREEN_VISIBLE_AREA(0, 319, 0, 239)
3779   MCFG_SCREEN_UPDATE_DRIVER(toaplan2_state, screen_update_toaplan2)
3780   MCFG_SCREEN_VBLANK_DRIVER(toaplan2_state, screen_eof_toaplan2)
3781
3782   MCFG_GFXDECODE(toaplan2)
3783   MCFG_PALETTE_LENGTH(T2PALETTE_LENGTH)
3784
3785   MCFG_DEVICE_ADD_VDP0
3786
3787   MCFG_VIDEO_START_OVERRIDE(toaplan2_state,toaplan2)
3788
3789   /* sound hardware */
3790   MCFG_SPEAKER_STANDARD_MONO("mono")
3791
3792   MCFG_OKIM6295_ADD("oki", XTAL_27MHz/8, OKIM6295_PIN7_HIGH)
36553793   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.5)
36563794MACHINE_CONFIG_END
36573795
r26543r26544
44844622   ROM_LOAD( "4.u33",        0x000000, 0x080000, CRC(3ab742f1) SHA1(ce8ca02ca57fd77872e421ce601afd017d3518a0) )
44854623ROM_END
44864624
4625ROM_START( othldrby )
4626   ROM_REGION( 0x080000, "maincpu", 0 )
4627   ROM_LOAD16_WORD_SWAP( "db0.1",        0x00000, 0x80000, CRC(6b4008d3) SHA1(4cf838c47563ba482be8364b2e115569a4a06c83) )
44874628
4629   ROM_REGION( 0x400000, "gfx1", 0 )
4630   ROM_LOAD( "db0-r2",       0x000000, 0x200000, CRC(4efff265) SHA1(4cd239ff42f532495946cb52bd1fee412f84e192) )
4631   ROM_LOAD( "db0-r3",       0x200000, 0x200000, CRC(5c142b38) SHA1(5466a8b061a0f2545493de0f96fd4387beea276a) )
4632
4633   ROM_REGION( 0x080000, "oki", 0 )    /* OKIM6295 samples */
4634   ROM_LOAD( "db0.4",        0x00000, 0x80000, CRC(a9701868) SHA1(9ee89556666d358e8d3915622573b3ba660048b8) )
4635ROM_END
4636
44884637ROM_START( snowbro2 )
44894638   ROM_REGION( 0x080000, "maincpu", 0 )            /* Main 68K code */
44904639   ROM_LOAD16_WORD_SWAP( "pro-4", 0x000000, 0x080000, CRC(4c7ee341) SHA1(ad46c605a38565d0148daac301be4e4b72302fe7) )
r26543r26544
51935342GAME( 1993, batsugunsp, batsugun, batsugun, batsugun, toaplan2_state,   dogyuun, ROT270, "Toaplan", "Batsugun - Special Version", GAME_SUPPORTS_SAVE )
51945343
51955344GAME( 1994, pwrkick,    0,        pwrkick,  pwrkick, driver_device,    0,       ROT0,   "Sunwise",  "Power Kick (Japan)", 0 )
5345GAME( 1995, othldrby,   0,        othldrby, othldrby,driver_device,    0,       ROT0,   "Sunwise",  "Othello Derby (Japan)", 0 )
51965346
51975347GAME( 1994, snowbro2,   0,        snowbro2, snowbro2, driver_device,   0,       ROT0,   "Hanafram", "Snow Bros. 2 - With New Elves / Otenki Paradise", GAME_SUPPORTS_SAVE )
51985348
trunk/src/mame/mame.mak
r26543r26544
21742174   $(DRIVERS)/oneshot.o $(VIDEO)/oneshot.o \
21752175   $(DRIVERS)/onetwo.o \
21762176   $(DRIVERS)/othello.o \
2177   $(DRIVERS)/othldrby.o $(VIDEO)/othldrby.o \
21782177   $(DRIVERS)/pachifev.o \
21792178   $(DRIVERS)/pasha2.o \
21802179   $(DRIVERS)/pass.o $(VIDEO)/pass.o \
trunk/src/mame/includes/othldrby.h
r26543r26544
1/*************************************************************************
2
3    Othello Derby
4
5*************************************************************************/
6#include "sound/okim6295.h"
7
8#define OTHLDRBY_VREG_SIZE   18
9
10class othldrby_state : public driver_device
11{
12public:
13   othldrby_state(const machine_config &mconfig, device_type type, const char *tag)
14      : driver_device(mconfig, type, tag) ,
15      m_maincpu(*this, "maincpu"),
16      m_oki(*this, "oki") { }
17
18   /* memory pointers */
19   UINT16 *     m_vram;
20   UINT16 *     m_buf_spriteram;
21   UINT16 *     m_buf_spriteram2;
22
23   /* video-related */
24   tilemap_t    *m_bg_tilemap[3];
25   UINT16       m_vreg[OTHLDRBY_VREG_SIZE];
26   UINT32       m_vram_addr;
27   UINT32       m_vreg_addr;
28
29   /* misc */
30   int          m_toggle;
31   DECLARE_READ16_MEMBER(othldrby_scanline_r);
32   DECLARE_WRITE16_MEMBER(coinctrl_w);
33   DECLARE_WRITE16_MEMBER(calendar_w);
34   DECLARE_READ16_MEMBER(calendar_r);
35   DECLARE_WRITE16_MEMBER(othldrby_videoram_addr_w);
36   DECLARE_READ16_MEMBER(othldrby_videoram_r);
37   DECLARE_WRITE16_MEMBER(othldrby_videoram_w);
38   DECLARE_WRITE16_MEMBER(othldrby_vreg_addr_w);
39   DECLARE_WRITE16_MEMBER(othldrby_vreg_w);
40   DECLARE_WRITE16_MEMBER(oki_bankswitch_w);
41   TILE_GET_INFO_MEMBER(get_tile_info0);
42   TILE_GET_INFO_MEMBER(get_tile_info1);
43   TILE_GET_INFO_MEMBER(get_tile_info2);
44   virtual void machine_start();
45   virtual void machine_reset();
46   virtual void video_start();
47   UINT32 screen_update_othldrby(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
48   void screen_eof_othldrby(screen_device &screen, bool state);
49   inline void get_tile_info( tile_data &tileinfo, int tile_index, int plane );
50   void draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect, int priority );
51   required_device<cpu_device> m_maincpu;
52   required_device<okim6295_device> m_oki;
53};
trunk/src/mame/includes/toaplan2.h
r26543r26544
159159   UINT8 m_pwrkick_hopper;
160160   DECLARE_CUSTOM_INPUT_MEMBER(pwrkick_hopper_status_r);
161161   DECLARE_WRITE8_MEMBER(pwrkick_coin_w);
162   DECLARE_READ8_MEMBER(upd4992_calendar_r);
163   DECLARE_WRITE8_MEMBER(upd4992_calendar_w);
162164
163165protected:
164166   virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
trunk/src/mame/video/othldrby.c
r26543r26544
1#include "emu.h"
2#include "includes/othldrby.h"
3
4
5#define VIDEORAM_SIZE      0x1c00
6#define SPRITERAM_START    0x1800
7#define SPRITERAM_SIZE     (VIDEORAM_SIZE - SPRITERAM_START)
8
9
10/***************************************************************************
11
12  Callbacks for the TileMap code
13
14***************************************************************************/
15
16inline void othldrby_state::get_tile_info( tile_data &tileinfo, int tile_index, int plane )
17{
18   UINT16 attr;
19
20   tile_index = 2 * tile_index + 0x800 * plane;
21   attr = m_vram[tile_index];
22   SET_TILE_INFO_MEMBER(
23         1,
24         m_vram[tile_index + 1],
25         attr & 0x7f,
26         0);
27   tileinfo.category = (attr & 0x0600) >> 9;
28}
29
30TILE_GET_INFO_MEMBER(othldrby_state::get_tile_info0)
31{
32   get_tile_info(tileinfo, tile_index, 0);
33}
34
35TILE_GET_INFO_MEMBER(othldrby_state::get_tile_info1)
36{
37   get_tile_info(tileinfo, tile_index, 1);
38}
39
40TILE_GET_INFO_MEMBER(othldrby_state::get_tile_info2)
41{
42   get_tile_info(tileinfo, tile_index, 2);
43}
44
45
46
47/***************************************************************************
48
49  Start the video hardware emulation.
50
51***************************************************************************/
52
53void othldrby_state::video_start()
54{
55   m_bg_tilemap[0] = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(othldrby_state::get_tile_info0),this), TILEMAP_SCAN_ROWS, 16, 16, 32, 32);
56   m_bg_tilemap[1] = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(othldrby_state::get_tile_info1),this), TILEMAP_SCAN_ROWS, 16, 16, 32, 32);
57   m_bg_tilemap[2] = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(othldrby_state::get_tile_info2),this), TILEMAP_SCAN_ROWS, 16, 16, 32, 32);
58
59   m_vram = auto_alloc_array(machine(), UINT16, VIDEORAM_SIZE);
60   m_buf_spriteram = auto_alloc_array(machine(), UINT16, 2 * SPRITERAM_SIZE);
61   m_buf_spriteram2 = m_buf_spriteram + SPRITERAM_SIZE;
62
63   m_bg_tilemap[0]->set_transparent_pen(0);
64   m_bg_tilemap[1]->set_transparent_pen(0);
65   m_bg_tilemap[2]->set_transparent_pen(0);
66
67   save_pointer(NAME(m_vram), VIDEORAM_SIZE);
68   save_pointer(NAME(m_buf_spriteram), 2 * SPRITERAM_SIZE);
69}
70
71
72
73/***************************************************************************
74
75  Memory handlers
76
77***************************************************************************/
78
79WRITE16_MEMBER(othldrby_state::othldrby_videoram_addr_w)
80{
81   m_vram_addr = data;
82}
83
84READ16_MEMBER(othldrby_state::othldrby_videoram_r)
85{
86   if (m_vram_addr < VIDEORAM_SIZE)
87      return m_vram[m_vram_addr++];
88   else
89   {
90      popmessage("GFXRAM OUT OF BOUNDS %04x", m_vram_addr);
91      return 0;
92   }
93}
94
95WRITE16_MEMBER(othldrby_state::othldrby_videoram_w)
96{
97   if (m_vram_addr < VIDEORAM_SIZE)
98   {
99      if (m_vram_addr < SPRITERAM_START)
100         m_bg_tilemap[m_vram_addr / 0x800]->mark_tile_dirty((m_vram_addr & 0x7ff) / 2);
101      m_vram[m_vram_addr++] = data;
102   }
103   else
104      popmessage("GFXRAM OUT OF BOUNDS %04x", m_vram_addr);
105}
106
107WRITE16_MEMBER(othldrby_state::othldrby_vreg_addr_w)
108{
109   m_vreg_addr = data & 0x7f;  /* bit 7 is set when screen is flipped */
110}
111
112WRITE16_MEMBER(othldrby_state::othldrby_vreg_w)
113{
114   if (m_vreg_addr < OTHLDRBY_VREG_SIZE)
115      m_vreg[m_vreg_addr++] = data;
116   else
117      popmessage("%06x: VREG OUT OF BOUNDS %04x", space.device().safe_pc(), m_vreg_addr);
118}
119
120
121
122/***************************************************************************
123
124  Display refresh
125
126***************************************************************************/
127
128void othldrby_state::draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect, int priority )
129{
130   int offs;
131
132   for (offs = 0; offs < SPRITERAM_SIZE; offs += 4)
133   {
134      int x, y, color, code, sx, sy, flipx, flipy, sizex, sizey, pri;
135
136      pri = (m_buf_spriteram[offs] & 0x0600) >> 9;
137      if (pri != priority)
138         continue;
139
140      flipx = m_buf_spriteram[offs] & 0x1000;
141      flipy = 0;
142      color = (m_buf_spriteram[offs] & 0x01fc) >> 2;
143      code = m_buf_spriteram[offs + 1] | ((m_buf_spriteram[offs] & 0x0003) << 16);
144      sx = (m_buf_spriteram[offs + 2] >> 7);
145      sy = (m_buf_spriteram[offs + 3] >> 7);
146      sizex = (m_buf_spriteram[offs + 2] & 0x000f) + 1;
147      sizey = (m_buf_spriteram[offs + 3] & 0x000f) + 1;
148
149      if (flip_screen())
150      {
151         flipx = !flipx;
152         flipy = !flipy;
153         sx = 246 - sx;
154         sy = 16 - sy;
155      }
156
157      for (y = 0; y < sizey; y++)
158      {
159         for (x = 0; x < sizex; x++)
160         {
161            drawgfx_transpen(bitmap,cliprect,machine().gfx[0],
162                  code + x + sizex * y,
163                  color,
164                  flipx,flipy,
165                  (sx + (flipx ? (-8*(x+1)+1) : 8*x) - m_vreg[6]+44) & 0x1ff,(sy + (flipy ? (-8*(y+1)+1) : 8*y) - m_vreg[7]-9) & 0x1ff,0);
166         }
167      }
168   }
169}
170
171UINT32 othldrby_state::screen_update_othldrby(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
172{
173   int layer;
174
175   flip_screen_set(m_vreg[0x0f] & 0x80);
176
177   for (layer = 0; layer < 3; layer++)
178   {
179      if (flip_screen())
180      {
181         m_bg_tilemap[layer]->set_scrollx(0, m_vreg[2 * layer] + 59);
182         m_bg_tilemap[layer]->set_scrolly(0, m_vreg[2 * layer + 1] + 248);
183      }
184      else
185      {
186         m_bg_tilemap[layer]->set_scrollx(0, m_vreg[2 * layer] - 58);
187         m_bg_tilemap[layer]->set_scrolly(0, m_vreg[2 * layer+1] + 9);
188      }
189   }
190
191   screen.priority().fill(0, cliprect);
192
193   bitmap.fill(0, cliprect);
194
195   for (layer = 0; layer < 3; layer++)
196      m_bg_tilemap[layer]->draw(screen, bitmap, cliprect, 0, 0);
197   draw_sprites(bitmap, cliprect, 0);
198
199   for (layer = 0; layer < 3; layer++)
200      m_bg_tilemap[layer]->draw(screen, bitmap, cliprect, 1, 0);
201   draw_sprites(bitmap, cliprect, 1);
202
203   for (layer = 0; layer < 3; layer++)
204      m_bg_tilemap[layer]->draw(screen, bitmap, cliprect, 2, 0);
205   draw_sprites(bitmap, cliprect, 2);
206
207   for (layer = 0; layer < 3; layer++)
208      m_bg_tilemap[layer]->draw(screen, bitmap, cliprect, 3, 0);
209   draw_sprites(bitmap, cliprect, 3);
210
211   return 0;
212}
213
214void othldrby_state::screen_eof_othldrby(screen_device &screen, bool state)
215{
216   // rising edge
217   if (state)
218   {
219      /* sprites need to be delayed two frames */
220      memcpy(m_buf_spriteram, m_buf_spriteram2, SPRITERAM_SIZE * sizeof(m_buf_spriteram[0]));
221      memcpy(m_buf_spriteram2, &m_vram[SPRITERAM_START], SPRITERAM_SIZE * sizeof(m_buf_spriteram[0]));
222   }
223}

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