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r26387 Saturday 23rd November, 2013 at 22:06:53 UTC by Michael Zapf
tms99xx: Improved debugging output, cycle fine-tuning. (nw)
[src/emu/cpu/tms9900]tms9900.c tms9900.h tms9980a.c

trunk/src/emu/cpu/tms9900/tms9980a.c
r26386r26387
147147   {
148148      if (m_irq_level == LOAD_INT)
149149      {
150         // Clearing m_reset is a hack to prevent an initial RESET.
151         // Should fix that in tms99xx
150         // Some boards start up with LOAD interrupt, so we clear the reset flag
152151         m_reset = false;
153152         m_load_state = true;
154153      }
trunk/src/emu/cpu/tms9900/tms9900.c
r26386r26387
119119   ST_IM = 0x000f      // Interrupt mask
120120};
121121
122#define LOG logerror
123#define VERBOSE 1
122/*
123    The following defines can be set to 0 or 1 to disable or enable certain
124    output in the log.
125*/
126// Emulation setup
127#define TRACE_SETUP 0
124128
129// Emulation details
130#define TRACE_EMU 0
131
132// Location and command
133#define TRACE_EXEC 0
134
135// Memory operation
136#define TRACE_MEM 0
137
138// Cycle count
139#define TRACE_CYCLES 0
140
141// Clock ticks
142#define TRACE_CLOCK 0
143
144// Wait states
145#define TRACE_WAIT 0
146
147// Interrupts
148#define TRACE_INT 0
149
150// CRU operation
151#define TRACE_CRU 0
152
153// Status register
154#define TRACE_STATUS 0
155
156// ALU details
157#define TRACE_ALU 0
158
159// Microinstruction level
160#define TRACE_MICRO 0
161
125162/****************************************************************************
126163    Common constructor for TMS9900 and TMS9980A
127164    The CRU mask is related to the bits, not to their addresses which are
r26386r26387
192229void tms99xx_device::device_stop()
193230{
194231   int k = 0;
195   if (VERBOSE>3) LOG("tms99xx: Deleting lookup tables\n");
232   if (TRACE_SETUP) logerror("tms99xx: Deleting lookup tables\n");
196233   while (m_lotables[k]!=NULL) delete[] m_lotables[k++];
197234}
198235
r26386r26387
221258*/
222259void tms99xx_device::device_reset()
223260{
224   if (VERBOSE>3) LOG("tms99xx: Device reset\n");
261   if (TRACE_EMU) logerror("tms99xx: Device reset by emulator\n");
225262   m_reset = true;
226263   m_check_ready = false;
227264   m_wait_state = false;
r26386r26387
522559{
523560   ALU_NOP,
524561   DATA_DERIVE,    // Get argument
525   ALU_XOP,        // 0 Save the address of the source operand, set address = 0x0040 + xopNr*4
562   ALU_XOP,        // 0 Save the address of the source operand, set address = 0x0040 + xopNr*4, 6 cycles
526563   MEMORY_READ,    // Read the new WP
527564   ALU_XOP,        // 1 Save old WP, set new WP, get the source operand address
528565   MEMORY_WRITE,   // Write the address of the source operand into the new R11
r26386r26387
535572   ALU_XOP,        // 5 Set the X bit in the ST
536573   MEMORY_READ,    // Read the new PC
537574   ALU_XOP,        // 6 Set the new PC
538   ALU_NOP,
539575   END
540576};
541577
r26386r26387
579615   ALU_NOP,
580616   DATA_DERIVE,
581617   ALU_B,
618   ALU_NOP,
582619   MEMORY_WRITE,
583   ALU_NOP,
584620   END
585621};
586622
r26386r26387
589625   ALU_NOP,
590626   DATA_DERIVE,            // Get argument
591627   ALU_BLWP,               // 0 Save old WP, set new WP, save position
628   ALU_NOP,
592629   MEMORY_WRITE,           // write ST to R15
593630   ALU_BLWP,               // 1
594631   MEMORY_WRITE,           // write PC to R14
r26386r26387
607644   ALU_SOURCE,
608645   ALU_NOP,
609646   ALU_LDCR,
647   ALU_NOP,
610648   MEMORY_READ,
611649   ALU_LDCR,
612650   CRU_OUTPUT,
r26386r26387
619657   ALU_NOP,
620658   DATA_DERIVE,
621659   ALU_SOURCE,         // Store address and value
622   ALU_STCR,           // 0 Set register_number = 12
660   ALU_STCR,           // 0 Set register_number = 12; 0 cycles (already done before)
623661   MEMORY_READ,
624662   ALU_STCR,           // 1 Prepare CRU access
663   ALU_NOP,
625664   CRU_INPUT,
626665   ALU_STCR,           // 2 Create result; Cycles = 5 + (8-#C-1) or + (16-#C)
666   ALU_NOP,
667   ALU_NOP,
668   ALU_NOP,
627669   MEMORY_WRITE,
628670   END
629671};
r26386r26387
631673MICROPROGRAM(sbz_sbo_mp)
632674{
633675   ALU_SBZ_SBO,
676   ALU_NOP,
634677   MEMORY_READ,
635678   ALU_SBZ_SBO,
636679   CRU_OUTPUT,
r26386r26387
650693MICROPROGRAM(jmp_mp)
651694{
652695   ALU_NOP,
653   ALU_NOP,
654696   ALU_JMP,
655697   ALU_JMP,
698   ALU_NOP,
656699   END
657700};
658701
r26386r26387
729772
730773MICROPROGRAM(external_mp)
731774{
775   ALU_NOP,
776   ALU_NOP,
732777   ALU_EXT,
778   ALU_NOP,
779   ALU_NOP,
733780   END
734781};
735782
736MICROPROGRAM(rtwp_mp)       // Problem: This makes RTWP use 8 instead of 7 machine cycles.
783MICROPROGRAM(rtwp_mp)
737784{
785   ALU_NOP,
738786   ALU_RTWP,
739787   MEMORY_READ,
740   ALU_RTWP,
788   ALU_RTWP,               // no cycles
741789   MEMORY_READ,
742   ALU_RTWP,
790   ALU_RTWP,               // no cycles
743791   MEMORY_READ,
744792   ALU_RTWP,
745793   END
r26386r26387
10021050   {
10031051      inst = &s_command[i];
10041052      table = m_command_lookup_table;
1005      if (VERBOSE>8) LOG("tms99xx: === opcode=%04x, len=%d\n", inst->opcode, format_mask_len[inst->format]);
1053      if (TRACE_SETUP) logerror("tms99xx: === opcode=%04x, len=%d\n", inst->opcode, format_mask_len[inst->format]);
10061054      bitcount = 4;
10071055      opcode = inst->opcode;
10081056      cmdindex = (opcode>>12) & 0x000f;
r26386r26387
10121060         // Descend
10131061         if (table[cmdindex].next_digit == NULL)
10141062         {
1015            if (VERBOSE>8) LOG("tms99xx: create new table at bitcount=%d for index=%d\n", bitcount, cmdindex);
1063            if (TRACE_SETUP) logerror("tms99xx: create new table at bitcount=%d for index=%d\n", bitcount, cmdindex);
10161064            table[cmdindex].next_digit = new lookup_entry[16];
10171065            m_lotables[k++] = table[cmdindex].next_digit;
10181066            for (int j=0; j < 16; j++)
r26386r26387
10231071         }
10241072         else
10251073         {
1026            if (VERBOSE>8) LOG("tms99xx: found a table at bitcount=%d\n", bitcount);
1074            if (TRACE_SETUP) logerror("tms99xx: found a table at bitcount=%d\n", bitcount);
10271075         }
10281076
10291077         table = table[cmdindex].next_digit;
r26386r26387
10311079         bitcount = bitcount+4;
10321080         opcode <<= 4;
10331081         cmdindex = (opcode>>12) & 0x000f;
1034         if (VERBOSE>8) LOG("tms99xx: next index=%x\n", cmdindex);
1082         if (TRACE_SETUP) logerror("tms99xx: next index=%x\n", cmdindex);
10351083      }
10361084
1037      if (VERBOSE>8) LOG("tms99xx: bitcount=%d\n", bitcount);
1085      if (TRACE_SETUP) logerror("tms99xx: bitcount=%d\n", bitcount);
10381086      // We are at the target level
10391087      // Need to fill in the same entry for all values in the bitcount
10401088      // (if a command needs 10 bits we have to copy it four
10411089      // times for all combinations with 12 bits)
10421090      for (int j=0; j < (1<<(bitcount-format_mask_len[inst->format])); j++)
10431091      {
1044         if (VERBOSE>8) LOG("tms99xx: opcode=%04x at position %d\n", inst->opcode, cmdindex+j);
1092         if (TRACE_SETUP) logerror("tms99xx: opcode=%04x at position %d\n", inst->opcode, cmdindex+j);
10451093         table[cmdindex+j].entry = inst;
10461094      }
10471095
r26386r26387
10491097   } while (inst->opcode != 0xf000);
10501098
10511099   m_lotables[k++] = NULL;
1052   if (VERBOSE>8) LOG("tms99xx: Allocated %d tables\n", k);
1100   if (TRACE_SETUP) logerror("tms99xx: Allocated %d tables\n", k);
10531101}
10541102
10551103/*
r26386r26387
10921140{
10931141   if (m_reset) service_interrupt();
10941142
1095   if (VERBOSE>6) LOG("tms99xx: calling execute_run for %d cycles\n", m_icount);
1143   if (TRACE_EMU) logerror("tms99xx: calling execute_run for %d cycles\n", m_icount);
10961144   do
10971145   {
10981146      // Only when last instruction has completed
r26386r26387
11001148      {
11011149         if (m_load_state)
11021150         {
1103            if (VERBOSE>4) LOG("tms99xx: LOAD interrupt\n");
1151            logerror("tms99xx: LOAD interrupt\n");
11041152            m_irq_level = LOAD_INT;
11051153            m_irq_state = false;
11061154            service_interrupt();
r26386r26387
11181166
11191167      if (m_program == NULL && m_idle_state)
11201168      {
1121         if (VERBOSE>5) LOG("tms99xx: idle state\n");
1169         if (TRACE_WAIT) logerror("tms99xx: idle state\n");
11221170         pulse_clock(1);
11231171         m_external_operation(IDLE_OP, 0);
11241172         m_external_operation(IDLE_OP, 1);
r26386r26387
11341182            m_program[MPC] != MEMORY_READ && m_program[MPC] != MEMORY_WRITE &&
11351183            m_program[MPC] != REG_READ && m_program[MPC] != REG_WRITE)))
11361184         {
1137            if (VERBOSE>2) LOG("tms99xx: hold state\n");
1185            if (TRACE_WAIT) logerror("tms99xx: hold\n");
11381186            if (!m_hold_acknowledged) acknowledge_hold();
11391187            pulse_clock(1);
11401188         }
r26386r26387
11451193            {
11461194               // We are in a wait state
11471195               set_wait_state(true);
1148               if (VERBOSE>2) LOG("tms99xx: wait state\n");
1196               if (TRACE_WAIT) logerror("tms99xx: wait\n");
11491197               // The clock output should be used to change the state of an outer
11501198               // device which operates the READY line
11511199               pulse_clock(1);
r26386r26387
11601208               {
11611209                  m_op = m_program[MPC];
11621210               }
1163               if (VERBOSE>8) LOG("tms99xx: MPC = %d, m_op = %d\n", MPC, m_op);
1211               if (TRACE_MICRO) logerror("tms99xx: MPC = %d, m_op = %d\n", MPC, m_op);
11641212               // Call the operation of the microprogram
11651213               (this->*s_microoperation[m_op])();
11661214               // If we have multiple passes (as in the TMS9980)
r26386r26387
11761224         }
11771225      }
11781226   } while (m_icount>0 && !m_reset);
1179   if (VERBOSE>6) LOG("tms99xx: cycles expired; will return soon.\n");
1227   if (TRACE_EMU) logerror("tms99xx: cycles expired; will return soon.\n");
11801228}
11811229
11821230/**************************************************************************/
r26386r26387
11961244      {
11971245         m_load_state = (state==ASSERT_LINE);
11981246         m_irq_level = -1;
1247         m_reset = false;
11991248      }
12001249      else
12011250      {
r26386r26387
12031252         if (state==ASSERT_LINE)
12041253         {
12051254            m_irq_level = get_intlevel(state);
1206            if (VERBOSE>6) LOG("tms99xx: interrupt line %d = %d, level=%d, ST=%04x\n", irqline, state, m_irq_level, ST);
1255            if (TRACE_INT) logerror("tms99xx: /INT asserted, level=%d, ST=%04x\n", m_irq_level, ST);
12071256         }
12081257         else
12091258         {
1210            if (VERBOSE>6) LOG("tms99xx: cleared interrupt line %d\n", irqline);
1259            if (TRACE_INT) logerror("tms99xx: /INT cleared\n");
12111260         }
12121261      }
12131262   }
r26386r26387
12531302
12541303      m_reset = false;
12551304   }
1256   if (VERBOSE>6) LOG("tms99xx: ********* triggered an interrupt on level %d\n", m_irq_level);
1305   if (TRACE_INT)
1306   {
1307      switch (m_irq_level)
1308      {
1309      case RESET_INT: logerror("tms99xx: **** triggered a RESET interrupt\n"); break;
1310      case LOAD_INT: logerror("tms99xx: **** triggered a LOAD (NMI) interrupt\n"); break;
1311      default: logerror("tms99xx: ** triggered an interrupt on level %d\n", m_irq_level); break;
1312      }
1313   }
12571314
12581315   MPC = 0;
12591316   m_first_cycle = m_icount;
r26386r26387
12701327      m_ready = m_ready_bufd;              // get the latched READY state
12711328      m_clock_out_line(CLEAR_LINE);
12721329      m_icount--;                         // This is the only location where we count down the cycles.
1273      if (VERBOSE>7)
1330      if (TRACE_CLOCK)
12741331      {
1275         if (m_check_ready) LOG("tms99xx: pulse_clock, READY=%d\n", m_ready? 1:0);
1276         else LOG("tms99xx: pulse_clock\n");
1332         if (m_check_ready) logerror("tms99xx: pulse_clock, READY=%d\n", m_ready? 1:0);
1333         else logerror("tms99xx: pulse_clock\n");
12771334      }
12781335   }
12791336}
r26386r26387
13431400   while (!complete)
13441401   {
13451402      index = (opcode >> 12) & 0x000f;
1346      if (VERBOSE>8) LOG("tms99xx: Check next hex digit of instruction %x\n", index);
1403      if (TRACE_MICRO) logerror("tms99xx: Check next hex digit of instruction %x\n", index);
13471404      if (table[index].next_digit != NULL)
13481405      {
13491406         table = table[index].next_digit;
r26386r26387
13551412   if (decoded == NULL)
13561413   {
13571414      // not found
1358      if (VERBOSE>0) LOG("tms99xx: Illegal opcode %04x\n", inst);
1415      logerror("tms99xx: Illegal opcode %04x\n", inst);
13591416      IR = 0;
13601417      // This will cause another instruction acquisition in the next machine cycle
13611418      // with an asserted IAQ line (can be used to indicate this illegal opcode detection).
r26386r26387
13661423      m_program = decoded->prog;
13671424      MPC = -1;
13681425      m_command = decoded->id;
1369      if (VERBOSE>8) LOG("tms99xx: Command decoded as id %d, %s, base opcode %04x\n", m_command, opname[m_command], decoded->opcode);
1426      if (TRACE_MICRO) logerror("tms99xx: Command decoded as id %d, %s, base opcode %04x\n", m_command, opname[m_command], decoded->opcode);
13701427      // Byte operations are either format 1 with the byte flag set
13711428      // or format 4 (CRU multi bit operations) with 1-8 bits to transfer.
13721429      m_byteop = ((decoded->format==1 && ((IR & 0x1000)!=0))
r26386r26387
13941451   if (m_mem_phase == 1)
13951452   {
13961453      decode(m_current_value);
1397      if (VERBOSE>3) LOG("tms99xx: ===== Next operation %04x (%s) at %04x =====\n", IR, opname[m_command], PC);
1454      if (TRACE_EXEC) logerror("tms99xx: %04x: %04x (%s)\n", PC, IR, opname[m_command]);
13981455      debugger_instruction_hook(this, PC);
13991456      PC = (PC + 2) & 0xfffe & m_prgaddr_mask;
14001457      // IAQ will be cleared in the main loop
r26386r26387
14181475      m_check_ready = true;
14191476      m_mem_phase = 2;
14201477      m_pass = 2;
1421      if (VERBOSE>7) LOG("tms99xx: set address bus %04x\n", m_address);
1478      if (TRACE_MEM) logerror("tms99xx: set address (r) %04x\n", m_address);
14221479
14231480      pulse_clock(1); // Concludes the first cycle
14241481      // If READY has been found to be low, the CPU will now stay in the wait state loop
r26386r26387
14301487      pulse_clock(1);
14311488      m_dbin_line(CLEAR_LINE);
14321489      m_mem_phase = 1;        // reset to phase 1
1433      if (VERBOSE>7) LOG("tms99xx: memory read %04x -> %04x\n", m_address, m_current_value);
1490      if (TRACE_MEM) logerror("tms99xx: mem r %04x -> %04x\n", m_address, m_current_value);
14341491   }
14351492}
14361493
r26386r26387
14401497   {
14411498      m_dbin_line(CLEAR_LINE);
14421499      // When writing, the data bus is asserted immediately after the address bus
1443      if (VERBOSE>7) LOG("tms99xx: set address bus %04x\n", m_address);
1500      if (TRACE_MEM) logerror("tms99xx: set address (w) %04x\n", m_address);
14441501      m_prgspace->set_address(m_address & m_prgaddr_mask & 0xfffe);
1445      if (VERBOSE>7) LOG("tms99xx: memory write %04x <- %04x\n", m_address, m_current_value);
1502      if (TRACE_MEM) logerror("tms99xx: mem w %04x <- %04x\n", m_address, m_current_value);
14461503      m_prgspace->write_word(m_address & m_prgaddr_mask & 0xfffe, m_current_value);
14471504      m_check_ready = true;
14481505      m_mem_phase = 2;
r26386r26387
15601617   // Write m_count bits from cru_address
15611618   for (int i=0; i < m_count; i++)
15621619   {
1563      if (VERBOSE>5) LOG("tms99xx: CRU output operation, address %04x, value %d\n", location<<1, value & 0x01);
1620      if (TRACE_CRU) logerror("tms99xx: CRU output operation, address %04x, value %d\n", location<<1, value & 0x01);
15641621      m_cru->write_byte(location, (value & 0x01));
15651622      value >>= 1;
15661623      location = (location + 1) & m_cruaddr_mask;
r26386r26387
15801637void tms99xx_device::command_completed()
15811638{
15821639   // Pseudo state at the end of the current instruction cycle sequence
1583   if (VERBOSE>4)
1640   if (TRACE_CYCLES)
15841641   {
1585      LOG("tms99xx: +++++ Instruction %04x (%s) completed", IR, opname[m_command]);
1642      logerror("tms99xx: ------");
15861643      int cycles =  m_first_cycle - m_icount;
15871644      // Avoid nonsense values due to expired and resumed main loop
1588      if (cycles > 0 && cycles < 10000) LOG(", consumed %d cycles", cycles);
1589      LOG(" +++++\n");
1645      if (cycles > 0 && cycles < 10000) logerror(" %d cycles", cycles);
1646      logerror("\n");
15901647   }
15911648   m_program = NULL;
15921649}
r26386r26387
16481705   set_status_bit(ST_EQ, value1 == value2);
16491706   set_status_bit(ST_LH, value1 > value2);
16501707   set_status_bit(ST_AGT, (INT16)value1 > (INT16)value2);
1651   if (VERBOSE>7) LOG("tms99xx: ST = %04x (val1=%04x, val2=%04x)\n", ST, value1, value2);
1708   if (TRACE_STATUS) logerror("tms99xx: ST = %04x (val1=%04x, val2=%04x)\n", ST, value1, value2);
16521709}
16531710
16541711/**************************************************************************
r26386r26387
17161773
17171774void tms99xx_device::alu_imm()
17181775{
1719   if (VERBOSE>7) LOG("tms99xx: Immediate operand, reading from position %04x\n", PC);
17201776   m_value_copy = m_current_value;
17211777   m_address_copy = m_address;
17221778   m_address = PC;
r26386r26387
18861942            compare_and_set_lae(m_current_value, 0);
18871943         }
18881944      }
1889      if (VERBOSE>7) LOG("tms99xx: ST = %04x\n", ST);
1945      if (TRACE_STATUS) logerror("tms99xx: ST = %04x\n", ST);
18901946      break;
18911947   }
18921948
r26386r26387
19051961      m_address = ((IR >> 5) & 0x001e) + WP;
19061962      break;
19071963   case 1: // After reading the register (multiplier)
1908      if (VERBOSE>7) LOG("tms99xx: Multiply %04x by %04x\n", m_current_value, m_source_value);
1964      if (TRACE_ALU) logerror("tms99xx: Multiply %04x by %04x\n", m_current_value, m_source_value);
19091965      result = (m_source_value & 0x0000ffff) * (m_current_value & 0x0000ffff);
19101966      m_current_value = (result >> 16) & 0xffff;
19111967      m_value_copy = result & 0xffff;
r26386r26387
19542010      // Create full word and perform division
19552011      uval32 = (m_value_copy << 16) | m_current_value;
19562012
1957      if (VERBOSE>7) LOG("tms99xx: Dividing %08x by %04x\n", uval32, m_source_value);
2013      if (TRACE_ALU) logerror("tms99xx: Dividing %08x by %04x\n", uval32, m_source_value);
19582014      m_current_value = uval32 / m_source_value;
19592015      m_value_copy = uval32 % m_source_value;
19602016
1961      if (VERBOSE>7) LOG("tms99xx: Quotient %04x, remainder %04x\n", m_current_value, m_value_copy);
2017      if (TRACE_ALU) logerror("tms99xx: Quotient %04x, remainder %04x\n", m_current_value, m_value_copy);
19622018
19632019      m_address = m_address_copy;
19642020
r26386r26387
19842040      // Prepare to write the remainder
19852041      m_current_value = m_value_copy;
19862042      m_address = m_address + 2;
1987      if (VERBOSE>7) LOG("tms99xx: ST = %04x (div)\n", ST);
2043      if (TRACE_STATUS) logerror("tms99xx: ST = %04x (div)\n", ST);
19882044      break;
19892045   }
19902046   pulse_clock(2);
r26386r26387
20022058      // and calculate the vector location
20032059      // [0010 11xx xx tt SSSS]  shift 6 right, then *4 => shift 4 right
20042060      m_address = 0x0040 + ((IR >> 4) & 0x003c);
2061      // Takes some additional cycles
2062      pulse_clock(4);
20052063      break;
20062064   case 1:
20072065      m_value_copy = WP;                      // save the old WP
r26386r26387
21322190
21332191void tms99xx_device::alu_x()
21342192{
2135   if (VERBOSE>7) LOG("tms99xx: Substituting current command by %04x\n", m_current_value);
2193   if (TRACE_ALU) logerror("tms99xx: Substituting current command by %04x\n", m_current_value);
21362194   decode(m_current_value);
21372195   pulse_clock(2);
21382196}
r26386r26387
21522210   m_current_value = PC;
21532211   PC = m_address & m_prgaddr_mask & 0xfffe;
21542212   m_address = WP + 22;
2155   if (VERBOSE>7) LOG("tms99xx: Set new PC = %04x\n", PC);
2213   if (TRACE_ALU) logerror("tms99xx: Set new PC = %04x\n", PC);
21562214   pulse_clock(2);
21572215}
21582216
r26386r26387
21802238      break;
21812239   case 4:
21822240      PC = m_current_value & m_prgaddr_mask & 0xfffe;
2183      if (VERBOSE>5) LOG("tms9900: Context switch complete; WP=%04x, PC=%04x, ST=%04x\n", WP, PC, ST);
2241      if (TRACE_ALU) logerror("tms9900: Context switch complete; WP=%04x, PC=%04x, ST=%04x\n", WP, PC, ST);
21842242      break;
21852243   }
21862244   pulse_clock(2);
r26386r26387
22222280      }
22232281      m_cru_address = m_current_value;
22242282      m_value = value;
2225      if (VERBOSE>6) LOG("tms99xx: Load CRU address %04x (%d bits), value = %04x\n", m_cru_address, m_count, m_value);
2283      if (TRACE_CRU) logerror("tms99xx: Load CRU address %04x (%d bits), value = %04x\n", m_cru_address, m_count, m_value);
22262284   }
22272285   m_state++;
22282286   pulse_clock(2);
r26386r26387
22312289void tms99xx_device::alu_stcr()
22322290{
22332291   UINT16 value;
2234
2292   int n = 2;
22352293   // For STCR transfers with more than 8 bits, the first CRU bit is
22362294   // always put into the least significant bit of the destination word.
22372295   // If the address is odd (e.g. 0x1001), it is treated as 0x1000, that is,
r26386r26387
22432301   {
22442302   case 0: // After getting the destination operand and saving the address/value
22452303      m_address = WP + 24;
2304      n = 0;
22462305      break;
22472306   case 1: // After getting R12
22482307      m_cru_address = m_current_value;
r26386r26387
22532312      value = m_value & 0xffff;
22542313      if (m_count < 9)
22552314      {
2256         if (VERBOSE>6) LOG("tms99xx: Store CRU at %04x (%d bits) in %04x, result = %02x\n", m_cru_address, m_count, m_source_address, value);
2315         if (TRACE_CRU) logerror("tms99xx: Store CRU at %04x (%d bits) in %04x, result = %02x\n", m_cru_address, m_count, m_source_address, value);
22572316         set_status_parity((UINT8)(value & 0xff));
22582317         compare_and_set_lae(value<<8, 0);
22592318         if (m_source_even)
r26386r26387
22652324      }
22662325      else
22672326      {
2268         if (VERBOSE>6) LOG("tms99xx: Store CRU at %04x (%d bits) in %04x, result = %04x\n", m_cru_address, m_count, m_source_address, value);
2327         if (TRACE_CRU) logerror("tms99xx: Store CRU at %04x (%d bits) in %04x, result = %04x\n", m_cru_address, m_count, m_source_address, value);
22692328         m_current_value = value;
22702329         compare_and_set_lae(value, 0);
22712330         pulse_clock(2*(5 + (16-m_count)));
r26386r26387
22752334   }
22762335
22772336   m_state++;
2278   pulse_clock(2);
2337   pulse_clock(n);
22792338}
22802339
22812340void tms99xx_device::alu_sbz_sbo()
r26386r26387
23112370      break;
23122371   case 2:
23132372      set_status_bit(ST_EQ, m_value!=0);
2314      if (VERBOSE>7) LOG("tms99xx: ST = %04x\n", ST);
2373      if (TRACE_STATUS) logerror("tms99xx: ST = %04x\n", ST);
23152374      break;
23162375   }
23172376   m_state++;
r26386r26387
23672426         cond = ((ST & ST_OP)!=0);
23682427         break;
23692428      }
2370      pulse_clock(2);
23712429      if (!cond)
23722430      {
2373         if (VERBOSE>7) LOG("tms99xx: Jump condition false\n");
2431         if (TRACE_ALU) logerror("tms99xx: Jump condition false\n");
23742432         MPC+=1; // skip next ALU call
23752433      }
23762434      else
2377         if (VERBOSE>7) LOG("tms99xx: Jump condition true\n");
2435         if (TRACE_ALU) logerror("tms99xx: Jump condition true\n");
23782436   }
23792437   else
23802438   {
23812439      displacement = (IR & 0xff);
23822440      PC = (PC + (displacement<<1)) & m_prgaddr_mask & 0xfffe;
2383      pulse_clock(2);
23842441   }
23852442   m_state++;
2443   pulse_clock(2);
23862444}
23872445
23882446void tms99xx_device::alu_shift()
r26386r26387
24132471      }
24142472      else
24152473      {
2416         if (VERBOSE>8) LOG("tms99xx: Shift operation gets count from R0\n");
2474         if (TRACE_ALU) logerror("tms99xx: Shift operation gets count from R0\n");
24172475      }
24182476      break;
24192477   case 2:
r26386r26387
24552513      set_status_bit(ST_OV, overflow);
24562514      compare_and_set_lae(m_current_value, 0);
24572515      m_address = m_address_saved;        // Register address
2458      if (VERBOSE>7) LOG("tms99xx: ST = %04x (val=%04x)\n", ST, m_current_value);
2516      if (TRACE_STATUS) logerror("tms99xx: ST = %04x (val=%04x)\n", ST, m_current_value);
24592517      break;
24602518   }
24612519   m_state++;
r26386r26387
25072565void tms99xx_device::alu_limi()
25082566{
25092567   ST = (ST & 0xfff0) | (m_current_value & 0x000f);
2510   if (VERBOSE>7) LOG("tms99xx: ST = %04x\n", ST);
2568   if (TRACE_STATUS) logerror("tms99xx: ST = %04x\n", ST);
25112569   pulse_clock(2);
25122570}
25132571
r26386r26387
25202578
25212579void tms99xx_device::alu_external()
25222580{
2523   pulse_clock(10);
2524
25252581   // Call some possibly attached external device
25262582   // We pass the bit pattern of the address bus to the external function
25272583
r26386r26387
25352591      m_idle_state = true;
25362592
25372593   m_external_operation((IR >> 5) & 0x07, 1);
2594   pulse_clock(2);
25382595}
25392596
25402597void tms99xx_device::alu_rtwp()
r26386r26387
25432600   {
25442601   case 0:
25452602      m_address = WP + 30;        // R15
2603      pulse_clock(2);
25462604      break;
25472605   case 1:
25482606      ST = m_current_value;
r26386r26387
25542612      break;
25552613   case 3:
25562614      WP = m_current_value & m_prgaddr_mask & 0xfffe;
2615      pulse_clock(2);
25572616      break;
25582617   }
25592618   m_state++;
2560   pulse_clock(2);
25612619}
25622620
25632621
25642622void tms99xx_device::alu_int()
25652623{
2566   if (VERBOSE>7) LOG("tms99xx: INT state %d; irq_level %d\n", m_state, m_irq_level);
2624   if (TRACE_EMU) logerror("tms99xx: INT state %d; irq_level %d\n", m_state, m_irq_level);
25672625   switch (m_state)
25682626   {
25692627   case 0:
r26386r26387
25982656      break;
25992657   case 4:
26002658      m_address = (m_address_copy + 2) & 0xfffe & m_prgaddr_mask;
2601      if (VERBOSE>7) LOG("tms99xx: read from %04x\n", m_address);
2659      if (TRACE_ALU) logerror("tms99xx: read from %04x\n", m_address);
26022660      break;
26032661   case 5:
26042662      PC = m_current_value & m_prgaddr_mask & 0xfffe;
trunk/src/emu/cpu/tms9900/tms9900.h
r26386r26387
3030
3131static const char opname[][5] =
3232{   "ILL ", "A   ", "AB  ", "ABS ", "AI  ", "ANDI", "B   ", "BL  ", "BLWP", "C   ",
33   "CI  ", "CB  ", "CKOF", "CKON", "CLR ", "COC ", "CZC ", "DEC ", "DECT", "DIV ",
33   "CB  ", "CI  ", "CKOF", "CKON", "CLR ", "COC ", "CZC ", "DEC ", "DECT", "DIV ",
3434   "IDLE", "INC ", "INCT", "INV ", "JEQ ", "JGT ", "JH  ", "JHE ", "JL  ", "JLE ",
3535   "JLT ", "JMP ", "JNC ", "JNE ", "JNO ", "JOC ", "JOP ", "LDCR", "LI  ", "LIMI",
3636   "LREX", "LWPI", "MOV ", "MOVB", "MPY ", "NEG ", "ORI ", "RSET", "RTWP", "S   ",

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