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r26373 Saturday 23rd November, 2013 at 10:32:43 UTC by Jürgen Buchmüller
Trying to fix the ethernet hardware emulation. Should probably be done on the JK-FF level, just as the disk controller, because it is all too complex to understand.
[/branches/alto2/src/emu/cpu/alto2]a2ether.c a2ether.h alto2cpu.h

branches/alto2/src/emu/cpu/alto2/a2ether.c
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290290      return;
291291   }
292292
293   /*
294    * IDR (input data ready) conditions to wakeup the Ether task (AND):
293   /**
294    * IDR (input data ready) conditions to wakeup the Ether task
295    *  signal  meaining
296    * --------------------------------------
295297    *   IBUSY   input busy
296298    *   BNNE    buffer next nearly empty
297299    *   BNE     buffer nearly empty
298300    *   ETAC    ether task active
299301    *
300    * IDR' = (IBUSY & (BNNE & (BNE' & ETAC')')')'
302    ************************************************************
303    *            +----+
304    * BNE'  >----|NAND| (i1)  +----+
305    *            |    o-------|NAND| (i2)  +----+
306    * ETAC' >----|    |       |    o-------|NAND|
307    *            +----+   ·---|    |       |    o-----> IDR'
308    *                     |   +----+   ·---|    |
309    *            +---+    |            |   +----+
310    * BNNE' >----|INVo----·            |
311    *            +---+                 |
312    *                                  |
313    * IBUSY >--------------------------·
314    *
315    ************************************************************
301316    */
302   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr];
303   UINT8 etac = m_task == task_ether ? 0 : 1;
304   UINT8 idr = GET_ETH_IBUSY(st) & ~(~BNNE(a49) & ~(BNE(a49) & etac));
305   if (idr) {
317   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_wr + m_eth.fifo_rd];
318   UINT8 ETAC = m_task == task_ether ? 0 : 1;
319   UINT8 i1 = ~(BNE(a49) & ETAC);
320   UINT8 i2 = ~(~BNNE(a49) & i1);
321   UINT8 IDR = ~(GET_ETH_IBUSY(st) & i2);
322   if (0 == IDR) {
306323      m_task_wakeup |= 1 << task_ether;
307      LOG((LOG_ETH,0,"input data ready\n"));
324      LOG((LOG_ETH,0,"IDR (input data ready)\n"));
308325      return;
309326   }
310327
311   /*
312    * ODR (output data ready) conditions to wakeup the Ether task:
313    *   WLF    write latch filled(?)
328   /**
329    * ODR (output data ready) conditions to wakeup the Ether task
330    *  signal  meaining
331    * --------------------------------------
332    *   WLF    write latch full(?)
314333    *   BF     buffer (FIFO) full
315334    *   OEOT   output end of transmission
316335    *   OBUSY  output busy
336    ************************************************************
337    *            +----+
338    * WLF'  >----|NAND| (o1)    +----+
339    *            |    o---------|NAND|
340    * BF'   >----|    |         |    |
341    *            +----+  ·------|    o----> ODR'
342    *                    |      |    |
343    *                    |  ·---|    |
344    * OEOT' >------------·  |   +----+
345    *                       |
346    *                       |
347    * OBUSY >---------------·
317348    *
318    * ODR'   = (OBUSY & OEOT' & (BF' & WLF')')'
349    ************************************************************
319350    */
320   UINT8 odr = GET_ETH_OBUSY(st) & ~(~GET_ETH_OEOT(st) & ~(BF(a49) & ~GET_ETH_WLF(st)));
321   if (odr) {
351   UINT8 o1 = ~(~GET_ETH_WLF(st) & BF(a49));
352   UINT8 ODR = ~(GET_ETH_OBUSY(st) & ~GET_ETH_OEOT(st) & o1);
353   if (0 == ODR) {
322354      m_task_wakeup |= 1 << task_ether;
323      LOG((LOG_ETH,0,"output data ready\n"));
355      LOG((LOG_ETH,0,"ODR (output data ready)\n"));
324356      return;
325357   }
326358
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474506   m_eth.fifo[m_eth.fifo_wr] = data;
475507   m_eth.fifo_wr = (m_eth.fifo_wr + 1) % ALTO2_ETHER_FIFO_SIZE;
476508
477//   PUT_ETH_WLF(m_eth.status, 1);   // set WLF (write latch full)?
509   PUT_ETH_IT(m_eth.status, 1);   // set IT (input shift register full ...)?
478510
479   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr];
511   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_wr + m_eth.fifo_rd];
480512   if (0 == BF(a49))
481513      PUT_ETH_IDL(m_eth.status, 1);   // fifo is overrun: set input data late flip flop
482514
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521553   m_eth.tx_crc = f9401_7(m_eth.tx_crc, data);
522554   m_eth.fifo_rd = (m_eth.fifo_rd + 1) % ALTO2_ETHER_FIFO_SIZE;
523555
524   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr];
556   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_wr + m_eth.fifo_rd];
525557   if (0 == BE(a49)) {
526558      // the FIFO is empty now: clear the OBUSY and WLF flip flops
527559      PUT_ETH_OBUSY(m_eth.status, 0);
r26372r26373
583615 * @brief ethernet input look function
584616 *
585617 * Gates the contents of the FIFO to BUS[0-15], but does not
586 * increment the read pointer;
618 * increment the read pointer
587619 */
588620void alto2_cpu_device::f1_early_eilfct()
589621{
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608640 */
609641void alto2_cpu_device::f1_early_epfct()
610642{
611   UINT16 r = ~X_RDBITS(m_eth.status,16,10,15) & 0177777;
643   UINT16 r = 0177777;
644   UINT16 st = m_eth.status;
612645   m_eth.status = 0;
613646   m_eth.tx_count = 0;
614   eth_wakeup();
615647
648   X_WRBITS(r,16,10,10,~GET_ETH_IDL(st));      // BUS[10] = IDL (input data late)
649   X_WRBITS(r,16,11,11,~GET_ETH_COLL(st));      // BUS[11] = COLL (collision)
650   X_WRBITS(r,16,12,12,~GET_ETH_CRC(st));      // BUS[12] = CRC (CRC error)
651   X_WRBITS(r,16,13,13,~GET_ETH_ICMD(st));      // BUS[13] = ICMD (input command)
652   X_WRBITS(r,16,14,14,~GET_ETH_OCMD(st));      // BUS[13] = OCMD (output command)
653   X_WRBITS(r,16,15,15,~GET_ETH_IT(st));      // BUS[13] = IT (input ???)
654   m_bus &= r;
655
616656   LOG((LOG_ETH,3, "   ←EPFCT; BUS[8-15] = STATUS (%#o)\n", r));
617657   LOG((LOG_ETH,5, "      IDL'    : %u\n", GET_ETH_IDL(r)));
618658   LOG((LOG_ETH,5, "      COLL'   : %u\n", GET_ETH_COLL(r)));
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620660   LOG((LOG_ETH,5, "      ICMD'   : %u\n", GET_ETH_ICMD(r)));
621661   LOG((LOG_ETH,5, "      OCMD'   : %u\n", GET_ETH_OCMD(r)));
622662   LOG((LOG_ETH,5, "      IT'     : %u\n", GET_ETH_IT(r)));
623
624   m_bus &= r;
663   eth_wakeup();
625664}
626665
627666/**
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674713   PUT_ETH_OBUSY(m_eth.status, 1);         // set OBUSY (output busy)
675714   eth_wakeup();
676715   // if the FIFO is full, stop wakeup and kick off the timer
677   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr];
716   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_wr + m_eth.fifo_rd];
678717   if (0 == BF(a49)) {
679718      m_task_wakeup &= ~(1 << task_ether);
680719      m_eth.tx_timer->adjust(attotime::from_usec(5.44), 0);
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682721}
683722
684723/**
685 * @brief f2_eosfct late: ethernet output start function
724 * @brief ethernet output start function
686725 *
687726 * Sets the OBUSY flip flop in the interface, starting data
688727 * wakeups to fill the FIFO for output. When the FIFO is full,
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698737}
699738
700739/**
701 * @brief f2_erbfct late: ethernet reset branch function
740 * @brief ethernet reset branch function
702741 *
703742 * This command dispatch function merges the ICMD and OCMD flip flops
704743 * into NEXT[6-7]. These flip flops are the means of communication
r26372r26373
737776 * @brief ethernet branch function
738777 *
739778 * ORs a 1 into NEXT[6] if a collision is detected.
740 * ORs a 1 into NEXT[7] if an input data late is detected,
741 *     or a SIO with AC0[14-15] non-zero is issued,
742 *     or if the transmitter is gone
743 *     or if the receiver is gone.
779 * ORs a 1 into NEXT[7] if
780 *     an input data late is detected,
781 *     or a SIO with AC0[14-15] non-zero is issued (ICMD or OCMD),
782 *     or if the receiver is gone (IGONE)
783 *     or if the transmitter is gone (OGONE).
744784 */
745785void alto2_cpu_device::f2_late_ebfct()
746786{
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757797}
758798
759799/**
760 * @brief f2_ecbfct late: ethernet countdown branch function
800 * @brief ethernet countdown branch function
761801 *
762802 * The BE' (buffer empty) signal is output D0 of PROM a49
763803 * ORs a one into NEXT[7] if the FIFO is not empty.
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765805void alto2_cpu_device::f2_late_ecbfct()
766806{
767807   UINT16 r = 0;
768   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr];
808   UINT8 a49 = m_ether_a49[16 * m_eth.fifo_wr + m_eth.fifo_rd];
769809   X_WRBITS(r,10,7,7,~BE(a49));
770810   LOG((LOG_ETH,3, "   ECBFCT; NEXT[7] = FIFO %sempty (%#o | %#o)\n", r ? "not " : "is ", m_next2, r));
771811   m_next2 |= r;
772812}
773813
774814/**
775 * @brief f2_eisfct late: ethernet input start function
815 * @brief ethernet input start function
776816 *
777817 * Sets the IBUSY flip flop in the interface, causing it to hunt
778818 * for the beginning of a packet: silence on the Ether followed
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831871   m_eth.tx_timer->reset();
832872
833873   m_eth.rx_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(alto2_cpu_device::rx_breath_of_life),this));
834   if (m_eth.breath_of_life)
835      m_eth.rx_timer->adjust(attotime::from_seconds(m_eth.breath_of_life), 0);
836   else
837      m_eth.rx_timer->reset();
874   m_eth.rx_timer->reset();
838875}
839876
840877void alto2_cpu_device::exit_ether()
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864901   if (config)
865902      m_eth.breath_of_life = breath_of_life_sec[(config->read() >> 4) & 7];
866903   logerror("Ethernet breath_of_life %d sec\n", m_eth.breath_of_life);
904   if (m_eth.breath_of_life)
905      m_eth.rx_timer->adjust(attotime::from_seconds(m_eth.breath_of_life), 0);
867906}
branches/alto2/src/emu/cpu/alto2/alto2cpu.h
r26372r26373
4343};
4444
4545#ifndef   ALTO2_DEBUG
46#define   ALTO2_DEBUG             0         //!< define to 1 to enable logerror() output
46#define   ALTO2_DEBUG             1         //!< define to 1 to enable logerror() output
4747#endif
4848
4949#ifndef   ALTO2_CRAM_CONFIG
branches/alto2/src/emu/cpu/alto2/a2ether.h
r26372r26373
5454   UINT16 fifo_rd;                        //!< FIFO input pointer
5555   UINT16 fifo_wr;                        //!< FIFO output pointer
5656   UINT16 status;                        //!< status word
57   UINT32 rx_crc;                        //!< receiver CRC
58   UINT32 tx_crc;                        //!< transmitter CRC
57   UINT16 rx_crc;                        //!< receiver CRC
58   UINT16 tx_crc;                        //!< transmitter CRC
5959   UINT32 rx_count;                     //!< received words count
6060   UINT32 tx_count;                     //!< transmitted words count
6161   UINT16* rx_packet;                     //!< buffer to collect received words

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