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r26365 Friday 22nd November, 2013 at 18:21:14 UTC by Osso
Moved some functions into driver class for vegas.c (nw)

[src/mame/drivers]

vegas.c

trunk/src/mame/drivers/vegas.c

r26364	r26365
313	313
314	314	#define MAX_DYNAMIC_ADDRESSES   32
315	315
316		#define NOP_HANDLER         ((read32_space_func)-1)
	316	#define NOP_HANDLER         read32_delegate()
317	317
318	318
319	319
r26364	r26365
443	443	#define NINT_PCIE           (15)
444	444
445	445
446
447		struct dynamic_address
	446	struct legacy_dynamic_address
448	447	{
449	448	offs_t          start;
450	449	offs_t          end;
r26364	r26365
457	456	const char *    wrname;
458	457	};
459	458
	459	struct dynamic_address
	460	{
	461	offs_t          start;
	462	offs_t          end;
	463	read32_delegate   read;
	464	write32_delegate write;
	465	};
	466
460	467	class vegas_state : public driver_device
461	468	{
462	469	public:
463	470	vegas_state(const machine_config &mconfig, device_type type, const char *tag)
464	471	: driver_device(mconfig, type, tag),
465		m_timekeeper(*this, "timekeeper") ,
	472	m_maincpu(*this, "maincpu"),
	473	m_timekeeper(*this, "timekeeper") ,
	474	m_ide(*this, "ide"),
	475	m_ethernet(*this, "ethernet"),
466	476	m_rambase(*this, "rambase"),
467	477	m_nile_regs(*this, "nile_regs"),
468		m_rombase(*this, "rombase"),
469		m_maincpu(*this, "maincpu") { }
	478	m_rombase(*this, "rombase") { }
470	479
	480	required_device<cpu_device> m_maincpu;
471	481	required_device<m48t37_device> m_timekeeper;
	482	required_device<bus_master_ide_controller_device> m_ide;
	483	required_device<smc91c94_device> m_ethernet;
472	484	required_shared_ptr<UINT32> m_rambase;
473	485	required_shared_ptr<UINT32> m_nile_regs;
474	486	required_shared_ptr<UINT32> m_rombase;
r26364	r26365
489	501	device_t *m_voodoo;
490	502	UINT8 m_dcs_idma_cs;
491	503	int m_count;
	504	int m_legacy_dynamic_count;
492	505	int m_dynamic_count;
	506	legacy_dynamic_address m_legacy_dynamic[MAX_DYNAMIC_ADDRESSES];
493	507	dynamic_address m_dynamic[MAX_DYNAMIC_ADDRESSES];
494	508	DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
495	509	DECLARE_WRITE_LINE_MEMBER(vblank_assert);
r26364	r26365
511	525	void remap_dynamic_addresses();
512	526	void update_nile_irqs();
513	527	void update_sio_irqs();
514		inline void _add_dynamic_address(offs_t start, offs_t end, read32_space_func read, write32_space_func write, const char *rdname, const char *wrname);
515		inline void _add_dynamic_device_address(device_t *device, offs_t start, offs_t end, read32_device_func read, write32_device_func write, const char *rdname, const char *wrname);
	528	inline void _add_dynamic_address(offs_t start, offs_t end, read32_delegate read, write32_delegate write);
	529	inline void _add_legacy_dynamic_address(offs_t start, offs_t end, read32_space_func read, write32_space_func write, const char *rdname, const char *wrname);
	530	inline void _add_legacy_dynamic_device_address(device_t *device, offs_t start, offs_t end, read32_device_func read, write32_device_func write, const char *rdname, const char *wrname);
516	531
517	532	void init_common(int ioasic, int serialnum);
518		required_device<cpu_device> m_maincpu;
	533	DECLARE_WRITE32_MEMBER( cmos_unlock_w );
	534	DECLARE_WRITE32_MEMBER(timekeeper_w);
	535	DECLARE_READ32_MEMBER(timekeeper_r);
	536	DECLARE_READ32_MEMBER( pci_bridge_r );
	537	DECLARE_WRITE32_MEMBER( pci_bridge_w );
	538	DECLARE_READ32_MEMBER( pci_ide_r );
	539	DECLARE_WRITE32_MEMBER( pci_ide_w );
	540	DECLARE_READ32_MEMBER( pci_3dfx_r );
	541	DECLARE_WRITE32_MEMBER( pci_3dfx_w );
	542	DECLARE_READ32_MEMBER( nile_r );
	543	DECLARE_WRITE32_MEMBER( nile_w );
	544	DECLARE_READ32_MEMBER( sio_irq_clear_r );
	545	DECLARE_WRITE32_MEMBER( sio_irq_clear_w );
	546	DECLARE_READ32_MEMBER( sio_irq_enable_r );
	547	DECLARE_WRITE32_MEMBER( sio_irq_enable_w );
	548	DECLARE_READ32_MEMBER( sio_irq_cause_r );
	549	DECLARE_READ32_MEMBER( sio_irq_status_r );
	550	DECLARE_WRITE32_MEMBER( sio_led_w );
	551	DECLARE_READ32_MEMBER( sio_led_r );
	552	DECLARE_WRITE32_MEMBER( sio_w );
	553	DECLARE_READ32_MEMBER( sio_r );
	554	DECLARE_READ32_MEMBER( analog_port_r );
	555	DECLARE_WRITE32_MEMBER( analog_port_w );
	556	DECLARE_WRITE32_MEMBER( vegas_watchdog_w );
	557	DECLARE_WRITE32_MEMBER( asic_fifo_w );
	558	DECLARE_READ32_MEMBER( ide_main_r );
	559	DECLARE_WRITE32_MEMBER( ide_main_w );
	560	DECLARE_READ32_MEMBER( ide_alt_r );
	561	DECLARE_WRITE32_MEMBER( ide_alt_w );
	562	DECLARE_READ32_MEMBER( ide_bus_master32_r );
	563	DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
	564	DECLARE_READ32_MEMBER( ethernet_r );
	565	DECLARE_WRITE32_MEMBER( ethernet_w );
	566	DECLARE_WRITE32_MEMBER( dcs3_fifo_full_w );
519	567	};
520	568
521	569
r26364	r26365
607	655	*
608	656	*************************************/
609	657
610		static WRITE32_HANDLER( cmos_unlock_w )
	658	WRITE32_MEMBER( vegas_state::cmos_unlock_w )
611	659	{
612		vegas_state *state = space.machine().driver_data<vegas_state>();
613		state->m_cmos_unlocked = 1;
	660	m_cmos_unlocked = 1;
614	661	}
615	662
616	663
617		static WRITE32_HANDLER( timekeeper_w )
	664	WRITE32_MEMBER( vegas_state::timekeeper_w )
618	665	{
619		vegas_state *state = space.machine().driver_data<vegas_state>();
620		if (state->m_cmos_unlocked)
	666	if (m_cmos_unlocked)
621	667	{
622	668	if ((mem_mask & 0x000000ff) != 0)
623		state->m_timekeeper->write(space, offset * 4 + 0, data >> 0, 0xff);
	669	m_timekeeper->write(space, offset * 4 + 0, data >> 0, 0xff);
624	670	if ((mem_mask & 0x0000ff00) != 0)
625		state->m_timekeeper->write(space, offset * 4 + 1, data >> 8, 0xff);
	671	m_timekeeper->write(space, offset * 4 + 1, data >> 8, 0xff);
626	672	if ((mem_mask & 0x00ff0000) != 0)
627		state->m_timekeeper->write(space, offset * 4 + 2, data >> 16, 0xff);
	673	m_timekeeper->write(space, offset * 4 + 2, data >> 16, 0xff);
628	674	if ((mem_mask & 0xff000000) != 0)
629		state->m_timekeeper->write(space, offset * 4 + 3, data >> 24, 0xff);
	675	m_timekeeper->write(space, offset * 4 + 3, data >> 24, 0xff);
630	676	if (offset*4 >= 0x7ff0)
631	677	if (LOG_TIMEKEEPER) logerror("timekeeper_w(%04X & %08X) = %08X\n", offset*4, mem_mask, data);
632		state->m_cmos_unlocked = 0;
	678	m_cmos_unlocked = 0;
633	679	}
634	680	else
635		logerror("%08X:timekeeper_w(%04X,%08X & %08X) without CMOS unlocked\n", space.device().safe_pc(), offset, data, mem_mask);
	681	logerror("%08X:timekeeper_w(%04X,%08X & %08X) without CMOS unlocked\n", safe_pc(), offset, data, mem_mask);
636	682	}
637	683
638	684
639		static READ32_HANDLER( timekeeper_r )
	685	READ32_MEMBER( vegas_state::timekeeper_r )
640	686	{
641		vegas_state *state = space.machine().driver_data<vegas_state>();
642	687	UINT32 result = 0xffffffff;
643	688	if ((mem_mask & 0x000000ff) != 0)
644		result = (result & ~0x000000ff) | (state->m_timekeeper->read(space, offset * 4 + 0, 0xff) << 0);
	689	result = (result & ~0x000000ff) | (m_timekeeper->read(space, offset * 4 + 0, 0xff) << 0);
645	690	if ((mem_mask & 0x0000ff00) != 0)
646		result = (result & ~0x0000ff00) | (state->m_timekeeper->read(space, offset * 4 + 1, 0xff) << 8);
	691	result = (result & ~0x0000ff00) | (m_timekeeper->read(space, offset * 4 + 1, 0xff) << 8);
647	692	if ((mem_mask & 0x00ff0000) != 0)
648		result = (result & ~0x00ff0000) | (state->m_timekeeper->read(space, offset * 4 + 2, 0xff) << 16);
	693	result = (result & ~0x00ff0000) | (m_timekeeper->read(space, offset * 4 + 2, 0xff) << 16);
649	694	if ((mem_mask & 0xff000000) != 0)
650		result = (result & ~0xff000000) | (state->m_timekeeper->read(space, offset * 4 + 3, 0xff) << 24);
	695	result = (result & ~0xff000000) | (m_timekeeper->read(space, offset * 4 + 3, 0xff) << 24);
651	696	if (offset*4 >= 0x7ff0)
652	697	if (LOG_TIMEKEEPER) logerror("timekeeper_r(%04X & %08X) = %08X\n", offset*4, mem_mask, result);
653	698	return result;
r26364	r26365
661	706	*
662	707	*************************************/
663	708
664		static READ32_HANDLER( pci_bridge_r )
	709	READ32_MEMBER( vegas_state::pci_bridge_r )
665	710	{
666		vegas_state *state = space.machine().driver_data<vegas_state>();
667		UINT32 result = state->m_pci_bridge_regs[offset];
	711	UINT32 result = m_pci_bridge_regs[offset];
668	712
669	713	switch (offset)
670	714	{
r26364	r26365
678	722	}
679	723
680	724	if (LOG_PCI)
681		logerror("%06X:PCI bridge read: reg %d = %08X\n", space.device().safe_pc(), offset, result);
	725	logerror("%06X:PCI bridge read: reg %d = %08X\n", safe_pc(), offset, result);
682	726	return result;
683	727	}
684	728
685	729
686		static WRITE32_HANDLER( pci_bridge_w )
	730	WRITE32_MEMBER( vegas_state::pci_bridge_w )
687	731	{
688		vegas_state *state = space.machine().driver_data<vegas_state>();
689		state->m_pci_bridge_regs[offset] = data;
	732	m_pci_bridge_regs[offset] = data;
690	733	if (LOG_PCI)
691		logerror("%06X:PCI bridge write: reg %d = %08X\n", space.device().safe_pc(), offset, data);
	734	logerror("%06X:PCI bridge write: reg %d = %08X\n", safe_pc(), offset, data);
692	735	}
693	736
694	737
r26364	r26365
699	742	*
700	743	*************************************/
701	744
702		static READ32_HANDLER( pci_ide_r )
	745	READ32_MEMBER( vegas_state::pci_ide_r )
703	746	{
704		vegas_state *state = space.machine().driver_data<vegas_state>();
705		UINT32 result = state->m_pci_ide_regs[offset];
	747	UINT32 result = m_pci_ide_regs[offset];
706	748
707	749	switch (offset)
708	750	{
r26364	r26365
712	754
713	755	case 0x14:      /* interrupt pending */
714	756	result &= 0xffffff00;
715		if (state->m_ide_irq_state)
	757	if (m_ide_irq_state)
716	758	result |= 4;
717	759	break;
718	760	}
719	761
720	762	if (LOG_PCI)
721		logerror("%06X:PCI IDE read: reg %d = %08X\n", space.device().safe_pc(), offset, result);
	763	logerror("%06X:PCI IDE read: reg %d = %08X\n", safe_pc(), offset, result);
722	764	return result;
723	765	}
724	766
725	767
726		static WRITE32_HANDLER( pci_ide_w )
	768	WRITE32_MEMBER( vegas_state::pci_ide_w )
727	769	{
728		vegas_state *state = space.machine().driver_data<vegas_state>();
729		state->m_pci_ide_regs[offset] = data;
	770	m_pci_ide_regs[offset] = data;
730	771
731	772	switch (offset)
732	773	{
733	774	case 0x04:      /* address register */
734		state->m_pci_ide_regs[offset] &= 0xfffffff0;
735		state->remap_dynamic_addresses();
	775	m_pci_ide_regs[offset] &= 0xfffffff0;
	776	remap_dynamic_addresses();
736	777	break;
737	778
738	779	case 0x05:      /* address register */
739		state->m_pci_ide_regs[offset] &= 0xfffffffc;
740		state->remap_dynamic_addresses();
	780	m_pci_ide_regs[offset] &= 0xfffffffc;
	781	remap_dynamic_addresses();
741	782	break;
742	783
743	784	case 0x08:      /* address register */
744		state->m_pci_ide_regs[offset] &= 0xfffffff0;
745		state->remap_dynamic_addresses();
	785	m_pci_ide_regs[offset] &= 0xfffffff0;
	786	remap_dynamic_addresses();
746	787	break;
747	788
748	789	case 0x14:      /* interrupt pending */
749	790	if (data & 4)
750		state->ide_interrupt(0);
	791	ide_interrupt(0);
751	792	break;
752	793	}
753	794	if (LOG_PCI)
754		logerror("%06X:PCI IDE write: reg %d = %08X\n", space.device().safe_pc(), offset, data);
	795	logerror("%06X:PCI IDE write: reg %d = %08X\n", safe_pc(), offset, data);
755	796	}
756	797
757	798
r26364	r26365
762	803	*
763	804	*************************************/
764	805
765		static READ32_HANDLER( pci_3dfx_r )
	806	READ32_MEMBER( vegas_state::pci_3dfx_r )
766	807	{
767		vegas_state *state = space.machine().driver_data<vegas_state>();
768		int voodoo_type = voodoo_get_type(state->m_voodoo);
769		UINT32 result = state->m_pci_3dfx_regs[offset];
	808	int voodoo_type = voodoo_get_type(m_voodoo);
	809	UINT32 result = m_pci_3dfx_regs[offset];
770	810
771	811	switch (offset)
772	812	{
r26364	r26365
791	831	}
792	832
793	833	if (LOG_PCI)
794		logerror("%06X:PCI 3dfx read: reg %d = %08X\n", space.device().safe_pc(), offset, result);
	834	logerror("%06X:PCI 3dfx read: reg %d = %08X\n", safe_pc(), offset, result);
795	835	return result;
796	836	}
797	837
798	838
799		static WRITE32_HANDLER( pci_3dfx_w )
	839	WRITE32_MEMBER( vegas_state::pci_3dfx_w )
800	840	{
801		vegas_state *state = space.machine().driver_data<vegas_state>();
802		int voodoo_type = voodoo_get_type(state->m_voodoo);
	841	int voodoo_type = voodoo_get_type(m_voodoo);
803	842
804		state->m_pci_3dfx_regs[offset] = data;
	843	m_pci_3dfx_regs[offset] = data;
805	844
806	845	switch (offset)
807	846	{
808	847	case 0x04:      /* address register */
809	848	if (voodoo_type == TYPE_VOODOO_2)
810		state->m_pci_3dfx_regs[offset] &= 0xff000000;
	849	m_pci_3dfx_regs[offset] &= 0xff000000;
811	850	else
812		state->m_pci_3dfx_regs[offset] &= 0xfe000000;
813		state->remap_dynamic_addresses();
	851	m_pci_3dfx_regs[offset] &= 0xfe000000;
	852	remap_dynamic_addresses();
814	853	break;
815	854
816	855	case 0x05:      /* address register */
817	856	if (voodoo_type >= TYPE_VOODOO_BANSHEE)
818	857	{
819		state->m_pci_3dfx_regs[offset] &= 0xfe000000;
820		state->remap_dynamic_addresses();
	858	m_pci_3dfx_regs[offset] &= 0xfe000000;
	859	remap_dynamic_addresses();
821	860	}
822	861	break;
823	862
824	863	case 0x06:      /* I/O register */
825	864	if (voodoo_type >= TYPE_VOODOO_BANSHEE)
826	865	{
827		state->m_pci_3dfx_regs[offset] &= 0xffffff00;
828		state->remap_dynamic_addresses();
	866	m_pci_3dfx_regs[offset] &= 0xffffff00;
	867	remap_dynamic_addresses();
829	868	}
830	869	break;
831	870
832	871	case 0x0c:      /* romBaseAddr register */
833	872	if (voodoo_type >= TYPE_VOODOO_BANSHEE)
834	873	{
835		state->m_pci_3dfx_regs[offset] &= 0xffff0000;
836		state->remap_dynamic_addresses();
	874	m_pci_3dfx_regs[offset] &= 0xffff0000;
	875	remap_dynamic_addresses();
837	876	}
838	877	break;
839	878
840	879	case 0x10:      /* initEnable register */
841		voodoo_set_init_enable(state->m_voodoo, data);
	880	voodoo_set_init_enable(m_voodoo, data);
842	881	break;
843	882
844	883	}
845	884	if (LOG_PCI)
846		logerror("%06X:PCI 3dfx write: reg %d = %08X\n", space.device().safe_pc(), offset, data);
	885	logerror("%06X:PCI 3dfx write: reg %d = %08X\n", safe_pc(), offset, data);
847	886	}
848	887
849	888
r26364	r26365
950	989	*
951	990	*************************************/
952	991
953		static READ32_HANDLER( nile_r )
	992	READ32_MEMBER( vegas_state::nile_r )
954	993	{
955		vegas_state *state = space.machine().driver_data<vegas_state>();
956		UINT32 result = state->m_nile_regs[offset];
	994	UINT32 result = m_nile_regs[offset];
957	995	int logit = 1, which;
958	996
959	997	switch (offset)
960	998	{
961	999	case NREG_CPUSTAT+0:    /* CPU status */
962	1000	case NREG_CPUSTAT+1:    /* CPU status */
963		if (LOG_NILE) logerror("%08X:NILE READ: CPU status(%03X) = %08X\n", space.device().safe_pc(), offset*4, result);
	1001	if (LOG_NILE) logerror("%08X:NILE READ: CPU status(%03X) = %08X\n", safe_pc(), offset*4, result);
964	1002	logit = 0;
965	1003	break;
966	1004
967	1005	case NREG_INTCTRL+0:    /* Interrupt control */
968	1006	case NREG_INTCTRL+1:    /* Interrupt control */
969		if (LOG_NILE) logerror("%08X:NILE READ: interrupt control(%03X) = %08X\n", space.device().safe_pc(), offset*4, result);
	1007	if (LOG_NILE) logerror("%08X:NILE READ: interrupt control(%03X) = %08X\n", safe_pc(), offset*4, result);
970	1008	logit = 0;
971	1009	break;
972	1010
973	1011	case NREG_INTSTAT0+0:   /* Interrupt status 0 */
974	1012	case NREG_INTSTAT0+1:   /* Interrupt status 0 */
975		if (LOG_NILE) logerror("%08X:NILE READ: interrupt status 0(%03X) = %08X\n", space.device().safe_pc(), offset*4, result);
	1013	if (LOG_NILE) logerror("%08X:NILE READ: interrupt status 0(%03X) = %08X\n", safe_pc(), offset*4, result);
976	1014	logit = 0;
977	1015	break;
978	1016
979	1017	case NREG_INTSTAT1+0:   /* Interrupt status 1 */
980	1018	case NREG_INTSTAT1+1:   /* Interrupt status 1 */
981		if (LOG_NILE) logerror("%08X:NILE READ: interrupt status 1/enable(%03X) = %08X\n", space.device().safe_pc(), offset*4, result);
	1019	if (LOG_NILE) logerror("%08X:NILE READ: interrupt status 1/enable(%03X) = %08X\n", safe_pc(), offset*4, result);
982	1020	logit = 0;
983	1021	break;
984	1022
985	1023	case NREG_INTCLR+0:     /* Interrupt clear */
986	1024	case NREG_INTCLR+1:     /* Interrupt clear */
987		if (LOG_NILE) logerror("%08X:NILE READ: interrupt clear(%03X) = %08X\n", space.device().safe_pc(), offset*4, result);
	1025	if (LOG_NILE) logerror("%08X:NILE READ: interrupt clear(%03X) = %08X\n", safe_pc(), offset*4, result);
988	1026	logit = 0;
989	1027	break;
990	1028
991	1029	case NREG_INTPPES+0:    /* PCI Interrupt control */
992	1030	case NREG_INTPPES+1:    /* PCI Interrupt control */
993		if (LOG_NILE) logerror("%08X:NILE READ: PCI interrupt control(%03X) = %08X\n", space.device().safe_pc(), offset*4, result);
	1031	if (LOG_NILE) logerror("%08X:NILE READ: PCI interrupt control(%03X) = %08X\n", safe_pc(), offset*4, result);
994	1032	logit = 0;
995	1033	break;
996	1034
r26364	r26365
1010	1048	case NREG_T2CNTR:       /* general purpose timer control (counter) */
1011	1049	case NREG_T3CNTR:       /* watchdog timer control (counter) */
1012	1050	which = (offset - NREG_T0CTRL) / 4;
1013		if (state->m_nile_regs[offset - 1] & 1)
	1051	if (m_nile_regs[offset - 1] & 1)
1014	1052	{
1015		if (state->m_nile_regs[offset] & 2)
	1053	if (m_nile_regs[offset] & 2)
1016	1054	logerror("Unexpected value: timer %d is prescaled\n", which);
1017		result = state->m_nile_regs[offset + 1] = state->m_timer[which]->remaining().as_double() * (double)SYSTEM_CLOCK;
	1055	result = m_nile_regs[offset + 1] = m_timer[which]->remaining().as_double() * (double)SYSTEM_CLOCK;
1018	1056	}
1019	1057
1020		if (LOG_TIMERS) logerror("%08X:NILE READ: timer %d counter(%03X) = %08X\n", space.device().safe_pc(), which, offset*4, result);
	1058	if (LOG_TIMERS) logerror("%08X:NILE READ: timer %d counter(%03X) = %08X\n", safe_pc(), which, offset*4, result);
1021	1059	logit = 0;
1022	1060	break;
1023	1061
1024	1062	case NREG_UARTIIR:          /* serial port interrupt ID */
1025		if (state->m_nile_regs[NREG_UARTIER] & 2)
	1063	if (m_nile_regs[NREG_UARTIER] & 2)
1026	1064	result = 0x02;          /* transmitter buffer IRQ pending */
1027	1065	else
1028	1066	result = 0x01;          /* no IRQ pending */
r26364	r26365
1058	1096	}
1059	1097
1060	1098	if (LOG_NILE && logit)
1061		logerror("%06X:nile read from offset %03X = %08X\n", space.device().safe_pc(), offset*4, result);
	1099	logerror("%06X:nile read from offset %03X = %08X\n", safe_pc(), offset*4, result);
1062	1100	return result;
1063	1101	}
1064	1102
1065	1103
1066		static WRITE32_HANDLER( nile_w )
	1104	WRITE32_MEMBER( vegas_state::nile_w )
1067	1105	{
1068		vegas_state *state = space.machine().driver_data<vegas_state>();
1069		UINT32 olddata = state->m_nile_regs[offset];
	1106	UINT32 olddata = m_nile_regs[offset];
1070	1107	int logit = 1, which;
1071	1108
1072		COMBINE_DATA(&state->m_nile_regs[offset]);
	1109	COMBINE_DATA(&m_nile_regs[offset]);
1073	1110
1074	1111	switch (offset)
1075	1112	{
1076	1113	case NREG_CPUSTAT+0:    /* CPU status */
1077	1114	case NREG_CPUSTAT+1:    /* CPU status */
1078		if (LOG_NILE) logerror("%08X:NILE WRITE: CPU status(%03X) = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	1115	if (LOG_NILE) logerror("%08X:NILE WRITE: CPU status(%03X) = %08X & %08X\n", safe_pc(), offset*4, data, mem_mask);
1079	1116	logit = 0;
1080	1117	break;
1081	1118
1082	1119	case NREG_INTCTRL+0:    /* Interrupt control */
1083	1120	case NREG_INTCTRL+1:    /* Interrupt control */
1084		if (LOG_NILE) logerror("%08X:NILE WRITE: interrupt control(%03X) = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	1121	if (LOG_NILE) logerror("%08X:NILE WRITE: interrupt control(%03X) = %08X & %08X\n", safe_pc(), offset*4, data, mem_mask);
1085	1122	logit = 0;
1086		state->update_nile_irqs();
	1123	update_nile_irqs();
1087	1124	break;
1088	1125
1089	1126	case NREG_INTSTAT0+0:   /* Interrupt status 0 */
1090	1127	case NREG_INTSTAT0+1:   /* Interrupt status 0 */
1091		if (LOG_NILE) logerror("%08X:NILE WRITE: interrupt status 0(%03X) = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	1128	if (LOG_NILE) logerror("%08X:NILE WRITE: interrupt status 0(%03X) = %08X & %08X\n", safe_pc(), offset*4, data, mem_mask);
1092	1129	logit = 0;
1093		state->update_nile_irqs();
	1130	update_nile_irqs();
1094	1131	break;
1095	1132
1096	1133	case NREG_INTSTAT1+0:   /* Interrupt status 1 */
1097	1134	case NREG_INTSTAT1+1:   /* Interrupt status 1 */
1098		if (LOG_NILE) logerror("%08X:NILE WRITE: interrupt status 1/enable(%03X) = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	1135	if (LOG_NILE) logerror("%08X:NILE WRITE: interrupt status 1/enable(%03X) = %08X & %08X\n", safe_pc(), offset*4, data, mem_mask);
1099	1136	logit = 0;
1100		state->update_nile_irqs();
	1137	update_nile_irqs();
1101	1138	break;
1102	1139
1103	1140	case NREG_INTCLR+0:     /* Interrupt clear */
1104	1141	case NREG_INTCLR+1:     /* Interrupt clear */
1105		if (LOG_NILE) logerror("%08X:NILE WRITE: interrupt clear(%03X) = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	1142	if (LOG_NILE) logerror("%08X:NILE WRITE: interrupt clear(%03X) = %08X & %08X\n", safe_pc(), offset*4, data, mem_mask);
1106	1143	logit = 0;
1107		state->m_nile_irq_state &= ~(state->m_nile_regs[offset] & ~0xf00);
1108		state->update_nile_irqs();
	1144	m_nile_irq_state &= ~(m_nile_regs[offset] & ~0xf00);
	1145	update_nile_irqs();
1109	1146	break;
1110	1147
1111	1148	case NREG_INTPPES+0:    /* PCI Interrupt control */
1112	1149	case NREG_INTPPES+1:    /* PCI Interrupt control */
1113		if (LOG_NILE) logerror("%08X:NILE WRITE: PCI interrupt control(%03X) = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	1150	if (LOG_NILE) logerror("%08X:NILE WRITE: PCI interrupt control(%03X) = %08X & %08X\n", safe_pc(), offset*4, data, mem_mask);
1114	1151	logit = 0;
1115	1152	break;
1116	1153
r26364	r26365
1125	1162	break;
1126	1163
1127	1164	case NREG_PCIINIT1+0:   /* PCI master */
1128		if (((olddata & 0xe) == 0xa) != ((state->m_nile_regs[offset] & 0xe) == 0xa))
1129		state->remap_dynamic_addresses();
	1165	if (((olddata & 0xe) == 0xa) != ((m_nile_regs[offset] & 0xe) == 0xa))
	1166	remap_dynamic_addresses();
1130	1167	logit = 0;
1131	1168	break;
1132	1169
r26364	r26365
1135	1172	case NREG_T2CTRL+1:     /* general purpose timer control (control bits) */
1136	1173	case NREG_T3CTRL+1:     /* watchdog timer control (control bits) */
1137	1174	which = (offset - NREG_T0CTRL) / 4;
1138		if (LOG_NILE) logerror("%08X:NILE WRITE: timer %d control(%03X) = %08X & %08X\n", space.device().safe_pc(), which, offset*4, data, mem_mask);
	1175	if (LOG_NILE) logerror("%08X:NILE WRITE: timer %d control(%03X) = %08X & %08X\n", safe_pc(), which, offset*4, data, mem_mask);
1139	1176	logit = 0;
1140	1177
1141	1178	/* timer just enabled? */
1142		if (!(olddata & 1) && (state->m_nile_regs[offset] & 1))
	1179	if (!(olddata & 1) && (m_nile_regs[offset] & 1))
1143	1180	{
1144		UINT32 scale = state->m_nile_regs[offset + 1];
1145		if (state->m_nile_regs[offset] & 2)
	1181	UINT32 scale = m_nile_regs[offset + 1];
	1182	if (m_nile_regs[offset] & 2)
1146	1183	logerror("Unexpected value: timer %d is prescaled\n", which);
1147	1184	if (scale != 0)
1148		state->m_timer[which]->adjust(TIMER_PERIOD * scale, which);
1149		if (LOG_TIMERS) logerror("Starting timer %d at a rate of %d Hz\n", which, (int)ATTOSECONDS_TO_HZ((TIMER_PERIOD * (state->m_nile_regs[offset + 1] + 1)).attoseconds));
	1185	m_timer[which]->adjust(TIMER_PERIOD * scale, which);
	1186	if (LOG_TIMERS) logerror("Starting timer %d at a rate of %d Hz\n", which, (int)ATTOSECONDS_TO_HZ((TIMER_PERIOD * (m_nile_regs[offset + 1] + 1)).attoseconds));
1150	1187	}
1151	1188
1152	1189	/* timer disabled? */
1153		else if ((olddata & 1) && !(state->m_nile_regs[offset] & 1))
	1190	else if ((olddata & 1) && !(m_nile_regs[offset] & 1))
1154	1191	{
1155		if (state->m_nile_regs[offset] & 2)
	1192	if (m_nile_regs[offset] & 2)
1156	1193	logerror("Unexpected value: timer %d is prescaled\n", which);
1157		state->m_nile_regs[offset + 1] = state->m_timer[which]->remaining().as_double() * SYSTEM_CLOCK;
1158		state->m_timer[which]->adjust(attotime::never, which);
	1194	m_nile_regs[offset + 1] = m_timer[which]->remaining().as_double() * SYSTEM_CLOCK;
	1195	m_timer[which]->adjust(attotime::never, which);
1159	1196	}
1160	1197	break;
1161	1198
r26364	r26365
1164	1201	case NREG_T2CNTR:       /* general purpose timer control (counter) */
1165	1202	case NREG_T3CNTR:       /* watchdog timer control (counter) */
1166	1203	which = (offset - NREG_T0CTRL) / 4;
1167		if (LOG_TIMERS) logerror("%08X:NILE WRITE: timer %d counter(%03X) = %08X & %08X\n", space.device().safe_pc(), which, offset*4, data, mem_mask);
	1204	if (LOG_TIMERS) logerror("%08X:NILE WRITE: timer %d counter(%03X) = %08X & %08X\n", safe_pc(), which, offset*4, data, mem_mask);
1168	1205	logit = 0;
1169	1206
1170		if (state->m_nile_regs[offset - 1] & 1)
	1207	if (m_nile_regs[offset - 1] & 1)
1171	1208	{
1172		if (state->m_nile_regs[offset - 1] & 2)
	1209	if (m_nile_regs[offset - 1] & 2)
1173	1210	logerror("Unexpected value: timer %d is prescaled\n", which);
1174		state->m_timer[which]->adjust(TIMER_PERIOD * state->m_nile_regs[offset], which);
	1211	m_timer[which]->adjust(TIMER_PERIOD * m_nile_regs[offset], which);
1175	1212	}
1176	1213	break;
1177	1214
r26364	r26365
1180	1217	logit = 0;
1181	1218	break;
1182	1219	case NREG_UARTIER:      /* serial interrupt enable */
1183		state->update_nile_irqs();
	1220	update_nile_irqs();
1184	1221	break;
1185	1222
1186	1223	case NREG_VID:
r26364	r26365
1214	1251	case NREG_DCS8:
1215	1252	case NREG_PCIW0:
1216	1253	case NREG_PCIW1:
1217		state->remap_dynamic_addresses();
	1254	remap_dynamic_addresses();
1218	1255	break;
1219	1256	}
1220	1257
1221	1258	if (LOG_NILE && logit)
1222		logerror("%06X:nile write to offset %03X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	1259	logerror("%06X:nile write to offset %03X = %08X & %08X\n", safe_pc(), offset*4, data, mem_mask);
1223	1260	}
1224	1261
1225	1262
r26364	r26365
1297	1334	}
1298	1335
1299	1336
1300		static READ32_HANDLER( sio_irq_clear_r )
	1337	READ32_MEMBER( vegas_state::sio_irq_clear_r )
1301	1338	{
1302		vegas_state *state = space.machine().driver_data<vegas_state>();
1303		return state->m_sio_irq_clear;
	1339	return m_sio_irq_clear;
1304	1340	}
1305	1341
1306	1342
1307		static WRITE32_HANDLER( sio_irq_clear_w )
	1343	WRITE32_MEMBER( vegas_state::sio_irq_clear_w )
1308	1344	{
1309		vegas_state *state = space.machine().driver_data<vegas_state>();
1310	1345	if (ACCESSING_BITS_0_7)
1311	1346	{
1312		state->m_sio_irq_clear = data;
	1347	m_sio_irq_clear = data;
1313	1348
1314	1349	/* bit 0x01 seems to be used to reset the IOASIC */
1315	1350	if (!(data & 0x01))
r26364	r26365
1321	1356	/* they toggle bit 0x08 low to reset the VBLANK */
1322	1357	if (!(data & 0x08))
1323	1358	{
1324		state->m_sio_irq_state &= ~0x20;
1325		state->update_sio_irqs();
	1359	m_sio_irq_state &= ~0x20;
	1360	update_sio_irqs();
1326	1361	}
1327	1362	}
1328	1363	}
1329	1364
1330	1365
1331		static READ32_HANDLER( sio_irq_enable_r )
	1366	READ32_MEMBER( vegas_state::sio_irq_enable_r )
1332	1367	{
1333		vegas_state *state = space.machine().driver_data<vegas_state>();
1334		return state->m_sio_irq_enable;
	1368	return m_sio_irq_enable;
1335	1369	}
1336	1370
1337	1371
1338		static WRITE32_HANDLER( sio_irq_enable_w )
	1372	WRITE32_MEMBER( vegas_state::sio_irq_enable_w )
1339	1373	{
1340		vegas_state *state = space.machine().driver_data<vegas_state>();
1341	1374	if (ACCESSING_BITS_0_7)
1342	1375	{
1343		state->m_sio_irq_enable = data;
1344		state->update_sio_irqs();
	1376	m_sio_irq_enable = data;
	1377	update_sio_irqs();
1345	1378	}
1346	1379	}
1347	1380
1348	1381
1349		static READ32_HANDLER( sio_irq_cause_r )
	1382	READ32_MEMBER( vegas_state::sio_irq_cause_r )
1350	1383	{
1351		vegas_state *state = space.machine().driver_data<vegas_state>();
1352		return state->m_sio_irq_state & state->m_sio_irq_enable;
	1384	return m_sio_irq_state & m_sio_irq_enable;
1353	1385	}
1354	1386
1355	1387
1356		static READ32_HANDLER( sio_irq_status_r )
	1388	READ32_MEMBER( vegas_state::sio_irq_status_r )
1357	1389	{
1358		vegas_state *state = space.machine().driver_data<vegas_state>();
1359		return state->m_sio_irq_state;
	1390	return m_sio_irq_state;
1360	1391	}
1361	1392
1362	1393
1363		static WRITE32_HANDLER( sio_led_w )
	1394	WRITE32_MEMBER( vegas_state::sio_led_w )
1364	1395	{
1365		vegas_state *state = space.machine().driver_data<vegas_state>();
1366	1396	if (ACCESSING_BITS_0_7)
1367		state->m_sio_led_state = data;
	1397	m_sio_led_state = data;
1368	1398	}
1369	1399
1370	1400
1371		static READ32_HANDLER( sio_led_r )
	1401	READ32_MEMBER( vegas_state::sio_led_r )
1372	1402	{
1373		vegas_state *state = space.machine().driver_data<vegas_state>();
1374		return state->m_sio_led_state;
	1403	return m_sio_led_state;
1375	1404	}
1376	1405
1377	1406
r26364	r26365
1382	1411	*
1383	1412	*************************************/
1384	1413
1385		static WRITE32_HANDLER( sio_w )
	1414	WRITE32_MEMBER( vegas_state::sio_w )
1386	1415	{
1387		vegas_state *state = space.machine().driver_data<vegas_state>();
1388	1416	if (ACCESSING_BITS_0_7) offset += 0;
1389	1417	if (ACCESSING_BITS_8_15) offset += 1;
1390	1418	if (ACCESSING_BITS_16_23) offset += 2;
1391	1419	if (ACCESSING_BITS_24_31) offset += 3;
1392	1420	if (LOG_SIO && offset != 0)
1393		logerror("%08X:sio write to offset %X = %02X\n", space.device().safe_pc(), offset, data >> (offset*8));
	1421	logerror("%08X:sio write to offset %X = %02X\n", safe_pc(), offset, data >> (offset*8));
1394	1422	if (offset < 4)
1395		state->m_sio_data[offset] = data >> (offset*8);
	1423	m_sio_data[offset] = data >> (offset*8);
1396	1424	if (offset == 1)
1397		state->m_sio_data[2] = (state->m_sio_data[2] & ~0x02) | ((state->m_sio_data[1] & 0x01) << 1) | (state->m_sio_data[1] & 0x01);
	1425	m_sio_data[2] = (m_sio_data[2] & ~0x02) | ((m_sio_data[1] & 0x01) << 1) | (m_sio_data[1] & 0x01);
1398	1426	}
1399	1427
1400	1428
1401		static READ32_HANDLER( sio_r )
	1429	READ32_MEMBER( vegas_state::sio_r )
1402	1430	{
1403		vegas_state *state = space.machine().driver_data<vegas_state>();
1404	1431	UINT32 result = 0;
1405	1432	if (ACCESSING_BITS_0_7) offset += 0;
1406	1433	if (ACCESSING_BITS_8_15) offset += 1;
1407	1434	if (ACCESSING_BITS_16_23) offset += 2;
1408	1435	if (ACCESSING_BITS_24_31) offset += 3;
1409	1436	if (offset < 4)
1410		result = state->m_sio_data[0] | (state->m_sio_data[1] << 8) | (state->m_sio_data[2] << 16) | (state->m_sio_data[3] << 24);
	1437	result = m_sio_data[0] | (m_sio_data[1] << 8) | (m_sio_data[2] << 16) | (m_sio_data[3] << 24);
1411	1438	if (LOG_SIO && offset != 2)
1412		logerror("%08X:sio read from offset %X = %02X\n", space.device().safe_pc(), offset, result >> (offset*8));
	1439	logerror("%08X:sio read from offset %X = %02X\n", safe_pc(), offset, result >> (offset*8));
1413	1440	return result;
1414	1441	}
1415	1442
r26364	r26365
1421	1448	*
1422	1449	*************************************/
1423	1450
1424		static READ32_HANDLER( analog_port_r )
	1451	READ32_MEMBER( vegas_state::analog_port_r )
1425	1452	{
1426		vegas_state *state = space.machine().driver_data<vegas_state>();
1427		return state->m_pending_analog_read;
	1453	return m_pending_analog_read;
1428	1454	}
1429	1455
1430	1456
1431		static WRITE32_HANDLER( analog_port_w )
	1457	WRITE32_MEMBER( vegas_state::analog_port_w )
1432	1458	{
1433		vegas_state *state = space.machine().driver_data<vegas_state>();
1434	1459	static const char *const portnames[] = { "AN0", "AN1", "AN2", "AN3", "AN4", "AN5", "AN6", "AN7" };
1435	1460
1436	1461	if (data < 8 || data > 15)
1437		logerror("%08X:Unexpected analog port select = %08X\n", space.device().safe_pc(), data);
1438		state->m_pending_analog_read = state->ioport(portnames[data & 7])->read_safe(0);
	1462	logerror("%08X:Unexpected analog port select = %08X\n", safe_pc(), data);
	1463	m_pending_analog_read = ioport(portnames[data & 7])->read_safe(0);
1439	1464	}
1440	1465
1441	1466
r26364	r26365
1446	1471	*
1447	1472	*************************************/
1448	1473
1449		static WRITE32_HANDLER( vegas_watchdog_w )
	1474	WRITE32_MEMBER( vegas_state::vegas_watchdog_w )
1450	1475	{
1451	1476	space.device().execute().eat_cycles(100);
1452	1477	}
1453	1478
1454	1479
1455		static WRITE32_HANDLER( asic_fifo_w )
	1480	WRITE32_MEMBER( vegas_state::asic_fifo_w )
1456	1481	{
1457	1482	midway_ioasic_fifo_w(space.machine(), data);
1458	1483	}
1459	1484
1460	1485
1461		static READ32_DEVICE_HANDLER( ide_main_r )
	1486	READ32_MEMBER( vegas_state::ide_main_r )
1462	1487	{
1463		bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1464		return ide->read_cs0(space, offset, mem_mask);
	1488	return m_ide->read_cs0(space, offset, mem_mask);
1465	1489	}
1466	1490
1467	1491
1468		static WRITE32_DEVICE_HANDLER( ide_main_w )
	1492	WRITE32_MEMBER( vegas_state::ide_main_w )
1469	1493	{
1470		bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1471		ide->write_cs0(space, offset, data, mem_mask);
	1494	m_ide->write_cs0(space, offset, data, mem_mask);
1472	1495	}
1473	1496
1474	1497
1475		static READ32_DEVICE_HANDLER( ide_alt_r )
	1498	READ32_MEMBER( vegas_state::ide_alt_r )
1476	1499	{
1477		bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1478		return ide->read_cs1(space, offset + 1, mem_mask);
	1500	return m_ide->read_cs1(space, offset + 1, mem_mask);
1479	1501	}
1480	1502
1481	1503
1482		static WRITE32_DEVICE_HANDLER( ide_alt_w )
	1504	WRITE32_MEMBER( vegas_state::ide_alt_w )
1483	1505	{
1484		bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1485		ide->write_cs1(space, offset + 1, data, mem_mask);
	1506	m_ide->write_cs1(space, offset + 1, data, mem_mask);
1486	1507	}
1487	1508
1488	1509
1489		static READ32_DEVICE_HANDLER( ide_bus_master32_r )
	1510	READ32_MEMBER( vegas_state::ide_bus_master32_r )
1490	1511	{
1491		bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1492		return ide->bmdma_r(space, offset, mem_mask);
	1512	return m_ide->bmdma_r(space, offset, mem_mask);
1493	1513	}
1494	1514
1495	1515
1496		static WRITE32_DEVICE_HANDLER( ide_bus_master32_w )
	1516	WRITE32_MEMBER( vegas_state::ide_bus_master32_w )
1497	1517	{
1498		bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1499		ide->bmdma_w(space, offset, data, mem_mask);
	1518	m_ide->bmdma_w(space, offset, data, mem_mask);
1500	1519	}
1501	1520
1502	1521
1503		static READ32_DEVICE_HANDLER( ethernet_r )
	1522	READ32_MEMBER( vegas_state::ethernet_r )
1504	1523	{
1505		smc91c94_device *ethernet = space.machine().device<smc91c94_device>("ethernet");
1506
1507	1524	UINT32 result = 0;
1508	1525	if (ACCESSING_BITS_0_15)
1509		result |= ethernet->read(space, offset * 2 + 0, mem_mask);
	1526	result |= m_ethernet->read(space, offset * 2 + 0, mem_mask);
1510	1527	if (ACCESSING_BITS_16_31)
1511		result |= ethernet->read(space, offset * 2 + 1, mem_mask >> 16) << 16;
	1528	result |= m_ethernet->read(space, offset * 2 + 1, mem_mask >> 16) << 16;
1512	1529	return result;
1513	1530	}
1514	1531
1515	1532
1516		static WRITE32_DEVICE_HANDLER( ethernet_w )
	1533	WRITE32_MEMBER( vegas_state::ethernet_w )
1517	1534	{
1518		smc91c94_device *ethernet = space.machine().device<smc91c94_device>("ethernet");
1519
1520	1535	if (ACCESSING_BITS_0_15)
1521		ethernet->write(space, offset * 2 + 0, data, mem_mask);
	1536	m_ethernet->write(space, offset * 2 + 0, data, mem_mask);
1522	1537	if (ACCESSING_BITS_16_31)
1523		ethernet->write(space, offset * 2 + 1, data >> 16, mem_mask >> 16);
	1538	m_ethernet->write(space, offset * 2 + 1, data >> 16, mem_mask >> 16);
1524	1539	}
1525	1540
1526	1541
1527		static WRITE32_HANDLER( dcs3_fifo_full_w )
	1542	WRITE32_MEMBER( vegas_state::dcs3_fifo_full_w )
1528	1543	{
1529	1544	midway_ioasic_fifo_full_w(space.machine(), data);
1530	1545	}
r26364	r26365
1537	1552	*
1538	1553	*************************************/
1539	1554
1540		#define add_dynamic_address(s,e,r,w)         _add_dynamic_address(s,e,r,w,#r,#w)
1541		#define add_dynamic_device_address(d,s,e,r,w)    _add_dynamic_device_address(d,s,e,r,w,#r,#w)
	1555	#define add_dynamic_address(s,e,r,w)         _add_dynamic_address(s,e,r,w)
1542	1556
1543		inline void vegas_state::_add_dynamic_address(offs_t start, offs_t end, read32_space_func read, write32_space_func write, const char *rdname, const char *wrname)
	1557	#define add_legacy_dynamic_address(s,e,r,w)         _add_legacy_dynamic_address(s,e,r,w,#r,#w)
	1558	#define add_legacy_dynamic_device_address(d,s,e,r,w)    _add_legacy_dynamic_device_address(d,s,e,r,w,#r,#w)
	1559
	1560	inline void vegas_state::_add_dynamic_address(offs_t start, offs_t end, read32_delegate read, write32_delegate write)
1544	1561	{
1545	1562	dynamic_address *dynamic = m_dynamic;
1546	1563	dynamic[m_dynamic_count].start = start;
1547	1564	dynamic[m_dynamic_count].end = end;
1548		dynamic[m_dynamic_count].mread = read;
1549		dynamic[m_dynamic_count].mwrite = write;
1550		dynamic[m_dynamic_count].dread = NULL;
1551		dynamic[m_dynamic_count].dwrite = NULL;
1552		dynamic[m_dynamic_count].device = NULL;
1553		dynamic[m_dynamic_count].rdname = rdname;
1554		dynamic[m_dynamic_count].wrname = wrname;
	1565	dynamic[m_dynamic_count].read = read;
	1566	dynamic[m_dynamic_count].write = write;
1555	1567	m_dynamic_count++;
1556	1568	}
1557	1569
1558		inline void vegas_state::_add_dynamic_device_address(device_t *device, offs_t start, offs_t end, read32_device_func read, write32_device_func write, const char *rdname, const char *wrname)
	1570	inline void vegas_state::_add_legacy_dynamic_address(offs_t start, offs_t end, read32_space_func read, write32_space_func write, const char *rdname, const char *wrname)
1559	1571	{
1560		dynamic_address *dynamic = m_dynamic;
1561		dynamic[m_dynamic_count].start = start;
1562		dynamic[m_dynamic_count].end = end;
1563		dynamic[m_dynamic_count].mread = NULL;
1564		dynamic[m_dynamic_count].mwrite = NULL;
1565		dynamic[m_dynamic_count].dread = read;
1566		dynamic[m_dynamic_count].dwrite = write;
1567		dynamic[m_dynamic_count].device = device;
1568		dynamic[m_dynamic_count].rdname = rdname;
1569		dynamic[m_dynamic_count].wrname = wrname;
1570		m_dynamic_count++;
	1572	legacy_dynamic_address *l_dynamic = m_legacy_dynamic;
	1573	l_dynamic[m_legacy_dynamic_count].start = start;
	1574	l_dynamic[m_legacy_dynamic_count].end = end;
	1575	l_dynamic[m_legacy_dynamic_count].mread = read;
	1576	l_dynamic[m_legacy_dynamic_count].mwrite = write;
	1577	l_dynamic[m_legacy_dynamic_count].dread = NULL;
	1578	l_dynamic[m_legacy_dynamic_count].dwrite = NULL;
	1579	l_dynamic[m_legacy_dynamic_count].device = NULL;
	1580	l_dynamic[m_legacy_dynamic_count].rdname = rdname;
	1581	l_dynamic[m_legacy_dynamic_count].wrname = wrname;
	1582	m_legacy_dynamic_count++;
1571	1583	}
1572	1584
	1585	inline void vegas_state::_add_legacy_dynamic_device_address(device_t *device, offs_t start, offs_t end, read32_device_func read, write32_device_func write, const char *rdname, const char *wrname)
	1586	{
	1587	legacy_dynamic_address *l_dynamic = m_legacy_dynamic;
	1588	l_dynamic[m_legacy_dynamic_count].start = start;
	1589	l_dynamic[m_legacy_dynamic_count].end = end;
	1590	l_dynamic[m_legacy_dynamic_count].mread = NULL;
	1591	l_dynamic[m_legacy_dynamic_count].mwrite = NULL;
	1592	l_dynamic[m_legacy_dynamic_count].dread = read;
	1593	l_dynamic[m_legacy_dynamic_count].dwrite = write;
	1594	l_dynamic[m_legacy_dynamic_count].device = device;
	1595	l_dynamic[m_legacy_dynamic_count].rdname = rdname;
	1596	l_dynamic[m_legacy_dynamic_count].wrname = wrname;
	1597	m_legacy_dynamic_count++;
	1598	}
1573	1599
	1600
	1601
1574	1602	void vegas_state::remap_dynamic_addresses()
1575	1603	{
1576	1604	dynamic_address *dynamic = m_dynamic;
1577		device_t *ethernet = machine().device("ethernet");
1578		device_t *ide = machine().device("ide");
	1605	legacy_dynamic_address *l_dynamic = m_legacy_dynamic;
1579	1606	int voodoo_type = voodoo_get_type(m_voodoo);
1580	1607	offs_t base;
1581		int addr;
	1608	int addr, l_addr;
1582	1609
1583	1610	/* unmap everything we know about */
1584	1611	for (addr = 0; addr < m_dynamic_count; addr++)
1585	1612	m_maincpu->space(AS_PROGRAM).unmap_readwrite(dynamic[addr].start, dynamic[addr].end);
	1613
	1614	for (l_addr = 0; l_addr < m_legacy_dynamic_count; l_addr++)
	1615	m_maincpu->space(AS_PROGRAM).unmap_readwrite(l_dynamic[l_addr].start, l_dynamic[l_addr].end);
1586	1616
1587	1617	/* the build the list of stuff */
1588	1618	m_dynamic_count = 0;
	1619	m_legacy_dynamic_count = 0;
1589	1620
1590	1621	/* DCS2 */
1591	1622	base = m_nile_regs[NREG_DCS2] & 0x1fffff00;
1592	1623	if (base >= m_rambase.bytes())
1593	1624	{
1594		add_dynamic_address(base + 0x0000, base + 0x0003, sio_irq_clear_r, sio_irq_clear_w);
1595		add_dynamic_address(base + 0x1000, base + 0x1003, sio_irq_enable_r, sio_irq_enable_w);
1596		add_dynamic_address(base + 0x2000, base + 0x2003, sio_irq_cause_r, NULL);
1597		add_dynamic_address(base + 0x3000, base + 0x3003, sio_irq_status_r, NULL);
1598		add_dynamic_address(base + 0x4000, base + 0x4003, sio_led_r, sio_led_w);
1599		add_dynamic_address(base + 0x5000, base + 0x5007, NOP_HANDLER, NULL);
1600		add_dynamic_address(base + 0x6000, base + 0x6003, NULL, cmos_unlock_w);
1601		add_dynamic_address(base + 0x7000, base + 0x7003, NULL, vegas_watchdog_w);
	1625	add_dynamic_address(base + 0x0000, base + 0x0003, read32_delegate(FUNC(vegas_state::sio_irq_clear_r), this), write32_delegate(FUNC(vegas_state::sio_irq_clear_w), this));
	1626	add_dynamic_address(base + 0x1000, base + 0x1003, read32_delegate(FUNC(vegas_state::sio_irq_enable_r), this), write32_delegate(FUNC(vegas_state::sio_irq_enable_w), this));
	1627	add_dynamic_address(base + 0x2000, base + 0x2003, read32_delegate(FUNC(vegas_state::sio_irq_cause_r), this), write32_delegate());
	1628	add_dynamic_address(base + 0x3000, base + 0x3003, read32_delegate(FUNC(vegas_state::sio_irq_status_r), this), write32_delegate());
	1629	add_dynamic_address(base + 0x4000, base + 0x4003, read32_delegate(FUNC(vegas_state::sio_led_r), this), write32_delegate(FUNC(vegas_state::sio_led_w), this));
	1630	add_dynamic_address(base + 0x5000, base + 0x5007, NOP_HANDLER, write32_delegate());
	1631	add_dynamic_address(base + 0x6000, base + 0x6003, read32_delegate(), write32_delegate(FUNC(vegas_state::cmos_unlock_w), this));
	1632	add_dynamic_address(base + 0x7000, base + 0x7003, read32_delegate(), write32_delegate(FUNC(vegas_state::vegas_watchdog_w), this));
1602	1633	}
1603	1634
1604	1635	/* DCS3 */
1605	1636	base = m_nile_regs[NREG_DCS3] & 0x1fffff00;
1606	1637	if (base >= m_rambase.bytes())
1607		add_dynamic_address(base + 0x0000, base + 0x0003, analog_port_r, analog_port_w);
	1638	add_dynamic_address(base + 0x0000, base + 0x0003, read32_delegate(FUNC(vegas_state::analog_port_r), this), write32_delegate(FUNC(vegas_state::analog_port_w), this));
1608	1639
1609	1640	/* DCS4 */
1610	1641	base = m_nile_regs[NREG_DCS4] & 0x1fffff00;
1611	1642	if (base >= m_rambase.bytes())
1612		add_dynamic_address(base + 0x0000, base + 0x7fff, timekeeper_r, timekeeper_w);
	1643	add_dynamic_address(base + 0x0000, base + 0x7fff, read32_delegate(FUNC(vegas_state::timekeeper_r), this), write32_delegate(FUNC(vegas_state::timekeeper_w), this));
1613	1644
1614	1645	/* DCS5 */
1615	1646	base = m_nile_regs[NREG_DCS5] & 0x1fffff00;
1616	1647	if (base >= m_rambase.bytes())
1617		add_dynamic_address(base + 0x0000, base + 0x0003, sio_r, sio_w);
	1648	add_dynamic_address(base + 0x0000, base + 0x0003, read32_delegate(FUNC(vegas_state::sio_r), this), write32_delegate(FUNC(vegas_state::sio_w), this));
1618	1649
1619	1650	/* DCS6 */
1620	1651	base = m_nile_regs[NREG_DCS6] & 0x1fffff00;
1621	1652	if (base >= m_rambase.bytes())
1622	1653	{
1623		add_dynamic_address(base + 0x0000, base + 0x003f, midway_ioasic_packed_r, midway_ioasic_packed_w);
1624		add_dynamic_address(base + 0x1000, base + 0x1003, NULL, asic_fifo_w);
	1654	add_legacy_dynamic_address(base + 0x0000, base + 0x003f, midway_ioasic_packed_r, midway_ioasic_packed_w);
	1655	add_dynamic_address(base + 0x1000, base + 0x1003, read32_delegate(), write32_delegate(FUNC(vegas_state::asic_fifo_w), this));
1625	1656	if (m_dcs_idma_cs != 0)
1626		add_dynamic_address(base + 0x3000, base + 0x3003, NULL, dcs3_fifo_full_w);
	1657	add_dynamic_address(base + 0x3000, base + 0x3003, read32_delegate(), write32_delegate(FUNC(vegas_state::dcs3_fifo_full_w), this));
1627	1658	if (m_dcs_idma_cs == 6)
1628	1659	{
1629		add_dynamic_address(base + 0x5000, base + 0x5003, NULL, dsio_idma_addr_w);
1630		add_dynamic_address(base + 0x7000, base + 0x7003, dsio_idma_data_r, dsio_idma_data_w);
	1660	add_legacy_dynamic_address(base + 0x5000, base + 0x5003, NULL, dsio_idma_addr_w);
	1661	add_legacy_dynamic_address(base + 0x7000, base + 0x7003, dsio_idma_data_r, dsio_idma_data_w);
1631	1662	}
1632	1663	}
1633	1664
r26364	r26365
1635	1666	base = m_nile_regs[NREG_DCS7] & 0x1fffff00;
1636	1667	if (base >= m_rambase.bytes())
1637	1668	{
1638		add_dynamic_device_address(ethernet, base + 0x1000, base + 0x100f, ethernet_r, ethernet_w);
	1669	add_dynamic_address(base + 0x1000, base + 0x100f, read32_delegate(FUNC(vegas_state::ethernet_r), this), write32_delegate(FUNC(vegas_state::ethernet_w), this));
1639	1670	if (m_dcs_idma_cs == 7)
1640	1671	{
1641		add_dynamic_address(base + 0x5000, base + 0x5003, NULL, dsio_idma_addr_w);
1642		add_dynamic_address(base + 0x7000, base + 0x7003, dsio_idma_data_r, dsio_idma_data_w);
	1672	add_legacy_dynamic_address(base + 0x5000, base + 0x5003, NULL, dsio_idma_addr_w);
	1673	add_legacy_dynamic_address(base + 0x7000, base + 0x7003, dsio_idma_data_r, dsio_idma_data_w);
1643	1674	}
1644	1675	}
1645	1676
r26364	r26365
1649	1680	base = m_nile_regs[NREG_PCIW1] & 0x1fffff00;
1650	1681	if (base >= m_rambase.bytes())
1651	1682	{
1652		add_dynamic_address(base + (1 << (21 + 4)) + 0x0000, base + (1 << (21 + 4)) + 0x00ff, pci_3dfx_r, pci_3dfx_w);
1653		add_dynamic_address(base + (1 << (21 + 5)) + 0x0000, base + (1 << (21 + 5)) + 0x00ff, pci_ide_r, pci_ide_w);
	1683	add_dynamic_address(base + (1 << (21 + 4)) + 0x0000, base + (1 << (21 + 4)) + 0x00ff, read32_delegate(FUNC(vegas_state::pci_3dfx_r), this),  write32_delegate(FUNC(vegas_state::pci_3dfx_w), this));
	1684	add_dynamic_address(base + (1 << (21 + 5)) + 0x0000, base + (1 << (21 + 5)) + 0x00ff, read32_delegate(FUNC(vegas_state::pci_ide_r), this),  write32_delegate(FUNC(vegas_state::pci_ide_w), this));
1654	1685	}
1655	1686	}
1656	1687
r26364	r26365
1660	1691	/* IDE controller */
1661	1692	base = m_pci_ide_regs[0x04] & 0xfffffff0;
1662	1693	if (base >= m_rambase.bytes() && base < 0x20000000)
1663		add_dynamic_device_address(ide, base + 0x0000, base + 0x000f, ide_main_r, ide_main_w);
	1694	add_dynamic_address(base + 0x0000, base + 0x000f, read32_delegate(FUNC(vegas_state::ide_main_r), this),  write32_delegate(FUNC(vegas_state::ide_main_w), this));
1664	1695
1665	1696	base = m_pci_ide_regs[0x05] & 0xfffffffc;
1666	1697	if (base >= m_rambase.bytes() && base < 0x20000000)
1667		add_dynamic_device_address(ide, base + 0x0000, base + 0x0003, ide_alt_r, ide_alt_w);
	1698	add_dynamic_address(base + 0x0000, base + 0x0003, read32_delegate(FUNC(vegas_state::ide_alt_r), this), write32_delegate(FUNC(vegas_state::ide_alt_w), this));
1668	1699
1669	1700	base = m_pci_ide_regs[0x08] & 0xfffffff0;
1670	1701	if (base >= m_rambase.bytes() && base < 0x20000000)
1671		add_dynamic_device_address(ide, base + 0x0000, base + 0x0007, ide_bus_master32_r, ide_bus_master32_w);
	1702	add_dynamic_address(base + 0x0000, base + 0x0007, read32_delegate(FUNC(vegas_state::ide_bus_master32_r), this), write32_delegate(FUNC(vegas_state::ide_bus_master32_w), this));
1672	1703
1673	1704	/* 3dfx card */
1674	1705	base = m_pci_3dfx_regs[0x04] & 0xfffffff0;
1675	1706	if (base >= m_rambase.bytes() && base < 0x20000000)
1676	1707	{
1677	1708	if (voodoo_type == TYPE_VOODOO_2)
1678		add_dynamic_device_address(m_voodoo, base + 0x000000, base + 0xffffff, voodoo_r, voodoo_w);
	1709	add_legacy_dynamic_device_address(m_voodoo, base + 0x000000, base + 0xffffff, voodoo_r, voodoo_w);
1679	1710	else
1680		add_dynamic_device_address(m_voodoo, base + 0x000000, base + 0x1ffffff, banshee_r, banshee_w);
	1711	add_legacy_dynamic_device_address(m_voodoo, base + 0x000000, base + 0x1ffffff, banshee_r, banshee_w);
1681	1712	}
1682	1713
1683	1714	if (voodoo_type >= TYPE_VOODOO_BANSHEE)
1684	1715	{
1685	1716	base = m_pci_3dfx_regs[0x05] & 0xfffffff0;
1686	1717	if (base >= m_rambase.bytes() && base < 0x20000000)
1687		add_dynamic_device_address(m_voodoo, base + 0x0000000, base + 0x1ffffff, banshee_fb_r, banshee_fb_w);
	1718	add_legacy_dynamic_device_address(m_voodoo, base + 0x0000000, base + 0x1ffffff, banshee_fb_r, banshee_fb_w);
1688	1719
1689	1720	base = m_pci_3dfx_regs[0x06] & 0xfffffff0;
1690	1721	if (base >= m_rambase.bytes() && base < 0x20000000)
1691		add_dynamic_device_address(m_voodoo, base + 0x0000000, base + 0x00000ff, banshee_io_r, banshee_io_w);
	1722	add_legacy_dynamic_device_address(m_voodoo, base + 0x0000000, base + 0x00000ff, banshee_io_r, banshee_io_w);
1692	1723
1693	1724	base = m_pci_3dfx_regs[0x0c] & 0xffff0000;
1694	1725	if (base >= m_rambase.bytes() && base < 0x20000000)
1695		add_dynamic_device_address(m_voodoo, base + 0x0000000, base + 0x000ffff, banshee_rom_r, NULL);
	1726	add_legacy_dynamic_device_address(m_voodoo, base + 0x0000000, base + 0x000ffff, banshee_rom_r, NULL);
1696	1727	}
1697	1728	}
1698	1729
r26364	r26365
1701	1732	address_space &space = m_maincpu->space(AS_PROGRAM);
1702	1733	for (addr = 0; addr < m_dynamic_count; addr++)
1703	1734	{
1704		if (LOG_DYNAMIC) logerror("  installing: %08X-%08X %s,%s\n", dynamic[addr].start, dynamic[addr].end, dynamic[addr].rdname, dynamic[addr].wrname);
	1735	if (LOG_DYNAMIC) logerror("  installing: %08X-%08X \n", dynamic[addr].start, dynamic[addr].end);
1705	1736
1706		if (dynamic[addr].mread == NOP_HANDLER)
	1737	if (dynamic[addr].read == NOP_HANDLER)
1707	1738	space.nop_read(dynamic[addr].start, dynamic[addr].end);
1708		else if (dynamic[addr].mread != NULL)
1709		space.install_legacy_read_handler(dynamic[addr].start, dynamic[addr].end, 0, 0, dynamic[addr].mread, dynamic[addr].rdname);
1710		if (dynamic[addr].mwrite != NULL)
1711		space.install_legacy_write_handler(dynamic[addr].start, dynamic[addr].end, 0, 0, dynamic[addr].mwrite, dynamic[addr].wrname);
	1739	else if (!dynamic[addr].read.isnull())
	1740	space.install_read_handler(dynamic[addr].start, dynamic[addr].end, 0, 0, dynamic[addr].read);
	1741	if (!dynamic[addr].write.isnull())
	1742	space.install_write_handler(dynamic[addr].start, dynamic[addr].end, 0, 0, dynamic[addr].write);
	1743	}
	1744
	1745	for (l_addr = 0; l_addr < m_legacy_dynamic_count; l_addr++)
	1746	{
	1747	if (LOG_DYNAMIC) logerror("  installing: %08X-%08X %s,%s\n", l_dynamic[l_addr].start, l_dynamic[l_addr].end, l_dynamic[l_addr].rdname, l_dynamic[l_addr].wrname);
1712	1748
1713		if (dynamic[addr].dread != NULL || dynamic[addr].dwrite != NULL)
1714		space.install_legacy_readwrite_handler(*dynamic[addr].device, dynamic[addr].start, dynamic[addr].end, 0, 0, dynamic[addr].dread, dynamic[addr].rdname, dynamic[addr].dwrite, dynamic[addr].wrname);
	1749	if (l_dynamic[l_addr].mread != NULL)
	1750	space.install_legacy_read_handler(l_dynamic[l_addr].start, l_dynamic[l_addr].end, 0, 0, l_dynamic[l_addr].mread, l_dynamic[l_addr].rdname);
	1751	if (l_dynamic[l_addr].mwrite != NULL)
	1752	space.install_legacy_write_handler(l_dynamic[l_addr].start, l_dynamic[l_addr].end, 0, 0, l_dynamic[l_addr].mwrite, l_dynamic[l_addr].wrname);
	1753
	1754	if (l_dynamic[l_addr].dread != NULL || l_dynamic[l_addr].dwrite != NULL)
	1755	space.install_legacy_readwrite_handler(*l_dynamic[l_addr].device, l_dynamic[l_addr].start, l_dynamic[l_addr].end, 0, 0, l_dynamic[l_addr].dread, l_dynamic[l_addr].rdname, l_dynamic[l_addr].dwrite, l_dynamic[l_addr].wrname);
1715	1756	}
1716	1757
1717	1758	if (LOG_DYNAMIC)
r26364	r26365
1732	1773	static ADDRESS_MAP_START( vegas_map_8mb, AS_PROGRAM, 32, vegas_state )
1733	1774	ADDRESS_MAP_UNMAP_HIGH
1734	1775	AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase")
1735		AM_RANGE(0x1fa00000, 0x1fa00fff) AM_READWRITE_LEGACY(nile_r, nile_w) AM_SHARE("nile_regs")
	1776	AM_RANGE(0x1fa00000, 0x1fa00fff) AM_READWRITE(nile_r, nile_w) AM_SHARE("nile_regs")
1736	1777	AM_RANGE(0x1fc00000, 0x1fc7ffff) AM_ROM AM_REGION("user1", 0) AM_SHARE("rombase")
1737	1778	ADDRESS_MAP_END
1738	1779
r26364	r26365
1740	1781	static ADDRESS_MAP_START( vegas_map_32mb, AS_PROGRAM, 32, vegas_state )
1741	1782	ADDRESS_MAP_UNMAP_HIGH
1742	1783	AM_RANGE(0x00000000, 0x01ffffff) AM_RAM AM_SHARE("rambase")
1743		AM_RANGE(0x1fa00000, 0x1fa00fff) AM_READWRITE_LEGACY(nile_r, nile_w) AM_SHARE("nile_regs")
	1784	AM_RANGE(0x1fa00000, 0x1fa00fff) AM_READWRITE(nile_r, nile_w) AM_SHARE("nile_regs")
1744	1785	AM_RANGE(0x1fc00000, 0x1fc7ffff) AM_ROM AM_REGION("user1", 0) AM_SHARE("rombase")
1745	1786	ADDRESS_MAP_END
1746	1787

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