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r26292 Tuesday 19th November, 2013 at 23:00:25 UTC by Jürgen Buchmüller
Rename the bus source, f1 and f2 functions to include early or late. Remove inlined handling of shifte lsh1/rsh1/lcy8
[/branches/alto2/src/emu/cpu/alto2]a2curt.c a2dht.c a2disk.c a2disp.c a2dvt.c a2dwt.c a2emu.c a2ether.c a2ksec.c a2kwd.c a2mrt.c a2ram.c alto2cpu.c alto2cpu.h
[/branches/alto2/src/mess/drivers]alto2.c

branches/alto2/src/emu/cpu/alto2/a2ether.c
r26291r26292
436436 * Gates the contents of the FIFO to BUS[0-15], and increments
437437 * the read pointer at the end of the cycle.
438438 */
439void alto2_cpu_device::bs_eidfct_0()
439void alto2_cpu_device::bs_early_eidfct()
440440{
441441   UINT16 r = m_eth.fifo[m_eth.fifo_rd];
442442
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451451/**
452452 * @brief f1_eth_block early: block the Ether task
453453 */
454void alto2_cpu_device::f1_eth_block_0()
454void alto2_cpu_device::f1_early_eth_block()
455455{
456456   LOG((LOG_ETH,2,"   BLOCK %s\n", task_name(m_task)));
457457   m_task_wakeup &= ~(1 << task_ether);
r26291r26292
463463 * Gates the contents of the FIFO to BUS[0-15], but does not
464464 * increment the read pointer;
465465 */
466void alto2_cpu_device::f1_eilfct_0()
466void alto2_cpu_device::f1_early_eilfct()
467467{
468468   UINT16 r = m_eth.fifo[m_eth.fifo_rd];
469469   LOG((LOG_ETH,3, "   ←EILFCT; %06o at FIFO[%02o]\n", r, m_eth.fifo_rd));
r26291r26292
483483 * ;(LOW TRUE) to Bus [10:15], reset interface.
484484 *
485485 */
486void alto2_cpu_device::f1_epfct_0()
486void alto2_cpu_device::f1_early_epfct()
487487{
488488   UINT16 r = ~A2_GET16(m_eth.status,16,10,15) & 0177777;
489489
r26291r26292
502502 * This function must be issued in the instruction after a TASK.
503503 * The resulting wakeup is cleared when the Ether task next runs.
504504 */
505void alto2_cpu_device::f1_ewfct_1()
505void alto2_cpu_device::f1_late_ewfct()
506506{
507507   /*
508508    * Set a flag in the CPU to handle the next task switch
r26291r26292
517517 * Loads the FIFO from BUS[0-15], then increments the write
518518 * pointer at the end of the cycle.
519519 */
520void alto2_cpu_device::f2_eodfct_1()
520void alto2_cpu_device::f2_late_eodfct()
521521{
522522   LOG((LOG_ETH,3, "   EODFCT←; push %06o into FIFO[%02o]\n", m_bus, m_eth.fifo_wr));
523523
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543543 * or EEFCT has been issued, the interface will wait for silence
544544 * on the Ether and begin transmitting.
545545 */
546void alto2_cpu_device::f2_eosfct_1()
546void alto2_cpu_device::f2_late_eosfct()
547547{
548548   LOG((LOG_ETH,3, "   EOSFCT\n"));
549549   PUT_ETH_WLF(m_eth.status, 0);
r26291r26292
561561 * causing the Ethernet task to wakeup, dispatch on them and then
562562 * reset them with EPFCT.
563563 */
564void alto2_cpu_device::f2_erbfct_1()
564void alto2_cpu_device::f2_late_erbfct()
565565{
566566   UINT16 r = 0;
567567   A2_PUT16(r,10,6,6,GET_ETH_ICMD(m_eth.status));
r26291r26292
578578 * has been transferred to the FIFO. EEFCT disables further data
579579 * wakeups.
580580 */
581void alto2_cpu_device::f2_eefct_1()
581void alto2_cpu_device::f2_late_eefct()
582582{
583583   /* start transmitting the packet */
584584   PUT_ETH_OBUSY(m_eth.status, 1);
r26291r26292
599599 * with AC0[14-15] non-zero is issued, or if the transmitter or
600600 * receiver is gone. ORs a 1 into NEXT[6] if a collision is detected.
601601 */
602void alto2_cpu_device::f2_ebfct_1()
602void alto2_cpu_device::f2_late_ebfct()
603603{
604604   UINT16 r = 0;
605605   A2_PUT16(r,10,6,6, GET_ETH_COLL(m_eth.status));
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617617 *
618618 * ORs a one into NEXT[7] if the FIFO is not empty.
619619 */
620void alto2_cpu_device::f2_ecbfct_1()
620void alto2_cpu_device::f2_late_ecbfct()
621621{
622622   UINT16 r = 0;
623623   /* TODO: the BE' (buffer empty) signal is output D0 of PROM a49 */
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634634 * by a transition. When the interface has collected two words,
635635 * it will begin generating data wakeups to the microcode.
636636 */
637void alto2_cpu_device::f2_eisfct_1()
637void alto2_cpu_device::f2_late_eisfct()
638638{
639639   LOG((LOG_ETH,3, "   EISFCT\n"));
640640   PUT_ETH_IBUSY(m_eth.status, 0);
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658658   // intialize all ethernet variables
659659   memset(&m_eth, 0, sizeof(m_eth));
660660
661   set_bs(task, bs_ether_eidfct,   &alto2_cpu_device::bs_eidfct_0,   0);
661   set_bs(task, bs_ether_eidfct,   &alto2_cpu_device::bs_early_eidfct,   0);
662662
663   set_f1(task, f1_block,         &alto2_cpu_device::f1_eth_block_0, 0);
664   set_f1(task, f1_ether_eilfct,   &alto2_cpu_device::f1_eilfct_0, 0);
665   set_f1(task, f1_ether_epfct,   &alto2_cpu_device::f1_epfct_0, 0);
666   set_f1(task, f1_ether_ewfct,   0, &alto2_cpu_device::f1_ewfct_1);
663   set_f1(task, f1_block,         &alto2_cpu_device::f1_early_eth_block, 0);
664   set_f1(task, f1_ether_eilfct,   &alto2_cpu_device::f1_early_eilfct, 0);
665   set_f1(task, f1_ether_epfct,   &alto2_cpu_device::f1_early_epfct, 0);
666   set_f1(task, f1_ether_ewfct,   0, &alto2_cpu_device::f1_late_ewfct);
667667
668   set_f2(task, f2_ether_eodfct,   0, &alto2_cpu_device::f2_eodfct_1);
669   set_f2(task, f2_ether_eosfct,   0, &alto2_cpu_device::f2_eosfct_1);
670   set_f2(task, f2_ether_erbfct,   0, &alto2_cpu_device::f2_erbfct_1);
671   set_f2(task, f2_ether_eefct,   0, &alto2_cpu_device::f2_eefct_1);
672   set_f2(task, f2_ether_ebfct,   0, &alto2_cpu_device::f2_ebfct_1);
673   set_f2(task, f2_ether_ecbfct,   0, &alto2_cpu_device::f2_ecbfct_1);
674   set_f2(task, f2_ether_eisfct,   0, &alto2_cpu_device::f2_eisfct_1);
668   set_f2(task, f2_ether_eodfct,   0, &alto2_cpu_device::f2_late_eodfct);
669   set_f2(task, f2_ether_eosfct,   0, &alto2_cpu_device::f2_late_eosfct);
670   set_f2(task, f2_ether_erbfct,   0, &alto2_cpu_device::f2_late_erbfct);
671   set_f2(task, f2_ether_eefct,   0, &alto2_cpu_device::f2_late_eefct);
672   set_f2(task, f2_ether_ebfct,   0, &alto2_cpu_device::f2_late_ebfct);
673   set_f2(task, f2_ether_ecbfct,   0, &alto2_cpu_device::f2_late_ecbfct);
674   set_f2(task, f2_ether_eisfct,   0, &alto2_cpu_device::f2_late_eisfct);
675675
676676   m_active_callback[task] = &alto2_cpu_device::activate_eth;
677677}
branches/alto2/src/emu/cpu/alto2/alto2cpu.h
r26291r26292
10951095   DECLARE_READ16_MEMBER( bank_reg_r );         //!< read bank register in memory mapped I/O range
10961096   DECLARE_WRITE16_MEMBER( bank_reg_w );         //!< write bank register in memory mapped I/O range
10971097
1098   void bs_read_r_0();                        //!< bs_read_r early: drive bus by R register
1099   void bs_load_r_0();                        //!< bs_load_r early: load R places 0 on the BUS
1100   void bs_load_r_1();                        //!< bs_load_r late: load R from SHIFTER
1101   void bs_read_md_0();                     //!< bs_read_md early: drive BUS from read memory data
1102   void bs_mouse_0();                        //!< bs_mouse early: drive bus by mouse
1103   void bs_disp_0();                        //!< bs_disp early: drive bus by displacement (which?)
1104   void f1_load_mar_1();                     //!< f1_load_mar late: load memory address register
1105   void f1_task_0();                        //!< f1_task early: task switch
1106   void f2_bus_eq_zero_1();                  //!< f2_bus_eq_zero late: branch on bus equals zero
1107   void f2_shifter_lt_zero_1();               //!< f2_shifter_lt_zero late: branch on shifter less than zero
1108   void f2_shifter_eq_zero_1();               //!< f2_shifter_eq_zero late: branch on shifter equals zero
1109   void f2_bus_1();                        //!< f2_bus late: branch on bus bits BUS[6-15]
1110   void f2_alucy_1();                        //!< f2_alucy late: branch on latched ALU carry
1111   void f2_load_md_1();                     //!< f2_load_md late: load memory data
1098   void bs_early_read_r();                     //!< bus source: drive bus by R register
1099   void bs_early_load_r();                     //!< bus source: load R places 0 on the BUS
1100   void bs_late_load_r();                     //!< bus source: load R from SHIFTER
1101   void bs_early_read_md();                  //!< bus source: drive BUS from read memory data
1102   void bs_early_mouse();                     //!< bus source: drive bus by mouse
1103   void bs_early_disp();                     //!< bus source: drive bus by displacement (which?)
1104   void f1_late_load_mar();                  //!< F1 func: load memory address register
1105   void f1_early_task();                     //!< F1 func: task switch
1106   void f1_late_l_lsh_1();                     //!< F1 func: SHIFTER = left shift L once
1107   void f1_late_l_rsh_1();                     //!< F1 func: SHIFTER = right shift L once
1108   void f1_late_l_lcy_8();                     //!< F1 func: SHIFTER = byte swap L
1109   void f2_late_bus_eq_zero();                  //!< F2 func: branch on bus equals zero
1110   void f2_late_shifter_lt_zero();               //!< F2 func: branch on shifter less than zero
1111   void f2_late_shifter_eq_zero();               //!< F2 func: branch on shifter equals zero
1112   void f2_late_bus();                        //!< F2 func: branch on bus bits BUS[6-15]
1113   void f2_late_alucy();                     //!< F2 func: branch on latched ALU carry
1114   void f2_late_load_md();                     //!< F2 func: load memory data
11121115
11131116   UINT8* m_alu_a10;                        //!< ALU function to 74181 operation lookup PROM
1117#if   USE_ALU_74181
11141118   UINT32 alu_74181(UINT32 a, UINT32 b, UINT8 smc);
1115
1119#endif
11161120   void rdram();                           //!< read the microcode ROM/RAM halfword
11171121   void wrtram();                           //!< write the microcode RAM from M register and ALU
11181122
11191123   // ************************************************
11201124   // ram related stuff
11211125   // ************************************************
1122   void bs_read_sreg_0();                     //!< bs_read_sreg early: drive bus by S register or M (MYL), if rsel is = 0
1123   void bs_load_sreg_0();                     //!< bs_load_sreg early: load S register puts garbage on the bus
1124   void bs_load_sreg_1();                     //!< bs_load_sreg late: load S register from M
1126   void bs_early_read_sreg();                  //!< bus source: drive bus by S register or M (MYL), if rsel is = 0
1127   void bs_early_load_sreg();                  //!< bus source: load S register puts garbage on the bus
1128   void bs_late_load_sreg();                  //!< bus source: load S register from M
11251129   void branch_ROM(const char *from, int page);   //!< branch to ROM page
11261130   void branch_RAM(const char *from, int page);   //!< branch to RAM page
1127   void f1_swmode_1();                        //!< f1_swmode early: switch to micro program counter BUS[6-15] in other bank
1128   void f1_wrtram_1();                        //!< f1_wrtram late: start WRTRAM cycle
1129   void f1_rdram_1();                        //!< f1_rdram late: start RDRAM cycle
1131   void f1_late_swmode();                     //!< F1 func: switch to micro program counter BUS[6-15] in other bank
1132   void f1_late_wrtram();                     //!< F1 func: start WRTRAM cycle
1133   void f1_late_rdram();                     //!< F1 func: start RDRAM cycle
11301134#if   (ALTO2_UCODE_RAM_PAGES == 3)
1131   void f1_load_rmr_1();                     //!< f1_load_rmr late: load the reset mode register
1135   void f1_late_load_rmr();                  //!< F1 func: load the reset mode register
11321136#else   // ALTO2_UCODE_RAM_PAGES != 3
1133   void f1_load_srb_1();                     //!< f1_load_srb late: load the S register bank from BUS[12-14]
1137   void f1_late_load_srb();                  //!< F1 func: load the S register bank from BUS[12-14]
11341138#endif
11351139   void init_ram(int task);                  //!< called by RAM related tasks
11361140   void exit_ram();
r26291r26292
13631367    * sequence: 40 -> d0 -> b0 -> 20
13641368    * A motion to the south will first toggle MY1, then MY2.
13651369    * sequence: 10 -> 70 -> e0 -> 80
1366    *
1367    * This dump is from PROM madr.a32:
1368    * 0000: 017,007,013,017,013,017,017,007,007,017,017,013,017,013,007,017,
1369    * 0020: 003,015,005,003,005,003,003,015,015,003,003,005,003,005,015,003,
1370    * 0040: 011,001,016,011,016,011,011,001,001,011,011,016,011,016,001,011,
1371    * 0060: 017,007,013,017,013,017,017,007,007,017,017,013,017,013,007,017,
1372    * 0100: 011,001,016,011,016,011,011,001,001,011,011,016,011,016,001,011,
1373    * 0120: 017,007,013,017,013,017,017,007,007,017,017,013,017,013,007,017,
1374    * 0140: 017,007,013,017,013,017,017,007,007,017,017,013,017,013,007,017,
1375    * 0160: 003,015,005,003,005,003,003,015,015,003,003,005,003,005,015,003,
1376    * 0200: 003,015,005,003,005,003,003,015,015,003,003,005,003,005,015,003,
1377    * 0220: 017,007,013,017,013,017,017,007,007,017,017,013,017,013,007,017,
1378    * 0240: 017,007,013,017,013,017,017,007,007,017,017,013,017,013,007,017,
1379    * 0260: 011,001,016,011,016,011,011,001,001,011,011,016,011,016,001,011,
1380    * 0300: 017,007,013,017,013,017,017,007,007,017,017,013,017,013,007,017,
1381    * 0320: 011,001,016,011,016,011,011,001,001,011,011,016,011,016,001,011,
1382    * 0340: 003,015,005,003,005,003,003,015,015,003,003,005,003,005,015,003,
1383    * 0360: 017,007,013,017,013,017,017,007,007,017,017,013,017,013,007,017
13841370    * </PRE>
13851371    */
13861372   UINT8* m_madr_a32;
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14771463   void disk_bitclk(void *ptr, int arg);         //!< function to update the disk controller with a new bitclk
14781464#endif
14791465   void disk_block(int task);                  //!< called if one of the disk tasks (task_kwd or task_ksec) blocks
1480   void bs_read_kstat_0();                     //!< bs_read_kstat early: bus driven by disk status register KSTAT
1481   void bs_read_kdata_0();                     //!< bs_read_kdata early: bus driven by disk data register KDATA input
1482   void f1_strobe_1();                        //!< f1_strobe late: initiates a disk seek
1483   void f1_load_kstat_1();                     //!< f1_load_kstat late: load disk status register
1484   void f1_load_kdata_1();                     //!< f1_load_kdata late: load data out register, or the disk address register
1485   void f1_increcno_1();                     //!< f1_increcno late: advances shift registers holding KADR
1486   void f1_clrstat_1();                     //!< f1_clrstat late: reset all error latches
1487   void f1_load_kcom_1();                     //!< f1_load_kcom late: load the KCOM register from bus
1488   void f1_load_kadr_1();                     //!< f1_load_kadr late: load the KADR register from bus
1489   void f2_init_1();                        //!< f2_init late: branch on disk word task active and init
1490   void f2_rwc_1();                        //!< f2_rwc late: branch on read/write/check state of the current record
1491   void f2_recno_1();                        //!< f2_recno late: branch on the current record number by a lookup table
1492   void f2_xfrdat_1();                        //!< f2_xfrdat late: branch on the data transfer state
1493   void f2_swrnrdy_1();                     //!< f2_swrnrdy late: branch on the disk ready signal
1494   void f2_nfer_1();                        //!< f2_nfer late: branch on the disk fatal error condition
1495   void f2_strobon_1();                     //!< f2_strobon late: branch on the seek busy status
1466   void bs_early_read_kstat();                  //!< bus source: bus driven by disk status register KSTAT
1467   void bs_early_read_kdata();                  //!< bus source: bus driven by disk data register KDATA input
1468   void f1_late_strobe();                     //!< F1 func: initiates a disk seek
1469   void f1_late_load_kstat();                  //!< F1 func: load disk status register
1470   void f1_late_load_kdata();                  //!< F1 func: load data out register, or the disk address register
1471   void f1_late_increcno();                  //!< F1 func: advances shift registers holding KADR
1472   void f1_late_clrstat();                     //!< F1 func: reset all error latches
1473   void f1_late_load_kcom();                  //!< F1 func: load the KCOM register from bus
1474   void f1_late_load_kadr();                  //!< F1 func: load the KADR register from bus
1475   void f2_late_init();                     //!< F2 func: branch on disk word task active and init
1476   void f2_late_rwc();                        //!< F2 func: branch on read/write/check state of the current record
1477   void f2_late_recno();                     //!< F2 func: branch on the current record number by a lookup table
1478   void f2_late_xfrdat();                     //!< F2 func: branch on the data transfer state
1479   void f2_late_swrnrdy();                     //!< F2 func: branch on the disk ready signal
1480   void f2_late_nfer();                     //!< f2_nfer late: branch on the disk fatal error condition
1481   void f2_late_strobon();                     //!< f2_strobon late: branch on the seek busy status
14961482   void init_disk();                        //!< initialize the disk context
14971483   void exit_disk();                        //!< deinitialize the disk context
14981484
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17351721   void display_state_machine();
17361722
17371723   //! branch on the evenfield flip-flop
1738   void f2_evenfield_1(void);
1724   void f2_late_evenfield(void);
17391725
17401726   //! initialize the display context
17411727   void init_disp();
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18741860      UINT8 skip;                           //!< emulator skip
18751861      UINT8 cy;                           //!< emulator carry
18761862   }   m_emu;
1877   void bs_emu_disp_0();                     //!< bs_emu_disp early: drive bus by IR[8-15], possibly sign extended
1878   void f1_emu_block_0();                     //!< f1_block early: block task
1879   void f1_emu_load_rmr_1();                  //!< f1_load_rmr late: load the reset mode register
1880   void f1_emu_load_esrb_1();                  //!< f1_load_esrb late: load the extended S register bank from BUS[12-14]
1881   void f1_rsnf_0();                        //!< f1_rsnf early: drive the bus from the Ethernet node ID
1882   void f1_startf_0();                        //!< f1_startf early: defines commands for for I/O hardware, including Ethernet
1883   void f2_busodd_1();                        //!< f2_busodd late: branch on odd bus
1884   void f2_magic_1();                        //!< f2_magic late: shift and use T
1885   void f2_load_dns_0();                     //!< f2_load_dns early: modify RESELECT with DstAC = (3 - IR[3-4])
1886   void f2_load_dns_1();                     //!< f2_load_dns late: do novel shifts
1887   void f2_acdest_0();                        //!< f2_acdest early: modify RSELECT with DstAC = (3 - IR[3-4])
1863   void bs_early_emu_disp();                  //!< bus source: drive bus by IR[8-15], possibly sign extended
1864   void f1_early_emu_block();                  //!< F1 func: block task
1865   void f1_late_emu_load_rmr();               //!< F1 func: load the reset mode register
1866   void f1_late_emu_load_esrb();               //!< F1 func: load the extended S register bank from BUS[12-14]
1867   void f1_early_rsnf();                     //!< F1 func: drive the bus from the Ethernet node ID
1868   void f1_early_startf();                     //!< F1 func: defines commands for for I/O hardware, including Ethernet
1869   void f2_late_busodd();                     //!< F2 func: branch on odd bus
1870   void f2_late_magic();                     //!< F2 func: shift and use T
1871   void f2_early_load_dns();                  //!< F2 func: modify RESELECT with DstAC = (3 - IR[3-4])
1872   void f2_late_load_dns();                  //!< F2 func: do novel shifts
1873   void f2_early_acdest();                     //!< F2 func: modify RSELECT with DstAC = (3 - IR[3-4])
18881874   void bitblt_info();                        //!< debug bitblt opcode
1889   void f2_load_ir_1();                     //!< f2_load_ir late: load instruction register IR and branch on IR[0,5-7]
1890   void f2_idisp_1();                        //!< f2_idisp late: branch on: arithmetic IR_SH, others PROM ctl2k_u3[IR[1-7]]
1891   void f2_acsource_0();                     //!< f2_acsource early: modify RSELECT with SrcAC = (3 - IR[1-2])
1892   void f2_acsource_1();                     //!< f2_acsource late: branch on arithmetic IR_SH, others PROM ctl2k_u3[IR[1-7]]
1875   void f2_late_load_ir();                     //!< F2 func: load instruction register IR and branch on IR[0,5-7]
1876   void f2_late_idisp();                     //!< F2 func: branch on: arithmetic IR_SH, others PROM ctl2k_u3[IR[1-7]]
1877   void f2_early_acsource();                  //!< F2 func: modify RSELECT with SrcAC = (3 - IR[1-2])
1878   void f2_late_acsource();                  //!< F2 func: branch on arithmetic IR_SH, others PROM ctl2k_u3[IR[1-7]]
18931879   void init_emu(int task);                  //!< 000 initialize emulator task
18941880   void exit_emu();                        //!< deinitialize emulator task
18951881
18961882   // ************************************************
18971883   // ksec task
18981884   // ************************************************
1899   void f1_ksec_block_0(void);
1885   void f1_early_ksec_block(void);
19001886   void init_ksec(int task);                  //!< 004 initialize disk sector task
19011887   void exit_ksec();
19021888
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19661952    * D1 (11) BNE'   (buffer next empty ?)
19671953    * D2 (10) BNNE'  (buffer next next empty ?)
19681954    * D3  (9) BF'    (buffer full)
1969    *
1970    * Data from enet.a49 after address line reversal:
1971    * 000: 010 007 017 017 017 017 017 017 017 017 017 017 017 017 013 011
1972    * 020: 011 010 007 017 017 017 017 017 017 017 017 017 017 017 017 013
1973    * 040: 013 011 010 007 017 017 017 017 017 017 017 017 017 017 017 017
1974    * 060: 017 013 011 010 007 017 017 017 017 017 017 017 017 017 017 017
1975    * 100: 017 017 013 011 010 007 017 017 017 017 017 017 017 017 017 017
1976    * 120: 017 017 017 013 011 010 007 017 017 017 017 017 017 017 017 017
1977    * 140: 017 017 017 017 013 011 010 007 017 017 017 017 017 017 017 017
1978    * 160: 017 017 017 017 017 013 011 010 007 017 017 017 017 017 017 017
1979    * 200: 017 017 017 017 017 017 013 011 010 007 017 017 017 017 017 017
1980    * 220: 017 017 017 017 017 017 017 013 011 010 007 017 017 017 017 017
1981    * 240: 017 017 017 017 017 017 017 017 013 011 010 007 017 017 017 017
1982    * 260: 017 017 017 017 017 017 017 017 017 013 011 010 007 017 017 017
1983    * 300: 017 017 017 017 017 017 017 017 017 017 013 011 010 007 017 017
1984    * 320: 017 017 017 017 017 017 017 017 017 017 017 013 011 010 007 017
1985    * 340: 017 017 017 017 017 017 017 017 017 017 017 017 013 011 010 007
1986    * 360: 007 017 017 017 017 017 017 017 017 017 017 017 017 013 011 010
19871955    */
19881956   UINT8* m_ether_a49;
19891957
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20061974   TIMER_CALLBACK_MEMBER( tx_packet );            //!< transmit data from the FIFO to <nirvana for now>
20071975   void eth_wakeup();                        //!< check for the various reasons to wakeup the Ethernet task
20081976   void eth_startf();                        //!< start input or output depending on m_bus
2009   void bs_eidfct_0();                        //!< bs_eidfct early: Ethernet input data function
2010   void f1_eth_block_0();                     //!< f1_eth_block early: block the Ether task
2011   void f1_eilfct_0();                        //!< f1_eilfct early: Ethernet input look function
2012   void f1_epfct_0();                        //!< f1_epfct early: Ethernet post function
2013   void f1_ewfct_1();                        //!< f1_ewfct late: Ethernet countdown wakeup function
2014   void f2_eodfct_1();                        //!< f2_eodfct late: Ethernet output data function
2015   void f2_eosfct_1();                        //!< f2_eosfct late: Ethernet output start function
2016   void f2_erbfct_1();                        //!< f2_erbfct late: Ethernet reset branch function
2017   void f2_eefct_1();                        //!< f2_eefct late: Ethernet end of transmission function
2018   void f2_ebfct_1();                        //!< f2_ebfct late: Ethernet branch function
2019   void f2_ecbfct_1();                        //!< f2_ecbfct late: Ethernet countdown branch function
2020   void f2_eisfct_1();                        //!< f2_eisfct late: Ethernet input start function
1977   void bs_early_eidfct();                     //!< bus source: Ethernet input data function
1978   void f1_early_eth_block();                  //!< F1 func: block the Ether task
1979   void f1_early_eilfct();                     //!< F1 func: Ethernet input look function
1980   void f1_early_epfct();                     //!< F1 func: Ethernet post function
1981   void f1_late_ewfct();                     //!< F1 func: Ethernet countdown wakeup function
1982   void f2_late_eodfct();                     //!< F2 func: Ethernet output data function
1983   void f2_late_eosfct();                     //!< F2 func: Ethernet output start function
1984   void f2_late_erbfct();                     //!< F2 func: Ethernet reset branch function
1985   void f2_late_eefct();                     //!< F2 func: Ethernet end of transmission function
1986   void f2_late_ebfct();                     //!< F2 func: Ethernet branch function
1987   void f2_late_ecbfct();                     //!< F2 func: Ethernet countdown branch function
1988   void f2_late_eisfct();                     //!< F2 func: Ethernet input start function
20211989   void activate_eth();                     //!< called by the CPU when the Ethernet task becomes active
20221990   void init_ether(int task);                  //!< 007 initialize ethernet task
20231991   void exit_ether();                        //!< deinitialize ethernet task
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20251993   // ************************************************
20261994   // memory refresh task
20271995   // ************************************************
2028   void f1_mrt_block_0();                     //!< f1_mrt_block early: block the display word task
1996   void f1_early_mrt_block();                  //!< F1 func: block the display word task
20291997   void activate_mrt();                     //!< called by the CPU when MRT becomes active
20301998   void init_mrt(int task);                  //!< 010 initialize memory refresh task
20311999   void exit_mrt();                        //!< deinitialize memory refresh task
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20332001   // ************************************************
20342002   // display word task
20352003   // ************************************************
2036   void f1_dwt_block_0();                     //!< f1_dwt_block early: block the display word task
2037   void f2_dwt_load_ddr_1();                  //!< f2_dwt_load_ddr late: load the display data register
2004   void f1_early_dwt_block();                  //!< F1 func: block the display word task
2005   void f2_dwt_load_ddr_1();                  //!< F2 func: load the display data register
20382006   void init_dwt(int task);                  //!< 011 initialize display word task
20392007   void exit_dwt();                        //!< deinitialize display word task
20402008
20412009   // ************************************************
20422010   // cursor task
20432011   // ************************************************
2044   void f1_curt_block_0();                     //!< f1_curt_block early: disable the cursor task and set the curt_blocks flag
2045   void f2_load_xpreg_1();                     //!< f2_load_xpreg late: load the x position register from BUS[6-15]
2046   void f2_load_csr_1();                     //!< f2_load_csr late: load the cursor shift register from BUS[0-15]
2012   void f1_early_curt_block();                  //!< f1_curt_block early: disable the cursor task and set the curt_blocks flag
2013   void f2_late_load_xpreg();                  //!< f2_load_xpreg late: load the x position register from BUS[6-15]
2014   void f2_late_load_csr();                  //!< f2_load_csr late: load the cursor shift register from BUS[0-15]
20472015   void activate_curt();                     //!< curt_activate: called by the CPU when the cursor task becomes active
20482016   void init_curt(int task);                   //!< 012 initialize cursor task
20492017   void exit_curt();                        //!< deinitialize cursor task
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20512019   // ************************************************
20522020   // display horizontal task
20532021   // ************************************************
2054   void f1_dht_block_0();                     //!< f1_dht_block early: disable the display word task
2055   void f2_dht_setmode_1();                  //!< f2_dht_setmode late: set the next scanline's mode inverse and half clock and branch
2022   void f1_early_dht_block();                  //!< F1 func: disable the display word task
2023   void f2_late_dht_setmode();                  //!< F2 func: set the next scanline's mode inverse and half clock and branch
20562024   void activate_dht();                     //!< called by the CPU when the display horizontal task becomes active
20572025   void init_dht(int task);                  //!< 013 initialize display horizontal task
20582026   void exit_dht();                        //!< deinitialize display horizontal task
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20602028   // ************************************************
20612029   // display vertical task
20622030   // ************************************************
2063   void f1_dvt_block_0();                     //!< f1_dvt_block early: disable the display word task
2031   void f1_early_dvt_block();                  //!< F1 func: disable the display word task
20642032   void activate_dvt();                     //!< called by the CPU when the display vertical task becomes active
20652033   void init_dvt(int task);                  //!< 014 initialize display vertical task
20662034   void exit_dvt();                        //!< deinitialize display vertical task
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20752043   // ************************************************
20762044   // disk word task
20772045   // ************************************************
2078   void f1_kwd_block_0(void);
2046   void f1_early_kwd_block();                  //!< F1 func: disable the disk word task
20792047   void init_kwd(int task);                  //!< 016 initialize disk word task
20802048   void exit_kwd();                        //!< deinitialize disk word task
20812049};
branches/alto2/src/emu/cpu/alto2/a2curt.c
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1212/**
1313 * @brief f1_curt_block early: disable the cursor task and set the curt_blocks flag
1414 */
15void alto2_cpu_device::f1_curt_block_0()
15void alto2_cpu_device::f1_early_curt_block()
1616{
1717   m_task_wakeup &= ~(1 << m_task);
1818   LOG((LOG_CURT,2,"   BLOCK %s\n", task_name(m_task)));
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2222/**
2323 * @brief f2_load_xpreg late: load the x position register from BUS[6-15]
2424 */
25void alto2_cpu_device::f2_load_xpreg_1()
25void alto2_cpu_device::f2_late_load_xpreg()
2626{
2727   m_dsp.xpreg = A2_GET16(m_bus,16,6,15);
2828   LOG((LOG_CURT,2,"   XPREG← BUS[6-15] (%#o)\n", m_dsp.xpreg));
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4545 *    15        000000000000000xxxxxxxxxxxxxxxx0
4646 * </PRE>
4747 */
48void alto2_cpu_device::f2_load_csr_1()
48void alto2_cpu_device::f2_late_load_csr()
4949{
5050   m_dsp.csr = m_bus;
5151   LOG((LOG_CURT,2,"   CSR← BUS (%#o)\n", m_dsp.csr));
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6666/** @brief initialize the cursor task F1 and F2 functions */
6767void alto2_cpu_device::init_curt(int task)
6868{
69   set_f1(task, f1_block,            &alto2_cpu_device::f1_curt_block_0, 0);
70   set_f2(task, f2_curt_load_xpreg,   0, &alto2_cpu_device::f2_load_xpreg_1);
71   set_f2(task, f2_curt_load_csr,      0, &alto2_cpu_device::f2_load_csr_1);
69   set_f1(task, f1_block,            &alto2_cpu_device::f1_early_curt_block, 0);
70   set_f2(task, f2_curt_load_xpreg,   0, &alto2_cpu_device::f2_late_load_xpreg);
71   set_f2(task, f2_curt_load_csr,      0, &alto2_cpu_device::f2_late_load_csr);
7272   m_active_callback[task] = &alto2_cpu_device::activate_curt;
7373}
7474
branches/alto2/src/emu/cpu/alto2/a2ram.c
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1515 * Note: RSEL == 0 can't be read, because it is decoded as
1616 * access to the M register (MYL latch access, LREF' in the schematics)
1717 */
18void alto2_cpu_device::bs_read_sreg_0()
18void alto2_cpu_device::bs_early_read_sreg()
1919{
2020   UINT8 reg = MIR_RSEL(m_mir);
2121   UINT16 r;
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3434/**
3535 * @brief bs_load_sreg early: load S register puts garbage on the bus
3636 */
37void alto2_cpu_device::bs_load_sreg_0()
37void alto2_cpu_device::bs_early_load_sreg()
3838{
3939   int r = 0;   /* ??? */
4040   LOG((LOG_RAM,2,"   S%02o← BUS &= garbage (%#o)\n", MIR_RSEL(m_mir), r));
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4444/**
4545 * @brief bs_load_sreg late: load S register from M
4646 */
47void alto2_cpu_device::bs_load_sreg_1()
47void alto2_cpu_device::bs_late_load_sreg()
4848{
4949   UINT8 reg = MIR_RSEL(m_mir);
5050   UINT8 bank = m_s_reg_bank[m_task];
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8484 * NEXT[0-9] of uninitialized RAM is 0.
8585 *
8686 */
87void alto2_cpu_device::f1_swmode_1()
87void alto2_cpu_device::f1_late_swmode()
8888{
8989   /* currently executing in what page? */
9090   UINT16 current = m_mpc / ALTO2_UCODE_PAGE_SIZE;
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232232/**
233233 * @brief f1_wrtram late: start WRTRAM cycle
234234 */
235void alto2_cpu_device::f1_wrtram_1()
235void alto2_cpu_device::f1_late_wrtram()
236236{
237237   m_wrtram_flag = true;
238238   LOG((LOG_RAM,2,"   WRTRAM\n"));
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241241/**
242242 * @brief f1_rdram late: start RDRAM cycle
243243 */
244void alto2_cpu_device::f1_rdram_1()
244void alto2_cpu_device::f1_late_rdram()
245245{
246246   m_rdram_flag = true;
247247   LOG((LOG_RAM,2,"   RDRAM\n"));
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256256 * RAM option, F1=013 performs RMR← in all RAM-related tasks, including
257257 * the emulator.
258258 */
259void alto2_cpu_device::f1_load_rmr_1()
259void alto2_cpu_device::f1_late_load_rmr()
260260{
261261   LOG((LOG_RAM,2,"   RMR←; BUS (%#o)\n", m_bus));
262262   m_reset_mode = m_bus;
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265265/**
266266 * @brief f1_load_srb late: load the S register bank from BUS[12-14]
267267 */
268void alto2_cpu_device::f1_load_srb_1()
268void alto2_cpu_device::f1_late_load_srb()
269269{
270270   m_s_reg_bank[m_task] = A2_GET16(m_bus,16,12,14) % ALTO2_SREG_BANKS;
271271   LOG((LOG_RAM,2,"   SRB←; srb[%d] := %#o\n", m_task, m_s_reg_bank[m_task]));
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279279{
280280   m_ram_related[task] = true;
281281
282   set_bs(task, bs_ram_read_slocation,   &alto2_cpu_device::bs_read_sreg_0, 0);
283   set_bs(task, bs_ram_load_slocation,   &alto2_cpu_device::bs_load_sreg_0, &alto2_cpu_device::bs_load_sreg_1);
282   set_bs(task, bs_ram_read_slocation,   &alto2_cpu_device::bs_early_read_sreg, 0);
283   set_bs(task, bs_ram_load_slocation,   &alto2_cpu_device::bs_early_load_sreg, &alto2_cpu_device::bs_late_load_sreg);
284284
285   set_f1(task, f1_ram_swmode,         0, &alto2_cpu_device::f1_swmode_1);
286   set_f1(task, f1_ram_wrtram,         0, &alto2_cpu_device::f1_wrtram_1);
287   set_f1(task, f1_ram_rdram,         0, &alto2_cpu_device::f1_rdram_1);
285   set_f1(task, f1_ram_swmode,         0, &alto2_cpu_device::f1_late_swmode);
286   set_f1(task, f1_ram_wrtram,         0, &alto2_cpu_device::f1_late_wrtram);
287   set_f1(task, f1_ram_rdram,         0, &alto2_cpu_device::f1_late_rdram);
288288#if   (ALTO2_UCODE_RAM_PAGES == 3)
289289   set_f1(task, f1_ram_load_rmr,      0, &alto2_cpu_device::f1_load_rmr_1);
290290#else   // ALTO2_UCODE_RAM_PAGES != 3
291   set_f1(task, f1_ram_load_srb,      0, &alto2_cpu_device::f1_load_srb_1);
291   set_f1(task, f1_ram_load_srb,      0, &alto2_cpu_device::f1_late_load_srb);
292292#endif
293293}
294294
branches/alto2/src/emu/cpu/alto2/a2dht.c
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1212/**
1313 * @brief f1_dht_block early: disable the display word task
1414 */
15void alto2_cpu_device::f1_dht_block_0()
15void alto2_cpu_device::f1_early_dht_block()
1616{
1717   m_dsp.dht_blocks = 1;
1818   /* clear the wakeup for the display horizontal task */
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2828 *
2929 * The current BUS[0] drives the NEXT[09] line, i.e. branches to 0 or 1
3030 */
31void alto2_cpu_device::f2_dht_setmode_1()
31void alto2_cpu_device::f2_late_dht_setmode()
3232{
3333   UINT16 r = A2_GET16(m_bus,16,0,0);
3434   m_dsp.setmode = m_bus;
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5252 */
5353void alto2_cpu_device::init_dht(int task)
5454{
55   set_f1(task, f1_block,         &alto2_cpu_device::f1_dht_block_0, 0);
56   set_f2(task, f2_dht_evenfield,   0, &alto2_cpu_device::f2_evenfield_1);
57   set_f2(task, f2_dht_setmode,   0, &alto2_cpu_device::f2_dht_setmode_1);
55   set_f1(task, f1_block,         &alto2_cpu_device::f1_early_dht_block, 0);
56   set_f2(task, f2_dht_evenfield,   0, &alto2_cpu_device::f2_late_evenfield);
57   set_f2(task, f2_dht_setmode,   0, &alto2_cpu_device::f2_late_dht_setmode);
5858   m_active_callback[task] = &alto2_cpu_device::activate_dht;
5959}
6060
branches/alto2/src/emu/cpu/alto2/a2kwd.c
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1010#include "alto2cpu.h"
1111
1212//! f1_kwd_block early: block the disk word task
13void alto2_cpu_device::f1_kwd_block_0()
13void alto2_cpu_device::f1_early_kwd_block()
1414{
1515   LOG((LOG_KWD,2,"   BLOCK %s\n", task_name(m_task)));
1616   disk_block(m_task);
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1919//! disk word task slot initialization
2020void alto2_cpu_device::init_kwd(int task)
2121{
22   set_bs(task, bs_kwd_read_kstat,      &alto2_cpu_device::bs_read_kstat_0, 0);
23   set_bs(task, bs_kwd_read_kdata,      &alto2_cpu_device::bs_read_kdata_0, 0);
22   set_bs(task, bs_kwd_read_kstat,      &alto2_cpu_device::bs_early_read_kstat, 0);
23   set_bs(task, bs_kwd_read_kdata,      &alto2_cpu_device::bs_early_read_kdata, 0);
2424
25   set_f1(task, f1_block,            &alto2_cpu_device::f1_kwd_block_0, 0);
25   set_f1(task, f1_block,            &alto2_cpu_device::f1_early_kwd_block, 0);
2626
2727   set_f1(task, f1_task_10,         0, 0);
28   set_f1(task, f1_kwd_strobe,         0, &alto2_cpu_device::f1_strobe_1);
29   set_f1(task, f1_kwd_load_kstat,      0, &alto2_cpu_device::f1_load_kstat_1);
30   set_f1(task, f1_kwd_increcno,      0, &alto2_cpu_device::f1_increcno_1);
31   set_f1(task, f1_kwd_clrstat,      0, &alto2_cpu_device::f1_clrstat_1);
32   set_f1(task, f1_kwd_load_kcom,      0, &alto2_cpu_device::f1_load_kcom_1);
33   set_f1(task, f1_kwd_load_kadr,      0, &alto2_cpu_device::f1_load_kadr_1);
34   set_f1(task, f1_kwd_load_kdata,      0, &alto2_cpu_device::f1_load_kdata_1);
28   set_f1(task, f1_kwd_strobe,         0, &alto2_cpu_device::f1_late_strobe);
29   set_f1(task, f1_kwd_load_kstat,      0, &alto2_cpu_device::f1_late_load_kstat);
30   set_f1(task, f1_kwd_increcno,      0, &alto2_cpu_device::f1_late_increcno);
31   set_f1(task, f1_kwd_clrstat,      0, &alto2_cpu_device::f1_late_clrstat);
32   set_f1(task, f1_kwd_load_kcom,      0, &alto2_cpu_device::f1_late_load_kcom);
33   set_f1(task, f1_kwd_load_kadr,      0, &alto2_cpu_device::f1_late_load_kadr);
34   set_f1(task, f1_kwd_load_kdata,      0, &alto2_cpu_device::f1_late_load_kdata);
3535
36   set_f2(task, f2_kwd_init,         0, &alto2_cpu_device::f2_init_1);
37   set_f2(task, f2_kwd_rwc,         0, &alto2_cpu_device::f2_rwc_1);
38   set_f2(task, f2_kwd_recno,         0, &alto2_cpu_device::f2_recno_1);
39   set_f2(task, f2_kwd_xfrdat,         0, &alto2_cpu_device::f2_xfrdat_1);
40   set_f2(task, f2_kwd_swrnrdy,      0, &alto2_cpu_device::f2_swrnrdy_1);
41   set_f2(task, f2_kwd_nfer,         0, &alto2_cpu_device::f2_nfer_1);
42   set_f2(task, f2_kwd_strobon,      0, &alto2_cpu_device::f2_strobon_1);
36   set_f2(task, f2_kwd_init,         0, &alto2_cpu_device::f2_late_init);
37   set_f2(task, f2_kwd_rwc,         0, &alto2_cpu_device::f2_late_rwc);
38   set_f2(task, f2_kwd_recno,         0, &alto2_cpu_device::f2_late_recno);
39   set_f2(task, f2_kwd_xfrdat,         0, &alto2_cpu_device::f2_late_xfrdat);
40   set_f2(task, f2_kwd_swrnrdy,      0, &alto2_cpu_device::f2_late_swrnrdy);
41   set_f2(task, f2_kwd_nfer,         0, &alto2_cpu_device::f2_late_nfer);
42   set_f2(task, f2_kwd_strobon,      0, &alto2_cpu_device::f2_late_strobon);
4343   set_f2(task, f2_task_17,         0, 0);
4444}
4545
branches/alto2/src/emu/cpu/alto2/a2ksec.c
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1010#include "alto2cpu.h"
1111
1212//! f1_ksec_block early: block the disk sector task
13void alto2_cpu_device::f1_ksec_block_0()
13void alto2_cpu_device::f1_early_ksec_block()
1414{
1515   LOG((LOG_KSEC,2,"   BLOCK %s\n", task_name(m_task)));
1616   disk_block(m_task);
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1919//! disk sector task slot initialization
2020void alto2_cpu_device::init_ksec(int task)
2121{
22   set_bs(task, bs_ksec_read_kstat,   &alto2_cpu_device::bs_read_kstat_0, 0);
23   set_bs(task, bs_ksec_read_kdata,   &alto2_cpu_device::bs_read_kdata_0, 0);
22   set_bs(task, bs_ksec_read_kstat,   &alto2_cpu_device::bs_early_read_kstat, 0);
23   set_bs(task, bs_ksec_read_kdata,   &alto2_cpu_device::bs_early_read_kdata, 0);
2424
25   set_f1(task, f1_block,            &alto2_cpu_device::f1_ksec_block_0, 0);
25   set_f1(task, f1_block,            &alto2_cpu_device::f1_early_ksec_block, 0);
2626
2727   set_f1(task, f1_task_10,         0, 0);
28   set_f1(task, f1_ksec_strobe,      0, &alto2_cpu_device::f1_strobe_1);
29   set_f1(task, f1_ksec_load_kstat,   0, &alto2_cpu_device::f1_load_kstat_1);
30   set_f1(task, f1_ksec_increcno,      0, &alto2_cpu_device::f1_increcno_1);
31   set_f1(task, f1_ksec_clrstat,      0, &alto2_cpu_device::f1_clrstat_1);
32   set_f1(task, f1_ksec_load_kcom,      0, &alto2_cpu_device::f1_load_kcom_1);
33   set_f1(task, f1_ksec_load_kadr,      0, &alto2_cpu_device::f1_load_kadr_1);
34   set_f1(task, f1_ksec_load_kdata,   0, &alto2_cpu_device::f1_load_kdata_1);
28   set_f1(task, f1_ksec_strobe,      0, &alto2_cpu_device::f1_late_strobe);
29   set_f1(task, f1_ksec_load_kstat,   0, &alto2_cpu_device::f1_late_load_kstat);
30   set_f1(task, f1_ksec_increcno,      0, &alto2_cpu_device::f1_late_increcno);
31   set_f1(task, f1_ksec_clrstat,      0, &alto2_cpu_device::f1_late_clrstat);
32   set_f1(task, f1_ksec_load_kcom,      0, &alto2_cpu_device::f1_late_load_kcom);
33   set_f1(task, f1_ksec_load_kadr,      0, &alto2_cpu_device::f1_late_load_kadr);
34   set_f1(task, f1_ksec_load_kdata,   0, &alto2_cpu_device::f1_late_load_kdata);
3535
36   set_f2(task, f2_ksec_init,         0, &alto2_cpu_device::f2_init_1);
37   set_f2(task, f2_ksec_rwc,         0, &alto2_cpu_device::f2_rwc_1);
38   set_f2(task, f2_ksec_recno,         0, &alto2_cpu_device::f2_recno_1);
39   set_f2(task, f2_ksec_xfrdat,      0, &alto2_cpu_device::f2_xfrdat_1);
40   set_f2(task, f2_ksec_swrnrdy,      0, &alto2_cpu_device::f2_swrnrdy_1);
41   set_f2(task, f2_ksec_nfer,         0, &alto2_cpu_device::f2_nfer_1);
42   set_f2(task, f2_ksec_strobon,      0, &alto2_cpu_device::f2_strobon_1);
36   set_f2(task, f2_ksec_init,         0, &alto2_cpu_device::f2_late_init);
37   set_f2(task, f2_ksec_rwc,         0, &alto2_cpu_device::f2_late_rwc);
38   set_f2(task, f2_ksec_recno,         0, &alto2_cpu_device::f2_late_recno);
39   set_f2(task, f2_ksec_xfrdat,      0, &alto2_cpu_device::f2_late_xfrdat);
40   set_f2(task, f2_ksec_swrnrdy,      0, &alto2_cpu_device::f2_late_swrnrdy);
41   set_f2(task, f2_ksec_nfer,         0, &alto2_cpu_device::f2_late_nfer);
42   set_f2(task, f2_ksec_strobon,      0, &alto2_cpu_device::f2_late_strobon);
4343   set_f2(task, f2_task_17,         0, 0);
4444
4545   m_task_wakeup |= 1 << task;
branches/alto2/src/emu/cpu/alto2/a2emu.c
r26291r26292
262262 * then the DISP field is sign-extended and put on the bus.
263263 *
264264 */
265void alto2_cpu_device::bs_emu_disp_0()
265void alto2_cpu_device::bs_early_emu_disp()
266266{
267267   UINT16 r = IR_DISP(m_emu.ir);
268268   if (IR_X(m_emu.ir)) {
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277277 *
278278 * The task request for the active task is cleared
279279 */
280void alto2_cpu_device::f1_emu_block_0()
280void alto2_cpu_device::f1_early_emu_block()
281281{
282282#if   0
283283   CPU_CLR_TASK_WAKEUP(m_task);
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300300/**
301301 * @brief f1_load_rmr late: load the reset mode register
302302 */
303void alto2_cpu_device::f1_emu_load_rmr_1()
303void alto2_cpu_device::f1_late_emu_load_rmr()
304304{
305305   LOG((LOG_EMU,2,"   RMR←; BUS (%#o)\n", m_bus));
306306   m_reset_mode = m_bus;
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309309/**
310310 * @brief f1_load_esrb late: load the extended S register bank from BUS[12-14]
311311 */
312void alto2_cpu_device::f1_emu_load_esrb_1()
312void alto2_cpu_device::f1_late_emu_load_esrb()
313313{
314314   LOG((LOG_EMU,2,"   ESRB←; BUS[12-14] (%#o)\n", m_bus));
315315   m_s_reg_bank[m_task] = A2_GET16(m_bus,16,12,14);
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321321 * TODO: move this to the Ethernet code? It's really a emulator
322322 * specific function that is decoded by the Ethernet card.
323323 */
324void alto2_cpu_device::f1_rsnf_0()
324void alto2_cpu_device::f1_early_rsnf()
325325{
326326   UINT16 r = 0177400 | m_ether_id;
327327   LOG((LOG_EMU,2,"   ←RSNF; (%#o)\n", r));
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355355 * TODO: move this to the Ethernet code? It's really a emulator
356356 * specific function that is decoded by the Ethernet card.
357357 */
358void alto2_cpu_device::f1_startf_0()
358void alto2_cpu_device::f1_early_startf()
359359{
360360   LOG((LOG_EMU,2,"   STARTF (BUS is %06o)\n", m_bus));
361361   /* TODO: what do we do here? reset the CPU on bit 0? */
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370370/**
371371 * @brief f2_busodd late: branch on odd bus
372372 */
373void alto2_cpu_device::f2_busodd_1()
373void alto2_cpu_device::f2_late_busodd()
374374{
375375   UINT16 r = m_bus & 1;
376376   LOG((LOG_EMU,2,"   BUSODD; %sbranch (%#o|%#o)\n", r ? "" : "no ", m_next2, r));
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381381/**
382382 * @brief f2_magic late: shift and use T
383383 */
384void alto2_cpu_device::f2_magic_1()
384void alto2_cpu_device::f2_late_magic()
385385{
386386   int XC;
387387   switch (MIR_F1(m_mir)) {
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407407/**
408408 * @brief dns early: modify RESELECT with DstAC = (3 - IR[3-4])
409409 */
410void alto2_cpu_device::f2_load_dns_0()
410void alto2_cpu_device::f2_early_load_dns()
411411{
412412#if   USE_SCHEMATICS_RSEL
413413   A2_PUT8(m_rsel, 5, 3, 3, RA3(f2_emu_load_dns, m_emu.ir, m_rsel));
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424424 * <PRE>
425425 * New emulator carry is selected by instruction register
426426 * bits CY = IR[10-11]. R register and emulator carry are
427 * loaded only if NL = IR[12] is 0.
427 * loaded only if NL = IR[12] is 0 (NL = no load).
428428 * SKIP is set according to SK = IR[13-15].
429429 *
430430 *  CARRY     = !m_emu.cy
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446446 *            = (((NEWCARRY ^ 1) & IR14) | (SHZERO & IR13)) ^ IR15
447447 * </PRE>
448448 */
449void alto2_cpu_device::f2_load_dns_1()
449void alto2_cpu_device::f2_late_load_dns()
450450{
451   UINT8 IR10 = A2_BIT32(m_emu.ir,16,10);
452   UINT8 IR11 = A2_BIT32(m_emu.ir,16,11);
453   UINT8 IR12 = A2_BIT32(m_emu.ir,16,12);
454   UINT8 IR13 = A2_BIT32(m_emu.ir,16,13);
455   UINT8 IR14 = A2_BIT32(m_emu.ir,16,14);
456   UINT8 IR15 = A2_BIT32(m_emu.ir,16,15);
451   UINT8 IR10 = A2_BIT16(m_emu.ir,16,10);
452   UINT8 IR11 = A2_BIT16(m_emu.ir,16,11);
453   UINT8 IR12 = A2_BIT16(m_emu.ir,16,12);
454   UINT8 IR13 = A2_BIT16(m_emu.ir,16,13);
455   UINT8 IR14 = A2_BIT16(m_emu.ir,16,14);
456   UINT8 IR15 = A2_BIT16(m_emu.ir,16,15);
457457   UINT8 exorB = IR11 ^ IR10;
458458   UINT8 CARRY = m_emu.cy ^ 1;
459459   UINT8 ORA = (exorB | CARRY) ^ 1;
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498498/**
499499 * @brief f2_acdest early: modify RSELECT with DstAC = (3 - IR[3-4])
500500 */
501void alto2_cpu_device::f2_acdest_0()
501void alto2_cpu_device::f2_early_acdest()
502502{
503503#if   USE_SCHEMATICS_RSEL
504504   ALTO2_PUT(m_rsel, 5, 3, 3, RA3(f2_emu_acdest, m_emu.ir, m_rsel));
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556556 *
557557 * Loading the IR clears the skip latch.
558558 */
559void alto2_cpu_device::f2_load_ir_1()
559void alto2_cpu_device::f2_late_load_ir()
560560{
561561   UINT16 r = (A2_BIT16(m_bus,16,0) << 3) | A2_GET16(m_bus,16,5,7);
562562
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621621/**
622622 * @brief f2_idisp late: branch on: arithmetic IR_SH, others PROM ctl2k_u3[IR[1-7]]
623623 */
624void alto2_cpu_device::f2_idisp_1()
624void alto2_cpu_device::f2_late_idisp()
625625{
626626   UINT16 r;
627627
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641641/**
642642 * @brief f2_acsource early: modify RSELECT with SrcAC = (3 - IR[1-2])
643643 */
644void alto2_cpu_device::f2_acsource_0()
644void alto2_cpu_device::f2_early_acsource()
645645{
646646#if   USE_SCHEMATICS_RSEL
647647   A2_PUT8(m_rsel, 5, 3, 3, RA3(f2_emu_acsource, m_emu.ir, m_rsel));
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655655/**
656656 * @brief f2_acsource late: branch on: arithmetic IR_SH, others PROM ctl2k_u3[IR[1-7]]
657657 */
658void alto2_cpu_device::f2_acsource_1()
658void alto2_cpu_device::f2_late_acsource()
659659{
660660   UINT16 r;
661661
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676676{
677677   init_ram(task);
678678
679   set_bs(task, bs_emu_read_sreg,      &alto2_cpu_device::bs_read_sreg_0, 0);
680   set_bs(task, bs_emu_load_sreg,      &alto2_cpu_device::bs_load_sreg_0, &alto2_cpu_device::bs_load_sreg_1);
681   set_bs(task, bs_disp,            &alto2_cpu_device::bs_emu_disp_0, 0);
679   set_bs(task, bs_emu_read_sreg,      &alto2_cpu_device::bs_early_read_sreg, 0);
680   set_bs(task, bs_emu_load_sreg,      &alto2_cpu_device::bs_early_load_sreg, &alto2_cpu_device::bs_late_load_sreg);
681   set_bs(task, bs_disp,            &alto2_cpu_device::bs_early_emu_disp, 0);
682682
683   set_f1(task, f1_block,            &alto2_cpu_device::f1_emu_block_0, 0);   // catch the emulator task trying to block (wrong branch)
684   set_f1(task, f1_emu_swmode,         0, &alto2_cpu_device::f1_swmode_1);
685   set_f1(task, f1_emu_wrtram,         0, &alto2_cpu_device::f1_wrtram_1);
686   set_f1(task, f1_emu_rdram,         0, &alto2_cpu_device::f1_rdram_1);
687   set_f1(task, f1_emu_load_rmr,      0, &alto2_cpu_device::f1_emu_load_rmr_1);
683   set_f1(task, f1_block,            &alto2_cpu_device::f1_early_emu_block, 0);   // catch the emulator task trying to block (wrong branch)
684   set_f1(task, f1_emu_swmode,         0, &alto2_cpu_device::f1_late_swmode);
685   set_f1(task, f1_emu_wrtram,         0, &alto2_cpu_device::f1_late_wrtram);
686   set_f1(task, f1_emu_rdram,         0, &alto2_cpu_device::f1_late_rdram);
687   set_f1(task, f1_emu_load_rmr,      0, &alto2_cpu_device::f1_late_emu_load_rmr);
688688   /* F1 014 is undefined (?) */
689   set_f1(task, f1_task_14,         0, &alto2_cpu_device::f1_load_srb_1);
690   set_f1(task, f1_emu_load_esrb,      0, &alto2_cpu_device::f1_emu_load_esrb_1);
691   set_f1(task, f1_emu_rsnf,         &alto2_cpu_device::f1_rsnf_0, 0);
692   set_f1(task, f1_emu_startf,         &alto2_cpu_device::f1_startf_0,   0);
689   set_f1(task, f1_task_14,         0, &alto2_cpu_device::f1_late_load_srb);
690   set_f1(task, f1_emu_load_esrb,      0, &alto2_cpu_device::f1_late_emu_load_esrb);
691   set_f1(task, f1_emu_rsnf,         &alto2_cpu_device::f1_early_rsnf, 0);
692   set_f1(task, f1_emu_startf,         &alto2_cpu_device::f1_early_startf,   0);
693693
694   set_f2(task, f2_emu_busodd,         0, &alto2_cpu_device::f2_busodd_1);
695#if   0
696   set_f2(task, f2_emu_magic,         0, &alto2_cpu_device::f2_magic_1);
697#else
698   set_f2(task, f2_emu_magic,         0, 0);
699#endif
700   set_f2(task, f2_emu_load_dns,      &alto2_cpu_device::f2_load_dns_0, &alto2_cpu_device::f2_load_dns_1);
701   set_f2(task, f2_emu_acdest,         &alto2_cpu_device::f2_acdest_0, 0);
702   set_f2(task, f2_emu_load_ir,      0, &alto2_cpu_device::f2_load_ir_1);
703   set_f2(task, f2_emu_idisp,         0, &alto2_cpu_device::f2_idisp_1);
704   set_f2(task, f2_emu_acsource,      &alto2_cpu_device::f2_acsource_0, &alto2_cpu_device::f2_acsource_1);
694   set_f2(task, f2_emu_busodd,         0, &alto2_cpu_device::f2_late_busodd);
695   set_f2(task, f2_emu_magic,         0, &alto2_cpu_device::f2_late_magic);
696   set_f2(task, f2_emu_load_dns,      &alto2_cpu_device::f2_early_load_dns, &alto2_cpu_device::f2_late_load_dns);
697   set_f2(task, f2_emu_acdest,         &alto2_cpu_device::f2_early_acdest, 0);
698   set_f2(task, f2_emu_load_ir,      0, &alto2_cpu_device::f2_late_load_ir);
699   set_f2(task, f2_emu_idisp,         0, &alto2_cpu_device::f2_late_idisp);
700   set_f2(task, f2_emu_acsource,      &alto2_cpu_device::f2_early_acsource, &alto2_cpu_device::f2_late_acsource);
705701}
706702
707703void alto2_cpu_device::exit_emu()
branches/alto2/src/emu/cpu/alto2/a2disk.c
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16421642 *     BUS[13]    CHSEMERROR (FF 44b output Q' inverted)
16431643 * </PRE>
16441644 */
1645void alto2_cpu_device::bs_read_kstat_0()
1645void alto2_cpu_device::bs_early_read_kstat()
16461646{
16471647   diablo_hd_device* dhd = m_drive[m_dsk.drive];
16481648   UINT16 r;
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16891689 * 15 bits, and the current read data bit is the least significant
16901690 * bit. This is handled in kwd_timing.
16911691 */
1692void alto2_cpu_device::bs_read_kdata_0()
1692void alto2_cpu_device::bs_early_read_kdata()
16931693{
16941694   UINT16 r;
16951695   /* get the current word from the drive */
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17051705 * been loaded previously, and the SENDADR bit of the KCOM
17061706 * register previously set to 1.
17071707 */
1708void alto2_cpu_device::f1_strobe_1()
1708void alto2_cpu_device::f1_late_strobe()
17091709{
17101710   if (GET_KCOM_SENDADR(m_dsk.kcom)) {
17111711      LOG((LOG_DISK,1,"   STROBE (SENDADR:1)\n"));
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17291729 *
17301730 * NB: The 4 bits are just software, not changed by hardware
17311731 */
1732void alto2_cpu_device::f1_load_kstat_1()
1732void alto2_cpu_device::f1_late_load_kstat()
17331733{
17341734   LOG((LOG_DISK,1,"   KSTAT←; BUS[12-15] %#o\n", m_bus));
17351735   LOG((LOG_DISK,2,"      IDLE       : %d\n", GET_KSTAT_IDLE(m_bus)));
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17701770 *
17711771 * KDATA is loaded from BUS.
17721772 */
1773void alto2_cpu_device::f1_load_kdata_1()
1773void alto2_cpu_device::f1_late_load_kdata()
17741774{
17751775   m_dsk.dataout = m_bus;
17761776   if (GET_KCOM_SENDADR(m_dsk.kcom)) {
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18431843 * [ 6th        1           1         (none) 1 = check ]
18441844 * </PRE>
18451845 */
1846void alto2_cpu_device::f1_increcno_1()
1846void alto2_cpu_device::f1_late_increcno()
18471847{
18481848   switch (m_dsk.krecno) {
18491849   case RECNO_HEADER:
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18781878 *
18791879 * NB: IDLE (KSTAT[12]) and COMPLETION (KSTAT[14-15]) are not cleared
18801880 */
1881void alto2_cpu_device::f1_clrstat_1()
1881void alto2_cpu_device::f1_late_clrstat()
18821882{
18831883   diablo_hd_device* dhd = m_drive[m_dsk.drive];
18841884   UINT8 s0, s1;
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19841984 *      SENDADR = 0 inhibits such signalling.
19851985 * </PRE>
19861986 */
1987void alto2_cpu_device::f1_load_kcom_1()
1987void alto2_cpu_device::f1_late_load_kcom()
19881988{
19891989   m_dsk.kcom = m_bus;
19901990   LOG((LOG_DISK,2,"   KCOM←; BUS %06o\n", m_dsk.kcom));
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20052005 *
20062006 * NB: the record numer RECNO(0) and RECNO(1) is reset to 0
20072007 */
2008void alto2_cpu_device::f1_load_kadr_1()
2008void alto2_cpu_device::f1_late_load_kadr()
20092009{
20102010   int unit, head;
20112011
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20452045 *
20462046 * NEXT ← NEXT OR (WDTASKACT && WDINIT ? 037 : 0)
20472047 */
2048void alto2_cpu_device::f2_init_1()
2048void alto2_cpu_device::f2_late_init()
20492049{
20502050   // INIT = current task == KWD and WDINIT
20512051   UINT16 r = (m_task == task_kwd && m_dsk.wdinit0) ? 037 : 0;
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20762076 *  1  1  |  3
20772077 * </PRE>
20782078 */
2079void alto2_cpu_device::f2_rwc_1()
2079void alto2_cpu_device::f2_late_rwc()
20802080{
20812081   static UINT16 branch_map[4] = {0,2,3,3};
20822082   UINT16 r = branch_map[m_dsk.krwc];;
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21192119 * </PRE>
21202120 * NB: The map isn't needed, because m_dsk.krecno counts exactly this way.
21212121 */
2122void alto2_cpu_device::f2_recno_1()
2122void alto2_cpu_device::f2_late_recno()
21232123{
21242124   UINT16 r = m_dsk.krecno;
21252125   UINT16 init = (m_task == task_kwd && m_dsk.wdinit0) ? 037 : 0;
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21332133 *
21342134 * NEXT ← NEXT OR (if current command wants data transfer ? 1 : 0)
21352135 */
2136void alto2_cpu_device::f2_xfrdat_1()
2136void alto2_cpu_device::f2_late_xfrdat()
21372137{
21382138   UINT16 r = GET_KADR_NOXFER(m_dsk.kadr) ? 0 : 1;
21392139   UINT16 init = (m_task == task_kwd && m_dsk.wdinit0) ? 037 : 0;
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21472147 *
21482148 * NEXT ← NEXT OR (if disk not ready to accept command ? 1 : 0)
21492149 */
2150void alto2_cpu_device::f2_swrnrdy_1()
2150void alto2_cpu_device::f2_late_swrnrdy()
21512151{
21522152   diablo_hd_device* dhd = m_drive[m_dsk.drive];
21532153   UINT16 r = dhd->get_seek_read_write_0();
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21632163 *
21642164 * NEXT ← NEXT OR (if fatal error in latches ? 0 : 1)
21652165 */
2166void alto2_cpu_device::f2_nfer_1()
2166void alto2_cpu_device::f2_late_nfer()
21672167{
21682168   UINT16 r = m_dsk.kfer ? 0 : 1;
21692169   UINT16 init = (m_task == task_kwd && m_dsk.wdinit0) ? 037 : 0;
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21922192 * Rt = 20k, Cext = 0.01µF (=10000pF) => 57960ns (~= 58µs)
21932193 * </PRE>
21942194 */
2195void alto2_cpu_device::f2_strobon_1()
2195void alto2_cpu_device::f2_late_strobon()
21962196{
21972197   UINT16 r = m_dsk.strobe;
21982198   UINT16 init = (m_task == task_kwd && m_dsk.wdinit0) ? 037 : 0;
branches/alto2/src/emu/cpu/alto2/a2dvt.c
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1212/**
1313 * @brief f1_dvt_block early: disable the display word task
1414 */
15void alto2_cpu_device::f1_dvt_block_0()
15void alto2_cpu_device::f1_early_dvt_block()
1616{
1717   m_task_wakeup &= ~(1 << m_task);
1818   LOG((LOG_DVT,2,"   BLOCK %s\n", task_name(m_task)));
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3333 */
3434void alto2_cpu_device::init_dvt(int task)
3535{
36   set_f1(task, f1_block,         &alto2_cpu_device::f1_dvt_block_0, 0);
37   set_f2(task, f2_dvt_evenfield,   0, &alto2_cpu_device::f2_evenfield_1);
36   set_f1(task, f1_block,         &alto2_cpu_device::f1_early_dvt_block, 0);
37   set_f2(task, f2_dvt_evenfield,   0, &alto2_cpu_device::f2_late_evenfield);
3838   m_active_callback[task] = &alto2_cpu_device::activate_dvt;
3939}
4040
branches/alto2/src/emu/cpu/alto2/a2dwt.c
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1212/**
1313 * @brief f1_dwt_block early: block the display word task
1414 */
15void alto2_cpu_device::f1_dwt_block_0()
15void alto2_cpu_device::f1_early_dwt_block()
1616{
1717   m_dsp.dwt_blocks = 1;
1818
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4242
4343void alto2_cpu_device::init_dwt(int task)
4444{
45   set_f1(task, f1_block,         &alto2_cpu_device::f1_dwt_block_0, 0);
45   set_f1(task, f1_block,         &alto2_cpu_device::f1_early_dwt_block, 0);
4646   set_f2(task, f2_dwt_load_ddr,   0, &alto2_cpu_device::f2_dwt_load_ddr_1);
4747}
4848
branches/alto2/src/emu/cpu/alto2/a2disp.c
r26291r26292
2929 * Only two bits of a38 are used:
3030 *    O1 (002) = STOPWAKE'
3131 *    O3 (010) = MBEMPTY'
32 *
33 * This dump is from PROM displ.a38:
34 * 0000: 003,013,015,013,015,013,017,013,015,013,017,013,015,013,017,013,
35 * 0020: 013,003,013,015,013,015,013,017,013,015,013,017,013,015,013,017,
36 * 0040: 013,015,003,013,013,017,015,013,013,017,015,013,013,017,015,013,
37 * 0060: 015,013,013,003,017,013,013,015,017,013,013,015,017,013,013,015,
38 * 0100: 013,017,015,013,003,013,015,013,013,017,015,013,015,013,017,013,
39 * 0120: 017,013,013,015,013,003,013,015,017,013,013,015,013,015,013,017,
40 * 0140: 013,015,013,017,013,015,003,013,013,015,013,017,013,017,015,013,
41 * 0160: 015,013,017,013,015,013,013,003,015,013,017,013,017,013,013,015,
42 * 0200: 013,017,015,013,015,013,017,013,003,013,015,013,015,013,017,013,
43 * 0220: 017,013,013,015,013,015,013,017,013,003,013,015,013,015,013,017,
44 * 0240: 013,015,013,017,013,017,015,013,013,015,003,013,013,017,015,013,
45 * 0260: 015,013,017,013,017,013,013,015,015,013,013,003,017,013,013,015,
46 * 0300: 013,017,015,013,013,017,015,013,013,017,015,013,003,013,015,013,
47 * 0320: 017,013,013,015,017,013,013,015,017,013,013,015,013,003,013,015,
48 * 0340: 013,015,013,017,013,015,013,017,013,015,013,017,013,015,003,013,
49 * 0360: 015,013,017,013,015,013,017,013,015,013,017,013,015,013,013,003
5032 * </PRE>
5133 */
5234
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7557 *
7658 * The display_state_machine() is called at a rate of pixelclock/24.
7759 *
78 * This dump is from PROM displ.a63:
79 * 0000: 0007,0013,0015,0021,0024,0030,0034,0040,
80 * 0010: 0044,0050,0054,0060,0064,0070,0074,0200,
81 * 0020: 0004,0010,0014,0020,0024,0030,0034,0040,
82 * 0030: 0044,0050,0054,0060,0064,0070,0175,0203
83 *
8460 * Decoded states of this PROM:
8561 *
8662 *  STATE  PROM   binary   HBLANK  HSYNC NEXT SCANEND HLCGATE
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130106 * Q2 is VSYNC for the even field (with H1024=1)
131107 * Q3 is VBLANK for the odd field (with H1024=0)
132108 * Q4 is VBLANK for the even field (with H1024=1)
133 *
134 * This dump is from PROM displ.a66:
135 * 0000: 013,013,013,013,013,012,012,012,012,012,012,012,012,013,013,013,
136 * 0020: 013,013,013,013,013,013,013,013,013,013,013,013,013,013,013,013,
137 * 0040: 013,013,013,013,013,013,013,013,013,013,013,013,013,013,013,013,
138 * 0060: 013,013,013,013,013,013,013,013,013,013,013,013,013,013,013,013,
139 * 0100: 013,013,013,013,017,017,017,017,017,017,017,017,017,017,017,017,
140 * 0120: 017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,
141 * 0140: 017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,
142 * 0160: 017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,
143 * 0200: 017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,
144 * 0220: 017,017,017,017,017,017,007,007,007,007,005,005,005,005,005,005,
145 * 0240: 005,005,007,007,007,007,007,007,007,007,007,007,007,007,007,007,
146 * 0260: 007,007,007,007,007,007,007,007,007,007,007,007,007,007,007,007,
147 * 0300: 007,007,007,007,007,007,007,007,007,007,007,007,007,007,007,007,
148 * 0320: 007,007,007,007,007,007,007,007,017,017,017,017,017,017,017,017,
149 * 0340: 017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,
150 * 0360: 017,017,017,017,017,017,017,017,017,017,017,017,017,017,017,017
151109 * </PRE>
152110 */
153111
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358316
359317   if (A66_VBLANK_HI(a66, HLC1024)) {
360318      /* VBLANK: remember hlc */
361      m_dsp.vblank = m_dsp.hlc | HLC1024;
319      m_dsp.vblank = m_dsp.hlc & ~1;
362320
363321      LOG((LOG_DISPL,1, " VBLANK"));
364322
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475433 *
476434 * NEXT(09) = even field ? 1 : 0
477435 */
478void alto2_cpu_device::f2_evenfield_1()
436void alto2_cpu_device::f2_late_evenfield()
479437{
480438   UINT16 r = HLC1024 ^ 1;
481439   LOG((LOG_DISPL,2,"   evenfield branch on HLC1024 (%#o | %#o)\n", m_next2, r));
branches/alto2/src/emu/cpu/alto2/a2mrt.c
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1010#include "alto2cpu.h"
1111
1212//! f1_mrt_block early: block the display word task
13void alto2_cpu_device::f1_mrt_block_0()
13void alto2_cpu_device::f1_early_mrt_block()
1414{
1515   /* clear the wakeup for the memory refresh task */
1616   m_task_wakeup &= ~(1 << m_task);
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2727 //! memory refresh task slots initialization
2828void alto2_cpu_device::init_mrt(int task)
2929{
30   set_f1(task, f1_block,      &alto2_cpu_device::f1_mrt_block_0, 0);
30   set_f1(task, f1_block,      &alto2_cpu_device::f1_early_mrt_block, 0);
3131   /* auto block */
3232   m_active_callback[task] = &alto2_cpu_device::activate_mrt;
3333}
branches/alto2/src/emu/cpu/alto2/alto2cpu.c
r26291r26292
16791679/**
16801680 * @brief bs_read_r early: drive bus by R register
16811681 */
1682void alto2_cpu_device::bs_read_r_0()
1682void alto2_cpu_device::bs_early_read_r()
16831683{
16841684   UINT16 r = m_r[m_rsel];
16851685   LOG((LOG_CPU,2,"   ←R%02o; %s (%#o)\n", m_rsel, r_name(m_rsel), r));
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16891689/**
16901690 * @brief bs_load_r early: load R places 0 on the BUS
16911691 */
1692void alto2_cpu_device::bs_load_r_0()
1692void alto2_cpu_device::bs_early_load_r()
16931693{
16941694   UINT16 r = 0;
16951695   LOG((LOG_CPU,2,"   R%02o←; %s (BUS&=0)\n", m_rsel, r_name(m_rsel)));
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16991699/**
17001700 * @brief bs_load_r late: load R from SHIFTER
17011701 */
1702void alto2_cpu_device::bs_load_r_1()
1702void alto2_cpu_device::bs_late_load_r()
17031703{
17041704   if (MIR_F2(m_mir) != f2_emu_load_dns) {
17051705      m_r[m_rsel] = m_shifter;
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17191719/**
17201720 * @brief bs_read_md early: drive BUS from read memory data
17211721 */
1722void alto2_cpu_device::bs_read_md_0()
1722void alto2_cpu_device::bs_early_read_md()
17231723{
17241724#if   ALTO2_DEBUG
17251725   UINT32 mar = m_mem.mar;
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17321732/**
17331733 * @brief bs_mouse early: drive bus by mouse
17341734 */
1735void alto2_cpu_device::bs_mouse_0()
1735void alto2_cpu_device::bs_early_mouse()
17361736{
17371737   UINT16 r = mouse_read();
17381738   LOG((LOG_CPU,2,"   ←MOUSE; BUS&=MOUSE (%#o)\n", r));
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17421742/**
17431743 * @brief bs_disp early: drive bus by displacement (which?)
17441744 */
1745void alto2_cpu_device::bs_disp_0()
1745void alto2_cpu_device::bs_early_disp()
17461746{
17471747   UINT16 r = 0177777;
17481748   LOG((LOG_CPU,0,"BS ←DISP not handled by task %s mpc:%04x\n", task_name(m_task), m_mpc));
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17561756 * Load memory address register from the ALU output;
17571757 * start main memory reference (see section 2.3).
17581758 */
1759void alto2_cpu_device::f1_load_mar_1()
1759void alto2_cpu_device::f1_late_load_mar()
17601760{
17611761   UINT8 bank = m_bank_reg[m_task];
17621762   UINT32 msb;
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19661966 * 0 (GND)         10 I0   Q2:1 Q1:1 Q0:1 GS:0 EO:1  x    x    x    x
19671967 * </PRE>
19681968 */
1969void alto2_cpu_device::f1_task_0()
1969void alto2_cpu_device::f1_early_task()
19701970{
19711971#if   USE_PRIO_F9318
19721972   /* Doesn't work yet */
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20352035      LOG((LOG_CPU,2, "      no switch\n"));
20362036   }
20372037#else   /* USE_PRIO_F9318 */
2038   int i;
2039
20402038   LOG((LOG_CPU,2, "   TASK %02o:%s", m_task, task_name(m_task)));
2041   for (i = 15; i >= 0; i--) {
2039   for (int i = 15; i >= 0; i--) {
20422040      if (m_task_wakeup & (1 << i)) {
20432041         m_next2_task = i;
20442042         if (m_next2_task != m_next_task) {
r26291r26292
20662064}
20672065#endif
20682066
2067void alto2_cpu_device::f1_late_l_lsh_1()
2068{
2069#if   0
2070   if (m_task == task_emu) {
2071      if (f2 == f2_emu_magic) {
2072         m_shifter = ((m_l << 1) | (m_t >> 15)) & 0177777;
2073         LOG((LOG_CPU,2,"   SHIFTER ←L MLSH 1 (%#o := %#o<<1|%#o)\n", m_shifter, m_l, m_t >> 15));
2074      }
2075      if (f2 == f2_emu_load_dns) {
2076         /* shifter is done in F2 */
2077         break;
2078      }
2079   }
2080#endif
2081   m_shifter = (m_l << 1) & 0177777;
2082   LOG((LOG_CPU,2,"   SHIFTER ←L LSH 1 (%#o := %#o<<1)\n", m_shifter, m_l));
2083}
2084
2085void alto2_cpu_device::f1_late_l_rsh_1()
2086{
2087#if   0
2088   if (m_task == task_emu) {
2089      if (f2 == f2_emu_magic) {
2090         m_shifter = ((m_l >> 1) | (m_t << 15)) & 0177777;
2091         LOG((LOG_CPU,2,"   SHIFTER ←L MRSH 1 (%#o := %#o>>1|%#o)\n", m_shifter, m_l, (m_t << 15) & 0100000));
2092         break;
2093      }
2094      if (f2 == f2_emu_load_dns) {
2095         /* shifter is done in F2 */
2096         break;
2097      }
2098   }
2099#endif
2100   m_shifter = m_l >> 1;
2101   LOG((LOG_CPU,2,"   SHIFTER ←L RSH 1 (%#o := %#o>>1)\n", m_shifter, m_l));
2102}
2103
2104void alto2_cpu_device::f1_late_l_lcy_8()
2105{
2106   m_shifter = ((m_l >> 8) | (m_l << 8)) & 0177777;
2107   LOG((LOG_CPU,2,"   SHIFTER ←L LCY 8 (%#o := bswap %#o)\n", m_shifter, m_l));
2108}
2109
20692110/**
20702111 * @brief f2_bus_eq_zero late: branch on bus equals zero
20712112 */
2072void alto2_cpu_device::f2_bus_eq_zero_1()
2113void alto2_cpu_device::f2_late_bus_eq_zero()
20732114{
20742115   UINT16 r = m_bus == 0 ? 1 : 0;
20752116   LOG((LOG_CPU,2, "   BUS=0; %sbranch (%#o|%#o)\n", r ? "" : "no ", m_next2, r));
r26291r26292
20792120/**
20802121 * @brief f2_shifter_lt_zero late: branch on shifter less than zero
20812122 */
2082void alto2_cpu_device::f2_shifter_lt_zero_1()
2123void alto2_cpu_device::f2_late_shifter_lt_zero()
20832124{
20842125   UINT16 r = (m_shifter & 0100000) ? 1 : 0;
20852126   LOG((LOG_CPU,2, "   SH<0; %sbranch (%#o|%#o)\n", r ? "" : "no ", m_next2, r));
r26291r26292
20892130/**
20902131 * @brief f2_shifter_eq_zero late: branch on shifter equals zero
20912132 */
2092void alto2_cpu_device::f2_shifter_eq_zero_1()
2133void alto2_cpu_device::f2_late_shifter_eq_zero()
20932134{
20942135   UINT16 r = m_shifter == 0 ? 1 : 0;
20952136   LOG((LOG_CPU,2, "   SH=0; %sbranch (%#o|%#o)\n", r ? "" : "no ", m_next2, r));
r26291r26292
20992140/**
21002141 * @brief f2_bus late: branch on bus bits BUS[6-15]
21012142 */
2102void alto2_cpu_device::f2_bus_1()
2143void alto2_cpu_device::f2_late_bus()
21032144{
21042145   UINT16 r = A2_GET16(m_bus,16,6,15);
21052146   LOG((LOG_CPU,2, "   BUS; %sbranch (%#o|%#o)\n", r ? "" : "no ", m_next2, r));
r26291r26292
21092150/**
21102151 * @brief f2_alucy late: branch on latched ALU carry
21112152 */
2112void alto2_cpu_device::f2_alucy_1()
2153void alto2_cpu_device::f2_late_alucy()
21132154{
21142155   UINT16 r = m_laluc0;
21152156   LOG((LOG_CPU,2, "   ALUCY; %sbranch (%#o|%#o)\n", r ? "" : "no ", m_next2, r));
r26291r26292
21212162 *
21222163 * Deliver BUS data to memory.
21232164 */
2124void alto2_cpu_device::f2_load_md_1()
2165void alto2_cpu_device::f2_late_load_md()
21252166{
21262167#if   ALTO2_DEBUG
21272168   UINT16 mar = m_mem.mar;
r26291r26292
26942735         rdram();
26952736
26962737      /*
2697       * The constant memory is gated to the bus by F1 = 7, F2 = 7, or BS >= 4
2738       * The constant memory is gated to the bus by F1 == f1_const, F2 == f2_const, or BS >= 4
26982739       */
2699      if (!do_bs || bs >= 4) {
2740      if (!do_bs || bs >= bs_task_4) {
27002741         int addr = 8 * m_rsel + bs;
2701         // There is something going wrong with using:
2702         // m_const->read_word(m_const->address_to_byte(addr));
2703         // because for addr=0160 it returns const[0161] instead of const[0160]
2704         // For now fall back to reading the const data from the byte array
27052742         UINT16 data = m_const_data[2*addr+0] | (m_const_data[2*addr+1] << 8);
27062743         m_bus &= data;
27072744         LOG((LOG_CPU,2,"   %#o; BUS &= %#o CONST[%03o]\n", m_bus, data, addr));
r26291r26292
27092746
27102747      /*
27112748       * early f2 has to be done before early bs, because the
2712       * emulator f2 acsource or acdest may change rsel
2749       * emulator f2 acsource or acdest may change m_rsel
27132750       */
27142751      ((*this).*m_f2[0][m_task][f2])();
27152752
r26291r26292
29552992      if (m_wrtram_flag)
29562993         wrtram();
29572994
2958      switch (f1) {
2959      case f1_l_lsh_1:
2960         if (m_task == task_emu) {
2961            if (f2 == f2_emu_magic) {
2962               m_shifter = ((m_l << 1) | (m_t >> 15)) & 0177777;
2963               LOG((LOG_CPU,2,"   SHIFTER ←L MLSH 1 (%#o := %#o<<1|%#o)\n", m_shifter, m_l, m_t >> 15));
2964               break;
2965            }
2966            if (f2 == f2_emu_load_dns) {
2967               /* shifter is done in F2 */
2968               break;
2969            }
2970         }
2971         m_shifter = (m_l << 1) & 0177777;
2972         LOG((LOG_CPU,2,"   SHIFTER ←L LSH 1 (%#o := %#o<<1)\n", m_shifter, m_l));
2973         break;
2995      // shifter passes L, if F1 is not one of L LSH 1, L RSH 1 or L LCY 8
2996      m_shifter = m_l;
29742997
2975      case f1_l_rsh_1:
2976         if (m_task == task_emu) {
2977            if (f2 == f2_emu_magic) {
2978               m_shifter = ((m_l >> 1) | (m_t << 15)) & 0177777;
2979               LOG((LOG_CPU,2,"   SHIFTER ←L MRSH 1 (%#o := %#o>>1|%#o)\n", m_shifter, m_l, (m_t << 15) & 0100000));
2980               break;
2981            }
2982            if (f2 == f2_emu_load_dns) {
2983               /* shifter is done in F2 */
2984               break;
2985            }
2986         }
2987         m_shifter = m_l >> 1;
2988         LOG((LOG_CPU,2,"   SHIFTER ←L RSH 1 (%#o := %#o>>1)\n", m_shifter, m_l));
2989         break;
2990
2991      case f1_l_lcy_8:
2992         m_shifter = ((m_l >> 8) | (m_l << 8)) & 0177777;
2993         LOG((LOG_CPU,2,"   SHIFTER ←L LCY 8 (%#o := bswap %#o)\n", m_shifter, m_l));
2994         break;
2995
2996      default:
2997         /* shifter passes L, if F1 is not one of L LSH 1, L RSH 1 or L LCY 8 */
2998         m_shifter = m_l;
2999      }
3000
3001      /* late F1 is done now, if any */
2998      /* late F1 is done now */
30022999      ((*this).*m_f1[1][m_task][f1])();
30033000
3004      /* late F2 is done now, if any */
3001      /* late F2 is done now */
30053002      ((*this).*m_f2[1][m_task][f2])();
30063003
30073004      /* late BS is done now, if no constant was put on the bus */
30083005      if (do_bs)
30093006         ((*this).*m_bs[1][m_task][bs])();
30103007
3011      /*
3012       * update L register and LALUC0, and also M register,
3013       * if a RAM related task is active
3014       */
3008      // update L register and LALUC0, and also M register, if a RAM related task is active
30153009      if (MIR_L(m_mir)) {
3016         /* load L from ALU */
3017         m_l = m_alu;
3010         m_l = m_alu;         // load L from ALU
30183011         if (flags & ALUM2) {
30193012            m_laluc0 = m_aluc0;
30203013            LOG((LOG_CPU,2, "   L← ALU (%#o); LALUC0← ALUC0 (%o)\n", m_alu, m_aluc0));
r26291r26292
30233016            LOG((LOG_CPU,2, "   L← ALU (%#o); LALUC0← %o\n", m_alu, 0));
30243017         }
30253018         if (m_ram_related[m_task]) {
3026            /* load M from ALU, if 'GOODTASK' */
3027            m_m = m_alu;
3028            /* also writes to S[bank][0], which can't be read */
3029            m_s[m_s_reg_bank[m_task]][0] = m_alu;
3019            m_m = m_alu;      // load M from ALU, if 'GOODTASK'
3020            m_s[m_s_reg_bank[m_task]][0] = m_alu;   // also writes to S[bank][0], which can't be read
30303021            LOG((LOG_CPU,2, "   M← ALU (%#o)\n", m_alu));
30313022         }
30323023      }
30333024
3034      /* update T register, if LOADT is set */
3025      // update T register, if LOADT is set
30353026      if (MIR_T(m_mir)) {
30363027         m_cram_addr = m_alu;
30373028         if (flags & TSELECT) {
3029            m_t = m_alu;      // T source is ALU
30383030            LOG((LOG_CPU,2, "   T← ALU (%#o)\n", m_alu));
3039            m_t = m_alu;
30403031         } else {
3032            m_t = m_bus;      // T source is BUS
30413033            LOG((LOG_CPU,2, "   T← BUS (%#o)\n", m_bus));
3042            m_t = m_bus;
30433034         }
30443035      }
30453036
r26291r26292
30493040            /* one more microinstruction */
30503041            m_next_task = m_next2_task;
30513042         } else {
3052            /* save this task's mpc */
3043            /* save this task's mpc and next2 */
30533044            m_task_mpc[m_task] = m_next;
30543045            m_task_next2[m_task] = m_next2;
30553046            m_task = m_next_task;
30563047            LOG((LOG_CPU,1, "task switch to %02o:%s (cycle %lld)\n", m_task, task_name(m_task), cycle()));
3057            /* get new task's mpc */
3058            m_next = m_task_mpc[m_task];
3059            /* get address modifier after task switch (?) */
3060            m_next2 = m_task_next2[m_task];
3048            m_next = m_task_mpc[m_task];   // get new task's mpc
3049            m_next2 = m_task_next2[m_task];   // get address modifier after task switch (needed?)
30613050
3062            /*
3063             * let the task know it becomes active now
3064             * and (most probably) reset the wakeup
3065             */
3051            // let the task know it becomes active now and (most probably) reset the wakeup
30663052            ((*this).*m_active_callback[m_task])();
30673053         }
30683054      }
r26291r26292
30903076      if (0 == (m_reset_mode & (1 << task)))
30913077         m_task_mpc[task] |= ALTO2_UCODE_RAM_BASE;
30923078
3093      set_bs(task, bs_read_r,         &alto2_cpu_device::bs_read_r_0,   0);
3094      set_bs(task, bs_load_r,         &alto2_cpu_device::bs_load_r_0,   &alto2_cpu_device::bs_load_r_1);
3079      set_bs(task, bs_read_r,         &alto2_cpu_device::bs_early_read_r,   0);
3080      set_bs(task, bs_load_r,         &alto2_cpu_device::bs_early_load_r,   &alto2_cpu_device::bs_late_load_r);
30953081      set_bs(task, bs_no_source,      0, 0);
30963082      set_bs(task, bs_task_3,         &alto2_cpu_device::fn_bs_bad_0,   &alto2_cpu_device::fn_bs_bad_1);   // task specific
30973083      set_bs(task, bs_task_4,         &alto2_cpu_device::fn_bs_bad_0,   &alto2_cpu_device::fn_bs_bad_1);   // task specific
3098      set_bs(task, bs_read_md,      &alto2_cpu_device::bs_read_md_0, 0);
3099      set_bs(task, bs_mouse,         &alto2_cpu_device::bs_mouse_0, 0);
3100      set_bs(task, bs_disp,         &alto2_cpu_device::bs_disp_0, 0);
3084      set_bs(task, bs_read_md,      &alto2_cpu_device::bs_early_read_md, 0);
3085      set_bs(task, bs_mouse,         &alto2_cpu_device::bs_early_mouse, 0);
3086      set_bs(task, bs_disp,         &alto2_cpu_device::bs_early_disp, 0);
31013087
31023088      set_f1(task, f1_nop,         0, 0);
3103      set_f1(task, f1_load_mar,      0, &alto2_cpu_device::f1_load_mar_1);
3104      set_f1(task, f1_task,         &alto2_cpu_device::f1_task_0, 0);
3089      set_f1(task, f1_load_mar,      0, &alto2_cpu_device::f1_late_load_mar);
3090      set_f1(task, f1_task,         &alto2_cpu_device::f1_early_task, 0);
31053091      set_f1(task, f1_block,         &alto2_cpu_device::fn_f1_bad_0, &alto2_cpu_device::fn_f1_bad_1);   // not all tasks have the f1_block
3106      set_f1(task, f1_l_lsh_1,      0, 0);         // inlined in execute()
3107      set_f1(task, f1_l_rsh_1,      0, 0);         // inlined in execute()
3108      set_f1(task, f1_l_lcy_8,      0, 0);         // inlined in execute()
3092      set_f1(task, f1_l_lsh_1,      0, &alto2_cpu_device::f1_late_l_lsh_1);
3093      set_f1(task, f1_l_rsh_1,      0, &alto2_cpu_device::f1_late_l_rsh_1);
3094      set_f1(task, f1_l_lcy_8,      0, &alto2_cpu_device::f1_late_l_lcy_8);
31093095      set_f1(task, f1_const,         0, 0);
31103096      set_f1(task, f1_task_10,      &alto2_cpu_device::fn_f1_bad_0,   &alto2_cpu_device::fn_f1_bad_1);   // f1_task_10 to f1_task_17 are task specific
31113097      set_f1(task, f1_task_11,      &alto2_cpu_device::fn_f1_bad_0,   &alto2_cpu_device::fn_f1_bad_1);   // f1_task_10 to f1_task_17 are task specific
r26291r26292
31173103      set_f1(task, f1_task_17,      &alto2_cpu_device::fn_f1_bad_0,   &alto2_cpu_device::fn_f1_bad_1);   // f1_task_10 to f1_task_17 are task specific
31183104
31193105      set_f2(task, f2_nop,         0, 0);
3120      set_f2(task, f2_bus_eq_zero,   0, &alto2_cpu_device::f2_bus_eq_zero_1);
3121      set_f2(task, f2_shifter_lt_zero,0, &alto2_cpu_device::f2_shifter_lt_zero_1);
3122      set_f2(task, f2_shifter_eq_zero,0, &alto2_cpu_device::f2_shifter_eq_zero_1);
3123      set_f2(task, f2_bus,         0, &alto2_cpu_device::f2_bus_1);
3124      set_f2(task, f2_alucy,         0, &alto2_cpu_device::f2_alucy_1);
3125      set_f2(task, f2_load_md,      0, &alto2_cpu_device::f2_load_md_1);
3106      set_f2(task, f2_bus_eq_zero,   0, &alto2_cpu_device::f2_late_bus_eq_zero);
3107      set_f2(task, f2_shifter_lt_zero,0, &alto2_cpu_device::f2_late_shifter_lt_zero);
3108      set_f2(task, f2_shifter_eq_zero,0, &alto2_cpu_device::f2_late_shifter_eq_zero);
3109      set_f2(task, f2_bus,         0, &alto2_cpu_device::f2_late_bus);
3110      set_f2(task, f2_alucy,         0, &alto2_cpu_device::f2_late_alucy);
3111      set_f2(task, f2_load_md,      0, &alto2_cpu_device::f2_late_load_md);
31263112      set_f2(task, f2_const,         0, 0);
31273113      set_f2(task, f2_task_10,      &alto2_cpu_device::fn_f2_bad_0,   &alto2_cpu_device::fn_f2_bad_1);   // f2_task_10 to f2_task_17 are task specific
31283114      set_f2(task, f2_task_11,      &alto2_cpu_device::fn_f2_bad_0,   &alto2_cpu_device::fn_f2_bad_1);   // f2_task_10 to f2_task_17 are task specific
branches/alto2/src/mess/drivers/alto2.c
r26291r26292
206206   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON3) PORT_NAME("Mouse YELLOW (middel)") PORT_CODE(MOUSECODE_BUTTON3) PORT_CHANGED_MEMBER( ":maincpu", alto2_cpu_device, mouse_buttons, 0 )
207207
208208   PORT_START("mousex")   // Mouse - X AXIS
209   PORT_BIT( 0xffff, 0x00, IPT_MOUSE_X) PORT_SENSITIVITY(50) PORT_KEYDELTA(2) PORT_PLAYER(1) PORT_CHANGED_MEMBER( ":maincpu", alto2_cpu_device, mouse_motion_x, 0 )
209   PORT_BIT( 0xffff, 0x00, IPT_LIGHTGUN_X) PORT_SENSITIVITY(50) PORT_KEYDELTA(2) PORT_PLAYER(1) PORT_CHANGED_MEMBER( ":maincpu", alto2_cpu_device, mouse_motion_x, 0 )
210210
211211   PORT_START("mousey")   // Mouse - Y AXIS
212   PORT_BIT( 0xffff, 0x00, IPT_MOUSE_Y) PORT_SENSITIVITY(50) PORT_KEYDELTA(2) PORT_PLAYER(1) PORT_CHANGED_MEMBER( ":maincpu", alto2_cpu_device, mouse_motion_y, 0 )
212   PORT_BIT( 0xffff, 0x00, IPT_LIGHTGUN_Y) PORT_SENSITIVITY(50) PORT_KEYDELTA(2) PORT_PLAYER(1) PORT_CHANGED_MEMBER( ":maincpu", alto2_cpu_device, mouse_motion_y, 0 )
213213
214214PORT_START("CONFIG")    /* config diode on main board */
215215   PORT_CONFNAME( 0x40, 0x40, "TV system")

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