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| r26252 Monday 18th November, 2013 at 03:04:19 UTC by Jürgen Buchmüller |
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| Fix timing based on assumption that the CPU clock is 5.8MHz (divider 5). |
| [/branches/alto2/src/emu/cpu/alto2] | a2disp.c alto2.h |
| [/branches/alto2/src/mess/drivers] | alto2.c |
| r26251 | r26252 | |
|---|---|---|
| 502 | 502 | for (int y = 0; y < ALTO2_DISPLAY_HEIGHT; y++) { |
| 503 | 503 | UINT16* scanline = m_dsp.raw_bitmap + y * ALTO2_DISPLAY_SCANLINE_WORDS; |
| 504 | 504 | m_dsp.scanline[y] = scanline; |
| 505 | memset(m_dsp.scanline[y], y & 1 ? 0x55 : 0xaa, sizeof(UINT16) * ALTO2_DISPLAY_VISIBLE_WORDS); | |
| 506 | for (int x = 0; x < ALTO2_DISPLAY_SCANLINE_WORDS; x++) | |
| 507 | update_bitmap_word(x*16, y, scanline[x]); | |
| 508 | 505 | } |
| 509 | 506 | } |
| 510 | 507 |
| r26251 | r26252 | |
|---|---|---|
| 35 | 35 | #define ALTO2_BUSSRC 8 //!< 8 bus sources |
| 36 | 36 | #define ALTO2_F1MAX 16 //!< 16 F1 functions |
| 37 | 37 | #define ALTO2_F2MAX 16 //!< 16 F2 functions |
| 38 | #define ALTO2_UCYCLE 1 | |
| 38 | #define ALTO2_UCYCLE 169 //!< time in nano seconds for a CPU micro cycle: 29.4912MHz/5 -> 5.898240Hz ~= 169.542ns/clock | |
| 39 | 39 | |
| 40 | 40 | #define ALTO2_ETHER_FIFO_SIZE 16 |
| 41 | 41 |
| r26251 | r26252 | |
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| 256 | 256 | |
| 257 | 257 | static MACHINE_CONFIG_START( alto2, alto2_state ) |
| 258 | 258 | /* basic machine hardware */ |
| 259 | // SYSCLK is Display Control part A51 (tagged 29.4MHz) divided by 8 | |
| 260 | MCFG_CPU_ADD("maincpu", ALTO2, XTAL_29_4912MHz/8) | |
| 259 | // SYSCLK is Display Control part A51 (tagged 29.4MHz) divided by 5(?) | |
| 260 | // 5.8MHz according to de.wikipedia.org/wiki/Xerox_Alto | |
| 261 | MCFG_CPU_ADD("maincpu", ALTO2, XTAL_29_4912MHz/5) | |
| 261 | 262 | MCFG_CPU_PROGRAM_MAP(alto2_ucode_map) |
| 262 | 263 | MCFG_CPU_DATA_MAP(alto2_const_map) |
| 263 | 264 | MCFG_CPU_IO_MAP(alto2_iomem_map) |
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