trunk/src/emu/machine/z80dma.c
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| 123 | 123 | #define EOB_F_CLEAR (m_status |= 0x20) |
| 124 | 124 | |
| 125 | 125 | #define READY_ACTIVE_HIGH ((WR5>>3) & 0x01) |
| 126 | #define AUTO_RESTART ((WR5>>5) & 0x01) |
| 126 | 127 | |
| 127 | 128 | #define INTERRUPT_ENABLE (WR3 & 0x20) |
| 128 | 129 | #define INT_ON_MATCH (INTERRUPT_CTRL & 0x01) |
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| 292 | 293 | // set interrupt under service flag |
| 293 | 294 | m_ius = 1; |
| 294 | 295 | |
| 295 | | // disable DMA |
| 296 | | m_dma_enabled = 0; |
| 297 | | |
| 298 | 296 | return m_vector; |
| 299 | 297 | } |
| 300 | 298 | |
| 301 | | logerror("z80dma_irq_ack: failed to find an interrupt to ack!\n"); |
| 299 | //logerror("z80dma_irq_ack: failed to find an interrupt to ack!\n"); |
| 302 | 300 | |
| 303 | 301 | return 0; |
| 304 | 302 | } |
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| 322 | 320 | return; |
| 323 | 321 | } |
| 324 | 322 | |
| 325 | | logerror("z80dma_irq_reti: failed to find an interrupt to clear IEO on!\n"); |
| 323 | //logerror("z80dma_irq_reti: failed to find an interrupt to clear IEO on!\n"); |
| 326 | 324 | } |
| 327 | 325 | |
| 328 | 326 | |
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| 550 | 548 | { |
| 551 | 549 | trigger_interrupt(INT_END_OF_BLOCK); |
| 552 | 550 | } |
| 551 | |
| 552 | if (AUTO_RESTART) |
| 553 | { |
| 554 | if (LOG) logerror("Z80DMA '%s' Auto Restart\n", tag()); |
| 555 | |
| 556 | m_dma_enabled = 1; |
| 557 | m_addressA = PORTA_ADDRESS; |
| 558 | m_addressB = PORTB_ADDRESS; |
| 559 | m_count = BLOCKLEN; |
| 560 | m_status |= 0x30; |
| 561 | } |
| 553 | 562 | } |
| 554 | 563 | } |
| 555 | 564 | |
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| 626 | 635 | |
| 627 | 636 | void z80dma_device::write(UINT8 data) |
| 628 | 637 | { |
| 629 | | if (LOG) logerror("Z80DMA '%s' Write %02x\n", tag(), data); |
| 630 | | |
| 631 | 638 | if (m_num_follow == 0) |
| 632 | 639 | { |
| 633 | 640 | m_reset_pointer = 0; |
| 634 | 641 | |
| 635 | 642 | if ((data & 0x87) == 0) // WR2 |
| 636 | 643 | { |
| 644 | if (LOG) logerror("Z80DMA '%s' WR2 %02x\n", tag(), data); |
| 637 | 645 | WR2 = data; |
| 638 | 646 | if (data & 0x40) |
| 639 | 647 | m_regs_follow[m_num_follow++] = GET_REGNUM(PORTB_TIMING); |
| 640 | 648 | } |
| 641 | 649 | else if ((data & 0x87) == 0x04) // WR1 |
| 642 | 650 | { |
| 651 | if (LOG) logerror("Z80DMA '%s' WR1 %02x\n", tag(), data); |
| 643 | 652 | WR1 = data; |
| 644 | 653 | if (data & 0x40) |
| 645 | 654 | m_regs_follow[m_num_follow++] = GET_REGNUM(PORTA_TIMING); |
| 646 | 655 | } |
| 647 | 656 | else if ((data & 0x80) == 0) // WR0 |
| 648 | 657 | { |
| 658 | if (LOG) logerror("Z80DMA '%s' WR0 %02x\n", tag(), data); |
| 649 | 659 | WR0 = data; |
| 650 | 660 | if (data & 0x08) |
| 651 | 661 | m_regs_follow[m_num_follow++] = GET_REGNUM(PORTA_ADDRESS_L); |
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| 658 | 668 | } |
| 659 | 669 | else if ((data & 0x83) == 0x80) // WR3 |
| 660 | 670 | { |
| 671 | if (LOG) logerror("Z80DMA '%s' WR3 %02x\n", tag(), data); |
| 661 | 672 | WR3 = data; |
| 662 | 673 | if (data & 0x08) |
| 663 | 674 | m_regs_follow[m_num_follow++] = GET_REGNUM(MASK_BYTE); |
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| 666 | 677 | } |
| 667 | 678 | else if ((data & 0x83) == 0x81) // WR4 |
| 668 | 679 | { |
| 680 | if (LOG) logerror("Z80DMA '%s' WR4 %02x\n", tag(), data); |
| 669 | 681 | WR4 = data; |
| 670 | 682 | if (data & 0x04) |
| 671 | 683 | m_regs_follow[m_num_follow++] = GET_REGNUM(PORTB_ADDRESS_L); |
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| 676 | 688 | } |
| 677 | 689 | else if ((data & 0xC7) == 0x82) // WR5 |
| 678 | 690 | { |
| 691 | if (LOG) logerror("Z80DMA '%s' WR5 %02x\n", tag(), data); |
| 679 | 692 | WR5 = data; |
| 680 | 693 | } |
| 681 | 694 | else if ((data & 0x83) == 0x83) // WR6 |
| 682 | 695 | { |
| 696 | if (LOG) logerror("Z80DMA '%s' WR6 %02x\n", tag(), data); |
| 683 | 697 | m_dma_enabled = 0; |
| 684 | 698 | |
| 685 | 699 | WR6 = data; |
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| 802 | 816 | } |
| 803 | 817 | else |
| 804 | 818 | { |
| 819 | if (LOG) logerror("Z80DMA '%s' Write %02x\n", tag(), data); |
| 820 | |
| 805 | 821 | int nreg = m_regs_follow[m_cur_follow]; |
| 806 | 822 | m_regs[nreg] = data; |
| 807 | 823 | m_cur_follow++; |