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r26087 Sunday 10th November, 2013 at 10:04:56 UTC by Jürgen Buchmüller
Using cpu_device::memory_write(...) doesn't work either. This is frustrating to the point where I give up.

[/branches/alto2/src/emu/cpu/alto2]

alto2.c alto2.h

branches/alto2/src/emu/cpu/alto2/alto2.c

r26086	r26087
121	121	m_cram3k_a37(0),
122	122	m_madr_a64(0),
123	123	m_madr_a65(0),
	124	m_madr_a90(0),
	125	m_madr_a91(0),
124	126	m_bs(),
125	127	m_f1(),
126	128	m_f2(),
r26086	r26087
211	213	ROM_REGION( 0400, "2kctl_u76", 0 )
212	214	ROM_LOAD( "2kctl.u76",  00000, 00400, CRC(1edef867) SHA1(928b8a15ac515a99109f32672441832173883b81) )   //!< 3601-1 256x4 BPROM; 2KCTL replacement for u51 (1KCTL)
213	215
214		ROM_REGION( 0400, "alu_a10", 0 )
	216	ROM_REGION( 0040, "alu_a10", 0 )
215	217	ROM_LOAD( "alu.a10",    00000, 00040, CRC(e0857892) SHA1(dcd389767139f0acc1f87cf074459115abc5b90b) )
216	218
217	219	ROM_REGION( 0400, "3kcram_a37", 0 )
r26086	r26087
572	574	}
573	575	};
574	576
575		//-------------------------------------------------
576		//  device_start - device-specific startup
577		//-------------------------------------------------
	577	//! 82S23 32x8 BPROM; display HBLANK, HSYNC, SCANEND, HLCGATE ...
	578	static const prom_load_t pl_displ_a63 =
	579	{
	580	"displ.a63",
	581	0,
	582	"82a20d60",
	583	"39d90703568be5419ada950e112d99227873fdea",
	584	/* size */   0040,
	585	/* amap */   AMAP_DEFAULT,
	586	/* axor */   0,
	587	/* dxor */   0,
	588	/* width */   8,
	589	/* shift */   0,
	590	/* dmap */   DMAP_DEFAULT,
	591	/* dand */   ZERO,
	592	/* type */   sizeof(UINT8)
	593	};
578	594
579		// FIXME
580		void alto2_cpu_device::device_start()
	595	//! P3601 256x4 BPROM; display FIFO control: STOPWAKE, MBEMPTY
	596	static const prom_load_t pl_displ_a38 =
581	597	{
582		m_ucode = &space(AS_PROGRAM);
583		m_const = &space(AS_DATA);
	598	"displ.a38",
	599	0,
	600	"fd30beb7",
	601	"65e4a19ba4ff748d525122128c514abedd55d866",
	602	/* size */   0400,
	603	/* amap */   AMAP_REVERSE_0_7,         // reverse address lines A0-A7
	604	/* axor */   0,
	605	/* dxor */   0,
	606	/* width */   4,
	607	/* shift */   0,
	608	/* dmap */   DMAP_DEFAULT,
	609	/* dand */   ZERO,
	610	/* type */   sizeof(UINT8)
	611	};
584	612
585		m_ucode_proms = prom_load(ucode_prom_list, memregion("ucode_proms")->base(), ALTO2_UCODE_ROM_PAGES, 8);
586		m_const_proms = prom_load(const_prom_list, memregion("const_proms")->base(), 1, 4);
	613	//! P3601 256x4 BPROM; display VSYNC and VBLANK
	614	static const prom_load_t pl_displ_a66 =
	615	{
	616	"displ.a66",
	617	0,
	618	"9f91aad9",
	619	"69b1d4c71f4e18103112e8601850c2654e9265cf",
	620	/* size */   0400,
	621	/* amap */   AMAP_DEFAULT,
	622	/* axor */   0,
	623	/* dxor */   0,
	624	/* width */   4,
	625	/* shift */   0,
	626	/* dmap */   DMAP_DEFAULT,
	627	/* dand */   ZERO,
	628	/* type */   sizeof(UINT8)
	629	};
587	630
588		//! P3601 256x4 BPROM; display FIFO control: STOPWAKE, MBEMPTY
589		static const prom_load_t pl_displ_a38 =
590		{
591		"displ.a38",
592		0,
593		"fd30beb7",
594		"65e4a19ba4ff748d525122128c514abedd55d866",
595		/* size */   0400,
596		/* amap */   AMAP_REVERSE_0_7,         // reverse address lines A0-A7
597		/* axor */   0,
598		/* dxor */   0,
599		/* width */   4,
600		/* shift */   0,
601		/* dmap */   DMAP_DEFAULT,
602		/* dand */   ZERO,
603		/* type */   sizeof(UINT8)
604		};
605		m_disp_a38 = prom_load(&pl_displ_a38, memregion("displ_a38")->base(), 1, 1);
	631	//! 3601-1 256x4 BPROM; Emulator address modifier
	632	static const prom_load_t pl_2kctl_u3 =
	633	{
	634	"2kctl.u3",
	635	0,
	636	"5f8d89e8",
	637	"487cd944ab074290aea73425e81ef4900d92e250",
	638	/* size */   0400,
	639	/* amap */   AMAP_REVERSE_0_7,         // reverse address lines A0-A7
	640	/* axor */   0377,                  // invert address lines A0-A7
	641	/* dxor */   017,                  // invert data lines D0-D3
	642	/* width */   4,
	643	/* shift */   0,
	644	/* dmap */   DMAP_DEFAULT,
	645	/* dand */   ZERO,
	646	/* type */   sizeof(UINT8)
	647	};
606	648
607		//! 82S23 32x8 BPROM; display HBLANK, HSYNC, SCANEND, HLCGATE ...
608		static const prom_load_t pl_displ_a63 =
609		{
610		"displ.a63",
611		0,
612		"82a20d60",
613		"39d90703568be5419ada950e112d99227873fdea",
614		/* size */   0040,
615		/* amap */   AMAP_DEFAULT,
616		/* axor */   0,
617		/* dxor */   0,
618		/* width */   8,
619		/* shift */   0,
620		/* dmap */   DMAP_DEFAULT,
621		/* dand */   ZERO,
622		/* type */   sizeof(UINT8)
623		};
624		m_disp_a63 = prom_load(&pl_displ_a63, memregion("displ_a63")->base(), 1, 1);
	649	//! 82S23 32x8 BPROM; task priority and initial address
	650	static const prom_load_t pl_2kctl_u38 =
	651	{
	652	"2kctl.u38",
	653	0,
	654	"fc51b1d1",
	655	"e36c2a12a5da377394264899b5ae504e2ffda46e",
	656	/* size */   0040,
	657	/* amap */   AMAP_DEFAULT,
	658	/* axor */   0,
	659	/* dxor */   0,
	660	/* width */   8,
	661	/* shift */   0,
	662	/* dmap */   DMAP_DEFAULT,
	663	/* dand */   ZERO,
	664	/* type */   sizeof(UINT8)
	665	};
625	666
626		//! P3601 256x4 BPROM; display VSYNC and VBLANK
627		static const prom_load_t pl_displ_a66 =
628		{
629		"displ.a66",
630		0,
631		"9f91aad9",
632		"69b1d4c71f4e18103112e8601850c2654e9265cf",
633		/* size */   0400,
634		/* amap */   AMAP_DEFAULT,
635		/* axor */   0,
636		/* dxor */   0,
637		/* width */   4,
638		/* shift */   0,
639		/* dmap */   DMAP_DEFAULT,
640		/* dand */   ZERO,
641		/* type */   sizeof(UINT8)
642		};
643		m_disp_a66 = prom_load(&pl_displ_a66, memregion("displ_a66")->base(), 1, 1);
	667	//! 3601-1 256x4 BPROM; 2KCTL replacement for u51 (1KCTL)
	668	static const prom_load_t pl_2kctl_u76 =
	669	{
	670	"2kctl.u76",
	671	0,
	672	"1edef867",
	673	"928b8a15ac515a99109f32672441832173883b81",
	674	/* size */   0400,
	675	/* amap */   AMAP_DEFAULT,
	676	/* axor */   0077,                  // invert address lines A0-A5
	677	/* dxor */   0,
	678	/* width */   4,
	679	/* shift */   0,
	680	/* dmap */   DMAP_DEFAULT,
	681	/* dand */   ZERO,
	682	/* type */   sizeof(UINT8)
	683	};
644	684
645		//! 3601-1 256x4 BPROM; Emulator address modifier
646		static const prom_load_t pl_2kctl_u3 =
647		{
648		"2kctl.u3",
649		0,
650		"5f8d89e8",
651		"487cd944ab074290aea73425e81ef4900d92e250",
652		/* size */   0400,
653		/* amap */   AMAP_REVERSE_0_7,         // reverse address lines A0-A7
654		/* axor */   0377,                  // invert address lines A0-A7
655		/* dxor */   017,                  // invert data lines D0-D3
656		/* width */   4,
657		/* shift */   0,
658		/* dmap */   DMAP_DEFAULT,
659		/* dand */   ZERO,
660		/* type */   sizeof(UINT8)
661		};
662		m_ctl2k_u3 = prom_load(&pl_2kctl_u3, memregion("2kctl_u3")->base(), 1, 1);
	685	//! ALUF to ALU 741818 functions and carry in mapper
	686	static const prom_load_t pl_alu_a10 =
	687	{
	688	"alu.a10",
	689	0,
	690	"e0857892",
	691	"dcd389767139f0acc1f87cf074459115abc5b90b",
	692	/* size */   0040,
	693	/* amap */   AMAP_DEFAULT,
	694	/* axor */   0,
	695	/* dxor */   0,
	696	/* width */   4,
	697	/* shift */   0,
	698	/* dmap */   DMAP_DEFAULT,
	699	/* dand */   ZERO,
	700	/* type */   sizeof(UINT8)
	701	};
663	702
664		//! 82S23 32x8 BPROM; task priority and initial address
665		static const prom_load_t pl_2kctl_u38 =
666		{
667		"2kctl.u38",
668		0,
669		"fc51b1d1",
670		"e36c2a12a5da377394264899b5ae504e2ffda46e",
671		/* size */   0040,
672		/* amap */   AMAP_DEFAULT,
673		/* axor */   0,
674		/* dxor */   0,
675		/* width */   8,
676		/* shift */   0,
677		/* dmap */   DMAP_DEFAULT,
678		/* dand */   ZERO,
679		/* type */   sizeof(UINT8)
680		};
681		m_ctl2k_u38 = prom_load(&pl_2kctl_u38, memregion("2kctl_u38")->base(), 1, 1);
	703	static const prom_load_t pl_3kcram_a37 =
	704	{
	705	"3kcram.a37",
	706	0,
	707	"9417360d",
	708	"bfcdbc56ee4ffafd0f2f672c0c869a55d6dd194b",
	709	/* size */   0400,
	710	/* amap */   AMAP_DEFAULT,
	711	/* axor */   0,
	712	/* dxor */   017,                  // invert D0-D3
	713	/* width */   4,
	714	/* shift */   0,
	715	/* dmap */   DMAP_DEFAULT,
	716	/* dand */   ZERO,
	717	/* type */   sizeof(UINT8)
	718	};
682	719
683		//! 3601-1 256x4 BPROM; 2KCTL replacement for u51 (1KCTL)
684		static const prom_load_t pl_2kctl_u76 =
685		{
686		"2kctl.u76",
687		0,
688		"1edef867",
689		"928b8a15ac515a99109f32672441832173883b81",
690		/* size */   0400,
691		/* amap */   AMAP_DEFAULT,
692		/* axor */   0077,                  // invert address lines A0-A5
693		/* dxor */   0,
694		/* width */   4,
695		/* shift */   0,
696		/* dmap */   DMAP_DEFAULT,
697		/* dand */   ZERO,
698		/* type */   sizeof(UINT8)
699		};
700		m_ctl2k_u76 = prom_load(&pl_2kctl_u76, memregion("2kctl_u76")->base(), 1, 1);
	720	static const prom_load_t pl_madr_a32 =
	721	{
	722	"madr.a32",
	723	0,
	724	"a0e3b4a7",
	725	"24e50afdeb637a6a8588f8d3a3493c9188b8da2c",
	726	/* size */   0400,
	727	/* amap */   AMAP_DEFAULT,
	728	/* axor */   0,
	729	/* dxor */   017,                  // invert D0-D3
	730	/* width */   4,
	731	/* shift */   0,
	732	/* dmap */   DMAP_REVERSE_0_3,         // reverse D0-D3 to D3-D0
	733	/* dand */   ZERO,
	734	/* type */   sizeof(UINT8)
	735	};
701	736
702		//! ALUF to ALU 741818 functions and carry in mapper
703		static const prom_load_t pl_alu_a10 =
704		{
705		"alu.a10",
706		0,
707		"e0857892",
708		"dcd389767139f0acc1f87cf074459115abc5b90b",
709		/* size */   0040,
710		/* amap */   AMAP_DEFAULT,
711		/* axor */   0,
712		/* dxor */   0,
713		/* width */   4,
714		/* shift */   0,
715		/* dmap */   DMAP_DEFAULT,
716		/* dand */   ZERO,
717		/* type */   sizeof(UINT8)
718		};
719		m_alu_a10 = prom_load(&pl_alu_a10, memregion("alu_a10")->base(), 1, 1);
	737	static const prom_load_t pl_madr_a64 =
	738	{
	739	"madr.a64",
	740	0,
	741	"a66b0eda",
	742	"4d9088f592caa3299e90966b17765be74e523144",
	743	/* size */   0400,
	744	/* amap */   AMAP_DEFAULT,
	745	/* axor */   0,
	746	/* dxor */   017,                  // invert D0-D3
	747	/* width */   4,
	748	/* shift */   0,
	749	/* dmap */   DMAP_DEFAULT,
	750	/* dand */   ZERO,
	751	/* type */   sizeof(UINT8)
	752	};
720	753
721		static const prom_load_t pl_3kcram_a37 =
722		{
723		"3kcram.a37",
724		0,
725		"9417360d",
726		"bfcdbc56ee4ffafd0f2f672c0c869a55d6dd194b",
727		/* size */   0400,
728		/* amap */   AMAP_DEFAULT,
729		/* axor */   0,
730		/* dxor */   017,                  // invert D0-D3
731		/* width */   4,
732		/* shift */   0,
733		/* dmap */   DMAP_DEFAULT,
734		/* dand */   ZERO,
735		/* type */   sizeof(UINT8)
736		};
737		m_cram3k_a37 = prom_load(&pl_3kcram_a37, memregion("3kcram_a37")->base(), 1, 1);
	754	static const prom_load_t pl_madr_a65 =
	755	{
	756	"madr.a65",
	757	0,
	758	"ba37febd",
	759	"82e9db1cb65f451755295f0d179e6f8fe3349d4d",
	760	/* size */   0400,
	761	/* amap */   AMAP_DEFAULT,
	762	/* axor */   0,
	763	/* dxor */   017,                  // invert D0-D3
	764	/* width */   4,
	765	/* shift */   0,
	766	/* dmap */   DMAP_DEFAULT,
	767	/* dand */   ZERO,
	768	/* type */   sizeof(UINT8)
	769	};
738	770
739		static const prom_load_t pl_madr_a32 =
740		{
741		"madr.a32",
742		0,
743		"a0e3b4a7",
744		"24e50afdeb637a6a8588f8d3a3493c9188b8da2c",
745		/* size */   0400,
746		/* amap */   AMAP_DEFAULT,
747		/* axor */   0,
748		/* dxor */   017,                  // invert D0-D3
749		/* width */   4,
750		/* shift */   0,
751		/* dmap */   DMAP_REVERSE_0_3,         // reverse D0-D3 to D3-D0
752		/* dand */   ZERO,
753		/* type */   sizeof(UINT8)
754		};
	771	static const prom_load_t pl_madr_a90 =
	772	{
	773	"madr.a90",
	774	0,
	775	"7a2d8799",
	776	"c3760dba147740729d33b9b88e59088a4cc7437a",
	777	/* size */   0400,
	778	/* amap */   AMAP_DEFAULT,
	779	/* axor */   0,
	780	/* dxor */   017,                  // invert D0-D3
	781	/* width */   4,
	782	/* shift */   0,
	783	/* dmap */   DMAP_DEFAULT,
	784	/* dand */   ZERO,
	785	/* type */   sizeof(UINT8)
	786	};
755	787
756		m_madr_a32 = prom_load(&pl_madr_a32, memregion("madr_a32")->base(), 1, 1);
	788	static const prom_load_t pl_madr_a91 =
	789	{
	790	"madr.a91",
	791	0,
	792	"dd556aeb",
	793	"900f333a091e3ccde0843019c25f25fba62e6023",
	794	/* size */   0400,
	795	/* amap */   AMAP_DEFAULT,
	796	/* axor */   0,
	797	/* dxor */   017,                  // invert D0-D3
	798	/* width */   4,
	799	/* shift */   0,
	800	/* dmap */   DMAP_DEFAULT,
	801	/* dand */   ZERO,
	802	/* type */   sizeof(UINT8)
	803	};
757	804
758		static const prom_load_t pl_madr_a64 =
759		{
760		"madr.a64",
761		0,
762		"a66b0eda",
763		"4d9088f592caa3299e90966b17765be74e523144",
764		/* size */   0400,
765		/* amap */   AMAP_DEFAULT,
766		/* axor */   0,
767		/* dxor */   017,                  // invert D0-D3
768		/* width */   4,
769		/* shift */   0,
770		/* dmap */   DMAP_DEFAULT,
771		/* dand */   ZERO,
772		/* type */   sizeof(UINT8)
773		};
774		m_madr_a64 = prom_load(&pl_madr_a64, memregion("madr_a64")->base(), 1, 1);
	805	static const prom_load_t pl_enet_a41 =
	806	{   /* P3601 256x4 BPROM; Ethernet phase encoder 1 "PE1" */
	807	"enet.a41",
	808	0,
	809	"d5de8d86",
	810	"c134a4c898c73863124361a9b0218f7a7f00082a",
	811	/* size */   0400,
	812	/* amap */   AMAP_DEFAULT,
	813	/* axor */   0,
	814	/* dxor */   0,
	815	/* width */   4,
	816	/* shift */   0,
	817	/* dmap */   DMAP_DEFAULT,
	818	/* dand */   ZERO,
	819	/* type */   sizeof(UINT8)
	820	};
775	821
776		static const prom_load_t pl_madr_a65 =
777		{
778		"madr.a65",
779		0,
780		"ba37febd",
781		"82e9db1cb65f451755295f0d179e6f8fe3349d4d",
782		/* size */   0400,
783		/* amap */   AMAP_DEFAULT,
784		/* axor */   0,
785		/* dxor */   017,                  // invert D0-D3
786		/* width */   4,
787		/* shift */   0,
788		/* dmap */   DMAP_DEFAULT,
789		/* dand */   ZERO,
790		/* type */   sizeof(UINT8)
791		};
792		m_madr_a65 = prom_load(&pl_madr_a65, memregion("madr_a65")->base(), 1, 1);
	822	static const prom_load_t pl_enet_a42 =
	823	{   /* P3601 256x4 BPROM; Ethernet phase encoder 2 "PE2" */
	824	"enet.a42",
	825	0,
	826	"9d5c81bd",
	827	"ac7e63332a3dad0bef7cd0349b24e156a96a4bf0",
	828	/* size */   0400,
	829	/* amap */   AMAP_DEFAULT,
	830	/* axor */   0,
	831	/* dxor */   0,
	832	/* width */   4,
	833	/* shift */   0,
	834	/* dmap */   DMAP_DEFAULT,
	835	/* dand */   ZERO,
	836	/* type */   sizeof(UINT8)
	837	};
793	838
794		#if   0   // FIXME: add to alto2_cpu_device
795		static const prom_load_t pl_madr_a90 =
796		{
797		"madr.a90",
798		0,
799		"7a2d8799",
800		"c3760dba147740729d33b9b88e59088a4cc7437a",
801		/* size */   0400,
802		/* amap */   AMAP_DEFAULT,
803		/* axor */   0,
804		/* dxor */   017,                  // invert D0-D3
805		/* width */   4,
806		/* shift */   0,
807		/* dmap */   DMAP_DEFAULT,
808		/* dand */   ZERO,
809		/* type */   sizeof(UINT8)
810		};
811		m_madr_a90 = prom_load(&pl_madr_a90, memregion("madr_a90")->base(), 1 ,1);
	839	static const prom_load_t pl_enet_a49 =
	840	{   /* P3601 256x4 BPROM; Ethernet FIFO control "AFIFO" */
	841	"enet.a49",
	842	0,
	843	"4d2dcdb2",
	844	"583327a7d70cd02702c941c0e43c1e9408ff7fd0",
	845	/* size */   0400,
	846	/* amap */   AMAP_REVERSE_0_7,            // reverse address lines A0-A7
	847	/* axor */   0,
	848	/* dxor */   0,
	849	/* width */   4,
	850	/* shift */   0,
	851	/* dmap */   DMAP_DEFAULT,
	852	/* dand */   ZERO,
	853	/* type */   sizeof(UINT8)
	854	};
812	855
813		static const prom_load_t pl_madr_a91 =
814		{
815		"madr.a91",
816		0,
817		"dd556aeb",
818		"900f333a091e3ccde0843019c25f25fba62e6023",
819		/* size */   0400,
820		/* amap */   AMAP_DEFAULT,
821		/* axor */   0,
822		/* dxor */   017,                  // invert D0-D3
823		/* width */   4,
824		/* shift */   0,
825		/* dmap */   DMAP_DEFAULT,
826		/* dand */   ZERO,
827		/* type */   sizeof(UINT8)
828		};
829		m_madr_a91 = prom_load(&pl_madr_a91, memregion("madr_a91")->base(), 1, 1);
830		#endif
	856	//-------------------------------------------------
	857	//  device_start - device-specific startup
	858	//-------------------------------------------------
831	859
832		static const prom_load_t pl_enet_a41 =
833		{   /* P3601 256x4 BPROM; Ethernet phase encoder 1 "PE1" */
834		"enet.a41",
835		0,
836		"d5de8d86",
837		"c134a4c898c73863124361a9b0218f7a7f00082a",
838		/* size */   0400,
839		/* amap */   AMAP_DEFAULT,
840		/* axor */   0,
841		/* dxor */   0,
842		/* width */   4,
843		/* shift */   0,
844		/* dmap */   DMAP_DEFAULT,
845		/* dand */   ZERO,
846		/* type */   sizeof(UINT8)
847		};
848		m_ether_a41 = prom_load(&pl_enet_a41, memregion("ether_a41")->base(), 1, 1);
	860	// FIXME
	861	void alto2_cpu_device::device_start()
	862	{
	863	m_ucode = &space(AS_0);
	864	m_const = &space(AS_1);
849	865
850		static const prom_load_t pl_enet_a42 =
851		{   /* P3601 256x4 BPROM; Ethernet phase encoder 2 "PE2" */
852		"enet.a42",
853		0,
854		"9d5c81bd",
855		"ac7e63332a3dad0bef7cd0349b24e156a96a4bf0",
856		/* size */   0400,
857		/* amap */   AMAP_DEFAULT,
858		/* axor */   0,
859		/* dxor */   0,
860		/* width */   4,
861		/* shift */   0,
862		/* dmap */   DMAP_DEFAULT,
863		/* dand */   ZERO,
864		/* type */   sizeof(UINT8)
865		};
866		m_ether_a42 = prom_load(&pl_enet_a42, memregion("ether_a42")->base(), 1, 1);
	866	m_ucode_proms = prom_load(ucode_prom_list, memregion("ucode_proms")->base(), ALTO2_UCODE_ROM_PAGES, 8);
	867	m_const_proms = prom_load(const_prom_list, memregion("const_proms")->base(), 1, 4);
867	868
868		static const prom_load_t pl_enet_a49 =
869		{   /* P3601 256x4 BPROM; Ethernet FIFO control "AFIFO" */
870		"enet.a49",
871		0,
872		"4d2dcdb2",
873		"583327a7d70cd02702c941c0e43c1e9408ff7fd0",
874		/* size */   0400,
875		/* amap */   AMAP_REVERSE_0_7,            // reverse address lines A0-A7
876		/* axor */   0,
877		/* dxor */   0,
878		/* width */   4,
879		/* shift */   0,
880		/* dmap */   DMAP_DEFAULT,
881		/* dand */   ZERO,
882		/* type */   sizeof(UINT8)
883		};
884		m_ether_a49 = prom_load(&pl_enet_a49, memregion("ether_a49")->base(), 1, 1);
	869	for (offs_t offs = 0; offs < sizeof(UINT32)*ALTO2_UCODE_RAM_BASE; offs++)
	870	memory_write(AS_0, offs, 1, m_ucode_proms[offs]);
	871	for (offs_t offs = 0; offs < sizeof(UINT16)*ALTO2_CONST_SIZE; offs++)
	872	memory_write(AS_1, offs, 1, m_const_proms[offs]);
885	873
	874	m_disp_a38 = prom_load(&pl_displ_a38, memregion("displ_a38")->base());
	875	m_disp_a63 = prom_load(&pl_displ_a63, memregion("displ_a63")->base());
	876	m_disp_a66 = prom_load(&pl_displ_a66, memregion("displ_a66")->base());
	877	m_ctl2k_u3 = prom_load(&pl_2kctl_u3, memregion("2kctl_u3")->base());
	878	m_ctl2k_u38 = prom_load(&pl_2kctl_u38, memregion("2kctl_u38")->base());
	879	m_ctl2k_u76 = prom_load(&pl_2kctl_u76, memregion("2kctl_u76")->base());
	880	m_alu_a10 = prom_load(&pl_alu_a10, memregion("alu_a10")->base());
	881	m_cram3k_a37 = prom_load(&pl_3kcram_a37, memregion("3kcram_a37")->base());
	882	m_madr_a32 = prom_load(&pl_madr_a32, memregion("madr_a32")->base());
	883	m_madr_a64 = prom_load(&pl_madr_a64, memregion("madr_a64")->base());
	884	m_madr_a65 = prom_load(&pl_madr_a65, memregion("madr_a65")->base());
	885	m_madr_a90 = prom_load(&pl_madr_a90, memregion("madr_a90")->base(), 1 ,1);
	886	m_madr_a91 = prom_load(&pl_madr_a91, memregion("madr_a91")->base());
	887	m_ether_a41 = prom_load(&pl_enet_a41, memregion("ether_a41")->base());
	888	m_ether_a42 = prom_load(&pl_enet_a42, memregion("ether_a42")->base());
	889	m_ether_a49 = prom_load(&pl_enet_a49, memregion("ether_a49")->base());
	890
886	891	save_item(NAME(m_task_mpc));
887	892	save_item(NAME(m_task_next2));
888	893	save_item(NAME(m_ntime));
r26086	r26087
1096	1101	// FIXME
1097	1102	void alto2_cpu_device::device_reset()
1098	1103	{
1099		UINT8* raw;
1100	1104	soft_reset();
1101		raw = m_ucode->direct().raw();
1102		if (raw)
1103		memcpy(raw, m_ucode_proms, sizeof(UINT32)*ALTO2_UCODE_RAM_BASE);
1104		raw = m_const->direct().raw();
1105		if (raw)
1106		memcpy(raw, m_const_proms, sizeof(UINT16)*ALTO2_CONST_SIZE);
1107	1105	}
1108	1106
1109	1107	//-------------------------------------------------

branches/alto2/src/emu/cpu/alto2/alto2.h

r26086	r26087
224	224	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
225	225	{
226	226	switch (spacenum) {
227		case AS_PROGRAM:
	227	case AS_0:
228	228	return &m_ucode_config;
229		case AS_DATA:
	229	case AS_1:
230	230	return &m_const_config;
231	231	default:
232	232	return NULL;
r26086	r26087
992	992	*/
993	993	UINT8* m_madr_a65;
994	994
	995	/**
	996	* @brief unused PROM a90
	997	*/
	998	UINT8* m_madr_a90;
	999
	1000	/**
	1001	* @brief unused PROM a91
	1002	*/
	1003	UINT8* m_madr_a91;
	1004
995	1005	//! per task bus source function pointers, early (0) and late (1)
996	1006	a2func m_bs[2][ALTO2_TASKS][ALTO2_BUSSRC];
997	1007	void set_bs(UINT8 task, UINT8 fn, a2func f0, a2func f1) {

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