trunk/src/emu/video/mb_vcu.c
| r26026 | r26027 | |
|---|
| 41 | 41 | AM_RANGE(0x0000, 0x00ff) AM_RAM |
| 42 | 42 | AM_RANGE(0x0200, 0x02ff) AM_RAM |
| 43 | 43 | AM_RANGE(0x0400, 0x04ff) AM_RAM |
| 44 | | AM_RANGE(0x0600, 0x06ff) AM_WRITE(mb_vcu_paletteram_w) |
| 44 | AM_RANGE(0x0600, 0x06ff) AM_READWRITE(mb_vcu_paletteram_r,mb_vcu_paletteram_w) |
| 45 | 45 | ADDRESS_MAP_END |
| 46 | 46 | |
| 47 | READ8_MEMBER( mb_vcu_device::mb_vcu_paletteram_r ) |
| 48 | { |
| 49 | return m_palram[offset]; |
| 50 | } |
| 51 | |
| 47 | 52 | WRITE8_MEMBER( mb_vcu_device::mb_vcu_paletteram_w ) |
| 48 | 53 | { |
| 49 | 54 | int r,g,b, bit0, bit1, bit2; |
| 50 | 55 | |
| 51 | | UINT8 colour = data; |
| 56 | m_palram[offset] = data; |
| 52 | 57 | |
| 53 | 58 | /* red component */ |
| 54 | | bit1 = (colour >> 7) & 0x01; |
| 55 | | bit0 = (colour >> 6) & 0x01; |
| 59 | bit1 = (m_palram[offset] >> 7) & 0x01; |
| 60 | bit0 = (m_palram[offset] >> 6) & 0x01; |
| 56 | 61 | r = combine_2_weights(m_weights_r, bit0, bit1); |
| 57 | 62 | |
| 58 | 63 | /* green component */ |
| 59 | | bit2 = (colour >> 5) & 0x01; |
| 60 | | bit1 = (colour >> 4) & 0x01; |
| 61 | | bit0 = (colour >> 3) & 0x01; |
| 64 | bit2 = (m_palram[offset] >> 5) & 0x01; |
| 65 | bit1 = (m_palram[offset] >> 4) & 0x01; |
| 66 | bit0 = (m_palram[offset] >> 3) & 0x01; |
| 62 | 67 | g = combine_3_weights(m_weights_g, bit0, bit1, bit2); |
| 63 | 68 | |
| 64 | 69 | /* blue component */ |
| 65 | | bit2 = (colour >> 2) & 0x01; |
| 66 | | bit1 = (colour >> 1) & 0x01; |
| 67 | | bit0 = (colour >> 0) & 0x01; |
| 70 | bit2 = (m_palram[offset] >> 2) & 0x01; |
| 71 | bit1 = (m_palram[offset] >> 1) & 0x01; |
| 72 | bit0 = (m_palram[offset] >> 0) & 0x01; |
| 68 | 73 | b = combine_3_weights(m_weights_b, bit0, bit1, bit2); |
| 69 | 74 | |
| 70 | 75 | palette_set_color(machine(), offset, MAKE_RGB(r, g, b)); |
| r26026 | r26027 | |
|---|
| 185 | 190 | // TODO: m_screen_tag |
| 186 | 191 | m_cpu = machine().device<cpu_device>(m_cpu_tag); |
| 187 | 192 | m_ram = auto_alloc_array_clear(machine(), UINT8, 0x800); |
| 193 | m_palram = auto_alloc_array_clear(machine(), UINT8, 0x100); |
| 188 | 194 | |
| 189 | 195 | { |
| 190 | 196 | static const int resistances_r[2] = { 4700, 2200 }; |
trunk/src/emu/video/mb_vcu.h
| r26026 | r26027 | |
|---|
| 53 | 53 | DECLARE_WRITE8_MEMBER( background_color_w ); |
| 54 | 54 | DECLARE_READ8_MEMBER( status_r ); |
| 55 | 55 | DECLARE_WRITE8_MEMBER( vbank_w ); |
| 56 | DECLARE_READ8_MEMBER( mb_vcu_paletteram_r ); |
| 56 | 57 | DECLARE_WRITE8_MEMBER( mb_vcu_paletteram_w ); |
| 57 | 58 | |
| 58 | 59 | UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); |
| r26026 | r26027 | |
|---|
| 75 | 76 | const address_space_config m_paletteram_space_config; |
| 76 | 77 | UINT8 m_status; |
| 77 | 78 | UINT8 *m_ram; |
| 79 | UINT8 *m_palram; |
| 78 | 80 | cpu_device *m_cpu; |
| 79 | 81 | UINT16 m_param_offset_latch; |
| 80 | 82 | |