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r26011 Tuesday 5th November, 2013 at 18:08:17 UTC by Osso
harddriv: moved handlers in the driver state. (nw)

[src/mame/drivers]	harddriv.c
[src/mame/includes]	harddriv.h
[src/mame/machine]	harddriv.c
[src/mame/video]	harddriv.c

trunk/src/mame/drivers/harddriv.c

r26010	r26011
428	428	static ADDRESS_MAP_START( driver_68k_map, AS_PROGRAM, 16, harddriv_state )
429	429	ADDRESS_MAP_UNMAP_HIGH
430	430	AM_RANGE(0x000000, 0x0fffff) AM_ROM
431		AM_RANGE(0x600000, 0x603fff) AM_READ_LEGACY(hd68k_port0_r)
432		AM_RANGE(0x604000, 0x607fff) AM_WRITE_LEGACY(hd68k_nwr_w)
	431	AM_RANGE(0x600000, 0x603fff) AM_READ(hd68k_port0_r)
	432	AM_RANGE(0x604000, 0x607fff) AM_WRITE(hd68k_nwr_w)
433	433	AM_RANGE(0x608000, 0x60bfff) AM_WRITE(watchdog_reset16_w)
434		AM_RANGE(0x60c000, 0x60ffff) AM_WRITE_LEGACY(hd68k_irq_ack_w)
435		AM_RANGE(0xa00000, 0xa7ffff) AM_WRITE_LEGACY(hd68k_wr0_write)
436		AM_RANGE(0xa80000, 0xafffff) AM_READ_PORT("a80000") AM_WRITE_LEGACY(hd68k_wr1_write)
437		AM_RANGE(0xb00000, 0xb7ffff) AM_READWRITE_LEGACY(hd68k_adc8_r, hd68k_wr2_write)
438		AM_RANGE(0xb80000, 0xbfffff) AM_READWRITE_LEGACY(hd68k_adc12_r, hd68k_adc_control_w)
439		AM_RANGE(0xc00000, 0xc03fff) AM_READWRITE_LEGACY(hd68k_gsp_io_r, hd68k_gsp_io_w)
440		AM_RANGE(0xc04000, 0xc07fff) AM_READWRITE_LEGACY(hd68k_msp_io_r, hd68k_msp_io_w)
	434	AM_RANGE(0x60c000, 0x60ffff) AM_WRITE(hd68k_irq_ack_w)
	435	AM_RANGE(0xa00000, 0xa7ffff) AM_WRITE(hd68k_wr0_write)
	436	AM_RANGE(0xa80000, 0xafffff) AM_READ_PORT("a80000") AM_WRITE(hd68k_wr1_write)
	437	AM_RANGE(0xb00000, 0xb7ffff) AM_READWRITE(hd68k_adc8_r, hd68k_wr2_write)
	438	AM_RANGE(0xb80000, 0xbfffff) AM_READWRITE(hd68k_adc12_r, hd68k_adc_control_w)
	439	AM_RANGE(0xc00000, 0xc03fff) AM_READWRITE(hd68k_gsp_io_r, hd68k_gsp_io_w)
	440	AM_RANGE(0xc04000, 0xc07fff) AM_READWRITE(hd68k_msp_io_r, hd68k_msp_io_w)
441	441	AM_RANGE(0xff0000, 0xff001f) AM_DEVREADWRITE8("duartn68681", duartn68681_device, read, write, 0xff00)
442		AM_RANGE(0xff4000, 0xff4fff) AM_READWRITE_LEGACY(hd68k_zram_r, hd68k_zram_w) AM_SHARE("zram")
	442	AM_RANGE(0xff4000, 0xff4fff) AM_READWRITE(hd68k_zram_r, hd68k_zram_w) AM_SHARE("zram")
443	443	AM_RANGE(0xff8000, 0xffffff) AM_RAM
444	444	ADDRESS_MAP_END
445	445
r26010	r26011
447	447	static ADDRESS_MAP_START( driver_gsp_map, AS_PROGRAM, 16, harddriv_state )
448	448	ADDRESS_MAP_UNMAP_HIGH
449	449	AM_RANGE(0x00000000, 0x0000200f) AM_NOP                 /* hit during self-test */
450		AM_RANGE(0x02000000, 0x0207ffff) AM_READWRITE_LEGACY(hdgsp_vram_2bpp_r, hdgsp_vram_1bpp_w)
451		AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, hdgsp_io_w)
452		AM_RANGE(0xf4000000, 0xf40000ff) AM_READWRITE_LEGACY(hdgsp_control_lo_r, hdgsp_control_lo_w) AM_SHARE("gsp_control_lo")
453		AM_RANGE(0xf4800000, 0xf48000ff) AM_READWRITE_LEGACY(hdgsp_control_hi_r, hdgsp_control_hi_w) AM_SHARE("gsp_control_hi")
454		AM_RANGE(0xf5000000, 0xf5000fff) AM_READWRITE_LEGACY(hdgsp_paletteram_lo_r, hdgsp_paletteram_lo_w) AM_SHARE("gsp_palram_lo")
455		AM_RANGE(0xf5800000, 0xf5800fff) AM_READWRITE_LEGACY(hdgsp_paletteram_hi_r, hdgsp_paletteram_hi_w) AM_SHARE("gsp_palram_hi")
	450	AM_RANGE(0x02000000, 0x0207ffff) AM_READWRITE(hdgsp_vram_2bpp_r, hdgsp_vram_1bpp_w)
	451	AM_RANGE(0xc0000000, 0xc00001ff) AM_READ_LEGACY(tms34010_io_register_r) AM_WRITE(hdgsp_io_w)
	452	AM_RANGE(0xf4000000, 0xf40000ff) AM_READWRITE(hdgsp_control_lo_r, hdgsp_control_lo_w) AM_SHARE("gsp_control_lo")
	453	AM_RANGE(0xf4800000, 0xf48000ff) AM_READWRITE(hdgsp_control_hi_r, hdgsp_control_hi_w) AM_SHARE("gsp_control_hi")
	454	AM_RANGE(0xf5000000, 0xf5000fff) AM_READWRITE(hdgsp_paletteram_lo_r, hdgsp_paletteram_lo_w) AM_SHARE("gsp_palram_lo")
	455	AM_RANGE(0xf5800000, 0xf5800fff) AM_READWRITE(hdgsp_paletteram_hi_r, hdgsp_paletteram_hi_w) AM_SHARE("gsp_palram_hi")
456	456	AM_RANGE(0xff800000, 0xffffffff) AM_RAM AM_SHARE("gsp_vram")
457	457	ADDRESS_MAP_END
458	458
r26010	r26011
476	476	static ADDRESS_MAP_START( multisync_68k_map, AS_PROGRAM, 16, harddriv_state )
477	477	ADDRESS_MAP_UNMAP_HIGH
478	478	AM_RANGE(0x000000, 0x0fffff) AM_ROM
479		AM_RANGE(0x604000, 0x607fff) AM_READWRITE_LEGACY(hd68k_sound_reset_r, hd68k_nwr_w)
	479	AM_RANGE(0x604000, 0x607fff) AM_READWRITE(hd68k_sound_reset_r, hd68k_nwr_w)
480	480	AM_RANGE(0x608000, 0x60bfff) AM_WRITE(watchdog_reset16_w)
481		AM_RANGE(0x60c000, 0x60ffff) AM_READWRITE_LEGACY(hd68k_port0_r, hd68k_irq_ack_w)
482		AM_RANGE(0xa00000, 0xa7ffff) AM_WRITE_LEGACY(hd68k_wr0_write)
483		AM_RANGE(0xa80000, 0xafffff) AM_READ_PORT("a80000") AM_WRITE_LEGACY(hd68k_wr1_write)
484		AM_RANGE(0xb00000, 0xb7ffff) AM_READWRITE_LEGACY(hd68k_adc8_r, hd68k_wr2_write)
485		AM_RANGE(0xb80000, 0xbfffff) AM_READWRITE_LEGACY(hd68k_adc12_r, hd68k_adc_control_w)
486		AM_RANGE(0xc00000, 0xc03fff) AM_READWRITE_LEGACY(hd68k_gsp_io_r, hd68k_gsp_io_w)
487		AM_RANGE(0xc04000, 0xc07fff) AM_READWRITE_LEGACY(hd68k_msp_io_r, hd68k_msp_io_w)
	481	AM_RANGE(0x60c000, 0x60ffff) AM_READWRITE(hd68k_port0_r, hd68k_irq_ack_w)
	482	AM_RANGE(0xa00000, 0xa7ffff) AM_WRITE(hd68k_wr0_write)
	483	AM_RANGE(0xa80000, 0xafffff) AM_READ_PORT("a80000") AM_WRITE(hd68k_wr1_write)
	484	AM_RANGE(0xb00000, 0xb7ffff) AM_READWRITE(hd68k_adc8_r, hd68k_wr2_write)
	485	AM_RANGE(0xb80000, 0xbfffff) AM_READWRITE(hd68k_adc12_r, hd68k_adc_control_w)
	486	AM_RANGE(0xc00000, 0xc03fff) AM_READWRITE(hd68k_gsp_io_r, hd68k_gsp_io_w)
	487	AM_RANGE(0xc04000, 0xc07fff) AM_READWRITE(hd68k_msp_io_r, hd68k_msp_io_w)
488	488	AM_RANGE(0xff0000, 0xff001f) AM_DEVREADWRITE8("duartn68681", duartn68681_device, read, write, 0xff00)
489		AM_RANGE(0xff4000, 0xff4fff) AM_READWRITE_LEGACY(hd68k_zram_r, hd68k_zram_w) AM_SHARE("zram")
	489	AM_RANGE(0xff4000, 0xff4fff) AM_READWRITE(hd68k_zram_r, hd68k_zram_w) AM_SHARE("zram")
490	490	AM_RANGE(0xff8000, 0xffffff) AM_RAM
491	491	ADDRESS_MAP_END
492	492
r26010	r26011
494	494	static ADDRESS_MAP_START( multisync_gsp_map, AS_PROGRAM, 16, harddriv_state )
495	495	ADDRESS_MAP_UNMAP_HIGH
496	496	AM_RANGE(0x00000000, 0x0000200f) AM_NOP                 /* hit during self-test */
497		AM_RANGE(0x02000000, 0x020fffff) AM_READWRITE_LEGACY(hdgsp_vram_2bpp_r, hdgsp_vram_2bpp_w)
498		AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, hdgsp_io_w)
499		AM_RANGE(0xf4000000, 0xf40000ff) AM_READWRITE_LEGACY(hdgsp_control_lo_r, hdgsp_control_lo_w) AM_SHARE("gsp_control_lo")
500		AM_RANGE(0xf4800000, 0xf48000ff) AM_READWRITE_LEGACY(hdgsp_control_hi_r, hdgsp_control_hi_w) AM_SHARE("gsp_control_hi")
501		AM_RANGE(0xf5000000, 0xf5000fff) AM_READWRITE_LEGACY(hdgsp_paletteram_lo_r, hdgsp_paletteram_lo_w) AM_SHARE("gsp_palram_lo")
502		AM_RANGE(0xf5800000, 0xf5800fff) AM_READWRITE_LEGACY(hdgsp_paletteram_hi_r, hdgsp_paletteram_hi_w) AM_SHARE("gsp_palram_hi")
	497	AM_RANGE(0x02000000, 0x020fffff) AM_READWRITE(hdgsp_vram_2bpp_r, hdgsp_vram_2bpp_w)
	498	AM_RANGE(0xc0000000, 0xc00001ff) AM_READ_LEGACY(tms34010_io_register_r) AM_WRITE(hdgsp_io_w)
	499	AM_RANGE(0xf4000000, 0xf40000ff) AM_READWRITE(hdgsp_control_lo_r, hdgsp_control_lo_w) AM_SHARE("gsp_control_lo")
	500	AM_RANGE(0xf4800000, 0xf48000ff) AM_READWRITE(hdgsp_control_hi_r, hdgsp_control_hi_w) AM_SHARE("gsp_control_hi")
	501	AM_RANGE(0xf5000000, 0xf5000fff) AM_READWRITE(hdgsp_paletteram_lo_r, hdgsp_paletteram_lo_w) AM_SHARE("gsp_palram_lo")
	502	AM_RANGE(0xf5800000, 0xf5800fff) AM_READWRITE(hdgsp_paletteram_hi_r, hdgsp_paletteram_hi_w) AM_SHARE("gsp_palram_hi")
503	503	AM_RANGE(0xff800000, 0xffbfffff) AM_MIRROR(0x0400000) AM_RAM AM_SHARE("gsp_vram")
504	504	ADDRESS_MAP_END
505	505
r26010	r26011
514	514	static ADDRESS_MAP_START( multisync2_68k_map, AS_PROGRAM, 16, harddriv_state )
515	515	ADDRESS_MAP_UNMAP_HIGH
516	516	AM_RANGE(0x000000, 0x1fffff) AM_ROM
517		AM_RANGE(0x604000, 0x607fff) AM_WRITE_LEGACY(hd68k_nwr_w)
	517	AM_RANGE(0x604000, 0x607fff) AM_WRITE(hd68k_nwr_w)
518	518	AM_RANGE(0x608000, 0x60bfff) AM_WRITE(watchdog_reset16_w)
519		AM_RANGE(0x60c000, 0x60ffff) AM_READWRITE_LEGACY(hd68k_port0_r, hd68k_irq_ack_w)
520		AM_RANGE(0xa00000, 0xa7ffff) AM_WRITE_LEGACY(hd68k_wr0_write)
521		AM_RANGE(0xa80000, 0xafffff) AM_READ_PORT("a80000") AM_WRITE_LEGACY(hd68k_wr1_write)
522		AM_RANGE(0xb00000, 0xb7ffff) AM_READWRITE_LEGACY(hd68k_adc8_r, hd68k_wr2_write)
523		AM_RANGE(0xb80000, 0xbfffff) AM_READWRITE_LEGACY(hd68k_adc12_r, hd68k_adc_control_w)
524		AM_RANGE(0xc00000, 0xc03fff) AM_READWRITE_LEGACY(hd68k_gsp_io_r, hd68k_gsp_io_w)
525		AM_RANGE(0xc04000, 0xc07fff) AM_READWRITE_LEGACY(hd68k_msp_io_r, hd68k_msp_io_w)
	519	AM_RANGE(0x60c000, 0x60ffff) AM_READWRITE(hd68k_port0_r, hd68k_irq_ack_w)
	520	AM_RANGE(0xa00000, 0xa7ffff) AM_WRITE(hd68k_wr0_write)
	521	AM_RANGE(0xa80000, 0xafffff) AM_READ_PORT("a80000") AM_WRITE(hd68k_wr1_write)
	522	AM_RANGE(0xb00000, 0xb7ffff) AM_READWRITE(hd68k_adc8_r, hd68k_wr2_write)
	523	AM_RANGE(0xb80000, 0xbfffff) AM_READWRITE(hd68k_adc12_r, hd68k_adc_control_w)
	524	AM_RANGE(0xc00000, 0xc03fff) AM_READWRITE(hd68k_gsp_io_r, hd68k_gsp_io_w)
	525	AM_RANGE(0xc04000, 0xc07fff) AM_READWRITE(hd68k_msp_io_r, hd68k_msp_io_w)
526	526	AM_RANGE(0xfc0000, 0xfc001f) AM_DEVREADWRITE8("duartn68681", duartn68681_device, read, write, 0xff00)
527		AM_RANGE(0xfd0000, 0xfd0fff) AM_MIRROR(0x004000) AM_READWRITE_LEGACY(hd68k_zram_r, hd68k_zram_w) AM_SHARE("zram")
	527	AM_RANGE(0xfd0000, 0xfd0fff) AM_MIRROR(0x004000) AM_READWRITE(hd68k_zram_r, hd68k_zram_w) AM_SHARE("zram")
528	528	AM_RANGE(0xff0000, 0xffffff) AM_RAM
529	529	ADDRESS_MAP_END
530	530
r26010	r26011
533	533	static ADDRESS_MAP_START( multisync2_gsp_map, AS_PROGRAM, 16, harddriv_state )
534	534	ADDRESS_MAP_UNMAP_HIGH
535	535	AM_RANGE(0x00000000, 0x0000200f) AM_NOP                 /* hit during self-test */
536		AM_RANGE(0x02000000, 0x020fffff) AM_READWRITE_LEGACY(hdgsp_vram_2bpp_r, hdgsp_vram_2bpp_w)
537		AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, hdgsp_io_w)
538		AM_RANGE(0xf4000000, 0xf40000ff) AM_READWRITE_LEGACY(hdgsp_control_lo_r, hdgsp_control_lo_w) AM_SHARE("gsp_control_lo")
539		AM_RANGE(0xf4800000, 0xf48000ff) AM_READWRITE_LEGACY(hdgsp_control_hi_r, hdgsp_control_hi_w) AM_SHARE("gsp_control_hi")
540		AM_RANGE(0xf5000000, 0xf5000fff) AM_READWRITE_LEGACY(hdgsp_paletteram_lo_r, hdgsp_paletteram_lo_w) AM_SHARE("gsp_palram_lo")
541		AM_RANGE(0xf5800000, 0xf5800fff) AM_READWRITE_LEGACY(hdgsp_paletteram_hi_r, hdgsp_paletteram_hi_w) AM_SHARE("gsp_palram_hi")
	536	AM_RANGE(0x02000000, 0x020fffff) AM_READWRITE(hdgsp_vram_2bpp_r, hdgsp_vram_2bpp_w)
	537	AM_RANGE(0xc0000000, 0xc00001ff) AM_READ_LEGACY(tms34010_io_register_r) AM_WRITE(hdgsp_io_w)
	538	AM_RANGE(0xf4000000, 0xf40000ff) AM_READWRITE(hdgsp_control_lo_r, hdgsp_control_lo_w) AM_SHARE("gsp_control_lo")
	539	AM_RANGE(0xf4800000, 0xf48000ff) AM_READWRITE(hdgsp_control_hi_r, hdgsp_control_hi_w) AM_SHARE("gsp_control_hi")
	540	AM_RANGE(0xf5000000, 0xf5000fff) AM_READWRITE(hdgsp_paletteram_lo_r, hdgsp_paletteram_lo_w) AM_SHARE("gsp_palram_lo")
	541	AM_RANGE(0xf5800000, 0xf5800fff) AM_READWRITE(hdgsp_paletteram_hi_r, hdgsp_paletteram_hi_w) AM_SHARE("gsp_palram_hi")
542	542	AM_RANGE(0xff800000, 0xffffffff) AM_RAM AM_SHARE("gsp_vram")
543	543	ADDRESS_MAP_END
544	544
r26010	r26011
559	559	static ADDRESS_MAP_START( adsp_data_map, AS_DATA, 16, harddriv_state )
560	560	ADDRESS_MAP_UNMAP_HIGH
561	561	AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("adsp_data")
562		AM_RANGE(0x2000, 0x2fff) AM_READWRITE_LEGACY(hdadsp_special_r, hdadsp_special_w)
	562	AM_RANGE(0x2000, 0x2fff) AM_READWRITE(hdadsp_special_r, hdadsp_special_w)
563	563	ADDRESS_MAP_END
564	564
565	565
r26010	r26011
580	580	ADDRESS_MAP_UNMAP_HIGH
581	581	AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("adsp_data")
582	582	AM_RANGE(0x3800, 0x3bff) AM_RAM                     /* internal RAM */
583		AM_RANGE(0x3fe0, 0x3fff) AM_READWRITE_LEGACY(hdds3_control_r, hdds3_control_w)  /* adsp control regs */
584		AM_RANGE(0x2000, 0x3fff) AM_READWRITE_LEGACY(hdds3_special_r, hdds3_special_w)
	583	AM_RANGE(0x3fe0, 0x3fff) AM_READWRITE(hdds3_control_r, hdds3_control_w)  /* adsp control regs */
	584	AM_RANGE(0x2000, 0x3fff) AM_READWRITE(hdds3_special_r, hdds3_special_w)
585	585	ADDRESS_MAP_END
586	586
587	587
r26010	r26011
593	593	static ADDRESS_MAP_START( ds3sdsp_data_map, AS_DATA, 16, harddriv_state )
594	594	ADDRESS_MAP_UNMAP_HIGH
595	595	AM_RANGE(0x3800, 0x39ff) AM_RAM                     /* internal RAM */
596		AM_RANGE(0x3fe0, 0x3fff) AM_READWRITE_LEGACY(hdds3_sdsp_control_r, hdds3_sdsp_control_w)
597		AM_RANGE(0x2000, 0x3fff) AM_READWRITE_LEGACY(hdds3_sdsp_special_r, hdds3_sdsp_special_w)
	596	AM_RANGE(0x3fe0, 0x3fff) AM_READWRITE(hdds3_sdsp_control_r, hdds3_sdsp_control_w)
	597	AM_RANGE(0x2000, 0x3fff) AM_READWRITE(hdds3_sdsp_special_r, hdds3_sdsp_special_w)
598	598	ADDRESS_MAP_END
599	599
600	600
r26010	r26011
607	607	ADDRESS_MAP_UNMAP_HIGH
608	608	AM_RANGE(0x0000, 0x1fff) AM_RAM // TODO
609	609	AM_RANGE(0x3800, 0x39ff) AM_RAM                     /* internal RAM */
610		AM_RANGE(0x3fe0, 0x3fff) AM_READWRITE_LEGACY(hdds3_xdsp_control_r, hdds3_xdsp_control_w)
	610	AM_RANGE(0x3fe0, 0x3fff) AM_READWRITE(hdds3_xdsp_control_r, hdds3_xdsp_control_w)
611	611	ADDRESS_MAP_END
612	612
613	613
r26010	r26011
4054	4054	/* install handlers for the compact driving games' inputs */
4055	4055	if (compact_inputs)
4056	4056	{
4057		state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x400000, 0x400001, FUNC(hdc68k_wheel_r));
4058		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x408000, 0x408001, FUNC(hdc68k_wheel_edge_reset_w));
4059		state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0xa80000, 0xafffff, FUNC(hdc68k_port1_r));
	4057	state->m_maincpu->space(AS_PROGRAM).install_read_handler(0x400000, 0x400001, read16_delegate(FUNC(harddriv_state::hdc68k_wheel_r), state));
	4058	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x408000, 0x408001, write16_delegate(FUNC(harddriv_state::hdc68k_wheel_edge_reset_w), state));
	4059	state->m_maincpu->space(AS_PROGRAM).install_read_handler(0xa80000, 0xafffff, read16_delegate(FUNC(harddriv_state::hdc68k_port1_r), state));
4060	4060	}
4061	4061	}
4062	4062
r26010	r26011
4067	4067	harddriv_state *state = machine.driver_data<harddriv_state>();
4068	4068
4069	4069	/* install ADSP program RAM */
4070		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x800000, 0x807fff, FUNC(hd68k_adsp_program_r), FUNC(hd68k_adsp_program_w));
	4070	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x800000, 0x807fff, read16_delegate(FUNC(harddriv_state::hd68k_adsp_program_r), state), write16_delegate(FUNC(harddriv_state::hd68k_adsp_program_w), state));
4071	4071
4072	4072	/* install ADSP data RAM */
4073		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x808000, 0x80bfff, FUNC(hd68k_adsp_data_r), FUNC(hd68k_adsp_data_w));
	4073	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x808000, 0x80bfff, read16_delegate(FUNC(harddriv_state::hd68k_adsp_data_r), state), write16_delegate(FUNC(harddriv_state::hd68k_adsp_data_w), state));
4074	4074
4075	4075	/* install ADSP serial buffer RAM */
4076		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x810000, 0x813fff, FUNC(hd68k_adsp_buffer_r), FUNC(hd68k_adsp_buffer_w));
	4076	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x810000, 0x813fff, read16_delegate(FUNC(harddriv_state::hd68k_adsp_buffer_r), state), write16_delegate(FUNC(harddriv_state::hd68k_adsp_buffer_w), state));
4077	4077
4078	4078	/* install ADSP control locations */
4079		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x818000, 0x81801f, FUNC(hd68k_adsp_control_w));
4080		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x818060, 0x81807f, FUNC(hd68k_adsp_irq_clear_w));
4081		state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x838000, 0x83ffff, FUNC(hd68k_adsp_irq_state_r));
	4079	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x818000, 0x81801f, write16_delegate(FUNC(harddriv_state::hd68k_adsp_control_w), state));
	4080	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x818060, 0x81807f, write16_delegate(FUNC(harddriv_state::hd68k_adsp_irq_clear_w), state));
	4081	state->m_maincpu->space(AS_PROGRAM).install_read_handler(0x838000, 0x83ffff, read16_delegate(FUNC(harddriv_state::hd68k_adsp_irq_state_r), state));
4082	4082	}
4083	4083
4084	4084
r26010	r26011
4088	4088	harddriv_state *state = machine.driver_data<harddriv_state>();
4089	4089
4090	4090	/* install ADSP program RAM */
4091		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x800000, 0x807fff, FUNC(hd68k_ds3_program_r), FUNC(hd68k_ds3_program_w));
	4091	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x800000, 0x807fff, read16_delegate(FUNC(harddriv_state::hd68k_ds3_program_r), state), write16_delegate(FUNC(harddriv_state::hd68k_ds3_program_w), state));
4092	4092
4093	4093	/* install ADSP data RAM */
4094		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x808000, 0x80bfff, FUNC(hd68k_adsp_data_r), FUNC(hd68k_adsp_data_w));
4095		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x80c000, 0x80dfff, FUNC(hdds3_special_r), FUNC(hdds3_special_w));
	4094	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x808000, 0x80bfff, read16_delegate(FUNC(harddriv_state::hd68k_adsp_data_r), state), write16_delegate(FUNC(harddriv_state::hd68k_adsp_data_w), state));
	4095	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x80c000, 0x80dfff, read16_delegate(FUNC(harddriv_state::hdds3_special_r), state), write16_delegate(FUNC(harddriv_state::hdds3_special_w), state));
4096	4096
4097	4097	/* install ADSP control locations */
4098		state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x820000, 0x8207ff, FUNC(hd68k_ds3_gdata_r));
4099		state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x820800, 0x820fff, FUNC(hd68k_ds3_girq_state_r));
4100		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x820000, 0x8207ff, FUNC(hd68k_ds3_gdata_w));
4101		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x821000, 0x8217ff, FUNC(hd68k_adsp_irq_clear_w));
	4098	state->m_maincpu->space(AS_PROGRAM).install_read_handler(0x820000, 0x8207ff, read16_delegate(FUNC(harddriv_state::hd68k_ds3_gdata_r), state));
	4099	state->m_maincpu->space(AS_PROGRAM).install_read_handler(0x820800, 0x820fff, read16_delegate(FUNC(harddriv_state::hd68k_ds3_girq_state_r), state));
	4100	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x820000, 0x8207ff, write16_delegate(FUNC(harddriv_state::hd68k_ds3_gdata_w), state));
	4101	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x821000, 0x8217ff, write16_delegate(FUNC(harddriv_state::hd68k_adsp_irq_clear_w), state));
4102	4102
4103		state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x822000, 0x8227ff, FUNC(hd68k_ds3_sdata_r));
4104		state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x822800, 0x822fff, FUNC(hd68k_ds3_sirq_state_r));
4105		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x822000, 0x8227ff, FUNC(hd68k_ds3_sdata_w));
4106		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x823000, 0x8237ff, FUNC(hd68k_ds3_sirq_clear_w));
4107		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x823800, 0x823fff, FUNC(hd68k_ds3_control_w));
	4103	state->m_maincpu->space(AS_PROGRAM).install_read_handler(0x822000, 0x8227ff, read16_delegate(FUNC(harddriv_state::hd68k_ds3_sdata_r), state));
	4104	state->m_maincpu->space(AS_PROGRAM).install_read_handler(0x822800, 0x822fff, read16_delegate(FUNC(harddriv_state::hd68k_ds3_sirq_state_r), state));
	4105	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x822000, 0x8227ff, write16_delegate(FUNC(harddriv_state::hd68k_ds3_sdata_w), state));
	4106	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x823000, 0x8237ff, write16_delegate(FUNC(harddriv_state::hd68k_ds3_sirq_clear_w), state));
	4107	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x823800, 0x823fff, write16_delegate(FUNC(harddriv_state::hd68k_ds3_control_w), state));
4108	4108
4109	4109	/* predetermine memory regions */
4110	4110	state->m_ds3_sdata_memory = (UINT16 *)state->memregion("ds3sdsp_data")->base();
r26010	r26011
4186	4186	UINT8 *usr3 = state->memregion("user3")->base();
4187	4187
4188	4188	/* install ASIC61 */
4189		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x85c000, 0x85c7ff, FUNC(hd68k_dsk_dsp32_r), FUNC(hd68k_dsk_dsp32_w));
	4189	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x85c000, 0x85c7ff, read16_delegate(FUNC(harddriv_state::hd68k_dsk_dsp32_r), state), write16_delegate(FUNC(harddriv_state::hd68k_dsk_dsp32_w), state));
4190	4190
4191	4191	/* install control registers */
4192		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x85c800, 0x85c81f, FUNC(hd68k_dsk_control_w));
	4192	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x85c800, 0x85c81f, write16_delegate(FUNC(harddriv_state::hd68k_dsk_control_w), state));
4193	4193
4194	4194	/* install extra RAM */
4195		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x900000, 0x90ffff, FUNC(hd68k_dsk_ram_r), FUNC(hd68k_dsk_ram_w));
	4195	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x900000, 0x90ffff, read16_delegate(FUNC(harddriv_state::hd68k_dsk_ram_r), state), write16_delegate(FUNC(harddriv_state::hd68k_dsk_ram_w), state));
4196	4196	state->m_dsk_ram = (UINT16 *)(usr3 + 0x40000);
4197	4197
4198	4198	/* install extra ZRAM */
4199		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x910000, 0x910fff, FUNC(hd68k_dsk_zram_r), FUNC(hd68k_dsk_zram_w));
	4199	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x910000, 0x910fff, read16_delegate(FUNC(harddriv_state::hd68k_dsk_zram_r), state), write16_delegate(FUNC(harddriv_state::hd68k_dsk_zram_w), state));
4200	4200	state->m_dsk_zram = (UINT16 *)(usr3 + 0x50000);
4201	4201
4202	4202	/* install ASIC65 */
r26010	r26011
4205	4205	state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x918000, 0x91bfff, FUNC(asic65_io_r));
4206	4206
4207	4207	/* install extra ROM */
4208		state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x940000, 0x9fffff, FUNC(hd68k_dsk_small_rom_r));
	4208	state->m_maincpu->space(AS_PROGRAM).install_read_handler(0x940000, 0x9fffff, read16_delegate(FUNC(harddriv_state::hd68k_dsk_small_rom_r), state));
4209	4209	state->m_dsk_rom = (UINT16 *)(usr3 + 0x00000);
4210	4210
4211	4211	/* set up the ASIC65 */
r26010	r26011
4225	4225	state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x825000, 0x825001, FUNC(asic65_io_r));
4226	4226
4227	4227	/* install ASIC61 */
4228		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x827000, 0x8277ff, FUNC(hd68k_dsk_dsp32_r), FUNC(hd68k_dsk_dsp32_w));
	4228	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x827000, 0x8277ff, read16_delegate(FUNC(harddriv_state::hd68k_dsk_dsp32_r), state), write16_delegate(FUNC(harddriv_state::hd68k_dsk_dsp32_w), state));
4229	4229
4230	4230	/* install control registers */
4231		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x827800, 0x82781f, FUNC(hd68k_dsk_control_w));
	4231	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x827800, 0x82781f, write16_delegate(FUNC(harddriv_state::hd68k_dsk_control_w), state));
4232	4232
4233	4233	/* install extra RAM */
4234		state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0x880000, 0x8bffff, FUNC(hd68k_dsk_ram_r), FUNC(hd68k_dsk_ram_w));
	4234	state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x880000, 0x8bffff, read16_delegate(FUNC(harddriv_state::hd68k_dsk_ram_r), state), write16_delegate(FUNC(harddriv_state::hd68k_dsk_ram_w), state));
4235	4235	state->m_dsk_ram = (UINT16 *)(usr3 + 0x100000);
4236	4236
4237	4237	/* install extra ROM */
4238		state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x900000, 0x9fffff, FUNC(hd68k_dsk_rom_r));
	4238	state->m_maincpu->space(AS_PROGRAM).install_read_handler(0x900000, 0x9fffff, read16_delegate(FUNC(harddriv_state::hd68k_dsk_rom_r), state));
4239	4239	state->m_dsk_rom = (UINT16 *)(usr3 + 0x000000);
4240	4240
4241	4241	/* set up the ASIC65 */
r26010	r26011
4257	4257	asic65_config(machine, ASIC65_STEELTAL);
4258	4258
4259	4259	/* install DSPCOM control */
4260		state->m_maincpu->space(AS_PROGRAM).install_legacy_write_handler(0x904000, 0x90401f, FUNC(hddspcom_control_w));
	4260	state->m_maincpu->space(AS_PROGRAM).install_write_handler(0x904000, 0x90401f, write16_delegate(FUNC(harddriv_state::hddspcom_control_w), state));
4261	4261	}
4262	4262
4263	4263
r26010	r26011
4291	4291	init_driver_sound(machine());
4292	4292
4293	4293	/* set up gsp speedup handler */
4294		m_gsp_speedup_addr[0] = m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup1_w));
4295		m_gsp_speedup_addr[1] = m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfffcfc00, 0xfffcfc0f, FUNC(hdgsp_speedup2_w));
4296		m_gsp->space(AS_PROGRAM).install_legacy_read_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup_r));
	4294	m_gsp_speedup_addr[0] = m_gsp->space(AS_PROGRAM).install_write_handler(0xfff9fc00, 0xfff9fc0f, write16_delegate(FUNC(harddriv_state::hdgsp_speedup1_w), this));
	4295	m_gsp_speedup_addr[1] = m_gsp->space(AS_PROGRAM).install_write_handler(0xfffcfc00, 0xfffcfc0f, write16_delegate(FUNC(harddriv_state::hdgsp_speedup2_w), this));
	4296	m_gsp->space(AS_PROGRAM).install_read_handler(0xfff9fc00, 0xfff9fc0f, read16_delegate(FUNC(harddriv_state::hdgsp_speedup_r), this));
4297	4297	m_gsp_speedup_pc = 0xffc00f10;
4298	4298
4299	4299	/* set up msp speedup handler */
4300		m_msp_speedup_addr = m_msp->space(AS_PROGRAM).install_legacy_write_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_w));
4301		m_msp->space(AS_PROGRAM).install_legacy_read_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_r));
	4300	m_msp_speedup_addr = m_msp->space(AS_PROGRAM).install_write_handler(0x00751b00, 0x00751b0f, write16_delegate(FUNC(harddriv_state::hdmsp_speedup_w), this));
	4301	m_msp->space(AS_PROGRAM).install_read_handler(0x00751b00, 0x00751b0f, read16_delegate(FUNC(harddriv_state::hdmsp_speedup_r), this));
4302	4302	m_msp_speedup_pc = 0x00723b00;
4303	4303
4304	4304	/* set up adsp speedup handlers */
4305		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r));
	4305	m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), this));
4306	4306	}
4307	4307
4308	4308
r26010	r26011
4314	4314	init_driver_sound(machine());
4315	4315
4316	4316	/* set up gsp speedup handler */
4317		m_gsp_speedup_addr[0] = m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup1_w));
4318		m_gsp_speedup_addr[1] = m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfffcfc00, 0xfffcfc0f, FUNC(hdgsp_speedup2_w));
4319		m_gsp->space(AS_PROGRAM).install_legacy_read_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup_r));
	4317	m_gsp_speedup_addr[0] = m_gsp->space(AS_PROGRAM).install_write_handler(0xfff9fc00, 0xfff9fc0f, write16_delegate(FUNC(harddriv_state::hdgsp_speedup1_w), this));
	4318	m_gsp_speedup_addr[1] = m_gsp->space(AS_PROGRAM).install_write_handler(0xfffcfc00, 0xfffcfc0f, write16_delegate(FUNC(harddriv_state::hdgsp_speedup2_w), this));
	4319	m_gsp->space(AS_PROGRAM).install_read_handler(0xfff9fc00, 0xfff9fc0f, read16_delegate(FUNC(harddriv_state::hdgsp_speedup_r), this));
4320	4320	m_gsp_speedup_pc = 0xfff40ff0;
4321	4321
4322	4322	/* set up msp speedup handler */
4323		m_msp_speedup_addr = m_msp->space(AS_PROGRAM).install_legacy_write_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_w));
4324		m_msp->space(AS_PROGRAM).install_legacy_read_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_r));
	4323	m_msp_speedup_addr = m_msp->space(AS_PROGRAM).install_write_handler(0x00751b00, 0x00751b0f, write16_delegate(FUNC(harddriv_state::hdmsp_speedup_w), this));
	4324	m_msp->space(AS_PROGRAM).install_read_handler(0x00751b00, 0x00751b0f, read16_delegate(FUNC(harddriv_state::hdmsp_speedup_r), this));
4325	4325	m_msp_speedup_pc = 0x00723b00;
4326	4326
4327	4327	/* set up adsp speedup handlers */
4328		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r));
	4328	m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), this));
4329	4329	}
4330	4330
4331	4331
r26010	r26011
4336	4336	init_adsp(machine());
4337	4337
4338	4338	/* set up gsp speedup handler */
4339		m_gsp_speedup_addr[0] = m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup1_w));
4340		m_gsp_speedup_addr[1] = m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfffcfc00, 0xfffcfc0f, FUNC(hdgsp_speedup2_w));
4341		m_gsp->space(AS_PROGRAM).install_legacy_read_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup_r));
	4339	m_gsp_speedup_addr[0] = m_gsp->space(AS_PROGRAM).install_write_handler(0xfff9fc00, 0xfff9fc0f, write16_delegate(FUNC(harddriv_state::hdgsp_speedup1_w), this));
	4340	m_gsp_speedup_addr[1] = m_gsp->space(AS_PROGRAM).install_write_handler(0xfffcfc00, 0xfffcfc0f, write16_delegate(FUNC(harddriv_state::hdgsp_speedup2_w), this));
	4341	m_gsp->space(AS_PROGRAM).install_read_handler(0xfff9fc00, 0xfff9fc0f, read16_delegate(FUNC(harddriv_state::hdgsp_speedup_r), this));
4342	4342	m_gsp_speedup_pc = 0xfff41070;
4343	4343
4344	4344	/* set up adsp speedup handlers */
4345		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r));
	4345	m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), this));
4346	4346	}
4347	4347
4348	4348
r26010	r26011
4356	4356
4357	4357	/* set up the slapstic */
4358	4358	slapstic_init(machine(), 117);
4359		m_m68k_slapstic_base = m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0xe0000, 0xfffff, FUNC(rd68k_slapstic_r), FUNC(rd68k_slapstic_w));
	4359	m_m68k_slapstic_base = m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xe0000, 0xfffff, read16_delegate(FUNC(harddriv_state::rd68k_slapstic_r), this), write16_delegate(FUNC(harddriv_state::rd68k_slapstic_w), this));
4360	4360
4361	4361	/* synchronization */
4362		m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x613c00, 0x613c03, FUNC(rddsp32_sync0_w));
4363		m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x613e00, 0x613e03, FUNC(rddsp32_sync1_w));
	4362	m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM).install_write_handler(0x613c00, 0x613c03, write32_delegate(FUNC(harddriv_state::rddsp32_sync0_w), this));
	4363	m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM).install_write_handler(0x613e00, 0x613e03, write32_delegate(FUNC(harddriv_state::rddsp32_sync1_w), this));
4364	4364
4365	4365	/* set up adsp speedup handlers */
4366		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r));
	4366	m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), this));
4367	4367	}
4368	4368
4369	4369
r26010	r26011
4379	4379
4380	4380	/* set up the slapstic */
4381	4381	slapstic_init(machine, 117);
4382		state->m_m68k_slapstic_base = state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0xe0000, 0xfffff, FUNC(rd68k_slapstic_r), FUNC(rd68k_slapstic_w));
	4382	state->m_m68k_slapstic_base = state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xe0000, 0xfffff, read16_delegate(FUNC(harddriv_state::rd68k_slapstic_r), state), write16_delegate(FUNC(harddriv_state::rd68k_slapstic_w), state));
4383	4383
4384	4384	/* synchronization */
4385		state->m_rddsp32_sync[0] = state->m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x613c00, 0x613c03, FUNC(rddsp32_sync0_w));
4386		state->m_rddsp32_sync[1] = state->m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x613e00, 0x613e03, FUNC(rddsp32_sync1_w));
	4385	state->m_rddsp32_sync[0] = state->m_dsp32->space(AS_PROGRAM).install_write_handler(0x613c00, 0x613c03, write32_delegate(FUNC(harddriv_state::rddsp32_sync0_w), state));
	4386	state->m_rddsp32_sync[1] = state->m_dsp32->space(AS_PROGRAM).install_write_handler(0x613e00, 0x613e03, write32_delegate(FUNC(harddriv_state::rddsp32_sync1_w), state));
4387	4387
4388	4388	/* set up protection hacks */
4389		state->m_gsp_protection = state->m_gsp->space(AS_PROGRAM).install_legacy_write_handler(gsp_protection, gsp_protection + 0x0f, FUNC(hdgsp_protection_w));
	4389	state->m_gsp_protection = state->m_gsp->space(AS_PROGRAM).install_write_handler(gsp_protection, gsp_protection + 0x0f, write16_delegate(FUNC(harddriv_state::hdgsp_protection_w), state));
4390	4390
4391	4391	/* set up gsp speedup handler */
4392		state->m_gsp_speedup_addr[0] = state->m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfff76f60, 0xfff76f6f, FUNC(rdgsp_speedup1_w));
4393		state->m_gsp->space(AS_PROGRAM).install_legacy_read_handler(0xfff76f60, 0xfff76f6f, FUNC(rdgsp_speedup1_r));
	4392	state->m_gsp_speedup_addr[0] = state->m_gsp->space(AS_PROGRAM).install_write_handler(0xfff76f60, 0xfff76f6f, write16_delegate(FUNC(harddriv_state::rdgsp_speedup1_w), state));
	4393	state->m_gsp->space(AS_PROGRAM).install_read_handler(0xfff76f60, 0xfff76f6f, read16_delegate(FUNC(harddriv_state::rdgsp_speedup1_r), state));
4394	4394	state->m_gsp_speedup_pc = 0xfff43a00;
4395	4395
4396	4396	/* set up adsp speedup handlers */
4397		state->m_adsp->space(AS_DATA).install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r));
	4397	state->m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), state));
4398	4398	}
4399	4399
4400	4400	DRIVER_INIT_MEMBER(harddriv_state,racedrivc) { racedrivc_init_common(machine(), 0xfff95cd0); }
r26010	r26011
4437	4437	/* set up the SLOOP */
4438	4438	if (!proto_sloop)
4439	4439	{
4440		state->m_m68k_slapstic_base = state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0xe0000, 0xfffff, FUNC(st68k_sloop_r), FUNC(st68k_sloop_w));
4441		state->m_m68k_sloop_alt_base = state->m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0x4e000, 0x4ffff, FUNC(st68k_sloop_alt_r));
	4440	state->m_m68k_slapstic_base = state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xe0000, 0xfffff, read16_delegate(FUNC(harddriv_state::st68k_sloop_r), state),  write16_delegate(FUNC(harddriv_state::st68k_sloop_w), state));
	4441	state->m_m68k_sloop_alt_base = state->m_maincpu->space(AS_PROGRAM).install_read_handler(0x4e000, 0x4ffff, read16_delegate(FUNC(harddriv_state::st68k_sloop_alt_r), state));
4442	4442	}
4443	4443	else
4444		state->m_m68k_slapstic_base = state->m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0xe0000, 0xfffff, FUNC(st68k_protosloop_r), FUNC(st68k_protosloop_w));
	4444	state->m_m68k_slapstic_base = state->m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xe0000, 0xfffff, read16_delegate(FUNC(harddriv_state::st68k_protosloop_r), state), write16_delegate(FUNC(harddriv_state::st68k_protosloop_w), state));
4445	4445
4446	4446	/* set up protection hacks */
4447		state->m_gsp_protection = state->m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfff965d0, 0xfff965df, FUNC(hdgsp_protection_w));
	4447	state->m_gsp_protection = state->m_gsp->space(AS_PROGRAM).install_write_handler(0xfff965d0, 0xfff965df, write16_delegate(FUNC(harddriv_state::hdgsp_protection_w), state));
4448	4448
4449	4449	/* set up adsp speedup handlers */
4450		state->m_adsp->space(AS_DATA).install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r));
4451		state->m_adsp->space(AS_DATA).install_legacy_read_handler(0x1f99, 0x1f99, FUNC(hdds3_speedup_r));
	4450	state->m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), state));
	4451	state->m_adsp->space(AS_DATA).install_read_handler(0x1f99, 0x1f99, read16_delegate(FUNC(harddriv_state::hdds3_speedup_r), state));
4452	4452	state->m_ds3_speedup_addr = &state->m_adsp_data_memory[0x1f99];
4453	4453	state->m_ds3_speedup_pc = 0xff;
4454	4454	state->m_ds3_transfer_pc = ds3_transfer_pc;
r26010	r26011
4480	4480
4481	4481	/* set up the slapstic */
4482	4482	slapstic_init(machine(), 117);
4483		m_m68k_slapstic_base = m_maincpu->space(AS_PROGRAM).install_legacy_readwrite_handler(0xe0000, 0xfffff, FUNC(rd68k_slapstic_r), FUNC(rd68k_slapstic_w));
	4483	m_m68k_slapstic_base = m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xe0000, 0xfffff, read16_delegate(FUNC(harddriv_state::rd68k_slapstic_r), this), write16_delegate(FUNC(harddriv_state::rd68k_slapstic_w), this));
4484	4484
4485		m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0xa80000, 0xafffff, FUNC(hda68k_port1_r));
	4485	m_maincpu->space(AS_PROGRAM).install_read_handler(0xa80000, 0xafffff, read16_delegate(FUNC(harddriv_state::hda68k_port1_r), this));
4486	4486
4487	4487	/* synchronization */
4488		m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x613c00, 0x613c03, FUNC(rddsp32_sync0_w));
4489		m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x613e00, 0x613e03, FUNC(rddsp32_sync1_w));
	4488	m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM).install_write_handler(0x613c00, 0x613c03, write32_delegate(FUNC(harddriv_state::rddsp32_sync0_w), this));
	4489	m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM).install_write_handler(0x613e00, 0x613e03, write32_delegate(FUNC(harddriv_state::rddsp32_sync1_w), this));
4490	4490
4491	4491	/* set up protection hacks */
4492		m_gsp_protection = m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfff960a0, 0xfff960af, FUNC(hdgsp_protection_w));
	4492	m_gsp_protection = m_gsp->space(AS_PROGRAM).install_write_handler(0xfff960a0, 0xfff960af, write16_delegate(FUNC(harddriv_state::hdgsp_protection_w), this));
4493	4493
4494	4494	/* set up adsp speedup handlers */
4495		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r));
4496		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1f99, 0x1f99, FUNC(hdds3_speedup_r));
	4495	m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), this));
	4496	m_adsp->space(AS_DATA).install_read_handler(0x1f99, 0x1f99, read16_delegate(FUNC(harddriv_state::hdds3_speedup_r), this));
4497	4497	m_ds3_speedup_addr = &m_adsp_data_memory[0x1f99];
4498	4498	m_ds3_speedup_pc = 0xff;
4499	4499	m_ds3_transfer_pc = 0x43672;
r26010	r26011
4507	4507	init_ds3(machine());
4508	4508	init_dsk2(machine());
4509	4509
4510		m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0xa80000, 0xafffff, FUNC(hda68k_port1_r));
	4510	m_maincpu->space(AS_PROGRAM).install_read_handler(0xa80000, 0xafffff, read16_delegate(FUNC(harddriv_state::hda68k_port1_r), this));
4511	4511
4512	4512	/* synchronization */
4513		m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x21fe00, 0x21fe03, FUNC(rddsp32_sync0_w));
4514		m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x21ff00, 0x21ff03, FUNC(rddsp32_sync1_w));
	4513	m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM).install_write_handler(0x613c00, 0x613c03, write32_delegate(FUNC(harddriv_state::rddsp32_sync0_w), this));
	4514	m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM).install_write_handler(0x613e00, 0x613e03, write32_delegate(FUNC(harddriv_state::rddsp32_sync1_w), this));
4515	4515
4516	4516	/* set up protection hacks */
4517		m_gsp_protection = m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfff943f0, 0xfff943ff, FUNC(hdgsp_protection_w));
	4517	m_gsp_protection = m_gsp->space(AS_PROGRAM).install_write_handler(0xfff960a0, 0xfff960af, write16_delegate(FUNC(harddriv_state::hdgsp_protection_w), this));
4518	4518
4519	4519	/* set up adsp speedup handlers */
4520		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r));
4521		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1f99, 0x1f99, FUNC(hdds3_speedup_r));
	4520	m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), this));
	4521	m_adsp->space(AS_DATA).install_read_handler(0x1f99, 0x1f99, read16_delegate(FUNC(harddriv_state::hdds3_speedup_r), this));
4522	4522	m_ds3_speedup_addr = &m_adsp_data_memory[0x1f99];
4523	4523	m_ds3_speedup_pc = 0x2da;
4524	4524	m_ds3_transfer_pc = 0x407b8;
r26010	r26011
4532	4532	init_ds3(machine());
4533	4533	init_dsk2(machine());
4534	4534
4535		m_maincpu->space(AS_PROGRAM).install_legacy_read_handler(0xa80000, 0xafffff, FUNC(hda68k_port1_r));
	4535	m_maincpu->space(AS_PROGRAM).install_read_handler(0xa80000, 0xafffff, read16_delegate(FUNC(harddriv_state::hda68k_port1_r), this));
4536	4536
4537	4537	/* synchronization */
4538		m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x21fe00, 0x21fe03, FUNC(rddsp32_sync0_w));
4539		m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM).install_legacy_write_handler(0x21ff00, 0x21ff03, FUNC(rddsp32_sync1_w));
	4538	m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM).install_write_handler(0x613c00, 0x613c03, write32_delegate(FUNC(harddriv_state::rddsp32_sync0_w), this));
	4539	m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM).install_write_handler(0x613e00, 0x613e03, write32_delegate(FUNC(harddriv_state::rddsp32_sync1_w), this));
4540	4540
4541	4541	/* set up protection hacks */
4542		m_gsp_protection = m_gsp->space(AS_PROGRAM).install_legacy_write_handler(0xfff916c0, 0xfff916cf, FUNC(hdgsp_protection_w));
	4542	m_gsp_protection = m_gsp->space(AS_PROGRAM).install_write_handler(0xfff916c0, 0xfff916cf, write16_delegate(FUNC(harddriv_state::hdgsp_protection_w), this));
4543	4543
4544	4544	/* set up adsp speedup handlers */
4545		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r));
4546		m_adsp->space(AS_DATA).install_legacy_read_handler(0x1f9a, 0x1f9a, FUNC(hdds3_speedup_r));
	4545	m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), this));
	4546	m_adsp->space(AS_DATA).install_read_handler(0x1f9a, 0x1f9a, read16_delegate(FUNC(harddriv_state::hdds3_speedup_r), this));
4547	4547	m_ds3_speedup_addr = &m_adsp_data_memory[0x1f9a];
4548	4548	m_ds3_speedup_pc = 0x2d9;
4549	4549	m_ds3_transfer_pc = 0X407da;

trunk/src/mame/machine/harddriv.c

r26010	r26011
127	127	}
128	128
129	129
130		WRITE16_HANDLER( hd68k_irq_ack_w )
	130	WRITE16_MEMBER( harddriv_state::hd68k_irq_ack_w )
131	131	{
132		harddriv_state *state = space.machine().driver_data<harddriv_state>();
133		state->m_irq_state = 0;
134		state->update_interrupts();
	132	m_irq_state = 0;
	133	update_interrupts();
135	134	}
136	135
137	136
r26010	r26011
158	157	*
159	158	*************************************/
160	159
161		READ16_HANDLER( hd68k_gsp_io_r )
	160	READ16_MEMBER( harddriv_state::hd68k_gsp_io_r )
162	161	{
163		harddriv_state *state = space.machine().driver_data<harddriv_state>();
164	162	UINT16 result;
165	163	offset = (offset / 2) ^ 1;
166		state->m_hd34010_host_access = TRUE;
167		result = tms34010_host_r(state->m_gsp, offset);
168		state->m_hd34010_host_access = FALSE;
	164	m_hd34010_host_access = TRUE;
	165	result = tms34010_host_r(m_gsp, offset);
	166	m_hd34010_host_access = FALSE;
169	167	return result;
170	168	}
171	169
172	170
173		WRITE16_HANDLER( hd68k_gsp_io_w )
	171	WRITE16_MEMBER( harddriv_state::hd68k_gsp_io_w )
174	172	{
175		harddriv_state *state = space.machine().driver_data<harddriv_state>();
176	173	offset = (offset / 2) ^ 1;
177		state->m_hd34010_host_access = TRUE;
178		tms34010_host_w(state->m_gsp, offset, data);
179		state->m_hd34010_host_access = FALSE;
	174	m_hd34010_host_access = TRUE;
	175	tms34010_host_w(m_gsp, offset, data);
	176	m_hd34010_host_access = FALSE;
180	177	}
181	178
182	179
r26010	r26011
187	184	*
188	185	*************************************/
189	186
190		READ16_HANDLER( hd68k_msp_io_r )
	187	READ16_MEMBER( harddriv_state::hd68k_msp_io_r )
191	188	{
192		harddriv_state *state = space.machine().driver_data<harddriv_state>();
193	189	UINT16 result;
194	190	offset = (offset / 2) ^ 1;
195		state->m_hd34010_host_access = TRUE;
196		result = (state->m_msp != NULL) ? tms34010_host_r(state->m_msp, offset) : 0xffff;
197		state->m_hd34010_host_access = FALSE;
	191	m_hd34010_host_access = TRUE;
	192	result = (m_msp != NULL) ? tms34010_host_r(m_msp, offset) : 0xffff;
	193	m_hd34010_host_access = FALSE;
198	194	return result;
199	195	}
200	196
201	197
202		WRITE16_HANDLER( hd68k_msp_io_w )
	198	WRITE16_MEMBER( harddriv_state::hd68k_msp_io_w )
203	199	{
204		harddriv_state *state = space.machine().driver_data<harddriv_state>();
205	200	offset = (offset / 2) ^ 1;
206		if (state->m_msp != NULL)
	201	if (m_msp != NULL)
207	202	{
208		state->m_hd34010_host_access = TRUE;
209		tms34010_host_w(state->m_msp, offset, data);
210		state->m_hd34010_host_access = FALSE;
	203	m_hd34010_host_access = TRUE;
	204	tms34010_host_w(m_msp, offset, data);
	205	m_hd34010_host_access = FALSE;
211	206	}
212	207	}
213	208
r26010	r26011
219	214	*
220	215	*************************************/
221	216
222		READ16_HANDLER( hd68k_port0_r )
	217	READ16_MEMBER( harddriv_state::hd68k_port0_r )
223	218	{
224	219	/* port is as follows:
225	220
r26010	r26011
236	231	.....
237	232	0x8000 = SW1 #1
238	233	*/
239		harddriv_state *state = space.machine().driver_data<harddriv_state>();
240		int temp = (space.machine().root_device().ioport("SW1")->read() << 8) | space.machine().root_device().ioport("IN0")->read();
241		if (state->get_hblank(*state->m_screen)) temp ^= 0x0002;
	234	int temp = (ioport("SW1")->read() << 8) | ioport("IN0")->read();
	235	if (get_hblank(*m_screen)) temp ^= 0x0002;
242	236	temp ^= 0x0018;     /* both EOCs always high for now */
243	237	return temp;
244	238	}
245	239
246	240
247		READ16_HANDLER( hdc68k_port1_r )
	241	READ16_MEMBER( harddriv_state::hdc68k_port1_r )
248	242	{
249		harddriv_state *state = space.machine().driver_data<harddriv_state>();
250		UINT16 result = state->ioport("a80000")->read();
251		UINT16 diff = result ^ state->m_hdc68k_last_port1;
	243	UINT16 result = ioport("a80000")->read();
	244	UINT16 diff = result ^ m_hdc68k_last_port1;
252	245
253	246	/* if a new shifter position is selected, use it */
254	247	/* if it's the same shifter position as last time, go back to neutral */
255	248	if ((diff & 0x0100) && !(result & 0x0100))
256		state->m_hdc68k_shifter_state = (state->m_hdc68k_shifter_state == 1) ? 0 : 1;
	249	m_hdc68k_shifter_state = (m_hdc68k_shifter_state == 1) ? 0 : 1;
257	250	if ((diff & 0x0200) && !(result & 0x0200))
258		state->m_hdc68k_shifter_state = (state->m_hdc68k_shifter_state == 2) ? 0 : 2;
	251	m_hdc68k_shifter_state = (m_hdc68k_shifter_state == 2) ? 0 : 2;
259	252	if ((diff & 0x0400) && !(result & 0x0400))
260		state->m_hdc68k_shifter_state = (state->m_hdc68k_shifter_state == 4) ? 0 : 4;
	253	m_hdc68k_shifter_state = (m_hdc68k_shifter_state == 4) ? 0 : 4;
261	254	if ((diff & 0x0800) && !(result & 0x0800))
262		state->m_hdc68k_shifter_state = (state->m_hdc68k_shifter_state == 8) ? 0 : 8;
	255	m_hdc68k_shifter_state = (m_hdc68k_shifter_state == 8) ? 0 : 8;
263	256
264	257	/* merge in the new shifter value */
265		result = (result | 0x0f00) ^ (state->m_hdc68k_shifter_state << 8);
	258	result = (result | 0x0f00) ^ (m_hdc68k_shifter_state << 8);
266	259
267	260	/* merge in the wheel edge latch bit */
268		if (state->m_hdc68k_wheel_edge)
	261	if (m_hdc68k_wheel_edge)
269	262	result ^= 0x4000;
270	263
271		state->m_hdc68k_last_port1 = result;
	264	m_hdc68k_last_port1 = result;
272	265	return result;
273	266	}
274	267
275	268
276		READ16_HANDLER( hda68k_port1_r )
	269	READ16_MEMBER( harddriv_state::hda68k_port1_r )
277	270	{
278		harddriv_state *state = space.machine().driver_data<harddriv_state>();
279		UINT16 result = state->ioport("a80000")->read();
	271	UINT16 result = ioport("a80000")->read();
280	272
281	273	/* merge in the wheel edge latch bit */
282		if (state->m_hdc68k_wheel_edge)
	274	if (m_hdc68k_wheel_edge)
283	275	result ^= 0x4000;
284	276
285	277	return result;
286	278	}
287	279
288	280
289		READ16_HANDLER( hdc68k_wheel_r )
	281	READ16_MEMBER( harddriv_state::hdc68k_wheel_r )
290	282	{
291		harddriv_state *state = space.machine().driver_data<harddriv_state>();
292
293	283	/* grab the new wheel value and upconvert to 12 bits */
294		UINT16 new_wheel = state->ioport("12BADC0")->read() << 4;
	284	UINT16 new_wheel = ioport("12BADC0")->read() << 4;
295	285
296	286	/* hack to display the wheel position */
297	287	if (space.machine().input().code_pressed(KEYCODE_LSHIFT))
298	288	popmessage("%04X", new_wheel);
299	289
300	290	/* if we crossed the center line, latch the edge bit */
301		if ((state->m_hdc68k_last_wheel / 0xf0) != (new_wheel / 0xf0))
302		state->m_hdc68k_wheel_edge = 1;
	291	if ((m_hdc68k_last_wheel / 0xf0) != (new_wheel / 0xf0))
	292	m_hdc68k_wheel_edge = 1;
303	293
304	294	/* remember the last value and return the low 8 bits */
305		state->m_hdc68k_last_wheel = new_wheel;
	295	m_hdc68k_last_wheel = new_wheel;
306	296	return (new_wheel << 8) | 0xff;
307	297	}
308	298
309	299
310		READ16_HANDLER( hd68k_adc8_r )
	300	READ16_MEMBER( harddriv_state::hd68k_adc8_r )
311	301	{
312		harddriv_state *state = space.machine().driver_data<harddriv_state>();
313		return state->m_adc8_data;
	302	return m_adc8_data;
314	303	}
315	304
316	305
317		READ16_HANDLER( hd68k_adc12_r )
	306	READ16_MEMBER( harddriv_state::hd68k_adc12_r )
318	307	{
319		harddriv_state *state = space.machine().driver_data<harddriv_state>();
320		return state->m_adc12_byte ? ((state->m_adc12_data >> 8) & 0x0f) : (state->m_adc12_data & 0xff);
	308	return m_adc12_byte ? ((m_adc12_data >> 8) & 0x0f) : (m_adc12_data & 0xff);
321	309	}
322	310
323	311
324		READ16_HANDLER( hd68k_sound_reset_r )
	312	READ16_MEMBER( harddriv_state::hd68k_sound_reset_r )
325	313	{
326		harddriv_state *state = space.machine().driver_data<harddriv_state>();
327		if (state->m_jsa != NULL)
328		state->m_jsa->reset();
	314	if (m_jsa != NULL)
	315	m_jsa->reset();
329	316	return ~0;
330	317	}
331	318
r26010	r26011
337	324	*
338	325	*************************************/
339	326
340		WRITE16_HANDLER( hd68k_adc_control_w )
	327	WRITE16_MEMBER( harddriv_state::hd68k_adc_control_w )
341	328	{
342	329	static const char *const adc8names[] = { "8BADC0", "8BADC1", "8BADC2", "8BADC3", "8BADC4", "8BADC5", "8BADC6", "8BADC7" };
343	330	static const char *const adc12names[] = { "12BADC0", "12BADC1", "12BADC2", "12BADC3" };
344		harddriv_state *state = space.machine().driver_data<harddriv_state>();
	331
	332	COMBINE_DATA(&m_adc_control);
345	333
346		COMBINE_DATA(&state->m_adc_control);
347
348	334	/* handle a write to the 8-bit ADC address select */
349		if (state->m_adc_control & 0x08)
	335	if (m_adc_control & 0x08)
350	336	{
351		state->m_adc8_select = state->m_adc_control & 0x07;
352		state->m_adc8_data = state->ioport(adc8names[state->m_adc8_select])->read();
	337	m_adc8_select = m_adc_control & 0x07;
	338	m_adc8_data = ioport(adc8names[m_adc8_select])->read();
353	339	}
354	340
355	341	/* handle a write to the 12-bit ADC address select */
356		if (state->m_adc_control & 0x40)
	342	if (m_adc_control & 0x40)
357	343	{
358		state->m_adc12_select = (state->m_adc_control >> 4) & 0x03;
359		state->m_adc12_data = space.machine().root_device().ioport(adc12names[state->m_adc12_select])->read() << 4;
	344	m_adc12_select = (m_adc_control >> 4) & 0x03;
	345	m_adc12_data = space.machine().root_device().ioport(adc12names[m_adc12_select])->read() << 4;
360	346	}
361	347
362	348	/* bit 7 selects which byte of the 12 bit data to read */
363		state->m_adc12_byte = (state->m_adc_control >> 7) & 1;
	349	m_adc12_byte = (m_adc_control >> 7) & 1;
364	350	}
365	351
366	352
367		WRITE16_HANDLER( hd68k_wr0_write )
	353	WRITE16_MEMBER( harddriv_state::hd68k_wr0_write )
368	354	{
369	355	/* bit 3 selects the value; data is ignored */
370	356	data = (offset >> 3) & 1;
r26010	r26011
389	375	}
390	376
391	377
392		WRITE16_HANDLER( hd68k_wr1_write )
	378	WRITE16_MEMBER( harddriv_state::hd68k_wr1_write )
393	379	{
394	380	if (offset == 0) { //   logerror("Shifter Interface Latch = %02X\n", data);
395	381	} else {                logerror("/WR1(%04X)=%02X\n", offset, data);
r26010	r26011
397	383	}
398	384
399	385
400		WRITE16_HANDLER( hd68k_wr2_write )
	386	WRITE16_MEMBER( harddriv_state::hd68k_wr2_write )
401	387	{
402	388	if (offset == 0) { //   logerror("Steering Wheel Latch = %02X\n", data);
403	389	} else {                logerror("/WR2(%04X)=%02X\n", offset, data);
r26010	r26011
405	391	}
406	392
407	393
408		WRITE16_HANDLER( hd68k_nwr_w )
	394	WRITE16_MEMBER( harddriv_state::hd68k_nwr_w )
409	395	{
410		harddriv_state *state = space.machine().driver_data<harddriv_state>();
411
412	396	/* bit 3 selects the value; data is ignored */
413	397	data = (offset >> 3) & 1;
414	398
r26010	r26011
425	409	case 3: /* LC2 */
426	410	break;
427	411	case 4: /* ZP1 */
428		state->m_m68k_zp1 = data;
	412	m_m68k_zp1 = data;
429	413	break;
430	414	case 5: /* ZP2 */
431		state->m_m68k_zp2 = data;
	415	m_m68k_zp2 = data;
432	416	break;
433	417	case 6: /* /GSPRES */
434	418	logerror("Write to /GSPRES(%d)\n", data);
435		if (state->m_gsp != NULL)
436		state->m_gsp->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);
	419	if (m_gsp != NULL)
	420	m_gsp->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);
437	421	break;
438	422	case 7: /* /MSPRES */
439	423	logerror("Write to /MSPRES(%d)\n", data);
440		if (state->m_msp != NULL)
441		state->m_msp->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);
	424	if (m_msp != NULL)
	425	m_msp->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);
442	426	break;
443	427	}
444	428	}
445	429
446	430
447		WRITE16_HANDLER( hdc68k_wheel_edge_reset_w )
	431	WRITE16_MEMBER( harddriv_state::hdc68k_wheel_edge_reset_w )
448	432	{
449	433	/* reset the edge latch */
450		harddriv_state *state = space.machine().driver_data<harddriv_state>();
451		state->m_hdc68k_wheel_edge = 0;
	434	m_hdc68k_wheel_edge = 0;
452	435	}
453	436
454	437
r26010	r26011
459	442	*
460	443	*************************************/
461	444
462		READ16_HANDLER( hd68k_zram_r )
	445	READ16_MEMBER( harddriv_state::hd68k_zram_r )
463	446	{
464		harddriv_state *state = space.machine().driver_data<harddriv_state>();
465		return state->m_zram[offset];
	447	return m_zram[offset];
466	448	}
467	449
468	450
469		WRITE16_HANDLER( hd68k_zram_w )
	451	WRITE16_MEMBER( harddriv_state::hd68k_zram_w )
470	452	{
471		harddriv_state *state = space.machine().driver_data<harddriv_state>();
472		if (state->m_m68k_zp1 == 0 && state->m_m68k_zp2 == 1)
473		COMBINE_DATA(&state->m_zram[offset]);
	453	if (m_m68k_zp1 == 0 && m_m68k_zp2 == 1)
	454	COMBINE_DATA(&m_zram[offset]);
474	455	}
475	456
476	457
r26010	r26011
494	475	*
495	476	*************************************/
496	477
497		WRITE16_HANDLER( hdgsp_io_w )
	478	WRITE16_MEMBER( harddriv_state::hdgsp_io_w )
498	479	{
499		harddriv_state *state = space.machine().driver_data<harddriv_state>();
500
501	480	/* detect an enabling of the shift register and force yielding */
502	481	if (offset == REG_DPYCTL)
503	482	{
504	483	UINT8 new_shiftreg = (data >> 11) & 1;
505		if (new_shiftreg != state->m_last_gsp_shiftreg)
	484	if (new_shiftreg != m_last_gsp_shiftreg)
506	485	{
507		state->m_last_gsp_shiftreg = new_shiftreg;
	486	m_last_gsp_shiftreg = new_shiftreg;
508	487	if (new_shiftreg)
509	488	space.device().execute().yield();
510	489	}
r26010	r26011
512	491
513	492	/* detect changes to HEBLNK and HSBLNK and force an update before they change */
514	493	if ((offset == REG_HEBLNK || offset == REG_HSBLNK) && data != tms34010_io_register_r(space, offset, 0xffff))
515		state->m_screen->update_partial(state->m_screen->vpos() - 1);
	494	m_screen->update_partial(m_screen->vpos() - 1);
516	495
517	496	tms34010_io_register_w(space, offset, data, mem_mask);
518	497	}
r26010	r26011
525	504	*
526	505	*************************************/
527	506
528		WRITE16_HANDLER( hdgsp_protection_w )
	507	WRITE16_MEMBER( harddriv_state::hdgsp_protection_w )
529	508	{
530		harddriv_state *state = space.machine().driver_data<harddriv_state>();
531
532	509	/* this memory address is incremented whenever a protection check fails */
533	510	/* after it reaches a certain value, the GSP will randomly trash a */
534	511	/* register; we just prevent it from ever going above 0 */
535		*state->m_gsp_protection = 0;
	512	*m_gsp_protection = 0;
536	513	}
537	514
538	515
r26010	r26011
547	524	*
548	525	*************************************/
549	526
550		READ16_HANDLER( hd68k_adsp_program_r )
	527	READ16_MEMBER( harddriv_state::hd68k_adsp_program_r )
551	528	{
552		harddriv_state *state = space.machine().driver_data<harddriv_state>();
553		UINT32 word = state->m_adsp_pgm_memory[offset/2];
	529	UINT32 word = m_adsp_pgm_memory[offset/2];
554	530	return (!(offset & 1)) ? (word >> 16) : (word & 0xffff);
555	531	}
556	532
557	533
558		WRITE16_HANDLER( hd68k_adsp_program_w )
	534	WRITE16_MEMBER( harddriv_state::hd68k_adsp_program_w )
559	535	{
560		harddriv_state *state = space.machine().driver_data<harddriv_state>();
561		UINT32 *base = &state->m_adsp_pgm_memory[offset/2];
	536	UINT32 *base = &m_adsp_pgm_memory[offset/2];
562	537	UINT32 oldword = *base;
563	538	UINT16 temp;
564	539
r26010	r26011
585	560	*
586	561	*************************************/
587	562
588		READ16_HANDLER( hd68k_adsp_data_r )
	563	READ16_MEMBER( harddriv_state::hd68k_adsp_data_r )
589	564	{
590		harddriv_state *state = space.machine().driver_data<harddriv_state>();
591		return state->m_adsp_data_memory[offset];
	565	return m_adsp_data_memory[offset];
592	566	}
593	567
594	568
595		WRITE16_HANDLER( hd68k_adsp_data_w )
	569	WRITE16_MEMBER( harddriv_state::hd68k_adsp_data_w )
596	570	{
597		harddriv_state *state = space.machine().driver_data<harddriv_state>();
	571	COMBINE_DATA(&m_adsp_data_memory[offset]);
598	572
599		COMBINE_DATA(&state->m_adsp_data_memory[offset]);
600
601	573	/* any write to $1FFF is taken to be a trigger; synchronize the CPUs */
602	574	if (offset == 0x1fff)
603	575	{
604	576	logerror("%06X:ADSP sync address written (%04X)\n", space.device().safe_pcbase(), data);
605	577	space.machine().scheduler().synchronize();
606		state->m_adsp->signal_interrupt_trigger();
	578	m_adsp->signal_interrupt_trigger();
607	579	}
608	580	else
609	581	logerror("%06X:ADSP W@%04X (%04X)\n", space.device().safe_pcbase(), offset, data);
r26010	r26011
617	589	*
618	590	*************************************/
619	591
620		READ16_HANDLER( hd68k_adsp_buffer_r )
	592	READ16_MEMBER( harddriv_state::hd68k_adsp_buffer_r )
621	593	{
622		harddriv_state *state = space.machine().driver_data<harddriv_state>();
623		/*  logerror("hd68k_adsp_buffer_r(%04X)\n", offset);*/
624		return state->m_som_memory[state->m_m68k_adsp_buffer_bank * 0x2000 + offset];
	594	/*  logerror("hd68k_adsp_buffer_r(%04X)\n", offset);*/
	595	return m_som_memory[m_m68k_adsp_buffer_bank * 0x2000 + offset];
625	596	}
626	597
627	598
628		WRITE16_HANDLER( hd68k_adsp_buffer_w )
	599	WRITE16_MEMBER( harddriv_state::hd68k_adsp_buffer_w )
629	600	{
630		harddriv_state *state = space.machine().driver_data<harddriv_state>();
631		COMBINE_DATA(&state->m_som_memory[state->m_m68k_adsp_buffer_bank * 0x2000 + offset]);
	601	COMBINE_DATA(&m_som_memory[m_m68k_adsp_buffer_bank * 0x2000 + offset]);
632	602	}
633	603
634	604
r26010	r26011
690	660	}
691	661
692	662
693		WRITE16_HANDLER( hd68k_adsp_control_w )
	663	WRITE16_MEMBER( harddriv_state::hd68k_adsp_control_w )
694	664	{
695		harddriv_state *state = space.machine().driver_data<harddriv_state>();
696
697	665	/* bit 3 selects the value; data is ignored */
698	666	int val = (offset >> 3) & 1;
699	667
r26010	r26011
708	676
709	677	case 3:
710	678	logerror("ADSP bank = %d (deferred)\n", val);
711		space.machine().scheduler().synchronize(timer_expired_delegate(FUNC(harddriv_state::deferred_adsp_bank_switch),state), val);
	679	space.machine().scheduler().synchronize(timer_expired_delegate(FUNC(harddriv_state::deferred_adsp_bank_switch),this), val);
712	680	break;
713	681
714	682	case 5:
715	683	/* connected to the /BR (bus request) line; this effectively halts */
716	684	/* the ADSP at the next instruction boundary */
717		state->m_adsp_br = !val;
718		logerror("ADSP /BR = %d\n", !state->m_adsp_br);
719		if (state->m_adsp_br || state->m_adsp_halt)
720		state->m_adsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	685	m_adsp_br = !val;
	686	logerror("ADSP /BR = %d\n", !m_adsp_br);
	687	if (m_adsp_br || m_adsp_halt)
	688	m_adsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
721	689	else
722	690	{
723		state->m_adsp->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	691	m_adsp->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
724	692	/* a yield in this case is not enough */
725	693	/* we would need to increase the interleaving otherwise */
726	694	/* note that this only affects the test mode */
r26010	r26011
731	699	case 6:
732	700	/* connected to the /HALT line; this effectively halts */
733	701	/* the ADSP at the next instruction boundary */
734		state->m_adsp_halt = !val;
735		logerror("ADSP /HALT = %d\n", !state->m_adsp_halt);
736		if (state->m_adsp_br || state->m_adsp_halt)
737		state->m_adsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	702	m_adsp_halt = !val;
	703	logerror("ADSP /HALT = %d\n", !m_adsp_halt);
	704	if (m_adsp_br || m_adsp_halt)
	705	m_adsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
738	706	else
739	707	{
740		state->m_adsp->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	708	m_adsp->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
741	709	/* a yield in this case is not enough */
742	710	/* we would need to increase the interleaving otherwise */
743	711	/* note that this only affects the test mode */
r26010	r26011
747	715
748	716	case 7:
749	717	logerror("ADSP reset = %d\n", val);
750		state->m_adsp->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
	718	m_adsp->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
751	719	space.device().execute().yield();
752	720	break;
753	721
r26010	r26011
758	726	}
759	727
760	728
761		WRITE16_HANDLER( hd68k_adsp_irq_clear_w )
	729	WRITE16_MEMBER( harddriv_state::hd68k_adsp_irq_clear_w )
762	730	{
763		harddriv_state *state = space.machine().driver_data<harddriv_state>();
764	731	logerror("%06X:68k clears ADSP interrupt\n", space.device().safe_pcbase());
765		state->m_adsp_irq_state = 0;
766		state->update_interrupts();
	732	m_adsp_irq_state = 0;
	733	update_interrupts();
767	734	}
768	735
769	736
770		READ16_HANDLER( hd68k_adsp_irq_state_r )
	737	READ16_MEMBER( harddriv_state::hd68k_adsp_irq_state_r )
771	738	{
772		harddriv_state *state = space.machine().driver_data<harddriv_state>();
773	739	int result = 0xfffd;
774		if (state->m_adsp_xflag) result ^= 2;
775		if (state->m_adsp_irq_state) result ^= 1;
	740	if (m_adsp_xflag) result ^= 2;
	741	if (m_adsp_irq_state) result ^= 1;
776	742	logerror("%06X:68k reads ADSP interrupt state = %04x\n", space.device().safe_pcbase(), result);
777	743	return result;
778	744	}
r26010	r26011
785	751	*
786	752	*************************************/
787	753
788		READ16_HANDLER( hdadsp_special_r )
	754	READ16_MEMBER( harddriv_state::hdadsp_special_r )
789	755	{
790		harddriv_state *state = space.machine().driver_data<harddriv_state>();
791	756	switch (offset & 7)
792	757	{
793	758	case 0: /* /SIMBUF */
794		if (state->m_adsp_eprom_base + state->m_adsp_sim_address < state->m_sim_memory_size)
795		return state->m_sim_memory[state->m_adsp_eprom_base + state->m_adsp_sim_address++];
	759	if (m_adsp_eprom_base + m_adsp_sim_address < m_sim_memory_size)
	760	return m_sim_memory[m_adsp_eprom_base + m_adsp_sim_address++];
796	761	else
797	762	return 0xff;
798	763
r26010	r26011
813	778	}
814	779
815	780
816		WRITE16_HANDLER( hdadsp_special_w )
	781	WRITE16_MEMBER( harddriv_state::hdadsp_special_w )
817	782	{
818		harddriv_state *state = space.machine().driver_data<harddriv_state>();
819	783	switch (offset & 7)
820	784	{
821	785	case 1: /* /SIMCLK */
822		state->m_adsp_sim_address = data;
	786	m_adsp_sim_address = data;
823	787	break;
824	788
825	789	case 2: /* SOMLATCH */
826		state->m_som_memory[(state->m_m68k_adsp_buffer_bank ^ 1) * 0x2000 + (state->m_adsp_som_address++ & 0x1fff)] = data;
	790	m_som_memory[(m_m68k_adsp_buffer_bank ^ 1) * 0x2000 + (m_adsp_som_address++ & 0x1fff)] = data;
827	791	break;
828	792
829	793	case 3: /* /SOMCLK */
830		state->m_adsp_som_address = data;
	794	m_adsp_som_address = data;
831	795	break;
832	796
833	797	case 5: /* /XOUT */
834		state->m_adsp_xflag = data & 1;
	798	m_adsp_xflag = data & 1;
835	799	break;
836	800
837	801	case 6: /* /GINT */
838	802	logerror("%04X:ADSP signals interrupt\n", space.device().safe_pcbase());
839		state->m_adsp_irq_state = 1;
840		state->update_interrupts();
	803	m_adsp_irq_state = 1;
	804	update_interrupts();
841	805	break;
842	806
843	807	case 7: /* /MP */
844		state->m_adsp_eprom_base = 0x10000 * data;
	808	m_adsp_eprom_base = 0x10000 * data;
845	809	break;
846	810
847	811	default:
r26010	r26011
863	827	*
864	828	*************************************/
865	829
866		static void update_ds3_irq(harddriv_state *state)
	830	void harddriv_state::update_ds3_irq()
867	831	{
868	832	/* update the IRQ2 signal to the ADSP2101 */
869		if (!(!state->m_ds3_g68flag && state->m_ds3_g68irqs) && !(state->m_ds3_gflag && state->m_ds3_gfirqs))
870		state->m_adsp->set_input_line(ADSP2100_IRQ2, ASSERT_LINE);
	833	if (!(!m_ds3_g68flag && m_ds3_g68irqs) && !(m_ds3_gflag && m_ds3_gfirqs))
	834	m_adsp->set_input_line(ADSP2100_IRQ2, ASSERT_LINE);
871	835	else
872		state->m_adsp->set_input_line(ADSP2100_IRQ2, CLEAR_LINE);
	836	m_adsp->set_input_line(ADSP2100_IRQ2, CLEAR_LINE);
873	837	}
874	838
875	839
876		static void update_ds3_sirq(harddriv_state *state)
	840	void harddriv_state::update_ds3_sirq()
877	841	{
878	842	/* update the IRQ2 signal to the ADSP2105 */
879		if (!(!state->m_ds3_s68flag && state->m_ds3_s68irqs) && !(state->m_ds3_sflag && state->m_ds3_sfirqs))
880		state->m_ds3sdsp->set_input_line(ADSP2105_IRQ2, ASSERT_LINE);
	843	if (!(!m_ds3_s68flag && m_ds3_s68irqs) && !(m_ds3_sflag && m_ds3_sfirqs))
	844	m_ds3sdsp->set_input_line(ADSP2105_IRQ2, ASSERT_LINE);
881	845	else
882		state->m_ds3sdsp->set_input_line(ADSP2105_IRQ2, CLEAR_LINE);
	846	m_ds3sdsp->set_input_line(ADSP2105_IRQ2, CLEAR_LINE);
883	847	}
884	848
885	849
886		WRITE16_HANDLER( hd68k_ds3_control_w )
	850	WRITE16_MEMBER( harddriv_state::hd68k_ds3_control_w )
887	851	{
888		harddriv_state *state = space.machine().driver_data<harddriv_state>();
889	852	int val = (offset >> 3) & 1;
890	853
891	854	switch (offset & 7)
892	855	{
893	856	case 0:
894	857	/* SRES - reset sound CPU */
895		if (state->m_ds3sdsp)
	858	if (m_ds3sdsp)
896	859	{
897		state->m_ds3sdsp->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
898		state->m_ds3sdsp->load_boot_data(state->m_ds3sdsp->region()->base(), state->m_ds3sdsp_pgm_memory);
	860	m_ds3sdsp->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
	861	m_ds3sdsp->load_boot_data(m_ds3sdsp->region()->base(), m_ds3sdsp_pgm_memory);
899	862
900		if (val && !state->m_ds3_sreset)
	863	if (val && !m_ds3_sreset)
901	864	{
902		state->m_ds3_sflag = 0;
903		state->m_ds3_scmd = 0;
904		state->m_ds3_sfirqs = 0;
905		state->m_ds3_s68irqs = !state->m_ds3_sfirqs;
906		update_ds3_sirq(state);
	865	m_ds3_sflag = 0;
	866	m_ds3_scmd = 0;
	867	m_ds3_sfirqs = 0;
	868	m_ds3_s68irqs = !m_ds3_sfirqs;
	869	update_ds3_sirq();
907	870	}
908		state->m_ds3_sreset = val;
	871	m_ds3_sreset = val;
909	872	space.device().execute().yield();
910	873	}
911	874	break;
912	875
913	876	case 1:
914	877	/* XRES - reset sound helper CPU */
915		if (state->m_ds3xdsp)
	878	if (m_ds3xdsp)
916	879	{
917		state->m_ds3xdsp->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
918		state->m_ds3xdsp->load_boot_data(state->m_ds3xdsp->region()->base(), state->m_ds3xdsp_pgm_memory);
	880	m_ds3xdsp->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
	881	m_ds3xdsp->load_boot_data(m_ds3xdsp->region()->base(), m_ds3xdsp_pgm_memory);
919	882	}
920	883	break;
921	884
922	885	case 2:
923	886	/* connected to the /BR (bus request) line; this effectively halts */
924	887	/* the ADSP at the next instruction boundary */
925		state->m_adsp_br = !val;
926		if (state->m_adsp_br)
927		state->m_adsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	888	m_adsp_br = !val;
	889	if (m_adsp_br)
	890	m_adsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
928	891	else
929	892	{
930		state->m_adsp->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	893	m_adsp->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
931	894	/* a yield in this case is not enough */
932	895	/* we would need to increase the interleaving otherwise */
933	896	/* note that this only affects the test mode */
r26010	r26011
936	899	break;
937	900
938	901	case 3:
939		state->m_adsp->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
940		if (val && !state->m_ds3_reset)
	902	m_adsp->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
	903	if (val && !m_ds3_reset)
941	904	{
942		state->m_ds3_gflag = 0;
943		state->m_ds3_gcmd = 0;
944		state->m_ds3_gfirqs = 0;
945		state->m_ds3_g68irqs = !state->m_ds3_gfirqs;
946		state->m_ds3_send = 0;
947		update_ds3_irq(state);
	905	m_ds3_gflag = 0;
	906	m_ds3_gcmd = 0;
	907	m_ds3_gfirqs = 0;
	908	m_ds3_g68irqs = !m_ds3_gfirqs;
	909	m_ds3_send = 0;
	910	update_ds3_irq();
948	911	}
949		state->m_ds3_reset = val;
	912	m_ds3_reset = val;
950	913	space.device().execute().yield();
951	914	logerror("DS III reset = %d\n", val);
952	915	break;
r26010	r26011
969	932	*
970	933	*************************************/
971	934
972		READ16_HANDLER( hd68k_ds3_girq_state_r )
	935	READ16_MEMBER( harddriv_state::hd68k_ds3_girq_state_r )
973	936	{
974		harddriv_state *state = space.machine().driver_data<harddriv_state>();
975	937	int result = 0x0fff;
976		if (state->m_ds3_g68flag) result ^= 0x8000;
977		if (state->m_ds3_gflag) result ^= 0x4000;
978		if (state->m_ds3_g68irqs) result ^= 0x2000;
979		if (!state->m_adsp_irq_state) result ^= 0x1000;
	938	if (m_ds3_g68flag) result ^= 0x8000;
	939	if (m_ds3_gflag) result ^= 0x4000;
	940	if (m_ds3_g68irqs) result ^= 0x2000;
	941	if (!m_adsp_irq_state) result ^= 0x1000;
980	942	return result;
981	943	}
982	944
983	945
984		READ16_HANDLER( hd68k_ds3_gdata_r )
	946	READ16_MEMBER( harddriv_state::hd68k_ds3_gdata_r )
985	947	{
986		harddriv_state *state = space.machine().driver_data<harddriv_state>();
987	948	offs_t pc = space.device().safe_pc();
988	949
989		state->m_ds3_gflag = 0;
990		update_ds3_irq(state);
	950	m_ds3_gflag = 0;
	951	update_ds3_irq();
991	952
992		logerror("%06X:hd68k_ds3_gdata_r(%04X)\n", space.device().safe_pcbase(), state->m_ds3_gdata);
	953	logerror("%06X:hd68k_ds3_gdata_r(%04X)\n", space.device().safe_pcbase(), m_ds3_gdata);
993	954
994	955	/* attempt to optimize the transfer if conditions are right */
995		if (&space.device() == state->m_maincpu && pc == state->m_ds3_transfer_pc &&
996		!(!state->m_ds3_g68flag && state->m_ds3_g68irqs) && !(state->m_ds3_gflag && state->m_ds3_gfirqs))
	956	if (&space.device() == m_maincpu && pc == m_ds3_transfer_pc &&
	957	!(!m_ds3_g68flag && m_ds3_g68irqs) && !(m_ds3_gflag && m_ds3_gfirqs))
997	958	{
998		UINT32 destaddr = state->m_maincpu->state_int(M68K_A1);
999		UINT16 count68k = state->m_maincpu->state_int(M68K_D1);
1000		UINT16 mstat = state->m_adsp->state_int(ADSP2100_MSTAT);
1001		UINT16 i6 = state->m_adsp->state_int((mstat & 1) ? ADSP2100_MR0 : ADSP2100_MR0_SEC);
1002		UINT16 l6 = state->m_adsp->state_int(ADSP2100_L6) - 1;
1003		UINT16 m7 = state->m_adsp->state_int(ADSP2100_M7);
	959	UINT32 destaddr = m_maincpu->state_int(M68K_A1);
	960	UINT16 count68k = m_maincpu->state_int(M68K_D1);
	961	UINT16 mstat = m_adsp->state_int(ADSP2100_MSTAT);
	962	UINT16 i6 = m_adsp->state_int((mstat & 1) ? ADSP2100_MR0 : ADSP2100_MR0_SEC);
	963	UINT16 l6 = m_adsp->state_int(ADSP2100_L6) - 1;
	964	UINT16 m7 = m_adsp->state_int(ADSP2100_M7);
1004	965
1005		logerror("%06X:optimizing 68k transfer, %d words\n", state->m_maincpu->pcbase(), count68k);
	966	logerror("%06X:optimizing 68k transfer, %d words\n", m_maincpu->pcbase(), count68k);
1006	967
1007		while (count68k > 0 && state->m_adsp_data_memory[0x16e6] > 0)
	968	while (count68k > 0 && m_adsp_data_memory[0x16e6] > 0)
1008	969	{
1009		space.write_word(destaddr, state->m_ds3_gdata);
	970	space.write_word(destaddr, m_ds3_gdata);
1010	971	{
1011		state->m_adsp_data_memory[0x16e6]--;
1012		state->m_ds3_gdata = state->m_adsp_pgm_memory[i6] >> 8;
	972	m_adsp_data_memory[0x16e6]--;
	973	m_ds3_gdata = m_adsp_pgm_memory[i6] >> 8;
1013	974	i6 = (i6 & ~l6) | ((i6 + m7) & l6);
1014	975	}
1015	976	count68k--;
1016	977	}
1017		state->m_maincpu->set_state_int(M68K_D1, count68k);
1018		state->m_adsp->set_state_int((mstat & 1) ? ADSP2100_MR0 : ADSP2100_MR0_SEC, i6);
1019		state->m_adsp_speedup_count[1]++;
	978	m_maincpu->set_state_int(M68K_D1, count68k);
	979	m_adsp->set_state_int((mstat & 1) ? ADSP2100_MR0 : ADSP2100_MR0_SEC, i6);
	980	m_adsp_speedup_count[1]++;
1020	981	}
1021	982
1022	983	/* if we just cleared the IRQ, we are going to do some VERY timing critical reads */
r26010	r26011
1025	986	space.device().execute().spin_until_trigger(DS3_TRIGGER);
1026	987	space.machine().scheduler().trigger(DS3_TRIGGER, attotime::from_usec(5));
1027	988
1028		return state->m_ds3_gdata;
	989	return m_ds3_gdata;
1029	990	}
1030	991
1031	992
1032		WRITE16_HANDLER( hd68k_ds3_gdata_w )
	993	WRITE16_MEMBER( harddriv_state::hd68k_ds3_gdata_w )
1033	994	{
1034		harddriv_state *state = space.machine().driver_data<harddriv_state>();
	995	logerror("%06X:hd68k_ds3_gdata_w(%04X)\n", space.device().safe_pcbase(), m_ds3_gdata);
1035	996
1036		logerror("%06X:hd68k_ds3_gdata_w(%04X)\n", space.device().safe_pcbase(), state->m_ds3_gdata);
1037
1038		COMBINE_DATA(&state->m_ds3_g68data);
1039		state->m_ds3_g68flag = 1;
1040		state->m_ds3_gcmd = offset & 1;
1041		state->m_adsp->signal_interrupt_trigger();
1042		update_ds3_irq(state);
	997	COMBINE_DATA(&m_ds3_g68data);
	998	m_ds3_g68flag = 1;
	999	m_ds3_gcmd = offset & 1;
	1000	m_adsp->signal_interrupt_trigger();
	1001	update_ds3_irq();
1043	1002	}
1044	1003
1045	1004
r26010	r26011
1050	1009	*
1051	1010	*************************************/
1052	1011
1053		WRITE16_HANDLER( hd68k_ds3_sirq_clear_w )
	1012	WRITE16_MEMBER( harddriv_state::hd68k_ds3_sirq_clear_w )
1054	1013	{
1055		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1056	1014	logerror("%06X:68k clears ADSP interrupt\n", space.device().safe_pcbase());
1057		state->m_sound_int_state = 0;
1058		state->update_interrupts();
	1015	m_sound_int_state = 0;
	1016	update_interrupts();
1059	1017	}
1060	1018
1061	1019
1062		READ16_HANDLER( hd68k_ds3_sirq_state_r )
	1020	READ16_MEMBER( harddriv_state::hd68k_ds3_sirq_state_r )
1063	1021	{
1064		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1065	1022	int result = 0x0fff;
1066		if (state->m_ds3_s68flag) result ^= 0x8000;
1067		if (state->m_ds3_sflag) result ^= 0x4000;
1068		if (state->m_ds3_s68irqs) result ^= 0x2000;
1069		if (!state->m_sound_int_state) result ^= 0x1000;
	1023	if (m_ds3_s68flag) result ^= 0x8000;
	1024	if (m_ds3_sflag) result ^= 0x4000;
	1025	if (m_ds3_s68irqs) result ^= 0x2000;
	1026	if (!m_sound_int_state) result ^= 0x1000;
1070	1027	return result;
1071	1028	}
1072	1029
1073	1030
1074		READ16_HANDLER( hd68k_ds3_sdata_r )
	1031	READ16_MEMBER( harddriv_state::hd68k_ds3_sdata_r )
1075	1032	{
1076		harddriv_state *state = space.machine().driver_data<harddriv_state>();
	1033	m_ds3_sflag = 0;
	1034	update_ds3_sirq();
1077	1035
1078		state->m_ds3_sflag = 0;
1079		update_ds3_sirq(state);
1080
1081	1036	/* if we just cleared the IRQ, we are going to do some VERY timing critical reads */
1082	1037	/* it is important that all the CPUs be in sync before we continue, so spin a little */
1083	1038	/* while to let everyone else catch up */
1084	1039	space.device().execute().spin_until_trigger(DS3_STRIGGER);
1085	1040	space.machine().scheduler().trigger(DS3_STRIGGER, attotime::from_usec(5));
1086	1041
1087		return state->m_ds3_sdata;
	1042	return m_ds3_sdata;
1088	1043	}
1089	1044
1090	1045
1091		WRITE16_HANDLER( hd68k_ds3_sdata_w )
	1046	WRITE16_MEMBER( harddriv_state::hd68k_ds3_sdata_w )
1092	1047	{
1093		harddriv_state *state = space.machine().driver_data<harddriv_state>();
	1048	COMBINE_DATA(&m_ds3_s68data);
	1049	m_ds3_s68flag = 1;
	1050	m_ds3_scmd = offset & 1;
	1051	m_ds3sdsp->signal_interrupt_trigger();
1094	1052
1095		COMBINE_DATA(&state->m_ds3_s68data);
1096		state->m_ds3_s68flag = 1;
1097		state->m_ds3_scmd = offset & 1;
1098		state->m_ds3sdsp->signal_interrupt_trigger();
1099
1100		update_ds3_sirq(state);
	1053	update_ds3_sirq();
1101	1054	}
1102	1055
1103	1056
1104		READ16_HANDLER( hdds3_sdsp_special_r )
	1057	READ16_MEMBER( harddriv_state::hdds3_sdsp_special_r )
1105	1058	{
1106		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1107	1059	int result;
1108	1060
1109	1061	switch (offset & 7)
1110	1062	{
1111	1063	case 0:
1112		state->m_ds3_s68flag = 0;
1113		update_ds3_sirq(state);
1114		return state->m_ds3_s68data;
	1064	m_ds3_s68flag = 0;
	1065	update_ds3_sirq();
	1066	return m_ds3_s68data;
1115	1067
1116	1068	case 1:
1117	1069	result = 0x0fff;
1118		if (state->m_ds3_scmd) result ^= 0x8000;
1119		if (state->m_ds3_s68flag) result ^= 0x4000;
1120		if (state->m_ds3_sflag) result ^= 0x2000;
	1070	if (m_ds3_scmd) result ^= 0x8000;
	1071	if (m_ds3_s68flag) result ^= 0x4000;
	1072	if (m_ds3_sflag) result ^= 0x2000;
1121	1073	return result;
1122	1074
1123	1075	case 4:
1124		if (state->m_ds3_sdata_address < state->m_ds3_sdata_memory_size)
1125		return state->m_ds3_sdata_memory[state->m_ds3_sdata_address];
	1076	if (m_ds3_sdata_address < m_ds3_sdata_memory_size)
	1077	return m_ds3_sdata_memory[m_ds3_sdata_address];
1126	1078	else
1127	1079	return 0xff;
1128	1080
r26010	r26011
1140	1092	}
1141	1093
1142	1094
1143		WRITE16_HANDLER( hdds3_sdsp_special_w )
	1095	WRITE16_MEMBER( harddriv_state::hdds3_sdsp_special_w )
1144	1096	{
1145		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1146
1147	1097	/* Note: DS IV is slightly different */
1148	1098	switch (offset & 7)
1149	1099	{
1150	1100	case 0:
1151		state->m_ds3_sdata = data;
1152		state->m_ds3_sflag = 1;
1153		update_ds3_sirq(state);
	1101	m_ds3_sdata = data;
	1102	m_ds3_sflag = 1;
	1103	update_ds3_sirq();
1154	1104
1155	1105	/* once we've written data, trigger the main CPU to wake up again */
1156	1106	space.machine().scheduler().trigger(DS3_STRIGGER);
1157	1107	break;
1158	1108
1159	1109	case 1:
1160		state->m_sound_int_state = (data >> 1) & 1;
1161		state->update_interrupts();
	1110	m_sound_int_state = (data >> 1) & 1;
	1111	update_interrupts();
1162	1112	break;
1163	1113
1164	1114	case 2: /* bit 0 = T1 (unused) */
1165	1115	break;
1166	1116
1167	1117	case 3:
1168		state->m_ds3_sfirqs = (data >> 1) & 1;
1169		state->m_ds3_s68irqs = !state->m_ds3_sfirqs;
1170		update_ds3_sirq(state);
	1118	m_ds3_sfirqs = (data >> 1) & 1;
	1119	m_ds3_s68irqs = !m_ds3_sfirqs;
	1120	update_ds3_sirq();
1171	1121	break;
1172	1122
1173	1123	case 4:
1174		state->m_ds3dac1->write_signed16(data);
	1124	m_ds3dac1->write_signed16(data);
1175	1125	break;
1176	1126
1177	1127	case 5:
1178		state->m_ds3dac2->write_signed16(data);
	1128	m_ds3dac2->write_signed16(data);
1179	1129	break;
1180	1130
1181	1131	case 6:
1182		state->m_ds3_sdata_address = (state->m_ds3_sdata_address & 0xffff0000) | (data & 0xffff);
	1132	m_ds3_sdata_address = (m_ds3_sdata_address & 0xffff0000) | (data & 0xffff);
1183	1133	break;
1184	1134
1185	1135	case 7:
1186		state->m_ds3_sdata_address = (state->m_ds3_sdata_address & 0x0000ffff) | (data << 16);
	1136	m_ds3_sdata_address = (m_ds3_sdata_address & 0x0000ffff) | (data << 16);
1187	1137	break;
1188	1138	}
1189	1139	}
1190	1140
1191		READ16_HANDLER( hdds3_sdsp_control_r )
	1141	READ16_MEMBER( harddriv_state::hdds3_sdsp_control_r )
1192	1142	{
1193		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1194
1195	1143	switch (offset)
1196	1144	{
1197	1145	default:
1198		return state->m_ds3sdsp_regs[offset];
	1146	return m_ds3sdsp_regs[offset];
1199	1147	}
1200	1148
1201	1149	return 0xff;
1202	1150	}
1203	1151
1204	1152
1205		WRITE16_HANDLER( hdds3_sdsp_control_w )
	1153	WRITE16_MEMBER( harddriv_state::hdds3_sdsp_control_w )
1206	1154	{
1207		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1208
1209	1155	switch (offset)
1210	1156	{
1211	1157	case 0x1b:
1212	1158	// Scale
1213	1159	data &= 0xff;
1214	1160
1215		if (state->m_ds3sdsp_regs[0x1b] != data)
	1161	if (m_ds3sdsp_regs[0x1b] != data)
1216	1162	{
1217		state->m_ds3sdsp_regs[0x1b] = data;
	1163	m_ds3sdsp_regs[0x1b] = data;
1218	1164	hdds3sdsp_reset_timer(space.machine());
1219	1165	}
1220	1166	break;
1221	1167
1222	1168	case 0x1c:
1223	1169	// Count
1224		if (state->m_ds3sdsp_regs[0x1c] != data)
	1170	if (m_ds3sdsp_regs[0x1c] != data)
1225	1171	{
1226		state->m_ds3sdsp_regs[0x1c] = data;
	1172	m_ds3sdsp_regs[0x1c] = data;
1227	1173	hdds3sdsp_reset_timer(space.machine());
1228	1174	}
1229	1175	break;
1230	1176
1231	1177	case 0x1d:
1232	1178	// Period
1233		state->m_ds3sdsp_regs[0x1d] = data;
	1179	m_ds3sdsp_regs[0x1d] = data;
1234	1180	break;
1235	1181
1236	1182	case 0x1e:
1237		state->m_ds3sdsp_regs[0x1e] = data;
	1183	m_ds3sdsp_regs[0x1e] = data;
1238	1184	break;
1239	1185
1240	1186	case 0x1f:
r26010	r26011
1242	1188	if (data & 0x200)
1243	1189	{
1244	1190	UINT32 page = (data >> 6) & 7;
1245		state->m_ds3sdsp->load_boot_data(state->m_ds3sdsp->region()->base() + (0x2000 * page), state->m_ds3sdsp_pgm_memory);
1246		state->m_ds3sdsp->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
	1191	m_ds3sdsp->load_boot_data(m_ds3sdsp->region()->base() + (0x2000 * page), m_ds3sdsp_pgm_memory);
	1192	m_ds3sdsp->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
1247	1193	data &= ~0x200;
1248	1194	}
1249	1195
1250		state->m_ds3sdsp_regs[0x1f] = data;
	1196	m_ds3sdsp_regs[0x1f] = data;
1251	1197	break;
1252	1198
1253	1199	default:
1254		state->m_ds3sdsp_regs[offset] = data;
	1200	m_ds3sdsp_regs[offset] = data;
1255	1201	break;
1256	1202	}
1257	1203	}
1258	1204
1259	1205
1260		READ16_HANDLER( hdds3_xdsp_control_r )
	1206	READ16_MEMBER( harddriv_state::hdds3_xdsp_control_r )
1261	1207	{
1262		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1263
1264	1208	switch (offset)
1265	1209	{
1266	1210	default:
1267		return state->m_ds3xdsp_regs[offset];
	1211	return m_ds3xdsp_regs[offset];
1268	1212	}
1269	1213
1270	1214	return 0xff;
1271	1215	}
1272	1216
1273	1217
1274		WRITE16_HANDLER( hdds3_xdsp_control_w )
	1218	WRITE16_MEMBER( harddriv_state::hdds3_xdsp_control_w )
1275	1219	{
1276		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1277
1278	1220	switch (offset)
1279	1221	{
1280	1222	default:
1281		state->m_ds3xdsp_regs[offset] = data;
	1223	m_ds3xdsp_regs[offset] = data;
1282	1224	break;
1283	1225	}
1284	1226	}
r26010	r26011
1430	1372	*
1431	1373	*************************************/
1432	1374
1433		READ16_HANDLER( hdds3_special_r )
	1375	READ16_MEMBER( harddriv_state::hdds3_special_r )
1434	1376	{
1435		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1436	1377	int result;
1437	1378
1438	1379	switch (offset & 7)
1439	1380	{
1440	1381	case 0:
1441		state->m_ds3_g68flag = 0;
1442		update_ds3_irq(state);
1443		return state->m_ds3_g68data;
	1382	m_ds3_g68flag = 0;
	1383	update_ds3_irq();
	1384	return m_ds3_g68data;
1444	1385
1445	1386	case 1:
1446	1387	result = 0x0fff;
1447		if (state->m_ds3_gcmd) result ^= 0x8000;
1448		if (state->m_ds3_g68flag) result ^= 0x4000;
1449		if (state->m_ds3_gflag) result ^= 0x2000;
	1388	if (m_ds3_gcmd) result ^= 0x8000;
	1389	if (m_ds3_g68flag) result ^= 0x4000;
	1390	if (m_ds3_gflag) result ^= 0x2000;
1450	1391	return result;
1451	1392
1452	1393	case 6:
1453		logerror("ADSP r @ %04x\n", state->m_ds3_sim_address);
1454		if (state->m_ds3_sim_address < state->m_sim_memory_size)
1455		return state->m_sim_memory[state->m_ds3_sim_address];
	1394	logerror("ADSP r @ %04x\n", m_ds3_sim_address);
	1395	if (m_ds3_sim_address < m_sim_memory_size)
	1396	return m_sim_memory[m_ds3_sim_address];
1456	1397	else
1457	1398	return 0xff;
1458	1399	}
r26010	r26011
1460	1401	}
1461	1402
1462	1403
1463		WRITE16_HANDLER( hdds3_special_w )
	1404	WRITE16_MEMBER( harddriv_state::hdds3_special_w )
1464	1405	{
1465		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1466
1467	1406	/* IMPORTANT! these data values also write through to the underlying RAM */
1468		state->m_adsp_data_memory[offset] = data;
	1407	m_adsp_data_memory[offset] = data;
1469	1408
1470	1409	switch (offset & 7)
1471	1410	{
1472	1411	case 0:
1473	1412	logerror("%04X:ADSP sets gdata to %04X\n", space.device().safe_pcbase(), data);
1474		state->m_ds3_gdata = data;
1475		state->m_ds3_gflag = 1;
1476		update_ds3_irq(state);
	1413	m_ds3_gdata = data;
	1414	m_ds3_gflag = 1;
	1415	update_ds3_irq();
1477	1416
1478	1417	/* once we've written data, trigger the main CPU to wake up again */
1479	1418	space.machine().scheduler().trigger(DS3_TRIGGER);
r26010	r26011
1481	1420
1482	1421	case 1:
1483	1422	logerror("%04X:ADSP sets interrupt = %d\n", space.device().safe_pcbase(), (data >> 1) & 1);
1484		state->m_adsp_irq_state = (data >> 1) & 1;
1485		state->update_interrupts();
	1423	m_adsp_irq_state = (data >> 1) & 1;
	1424	update_interrupts();
1486	1425	break;
1487	1426
1488	1427	case 2:
1489		state->m_ds3_send = (data >> 0) & 1;
	1428	m_ds3_send = (data >> 0) & 1;
1490	1429	break;
1491	1430
1492	1431	case 3:
1493		state->m_ds3_gfirqs = (data >> 1) & 1;
1494		state->m_ds3_g68irqs = !state->m_ds3_gfirqs;
1495		update_ds3_irq(state);
	1432	m_ds3_gfirqs = (data >> 1) & 1;
	1433	m_ds3_g68irqs = !m_ds3_gfirqs;
	1434	update_ds3_irq();
1496	1435	break;
1497	1436
1498	1437	case 4:
1499		state->m_ds3_sim_address = (state->m_ds3_sim_address & 0xffff0000) | (data & 0xffff);
	1438	m_ds3_sim_address = (m_ds3_sim_address & 0xffff0000) | (data & 0xffff);
1500	1439	break;
1501	1440
1502	1441	case 5:
1503		state->m_ds3_sim_address = (state->m_ds3_sim_address & 0xffff) | ((data << 16) & 0x00070000);
	1442	m_ds3_sim_address = (m_ds3_sim_address & 0xffff) | ((data << 16) & 0x00070000);
1504	1443	break;
1505	1444	}
1506	1445	}
1507	1446
1508	1447
1509		READ16_HANDLER( hdds3_control_r )
	1448	READ16_MEMBER( harddriv_state::hdds3_control_r )
1510	1449	{
1511	1450	logerror("adsp2101 control r @ %04X\n", 0x3fe0 + offset);
1512	1451	return 0;
1513	1452	}
1514	1453
1515	1454
1516		WRITE16_HANDLER( hdds3_control_w )
	1455	WRITE16_MEMBER( harddriv_state::hdds3_control_w )
1517	1456	{
1518	1457	if (offset != 0x1e && offset != 0x1f)
1519	1458	logerror("adsp2101 control w @ %04X = %04X\n", 0x3fe0 + offset, data);
r26010	r26011
1527	1466	*
1528	1467	*************************************/
1529	1468
1530		READ16_HANDLER( hd68k_ds3_program_r )
	1469	READ16_MEMBER( harddriv_state::hd68k_ds3_program_r )
1531	1470	{
1532		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1533		UINT32 *base = &state->m_adsp_pgm_memory[offset & 0x1fff];
	1471	UINT32 *base = &m_adsp_pgm_memory[offset & 0x1fff];
1534	1472	UINT32 word = *base;
1535	1473	return (!(offset & 0x2000)) ? (word >> 8) : (word & 0xff);
1536	1474	}
1537	1475
1538	1476
1539		WRITE16_HANDLER( hd68k_ds3_program_w )
	1477	WRITE16_MEMBER( harddriv_state::hd68k_ds3_program_w )
1540	1478	{
1541		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1542		UINT32 *base = &state->m_adsp_pgm_memory[offset & 0x1fff];
	1479	UINT32 *base = &m_adsp_pgm_memory[offset & 0x1fff];
1543	1480	UINT32 oldword = *base;
1544	1481	UINT16 temp;
1545	1482
r26010	r26011
1586	1523	*
1587	1524	*************************************/
1588	1525
1589		WRITE16_HANDLER( hd68k_dsk_control_w )
	1526	WRITE16_MEMBER( harddriv_state::hd68k_dsk_control_w )
1590	1527	{
1591		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1592	1528	int val = (offset >> 3) & 1;
1593	1529	switch (offset & 7)
1594	1530	{
1595	1531	case 0: /* DSPRESTN */
1596		state->m_dsp32->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
	1532	m_dsp32->set_input_line(INPUT_LINE_RESET, val ? CLEAR_LINE : ASSERT_LINE);
1597	1533	break;
1598	1534
1599	1535	case 1: /* DSPZN */
1600		state->m_dsp32->set_input_line(INPUT_LINE_HALT, val ? CLEAR_LINE : ASSERT_LINE);
	1536	m_dsp32->set_input_line(INPUT_LINE_HALT, val ? CLEAR_LINE : ASSERT_LINE);
1601	1537	break;
1602	1538
1603	1539	case 2: /* ZW1 */
r26010	r26011
1627	1563	*
1628	1564	*************************************/
1629	1565
1630		READ16_HANDLER( hd68k_dsk_ram_r )
	1566	READ16_MEMBER( harddriv_state::hd68k_dsk_ram_r )
1631	1567	{
1632		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1633		return state->m_dsk_ram[offset];
	1568	return m_dsk_ram[offset];
1634	1569	}
1635	1570
1636	1571
1637		WRITE16_HANDLER( hd68k_dsk_ram_w )
	1572	WRITE16_MEMBER( harddriv_state::hd68k_dsk_ram_w )
1638	1573	{
1639		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1640		COMBINE_DATA(&state->m_dsk_ram[offset]);
	1574	COMBINE_DATA(&m_dsk_ram[offset]);
1641	1575	}
1642	1576
1643	1577
1644		READ16_HANDLER( hd68k_dsk_zram_r )
	1578	READ16_MEMBER( harddriv_state::hd68k_dsk_zram_r )
1645	1579	{
1646		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1647		return state->m_dsk_zram[offset];
	1580	return m_dsk_zram[offset];
1648	1581	}
1649	1582
1650	1583
1651		WRITE16_HANDLER( hd68k_dsk_zram_w )
	1584	WRITE16_MEMBER( harddriv_state::hd68k_dsk_zram_w )
1652	1585	{
1653		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1654		COMBINE_DATA(&state->m_dsk_zram[offset]);
	1586	COMBINE_DATA(&m_dsk_zram[offset]);
1655	1587	}
1656	1588
1657	1589
1658		READ16_HANDLER( hd68k_dsk_small_rom_r )
	1590	READ16_MEMBER( harddriv_state::hd68k_dsk_small_rom_r )
1659	1591	{
1660		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1661		return state->m_dsk_rom[offset & 0x1ffff];
	1592	return m_dsk_rom[offset & 0x1ffff];
1662	1593	}
1663	1594
1664	1595
1665		READ16_HANDLER( hd68k_dsk_rom_r )
	1596	READ16_MEMBER( harddriv_state::hd68k_dsk_rom_r )
1666	1597	{
1667		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1668		return state->m_dsk_rom[offset];
	1598	return m_dsk_rom[offset];
1669	1599	}
1670	1600
1671	1601
r26010	r26011
1676	1606	*
1677	1607	*************************************/
1678	1608
1679		WRITE16_HANDLER( hd68k_dsk_dsp32_w )
	1609	WRITE16_MEMBER( harddriv_state::hd68k_dsk_dsp32_w )
1680	1610	{
1681		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1682		state->m_dsk_pio_access = TRUE;
1683		state->m_dsp32->pio_w(offset, data);
1684		state->m_dsk_pio_access = FALSE;
	1611	m_dsk_pio_access = TRUE;
	1612	m_dsp32->pio_w(offset, data);
	1613	m_dsk_pio_access = FALSE;
1685	1614	}
1686	1615
1687	1616
1688		READ16_HANDLER( hd68k_dsk_dsp32_r )
	1617	READ16_MEMBER( harddriv_state::hd68k_dsk_dsp32_r )
1689	1618	{
1690		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1691	1619	UINT16 result;
1692		state->m_dsk_pio_access = TRUE;
1693		result = state->m_dsp32->pio_r(offset);
1694		state->m_dsk_pio_access = FALSE;
	1620	m_dsk_pio_access = TRUE;
	1621	result = m_dsp32->pio_r(offset);
	1622	m_dsk_pio_access = FALSE;
1695	1623	return result;
1696	1624	}
1697	1625
r26010	r26011
1708	1636	}
1709	1637
1710	1638
1711		WRITE32_HANDLER( rddsp32_sync0_w )
	1639	WRITE32_MEMBER( harddriv_state::rddsp32_sync0_w )
1712	1640	{
1713		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1714		if (state->m_dsk_pio_access)
	1641	if (m_dsk_pio_access)
1715	1642	{
1716		UINT32 *dptr = &state->m_rddsp32_sync[0][offset];
	1643	UINT32 *dptr = &m_rddsp32_sync[0][offset];
1717	1644	UINT32 newdata = *dptr;
1718	1645	COMBINE_DATA(&newdata);
1719		state->m_dataptr[state->m_next_msp_sync % MAX_MSP_SYNC] = dptr;
1720		state->m_dataval[state->m_next_msp_sync % MAX_MSP_SYNC] = newdata;
1721		space.machine().scheduler().synchronize(timer_expired_delegate(FUNC(harddriv_state::rddsp32_sync_cb),state), state->m_next_msp_sync++ % MAX_MSP_SYNC);
	1646	m_dataptr[m_next_msp_sync % MAX_MSP_SYNC] = dptr;
	1647	m_dataval[m_next_msp_sync % MAX_MSP_SYNC] = newdata;
	1648	space.machine().scheduler().synchronize(timer_expired_delegate(FUNC(harddriv_state::rddsp32_sync_cb),this), m_next_msp_sync++ % MAX_MSP_SYNC);
1722	1649	}
1723	1650	else
1724		COMBINE_DATA(&state->m_rddsp32_sync[0][offset]);
	1651	COMBINE_DATA(&m_rddsp32_sync[0][offset]);
1725	1652	}
1726	1653
1727	1654
1728		WRITE32_HANDLER( rddsp32_sync1_w )
	1655	WRITE32_MEMBER( harddriv_state::rddsp32_sync1_w )
1729	1656	{
1730		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1731		if (state->m_dsk_pio_access)
	1657	if (m_dsk_pio_access)
1732	1658	{
1733		UINT32 *dptr = &state->m_rddsp32_sync[1][offset];
	1659	UINT32 *dptr = &m_rddsp32_sync[1][offset];
1734	1660	UINT32 newdata = *dptr;
1735	1661	COMBINE_DATA(&newdata);
1736		state->m_dataptr[state->m_next_msp_sync % MAX_MSP_SYNC] = dptr;
1737		state->m_dataval[state->m_next_msp_sync % MAX_MSP_SYNC] = newdata;
1738		space.machine().scheduler().synchronize(timer_expired_delegate(FUNC(harddriv_state::rddsp32_sync_cb),state), state->m_next_msp_sync++ % MAX_MSP_SYNC);
	1662	m_dataptr[m_next_msp_sync % MAX_MSP_SYNC] = dptr;
	1663	m_dataval[m_next_msp_sync % MAX_MSP_SYNC] = newdata;
	1664	space.machine().scheduler().synchronize(timer_expired_delegate(FUNC(harddriv_state::rddsp32_sync_cb),this), m_next_msp_sync++ % MAX_MSP_SYNC);
1739	1665	}
1740	1666	else
1741		COMBINE_DATA(&state->m_rddsp32_sync[1][offset]);
	1667	COMBINE_DATA(&m_rddsp32_sync[1][offset]);
1742	1668	}
1743	1669
1744	1670
r26010	r26011
1754	1680	*
1755	1681	*************************************/
1756	1682
1757		WRITE16_HANDLER( hddspcom_control_w )
	1683	WRITE16_MEMBER( harddriv_state::hddspcom_control_w )
1758	1684	{
1759	1685	int val = (offset >> 3) & 1;
1760	1686	switch (offset & 7)
r26010	r26011
1782	1708	*
1783	1709	*************************************/
1784	1710
1785		WRITE16_HANDLER( rd68k_slapstic_w )
	1711	WRITE16_MEMBER( harddriv_state::rd68k_slapstic_w )
1786	1712	{
1787	1713	slapstic_tweak(space, offset & 0x3fff);
1788	1714	}
1789	1715
1790	1716
1791		READ16_HANDLER( rd68k_slapstic_r )
	1717	READ16_MEMBER( harddriv_state::rd68k_slapstic_r )
1792	1718	{
1793		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1794	1719	int bank = slapstic_tweak(space, offset & 0x3fff) * 0x4000;
1795		return state->m_m68k_slapstic_base[bank + (offset & 0x3fff)];
	1720	return m_m68k_slapstic_base[bank + (offset & 0x3fff)];
1796	1721	}
1797	1722
1798	1723
r26010	r26011
1803	1728	*
1804	1729	*************************************/
1805	1730
1806		static int st68k_sloop_tweak(harddriv_state *state, offs_t offset)
	1731	int harddriv_state::st68k_sloop_tweak(offs_t offset)
1807	1732	{
1808	1733	static int last_offset;
1809	1734
r26010	r26011
1812	1737	switch (offset)
1813	1738	{
1814	1739	case 0x78e8:
1815		state->m_st68k_sloop_bank = 0;
	1740	m_st68k_sloop_bank = 0;
1816	1741	break;
1817	1742	case 0x6ca4:
1818		state->m_st68k_sloop_bank = 1;
	1743	m_st68k_sloop_bank = 1;
1819	1744	break;
1820	1745	case 0x15ea:
1821		state->m_st68k_sloop_bank = 2;
	1746	m_st68k_sloop_bank = 2;
1822	1747	break;
1823	1748	case 0x6b28:
1824		state->m_st68k_sloop_bank = 3;
	1749	m_st68k_sloop_bank = 3;
1825	1750	break;
1826	1751	}
1827	1752	}
1828	1753	last_offset = offset;
1829		return state->m_st68k_sloop_bank;
	1754	return m_st68k_sloop_bank;
1830	1755	}
1831	1756
1832	1757
1833		WRITE16_HANDLER( st68k_sloop_w )
	1758	WRITE16_MEMBER( harddriv_state::st68k_sloop_w )
1834	1759	{
1835		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1836		st68k_sloop_tweak(state, offset & 0x3fff);
	1760	st68k_sloop_tweak(offset & 0x3fff);
1837	1761	}
1838	1762
1839	1763
1840		READ16_HANDLER( st68k_sloop_r )
	1764	READ16_MEMBER( harddriv_state::st68k_sloop_r )
1841	1765	{
1842		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1843		int bank = st68k_sloop_tweak(state, offset) * 0x4000;
1844		return state->m_m68k_slapstic_base[bank + (offset & 0x3fff)];
	1766	int bank = st68k_sloop_tweak(offset) * 0x4000;
	1767	return m_m68k_slapstic_base[bank + (offset & 0x3fff)];
1845	1768	}
1846	1769
1847	1770
1848		READ16_HANDLER( st68k_sloop_alt_r )
	1771	READ16_MEMBER( harddriv_state::st68k_sloop_alt_r )
1849	1772	{
1850		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1851		if (state->m_st68k_last_alt_sloop_offset == 0x00fe)
	1773	if (m_st68k_last_alt_sloop_offset == 0x00fe)
1852	1774	{
1853	1775	switch (offset*2)
1854	1776	{
1855	1777	case 0x22c:
1856		state->m_st68k_sloop_bank = 0;
	1778	m_st68k_sloop_bank = 0;
1857	1779	break;
1858	1780	case 0x1e2:
1859		state->m_st68k_sloop_bank = 1;
	1781	m_st68k_sloop_bank = 1;
1860	1782	break;
1861	1783	case 0x1fa:
1862		state->m_st68k_sloop_bank = 2;
	1784	m_st68k_sloop_bank = 2;
1863	1785	break;
1864	1786	case 0x206:
1865		state->m_st68k_sloop_bank = 3;
	1787	m_st68k_sloop_bank = 3;
1866	1788	break;
1867	1789	}
1868	1790	}
1869		state->m_st68k_last_alt_sloop_offset = offset*2;
1870		return state->m_m68k_sloop_alt_base[offset];
	1791	m_st68k_last_alt_sloop_offset = offset*2;
	1792	return m_m68k_sloop_alt_base[offset];
1871	1793	}
1872	1794
1873	1795
1874		static int st68k_protosloop_tweak(harddriv_state *state, offs_t offset)
	1796	int harddriv_state::st68k_protosloop_tweak(offs_t offset)
1875	1797	{
1876	1798	static int last_offset;
1877	1799
r26010	r26011
1880	1802	switch (offset)
1881	1803	{
1882	1804	case 0x0001:
1883		state->m_st68k_sloop_bank = 0;
	1805	m_st68k_sloop_bank = 0;
1884	1806	break;
1885	1807	case 0x0002:
1886		state->m_st68k_sloop_bank = 1;
	1808	m_st68k_sloop_bank = 1;
1887	1809	break;
1888	1810	case 0x0003:
1889		state->m_st68k_sloop_bank = 2;
	1811	m_st68k_sloop_bank = 2;
1890	1812	break;
1891	1813	case 0x0004:
1892		state->m_st68k_sloop_bank = 3;
	1814	m_st68k_sloop_bank = 3;
1893	1815	break;
1894	1816	}
1895	1817	}
1896	1818	last_offset = offset;
1897		return state->m_st68k_sloop_bank;
	1819	return m_st68k_sloop_bank;
1898	1820	}
1899	1821
1900	1822
1901		WRITE16_HANDLER( st68k_protosloop_w )
	1823	WRITE16_MEMBER( harddriv_state::st68k_protosloop_w )
1902	1824	{
1903		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1904		st68k_protosloop_tweak(state, offset & 0x3fff);
	1825	st68k_protosloop_tweak(offset & 0x3fff);
1905	1826	}
1906	1827
1907	1828
1908		READ16_HANDLER( st68k_protosloop_r )
	1829	READ16_MEMBER( harddriv_state::st68k_protosloop_r )
1909	1830	{
1910		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1911		int bank = st68k_protosloop_tweak(state, offset) * 0x4000;
1912		return state->m_m68k_slapstic_base[bank + (offset & 0x3fff)];
	1831	int bank = st68k_protosloop_tweak(offset) * 0x4000;
	1832	return m_m68k_slapstic_base[bank + (offset & 0x3fff)];
1913	1833	}
1914	1834
1915	1835
r26010	r26011
1928	1848	*
1929	1849	*************************************/
1930	1850
1931		READ16_HANDLER( hdgsp_speedup_r )
	1851	READ16_MEMBER( harddriv_state::hdgsp_speedup_r )
1932	1852	{
1933		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1934		int result = state->m_gsp_speedup_addr[0][offset];
	1853	int result = m_gsp_speedup_addr[0][offset];
1935	1854
1936	1855	/* if both this address and the other important address are not $ffff */
1937	1856	/* then we can spin until something gets written */
1938		if (result != 0xffff && state->m_gsp_speedup_addr[1][0] != 0xffff &&
1939		&space.device() == state->m_gsp && space.device().safe_pc() == state->m_gsp_speedup_pc)
	1857	if (result != 0xffff && m_gsp_speedup_addr[1][0] != 0xffff &&
	1858	&space.device() == m_gsp && space.device().safe_pc() == m_gsp_speedup_pc)
1940	1859	{
1941		state->m_gsp_speedup_count[0]++;
	1860	m_gsp_speedup_count[0]++;
1942	1861	space.device().execute().spin_until_interrupt();
1943	1862	}
1944	1863
r26010	r26011
1946	1865	}
1947	1866
1948	1867
1949		WRITE16_HANDLER( hdgsp_speedup1_w )
	1868	WRITE16_MEMBER( harddriv_state::hdgsp_speedup1_w )
1950	1869	{
1951		harddriv_state *state = space.machine().driver_data<harddriv_state>();
	1870	COMBINE_DATA(&m_gsp_speedup_addr[0][offset]);
1952	1871
1953		COMBINE_DATA(&state->m_gsp_speedup_addr[0][offset]);
1954
1955	1872	/* if $ffff is written, send an "interrupt" trigger to break us out of the spin loop */
1956		if (state->m_gsp_speedup_addr[0][offset] == 0xffff)
1957		state->m_gsp->signal_interrupt_trigger();
	1873	if (m_gsp_speedup_addr[0][offset] == 0xffff)
	1874	m_gsp->signal_interrupt_trigger();
1958	1875	}
1959	1876
1960	1877
1961		WRITE16_HANDLER( hdgsp_speedup2_w )
	1878	WRITE16_MEMBER( harddriv_state::hdgsp_speedup2_w )
1962	1879	{
1963		harddriv_state *state = space.machine().driver_data<harddriv_state>();
	1880	COMBINE_DATA(&m_gsp_speedup_addr[1][offset]);
1964	1881
1965		COMBINE_DATA(&state->m_gsp_speedup_addr[1][offset]);
1966
1967	1882	/* if $ffff is written, send an "interrupt" trigger to break us out of the spin loop */
1968		if (state->m_gsp_speedup_addr[1][offset] == 0xffff)
1969		state->m_gsp->signal_interrupt_trigger();
	1883	if (m_gsp_speedup_addr[1][offset] == 0xffff)
	1884	m_gsp->signal_interrupt_trigger();
1970	1885	}
1971	1886
1972	1887
r26010	r26011
1979	1894	*
1980	1895	*************************************/
1981	1896
1982		READ16_HANDLER( rdgsp_speedup1_r )
	1897	READ16_MEMBER( harddriv_state::rdgsp_speedup1_r )
1983	1898	{
1984		harddriv_state *state = space.machine().driver_data<harddriv_state>();
1985		UINT16 result = state->m_gsp_speedup_addr[0][offset];
	1899	UINT16 result = m_gsp_speedup_addr[0][offset];
1986	1900
1987	1901	/* if this address is equal to $f000, spin until something gets written */
1988		if (&space.device() == state->m_gsp && space.device().safe_pc() == state->m_gsp_speedup_pc &&
	1902	if (&space.device() == m_gsp && space.device().safe_pc() == m_gsp_speedup_pc &&
1989	1903	(UINT8)result < space.device().state().state_int(TMS34010_A1))
1990	1904	{
1991		state->m_gsp_speedup_count[0]++;
	1905	m_gsp_speedup_count[0]++;
1992	1906	space.device().execute().spin_until_interrupt();
1993	1907	}
1994	1908
r26010	r26011
1996	1910	}
1997	1911
1998	1912
1999		WRITE16_HANDLER( rdgsp_speedup1_w )
	1913	WRITE16_MEMBER( harddriv_state::rdgsp_speedup1_w )
2000	1914	{
2001		harddriv_state *state = space.machine().driver_data<harddriv_state>();
2002		COMBINE_DATA(&state->m_gsp_speedup_addr[0][offset]);
2003		if (&space.device() != state->m_gsp)
2004		state->m_gsp->signal_interrupt_trigger();
	1915	COMBINE_DATA(&m_gsp_speedup_addr[0][offset]);
	1916	if (&space.device() != m_gsp)
	1917	m_gsp->signal_interrupt_trigger();
2005	1918	}
2006	1919
2007	1920
r26010	r26011
2017	1930	*
2018	1931	*************************************/
2019	1932
2020		READ16_HANDLER( hdmsp_speedup_r )
	1933	READ16_MEMBER( harddriv_state::hdmsp_speedup_r )
2021	1934	{
2022		harddriv_state *state = space.machine().driver_data<harddriv_state>();
2023		int data = state->m_msp_speedup_addr[offset];
	1935	int data = m_msp_speedup_addr[offset];
2024	1936
2025		if (data == 0 && &space.device() == state->m_msp && space.device().safe_pc() == state->m_msp_speedup_pc)
	1937	if (data == 0 && &space.device() == m_msp && space.device().safe_pc() == m_msp_speedup_pc)
2026	1938	{
2027		state->m_msp_speedup_count[0]++;
	1939	m_msp_speedup_count[0]++;
2028	1940	space.device().execute().spin_until_interrupt();
2029	1941	}
2030	1942
r26010	r26011
2032	1944	}
2033	1945
2034	1946
2035		WRITE16_HANDLER( hdmsp_speedup_w )
	1947	WRITE16_MEMBER( harddriv_state::hdmsp_speedup_w )
2036	1948	{
2037		harddriv_state *state = space.machine().driver_data<harddriv_state>();
2038		COMBINE_DATA(&state->m_msp_speedup_addr[offset]);
2039		if (offset == 0 && state->m_msp_speedup_addr[offset] != 0)
2040		state->m_msp->signal_interrupt_trigger();
	1949	COMBINE_DATA(&m_msp_speedup_addr[offset]);
	1950	if (offset == 0 && m_msp_speedup_addr[offset] != 0)
	1951	m_msp->signal_interrupt_trigger();
2041	1952	}
2042	1953
2043	1954
r26010	r26011
2052	1963	*
2053	1964	*************************************/
2054	1965
2055		READ16_HANDLER( hdadsp_speedup_r )
	1966	READ16_MEMBER( harddriv_state::hdadsp_speedup_r )
2056	1967	{
2057		harddriv_state *state = space.machine().driver_data<harddriv_state>();
2058		int data = state->m_adsp_data_memory[0x1fff];
	1968	int data = m_adsp_data_memory[0x1fff];
2059	1969
2060		if (data == 0xffff && &space.device() == state->m_adsp && space.device().safe_pc() <= 0x3b)
	1970	if (data == 0xffff && &space.device() == m_adsp && space.device().safe_pc() <= 0x3b)
2061	1971	{
2062		state->m_adsp_speedup_count[0]++;
	1972	m_adsp_speedup_count[0]++;
2063	1973	space.device().execute().spin_until_interrupt();
2064	1974	}
2065	1975
r26010	r26011
2067	1977	}
2068	1978
2069	1979
2070		READ16_HANDLER( hdds3_speedup_r )
	1980	READ16_MEMBER( harddriv_state::hdds3_speedup_r )
2071	1981	{
2072		harddriv_state *state = space.machine().driver_data<harddriv_state>();
2073		int data = *state->m_ds3_speedup_addr;
	1982	int data = *m_ds3_speedup_addr;
2074	1983
2075		if (data != 0 && &space.device() == state->m_adsp && space.device().safe_pc() == state->m_ds3_speedup_pc)
	1984	if (data != 0 && &space.device() == m_adsp && space.device().safe_pc() == m_ds3_speedup_pc)
2076	1985	{
2077		state->m_adsp_speedup_count[2]++;
	1986	m_adsp_speedup_count[2]++;
2078	1987	space.device().execute().spin_until_interrupt();
2079	1988	}
2080	1989

trunk/src/mame/includes/harddriv.h

r26010	r26011
273	273	optional_device<dac_device> m_dac;
274	274	required_device<duartn68681_device> m_duart;
275	275	DECLARE_WRITE_LINE_MEMBER(harddriv_duart_irq_handler);
276		};
	276
	277	/*----------- defined in machine/harddriv.c -----------*/
277	278
	279	/* Driver/Multisync board */
	280	DECLARE_WRITE16_MEMBER( hd68k_irq_ack_w );
278	281
279		/*----------- defined in machine/harddriv.c -----------*/
	282	DECLARE_READ16_MEMBER( hd68k_gsp_io_r );
	283	DECLARE_WRITE16_MEMBER( hd68k_gsp_io_w );
280	284
281		/* Driver/Multisync board */
	285	DECLARE_READ16_MEMBER( hd68k_msp_io_r );
	286	DECLARE_WRITE16_MEMBER( hd68k_msp_io_w );
282	287
283		DECLARE_WRITE16_HANDLER( hd68k_irq_ack_w );
284		void hdgsp_irq_gen(device_t *device, int state);
285		void hdmsp_irq_gen(device_t *device, int state);
	288	DECLARE_READ16_MEMBER( hd68k_port0_r );
	289	DECLARE_READ16_MEMBER( hd68k_adc8_r );
	290	DECLARE_READ16_MEMBER( hd68k_adc12_r );
	291	DECLARE_READ16_MEMBER( hdc68k_port1_r );
	292	DECLARE_READ16_MEMBER( hda68k_port1_r );
	293	DECLARE_READ16_MEMBER( hdc68k_wheel_r );
	294	DECLARE_READ16_MEMBER( hd68k_sound_reset_r );
286	295
287		DECLARE_READ16_HANDLER( hd68k_gsp_io_r );
288		DECLARE_WRITE16_HANDLER( hd68k_gsp_io_w );
	296	DECLARE_WRITE16_MEMBER( hd68k_adc_control_w );
	297	DECLARE_WRITE16_MEMBER( hd68k_wr0_write );
	298	DECLARE_WRITE16_MEMBER( hd68k_wr1_write );
	299	DECLARE_WRITE16_MEMBER( hd68k_wr2_write );
	300	DECLARE_WRITE16_MEMBER( hd68k_nwr_w );
	301	DECLARE_WRITE16_MEMBER( hdc68k_wheel_edge_reset_w );
289	302
290		DECLARE_READ16_HANDLER( hd68k_msp_io_r );
291		DECLARE_WRITE16_HANDLER( hd68k_msp_io_w );
	303	DECLARE_READ16_MEMBER( hd68k_zram_r );
	304	DECLARE_WRITE16_MEMBER( hd68k_zram_w );
292	305
293		DECLARE_READ16_HANDLER( hd68k_port0_r );
294		DECLARE_READ16_HANDLER( hd68k_adc8_r );
295		DECLARE_READ16_HANDLER( hd68k_adc12_r );
296		DECLARE_READ16_HANDLER( hdc68k_port1_r );
297		DECLARE_READ16_HANDLER( hda68k_port1_r );
298		DECLARE_READ16_HANDLER( hdc68k_wheel_r );
299		DECLARE_READ16_HANDLER( hd68k_sound_reset_r );
	306	DECLARE_WRITE16_MEMBER( hdgsp_io_w );
300	307
301		DECLARE_WRITE16_HANDLER( hd68k_adc_control_w );
302		DECLARE_WRITE16_HANDLER( hd68k_wr0_write );
303		DECLARE_WRITE16_HANDLER( hd68k_wr1_write );
304		DECLARE_WRITE16_HANDLER( hd68k_wr2_write );
305		DECLARE_WRITE16_HANDLER( hd68k_nwr_w );
306		DECLARE_WRITE16_HANDLER( hdc68k_wheel_edge_reset_w );
	308	DECLARE_WRITE16_MEMBER( hdgsp_protection_w );
	309
	310	/* ADSP board */
	311	DECLARE_READ16_MEMBER( hd68k_adsp_program_r );
	312	DECLARE_WRITE16_MEMBER( hd68k_adsp_program_w );
307	313
308		DECLARE_READ16_HANDLER( hd68k_zram_r );
309		DECLARE_WRITE16_HANDLER( hd68k_zram_w );
	314	DECLARE_READ16_MEMBER( hd68k_adsp_data_r );
	315	DECLARE_WRITE16_MEMBER( hd68k_adsp_data_w );
310	316
311		DECLARE_WRITE16_HANDLER( hdgsp_io_w );
	317	DECLARE_READ16_MEMBER( hd68k_adsp_buffer_r );
	318	DECLARE_WRITE16_MEMBER( hd68k_adsp_buffer_w );
312	319
313		DECLARE_WRITE16_HANDLER( hdgsp_protection_w );
	320	DECLARE_WRITE16_MEMBER( hd68k_adsp_control_w );
	321	DECLARE_WRITE16_MEMBER( hd68k_adsp_irq_clear_w );
	322	DECLARE_READ16_MEMBER( hd68k_adsp_irq_state_r );
314	323
	324	DECLARE_READ16_MEMBER( hdadsp_special_r );
	325	DECLARE_WRITE16_MEMBER( hdadsp_special_w );
	326
	327	/* DS III/IV board */
	328	void update_ds3_irq();
	329	void update_ds3_sirq();
	330
	331	DECLARE_WRITE16_MEMBER( hd68k_ds3_control_w );
	332	DECLARE_READ16_MEMBER( hd68k_ds3_girq_state_r );
315	333
316		/* ADSP board */
317		DECLARE_READ16_HANDLER( hd68k_adsp_program_r );
318		DECLARE_WRITE16_HANDLER( hd68k_adsp_program_w );
	334	DECLARE_READ16_MEMBER( hd68k_ds3_gdata_r );
	335	DECLARE_WRITE16_MEMBER( hd68k_ds3_gdata_w );
319	336
320		DECLARE_READ16_HANDLER( hd68k_adsp_data_r );
321		DECLARE_WRITE16_HANDLER( hd68k_adsp_data_w );
	337	DECLARE_READ16_MEMBER( hdds3_special_r );
	338	DECLARE_WRITE16_MEMBER( hdds3_special_w );
	339	DECLARE_READ16_MEMBER( hdds3_control_r );
	340	DECLARE_WRITE16_MEMBER( hdds3_control_w );
322	341
323		DECLARE_READ16_HANDLER( hd68k_adsp_buffer_r );
324		DECLARE_WRITE16_HANDLER( hd68k_adsp_buffer_w );
	342	DECLARE_READ16_MEMBER( hd68k_ds3_program_r );
	343	DECLARE_WRITE16_MEMBER( hd68k_ds3_program_w );
325	344
326		DECLARE_WRITE16_HANDLER( hd68k_adsp_control_w );
327		DECLARE_WRITE16_HANDLER( hd68k_adsp_irq_clear_w );
328		DECLARE_READ16_HANDLER( hd68k_adsp_irq_state_r );
	345	DECLARE_READ16_MEMBER( hd68k_ds3_sdata_r );
	346	DECLARE_WRITE16_MEMBER( hd68k_ds3_sdata_w );
	347	DECLARE_WRITE16_MEMBER( hd68k_ds3_sirq_clear_w );
	348	DECLARE_READ16_MEMBER( hd68k_ds3_sirq_state_r );
329	349
330		DECLARE_READ16_HANDLER( hdadsp_special_r );
331		DECLARE_WRITE16_HANDLER( hdadsp_special_w );
	350	DECLARE_READ16_MEMBER( hdds3_sdsp_special_r );
	351	DECLARE_WRITE16_MEMBER( hdds3_sdsp_special_w );
332	352
333		/* DS III/IV board */
334		TIMER_DEVICE_CALLBACK( ds3sdsp_internal_timer_callback );
335		void hdds3sdsp_timer_enable_callback(adsp21xx_device &device, int enable);
	353	DECLARE_READ16_MEMBER( hdds3_sdsp_control_r );
	354	DECLARE_WRITE16_MEMBER( hdds3_sdsp_control_w );
	355	DECLARE_READ16_MEMBER( hdds3_xdsp_control_r );
	356	DECLARE_WRITE16_MEMBER( hdds3_xdsp_control_w );
	357
	358	/* DSK board */
	359	DECLARE_WRITE16_MEMBER( hd68k_dsk_control_w );
	360	DECLARE_READ16_MEMBER( hd68k_dsk_ram_r );
	361	DECLARE_WRITE16_MEMBER( hd68k_dsk_ram_w );
	362	DECLARE_READ16_MEMBER( hd68k_dsk_zram_r );
	363	DECLARE_WRITE16_MEMBER( hd68k_dsk_zram_w );
	364	DECLARE_READ16_MEMBER( hd68k_dsk_small_rom_r );
	365	DECLARE_READ16_MEMBER( hd68k_dsk_rom_r );
	366	DECLARE_WRITE16_MEMBER( hd68k_dsk_dsp32_w );
	367	DECLARE_READ16_MEMBER( hd68k_dsk_dsp32_r );
	368	DECLARE_WRITE32_MEMBER( rddsp32_sync0_w );
	369	DECLARE_WRITE32_MEMBER( rddsp32_sync1_w );
336	370
337		void hdds3sdsp_serial_tx_callback(adsp21xx_device &device, int port, INT32 data);
338		INT32 hdds3sdsp_serial_rx_callback(adsp21xx_device &device, int port);
	371	/* DSPCOM board */
	372	DECLARE_WRITE16_MEMBER( hddspcom_control_w );
339	373
340		TIMER_DEVICE_CALLBACK( ds3xdsp_internal_timer_callback );
341		void hdds3xdsp_timer_enable_callback(adsp21xx_device &device, int enable);
	374	DECLARE_WRITE16_MEMBER( rd68k_slapstic_w );
	375	DECLARE_READ16_MEMBER( rd68k_slapstic_r );
342	376
343		void hdds3xdsp_serial_tx_callback(adsp21xx_device &device, int port, INT32 data);
344		INT32 hdds3xdsp_serial_rx_callback(adsp21xx_device &device, int port);
	377	/* Game-specific protection */
	378	int st68k_sloop_tweak(offs_t offset);
	379	DECLARE_WRITE16_MEMBER( st68k_sloop_w );
	380	DECLARE_READ16_MEMBER( st68k_sloop_r );
	381	DECLARE_READ16_MEMBER( st68k_sloop_alt_r );
	382	int st68k_protosloop_tweak(offs_t offset);
	383	DECLARE_WRITE16_MEMBER( st68k_protosloop_w );
	384	DECLARE_READ16_MEMBER( st68k_protosloop_r );
345	385
346		WRITE16_HANDLER( hd68k_ds3_control_w );
347		READ16_HANDLER( hd68k_ds3_girq_state_r );
	386	/* GSP optimizations */
	387	DECLARE_READ16_MEMBER( hdgsp_speedup_r );
	388	DECLARE_WRITE16_MEMBER( hdgsp_speedup1_w );
	389	DECLARE_WRITE16_MEMBER( hdgsp_speedup2_w );
	390	DECLARE_READ16_MEMBER( rdgsp_speedup1_r );
	391	DECLARE_WRITE16_MEMBER( rdgsp_speedup1_w );
348	392
349		READ16_HANDLER( hd68k_ds3_gdata_r );
350		WRITE16_HANDLER( hd68k_ds3_gdata_w );
	393	/* MSP optimizations */
	394	DECLARE_READ16_MEMBER( hdmsp_speedup_r );
	395	DECLARE_WRITE16_MEMBER( hdmsp_speedup_w );
351	396
352		READ16_HANDLER( hdds3_special_r );
353		WRITE16_HANDLER( hdds3_special_w );
354		READ16_HANDLER( hdds3_control_r );
355		WRITE16_HANDLER( hdds3_control_w );
	397	/* ADSP optimizations */
	398	DECLARE_READ16_MEMBER( hdadsp_speedup_r );
	399	DECLARE_READ16_MEMBER( hdds3_speedup_r );
	400
	401	/*----------- defined in video/harddriv.c -----------*/
	402	DECLARE_READ16_MEMBER( hdgsp_control_lo_r );
	403	DECLARE_WRITE16_MEMBER( hdgsp_control_lo_w );
	404	DECLARE_READ16_MEMBER( hdgsp_control_hi_r );
	405	DECLARE_WRITE16_MEMBER( hdgsp_control_hi_w );
356	406
357		READ16_HANDLER( hd68k_ds3_program_r );
358		WRITE16_HANDLER( hd68k_ds3_program_w );
	407	DECLARE_READ16_MEMBER( hdgsp_vram_2bpp_r );
	408	DECLARE_WRITE16_MEMBER( hdgsp_vram_1bpp_w );
	409	DECLARE_WRITE16_MEMBER( hdgsp_vram_2bpp_w );
359	410
	411	DECLARE_READ16_MEMBER( hdgsp_paletteram_lo_r );
	412	DECLARE_WRITE16_MEMBER( hdgsp_paletteram_lo_w );
	413	DECLARE_READ16_MEMBER( hdgsp_paletteram_hi_r );
	414	DECLARE_WRITE16_MEMBER( hdgsp_paletteram_hi_w );
	415	};
360	416
361		READ16_HANDLER( hd68k_ds3_sdata_r );
362		WRITE16_HANDLER( hd68k_ds3_sdata_w );
363		WRITE16_HANDLER( hd68k_ds3_sirq_clear_w );
364		READ16_HANDLER( hd68k_ds3_sirq_state_r );
365	417
366		READ16_HANDLER( hdds3_sdsp_special_r );
367		WRITE16_HANDLER( hdds3_sdsp_special_w );
	418	/*----------- defined in machine/harddriv.c -----------*/
368	419
369		READ16_HANDLER( hdds3_sdsp_control_r );
370		WRITE16_HANDLER( hdds3_sdsp_control_w );
371		READ16_HANDLER( hdds3_xdsp_control_r );
372		WRITE16_HANDLER( hdds3_xdsp_control_w );
	420	/* Driver/Multisync board */
	421	void hdgsp_irq_gen(device_t *device, int state);
	422	void hdmsp_irq_gen(device_t *device, int state);
373	423
	424	/* DS III/IV board */
	425	TIMER_DEVICE_CALLBACK( ds3sdsp_internal_timer_callback );
	426	void hdds3sdsp_timer_enable_callback(adsp21xx_device &device, int enable);
374	427
375		/* DSK board */
376		void hddsk_update_pif(dsp32c_device &device, UINT32 pins);
377		DECLARE_WRITE16_HANDLER( hd68k_dsk_control_w );
378		DECLARE_READ16_HANDLER( hd68k_dsk_ram_r );
379		DECLARE_WRITE16_HANDLER( hd68k_dsk_ram_w );
380		DECLARE_READ16_HANDLER( hd68k_dsk_zram_r );
381		DECLARE_WRITE16_HANDLER( hd68k_dsk_zram_w );
382		DECLARE_READ16_HANDLER( hd68k_dsk_small_rom_r );
383		DECLARE_READ16_HANDLER( hd68k_dsk_rom_r );
384		DECLARE_WRITE16_HANDLER( hd68k_dsk_dsp32_w );
385		DECLARE_READ16_HANDLER( hd68k_dsk_dsp32_r );
386		DECLARE_WRITE32_HANDLER( rddsp32_sync0_w );
387		DECLARE_WRITE32_HANDLER( rddsp32_sync1_w );
	428	void hdds3sdsp_serial_tx_callback(adsp21xx_device &device, int port, INT32 data);
	429	INT32 hdds3sdsp_serial_rx_callback(adsp21xx_device &device, int port);
388	430
389		/* DSPCOM board */
390		DECLARE_WRITE16_HANDLER( hddspcom_control_w );
	431	TIMER_DEVICE_CALLBACK( ds3xdsp_internal_timer_callback );
	432	void hdds3xdsp_timer_enable_callback(adsp21xx_device &device, int enable);
391	433
392		DECLARE_WRITE16_HANDLER( rd68k_slapstic_w );
393		DECLARE_READ16_HANDLER( rd68k_slapstic_r );
	434	void hdds3xdsp_serial_tx_callback(adsp21xx_device &device, int port, INT32 data);
	435	INT32 hdds3xdsp_serial_rx_callback(adsp21xx_device &device, int port);
394	436
395		/* Game-specific protection */
396		DECLARE_WRITE16_HANDLER( st68k_sloop_w );
397		DECLARE_READ16_HANDLER( st68k_sloop_r );
398		DECLARE_READ16_HANDLER( st68k_sloop_alt_r );
399		DECLARE_WRITE16_HANDLER( st68k_protosloop_w );
400		DECLARE_READ16_HANDLER( st68k_protosloop_r );
	437	/* DSK board */
	438	void hddsk_update_pif(dsp32c_device &device, UINT32 pins);
401	439
402		/* GSP optimizations */
403		DECLARE_READ16_HANDLER( hdgsp_speedup_r );
404		DECLARE_WRITE16_HANDLER( hdgsp_speedup1_w );
405		DECLARE_WRITE16_HANDLER( hdgsp_speedup2_w );
406		DECLARE_READ16_HANDLER( rdgsp_speedup1_r );
407		DECLARE_WRITE16_HANDLER( rdgsp_speedup1_w );
408
409		/* MSP optimizations */
410		DECLARE_READ16_HANDLER( hdmsp_speedup_r );
411		DECLARE_WRITE16_HANDLER( hdmsp_speedup_w );
412
413		/* ADSP optimizations */
414		DECLARE_READ16_HANDLER( hdadsp_speedup_r );
415		DECLARE_READ16_HANDLER( hdds3_speedup_r );
416
417
418	440	/*----------- defined in audio/harddriv.c -----------*/
419	441
420	442	void hdsnd_init(running_machine &machine);
421	443
422	444	/*----------- defined in video/harddriv.c -----------*/
423	445
424
425	446	void hdgsp_write_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
426	447	void hdgsp_read_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
427	448
428		DECLARE_READ16_HANDLER( hdgsp_control_lo_r );
429		DECLARE_WRITE16_HANDLER( hdgsp_control_lo_w );
430		DECLARE_READ16_HANDLER( hdgsp_control_hi_r );
431		DECLARE_WRITE16_HANDLER( hdgsp_control_hi_w );
432
433		DECLARE_READ16_HANDLER( hdgsp_vram_2bpp_r );
434		DECLARE_WRITE16_HANDLER( hdgsp_vram_1bpp_w );
435		DECLARE_WRITE16_HANDLER( hdgsp_vram_2bpp_w );
436
437		DECLARE_READ16_HANDLER( hdgsp_paletteram_lo_r );
438		DECLARE_WRITE16_HANDLER( hdgsp_paletteram_lo_w );
439		DECLARE_READ16_HANDLER( hdgsp_paletteram_hi_r );
440		DECLARE_WRITE16_HANDLER( hdgsp_paletteram_hi_w );
441
442	449	void harddriv_scanline_driver(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
443	450	void harddriv_scanline_multisync(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);

trunk/src/mame/video/harddriv.c

r26010	r26011
178	178	*
179	179	*************************************/
180	180
181		READ16_HANDLER( hdgsp_control_lo_r )
	181	READ16_MEMBER( harddriv_state::hdgsp_control_lo_r )
182	182	{
183		harddriv_state *state = space.machine().driver_data<harddriv_state>();
184		return state->m_gsp_control_lo[offset];
	183	return m_gsp_control_lo[offset];
185	184	}
186	185
187	186
188		WRITE16_HANDLER( hdgsp_control_lo_w )
	187	WRITE16_MEMBER( harddriv_state::hdgsp_control_lo_w )
189	188	{
190		harddriv_state *state = space.machine().driver_data<harddriv_state>();
191		int oldword = state->m_gsp_control_lo[offset];
	189	int oldword = m_gsp_control_lo[offset];
192	190	int newword;
193	191
194		COMBINE_DATA(&state->m_gsp_control_lo[offset]);
195		newword = state->m_gsp_control_lo[offset];
	192	COMBINE_DATA(&m_gsp_control_lo[offset]);
	193	newword = m_gsp_control_lo[offset];
196	194
197	195	if (oldword != newword && offset != 0)
198	196	logerror("GSP:gsp_control_lo(%X)=%04X\n", offset, newword);
r26010	r26011
206	204	*
207	205	*************************************/
208	206
209		READ16_HANDLER( hdgsp_control_hi_r )
	207	READ16_MEMBER( harddriv_state::hdgsp_control_hi_r )
210	208	{
211		harddriv_state *state = space.machine().driver_data<harddriv_state>();
212		return state->m_gsp_control_hi[offset];
	209	return m_gsp_control_hi[offset];
213	210	}
214	211
215	212
216		WRITE16_HANDLER( hdgsp_control_hi_w )
	213	WRITE16_MEMBER( harddriv_state::hdgsp_control_hi_w )
217	214	{
218		harddriv_state *state = space.machine().driver_data<harddriv_state>();
219	215	int val = (offset >> 3) & 1;
220	216
221		int oldword = state->m_gsp_control_hi[offset];
	217	int oldword = m_gsp_control_hi[offset];
222	218	int newword;
223	219
224		COMBINE_DATA(&state->m_gsp_control_hi[offset]);
225		newword = state->m_gsp_control_hi[offset];
	220	COMBINE_DATA(&m_gsp_control_hi[offset]);
	221	newword = m_gsp_control_hi[offset];
226	222
227	223	switch (offset & 7)
228	224	{
229	225	case 0x00:
230		state->m_shiftreg_enable = val;
	226	m_shiftreg_enable = val;
231	227	break;
232	228
233	229	case 0x01:
234		data = data & (15 >> state->m_gsp_multisync);
235		state->m_screen->update_partial(state->m_screen->vpos() - 1);
236		state->m_gfx_finescroll = data;
	230	data = data & (15 >> m_gsp_multisync);
	231	m_screen->update_partial(m_screen->vpos() - 1);
	232	m_gfx_finescroll = data;
237	233	break;
238	234
239	235	case 0x02:
240		update_palette_bank(space.machine(), (state->m_gfx_palettebank & ~1) | val);
	236	update_palette_bank(space.machine(), (m_gfx_palettebank & ~1) | val);
241	237	break;
242	238
243	239	case 0x03:
244		update_palette_bank(space.machine(), (state->m_gfx_palettebank & ~2) | (val << 1));
	240	update_palette_bank(space.machine(), (m_gfx_palettebank & ~2) | (val << 1));
245	241	break;
246	242
247	243	case 0x04:
248	244	if (space.machine().total_colors() >= 256 * 8)
249		update_palette_bank(space.machine(), (state->m_gfx_palettebank & ~4) | (val << 2));
	245	update_palette_bank(space.machine(), (m_gfx_palettebank & ~4) | (val << 2));
250	246	break;
251	247
252	248	case 0x07:
r26010	r26011
268	264	*
269	265	*************************************/
270	266
271		READ16_HANDLER( hdgsp_vram_2bpp_r )
	267	READ16_MEMBER( harddriv_state::hdgsp_vram_2bpp_r )
272	268	{
273	269	return 0;
274	270	}
275	271
276	272
277		WRITE16_HANDLER( hdgsp_vram_1bpp_w )
	273	WRITE16_MEMBER( harddriv_state::hdgsp_vram_1bpp_w )
278	274	{
279		harddriv_state *state = space.machine().driver_data<harddriv_state>();
280		UINT32 *dest = (UINT32 *)&state->m_gsp_vram[offset * 16];
281		UINT32 *mask = &state->m_mask_table[data * 4];
282		UINT32 color = state->m_gsp_control_lo[0] & 0xff;
	275	UINT32 *dest = (UINT32 *)&m_gsp_vram[offset * 16];
	276	UINT32 *mask = &m_mask_table[data * 4];
	277	UINT32 color = m_gsp_control_lo[0] & 0xff;
283	278	UINT32 curmask;
284	279
285	280	color |= color << 8;
r26010	r26011
303	298	}
304	299
305	300
306		WRITE16_HANDLER( hdgsp_vram_2bpp_w )
	301	WRITE16_MEMBER( harddriv_state::hdgsp_vram_2bpp_w )
307	302	{
308		harddriv_state *state = space.machine().driver_data<harddriv_state>();
309		UINT32 *dest = (UINT32 *)&state->m_gsp_vram[offset * 8];
310		UINT32 *mask = &state->m_mask_table[data * 2];
311		UINT32 color = state->m_gsp_control_lo[0];
	303	UINT32 *dest = (UINT32 *)&m_gsp_vram[offset * 8];
	304	UINT32 *mask = &m_mask_table[data * 2];
	305	UINT32 color = m_gsp_control_lo[0];
312	306	UINT32 curmask;
313	307
314	308	color |= color << 16;
r26010	r26011
340	334	}
341	335
342	336
343		READ16_HANDLER( hdgsp_paletteram_lo_r )
	337	READ16_MEMBER( harddriv_state::hdgsp_paletteram_lo_r )
344	338	{
345		harddriv_state *state = space.machine().driver_data<harddriv_state>();
346
347	339	/* note that the palette is only accessed via the first 256 entries */
348	340	/* others are selected via the palette bank */
349		offset = state->m_gfx_palettebank * 0x100 + (offset & 0xff);
	341	offset = m_gfx_palettebank * 0x100 + (offset & 0xff);
350	342
351		return state->m_gsp_paletteram_lo[offset];
	343	return m_gsp_paletteram_lo[offset];
352	344	}
353	345
354	346
355		WRITE16_HANDLER( hdgsp_paletteram_lo_w )
	347	WRITE16_MEMBER( harddriv_state::hdgsp_paletteram_lo_w )
356	348	{
357		harddriv_state *state = space.machine().driver_data<harddriv_state>();
358
359	349	/* note that the palette is only accessed via the first 256 entries */
360	350	/* others are selected via the palette bank */
361		offset = state->m_gfx_palettebank * 0x100 + (offset & 0xff);
	351	offset = m_gfx_palettebank * 0x100 + (offset & 0xff);
362	352
363		COMBINE_DATA(&state->m_gsp_paletteram_lo[offset]);
	353	COMBINE_DATA(&m_gsp_paletteram_lo[offset]);
364	354	gsp_palette_change(space.machine(), offset);
365	355	}
366	356
r26010	r26011
372	362	*
373	363	*************************************/
374	364
375		READ16_HANDLER( hdgsp_paletteram_hi_r )
	365	READ16_MEMBER( harddriv_state::hdgsp_paletteram_hi_r )
376	366	{
377		harddriv_state *state = space.machine().driver_data<harddriv_state>();
378
379	367	/* note that the palette is only accessed via the first 256 entries */
380	368	/* others are selected via the palette bank */
381		offset = state->m_gfx_palettebank * 0x100 + (offset & 0xff);
	369	offset = m_gfx_palettebank * 0x100 + (offset & 0xff);
382	370
383		return state->m_gsp_paletteram_hi[offset];
	371	return m_gsp_paletteram_hi[offset];
384	372	}
385	373
386	374
387		WRITE16_HANDLER( hdgsp_paletteram_hi_w )
	375	WRITE16_MEMBER( harddriv_state::hdgsp_paletteram_hi_w )
388	376	{
389		harddriv_state *state = space.machine().driver_data<harddriv_state>();
390
391	377	/* note that the palette is only accessed via the first 256 entries */
392	378	/* others are selected via the palette bank */
393		offset = state->m_gfx_palettebank * 0x100 + (offset & 0xff);
	379	offset = m_gfx_palettebank * 0x100 + (offset & 0xff);
394	380
395		COMBINE_DATA(&state->m_gsp_paletteram_hi[offset]);
	381	COMBINE_DATA(&m_gsp_paletteram_hi[offset]);
396	382	gsp_palette_change(space.machine(), offset);
397	383	}
398	384

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