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r25511 Thursday 3rd October, 2013 at 20:35:49 UTC by Angelo Salese
SCSP: improved DMA and fixed triggering from SH-2 side [Angelo Salese]
[src/emu/sound]aica.c scsp.c

trunk/src/emu/sound/aica.c
r25510r25511
212212   device_t *device;
213213};
214214
215static void aica_exec_dma(aica_state *aica,address_space &space);       /*state DMA transfer function*/
215static void aica_exec_dma(address_space &space,aica_state *aica);       /*state DMA transfer function*/
216216
217217static const float SDLT[16]={-1000000.0,-42.0,-39.0,-36.0,-33.0,-30.0,-27.0,-24.0,-21.0,-18.0,-15.0,-12.0,-9.0,-6.0,-3.0,0.0};
218218
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767767         AICA->dma.dlg = (AICA->udata.data[0x8c/2] & 0x7ffc);
768768         AICA->dma.ddir = (AICA->udata.data[0x8c/2] & 0x8000) >> 15;
769769         if(AICA->udata.data[0x8c/2] & 1) // dexe
770            aica_exec_dma(AICA,space);
770            aica_exec_dma(space,AICA);
771771         break;
772772
773773      case 0x90:
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14101410}
14111411
14121412/* TODO: this needs to be timer-ized */
1413static void aica_exec_dma(aica_state *aica,address_space &space)
1413static void aica_exec_dma(address_space &space, aica_state *aica)
14141414{
14151415   static UINT16 tmp_dma[4];
14161416   int i;
trunk/src/emu/sound/scsp.c
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216216   emu_timer *timerA, *timerB, *timerC;
217217
218218   // DMA stuff
219   UINT32 scsp_dmea;
220   UINT16 scsp_drga;
221   UINT16 scsp_dtlg;
222   UINT16 scsp_dmactrl;
219   struct{
220      UINT32 dmea;
221      UINT16 drga;
222      UINT16 dtlg;
223      UINT8 dgate;
224      UINT8 ddir;
225   }dma;
223226
224   UINT16 dma_regs[3];
225
226227   UINT16 mcieb;
227228   UINT16 mcipd;
228229
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234235   device_t *device;
235236};
236237
237static void dma_scsp(address_space &space, scsp_state *scsp);       /*state DMA transfer function*/
238#define scsp_dgate      scsp->scsp_dmactrl & 0x4000
239#define scsp_ddir       scsp->scsp_dmactrl & 0x2000
240#define scsp_dexe       scsp->scsp_dmactrl & 0x1000
238static void scsp_exec_dma(address_space &space, scsp_state *scsp);       /*state DMA transfer function*/
241239/* TODO */
242240//#define dma_transfer_end  ((scsp_regs[0x24/2] & 0x10)>>4)|(((scsp_regs[0x26/2] & 0x10)>>4)<<1)|(((scsp_regs[0x28/2] & 0x10)>>4)<<2)
243241
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747745         break;
748746      case 0x12:
749747      case 0x13:
748         scsp->dma.dmea = (scsp->udata.data[0x12/2] & 0xfffe) | (scsp->dma.dmea & 0xf0000);
749         break;
750750      case 0x14:
751751      case 0x15:
752         scsp->dma.dmea = ((scsp->udata.data[0x14/2] & 0xf000) << 4) | (scsp->dma.dmea & 0xfffe);
753         scsp->dma.drga = (scsp->udata.data[0x14/2] & 0x0ffe);
754         break;
752755      case 0x16:
753756      case 0x17:
757         scsp->dma.dtlg = (scsp->udata.data[0x16/2] & 0x0ffe);
758         scsp->dma.ddir = (scsp->udata.data[0x16/2] & 0x2000) >> 13;
759         scsp->dma.dgate = (scsp->udata.data[0x16/2] & 0x4000) >> 14;
760         if(scsp->udata.data[0x16/2] & 0x1000) // dexe
761            scsp_exec_dma(space,scsp);
754762         break;
755763      case 0x18:
756764      case 0x19:
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9991007      SCSP_UpdateSlotRegR(scsp, slot,addr&0x1f);
10001008      v=*((unsigned short *) (scsp->Slots[slot].udata.datab+(addr)));
10011009   }
1002   else if(addr>=0x412 && addr <= 0x416)
1003      v = scsp->dma_regs[((addr-0x412)/2) & 3];
10041010   else if(addr<0x600)
10051011   {
10061012      if (addr < 0x430)
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13191325}
13201326
13211327/* TODO: this needs to be timer-ized */
1322static void dma_scsp(address_space &space, scsp_state *scsp)
1328static void scsp_exec_dma(address_space &space, scsp_state *scsp)
13231329{
13241330   static UINT16 tmp_dma[3];
13251331   int i;
13261332
1327   scsp->scsp_dmactrl = scsp->dma_regs[2] & 0x7000;
1328
1329   if(!(scsp_dexe)) //don't bother if DMA is off
1330      return;
1331
1332   /* calc the registers */
1333   scsp->scsp_dmea = ((scsp->dma_regs[1] & 0xf000) << 4) | (scsp->dma_regs[0] & 0xfffe); /* RAM address */
1334   scsp->scsp_drga = (scsp->dma_regs[1] & 0x0ffe);
1335   scsp->scsp_dtlg = (scsp->dma_regs[2] & 0x0ffe);
1336
13371333   logerror("SCSP: DMA transfer START\n"
13381334            "DMEA: %04x DRGA: %04x DTLG: %04x\n"
1339            "DGATE: %d  DDIR: %d\n",scsp->scsp_dmea,scsp->scsp_drga,scsp->scsp_dtlg,scsp_dgate ? 1 : 0,scsp_ddir ? 1 : 0);
1335            "DGATE: %d  DDIR: %d\n",scsp->dma.dmea,scsp->dma.drga,scsp->dma.dtlg,scsp->dma.dgate ? 1 : 0,scsp->dma.ddir ? 1 : 0);
13401336
13411337   /* Copy the dma values in a temp storage for resuming later */
13421338      /* (DMA *can't* overwrite its parameters).                  */
1343   if(!(scsp_ddir))
1339   if(!(scsp->dma.ddir))
13441340   {
13451341      for(i=0;i<3;i++)
1346         tmp_dma[i] = scsp->dma_regs[i];
1342         tmp_dma[i] = scsp->udata.data[(0x12+(i*2))/2];
13471343   }
13481344
13491345   /* note: we don't use space.read_word / write_word because it can happen that SH-2 enables the DMA instead of m68k. */
13501346   /* TODO: don't know if params auto-updates, I guess not ... */
1351   if(scsp_ddir)
1347   if(scsp->dma.ddir)
13521348   {
1353      if(scsp_dgate)
1349      if(scsp->dma.dgate)
13541350      {
13551351         popmessage("Check: SCSP DMA DGATE enabled, contact MAME/MESSdev");
1356         for(i=0;i < scsp->scsp_dtlg;i+=2)
1352         for(i=0;i < scsp->dma.dtlg;i+=2)
13571353         {
1358            scsp->SCSPRAM[scsp->scsp_dmea] = 0;
1359            scsp->SCSPRAM[scsp->scsp_dmea+1] = 0;
1360            scsp->scsp_dmea+=2;
1354            scsp->SCSPRAM[scsp->dma.dmea] = 0;
1355            scsp->SCSPRAM[scsp->dma.dmea+1] = 0;
1356            scsp->dma.dmea+=2;
13611357         }
13621358      }
13631359      else
13641360      {
1365         for(i=0;i < scsp->scsp_dtlg;i+=2)
1361         for(i=0;i < scsp->dma.dtlg;i+=2)
13661362         {
13671363            UINT16 tmp;
1368            tmp = SCSP_r16(scsp, space, scsp->scsp_drga);
1369            scsp->SCSPRAM[scsp->scsp_dmea] = tmp & 0xff;
1370            scsp->SCSPRAM[scsp->scsp_dmea+1] = tmp>>8;
1371            scsp->scsp_dmea+=2;
1372            scsp->scsp_drga+=2;
1364            tmp = SCSP_r16(scsp, space, scsp->dma.drga);
1365            scsp->SCSPRAM[scsp->dma.dmea] = tmp & 0xff;
1366            scsp->SCSPRAM[scsp->dma.dmea+1] = tmp>>8;
1367            scsp->dma.dmea+=2;
1368            scsp->dma.drga+=2;
13731369         }
13741370      }
13751371   }
13761372   else
13771373   {
1378      if(scsp_dgate)
1374      if(scsp->dma.dgate)
13791375      {
13801376         popmessage("Check: SCSP DMA DGATE enabled, contact MAME/MESSdev");
1381         for(i=0;i < scsp->scsp_dtlg;i+=2)
1377         for(i=0;i < scsp->dma.dtlg;i+=2)
13821378         {
1383            SCSP_w16(scsp, space, scsp->scsp_drga, 0);
1384            scsp->scsp_drga+=2;
1379            SCSP_w16(scsp, space, scsp->dma.drga, 0);
1380            scsp->dma.drga+=2;
13851381         }
13861382      }
13871383      else
13881384      {
1389         for(i=0;i < scsp->scsp_dtlg;i+=2)
1385         for(i=0;i < scsp->dma.dtlg;i+=2)
13901386         {
13911387            UINT16 tmp;
1392            tmp = scsp->SCSPRAM[scsp->scsp_dmea];
1393            tmp|= scsp->SCSPRAM[scsp->scsp_dmea+1]<<8;
1394            SCSP_w16(scsp, space, scsp->scsp_drga, tmp);
1395            scsp->scsp_dmea+=2;
1396            scsp->scsp_drga+=2;
1388            tmp = scsp->SCSPRAM[scsp->dma.dmea];
1389            tmp|= scsp->SCSPRAM[scsp->dma.dmea+1]<<8;
1390            SCSP_w16(scsp, space, scsp->dma.drga, tmp);
1391            scsp->dma.dmea+=2;
1392            scsp->dma.drga+=2;
13971393         }
13981394      }
13991395   }
14001396
14011397   /*Resume the values*/
1402   if(!(scsp_ddir))
1398   if(!(scsp->dma.ddir))
14031399   {
14041400      for(i=0;i<3;i++)
1405         scsp->dma_regs[i] = tmp_dma[i];
1401         scsp->udata.data[(0x12+(i*2))/2] = tmp_dma[i];
14061402   }
14071403
14081404   /* Job done */
1409   scsp->dma_regs[2] &= ~0x1000;
1405   scsp->udata.data[0x16/2] &= ~0x1000;
14101406   /* request a dma end irq (TODO: make it inside the interface) */
14111407   if(scsp->udata.data[0x1e/2] & 0x10)
14121408   {
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14861482   tmp = SCSP_r16(scsp, space, offset*2);
14871483   COMBINE_DATA(&tmp);
14881484   SCSP_w16(scsp,space,offset*2, tmp);
1489
1490   /* TODO: move in UpdateSlot structure */
1491   switch(offset*2)
1492   {
1493      // check DMA
1494      case 0x412:
1495      case 0x414:
1496      case 0x416:
1497         COMBINE_DATA(&scsp->dma_regs[((offset-0x412)/2) & 3]);
1498         if(ACCESSING_BITS_8_15 && offset*2 == 0x416)
1499            dma_scsp(space, scsp);
1500         break;
1501   }
15021485}
15031486
15041487WRITE16_DEVICE_HANDLER( scsp_midi_in )

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