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r24853 Monday 12th August, 2013 at 03:54:45 UTC by R. Belmont
MC6801/6803 updates: [R. Belmont]
 * Support for timer output capture to pin P21
 * Support for externally-clocked serial
 * Added devcb2 hook for serial xmit to easily differentiate xmit from other Port 2 updates.  Bits are still also sent to Port 2 of course.
[src/emu/cpu/m6800]m6800.c m6800.h

trunk/src/emu/cpu/m6800/m6800.h
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4646
4747#define MCFG_M6801_SC2(_devcb) \
4848   m6800_cpu_device::set_out_sc2_func(*device, DEVCB2_##_devcb);
49#define MCFG_M6801_SER_TX(_devcb) \
50   m6800_cpu_device::set_out_sertx_func(*device, DEVCB2_##_devcb);
4951
50
5152class m6800_cpu_device :  public cpu_device
5253{
5354public:
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5960
6061   // static configuration helpers
6162   template<class _Object> static devcb2_base &set_out_sc2_func(device_t &device, _Object object) { return downcast<m6800_cpu_device &>(device).m_out_sc2_func.set_callback(object); }
63   template<class _Object> static devcb2_base &set_out_sertx_func(device_t &device, _Object object) { return downcast<m6800_cpu_device &>(device).m_out_sertx_func.set_callback(object); }
6264
6365   DECLARE_READ8_MEMBER( m6801_io_r );
6466   DECLARE_WRITE8_MEMBER( m6801_io_w );
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9294   bool m_has_io;
9395
9496   devcb2_write_line m_out_sc2_func;
97   devcb2_write_line m_out_sertx_func;
9598
9699   PAIR    m_ppc;            /* Previous program counter */
97100   PAIR    m_pc;             /* Program counter */
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135138
136139   int     m_clock_divider;
137140   UINT8   m_trcsr, m_rmcr, m_rdr, m_tdr, m_rsr, m_tsr;
138   int     m_rxbits, m_txbits, m_txstate, m_trcsr_read_tdre, m_trcsr_read_orfe, m_trcsr_read_rdrf, m_tx;
141   int     m_rxbits, m_txbits, m_txstate, m_trcsr_read_tdre, m_trcsr_read_orfe, m_trcsr_read_rdrf, m_tx, m_ext_serclock;
142   bool   m_use_ext_serclock;
139143   int     m_port2_written;
140144
141145   int     m_icount;
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425429   m6801_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
426430   m6801_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, const m6800_cpu_device::op_func *insn, const UINT8 *cycles, address_map_constructor internal = NULL);
427431
432   void m6801_clock_serial();
433
428434protected:
429435   virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 4 - 1) / 4; }
430436   virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 4); }
trunk/src/emu/cpu/m6800/m6800.c
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536536   , m_io_config("io", ENDIANNESS_BIG, 8, 9, 0)
537537   , m_has_io(false)
538538   , m_out_sc2_func(*this)
539   , m_out_sertx_func(*this)
539540   , m_insn(m6800_insn)
540541   , m_cycles(cycles_6800)
541542{
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548549   , m_io_config("io", ENDIANNESS_BIG, 8, 9, 0)
549550   , m_has_io(has_io)
550551   , m_out_sc2_func(*this)
552   , m_out_sertx_func(*this)
551553   , m_insn(insn)
552554   , m_cycles(cycles)
553555{
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730732         m_wai_state &= ~M6800_SLP;
731733      if ( !(CC & 0x10) && (m_tcsr & TCSR_EOCI))
732734         TAKE_OCI;
735
736      // if output on P21 is enabled, let's do it
737      if (m_port2_ddr & 2)
738      {
739         m_port2_data &= ~2;
740         m_port2_data |= (m_tcsr & TCSR_OLVL) << 1;
741         m_port2_written = 1;
742         write_port2();
743      }
733744   }
734745   /* TOI */
735746   if( CTD >= TOD)
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767778   switch ((m_rmcr & M6800_RMCR_CC_MASK) >> 2)
768779   {
769780   case 0:
770   case 3: // not implemented
771781      m_sci_timer->enable(false);
782      m_use_ext_serclock = false;
772783      break;
773784
785   case 3: // external clock
786      m_use_ext_serclock = true;
787      m_sci_timer->enable(false);
788      break;
789
774790   case 1:
775791   case 2:
776792      {
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778794         int clock = m_clock / m_clock_divider;
779795
780796         m_sci_timer->adjust(attotime::from_hz(clock / divisor), 0, attotime::from_hz(clock / divisor));
797         m_use_ext_serclock = false;
781798      }
782799      break;
783800   }
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844861         case M6800_SERIAL_START:
845862            if (m_trcsr & M6800_TRCSR_TDRE)
846863            {
847               // transmit buffer is empty, send consecutive '1's
848               m_tx = 1;
864               // transmit buffer is empty, send nothing
865               return;
849866            }
850867            else
851868            {
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892909         break;
893910      }
894911
912      m_out_sertx_func((m_tx == 1) ? ASSERT_LINE : CLEAR_LINE);
895913      m_port2_written = 1;
896914      write_port2();
897915   }
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10231041      m_io = &space(AS_IO);
10241042
10251043   m_out_sc2_func.resolve_safe();
1044   m_out_sertx_func.resolve_safe();
10261045   m_sci_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(m6800_cpu_device::sci_tick),this));
10271046
10281047   save_item(NAME(m_ppc.w.l));
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11441163   m_trcsr_read_tdre = 0;
11451164   m_trcsr_read_orfe = 0;
11461165   m_trcsr_read_rdrf = 0;
1166   m_ext_serclock = 0;
1167   m_use_ext_serclock = false;
11471168
11481169   set_rmcr(0);
11491170}
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14791500      {
14801501         m_port2_ddr = data;
14811502         write_port2();
1482
1483         if (m_port2_ddr & 2)
1484            logerror("CPU '%s' PC %04x: warning - port 2 bit 1 set as output (OLVL) - not supported\n",space.device().tag(),space.device().safe_pc());
14851503      }
14861504      break;
14871505
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16831701   }
16841702}
16851703
1704void m6801_cpu_device::m6801_clock_serial()
1705{
1706   if (m_use_ext_serclock)
1707   {
1708      m_ext_serclock++;
16861709
1710      if (m_ext_serclock >= 8)
1711      {
1712         m_ext_serclock = 0;
1713         serial_transmit();
1714         serial_receive();
1715      }
1716   }
1717}
1718
16871719offs_t m6800_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
16881720{
16891721   extern CPU_DISASSEMBLE( m6800 );
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17391771   return CPU_DISASSEMBLE_NAME(nsc8105)(this, buffer, pc, oprom, opram, options);
17401772}
17411773
1742

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