| Previous | 199869 Revisions | Next |
| r24592 Wednesday 31st July, 2013 at 06:22:14 UTC by Aaron Giles |
|---|
| Make sure shift register is clear at the start of a read to simulate the dummy 0 bit. Fix polarity of CS/CLK lines in mitchell.c. |
| [src/emu/machine] | eepromser.c |
| [src/mame/drivers] | mitchell.c |
| r24591 | r24592 | |
|---|---|---|
| 527 | 527 | switch (m_command) |
| 528 | 528 | { |
| 529 | 529 | // advance to the READING_DATA state; data is fetched after first CLK |
| 530 | // reset the shift register to 0 to simulate the dummy 0 bit that happens prior | |
| 531 | // to the first clock | |
| 530 | 532 | case COMMAND_READ: |
| 533 | m_shift_register = 0; | |
| 531 | 534 | set_state(STATE_READING_DATA); |
| 532 | 535 | break; |
| 533 | 536 |
| r24591 | r24592 | |
|---|---|---|
| 96 | 96 | |
| 97 | 97 | WRITE8_MEMBER(mitchell_state::eeprom_cs_w) |
| 98 | 98 | { |
| 99 | m_eeprom->cs_write(data ? | |
| 99 | m_eeprom->cs_write(data ? ASSERT_LINE : CLEAR_LINE); | |
| 100 | 100 | } |
| 101 | 101 | |
| 102 | 102 | WRITE8_MEMBER(mitchell_state::eeprom_clock_w) |
| 103 | 103 | { |
| 104 | m_eeprom->clk_write(data ? | |
| 104 | m_eeprom->clk_write(data ? ASSERT_LINE : CLEAR_LINE); | |
| 105 | 105 | } |
| 106 | 106 | |
| 107 | 107 | WRITE8_MEMBER(mitchell_state::eeprom_serial_w) |
| 108 | 108 | { |
| 109 | m_eeprom->di_write(data); | |
| 109 | m_eeprom->di_write(data & 1); | |
| 110 | 110 | } |
| 111 | 111 | |
| 112 | 112 |
| Previous | 199869 Revisions | Next |