MAME SVN History

199869 Revisions

r24075 Thursday 4th July, 2013 at 20:17:04 UTC by Wilbert Pol
arm7.c: Modernized cpu core. (nw)

[src/emu/cpu]	cpu.mak
[src/emu/cpu/arm7]	arm7.c arm7.h arm7core.c arm7core.h arm7drc.c arm7help.h arm7ops.c ~~arm7ops.h~~ arm7tdrc.c arm7thmb.c ~~arm7thmb.h~~

trunk/src/emu/cpu/arm7/arm7thmb.h
r24074	r24075
1
2
3
4		const void tg00_0(arm_state *arm, UINT32 pc, UINT32 insn);
5		const void tg00_1(arm_state *arm, UINT32 pc, UINT32 insn);
6		const void tg01_0(arm_state *arm, UINT32 pc, UINT32 insn);
7		const void tg01_10(arm_state *arm, UINT32 pc, UINT32 insn);
8		const void tg01_11(arm_state *arm, UINT32 pc, UINT32 insn);
9		const void tg01_12(arm_state *arm, UINT32 pc, UINT32 insn);
10		const void tg01_13(arm_state *arm, UINT32 pc, UINT32 insn);
11		const void tg02_0(arm_state *arm, UINT32 pc, UINT32 insn);
12		const void tg02_1(arm_state *arm, UINT32 pc, UINT32 insn);
13		const void tg03_0(arm_state *arm, UINT32 pc, UINT32 insn);
14		const void tg03_1(arm_state *arm, UINT32 pc, UINT32 insn);
15		const void tg04_00_00(arm_state *arm, UINT32 pc, UINT32 insn);
16		const void tg04_00_01(arm_state *arm, UINT32 pc, UINT32 insn);
17		const void tg04_00_02(arm_state *arm, UINT32 pc, UINT32 insn);
18		const void tg04_00_03(arm_state *arm, UINT32 pc, UINT32 insn);
19		const void tg04_00_04(arm_state *arm, UINT32 pc, UINT32 insn);
20		const void tg04_00_05(arm_state *arm, UINT32 pc, UINT32 insn);
21		const void tg04_00_06(arm_state *arm, UINT32 pc, UINT32 insn);
22		const void tg04_00_07(arm_state *arm, UINT32 pc, UINT32 insn);
23		const void tg04_00_08(arm_state *arm, UINT32 pc, UINT32 insn);
24		const void tg04_00_09(arm_state *arm, UINT32 pc, UINT32 insn);
25		const void tg04_00_0a(arm_state *arm, UINT32 pc, UINT32 insn);
26		const void tg04_00_0b(arm_state *arm, UINT32 pc, UINT32 insn);
27		const void tg04_00_0c(arm_state *arm, UINT32 pc, UINT32 insn);
28		const void tg04_00_0d(arm_state *arm, UINT32 pc, UINT32 insn);
29		const void tg04_00_0e(arm_state *arm, UINT32 pc, UINT32 insn);
30		const void tg04_00_0f(arm_state *arm, UINT32 pc, UINT32 insn);
31		const void tg04_01_00(arm_state *arm, UINT32 pc, UINT32 insn);
32		const void tg04_01_01(arm_state *arm, UINT32 pc, UINT32 insn);
33		const void tg04_01_02(arm_state *arm, UINT32 pc, UINT32 insn);
34		const void tg04_01_03(arm_state *arm, UINT32 pc, UINT32 insn);
35		const void tg04_01_10(arm_state *arm, UINT32 pc, UINT32 insn);
36		const void tg04_01_11(arm_state *arm, UINT32 pc, UINT32 insn);
37		const void tg04_01_12(arm_state *arm, UINT32 pc, UINT32 insn);
38		const void tg04_01_13(arm_state *arm, UINT32 pc, UINT32 insn);
39		const void tg04_01_20(arm_state *arm, UINT32 pc, UINT32 insn);
40		const void tg04_01_21(arm_state *arm, UINT32 pc, UINT32 insn);
41		const void tg04_01_22(arm_state *arm, UINT32 pc, UINT32 insn);
42		const void tg04_01_23(arm_state *arm, UINT32 pc, UINT32 insn);
43		const void tg04_01_30(arm_state *arm, UINT32 pc, UINT32 insn);
44		const void tg04_01_31(arm_state *arm, UINT32 pc, UINT32 insn);
45		const void tg04_01_32(arm_state *arm, UINT32 pc, UINT32 insn);
46		const void tg04_01_33(arm_state *arm, UINT32 pc, UINT32 insn);
47		const void tg04_0203(arm_state *arm, UINT32 pc, UINT32 insn);
48		const void tg05_0(arm_state *arm, UINT32 pc, UINT32 insn);
49		const void tg05_1(arm_state *arm, UINT32 pc, UINT32 insn);
50		const void tg05_2(arm_state *arm, UINT32 pc, UINT32 insn);
51		const void tg05_3(arm_state *arm, UINT32 pc, UINT32 insn);
52		const void tg05_4(arm_state *arm, UINT32 pc, UINT32 insn);
53		const void tg05_5(arm_state *arm, UINT32 pc, UINT32 insn);
54		const void tg05_6(arm_state *arm, UINT32 pc, UINT32 insn);
55		const void tg05_7(arm_state *arm, UINT32 pc, UINT32 insn);
56		const void tg06_0(arm_state *arm, UINT32 pc, UINT32 insn);
57		const void tg06_1(arm_state *arm, UINT32 pc, UINT32 insn);
58		const void tg07_0(arm_state *arm, UINT32 pc, UINT32 insn);
59		const void tg07_1(arm_state *arm, UINT32 pc, UINT32 insn);
60		const void tg08_0(arm_state *arm, UINT32 pc, UINT32 insn);
61		const void tg08_1(arm_state *arm, UINT32 pc, UINT32 insn);
62		const void tg09_0(arm_state *arm, UINT32 pc, UINT32 insn);
63		const void tg09_1(arm_state *arm, UINT32 pc, UINT32 insn);
64		const void tg0a_0(arm_state *arm, UINT32 pc, UINT32 insn);
65		const void tg0a_1(arm_state *arm, UINT32 pc, UINT32 insn);
66		const void tg0b_0(arm_state *arm, UINT32 pc, UINT32 insn);
67		const void tg0b_1(arm_state *arm, UINT32 pc, UINT32 insn);
68		const void tg0b_2(arm_state *arm, UINT32 pc, UINT32 insn);
69		const void tg0b_3(arm_state *arm, UINT32 pc, UINT32 insn);
70		const void tg0b_4(arm_state *arm, UINT32 pc, UINT32 insn);
71		const void tg0b_5(arm_state *arm, UINT32 pc, UINT32 insn);
72		const void tg0b_6(arm_state *arm, UINT32 pc, UINT32 insn);
73		const void tg0b_7(arm_state *arm, UINT32 pc, UINT32 insn);
74		const void tg0b_8(arm_state *arm, UINT32 pc, UINT32 insn);
75		const void tg0b_9(arm_state *arm, UINT32 pc, UINT32 insn);
76		const void tg0b_a(arm_state *arm, UINT32 pc, UINT32 insn);
77		const void tg0b_b(arm_state *arm, UINT32 pc, UINT32 insn);
78		const void tg0b_c(arm_state *arm, UINT32 pc, UINT32 insn);
79		const void tg0b_d(arm_state *arm, UINT32 pc, UINT32 insn);
80		const void tg0b_e(arm_state *arm, UINT32 pc, UINT32 insn);
81		const void tg0b_f(arm_state *arm, UINT32 pc, UINT32 insn);
82		const void tg0c_0(arm_state *arm, UINT32 pc, UINT32 insn);
83		const void tg0c_1(arm_state *arm, UINT32 pc, UINT32 insn);
84		const void tg0d_0(arm_state *arm, UINT32 pc, UINT32 insn);
85		const void tg0d_1(arm_state *arm, UINT32 pc, UINT32 insn);
86		const void tg0d_2(arm_state *arm, UINT32 pc, UINT32 insn);
87		const void tg0d_3(arm_state *arm, UINT32 pc, UINT32 insn);
88		const void tg0d_4(arm_state *arm, UINT32 pc, UINT32 insn);
89		const void tg0d_5(arm_state *arm, UINT32 pc, UINT32 insn);
90		const void tg0d_6(arm_state *arm, UINT32 pc, UINT32 insn);
91		const void tg0d_7(arm_state *arm, UINT32 pc, UINT32 insn);
92		const void tg0d_8(arm_state *arm, UINT32 pc, UINT32 insn);
93		const void tg0d_9(arm_state *arm, UINT32 pc, UINT32 insn);
94		const void tg0d_a(arm_state *arm, UINT32 pc, UINT32 insn);
95		const void tg0d_b(arm_state *arm, UINT32 pc, UINT32 insn);
96		const void tg0d_c(arm_state *arm, UINT32 pc, UINT32 insn);
97		const void tg0d_d(arm_state *arm, UINT32 pc, UINT32 insn);
98		const void tg0d_e(arm_state *arm, UINT32 pc, UINT32 insn);
99		const void tg0d_f(arm_state *arm, UINT32 pc, UINT32 insn);
100		const void tg0e_0(arm_state *arm, UINT32 pc, UINT32 insn);
101		const void tg0e_1(arm_state *arm, UINT32 pc, UINT32 insn);
102		const void tg0f_0(arm_state *arm, UINT32 pc, UINT32 insn);
103		const void tg0f_1(arm_state *arm, UINT32 pc, UINT32 insn);

trunk/src/emu/cpu/arm7/arm7ops.h
r24074	r24075
1
2		const void arm7ops_0123(arm_state *arm, UINT32 insn);
3		const void arm7ops_4567(arm_state *arm, UINT32 insn);
4		const void arm7ops_89(arm_state *arm, UINT32 insn);
5		const void arm7ops_ab(arm_state *arm, UINT32 insn);
6		const void arm7ops_cd(arm_state *arm, UINT32 insn);
7		const void arm7ops_e(arm_state *arm, UINT32 insn);
8		const void arm7ops_f(arm_state *arm, UINT32 insn);

trunk/src/emu/cpu/arm7/arm7drc.c
r24074	r24075
36	36	**
37	37	*****************************************************************************/
38	38
39		#include "emu.h"
40		#include "debugger.h"
41		#include "arm7fe.h"
42		#include "cpu/drcfe.h"
43		#include "cpu/drcuml.h"
44		#include "cpu/drcumlsh.h"
45	39
46		#ifdef ARM7_USE_DRC
47
48		using namespace uml;
49
50	40	/***************************************************************************
51	41	DEBUGGING
52	42	***************************************************************************/
r24074	r24075
61	51	CONSTANTS
62	52	***************************************************************************/
63	53
64		typedef const void (arm7thumb_drcophandler)(arm_state, drcuml_block, compiler_state, opcode_desc*);
65
66	54	#include "arm7tdrc.c"
67	55
68	56	/* map variables */
69		#define MAPVAR_PC M0
70		#define MAPVAR_CYCLES M1
	57	#define MAPVAR_PC uml::M0
	58	#define MAPVAR_CYCLES uml::M1
71	59
72	60	/* size of the execution code cache */
73	61	#define CACHE_SIZE (32 * 1024 * 1024)
r24074	r24075
85	73	#define EXECUTE_RESET_CACHE 3
86	74
87	75
88
89	76	/***************************************************************************
90		MACROS
91		***************************************************************************/
92
93		/***************************************************************************
94		STRUCTURES & TYPEDEFS
95		***************************************************************************/
96
97		/* fast RAM info */
98		struct fast_ram_info
99		{
100		offs_t start; /* start of the RAM block */
101		offs_t end; /* end of the RAM block */
102		UINT8 readonly; /* TRUE if read-only */
103		void * base; /* base in memory where the RAM lives */
104		};
105
106
107		/* internal compiler state */
108		struct compiler_state
109		{
110		UINT32 cycles; /* accumulated cycles */
111		UINT8 checkints; /* need to check interrupts before next instruction */
112		UINT8 checksoftints; /* need to check software interrupts before next instruction */
113		code_label labelnum; /* index for local labels */
114		};
115
116
117		/* ARM7 registers */
118		struct arm7imp_state
119		{
120		/* core state */
121		drc_cache * cache; /* pointer to the DRC code cache */
122		drcuml_state * drcuml; /* DRC UML generator state */
123		arm7_frontend * drcfe; /* pointer to the DRC front-end state */
124		UINT32 drcoptions; /* configurable DRC options */
125
126		/* internal stuff */
127		UINT8 cache_dirty; /* true if we need to flush the cache */
128		UINT32 jmpdest; /* destination jump target */
129
130		/* parameters for subroutines */
131		UINT64 numcycles; /* return value from gettotalcycles */
132		UINT32 mode; /* current global mode */
133		const char * format; /* format string for print_debug */
134		UINT32 arg0; /* print_debug argument 1 */
135		UINT32 arg1; /* print_debug argument 2 */
136
137		/* register mappings */
138		parameter regmap[NUM_REGS]; /* parameter to register mappings for all 16 integer registers */
139
140		/* subroutines */
141		code_handle * entry; /* entry point */
142		code_handle * nocode; /* nocode exception handler */
143		code_handle * out_of_cycles; /* out of cycles exception handler */
144		code_handle * tlb_translate; /* tlb translation handler */
145		code_handle * detect_fault; /* tlb fault detection handler */
146		code_handle * check_irq; /* irq check handler */
147		code_handle * read8; /* read byte */
148		code_handle * write8; /* write byte */
149		code_handle * read16; /* read half */
150		code_handle * write16; /* write half */
151		code_handle * read32; /* read word */
152		code_handle * write32; /* write word */
153
154		/* fast RAM */
155		UINT32 fastram_select;
156		fast_ram_info fastram[ARM7_MAX_FASTRAM];
157		};
158
159
160
161		/***************************************************************************
162		FUNCTION PROTOTYPES
163		***************************************************************************/
164
165		static void code_flush_cache(arm_state *arm);
166		static void code_compile_block(arm_state *arm, UINT8 mode, offs_t pc);
167
168		static void cfunc_printf_exception(void *param);
169		static void cfunc_get_cycles(void *param);
170
171		static void static_generate_entry_point(arm_state *arm);
172		static void static_generate_nocode_handler(arm_state *arm);
173		static void static_generate_out_of_cycles(arm_state *arm);
174		static void static_generate_tlb_translate(arm_state *arm);
175		static void static_generate_detect_fault(arm_state *arm);
176		static void static_generate_check_irq(arm_state *arm);
177
178		static void generate_update_cycles(arm_state arm, drcuml_block block, compiler_state *compiler, parameter param, int allow_exception);
179		static void generate_checksum_block(arm_state arm, drcuml_block block, compiler_state compiler, const opcode_desc seqhead, const opcode_desc *seqlast);
180		static void generate_sequence_instruction(arm_state arm, drcuml_block block, compiler_state compiler, const opcode_desc desc);
181		static void generate_delay_slot_and_branch(arm_state arm, drcuml_block block, compiler_state compiler, const opcode_desc desc, UINT8 linkreg);
182		static int generate_opcode(arm_state arm, drcuml_block block, compiler_state compiler, const opcode_desc desc);
183
184		static void log_add_disasm_comment(arm_state arm, drcuml_block block, UINT32 pc, UINT32 op);
185		static const char *log_desc_flags_to_string(UINT32 flags);
186		static void log_register_list(drcuml_state drcuml, const char string, const UINT32 reglist, const UINT32 regnostarlist);
187		static void log_opcode_desc(drcuml_state drcuml, const opcode_desc desclist, int indent);
188
189		/***************************************************************************
190		PRIVATE GLOBAL VARIABLES
191		***************************************************************************/
192
193		/***************************************************************************
194	77	INLINE FUNCTIONS
195	78	***************************************************************************/
196	79
197		INLINE arm_state get_safe_token(device_t device)
198		{
199		assert(device != NULL);
200		assert(device->type() == ARM7 \|\|
201		device->type() == ARM7_BE \|\|
202		device->type() == ARM7500 \|\|
203		device->type() == ARM9 \|\|
204		device->type() == ARM920T \|\|
205		device->type() == PXA255 \|\|
206		device->type() == SA1110);
207		return (arm_state )downcast<legacy_cpu_device >(device)->token();
208		}
209
210	80	/*-------------------------------------------------
211	81	epc - compute the exception PC from a
212	82	descriptor
r24074	r24075
223	93	already allocated
224	94	-------------------------------------------------*/
225	95
226		INLINE void alloc_handle(drcuml_state drcuml, code_handle handleptr, const char name)
	96	INLINE void alloc_handle(drcuml_state drcuml, uml::code_handle handleptr, const char name)
227	97	{
228	98	if (*handleptr == NULL)
229	99	*handleptr = drcuml->handle_alloc(name);
r24074	r24075
235	105	registers
236	106	-------------------------------------------------*/
237	107
238		~~INLINE~~ void load_fast_iregs(~~arm_state arm,~~ drcuml_block block)
	108	void arm7_cpu_device::load_fast_iregs(drcuml_block *block)
239	109	{
240	110	int regnum;
241	111
242		for (regnum = 0; regnum < ARRAY_LENGTH(arm->impstate->regmap); regnum++)
243		if (arm->impstate->regmap[regnum].is_int_register())
244		UML_DMOV(block, ireg(arm->impstate->regmap[regnum].ireg() - REG_I0), mem(&arm->r[regnum]));
	112	for (regnum = 0; regnum < ARRAY_LENGTH(m_impstate.regmap); regnum++)
	113	if (m_impstate.regmap[regnum].is_int_register())
	114	UML_DMOV(block, uml::ireg(m_impstate.regmap[regnum].ireg() - uml::REG_I0), uml::mem(&m_r[regnum]));
245	115	}
246	116
247	117
r24074	r24075
250	120	registers
251	121	-------------------------------------------------*/
252	122
253		~~INLINE~~ void save_fast_iregs(~~arm_state arm,~~ drcuml_block block)
	123	void arm7_cpu_device::save_fast_iregs(drcuml_block *block)
254	124	{
255	125	int regnum;
256	126
257		for (regnum = 0; regnum < ARRAY_LENGTH(arm->impstate->regmap); regnum++)
258		if (arm->impstate->regmap[regnum].is_int_register())
259		UML_DMOV(block, mem(&arm->r[regnum]), ireg(arm->impstate->regmap[regnum].ireg() - REG_I0));
	127	for (regnum = 0; regnum < ARRAY_LENGTH(m_impstate.regmap); regnum++)
	128	if (m_impstate.regmap[regnum].is_int_register())
	129	UML_DMOV(block, uml::mem(&m_r[regnum]), uml::ireg(m_impstate.regmap[regnum].ireg() - uml::REG_I0));
260	130	}
261	131
262	132
r24074	r24075
269	139	arm7_init - initialize the processor
270	140	-------------------------------------------------*/
271	141
272		~~static~~ void arm7_~~init(arm7_flavor flavor, int bigendian, lega~~c~~y_c~~pu_device *d~~evi~~c~~e, device~~_i~~rq_ack~~n~~owledge_callback~~ i~~rqcallback~~)
	142	void arm7_cpu_device::arm7_drc_init()
273	143	{
274		arm_state *arm;
275	144	drc_cache *cache;
276	145	drcbe_info beinfo;
277	146	UINT32 flags = 0;
278		int regnum;
279	147
280		arm7_core_init(device, "arm7");
281	148	/* allocate enough space for the cache and the core */
282		cache = auto_alloc(~~device->~~machine(), drc_cache(CACHE_SIZE ~~+ sizeof(*arm)~~));
	149	cache = auto_alloc(machine(), drc_cache(CACHE_SIZE));
283	150	if (cache == NULL)
284		fatalerror("Unable to allocate cache of size %d\n", (UINT32)(CACHE_SIZE ~~+ sizeof(*arm)~~));
	151	fatalerror("Unable to allocate cache of size %d\n", (UINT32)(CACHE_SIZE));
285	152
286		/* allocate the core memory */
287		(arm_state )device->token() = arm = (arm_state )cache->alloc_near(sizeof(*arm));
288		memset(arm, 0, sizeof(*arm));
289
290		/* initialize the core */
291		arm7_core_init(device, "arm7");
292
293	153	/* allocate the implementation-specific state from the full cache */
294		arm->impstate = (arm7imp_state )cache->alloc_near(sizeof(arm->impstate));
295		memset(arm->impstate, 0, sizeof(*arm->impstate));
296		arm->impstate->cache = cache;
	154	memset(&m_impstate, 0, sizeof(m_impstate));
	155	m_impstate.cache = cache;
297	156
298	157	/* initialize the UML generator */
299	158	if (FORCE_C_BACKEND)
r24074	r24075
302	161	flags \|= DRCUML_OPTION_LOG_UML;
303	162	if (LOG_NATIVE)
304	163	flags \|= DRCUML_OPTION_LOG_NATIVE;
305		arm->impstate->drcuml = ~~auto_alloc(device->machi~~ne~~(),~~ drcuml_state(~~dev~~ice, cache, flags, 1, 32, 1));
	164	m_impstate.drcuml = new drcuml_state(this, cache, flags, 1, 32, 1);
306	165
307	166	/* add symbols for our stuff */
308		arm->impstate->drcuml->symbol_add(&arm->icount, sizeof(arm->icount), "icount");
	167	m_impstate.drcuml->symbol_add(&m_icount, sizeof(m_icount), "icount");
309	168	for (int regnum = 0; regnum < 37; regnum++)
310	169	{
311	170	char buf[10];
312	171	sprintf(buf, "r%d", regnum);
313		arm->impstate->drcuml->symbol_add(&arm->r[regnum], sizeof(arm->r[regnum]), buf);
	172	m_impstate.drcuml->symbol_add(&m_r[regnum], sizeof(m_r[regnum]), buf);
314	173	}
315		arm->impstate->drcuml->symbol_add(&arm->impstate->mode, sizeof(arm->impstate->mode), "mode");
316		arm->impstate->drcuml->symbol_add(&arm->impstate->arg0, sizeof(arm->impstate->arg0), "arg0");
317		arm->impstate->drcuml->symbol_add(&arm->impstate->arg1, sizeof(arm->impstate->arg1), "arg1");
318		arm->impstate->drcuml->symbol_add(&arm->impstate->numcycles, sizeof(arm->impstate->numcycles), "numcycles");
319		arm->impstate->drcuml->symbol_add(&arm->impstate->fpmode, sizeof(arm->impstate->fpmode), "fpmode");
	174	m_impstate.drcuml->symbol_add(&m_impstate.mode, sizeof(m_impstate.mode), "mode");
	175	m_impstate.drcuml->symbol_add(&m_impstate.arg0, sizeof(m_impstate.arg0), "arg0");
	176	m_impstate.drcuml->symbol_add(&m_impstate.arg1, sizeof(m_impstate.arg1), "arg1");
	177	m_impstate.drcuml->symbol_add(&m_impstate.numcycles, sizeof(m_impstate.numcycles), "numcycles");
	178	//m_impstate.drcuml->symbol_add(&m_impstate.fpmode, sizeof(m_impstate.fpmode), "fpmode"); // TODO
320	179
321	180	/* initialize the front-end helper */
322		arm->impstate->drcfe = auto_alloc(~~device->~~machine(), arm7_frontend(*arm, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE));
	181	//m_impstate.drcfe = auto_alloc(machine(), arm7_frontend(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE));
323	182
324	183	/* allocate memory for cache-local state and initialize it */
325		memcpy(arm->impstate->fpmode, fpmode_source, sizeof(fpmode_source));
	184	//memcpy(&m_impstate.fpmode, fpmode_source, sizeof(fpmode_source)); // TODO
326	185
327	186	/* compute the register parameters */
328	187	for (int regnum = 0; regnum < 37; regnum++)
329	188	{
330		arm->impstate->regmap[regnum] = (regnum == 0) ? parameter(0) : parameter::make_memory(&arm->r[regnum]);
	189	m_impstate.regmap[regnum] = (regnum == 0) ? uml::parameter(0) : uml::parameter::make_memory(&m_r[regnum]);
331	190	}
332	191
333	192	/* if we have registers to spare, assign r2, r3, r4 to leftovers */
334		if (!DISABLE_FAST_REGISTERS)
	193	//if (!DISABLE_FAST_REGISTERS) // TODO
335	194	{
336		arm->impstate->drcuml->get_backend_info(beinfo);
	195	m_impstate.drcuml->get_backend_info(beinfo);
337	196	if (beinfo.direct_iregs > 4)
338	197	{ // PC
339		arm->impstate->regmap[eR15] = I4;
	198	m_impstate.regmap[eR15] = uml::I4;
340	199	}
341	200	if (beinfo.direct_iregs > 5)
342	201	{ // Status
343		arm->impstate->regmap[eCPSR] = I5;
	202	m_impstate.regmap[eCPSR] = uml::I5;
344	203	}
345	204	if (beinfo.direct_iregs > 6)
346	205	{ // SP
347		arm->impstate->regmap[eR13] = I6;
	206	m_impstate.regmap[eR13] = uml::I6;
348	207	}
349	208	}
350	209
351	210	/* mark the cache dirty so it is updated on next execute */
352		arm->impstate->cache_dirty = TRUE;
	211	m_impstate.cache_dirty = TRUE;
353	212	}
354	213
355	214
356	215	/*-------------------------------------------------
357		arm7_reset - reset the processor
358		-------------------------------------------------*/
359
360		static CPU_RESET( arm7 )
361		{
362		arm_state *arm = get_safe_token(device);
363
364		/* reset the common code and mark the cache dirty */
365		arm7_core_reset(arm);
366
367		arm->impstate->cache_dirty = TRUE;
368
369		arm->archRev = 4; // ARMv4
370		arm->archFlags = eARM_ARCHFLAGS_T; // has Thumb
371		}
372
373		static CPU_RESET( arm7_be )
374		{
375		arm_state *arm = get_safe_token(device);
376
377		/* reset the common code and mark the cache dirty */
378		arm7_core_reset(arm);
379
380		arm->impstate->cache_dirty = TRUE;
381
382		arm->endian = ENDIANNESS_BIG;
383
384		arm->archRev = 4; // ARMv4
385		arm->archFlags = eARM_ARCHFLAGS_T; // has Thumb
386		}
387
388		static CPU_RESET( arm7500 )
389		{
390		arm_state *arm = get_safe_token(device);
391
392		// must call core reset
393		arm7_core_reset(device);
394
395		arm->impstate->cache_dirty = TRUE;
396
397		arm->archRev = 3; // ARMv3
398		arm->archFlags = eARM_ARCHFLAGS_MODE26;
399		}
400
401		static CPU_RESET( arm9 )
402		{
403		arm_state *arm = get_safe_token(device);
404
405		// must call core reset
406		arm7_core_reset(device);
407
408		arm->impstate->cache_dirty = TRUE;
409
410		arm->archRev = 5; // ARMv5
411		arm->archFlags = eARM_ARCHFLAGS_T \| eARM_ARCHFLAGS_E; // has TE extensions
412		}
413
414		static CPU_RESET( arm920t )
415		{
416		arm_state *arm = get_safe_token(device);
417
418		// must call core reset
419		arm7_core_reset(device);
420
421		arm->impstate->cache_dirty = TRUE;
422
423		arm->archRev = 4; // ARMv4
424		arm->archFlags = eARM_ARCHFLAGS_T; // has T extension
425		}
426
427		static CPU_RESET( pxa255 )
428		{
429		arm_state *arm = get_safe_token(device);
430
431		// must call core reset
432		arm7_core_reset(device);
433
434		arm->impstate->cache_dirty = TRUE;
435
436		arm->archRev = 5; // ARMv5
437		arm->archFlags = eARM_ARCHFLAGS_T \| eARM_ARCHFLAGS_E \| eARM_ARCHFLAGS_XSCALE; // has TE and XScale extensions
438		}
439
440		static CPU_RESET( sa1110 )
441		{
442		arm_state *arm = get_safe_token(device);
443
444		// must call core reset
445		arm7_core_reset(device);
446
447		arm->impstate->cache_dirty = TRUE;
448
449		arm->archRev = 4; // ARMv4
450		arm->archFlags = eARM_ARCHFLAGS_SA; // has StrongARM, no Thumb, no Enhanced DSP
451		}
452
453		/*-------------------------------------------------
454	216	arm7_execute - execute the CPU for the
455	217	specified number of cycles
456	218	-------------------------------------------------*/
457	219
458		~~stat~~ic ~~CPU_EXECUTE(~~ arm7 )
	220	void arm7_cpu_device::execute_run_drc()
459	221	{
460		arm_state *arm = get_safe_token(device);
461		drcuml_state *drcuml = arm->impstate->drcuml;
	222	drcuml_state *drcuml = m_impstate.drcuml;
462	223	int execute_result;
463	224
464	225	/* reset the cache if dirty */
465		if (arm->impstate->cache_dirty)
466		code_flush_cache(arm);
467		arm->impstate->cache_dirty = FALSE;
	226	if (m_impstate.cache_dirty)
	227	code_flush_cache();
	228	m_impstate.cache_dirty = FALSE;
468	229
469	230	/* execute */
470	231	do
471	232	{
472	233	/* run as much as we can */
473		execute_result = drcuml->execute(*arm->impstate->entry);
	234	execute_result = drcuml->execute(*m_impstate.entry);
474	235
475	236	/* if we need to recompile, do it */
476	237	if (execute_result == EXECUTE_MISSING_CODE)
477		code_compile_block(arm~~, arm->~~impstate->mode, arm->r[eR15]);
	238	code_compile_block(m_impstate.mode, m_r[eR15]);
478	239	else if (execute_result == EXECUTE_UNMAPPED_CODE)
479		fatalerror("Attempted to execute unmapped code at PC=%08X\n", arm->r[eR15]);
	240	fatalerror("Attempted to execute unmapped code at PC=%08X\n", m_r[eR15]);
480	241	else if (execute_result == EXECUTE_RESET_CACHE)
481		code_flush_cache(~~arm~~);
	242	code_flush_cache();
482	243
483	244	} while (execute_result != EXECUTE_OUT_OF_CYCLES);
484	245	}
r24074	r24075
487	248	arm7_exit - cleanup from execution
488	249	-------------------------------------------------*/
489	250
490		~~stat~~ic ~~CPU~~_~~EXIT(~~ arm7 )
	251	void arm7_cpu_device::arm7_drc_exit()
491	252	{
492		arm_state *arm = get_safe_token(device);
493
494	253	/* clean up the DRC */
495		auto_free(device->machine(), arm->impstate->drcfe);
496		auto_free(device->machine(), arm->impstate->drcuml);
497		auto_free(device->machine(), arm->impstate->cache);
	254	//auto_free(machine(), m_impstate.drcfe);
	255	delete m_impstate.drcuml;
	256	auto_free(machine(), m_impstate.cache);
498	257	}
499	258
500	259
501	260	/*-------------------------------------------------
502		arm7_translate - perform virtual-to-physical
503		address translation
504		-------------------------------------------------*/
505
506		static CPU_TRANSLATE( arm7 )
507		{
508		arm_state *arm = get_safe_token(device);
509
510		/* only applies to the program address space and only does something if the MMU's enabled */
511		if( space == AS_PROGRAM && ( COPRO_CTRL & COPRO_CTRL_MMU_EN ) )
512		{
513		return arm7_tlb_translate(arm, address, 0);
514		}
515		return TRUE;
516		}
517
518
519		static CPU_DISASSEMBLE( arm7 )
520		{
521		CPU_DISASSEMBLE( arm7arm );
522		CPU_DISASSEMBLE( arm7thumb );
523
524		arm_state *arm = get_safe_token(device);
525
526		if (T_IS_SET(GET_CPSR))
527		return CPU_DISASSEMBLE_CALL(arm7thumb);
528		else
529		return CPU_DISASSEMBLE_CALL(arm7arm);
530		}
531
532
533		/*-------------------------------------------------
534		arm7_set_info - set information about a given
535		CPU instance
536		-------------------------------------------------*/
537
538		static CPU_SET_INFO( arm7 )
539		{
540		arm_state *arm = get_safe_token(device);
541
542		switch (state)
543		{
544		/* --- the following bits of info are set as 64-bit signed integers --- */
545
546		/* interrupt lines/exceptions */
547		case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: set_irq_line(arm, ARM7_IRQ_LINE, info->i); break;
548		case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: set_irq_line(arm, ARM7_FIRQ_LINE, info->i); break;
549		case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: set_irq_line(arm, ARM7_ABORT_EXCEPTION, info->i); break;
550		case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: set_irq_line(arm, ARM7_ABORT_PREFETCH_EXCEPTION, info->i); break;
551		case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: set_irq_line(arm, ARM7_UNDEFINE_EXCEPTION, info->i); break;
552
553		/* registers shared by all operating modes */
554		case CPUINFO_INT_REGISTER + ARM7_R0: ARM7REG( 0) = info->i; break;
555		case CPUINFO_INT_REGISTER + ARM7_R1: ARM7REG( 1) = info->i; break;
556		case CPUINFO_INT_REGISTER + ARM7_R2: ARM7REG( 2) = info->i; break;
557		case CPUINFO_INT_REGISTER + ARM7_R3: ARM7REG( 3) = info->i; break;
558		case CPUINFO_INT_REGISTER + ARM7_R4: ARM7REG( 4) = info->i; break;
559		case CPUINFO_INT_REGISTER + ARM7_R5: ARM7REG( 5) = info->i; break;
560		case CPUINFO_INT_REGISTER + ARM7_R6: ARM7REG( 6) = info->i; break;
561		case CPUINFO_INT_REGISTER + ARM7_R7: ARM7REG( 7) = info->i; break;
562		case CPUINFO_INT_REGISTER + ARM7_R8: ARM7REG( 8) = info->i; break;
563		case CPUINFO_INT_REGISTER + ARM7_R9: ARM7REG( 9) = info->i; break;
564		case CPUINFO_INT_REGISTER + ARM7_R10: ARM7REG(10) = info->i; break;
565		case CPUINFO_INT_REGISTER + ARM7_R11: ARM7REG(11) = info->i; break;
566		case CPUINFO_INT_REGISTER + ARM7_R12: ARM7REG(12) = info->i; break;
567		case CPUINFO_INT_REGISTER + ARM7_R13: ARM7REG(13) = info->i; break;
568		case CPUINFO_INT_REGISTER + ARM7_R14: ARM7REG(14) = info->i; break;
569		case CPUINFO_INT_REGISTER + ARM7_R15: ARM7REG(15) = info->i; break;
570		case CPUINFO_INT_REGISTER + ARM7_CPSR: SET_CPSR(info->i); break;
571
572		case CPUINFO_INT_PC:
573		case CPUINFO_INT_REGISTER + ARM7_PC: R15 = info->i; break;
574		case CPUINFO_INT_SP: SetRegister(arm, 13,info->i); break;
575
576		/* FIRQ Mode Shadowed Registers */
577		case CPUINFO_INT_REGISTER + ARM7_FR8: ARM7REG(eR8_FIQ) = info->i; break;
578		case CPUINFO_INT_REGISTER + ARM7_FR9: ARM7REG(eR9_FIQ) = info->i; break;
579		case CPUINFO_INT_REGISTER + ARM7_FR10: ARM7REG(eR10_FIQ) = info->i; break;
580		case CPUINFO_INT_REGISTER + ARM7_FR11: ARM7REG(eR11_FIQ) = info->i; break;
581		case CPUINFO_INT_REGISTER + ARM7_FR12: ARM7REG(eR12_FIQ) = info->i; break;
582		case CPUINFO_INT_REGISTER + ARM7_FR13: ARM7REG(eR13_FIQ) = info->i; break;
583		case CPUINFO_INT_REGISTER + ARM7_FR14: ARM7REG(eR14_FIQ) = info->i; break;
584		case CPUINFO_INT_REGISTER + ARM7_FSPSR: ARM7REG(eSPSR_FIQ) = info->i; break;
585
586		/* IRQ Mode Shadowed Registers */
587		case CPUINFO_INT_REGISTER + ARM7_IR13: ARM7REG(eR13_IRQ) = info->i; break;
588		case CPUINFO_INT_REGISTER + ARM7_IR14: ARM7REG(eR14_IRQ) = info->i; break;
589		case CPUINFO_INT_REGISTER + ARM7_ISPSR: ARM7REG(eSPSR_IRQ) = info->i; break;
590
591		/* Supervisor Mode Shadowed Registers */
592		case CPUINFO_INT_REGISTER + ARM7_SR13: ARM7REG(eR13_SVC) = info->i; break;
593		case CPUINFO_INT_REGISTER + ARM7_SR14: ARM7REG(eR14_SVC) = info->i; break;
594		case CPUINFO_INT_REGISTER + ARM7_SSPSR: ARM7REG(eSPSR_SVC) = info->i; break;
595
596		/* Abort Mode Shadowed Registers */
597		case CPUINFO_INT_REGISTER + ARM7_AR13: ARM7REG(eR13_ABT) = info->i; break;
598		case CPUINFO_INT_REGISTER + ARM7_AR14: ARM7REG(eR14_ABT) = info->i; break;
599		case CPUINFO_INT_REGISTER + ARM7_ASPSR: ARM7REG(eSPSR_ABT) = info->i; break;
600
601		/* Undefined Mode Shadowed Registers */
602		case CPUINFO_INT_REGISTER + ARM7_UR13: ARM7REG(eR13_UND) = info->i; break;
603		case CPUINFO_INT_REGISTER + ARM7_UR14: ARM7REG(eR14_UND) = info->i; break;
604		case CPUINFO_INT_REGISTER + ARM7_USPSR: ARM7REG(eSPSR_UND) = info->i; break;
605		}
606		}
607
608
609		/*-------------------------------------------------
610		arm7_get_info - return information about a
611		given CPU instance
612		-------------------------------------------------*/
613
614		static CPU_GET_INFO( arm7 )
615		{
616		arm_state *arm = get_safe_token(device);
617
618		switch (state)
619		{
620		/* --- the following bits of info are returned as 64-bit signed integers --- */
621
622		/* cpu implementation data */
623		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(arm_state); break;
624		case CPUINFO_INT_INPUT_LINES: info->i = ARM7_NUM_LINES; break;
625		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
626		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
627		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
628		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
629		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
630		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
631		case CPUINFO_INT_MIN_CYCLES: info->i = 3; break;
632		case CPUINFO_INT_MAX_CYCLES: info->i = 4; break;
633
634		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
635		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
636		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
637		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
638		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
639		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
640		case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
641		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
642		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
643
644		/* interrupt lines/exceptions */
645		case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: info->i = arm->pendingIrq; break;
646		case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: info->i = arm->pendingFiq; break;
647		case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: info->i = arm->pendingAbtD; break;
648		case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: info->i = arm->pendingAbtP; break;
649		case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: info->i = arm->pendingUnd; break;
650
651		/* registers shared by all operating modes */
652		case CPUINFO_INT_REGISTER + ARM7_R0: info->i = ARM7REG( 0); break;
653		case CPUINFO_INT_REGISTER + ARM7_R1: info->i = ARM7REG( 1); break;
654		case CPUINFO_INT_REGISTER + ARM7_R2: info->i = ARM7REG( 2); break;
655		case CPUINFO_INT_REGISTER + ARM7_R3: info->i = ARM7REG( 3); break;
656		case CPUINFO_INT_REGISTER + ARM7_R4: info->i = ARM7REG( 4); break;
657		case CPUINFO_INT_REGISTER + ARM7_R5: info->i = ARM7REG( 5); break;
658		case CPUINFO_INT_REGISTER + ARM7_R6: info->i = ARM7REG( 6); break;
659		case CPUINFO_INT_REGISTER + ARM7_R7: info->i = ARM7REG( 7); break;
660		case CPUINFO_INT_REGISTER + ARM7_R8: info->i = ARM7REG( 8); break;
661		case CPUINFO_INT_REGISTER + ARM7_R9: info->i = ARM7REG( 9); break;
662		case CPUINFO_INT_REGISTER + ARM7_R10: info->i = ARM7REG(10); break;
663		case CPUINFO_INT_REGISTER + ARM7_R11: info->i = ARM7REG(11); break;
664		case CPUINFO_INT_REGISTER + ARM7_R12: info->i = ARM7REG(12); break;
665		case CPUINFO_INT_REGISTER + ARM7_R13: info->i = ARM7REG(13); break;
666		case CPUINFO_INT_REGISTER + ARM7_R14: info->i = ARM7REG(14); break;
667		case CPUINFO_INT_REGISTER + ARM7_R15: info->i = ARM7REG(15); break;
668
669		case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* not implemented */ break;
670		case CPUINFO_INT_PC:
671		case CPUINFO_INT_REGISTER + ARM7_PC: info->i = GET_PC; break;
672		case CPUINFO_INT_SP: info->i = GetRegister(arm, 13); break;
673
674		/* FIRQ Mode Shadowed Registers */
675		case CPUINFO_INT_REGISTER + ARM7_FR8: info->i = ARM7REG(eR8_FIQ); break;
676		case CPUINFO_INT_REGISTER + ARM7_FR9: info->i = ARM7REG(eR9_FIQ); break;
677		case CPUINFO_INT_REGISTER + ARM7_FR10: info->i = ARM7REG(eR10_FIQ); break;
678		case CPUINFO_INT_REGISTER + ARM7_FR11: info->i = ARM7REG(eR11_FIQ); break;
679		case CPUINFO_INT_REGISTER + ARM7_FR12: info->i = ARM7REG(eR12_FIQ); break;
680		case CPUINFO_INT_REGISTER + ARM7_FR13: info->i = ARM7REG(eR13_FIQ); break;
681		case CPUINFO_INT_REGISTER + ARM7_FR14: info->i = ARM7REG(eR14_FIQ); break;
682		case CPUINFO_INT_REGISTER + ARM7_FSPSR: info->i = ARM7REG(eSPSR_FIQ); break;
683
684		/* IRQ Mode Shadowed Registers */
685		case CPUINFO_INT_REGISTER + ARM7_IR13: info->i = ARM7REG(eR13_IRQ); break;
686		case CPUINFO_INT_REGISTER + ARM7_IR14: info->i = ARM7REG(eR14_IRQ); break;
687		case CPUINFO_INT_REGISTER + ARM7_ISPSR: info->i = ARM7REG(eSPSR_IRQ); break;
688
689		/* Supervisor Mode Shadowed Registers */
690		case CPUINFO_INT_REGISTER + ARM7_SR13: info->i = ARM7REG(eR13_SVC); break;
691		case CPUINFO_INT_REGISTER + ARM7_SR14: info->i = ARM7REG(eR14_SVC); break;
692		case CPUINFO_INT_REGISTER + ARM7_SSPSR: info->i = ARM7REG(eSPSR_SVC); break;
693
694		/* Abort Mode Shadowed Registers */
695		case CPUINFO_INT_REGISTER + ARM7_AR13: info->i = ARM7REG(eR13_ABT); break;
696		case CPUINFO_INT_REGISTER + ARM7_AR14: info->i = ARM7REG(eR14_ABT); break;
697		case CPUINFO_INT_REGISTER + ARM7_ASPSR: info->i = ARM7REG(eSPSR_ABT); break;
698
699		/* Undefined Mode Shadowed Registers */
700		case CPUINFO_INT_REGISTER + ARM7_UR13: info->i = ARM7REG(eR13_UND); break;
701		case CPUINFO_INT_REGISTER + ARM7_UR14: info->i = ARM7REG(eR14_UND); break;
702		case CPUINFO_INT_REGISTER + ARM7_USPSR: info->i = ARM7REG(eSPSR_UND); break;
703
704		/* --- the following bits of info are returned as pointers to data or functions --- */
705		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(arm7); break;
706		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(arm7); break;
707		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm7); break;
708		case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(arm7); break;
709		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(arm7); break;
710		case CPUINFO_FCT_BURN: info->burn = NULL; break;
711		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(arm7); break;
712		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &ARM7_ICOUNT; break;
713		case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(arm7); break;
714
715		/* --- the following bits of info are returned as NULL-terminated strings --- */
716		case CPUINFO_STR_NAME: strcpy(info->s, "ARM7"); break;
717		case CPUINFO_STR_FAMILY: strcpy(info->s, "Acorn Risc Machine"); break;
718		case CPUINFO_STR_VERSION: strcpy(info->s, "2.0"); break;
719		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
720		case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Steve Ellenoff, sellenoff@hotmail.com"); break;
721
722		case CPUINFO_STR_FLAGS:
723		sprintf(info->s, "%c%c%c%c%c%c%c%c %s",
724		(ARM7REG(eCPSR) & N_MASK) ? 'N' : '-',
725		(ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-',
726		(ARM7REG(eCPSR) & C_MASK) ? 'C' : '-',
727		(ARM7REG(eCPSR) & V_MASK) ? 'V' : '-',
728		(ARM7REG(eCPSR) & Q_MASK) ? 'Q' : '-',
729		(ARM7REG(eCPSR) & I_MASK) ? 'I' : '-',
730		(ARM7REG(eCPSR) & F_MASK) ? 'F' : '-',
731		(ARM7REG(eCPSR) & T_MASK) ? 'T' : '-',
732		GetModeText(ARM7REG(eCPSR)));
733		break;
734
735		/* registers shared by all operating modes */
736		case CPUINFO_STR_REGISTER + ARM7_PC: sprintf(info->s, "PC :%08x", GET_PC); break;
737		case CPUINFO_STR_REGISTER + ARM7_R0: sprintf(info->s, "R0 :%08x", ARM7REG( 0)); break;
738		case CPUINFO_STR_REGISTER + ARM7_R1: sprintf(info->s, "R1 :%08x", ARM7REG( 1)); break;
739		case CPUINFO_STR_REGISTER + ARM7_R2: sprintf(info->s, "R2 :%08x", ARM7REG( 2)); break;
740		case CPUINFO_STR_REGISTER + ARM7_R3: sprintf(info->s, "R3 :%08x", ARM7REG( 3)); break;
741		case CPUINFO_STR_REGISTER + ARM7_R4: sprintf(info->s, "R4 :%08x", ARM7REG( 4)); break;
742		case CPUINFO_STR_REGISTER + ARM7_R5: sprintf(info->s, "R5 :%08x", ARM7REG( 5)); break;
743		case CPUINFO_STR_REGISTER + ARM7_R6: sprintf(info->s, "R6 :%08x", ARM7REG( 6)); break;
744		case CPUINFO_STR_REGISTER + ARM7_R7: sprintf(info->s, "R7 :%08x", ARM7REG( 7)); break;
745		case CPUINFO_STR_REGISTER + ARM7_R8: sprintf(info->s, "R8 :%08x", ARM7REG( 8)); break;
746		case CPUINFO_STR_REGISTER + ARM7_R9: sprintf(info->s, "R9 :%08x", ARM7REG( 9)); break;
747		case CPUINFO_STR_REGISTER + ARM7_R10: sprintf(info->s, "R10 :%08x", ARM7REG(10)); break;
748		case CPUINFO_STR_REGISTER + ARM7_R11: sprintf(info->s, "R11 :%08x", ARM7REG(11)); break;
749		case CPUINFO_STR_REGISTER + ARM7_R12: sprintf(info->s, "R12 :%08x", ARM7REG(12)); break;
750		case CPUINFO_STR_REGISTER + ARM7_R13: sprintf(info->s, "R13 :%08x", ARM7REG(13)); break;
751		case CPUINFO_STR_REGISTER + ARM7_R14: sprintf(info->s, "R14 :%08x", ARM7REG(14)); break;
752		case CPUINFO_STR_REGISTER + ARM7_R15: sprintf(info->s, "R15 :%08x", ARM7REG(15)); break;
753
754		/* FIRQ Mode Shadowed Registers */
755		case CPUINFO_STR_REGISTER + ARM7_FR8: sprintf(info->s, "FR8 :%08x", ARM7REG(eR8_FIQ) ); break;
756		case CPUINFO_STR_REGISTER + ARM7_FR9: sprintf(info->s, "FR9 :%08x", ARM7REG(eR9_FIQ) ); break;
757		case CPUINFO_STR_REGISTER + ARM7_FR10: sprintf(info->s, "FR10:%08x", ARM7REG(eR10_FIQ) ); break;
758		case CPUINFO_STR_REGISTER + ARM7_FR11: sprintf(info->s, "FR11:%08x", ARM7REG(eR11_FIQ) ); break;
759		case CPUINFO_STR_REGISTER + ARM7_FR12: sprintf(info->s, "FR12:%08x", ARM7REG(eR12_FIQ) ); break;
760		case CPUINFO_STR_REGISTER + ARM7_FR13: sprintf(info->s, "FR13:%08x", ARM7REG(eR13_FIQ) ); break;
761		case CPUINFO_STR_REGISTER + ARM7_FR14: sprintf(info->s, "FR14:%08x", ARM7REG(eR14_FIQ) ); break;
762		case CPUINFO_STR_REGISTER + ARM7_FSPSR: sprintf(info->s, "FR16:%08x", ARM7REG(eSPSR_FIQ)); break;
763
764		/* IRQ Mode Shadowed Registers */
765		case CPUINFO_STR_REGISTER + ARM7_IR13: sprintf(info->s, "IR13:%08x", ARM7REG(eR13_IRQ) ); break;
766		case CPUINFO_STR_REGISTER + ARM7_IR14: sprintf(info->s, "IR14:%08x", ARM7REG(eR14_IRQ) ); break;
767		case CPUINFO_STR_REGISTER + ARM7_ISPSR: sprintf(info->s, "IR16:%08x", ARM7REG(eSPSR_IRQ)); break;
768
769		/* Supervisor Mode Shadowed Registers */
770		case CPUINFO_STR_REGISTER + ARM7_SR13: sprintf(info->s, "SR13:%08x", ARM7REG(eR13_SVC) ); break;
771		case CPUINFO_STR_REGISTER + ARM7_SR14: sprintf(info->s, "SR14:%08x", ARM7REG(eR14_SVC) ); break;
772		case CPUINFO_STR_REGISTER + ARM7_SSPSR: sprintf(info->s, "SR16:%08x", ARM7REG(eSPSR_SVC)); break;
773
774		/* Abort Mode Shadowed Registers */
775		case CPUINFO_STR_REGISTER + ARM7_AR13: sprintf(info->s, "AR13:%08x", ARM7REG(eR13_ABT) ); break;
776		case CPUINFO_STR_REGISTER + ARM7_AR14: sprintf(info->s, "AR14:%08x", ARM7REG(eR14_ABT) ); break;
777		case CPUINFO_STR_REGISTER + ARM7_ASPSR: sprintf(info->s, "AR16:%08x", ARM7REG(eSPSR_ABT)); break;
778
779		/* Undefined Mode Shadowed Registers */
780		case CPUINFO_STR_REGISTER + ARM7_UR13: sprintf(info->s, "UR13:%08x", ARM7REG(eR13_UND) ); break;
781		case CPUINFO_STR_REGISTER + ARM7_UR14: sprintf(info->s, "UR14:%08x", ARM7REG(eR14_UND) ); break;
782		case CPUINFO_STR_REGISTER + ARM7_USPSR: sprintf(info->s, "UR16:%08x", ARM7REG(eSPSR_UND)); break;
783		}
784		}
785
786		CPU_GET_INFO( arm7_be )
787		{
788		switch (state)
789		{
790		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
791		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm7_be); break;
792		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(arm7_be); break;
793		case CPUINFO_STR_NAME: strcpy(info->s, "ARM7 (big endian)"); break;
794		default: CPU_GET_INFO_CALL(arm7);
795		}
796		}
797
798		CPU_GET_INFO( arm7500 )
799		{
800		switch (state)
801		{
802		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm7500); break;
803		case CPUINFO_STR_NAME: strcpy(info->s, "ARM7500"); break;
804		default: CPU_GET_INFO_CALL(arm7);
805		break;
806		}
807		}
808
809		CPU_GET_INFO( arm9 )
810		{
811		switch (state)
812		{
813		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm9); break;
814		case CPUINFO_STR_NAME: strcpy(info->s, "ARM9"); break;
815		default: CPU_GET_INFO_CALL(arm7);
816		break;
817		}
818		}
819
820		CPU_GET_INFO( arm920t )
821		{
822		switch (state)
823		{
824		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm920t); break;
825		case CPUINFO_STR_NAME: strcpy(info->s, "ARM920T"); break;
826		default: CPU_GET_INFO_CALL(arm7);
827		break;
828		}
829		}
830
831		CPU_GET_INFO( pxa255 )
832		{
833		switch (state)
834		{
835		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(pxa255); break;
836		case CPUINFO_STR_NAME: strcpy(info->s, "PXA255"); break;
837		default: CPU_GET_INFO_CALL(arm7);
838		break;
839		}
840		}
841
842		CPU_GET_INFO( sa1110 )
843		{
844		switch (state)
845		{
846		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sa1110); break;
847		case CPUINFO_STR_NAME: strcpy(info->s, "SA1110"); break;
848		default: CPU_GET_INFO_CALL(arm7);
849		break;
850		}
851		}
852
853
854		/* ARM system coprocessor support */
855		static WRITE32_DEVICE_HANDLER( arm7_do_callback )
856		{
857		arm_state *arm = get_safe_token(device);
858		arm->pendingUnd = 1;
859		}
860
861		static READ32_DEVICE_HANDLER( arm7_rt_r_callback )
862		{
863		arm_state *arm = get_safe_token(device);
864		UINT32 opcode = offset;
865		UINT8 cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
866		UINT8 op2 = ( opcode & INSN_COPRO_OP2 ) >> INSN_COPRO_OP2_SHIFT;
867		UINT8 op3 = opcode & INSN_COPRO_OP3;
868		UINT8 cpnum = (opcode & INSN_COPRO_CPNUM) >> INSN_COPRO_CPNUM_SHIFT;
869		UINT32 data = 0;
870
871		// printf("cpnum %d cReg %d op2 %d op3 %d (%x)\n", cpnum, cReg, op2, op3, GET_REGISTER(arm, 15));
872
873		// we only handle system copro here
874		if (cpnum != 15)
875		{
876		if (arm->archFlags & eARM_ARCHFLAGS_XSCALE)
877		{
878		// handle XScale specific CP14
879		if (cpnum == 14)
880		{
881		switch( cReg )
882		{
883		case 1: // clock counter
884		data = (UINT32)arm->device->total_cycles();
885		break;
886
887		default:
888		break;
889		}
890		}
891		else
892		{
893		fatalerror("XScale: Unhandled coprocessor %d (archFlags %x)\n", cpnum, arm->archFlags);
894		}
895
896		return data;
897		}
898		else
899		{
900		LOG( ("ARM7: Unhandled coprocessor %d (archFlags %x)\n", cpnum, arm->archFlags) );
901		arm->pendingUnd = 1;
902		return 0;
903		}
904		}
905
906		switch( cReg )
907		{
908		case 4:
909		case 7:
910		case 8:
911		case 9:
912		case 10:
913		case 11:
914		case 12:
915		// RESERVED
916		LOG( ( "arm7_rt_r_callback CR%d, RESERVED\n", cReg ) );
917		break;
918		case 0: // ID
919		switch(op2)
920		{
921		case 0:
922		switch (arm->archRev)
923		{
924		case 3: // ARM6 32-bit
925		data = 0x41;
926		break;
927
928		case 4: // ARM7/SA11xx
929		if (arm->archFlags & eARM_ARCHFLAGS_SA)
930		{
931		// ARM Architecture Version 4
932		// Part Number 0xB11 (SA1110)
933		// Stepping B5
934		data = 0x69 \| ( 0x01 << 16 ) \| ( 0xB11 << 4 ) \| 0x9;
935		}
936		else
937		{
938		if (device->type() == ARM920T)
939		{
940		data = (0x41 << 24) \| (1 << 20) \| (2 << 16) \| (0x920 << 4) \| (0 << 0); // ARM920T (S3C24xx)
941		}
942		else if (device->type() == ARM7500)
943		{
944		data = (0x41 << 24) \| (0 << 20) \| (1 << 16) \| (0x710 << 4) \| (0 << 0); // ARM7500
945		}
946		else
947		{
948		data = 0x41 \| (1 << 23) \| (7 << 12); // <-- where did this come from?
949		}
950		}
951		break;
952
953		case 5: // ARM9/10/XScale
954		data = 0x41 \| (9 << 12);
955		if (arm->archFlags & eARM_ARCHFLAGS_T)
956		{
957		if (arm->archFlags & eARM_ARCHFLAGS_E)
958		{
959		if (arm->archFlags & eARM_ARCHFLAGS_J)
960		{
961		data \|= (6<<16); // v5TEJ
962		}
963		else
964		{
965		data \|= (5<<16); // v5TE
966		}
967		}
968		else
969		{
970		data \|= (4<<16); // v5T
971		}
972		}
973		break;
974
975		case 6: // ARM11
976		data = 0x41 \| (10<< 12) \| (7<<16); // v6
977		break;
978		}
979		break;
980		case 1: // cache type
981		data = 0x0f0d2112; // HACK: value expected by ARMWrestler (probably Nintendo DS ARM9's value)
982		//data = (6 << 25) \| (1 << 24) \| (0x172 << 12) \| (0x172 << 0); // ARM920T (S3C24xx)
983		break;
984		case 2: // TCM type
985		data = 0;
986		break;
987		case 3: // TLB type
988		data = 0;
989		break;
990		case 4: // MPU type
991		data = 0;
992		break;
993		}
994		LOG( ( "arm7_rt_r_callback, ID\n" ) );
995		break;
996		case 1: // Control
997		data = COPRO_CTRL \| 0x70; // bits 4-6 always read back as "1" (bit 3 too in XScale)
998		break;
999		case 2: // Translation Table Base
1000		data = COPRO_TLB_BASE;
1001		break;
1002		case 3: // Domain Access Control
1003		LOG( ( "arm7_rt_r_callback, Domain Access Control\n" ) );
1004		data = COPRO_DOMAIN_ACCESS_CONTROL;
1005		break;
1006		case 5: // Fault Status
1007		LOG( ( "arm7_rt_r_callback, Fault Status\n" ) );
1008		switch (op3)
1009		{
1010		case 0: data = COPRO_FAULT_STATUS_D; break;
1011		case 1: data = COPRO_FAULT_STATUS_P; break;
1012		}
1013		break;
1014		case 6: // Fault Address
1015		LOG( ( "arm7_rt_r_callback, Fault Address\n" ) );
1016		data = COPRO_FAULT_ADDRESS;
1017		break;
1018		case 13: // Read Process ID (PID)
1019		LOG( ( "arm7_rt_r_callback, Read PID\n" ) );
1020		data = COPRO_FCSE_PID;
1021		break;
1022		case 14: // Read Breakpoint
1023		LOG( ( "arm7_rt_r_callback, Read Breakpoint\n" ) );
1024		break;
1025		case 15: // Test, Clock, Idle
1026		LOG( ( "arm7_rt_r_callback, Test / Clock / Idle \n" ) );
1027		break;
1028		}
1029
1030		return data;
1031		}
1032
1033		static WRITE32_DEVICE_HANDLER( arm7_rt_w_callback )
1034		{
1035		arm_state *arm = get_safe_token(device);
1036		UINT32 opcode = offset;
1037		UINT8 cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
1038		UINT8 op2 = ( opcode & INSN_COPRO_OP2 ) >> INSN_COPRO_OP2_SHIFT;
1039		UINT8 op3 = opcode & INSN_COPRO_OP3;
1040		UINT8 cpnum = (opcode & INSN_COPRO_CPNUM) >> INSN_COPRO_CPNUM_SHIFT;
1041
1042		// handle XScale specific CP14 - just eat writes for now
1043		if (cpnum != 15)
1044		{
1045		if (cpnum == 14)
1046		{
1047		LOG( ("arm7_rt_w_callback: write %x to XScale CP14 reg %d\n", data, cReg) );
1048		return;
1049		}
1050		else
1051		{
1052		LOG( ("ARM7: Unhandled coprocessor %d\n", cpnum) );
1053		arm->pendingUnd = 1;
1054		return;
1055		}
1056		}
1057
1058		switch( cReg )
1059		{
1060		case 0:
1061		case 4:
1062		case 10:
1063		case 11:
1064		case 12:
1065		// RESERVED
1066		LOG( ( "arm7_rt_w_callback CR%d, RESERVED = %08x\n", cReg, data) );
1067		break;
1068		case 1: // Control
1069		LOG( ( "arm7_rt_w_callback Control = %08x (%d) (%d)\n", data, op2, op3 ) );
1070		LOG( ( " MMU:%d, Address Fault:%d, Data Cache:%d, Write Buffer:%d\n",
1071		data & COPRO_CTRL_MMU_EN, ( data & COPRO_CTRL_ADDRFAULT_EN ) >> COPRO_CTRL_ADDRFAULT_EN_SHIFT,
1072		( data & COPRO_CTRL_DCACHE_EN ) >> COPRO_CTRL_DCACHE_EN_SHIFT,
1073		( data & COPRO_CTRL_WRITEBUF_EN ) >> COPRO_CTRL_WRITEBUF_EN_SHIFT ) );
1074		LOG( ( " Endianness:%d, System:%d, ROM:%d, Instruction Cache:%d\n",
1075		( data & COPRO_CTRL_ENDIAN ) >> COPRO_CTRL_ENDIAN_SHIFT,
1076		( data & COPRO_CTRL_SYSTEM ) >> COPRO_CTRL_SYSTEM_SHIFT,
1077		( data & COPRO_CTRL_ROM ) >> COPRO_CTRL_ROM_SHIFT,
1078		( data & COPRO_CTRL_ICACHE_EN ) >> COPRO_CTRL_ICACHE_EN_SHIFT ) );
1079		LOG( ( " Int Vector Adjust:%d\n", ( data & COPRO_CTRL_INTVEC_ADJUST ) >> COPRO_CTRL_INTVEC_ADJUST_SHIFT ) );
1080		#if ARM7_MMU_ENABLE_HACK
1081		if (((data & COPRO_CTRL_MMU_EN) != 0) && ((COPRO_CTRL & COPRO_CTRL_MMU_EN) == 0))
1082		{
1083		arm->mmu_enable_addr = R15;
1084		}
1085		if (((data & COPRO_CTRL_MMU_EN) == 0) && ((COPRO_CTRL & COPRO_CTRL_MMU_EN) != 0))
1086		{
1087		if (!arm7_tlb_translate( arm, &R15, 0))
1088		{
1089		fatalerror("ARM7_MMU_ENABLE_HACK translate failed\n");
1090		}
1091		}
1092		#endif
1093		COPRO_CTRL = data & COPRO_CTRL_MASK;
1094		break;
1095		case 2: // Translation Table Base
1096		LOG( ( "arm7_rt_w_callback TLB Base = %08x (%d) (%d)\n", data, op2, op3 ) );
1097		COPRO_TLB_BASE = data;
1098		break;
1099		case 3: // Domain Access Control
1100		LOG( ( "arm7_rt_w_callback Domain Access Control = %08x (%d) (%d)\n", data, op2, op3 ) );
1101		COPRO_DOMAIN_ACCESS_CONTROL = data;
1102		break;
1103		case 5: // Fault Status
1104		LOG( ( "arm7_rt_w_callback Fault Status = %08x (%d) (%d)\n", data, op2, op3 ) );
1105		switch (op3)
1106		{
1107		case 0: COPRO_FAULT_STATUS_D = data; break;
1108		case 1: COPRO_FAULT_STATUS_P = data; break;
1109		}
1110		break;
1111		case 6: // Fault Address
1112		LOG( ( "arm7_rt_w_callback Fault Address = %08x (%d) (%d)\n", data, op2, op3 ) );
1113		COPRO_FAULT_ADDRESS = data;
1114		break;
1115		case 7: // Cache Operations
1116		// LOG( ( "arm7_rt_w_callback Cache Ops = %08x (%d) (%d)\n", data, op2, op3 ) );
1117		break;
1118		case 8: // TLB Operations
1119		LOG( ( "arm7_rt_w_callback TLB Ops = %08x (%d) (%d)\n", data, op2, op3 ) );
1120		break;
1121		case 9: // Read Buffer Operations
1122		LOG( ( "arm7_rt_w_callback Read Buffer Ops = %08x (%d) (%d)\n", data, op2, op3 ) );
1123		break;
1124		case 13: // Write Process ID (PID)
1125		LOG( ( "arm7_rt_w_callback Write PID = %08x (%d) (%d)\n", data, op2, op3 ) );
1126		COPRO_FCSE_PID = data;
1127		break;
1128		case 14: // Write Breakpoint
1129		LOG( ( "arm7_rt_w_callback Write Breakpoint = %08x (%d) (%d)\n", data, op2, op3 ) );
1130		break;
1131		case 15: // Test, Clock, Idle
1132		LOG( ( "arm7_rt_w_callback Test / Clock / Idle = %08x (%d) (%d)\n", data, op2, op3 ) );
1133		break;
1134		}
1135		}
1136
1137		void arm7_dt_r_callback(arm_state arm, UINT32 insn, UINT32 prn, UINT32 (read32)(arm_state arm, UINT32 addr))
1138		{
1139		UINT8 cpn = (insn >> 8) & 0xF;
1140		if ((arm->archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
1141		{
1142		LOG( ( "arm7_dt_r_callback: DSP Coprocessor 0 (CP0) not yet emulated (PC %08x)\n", GET_PC ) );
1143		}
1144		else
1145		{
1146		arm->pendingUnd = 1;
1147		}
1148		}
1149
1150		void arm7_dt_w_callback(arm_state arm, UINT32 insn, UINT32 prn, void (write32)(arm_state arm, UINT32 addr, UINT32 data))
1151		{
1152		UINT8 cpn = (insn >> 8) & 0xF;
1153		if ((arm->archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
1154		{
1155		LOG( ( "arm7_dt_w_callback: DSP Coprocessor 0 (CP0) not yet emulated (PC %08x)\n", GET_PC ) );
1156		}
1157		else
1158		{
1159		arm->pendingUnd = 1;
1160		}
1161		}
1162
1163
1164		/*-------------------------------------------------
1165	261	arm7drc_set_options - configure DRC options
1166	262	-------------------------------------------------*/
1167	263
1168		void arm7drc_set_options(~~device_t *device,~~ UINT32 options)
	264	void arm7_cpu_device::arm7drc_set_options(UINT32 options)
1169	265	{
1170		arm_state *arm = get_safe_token(device);
1171		arm->impstate->drcoptions = options;
	266	m_impstate.drcoptions = options;
1172	267	}
1173	268
1174	269
r24074	r24075
1177	272	region
1178	273	-------------------------------------------------*/
1179	274
1180		void arm7drc_add_fastram(~~device_t device,~~ offs_t start, offs_t end, UINT8 readonly, void base)
	275	void arm7_cpu_device::arm7drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base)
1181	276	{
1182		arm_state *arm = get_safe_token(device);
1183		if (arm->impstate->fastram_select < ARRAY_LENGTH(arm->impstate->fastram))
	277	if (m_impstate.fastram_select < ARRAY_LENGTH(m_impstate.fastram))
1184	278	{
1185		arm->impstate->fastram[arm->impstate->fastram_select].start = start;
1186		arm->impstate->fastram[arm->impstate->fastram_select].end = end;
1187		arm->impstate->fastram[arm->impstate->fastram_select].readonly = readonly;
1188		arm->impstate->fastram[arm->impstate->fastram_select].base = base;
1189		arm->impstate->fastram_select++;
	279	m_impstate.fastram[m_impstate.fastram_select].start = start;
	280	m_impstate.fastram[m_impstate.fastram_select].end = end;
	281	m_impstate.fastram[m_impstate.fastram_select].readonly = readonly;
	282	m_impstate.fastram[m_impstate.fastram_select].base = base;
	283	m_impstate.fastram_select++;
1190	284	}
1191	285	}
1192	286
r24074	r24075
1195	289	arm7drc_add_hotspot - add a new hotspot
1196	290	-------------------------------------------------*/
1197	291
1198		void arm7drc_add_hotspot(~~device_t *device,~~ offs_t pc, UINT32 opcode, UINT32 cycles)
	292	void arm7_cpu_device::arm7drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles)
1199	293	{
1200		arm_state *arm = get_safe_token(device);
1201		if (arm->impstate->hotspot_select < ARRAY_LENGTH(arm->impstate->hotspot))
	294	if (m_impstate.hotspot_select < ARRAY_LENGTH(m_impstate.hotspot))
1202	295	{
1203		arm->impstate->hotspot[arm->impstate->hotspot_select].pc = pc;
1204		arm->impstate->hotspot[arm->impstate->hotspot_select].opcode = opcode;
1205		arm->impstate->hotspot[arm->impstate->hotspot_select].cycles = cycles;
1206		arm->impstate->hotspot_select++;
	296	m_impstate.hotspot[m_impstate.hotspot_select].pc = pc;
	297	m_impstate.hotspot[m_impstate.hotspot_select].opcode = opcode;
	298	m_impstate.hotspot[m_impstate.hotspot_select].cycles = cycles;
	299	m_impstate.hotspot_select++;
1207	300	}
1208	301	}
1209	302
r24074	r24075
1218	311	regenerate static code
1219	312	-------------------------------------------------*/
1220	313
1221		~~static~~ void code_flush_cache(~~arm_state *arm~~)
	314	void arm7_cpu_device::code_flush_cache()
1222	315	{
1223		int mode;
1224
1225	316	/* empty the transient cache contents */
1226		arm->impstate->drcuml->reset();
	317	m_impstate.drcuml->reset();
1227	318
1228	319	try
1229	320	{
1230	321	/* generate the entry point and out-of-cycles handlers */
1231		static_generate_entry_point(arm);
1232		static_generate_nocode_handler(arm);
1233		static_generate_out_of_cycles(arm);
1234		static_generate_tlb_translate(arm);
1235		static_generate_detect_fault(arm);
1236		//static_generate_tlb_mismatch(arm);
	322	static_generate_entry_point();
	323	static_generate_nocode_handler();
	324	static_generate_out_of_cycles();
	325	static_generate_tlb_translate(NULL); // TODO FIXME
	326	static_generate_detect_fault(NULL); // TODO FIXME
	327	//static_generate_tlb_mismatch();
1237	328
1238	329	/* add subroutines for memory accesses */
1239		static_generate_memory_accessor(arm, mode, 1, FALSE, FALSE, "read8", &arm->impstate->read8);
1240		static_generate_memory_accessor(arm, mode, 1, TRUE, FALSE, "write8", &arm->impstate->write8);
1241		static_generate_memory_accessor(arm, mode, 2, FALSE, FALSE, "read16", &arm->impstate->read16);
1242		static_generate_memory_accessor(arm, mode, 2, TRUE, FALSE, "write16", &arm->impstate->write16);
1243		static_generate_memory_accessor(arm, mode, 4, FALSE, FALSE, "read32", &arm->impstate->read32);
1244		static_generate_memory_accessor(arm, mode, 4, TRUE, FALSE, "write32", &arm->impstate->write32);
	330	static_generate_memory_accessor(1, FALSE, FALSE, "read8", &m_impstate.read8);
	331	static_generate_memory_accessor(1, TRUE, FALSE, "write8", &m_impstate.write8);
	332	static_generate_memory_accessor(2, FALSE, FALSE, "read16", &m_impstate.read16);
	333	static_generate_memory_accessor(2, TRUE, FALSE, "write16", &m_impstate.write16);
	334	static_generate_memory_accessor(4, FALSE, FALSE, "read32", &m_impstate.read32);
	335	static_generate_memory_accessor(4, TRUE, FALSE, "write32", &m_impstate.write32);
1245	336	}
1246	337	catch (drcuml_block::abort_compilation &)
1247	338	{
r24074	r24075
1255	346	given mode at the specified pc
1256	347	-------------------------------------------------*/
1257	348
1258		~~static~~ void code_compile_block(~~arm_state *arm,~~ UINT8 mode, offs_t pc)
	349	void arm7_cpu_device::code_compile_block(UINT8 mode, offs_t pc)
1259	350	{
1260		drcuml_state *drcuml = arm->impstate->drcuml;
	351	drcuml_state *drcuml = m_impstate.drcuml;
1261	352	compiler_state compiler = { 0 };
1262	353	const opcode_desc *seqlast;
1263	354	int override = FALSE;
r24074	r24075
1265	356	g_profiler.start(PROFILER_DRC_COMPILE);
1266	357
1267	358	/* get a description of this sequence */
1268		const opcode_desc *desclist = arm->impstate->drcfe->describe_code(pc);
1269		if (LOG_UML \|\| LOG_NATIVE)
1270		log_opcode_desc(drcuml, desclist, 0);
	359	// TODO FIXME
	360	const opcode_desc *desclist = NULL; //m_impstate.drcfe->describe_code(pc); // TODO
	361	// if (LOG_UML \|\| LOG_NATIVE)
	362	// log_opcode_desc(drcuml, desclist, 0);
1271	363
1272	364	/* if we get an error back, flush the cache and try again */
1273	365	bool succeeded = false;
r24074	r24075
1310	402	else
1311	403	{
1312	404	UML_LABEL(block, seqhead->pc \| 0x80000000); // label seqhead->pc \| 0x80000000
1313		UML_HASHJMP(block, 0, seqhead->pc, *arm->impstate->nocode);
	405	UML_HASHJMP(block, 0, seqhead->pc, *m_impstate.nocode);
1314	406	// hashjmp <mode>,seqhead->pc,nocode
1315	407	continue;
1316	408	}
1317	409
1318	410	/* validate this code block if we're not pointing into ROM */
1319		if (arm->program->get_write_ptr(seqhead->physpc) != NULL)
1320		generate_checksum_block(arm, block, &compiler, seqhead, seqlast);
	411	if (m_program->get_write_ptr(seqhead->physpc) != NULL)
	412	generate_checksum_block(block, &compiler, seqhead, seqlast);
1321	413
1322	414	/* label this instruction, if it may be jumped to locally */
1323	415	if (seqhead->flags & OPFLAG_IS_BRANCH_TARGET)
r24074	r24075
1325	417
1326	418	/* iterate over instructions in the sequence and compile them */
1327	419	for (curdesc = seqhead; curdesc != seqlast->next(); curdesc = curdesc->next())
1328		generate_sequence_instruction(~~arm,~~ block, &compiler, curdesc);
	420	generate_sequence_instruction(block, &compiler, curdesc);
1329	421
1330	422	/* if we need to return to the start, do it */
1331	423	if (seqlast->flags & OPFLAG_RETURN_TO_START)
r24074	r24075
1336	428	nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
1337	429
1338	430	/* count off cycles and go there */
1339		generate_update_cycles(~~arm,~~ block, &compiler, nextpc~~, TRUE~~); // <subtract cycles>
	431	generate_update_cycles(block, &compiler, nextpc); // <subtract cycles>
1340	432
1341	433	/* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */
1342	434	/*if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES)
1343		UML_HASHJMP(block, mem(&arm->impstate->mode), nextpc, *arm->impstate->nocode);
	435	UML_HASHJMP(block, uml::mem(&m_impstate.mode), nextpc, *m_impstate.nocode);
1344	436	// hashjmp <mode>,nextpc,nocode
1345	437	else*/ if (seqlast->next() == NULL \|\| seqlast->next()->pc != nextpc)
1346		UML_HASHJMP(block, arm->impstate->mode, nextpc, *arm->impstate->nocode);
	438	UML_HASHJMP(block, m_impstate.mode, nextpc, *m_impstate.nocode);
1347	439	// hashjmp <mode>,nextpc,nocode
1348	440	}
1349	441
r24074	r24075
1354	446	}
1355	447	catch (drcuml_block::abort_compilation &)
1356	448	{
1357		code_flush_cache(~~arm~~);
	449	code_flush_cache();
1358	450	}
1359	451	}
1360	452	}
r24074	r24075
1369	461	of cycles executed so far
1370	462	-------------------------------------------------*/
1371	463
1372		~~static~~ void cfunc_get_cycles(~~void *param~~)
	464	void arm7_cpu_device::cfunc_get_cycles()
1373	465	{
1374		arm_state arm = (arm_state )param;
1375		arm->impstate->numcycles = arm->device->total_cycles();
	466	m_impstate.numcycles = total_cycles();
1376	467	}
1377	468
1378	469
r24074	r24075
1381	472	unimplemented opcdes
1382	473	-------------------------------------------------*/
1383	474
1384		~~static~~ void cfunc_unimplemented(~~void *param~~)
	475	void arm7_cpu_device::cfunc_unimplemented()
1385	476	{
1386		arm_state arm = (arm_state )param;
1387		UINT32 opcode = arm->impstate->arg0;
1388		fatalerror("PC=%08X: Unimplemented op %08X\n", arm->r[eR15], opcode);
	477	UINT32 opcode = m_impstate.arg0;
	478	fatalerror("PC=%08X: Unimplemented op %08X\n", m_r[eR15], opcode);
1389	479	}
1390	480
1391	481
r24074	r24075
1398	488	static entry point
1399	489	-------------------------------------------------*/
1400	490
1401		~~static~~ void static_generate_entry_point(~~arm_state *arm~~)
	491	void arm7_cpu_device::static_generate_entry_point()
1402	492	{
1403		drcuml_state *drcuml = arm->impstate->drcuml;
1404		code_label nodabt;
1405		code_label nofiq;
1406		code_label noirq;
1407		code_label irq32;
1408		code_label nopabd;
1409		code_label nound;
1410		code_label swi32;
1411		code_label irqadjust;
1412		code_label done;
1413		int label = 1;
	493	drcuml_state *drcuml = m_impstate.drcuml;
	494	uml::code_label nodabt;
	495	uml::code_label nofiq;
	496	uml::code_label noirq;
	497	uml::code_label irq32;
	498	uml::code_label nopabd;
	499	uml::code_label nound;
	500	uml::code_label swi32;
	501	uml::code_label irqadjust;
	502	uml::code_label done;
1414	503	drcuml_block *block;
1415	504
1416	505	block = drcuml->begin_block(110);
1417	506
1418	507	/* forward references */
1419		alloc_handle(drcuml, &arm->impstate->exception_norecover[EXCEPTION_INTERRUPT], "interrupt_norecover");
1420		alloc_handle(drcuml, &arm->impstate->nocode, "nocode");
1421		alloc_handle(drcuml, &arm->impstate->detect_fault, "detect_fault");
1422		alloc_handle(drcuml, &arm->impstate->tlb_translate, "tlb_translate");
	508	//alloc_handle(drcuml, &m_impstate.exception_norecover[EXCEPTION_INTERRUPT], "interrupt_norecover");
	509	alloc_handle(drcuml, &m_impstate.nocode, "nocode");
	510	alloc_handle(drcuml, &m_impstate.detect_fault, "detect_fault");
	511	alloc_handle(drcuml, &m_impstate.tlb_translate, "tlb_translate");
1423	512
1424		alloc_handle(drcuml, &arm->impstate->entry, "entry");
1425		UML_HANDLE(block, *arm->impstate->entry); // handle entry
	513	alloc_handle(drcuml, &m_impstate.entry, "entry");
	514	UML_HANDLE(block, *m_impstate.entry); // handle entry
1426	515
1427	516	/* load fast integer registers */
1428		load_fast_iregs(~~arm,~~ block);
	517	load_fast_iregs(block);
1429	518
1430		UML_CALLH(block, *arm->impstate->check_irq);
	519	UML_CALLH(block, *m_impstate.check_irq);
1431	520
1432	521	/* generate a hash jump via the current mode and PC */
1433		UML_HASHJMP(block, 0, mem(&arm->pc), *arm->impstate->nocode); // hashjmp 0,<pc>,nocode
	522	UML_HASHJMP(block, 0, uml::mem(&m_pc), *m_impstate.nocode); // hashjmp 0,<pc>,nocode
1434	523	block->end();
1435	524	}
1436	525
r24074	r24075
1440	529	to check IRQs
1441	530	-------------------------------------------------*/
1442	531
1443		~~static~~ void static_generate_check_irq(~~arm_state *arm~~)
	532	void arm7_cpu_device::static_generate_check_irq()
1444	533	{
1445		drcuml_state *drcuml = arm->impstate->drcuml;
	534	drcuml_state *drcuml = m_impstate.drcuml;
1446	535	drcuml_block *block;
	536	uml::code_label noirq;
1447	537	int nodabt = 0;
1448	538	int nopabt = 0;
1449	539	int irqadjust = 0;
r24074	r24075
1457	547	block = drcuml->begin_block(120);
1458	548
1459	549	/* generate a hash jump via the current mode and PC */
1460		alloc_handle(drcuml, &arm->impstate->check_irq, "check_irq");
1461		UML_HANDLE(block, *arm->impstate->check_irq); // handle check_irq
	550	alloc_handle(drcuml, &m_impstate.check_irq, "check_irq");
	551	UML_HANDLE(block, *m_impstate.check_irq); // handle check_irq
1462	552	/* Exception priorities:
1463	553
1464	554	Reset
r24074	r24075
1470	560	Software Interrupt
1471	561	*/
1472	562
1473		UML_ADD(block, I0, mem(&R15), 4); // add i0, PC, 4 ;insn pc
	563	UML_ADD(block, uml::I0, uml::mem(&R15), 4); // add i0, PC, 4 ;insn pc
1474	564
1475	565	// Data Abort
1476		UML_TEST(block, mem(&arm->pendingAbtD, 1); // test pendingAbtD, 1
1477		UML_JMPc(block, COND_Z, nodabt = label++); // jmpz nodabt
	566	UML_TEST(block, uml::mem(&m_pendingAbtD), 1); // test pendingAbtD, 1
	567	UML_JMPc(block, uml::COND_Z, nodabt = label++); // jmpz nodabt
1478	568
1479		UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_ABT, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_ABT, 0, MODE_FLAG
1480		UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0
1481		UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR
1482		UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
1483		UML_ROLAND(block, mem(&GET_CPSR), mem(&GET_CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
1484		UML_MOV(block, mem(&R15), 0x00000010); // mov PC, 0x10 (Data Abort vector address)
1485		UML_MOV(block, mem(&arm->pendingAbtD, 0); // mov pendingAbtD, 0
	569	UML_ROLINS(block, uml::mem(&GET_CPSR), eARM7_MODE_ABT, 0, MODE_FLAG); // rolins CPSR, eARM7_MODE_ABT, 0, MODE_FLAG
	570	UML_MOV(block, uml::mem(&GET_REGISTER(14)), uml::I0); // mov LR, i0
	571	UML_MOV(block, uml::mem(&GET_REGISTER(SPSR)), uml::mem(&GET_CPSR)); // mov SPSR, CPSR
	572	UML_OR(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
	573	UML_ROLAND(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
	574	UML_MOV(block, uml::mem(&R15), 0x00000010); // mov PC, 0x10 (Data Abort vector address)
	575	UML_MOV(block, uml::mem(&m_pendingAbtD), 0); // mov pendingAbtD, 0
1486	576	UML_JMP(block, irqadjust = label++); // jmp irqadjust
1487	577
1488	578	UML_LABEL(block, nodabt); // nodabt:
1489	579
1490	580	// FIQ
1491		UML_TEST(block, mem(&arm->pendingFiq, 1); // test pendingFiq, 1
1492		UML_JMPc(block, COND_Z, nofiq = label++); // jmpz nofiq
1493		UML_TEST(block, mem(&GET_CPSR), F_MASK); // test CPSR, F_MASK
1494		UML_JMPc(block, COND_Z, nofiq); // jmpz nofiq
	581	UML_TEST(block, uml::mem(&m_pendingFiq), 1); // test pendingFiq, 1
	582	UML_JMPc(block, uml::COND_Z, nofiq = label++); // jmpz nofiq
	583	UML_TEST(block, uml::mem(&GET_CPSR), F_MASK); // test CPSR, F_MASK
	584	UML_JMPc(block, uml::COND_Z, nofiq); // jmpz nofiq
1495	585
1496		UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0
1497		UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR
1498		UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK \| F_MASK); // or CPSR, CPSR, I_MASK \| F_MASK
1499		UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
1500		UML_MOV(block, mem(&R15), 0x0000001c); // mov PC, 0x1c (FIQ vector address)
1501		UML_MOV(block, mem(&arm->pendingFiq, 0); // mov pendingFiq, 0
	586	UML_MOV(block, uml::mem(&GET_REGISTER(14)), uml::I0); // mov LR, i0
	587	UML_MOV(block, uml::mem(&GET_REGISTER(SPSR)), uml::mem(&GET_CPSR)); // mov SPSR, CPSR
	588	UML_OR(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), I_MASK \| F_MASK); // or CPSR, CPSR, I_MASK \| F_MASK
	589	UML_ROLAND(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
	590	UML_MOV(block, uml::mem(&R15), 0x0000001c); // mov PC, 0x1c (FIQ vector address)
	591	UML_MOV(block, uml::mem(&m_pendingFiq), 0); // mov pendingFiq, 0
1502	592	UML_JMP(block, irqadjust); // jmp irqadjust
1503	593
1504	594	UML_LABEL(block, nofiq); // nofiq:
1505	595
1506	596	// IRQ
1507		UML_TEST(block, mem(&arm->pendingIrq, 1); // test pendingIrq, 1
1508		UML_JMPc(block, COND_Z, noirq = label++); // jmpz noirq
1509		UML_TEST(block, mem(&GET_CPSR), I_MASK); // test CPSR, I_MASK
1510		UML_JMPc(block, COND_Z, noirq); // jmpz noirq
	597	UML_TEST(block, uml::mem(&m_pendingIrq), 1); // test pendingIrq, 1
	598	UML_JMPc(block, uml::COND_Z, noirq = label++); // jmpz noirq
	599	UML_TEST(block, uml::mem(&GET_CPSR), I_MASK); // test CPSR, I_MASK
	600	UML_JMPc(block, uml::COND_Z, noirq); // jmpz noirq
1511	601
1512		UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0
1513		UML_TEST(block, mem(&GET_CPSR), SR_MODE32); // test CPSR, MODE32
1514		UML_JMPc(block, COND_NZ, irq32 = label++); // jmpnz irq32
1515		UML_AND(block, I1, I0, 0xf4000000); // and i1, i0, 0xf4000000
1516		UML_OR(block, mem(&R15), I1, 0x0800001a); // or PC, i1, 0x0800001a
1517		UML_AND(block, I1, mem(&GET_CPSR), 0x0fffff3f); // and i1, CPSR, 0x0fffff3f
1518		UML_ROLAND(block, I0, mem(&R15), 32-20, 0x0000000c); // roland i0, R15, 32-20, 0x0000000c
1519		UML_ROLINS(block, I0, mem(&R15), 0, 0xf0000000); // rolins i0, R15, 0, 0xf0000000
1520		UML_OR(block, mem(&GET_CPSR), I0, I1); // or CPSR, i0, i1
	602	UML_MOV(block, uml::mem(&GET_REGISTER(14)), uml::I0); // mov LR, i0
	603	UML_TEST(block, uml::mem(&GET_CPSR), SR_MODE32); // test CPSR, MODE32
	604	UML_JMPc(block, uml::COND_NZ, irq32 = label++); // jmpnz irq32
	605	UML_AND(block, uml::I1, uml::I0, 0xf4000000); // and i1, i0, 0xf4000000
	606	UML_OR(block, uml::mem(&R15), uml::I1, 0x0800001a); // or PC, i1, 0x0800001a
	607	UML_AND(block, uml::I1, uml::mem(&GET_CPSR), 0x0fffff3f); // and i1, CPSR, 0x0fffff3f
	608	UML_ROLAND(block, uml::I0, uml::mem(&R15), 32-20, 0x0000000c); // roland i0, R15, 32-20, 0x0000000c
	609	UML_ROLINS(block, uml::I0, uml::mem(&R15), 0, 0xf0000000); // rolins i0, R15, 0, 0xf0000000
	610	UML_OR(block, uml::mem(&GET_CPSR), uml::I0, uml::I1); // or CPSR, i0, i1
1521	611	UML_JMP(block, irqadjust); // jmp irqadjust
1522	612
1523	613	UML_LABEL(block, irq32); // irq32:
1524		UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR
1525		UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
1526		UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
1527		UML_MOV(block, mem(&R15), 0x00000018); // mov PC, 0x18 (IRQ vector address)
	614	UML_MOV(block, uml::mem(&GET_REGISTER(SPSR)), uml::mem(&GET_CPSR)); // mov SPSR, CPSR
	615	UML_OR(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
	616	UML_ROLAND(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
	617	UML_MOV(block, uml::mem(&R15), 0x00000018); // mov PC, 0x18 (IRQ vector address)
1528	618
1529	619	UML_JMP(block, irqadjust); // jmp irqadjust
1530	620
1531	621	UML_LABEL(block, noirq); // noirq:
1532	622
1533	623	// Prefetch Abort
1534		UML_TEST(block, mem(&arm->pendingAbtP, 1); // test pendingAbtP, 1
1535		UML_JMPc(block, COND_Z, nopabt = label++); // jmpz nopabt
	624	UML_TEST(block, uml::mem(&m_pendingAbtP), 1); // test pendingAbtP, 1
	625	UML_JMPc(block, uml::COND_Z, nopabt = label++); // jmpz nopabt
1536	626
1537		UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_ABT, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_ABT, 0, MODE_FLAG
1538		UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0
1539		UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR
1540		UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
1541		UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
1542		UML_MOV(block, mem(&R15), 0x0000000c); // mov PC, 0x0c (Prefetch Abort vector address)
1543		UML_MOV(block, mem(&arm->pendingAbtP, 0); // mov pendingAbtP, 0
	627	UML_ROLINS(block, uml::mem(&GET_CPSR), eARM7_MODE_ABT, 0, MODE_FLAG); // rolins CPSR, eARM7_MODE_ABT, 0, MODE_FLAG
	628	UML_MOV(block, uml::mem(&GET_REGISTER(14)), uml::I0); // mov LR, i0
	629	UML_MOV(block, uml::mem(&GET_REGISTER(SPSR)), uml::mem(&GET_CPSR)); // mov SPSR, CPSR
	630	UML_OR(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
	631	UML_ROLAND(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
	632	UML_MOV(block, uml::mem(&R15), 0x0000000c); // mov PC, 0x0c (Prefetch Abort vector address)
	633	UML_MOV(block, uml::mem(&m_pendingAbtP), 0); // mov pendingAbtP, 0
1544	634	UML_JMP(block, irqadjust); // jmp irqadjust
1545	635
1546	636	UML_LABEL(block, nopabt); // nopabt:
1547	637
1548	638	// Undefined instruction
1549		UML_TEST(block, mem(&arm->pendingUnd, 1); // test pendingUnd, 1
1550		UML_JMPc(block, COND_Z, nopabt = label++); // jmpz nound
	639	UML_TEST(block, uml::mem(&m_pendingUnd), 1); // test pendingUnd, 1
	640	UML_JMPc(block, uml::COND_Z, nopabt = label++); // jmpz nound
1551	641
1552		UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_UND, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_UND, 0, MODE_FLAG
1553		UML_MOV(block, I1, -4); // mov i1, -4
1554		UML_TEST(block, mem(&GET_CPSR), T_MASK); // test CPSR, T_MASK
1555		UML_MOVc(block, COND_NZ, I1, -2); // movnz i1, -2
1556		UML_ADD(block, mem(&GET_REGISTER(arm, 14)), I0, I1); // add LR, i0, i1
1557		UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR
1558		UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
1559		UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
1560		UML_MOV(block, mem(&R15), 0x00000004); // mov PC, 0x0c (Undefined Insn vector address)
1561		UML_MOV(block, mem(&arm->pendingUnd, 0); // mov pendingUnd, 0
	642	UML_ROLINS(block, uml::mem(&GET_CPSR), eARM7_MODE_UND, 0, MODE_FLAG); // rolins CPSR, eARM7_MODE_UND, 0, MODE_FLAG
	643	UML_MOV(block, uml::I1, -4); // mov i1, -4
	644	UML_TEST(block, uml::mem(&GET_CPSR), T_MASK); // test CPSR, T_MASK
	645	UML_MOVc(block, uml::COND_NZ, uml::I1, -2); // movnz i1, -2
	646	UML_ADD(block, uml::mem(&GET_REGISTER(14)), uml::I0, uml::I1); // add LR, i0, i1
	647	UML_MOV(block, uml::mem(&GET_REGISTER(SPSR)), uml::mem(&GET_CPSR)); // mov SPSR, CPSR
	648	UML_OR(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
	649	UML_ROLAND(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
	650	UML_MOV(block, uml::mem(&R15), 0x00000004); // mov PC, 0x0c (Undefined Insn vector address)
	651	UML_MOV(block, uml::mem(&m_pendingUnd), 0); // mov pendingUnd, 0
1562	652	UML_JMP(block, irqadjust); // jmp irqadjust
1563	653
1564	654	UML_LABEL(block, nopabt); // nopabt:
1565	655
1566	656	// Software Interrupt
1567		UML_TEST(block, mem(&arm->pendingSwi, 1); // test pendingSwi, 1
1568		UML_JMPc(block, COND_Z, done = label++); // jmpz done
	657	UML_TEST(block, uml::mem(&m_pendingSwi), 1); // test pendingSwi, 1
	658	UML_JMPc(block, uml::COND_Z, done = label++); // jmpz done
1569	659
1570		UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_SVC, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_SVC, 0, MODE_FLAG
1571		UML_MOV(block, I1, -4); // mov i1, -4
1572		UML_TEST(block, mem(&GET_CPSR), T_MASK); // test CPSR, T_MASK
1573		UML_MOVc(block, COND_NZ, I1, -2); // movnz i1, -2
1574		UML_ADD(block, mem(&GET_REGISTER(arm, 14)), I0, I1); // add LR, i0, i1
	660	UML_ROLINS(block, uml::mem(&GET_CPSR), eARM7_MODE_SVC, 0, MODE_FLAG); // rolins CPSR, eARM7_MODE_SVC, 0, MODE_FLAG
	661	UML_MOV(block, uml::I1, -4); // mov i1, -4
	662	UML_TEST(block, uml::mem(&GET_CPSR), T_MASK); // test CPSR, T_MASK
	663	UML_MOVc(block, uml::COND_NZ, uml::I1, -2); // movnz i1, -2
	664	UML_ADD(block, uml::mem(&GET_REGISTER(14)), uml::I0, uml::I1); // add LR, i0, i1
1575	665
1576		UML_TEST(block, mem(&GET_CPSR), SR_MODE32); // test CPSR, MODE32
1577		UML_JMPc(block, COND_NZ, swi32 = label++); // jmpnz swi32
1578		UML_AND(block, I1, I0, 0xf4000000); // and i1, i0, 0xf4000000
1579		UML_OR(block, mem(&R15), I1, 0x0800001b); // or PC, i1, 0x0800001b
1580		UML_AND(block, I1, mem(&GET_CPSR), 0x0fffff3f); // and i1, CPSR, 0x0fffff3f
1581		UML_ROLAND(block, I0, mem(&R15), 32-20, 0x0000000c); // roland i0, R15, 32-20, 0x0000000c
1582		UML_ROLINS(block, I0, mem(&R15), 0, 0xf0000000); // rolins i0, R15, 0, 0xf0000000
1583		UML_OR(block, mem(&GET_CPSR), I0, I1); // or CPSR, i0, i1
1584		UML_MOV(block, mem(&arm->pendingSwi, 0); // mov pendingSwi, 0
	666	UML_TEST(block, uml::mem(&GET_CPSR), SR_MODE32); // test CPSR, MODE32
	667	UML_JMPc(block, uml::COND_NZ, swi32 = label++); // jmpnz swi32
	668	UML_AND(block, uml::I1, uml::I0, 0xf4000000); // and i1, i0, 0xf4000000
	669	UML_OR(block, uml::mem(&R15), uml::I1, 0x0800001b); // or PC, i1, 0x0800001b
	670	UML_AND(block, uml::I1, uml::mem(&GET_CPSR), 0x0fffff3f); // and i1, CPSR, 0x0fffff3f
	671	UML_ROLAND(block, uml::I0, uml::mem(&R15), 32-20, 0x0000000c); // roland i0, R15, 32-20, 0x0000000c
	672	UML_ROLINS(block, uml::I0, uml::mem(&R15), 0, 0xf0000000); // rolins i0, R15, 0, 0xf0000000
	673	UML_OR(block, uml::mem(&GET_CPSR), uml::I0, uml::I1); // or CPSR, i0, i1
	674	UML_MOV(block, uml::mem(&m_pendingSwi), 0); // mov pendingSwi, 0
1585	675	UML_JMP(block, irqadjust); // jmp irqadjust
1586	676
1587	677	UML_LABEL(block, swi32); // irq32:
1588		UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR
1589		UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
1590		UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
1591		UML_MOV(block, mem(&R15), 0x00000008); // mov PC, 0x08 (SWI vector address)
1592		UML_MOV(block, mem(&arm->pendingSwi, 0); // mov pendingSwi, 0
	678	UML_MOV(block, uml::mem(&GET_REGISTER(SPSR)), uml::mem(&GET_CPSR)); // mov SPSR, CPSR
	679	UML_OR(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK
	680	UML_ROLAND(block, uml::mem(&GET_CPSR), uml::mem(&GET_CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK
	681	UML_MOV(block, uml::mem(&R15), 0x00000008); // mov PC, 0x08 (SWI vector address)
	682	UML_MOV(block, uml::mem(&m_pendingSwi), 0); // mov pendingSwi, 0
1593	683	UML_JMP(block, irqadjust); // jmp irqadjust
1594	684
1595	685	UML_LABEL(block, irqadjust); // irqadjust:
1596		UML_MOV(block, I1, 0); // mov i1, 0
1597		UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN \| COPRO_CTRL_INTVEC_ADJUST); // test COPRO_CTRL, MMU_EN \| INTVEC_ADJUST
1598		UML_MOVc(block, COND_NZ, I1, 0xffff0000); // movnz i1, 0xffff0000
1599		UML_OR(block, mem(&R15), mem(R15), I1); // or PC, i1
	686	UML_MOV(block, uml::I1, 0); // mov i1, 0
	687	UML_TEST(block, uml::mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN \| COPRO_CTRL_INTVEC_ADJUST); // test COPRO_CTRL, MMU_EN \| INTVEC_ADJUST
	688	UML_MOVc(block, uml::COND_NZ, uml::I1, 0xffff0000); // movnz i1, 0xffff0000
	689	UML_OR(block, uml::mem(&R15), uml::mem(&R15), uml::I1); // or PC, i1
1600	690
1601	691	UML_LABEL(block, done); // done:
1602	692
r24074	r24075
1608	698	exception handler for "out of code"
1609	699	-------------------------------------------------*/
1610	700
1611		~~static~~ void static_generate_nocode_handler(~~arm_state *arm~~)
	701	void arm7_cpu_device::static_generate_nocode_handler()
1612	702	{
1613		drcuml_state *drcuml = arm->impstate->drcuml;
	703	drcuml_state *drcuml = m_impstate.drcuml;
1614	704	drcuml_block *block;
1615	705
1616	706	/* begin generating */
1617	707	block = drcuml->begin_block(10);
1618	708
1619	709	/* generate a hash jump via the current mode and PC */
1620		alloc_handle(drcuml, &arm->impstate->nocode, "nocode");
1621		UML_HANDLE(block, *arm->impstate->nocode); // handle nocode
1622		UML_GETEXP(block, I0); // getexp i0
1623		UML_MOV(block, mem(&R15), I0); // mov [pc],i0
1624		save_fast_iregs(arm, block);
	710	alloc_handle(drcuml, &m_impstate.nocode, "nocode");
	711	UML_HANDLE(block, *m_impstate.nocode); // handle nocode
	712	UML_GETEXP(block, uml::I0); // getexp i0
	713	UML_MOV(block, uml::mem(&R15), uml::I0); // mov [pc],i0
	714	save_fast_iregs(block);
1625	715	UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE
1626	716
1627	717	block->end();
r24074	r24075
1633	723	out of cycles exception handler
1634	724	-------------------------------------------------*/
1635	725
1636		~~static~~ void static_generate_out_of_cycles(~~arm_state *arm~~)
	726	void arm7_cpu_device::static_generate_out_of_cycles()
1637	727	{
1638		drcuml_state *drcuml = arm->impstate->drcuml;
	728	drcuml_state *drcuml = m_impstate.drcuml;
1639	729	drcuml_block *block;
1640	730
1641	731	/* begin generating */
1642	732	block = drcuml->begin_block(10);
1643	733
1644	734	/* generate a hash jump via the current mode and PC */
1645		alloc_handle(drcuml, &arm->impstate->out_of_cycles, "out_of_cycles");
1646		UML_HANDLE(block, *arm->impstate->out_of_cycles); // handle out_of_cycles
1647		UML_GETEXP(block, I0); // getexp i0
1648		UML_MOV(block, mem(&R15), I0); // mov <pc>,i0
1649		save_fast_iregs(arm, block);
	735	alloc_handle(drcuml, &m_impstate.out_of_cycles, "out_of_cycles");
	736	UML_HANDLE(block, *m_impstate.out_of_cycles); // handle out_of_cycles
	737	UML_GETEXP(block, uml::I0); // getexp i0
	738	UML_MOV(block, uml::mem(&R15), uml::I0); // mov <pc>,i0
	739	save_fast_iregs(block);
1650	740	UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES
1651	741
1652	742	block->end();
r24074	r24075
1657	747	static_generate_tlb_translate
1658	748	------------------------------------------------------------------*/
1659	749
1660		~~static~~ void static_generate_detect_fault(arm~~_state arm,~~ code_handle *handleptr)
	750	void arm7_cpu_device::static_generate_detect_fault(uml::code_handle **handleptr)
1661	751	{
1662	752	/* on entry, flags are in I2, vaddr is in I3, desc_lvl1 is in I4, ap is in R5 */
1663	753	/* on exit, fault result is in I6 */
1664		drcuml_state *drcuml = arm->impstate->drcuml;
	754	drcuml_state *drcuml = m_impstate.drcuml;
1665	755	drcuml_block *block;
1666	756	int donefault = 0;
1667	757	int checkuser = 0;
r24074	r24075
1671	761	block = drcuml->begin_block(1024);
1672	762
1673	763	/* add a global entry for this */
1674		alloc_handle(drcuml, &arm->impstate->detect_fault, "detect_fault");
1675		UML_HANDLE(block, *arm->impstate->detect_fault); // handle detect_fault
	764	alloc_handle(drcuml, &m_impstate.detect_fault, "detect_fault");
	765	UML_HANDLE(block, *m_impstate.detect_fault); // handle detect_fault
1676	766
1677		UML_ROLAND(block, I6, I4, 32-4, 0x0f<<1); // roland i6, i4, 32-4, 0xf<<1
1678		UML_ROLAND(block, I6, mem(&COPRO_DOMAIN_ACCESS_CONTROL), I6, 3);// roland i6, COPRO_DOMAIN_ACCESS_CONTROL, i6, 3
	767	UML_ROLAND(block, uml::I6, uml::I4, 32-4, 0x0f<<1); // roland i6, i4, 32-4, 0xf<<1
	768	UML_ROLAND(block, uml::I6, uml::mem(&COPRO_DOMAIN_ACCESS_CONTROL), uml::I6, 3);// roland i6, COPRO_DOMAIN_ACCESS_CONTROL, i6, 3
1679	769	// if permission == 3, FAULT_NONE
1680		UML_CMP(block, I6, 3); // cmp i6, 3
1681		UML_MOVc(block, COND_E, I6, FAULT_NONE); // move i6, FAULT_NONE
1682		UML_JMPc(block, COND_E, donefault = label++); // jmpe donefault
	770	UML_CMP(block, uml::I6, 3); // cmp i6, 3
	771	UML_MOVc(block, uml::COND_E, uml::I6, FAULT_NONE); // move i6, FAULT_NONE
	772	UML_JMPc(block, uml::COND_E, donefault = label++); // jmpe donefault
1683	773	// if permission == 0 \|\| permission == 2, FAULT_DOMAIN
1684		UML_CMP(block, I6, 1); // cmp i6, 1
1685		UML_MOVc(block, COND_NE, I6, FAULT_DOMAIN); // movne i6, FAULT_DOMAIN
1686		UML_JMPc(block, COND_NE, donefault); // jmpne donefault
	774	UML_CMP(block, uml::I6, 1); // cmp i6, 1
	775	UML_MOVc(block, uml::COND_NE, uml::I6, FAULT_DOMAIN); // movne i6, FAULT_DOMAIN
	776	UML_JMPc(block, uml::COND_NE, donefault); // jmpne donefault
1687	777
1688	778	// if permission == 1
1689		UML_CMP(block, I5, 3); // cmp i5, 3
1690		UML_MOVc(block, COND_E, I6, FAULT_NONE); // move i6, FAULT_NONE
1691		UML_JMPc(block, COND_E, donefault); // jmpe donefault
1692		UML_CMP(block, I5, 0); // cmp i5, 1
1693		UML_JMPc(block, COND_NE, checkuser = label++); // jmpne checkuser
1694		UML_ROLAND(block, I6, mem(&COPRO_CTRL), // roland i6, COPRO_CTRL, 32 - COPRO_CTRL_SYSTEM_SHIFT,
	779	UML_CMP(block, uml::I5, 3); // cmp i5, 3
	780	UML_MOVc(block, uml::COND_E, uml::I6, FAULT_NONE); // move i6, FAULT_NONE
	781	UML_JMPc(block, uml::COND_E, donefault); // jmpe donefault
	782	UML_CMP(block, uml::I5, 0); // cmp i5, 1
	783	UML_JMPc(block, uml::COND_NE, checkuser = label++); // jmpne checkuser
	784	UML_ROLAND(block, uml::I6, uml::mem(&COPRO_CTRL), // roland i6, COPRO_CTRL, 32 - COPRO_CTRL_SYSTEM_SHIFT,
1695	785	32 - COPRO_CTRL_SYSTEM_SHIFT, // COPRO_CTRL_SYSTEM \| COPRO_CTRL_ROM
1696	786	COPRO_CTRL_SYSTEM \| COPRO_CTRL_ROM);
1697	787	// if s == 0 && r == 0, FAULT_PERMISSION
1698		UML_CMP(block, I6, 0); // cmp i6, 0
1699		UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
1700		UML_JMPc(block, COND_E, donefault); // jmpe donefault
	788	UML_CMP(block, uml::I6, 0); // cmp i6, 0
	789	UML_MOVc(block, uml::COND_E, uml::I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
	790	UML_JMPc(block, uml::COND_E, donefault); // jmpe donefault
1701	791	// if s == 1 && r == 1, FAULT_PERMISSION
1702		UML_CMP(block, I6, 3); // cmp i6, 3
1703		UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
1704		UML_JMPc(block, COND_E, donefault); // jmpe donefault
	792	UML_CMP(block, uml::I6, 3); // cmp i6, 3
	793	UML_MOVc(block, uml::COND_E, uml::I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
	794	UML_JMPc(block, uml::COND_E, donefault); // jmpe donefault
1705	795	// if flags & TLB_WRITE, FAULT_PERMISSION
1706		UML_TEST(block, I2, ARM7_TLB_WRITE); // test i2, ARM7_TLB_WRITE
1707		UML_MOVc(block, COND_NZ, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
1708		UML_JMPc(block, COND_NZ, donefault); // jmpe donefault
	796	UML_TEST(block, uml::I2, ARM7_TLB_WRITE); // test i2, ARM7_TLB_WRITE
	797	UML_MOVc(block, uml::COND_NZ, uml::I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
	798	UML_JMPc(block, uml::COND_NZ, donefault); // jmpe donefault
1709	799	// if r == 1 && s == 0, FAULT_NONE
1710		UML_CMP(block, I6, 2); // cmp i6, 2
1711		UML_MOVc(block, COND_E, I6, FAULT_NONE); // move i6, FAULT_NONE
1712		UML_JMPc(block, COND_E, donefault); // jmpe donefault
1713		UML_AND(block, I6, mem(&GET_CPSR), MODE_FLAG); // and i6, GET_CPSR, MODE_FLAG
1714		UML_CMP(block, I6, eARM7_MODE_USER); // cmp i6, eARM7_MODE_USER
	800	UML_CMP(block, uml::I6, 2); // cmp i6, 2
	801	UML_MOVc(block, uml::COND_E, uml::I6, FAULT_NONE); // move i6, FAULT_NONE
	802	UML_JMPc(block, uml::COND_E, donefault); // jmpe donefault
	803	UML_AND(block, uml::I6, uml::mem(&GET_CPSR), MODE_FLAG); // and i6, GET_CPSR, MODE_FLAG
	804	UML_CMP(block, uml::I6, eARM7_MODE_USER); // cmp i6, eARM7_MODE_USER
1715	805	// if r == 0 && s == 1 && usermode, FAULT_PERMISSION
1716		UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
1717		UML_MOVc(block, COND_NE, I6, FAULT_NONE); // movne i6, FAULT_NONE
	806	UML_MOVc(block, uml::COND_E, uml::I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
	807	UML_MOVc(block, uml::COND_NE, uml::I6, FAULT_NONE); // movne i6, FAULT_NONE
1718	808	UML_JMP(block, donefault); // jmp donefault
1719	809
1720	810	UML_LABEL(block, checkuser); // checkuser:
1721	811	// if !write, FAULT_NONE
1722		UML_TEST(block, I2, ARM7_TLB_WRITE); // test i2, ARM7_TLB_WRITE
1723		UML_MOVc(block, COND_Z, I6, FAULT_NONE); // movz i6, FAULT_NONE
1724		UML_JMPc(block, COND_Z, donefault); // jmp donefault
1725		UML_AND(block, I6, mem(&GET_CPSR), MODE_FLAG); // and i6, GET_CPSR, MODE_FLAG
1726		UML_CMP(block, I6, eARM7_MODE_USER); // cmp i6, eARM7_MODE_USER
1727		UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
1728		UML_MOVc(block, COND_NE, I6, FAULT_NONE); // move i6, FAULT_NONE
	812	UML_TEST(block, uml::I2, ARM7_TLB_WRITE); // test i2, ARM7_TLB_WRITE
	813	UML_MOVc(block, uml::COND_Z, uml::I6, FAULT_NONE); // movz i6, FAULT_NONE
	814	UML_JMPc(block, uml::COND_Z, donefault); // jmp donefault
	815	UML_AND(block, uml::I6, uml::mem(&GET_CPSR), MODE_FLAG); // and i6, GET_CPSR, MODE_FLAG
	816	UML_CMP(block, uml::I6, eARM7_MODE_USER); // cmp i6, eARM7_MODE_USER
	817	UML_MOVc(block, uml::COND_E, uml::I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION
	818	UML_MOVc(block, uml::COND_NE, uml::I6, FAULT_NONE); // move i6, FAULT_NONE
1729	819
1730	820	UML_LABEL(block, donefault); // donefault:
1731	821	UML_RET(block); // ret
r24074	r24075
1735	825	static_generate_tlb_translate
1736	826	------------------------------------------------------------------*/
1737	827
1738		~~static~~ void static_generate_tlb_translate(arm~~_state arm,~~ code_handle *handleptr)
	828	void arm7_cpu_device::static_generate_tlb_translate(uml::code_handle **handleptr)
1739	829	{
1740	830	/* on entry, address is in I0 and flags are in I2 */
1741	831	/* on exit, translated address is in I0 and success/failure is in I2 */
1742	832	/* routine trashes I4-I7 */
1743		drcuml_state *drcuml = arm->impstate->drcuml;
	833	drcuml_state *drcuml = m_impstate.drcuml;
1744	834	drcuml_block *block;
	835	uml::code_label smallfault;
	836	uml::code_label smallprefetch;
1745	837	int nopid = 0;
1746	838	int nounmapped = 0;
1747	839	int nounmapped2 = 0;
r24074	r24075
1760	852	/* begin generating */
1761	853	block = drcuml->begin_block(170);
1762	854
1763		alloc_handle(drcuml, &arm->impstate->tlb_translate, "tlb_translate");
1764		UML_HANDLE(block, *arm->impstate->tlb_translate); // handle tlb_translate
	855	alloc_handle(drcuml, &m_impstate.tlb_translate, "tlb_translate");
	856	UML_HANDLE(block, *m_impstate.tlb_translate); // handle tlb_translate
1765	857
1766	858	// I3: vaddr
1767		UML_CMP(block, I0, 32 * 1024 * 1024); // cmp i0, 3210241024
1768		UML_JMPc(block, COND_GE, nopid = label++); // jmpge nopid
1769		UML_AND(block, I3, mem(&COPRO_FCSE_PID), 0xfe000000); // and i3, COPRO_FCSE_PID, 0xfe000000
1770		UML_ADD(block, I3, I3, I0); // add i3, i3, i0
	859	UML_CMP(block, uml::I0, 32 * 1024 * 1024); // cmp i0, 3210241024
	860	UML_JMPc(block, uml::COND_GE, nopid = label++); // jmpge nopid
	861	UML_AND(block, uml::I3, uml::mem(&COPRO_FCSE_PID), 0xfe000000); // and i3, COPRO_FCSE_PID, 0xfe000000
	862	UML_ADD(block, uml::I3, uml::I3, uml::I0); // add i3, i3, i0
1771	863
1772	864	// I4: desc_lvl1
1773		UML_AND(block, I4, mem(&COPRO_TLB_BASE), COPRO_TLB_BASE_MASK); // and i4, COPRO_TLB_BASE, COPRO_TLB_BASE_MASK
1774		UML_ROLINS(block, I4, I3, 32 - COPRO_TLB_VADDR_FLTI_MASK_SHIFT, // rolins i4, i3, 32-COPRO_TLB_VADDR_FLTI_MASK_SHIFT,
	865	UML_AND(block, uml::I4, uml::mem(&COPRO_TLB_BASE), COPRO_TLB_BASE_MASK); // and i4, COPRO_TLB_BASE, COPRO_TLB_BASE_MASK
	866	UML_ROLINS(block, uml::I4, uml::I3, 32 - COPRO_TLB_VADDR_FLTI_MASK_SHIFT, // rolins i4, i3, 32-COPRO_TLB_VADDR_FLTI_MASK_SHIFT,
1775	867	COPRO_TLB_VADDR_FLTI_MASK); // COPRO_TLB_VADDR_FLTI_MASK
1776		UML_READ(block, I4, I4, SIZE_DWORD, SPACE_PROGRAM); // read32 i4, i4, PROGRAM
	868	UML_READ(block, uml::I4, uml::I4, uml::SIZE_DWORD, uml::SPACE_PROGRAM); // read32 i4, i4, PROGRAM
1777	869
1778	870	// I7: desc_lvl1 & 3
1779		UML_AND(block, I7, I4, 3); // and i7, i4, 3
	871	UML_AND(block, uml::I7, uml::I4, 3); // and i7, i4, 3
1780	872
1781		UML_CMP(block, I7, COPRO_TLB_UNMAPPED); // cmp i7, COPRO_TLB_UNMAPPED
1782		UML_JMPc(block, COND_NE, nounmapped = label++); // jmpne nounmapped
	873	UML_CMP(block, uml::I7, COPRO_TLB_UNMAPPED); // cmp i7, COPRO_TLB_UNMAPPED
	874	UML_JMPc(block, uml::COND_NE, nounmapped = label++); // jmpne nounmapped
1783	875
1784	876	// TLB Unmapped
1785		UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D
1786		UML_MOVc(block, COND_E, mem(&COPRO_FAULT_STATUS_D), (5 << 0)); // move COPRO_FAULT_STATUS_D, (5 << 0)
1787		UML_MOVc(block, COND_E, mem(&COPRO_FAULT_ADDRESS), I3); // move COPRO_FAULT_ADDRESS, i3
1788		UML_MOVc(block, COND_E, mem(&arm->pendingAbtD), 1); // move pendingAbtD, 1
1789		UML_MOVc(block, COND_E, I2, 0); // move i2, 0
1790		UML_RETc(block, COND_E); // rete
	877	UML_TEST(block, uml::I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D
	878	UML_MOVc(block, uml::COND_E, uml::mem(&COPRO_FAULT_STATUS_D), (5 << 0)); // move COPRO_FAULT_STATUS_D, (5 << 0)
	879	UML_MOVc(block, uml::COND_E, uml::mem(&COPRO_FAULT_ADDRESS), uml::I3); // move COPRO_FAULT_ADDRESS, i3
	880	UML_MOVc(block, uml::COND_E, uml::mem(&m_pendingAbtD), 1); // move pendingAbtD, 1
	881	UML_MOVc(block, uml::COND_E, uml::I2, 0); // move i2, 0
	882	UML_RETc(block, uml::COND_E); // rete
1791	883
1792		UML_TEST(block, I2, ARM7_TLB_ABORT_P); // test i2, ARM7_TLB_ABORT_P
1793		UML_MOVc(block, COND_E, mem(&arm->pendingAbtP), 1); // move pendingAbtP, 1
1794		UML_MOV(block, I2, 0); // mov i2, 0
	884	UML_TEST(block, uml::I2, ARM7_TLB_ABORT_P); // test i2, ARM7_TLB_ABORT_P
	885	UML_MOVc(block, uml::COND_E, uml::mem(&m_pendingAbtP), 1); // move pendingAbtP, 1
	886	UML_MOV(block, uml::I2, 0); // mov i2, 0
1795	887	UML_RET(block); // ret
1796	888
1797	889	UML_LABEL(block, nounmapped); // nounmapped:
1798		UML_CMP(block, I7, COPRO_TLB_COARSE_TABLE); // cmp i7, COPRO_TLB_COARSE_TABLE
1799		UML_JMPc(block, COND_NE, nocoarse = label++); // jmpne nocoarse
	890	UML_CMP(block, uml::I7, COPRO_TLB_COARSE_TABLE); // cmp i7, COPRO_TLB_COARSE_TABLE
	891	UML_JMPc(block, uml::COND_NE, nocoarse = label++); // jmpne nocoarse
1800	892
1801		UML_ROLAND(block, I5, I4, 32-4, 0x0f<<1); // roland i5, i4, 32-4, 0xf<<1
1802		UML_ROLAND(block, I5, mem(&COPRO_DOMAIN_ACCESS_CONTROL), I5, 3);// roland i5, COPRO_DOMAIN_ACCESS_CONTROL, i5, 3
1803		UML_CMP(block, I5, 1); // cmp i5, 1
1804		UML_JMPc(block, COND_E, level2 = label++); // jmpe level2
1805		UML_CMP(block, I5, 3); // cmp i5, 3
1806		UML_JMPc(block, COND_NE, nofine = label++); // jmpne nofine
	893	UML_ROLAND(block, uml::I5, uml::I4, 32-4, 0x0f<<1); // roland i5, i4, 32-4, 0xf<<1
	894	UML_ROLAND(block, uml::I5, uml::mem(&COPRO_DOMAIN_ACCESS_CONTROL), uml::I5, 3);// roland i5, COPRO_DOMAIN_ACCESS_CONTROL, i5, 3
	895	UML_CMP(block, uml::I5, 1); // cmp i5, 1
	896	UML_JMPc(block, uml::COND_E, level2 = label++); // jmpe level2
	897	UML_CMP(block, uml::I5, 3); // cmp i5, 3
	898	UML_JMPc(block, uml::COND_NE, nofine = label++); // jmpne nofine
1807	899	UML_LABEL(block, level2); // level2:
1808	900
1809	901	// I7: desc_level2
1810		UML_AND(block, I7, I4, COPRO_TLB_CFLD_ADDR_MASK); // and i7, i4, COPRO_TLB_CFLD_ADDR_MASK
1811		UML_ROLINS(block, I7, I3, 32 - COPRO_TLB_VADDR_CSLTI_MASK_SHIFT,// rolins i7, i3, 32 - COPRO_TLB_VADDR_CSLTI_MASK_SHIFT
	902	UML_AND(block, uml::I7, uml::I4, COPRO_TLB_CFLD_ADDR_MASK); // and i7, i4, COPRO_TLB_CFLD_ADDR_MASK
	903	UML_ROLINS(block, uml::I7, uml::I3, 32 - COPRO_TLB_VADDR_CSLTI_MASK_SHIFT,// rolins i7, i3, 32 - COPRO_TLB_VADDR_CSLTI_MASK_SHIFT
1812	904	COPRO_TLB_VADDR_CSLTI_MASK); // COPRO_TLB_VADDR_CSLTI_MASK
1813		UML_READ(block, I7, I7, SIZE_DWORD, SPACE_PROGRAM); // read32 i7, i7, PROGRAM
	905	UML_READ(block, uml::I7, uml::I7, uml::SIZE_DWORD, uml::SPACE_PROGRAM); // read32 i7, i7, PROGRAM
1814	906	UML_JMP(block, nofine); // jmp nofine
1815	907
1816	908	UML_LABEL(block, nocoarse); // nocoarse:
1817		UML_CMP(block, I7, COPRO_TLB_SECTION_TABLE); // cmp i7, COPRO_TLB_SECTION_TABLE
1818		UML_JMPc(block, COND_NE, nosection = label++); // jmpne nosection
	909	UML_CMP(block, uml::I7, COPRO_TLB_SECTION_TABLE); // cmp i7, COPRO_TLB_SECTION_TABLE
	910	UML_JMPc(block, uml::COND_NE, nosection = label++); // jmpne nosection
1819	911
1820		UML_ROLAND(block, I5, I4, 32-10, 3); // roland i7, i4, 32-10, 3
	912	UML_ROLAND(block, uml::I5, uml::I4, 32-10, 3); // roland i7, i4, 32-10, 3
1821	913	// result in I6
1822		UML_CALLH(block, *arm->impstate->detect_fault); // callh detect_fault
1823		UML_CMP(block, I6, FAULT_NONE); // cmp i6, FAULT_NONE
1824		UML_JMPc(block, COND_NE, handlefault = label++); // jmpne handlefault
	914	UML_CALLH(block, *m_impstate.detect_fault); // callh detect_fault
	915	UML_CMP(block, uml::I6, FAULT_NONE); // cmp i6, FAULT_NONE
	916	UML_JMPc(block, uml::COND_NE, handlefault = label++); // jmpne handlefault
1825	917
1826	918	// no fault, return translated address
1827		UML_AND(block, I0, I3, ~COPRO_TLB_SECTION_PAGE_MASK); // and i0, i3, ~COPRO_TLB_SECTION_PAGE_MASK
1828		UML_ROLINS(block, I0, I4, 0, COPRO_TLB_SECTION_PAGE_MASK); // rolins i0, i4, COPRO_TLB_SECTION_PAGE_MASK
1829		UML_MOV(block, I2, 1); // mov i2, 1
	919	UML_AND(block, uml::I0, uml::I3, ~COPRO_TLB_SECTION_PAGE_MASK); // and i0, i3, ~COPRO_TLB_SECTION_PAGE_MASK
	920	UML_ROLINS(block, uml::I0, uml::I4, 0, COPRO_TLB_SECTION_PAGE_MASK); // rolins i0, i4, COPRO_TLB_SECTION_PAGE_MASK
	921	UML_MOV(block, uml::I2, 1); // mov i2, 1
1830	922	UML_RET(block); // ret
1831	923
1832	924	UML_LABEL(block, handlefault); // handlefault:
1833		UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D
1834		UML_JMPc(block, COND_Z, prefetch = label++); // jmpz prefetch
1835		UML_MOV(block, mem(&COPRO_FAULT_ADDRESS), I3); // mov COPRO_FAULT_ADDRESS, i3
1836		UML_MOV(block, mem(&arm->pendingAbtD), 1); // mov arm->pendingAbtD, 1
1837		UML_ROLAND(block, I5, I4, 31, 0xf0); // roland i5, i4, 31, 0xf0
1838		UML_CMP(block, I6, FAULT_DOMAIN); // cmp i6, FAULT_DOMAIN
1839		UML_MOVc(block, COND_E, I6, 9 << 0); // move i6, 9 << 0
1840		UML_MOVc(block, COND_NE, I6, 13 << 0); // movne i6, 13 << 0
1841		UML_OR(block, mem(&COPRO_FAULT_STATUS_D), I5, I6); // or COPRO_FAULT_STATUS_D, i5, i6
1842		UML_MOV(block, I2, 0); // mov i2, 0
	925	UML_TEST(block, uml::I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D
	926	UML_JMPc(block, uml::COND_Z, prefetch = label++); // jmpz prefetch
	927	UML_MOV(block, uml::mem(&COPRO_FAULT_ADDRESS), uml::I3); // mov COPRO_FAULT_ADDRESS, i3
	928	UML_MOV(block, uml::mem(&m_pendingAbtD), 1); // mov m_pendingAbtD, 1
	929	UML_ROLAND(block, uml::I5, uml::I4, 31, 0xf0); // roland i5, i4, 31, 0xf0
	930	UML_CMP(block, uml::I6, FAULT_DOMAIN); // cmp i6, FAULT_DOMAIN
	931	UML_MOVc(block, uml::COND_E, uml::I6, 9 << 0); // move i6, 9 << 0
	932	UML_MOVc(block, uml::COND_NE, uml::I6, 13 << 0); // movne i6, 13 << 0
	933	UML_OR(block, uml::mem(&COPRO_FAULT_STATUS_D), uml::I5, uml::I6); // or COPRO_FAULT_STATUS_D, i5, i6
	934	UML_MOV(block, uml::I2, 0); // mov i2, 0
1843	935	UML_RET(block); // ret
1844	936
1845	937	UML_LABEL(block, prefetch); // prefetch:
1846		UML_MOV(block, mem(&arm->pendingAbtP), 1); // mov arm->pendingAbtP, 1
1847		UML_MOV(block, I2, 0); // mov i2, 0
	938	UML_MOV(block, uml::mem(&m_pendingAbtP), 1); // mov m_pendingAbtP, 1
	939	UML_MOV(block, uml::I2, 0); // mov i2, 0
1848	940	UML_RET(block); // ret
1849	941
1850	942	UML_LABEL(block, nosection); // nosection:
1851		UML_CMP(block, I7, COPRO_TLB_FINE_TABLE); // cmp i7, COPRO_TLB_FINE_TABLE
1852		UML_JMPc(block, COND_NE, nofine); // jmpne nofine
	943	UML_CMP(block, uml::I7, COPRO_TLB_FINE_TABLE); // cmp i7, COPRO_TLB_FINE_TABLE
	944	UML_JMPc(block, uml::COND_NE, nofine); // jmpne nofine
1853	945
1854	946	// Not yet implemented
1855		UML_MOV(block, I2, 1); // mov i2, 1
	947	UML_MOV(block, uml::I2, 1); // mov i2, 1
1856	948	UML_RET(block); // ret
1857	949
1858	950	UML_LABEL(block, nofine); // nofine:
1859	951
1860	952	// I7: desc_lvl2
1861		UML_AND(block, I6, I7, 3); // and i6, i7, 3
1862		UML_CMP(block, I6, COPRO_TLB_UNMAPPED); // cmp i6, COPRO_TLB_UNMAPPED
1863		UML_JMPc(block, COND_NE, nounmapped2 = label++); // jmpne nounmapped2
	953	UML_AND(block, uml::I6, uml::I7, 3); // and i6, i7, 3
	954	UML_CMP(block, uml::I6, COPRO_TLB_UNMAPPED); // cmp i6, COPRO_TLB_UNMAPPED
	955	UML_JMPc(block, uml::COND_NE, nounmapped2 = label++); // jmpne nounmapped2
1864	956
1865		UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D
1866		UML_JMPc(block, COND_Z, prefetch2 = label++); // jmpz prefetch2
1867		UML_MOV(block, mem(&COPRO_FAULT_ADDRESS), I3); // mov COPRO_FAULT_ADDRESS, i3
1868		UML_MOV(block, mem(&arm->pendingAbtD), 1); // mov arm->pendingAbtD, 1
1869		UML_ROLAND(block, I5, I4, 31, 0xf0); // roland i5, i4, 31, 0xf0
1870		UML_OR(block, I5, I5, 7 << 0); // or i5, i5, 7 << 0
1871		UML_OR(block, mem(&COPRO_FAULT_STATUS_D), I5, I6); // or COPRO_FAULT_STATUS_D, i5, i6
1872		UML_MOV(block, I2, 0); // mov i2, 0
	957	UML_TEST(block, uml::I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D
	958	UML_JMPc(block, uml::COND_Z, prefetch2 = label++); // jmpz prefetch2
	959	UML_MOV(block, uml::mem(&COPRO_FAULT_ADDRESS), uml::I3); // mov COPRO_FAULT_ADDRESS, i3
	960	UML_MOV(block, uml::mem(&m_pendingAbtD), 1); // mov m_pendingAbtD, 1
	961	UML_ROLAND(block, uml::I5, uml::I4, 31, 0xf0); // roland i5, i4, 31, 0xf0
	962	UML_OR(block, uml::I5, uml::I5, 7 << 0); // or i5, i5, 7 << 0
	963	UML_OR(block, uml::mem(&COPRO_FAULT_STATUS_D), uml::I5, uml::I6); // or COPRO_FAULT_STATUS_D, i5, i6
	964	UML_MOV(block, uml::I2, 0); // mov i2, 0
1873	965	UML_RET(block); // ret
1874	966
1875	967	UML_LABEL(block, prefetch2); // prefetch2:
1876		UML_MOV(block, mem(&arm->pendingAbtP), 1); // mov arm->pendingAbtP, 1
1877		UML_MOV(block, I2, 0); // mov i2, 0
	968	UML_MOV(block, uml::mem(&m_pendingAbtP), 1); // mov m_pendingAbtP, 1
	969	UML_MOV(block, uml::I2, 0); // mov i2, 0
1878	970	UML_RET(block); // ret
1879	971
1880	972	UML_LABEL(block, nounmapped2); // nounmapped2:
1881		UML_CMP(block, I6, COPRO_TLB_LARGE_PAGE); // cmp i6, COPRO_TLB_LARGE_PAGE
1882		UML_JMPc(block, COND_NE, nolargepage = label++); // jmpne nolargepage
	973	UML_CMP(block, uml::I6, COPRO_TLB_LARGE_PAGE); // cmp i6, COPRO_TLB_LARGE_PAGE
	974	UML_JMPc(block, uml::COND_NE, nolargepage = label++); // jmpne nolargepage
1883	975
1884		UML_AND(block, I0, I3, ~COPRO_TLB_LARGE_PAGE_MASK); // and i0, i3, ~COPRO_TLB_LARGE_PAGE_MASK
1885		UML_ROLINS(block, I0, I7, 0, COPRO_TLB_LARGE_PAGE_MASK); // rolins i0, i7, 0, COPRO_TLB_LARGE_PAGE_MASK
1886		UML_MOV(block, I2, 1); // mov i2, 1
	976	UML_AND(block, uml::I0, uml::I3, ~COPRO_TLB_LARGE_PAGE_MASK); // and i0, i3, ~COPRO_TLB_LARGE_PAGE_MASK
	977	UML_ROLINS(block, uml::I0, uml::I7, 0, COPRO_TLB_LARGE_PAGE_MASK); // rolins i0, i7, 0, COPRO_TLB_LARGE_PAGE_MASK
	978	UML_MOV(block, uml::I2, 1); // mov i2, 1
1887	979	UML_RET(block); // ret
1888	980
1889	981	UML_LABEL(block, nolargepage); // nolargepage:
1890		UML_CMP(block, I6, COPRO_TLB_SMALL_PAGE); // cmp i6, COPRO_TLB_SMALL_PAGE
1891		UML_JMPc(block, COND_NE, nosmallpage = label++); // jmpne nosmallpage
	982	UML_CMP(block, uml::I6, COPRO_TLB_SMALL_PAGE); // cmp i6, COPRO_TLB_SMALL_PAGE
	983	UML_JMPc(block, uml::COND_NE, nosmallpage = label++); // jmpne nosmallpage
1892	984
1893		UML_ROLAND(block, I5, I3, 32-9, 3<<1); // roland i5, i3, 32-9, 3<<1
1894		UML_ROLAND(block, I6, I7, 32-4, 0xff); // roland i6, i7, 32-4, 0xff
1895		UML_SHR(block, I5, I7, I5); // shr i5, i7, i5
1896		UML_AND(block, I5, I5, 3); // and i5, i5, 3
	985	UML_ROLAND(block, uml::I5, uml::I3, 32-9, 3<<1); // roland i5, i3, 32-9, 3<<1
	986	UML_ROLAND(block, uml::I6, uml::I7, 32-4, 0xff); // roland i6, i7, 32-4, 0xff
	987	UML_SHR(block, uml::I5, uml::I7, uml::I5); // shr i5, i7, i5
	988	UML_AND(block, uml::I5, uml::I5, 3); // and i5, i5, 3
1897	989	// result in I6
1898		UML_CALLH(block, *arm->impstate->detect_fault); // callh detect_fault
	990	UML_CALLH(block, *m_impstate.detect_fault); // callh detect_fault
1899	991
1900		UML_CMP(block, I6, FAULT_NONE); // cmp i6, FAULT_NONE
1901		UML_JMPc(block, COND_NE, smallfault = label++); // jmpne smallfault
1902		UML_AND(block, I0, I7, COPRO_TLB_SMALL_PAGE_MASK); // and i0, i7, COPRO_TLB_SMALL_PAGE_MASK
1903		UML_ROLINS(block, I0, I3, 0, ~COPRO_TLB_SMALL_PAGE_MASK); // rolins i0, i3, 0, ~COPRO_TLB_SMALL_PAGE_MASK
1904		UML_MOV(block, I2, 1); // mov i2, 1
	992	UML_CMP(block, uml::I6, FAULT_NONE); // cmp i6, FAULT_NONE
	993	UML_JMPc(block, uml::COND_NE, smallfault = label++); // jmpne smallfault
	994	UML_AND(block, uml::I0, uml::I7, COPRO_TLB_SMALL_PAGE_MASK); // and i0, i7, COPRO_TLB_SMALL_PAGE_MASK
	995	UML_ROLINS(block, uml::I0, uml::I3, 0, ~COPRO_TLB_SMALL_PAGE_MASK); // rolins i0, i3, 0, ~COPRO_TLB_SMALL_PAGE_MASK
	996	UML_MOV(block, uml::I2, 1); // mov i2, 1
1905	997	UML_RET(block); // ret
1906	998
1907	999	UML_LABEL(block, smallfault); // smallfault:
1908		UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D
1909		UML_JMPc(block, COND_NZ, smallprefetch = label++); // jmpnz smallprefetch
1910		UML_MOV(block, mem(&COPRO_FAULT_ADDRESS), I3); // mov COPRO_FAULT_ADDRESS, i3
1911		UML_MOV(block, mem(&arm->pendingAbtD), 1); // mov pendingAbtD, 1
1912		UML_CMP(block, I6, FAULT_DOMAIN); // cmp i6, FAULT_DOMAIN
1913		UML_MOVc(block, COND_E, I5, 11 << 0); // move i5, 11 << 0
1914		UML_MOVc(block, COND_NE, I5, 15 << 0); // movne i5, 15 << 0
1915		UML_ROLINS(block, I5, I4, 31, 0xf0); // rolins i5, i4, 31, 0xf0
1916		UML_MOV(block, mem(&COPRO_FAULT_STATUS_D), I5); // mov COPRO_FAULT_STATUS_D, i5
1917		UML_MOV(block, I2, 0); // mov i2, 0
	1000	UML_TEST(block, uml::I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D
	1001	UML_JMPc(block, uml::COND_NZ, smallprefetch = label++); // jmpnz smallprefetch
	1002	UML_MOV(block, uml::mem(&COPRO_FAULT_ADDRESS), uml::I3); // mov COPRO_FAULT_ADDRESS, i3
	1003	UML_MOV(block, uml::mem(&m_pendingAbtD), 1); // mov pendingAbtD, 1
	1004	UML_CMP(block, uml::I6, FAULT_DOMAIN); // cmp i6, FAULT_DOMAIN
	1005	UML_MOVc(block, uml::COND_E, uml::I5, 11 << 0); // move i5, 11 << 0
	1006	UML_MOVc(block, uml::COND_NE, uml::I5, 15 << 0); // movne i5, 15 << 0
	1007	UML_ROLINS(block, uml::I5, uml::I4, 31, 0xf0); // rolins i5, i4, 31, 0xf0
	1008	UML_MOV(block, uml::mem(&COPRO_FAULT_STATUS_D), uml::I5); // mov COPRO_FAULT_STATUS_D, i5
	1009	UML_MOV(block, uml::I2, 0); // mov i2, 0
1918	1010	UML_RET(block); // ret
1919	1011
1920	1012	UML_LABEL(block, smallprefetch); // smallprefetch:
1921		UML_MOV(block, mem(&arm->pendingAbtP), 1); // mov pendingAbtP, 1
1922		UML_MOV(block, I2, 0); // mov i2, 0
	1013	UML_MOV(block, uml::mem(&m_pendingAbtP), 1); // mov pendingAbtP, 1
	1014	UML_MOV(block, uml::I2, 0); // mov i2, 0
1923	1015	UML_RET(block); // ret
1924	1016
1925	1017	UML_LABEL(block, nosmallpage); // nosmallpage:
1926		UML_CMP(block, I6, COPRO_TLB_TINY_PAGE); // cmp i6, COPRO_TLB_TINY_PAGE
1927		UML_JMPc(block, COND_NE, notinypage = label++); // jmpne notinypage
	1018	UML_CMP(block, uml::I6, COPRO_TLB_TINY_PAGE); // cmp i6, COPRO_TLB_TINY_PAGE
	1019	UML_JMPc(block, uml::COND_NE, notinypage = label++); // jmpne notinypage
1928	1020
1929		UML_AND(block, I0, I3, ~COPRO_TLB_TINY_PAGE_MASK); // and i0, i3, ~COPRO_TLB_TINY_PAGE_MASK
1930		UML_ROLINS(block, I0, I7, 0, COPRO_TLB_TINY_PAGE_MASK); // rolins i0, i7, 0, COPRO_TLB_TINY_PAGE_MASK
1931		UML_MOV(block, I2, 1); // mov i2, 1
	1021	UML_AND(block, uml::I0, uml::I3, ~COPRO_TLB_TINY_PAGE_MASK); // and i0, i3, ~COPRO_TLB_TINY_PAGE_MASK
	1022	UML_ROLINS(block, uml::I0, uml::I7, 0, COPRO_TLB_TINY_PAGE_MASK); // rolins i0, i7, 0, COPRO_TLB_TINY_PAGE_MASK
	1023	UML_MOV(block, uml::I2, 1); // mov i2, 1
1932	1024	UML_RET(block); // ret
1933	1025
1934	1026	UML_LABEL(block, notinypage); // notinypage:
1935		UML_MOV(block, I0, I3); // mov i0, i3
	1027	UML_MOV(block, uml::I0, uml::I3); // mov i0, i3
1936	1028	UML_RET(block); // ret
1937	1029
1938	1030	block->end();
r24074	r24075
1942	1034	static_generate_memory_accessor
1943	1035	------------------------------------------------------------------*/
1944	1036
1945		~~static~~ void static_generate_memory_accessor(~~arm_state arm,~~ int size, bool istlb, bool iswrite, const char name, code_handle **handleptr)
	1037	void arm7_cpu_device::static_generate_memory_accessor(int size, bool istlb, bool iswrite, const char name, uml::code_handle *handleptr)
1946	1038	{
1947	1039	/* on entry, address is in I0; data for writes is in I1, fetch type in I2 */
1948	1040	/* on exit, read result is in I0 */
1949	1041	/* routine trashes I0-I3 */
1950		drcuml_state *drcuml = arm->impstate->drcuml;
	1042	drcuml_state *drcuml = m_impstate.drcuml;
1951	1043	drcuml_block *block;
1952		int tlbmiss = 0;
	1044	//int tlbmiss = 0;
1953	1045	int label = 1;
1954	1046
1955	1047	/* begin generating */
r24074	r24075
1961	1053
1962	1054	if (istlb)
1963	1055	{
1964		UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN
	1056	UML_TEST(block, uml::mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN
1965	1057	if (iswrite)
1966	1058	{
1967		UML_MOVc(block, COND_NZ, I3, ARM7_TLB_WRITE); // movnz i3, ARM7_TLB_WRITE
	1059	UML_MOVc(block, uml::COND_NZ, uml::I3, ARM7_TLB_WRITE); // movnz i3, ARM7_TLB_WRITE
1968	1060	}
1969	1061	else
1970	1062	{
1971		UML_MOVc(block, COND_NZ, I3, ARM7_TLB_READ); // movnz i3, ARM7_TLB_READ
	1063	UML_MOVc(block, uml::COND_NZ, uml::I3, ARM7_TLB_READ); // movnz i3, ARM7_TLB_READ
1972	1064	}
1973		UML_OR(block, I2, I2, I3); // or i2, i2, i3
1974		UML_CALLHc(block, COND_NZ, *arm->impstate->tlb_translate); // callhnz tlb_translate
	1065	UML_OR(block, uml::I2, uml::I2, uml::I3); // or i2, i2, i3
	1066	UML_CALLHc(block, uml::COND_NZ, *m_impstate.tlb_translate); // callhnz tlb_translate
1975	1067	}
1976	1068
1977	1069	/* general case: assume paging and perform a translation */
1978		if ((~~arm->device->~~machine().debug_flags & DEBUG_FLAG_ENABLED) == 0)
	1070	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0)
1979	1071	{
1980	1072	for (int ramnum = 0; ramnum < ARM7_MAX_FASTRAM; ramnum++)
1981	1073	{
1982		if (arm->impstate->fastram[ramnum].base != NULL && (!iswrite \|\| !arm->impstate->fastram[ramnum].readonly))
	1074	if (m_impstate.fastram[ramnum].base != NULL && (!iswrite \|\| !m_impstate.fastram[ramnum].readonly))
1983	1075	{
1984		void fastbase = (UINT8 )arm->impstate->fastram[ramnum].base - arm->impstate->fastram[ramnum].start;
	1076	void fastbase = (UINT8 )m_impstate.fastram[ramnum].base - m_impstate.fastram[ramnum].start;
1985	1077	UINT32 skip = label++;
1986		if (arm->impstate->fastram[ramnum].end != 0xffffffff)
	1078	if (m_impstate.fastram[ramnum].end != 0xffffffff)
1987	1079	{
1988		UML_CMP(block, I0, arm->impstate->fastram[ramnum].end); // cmp i0, end
1989		UML_JMPc(block, COND_A, skip); // ja skip
	1080	UML_CMP(block, uml::I0, m_impstate.fastram[ramnum].end); // cmp i0, end
	1081	UML_JMPc(block, uml::COND_A, skip); // ja skip
1990	1082	}
1991		if (arm->impstate->fastram[ramnum].start != 0x00000000)
	1083	if (m_impstate.fastram[ramnum].start != 0x00000000)
1992	1084	{
1993		UML_CMP(block, I0, arm->impstate->fastram[ramnum].start); // cmp i0, fastram_start
1994		UML_JMPc(block, COND_B, skip); // jb skip
	1085	UML_CMP(block, uml::I0, m_impstate.fastram[ramnum].start); // cmp i0, fastram_start
	1086	UML_JMPc(block, uml::COND_B, skip); // jb skip
1995	1087	}
1996	1088
1997	1089	if (!iswrite)
1998	1090	{
1999	1091	if (size == 1)
2000	1092	{
2001		UML_XOR(block, I0, I0, (arm->endian~~ess~~ == ENDIANNESS_BIG) ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0));
	1093	UML_XOR(block, uml::I0, uml::I0, (m_endian == ENDIANNESS_BIG) ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0));
2002	1094	// xor i0, i0, bytexor
2003		UML_LOAD(block, I0, fastbase, I0, SIZE_BYTE, SCALE_x1); // load i0, fastbase, i0, byte
	1095	UML_LOAD(block, uml::I0, fastbase, uml::I0, uml::SIZE_BYTE, uml::SCALE_x1); // load i0, fastbase, i0, byte
2004	1096	}
2005	1097	else if (size == 2)
2006	1098	{
2007		UML_XOR(block, I0, I0, (arm->endian~~ess~~ == ENDIANNESS_BIG) ? WORD_XOR_BE(0) : WORD_XOR_LE(0));
	1099	UML_XOR(block, uml::I0, uml::I0, (m_endian == ENDIANNESS_BIG) ? WORD_XOR_BE(0) : WORD_XOR_LE(0));
2008	1100	// xor i0, i0, wordxor
2009		UML_LOAD(block, I0, fastbase, I0, SIZE_WORD, SCALE_x1); // load i0, fastbase, i0, word_x1
	1101	UML_LOAD(block, uml::I0, fastbase, uml::I0, uml::SIZE_WORD, uml::SCALE_x1); // load i0, fastbase, i0, word_x1
2010	1102	}
2011	1103	else if (size == 4)
2012	1104	{
2013		UML_LOAD(block, I0, fastbase, I0, SIZE_DWORD, SCALE_x1); // load i0, fastbase, i0, dword_x1
	1105	UML_LOAD(block, uml::I0, fastbase, uml::I0, uml::SIZE_DWORD, uml::SCALE_x1); // load i0, fastbase, i0, dword_x1
2014	1106	}
2015	1107	UML_RET(block); // ret
2016	1108	}
r24074	r24075
2018	1110	{
2019	1111	if (size == 1)
2020	1112	{
2021		UML_XOR(block, I0, I0, (arm->endian~~ess~~ == ENDIANNESS_BIG) ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0));
	1113	UML_XOR(block, uml::I0, uml::I0, (m_endian == ENDIANNESS_BIG) ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0));
2022	1114	// xor i0, i0, bytexor
2023		UML_STORE(block, fastbase, I0, I1, SIZE_BYTE, SCALE_x1); // store fastbase, i0, i1, byte
	1115	UML_STORE(block, fastbase, uml::I0, uml::I1, uml::SIZE_BYTE, uml::SCALE_x1); // store fastbase, i0, i1, byte
2024	1116	}
2025	1117	else if (size == 2)
2026	1118	{
2027		UML_XOR(block, I0, I0, arm~~->big~~endian ? WORD_XOR_BE(0) : WORD_XOR_LE(0));
	1119	UML_XOR(block, uml::I0, uml::I0, (m_endian == ENDIANNESS_BIG) ? WORD_XOR_BE(0) : WORD_XOR_LE(0));
2028	1120	// xor i0, i0, wordxor
2029		UML_STORE(block, fastbase, I0, I1, SIZE_WORD, SCALE_x1); // store fastbase, i0, i1, word_x1
	1121	UML_STORE(block, fastbase, uml::I0, uml::I1, uml::SIZE_WORD, uml::SCALE_x1); // store fastbase, i0, i1, word_x1
2030	1122	}
2031	1123	else if (size == 4)
2032	1124	{
2033		UML_STORE(block, fastbase, I0, I1, SIZE_DWORD, SCALE_x1); // store fastbase,i0,i1,dword_x1
	1125	UML_STORE(block, fastbase, uml::I0, uml::I1, uml::SIZE_DWORD, uml::SCALE_x1); // store fastbase,i0,i1,dword_x1
2034	1126	}
2035	1127	UML_RET(block); // ret
2036	1128	}
r24074	r24075
2045	1137	case 1:
2046	1138	if (iswrite)
2047	1139	{
2048		UML_WRITE(block, I0, I1, SIZE_BYTE, SPACE_PROGRAM); // write i0, i1, program_byte
	1140	UML_WRITE(block, uml::I0, uml::I1, uml::SIZE_BYTE, uml::SPACE_PROGRAM); // write i0, i1, program_byte
2049	1141	}
2050	1142	else
2051	1143	{
2052		UML_READ(block, I0, I0, SIZE_BYTE, SPACE_PROGRAM); // read i0, i0, program_byte
	1144	UML_READ(block, uml::I0, uml::I0, uml::SIZE_BYTE, uml::SPACE_PROGRAM); // read i0, i0, program_byte
2053	1145	}
2054	1146	break;
2055	1147
2056	1148	case 2:
2057	1149	if (iswrite)
2058	1150	{
2059		UML_WRITE(block, I0, I1, SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word
	1151	UML_WRITE(block, uml::I0, uml::I1, uml::SIZE_WORD, uml::SPACE_PROGRAM); // write i0,i1,program_word
2060	1152	}
2061	1153	else
2062	1154	{
2063		UML_READ(block, I0, I0, SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word
	1155	UML_READ(block, uml::I0, uml::I0, uml::SIZE_WORD, uml::SPACE_PROGRAM); // read i0,i0,program_word
2064	1156	}
2065	1157	break;
2066	1158
2067	1159	case 4:
2068	1160	if (iswrite)
2069	1161	{
2070		UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword
	1162	UML_WRITE(block, uml::I0, uml::I1, uml::SIZE_DWORD, uml::SPACE_PROGRAM); // write i0,i1,program_dword
2071	1163	}
2072	1164	else
2073	1165	{
2074		UML_READ(block, I0, I0, SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword
	1166	UML_READ(block, uml::I0, uml::I0, uml::SIZE_DWORD, uml::SPACE_PROGRAM); // read i0,i0,program_dword
2075	1167	}
2076	1168	break;
2077	1169	}
r24074	r24075
2090	1182	an exception if out
2091	1183	-------------------------------------------------*/
2092	1184
2093		~~static~~ void generate_update_cycles(~~arm_state arm,~~ drcuml_block block, compiler_state *compiler, parameter param)
	1185	void arm7_cpu_device::generate_update_cycles(drcuml_block block, compiler_state compiler, uml::parameter param)
2094	1186	{
2095	1187	/* check full interrupts if pending */
2096	1188	if (compiler->checkints)
2097	1189	{
2098		code_label skip;
	1190	uml::code_label skip;
2099	1191
2100	1192	compiler->checkints = FALSE;
2101		UML_CALLH(block, *arm->impstate->check_irq);
	1193	UML_CALLH(block, *m_impstate.check_irq);
2102	1194	}
2103	1195
2104	1196	/* account for cycles */
2105	1197	if (compiler->cycles > 0)
2106	1198	{
2107		UML_SUB(block, mem(&arm->icount), mem(&arm->icount), MAPVAR_CYCLES); // sub icount,icount,cycles
	1199	UML_SUB(block, uml::mem(&m_icount), uml::mem(&m_icount), MAPVAR_CYCLES); // sub icount,icount,cycles
2108	1200	UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0
2109		UML_EXHc(block, COND_S, *arm->impstate->out_of_cycles, param); // exh out_of_cycles,nextpc
	1201	UML_EXHc(block, uml::COND_S, *m_impstate.out_of_cycles, param); // exh out_of_cycles,nextpc
2110	1202	}
2111	1203	compiler->cycles = 0;
2112	1204	}
r24074	r24075
2117	1209	validate a sequence of opcodes
2118	1210	-------------------------------------------------*/
2119	1211
2120		~~static~~ void generate_checksum_block(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc seqhead, const opcode_desc *seqlast)
	1212	void arm7_cpu_device::generate_checksum_block(drcuml_block block, compiler_state compiler, const opcode_desc seqhead, const opcode_desc seqlast)
2121	1213	{
2122	1214	const opcode_desc *curdesc;
2123	1215	if (LOG_UML)
r24074	r24075
2126	1218	}
2127	1219
2128	1220	/* loose verify or single instruction: just compare and fail */
2129		if (!(arm->impstate->drcoptions & ARM7DRC_STRICT_VERIFY) \|\| seqhead->next() == NULL)
	1221	if (!(m_impstate.drcoptions & ARM7DRC_STRICT_VERIFY) \|\| seqhead->next() == NULL)
2130	1222	{
2131	1223	if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP))
2132	1224	{
2133	1225	UINT32 sum = seqhead->opptr.l[0];
2134		void *base = arm->direct->read_decrypted_ptr(seqhead->physpc);
2135		UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword
	1226	void *base = m_direct->read_decrypted_ptr(seqhead->physpc);
	1227	UML_LOAD(block, uml::I0, base, 0, uml::SIZE_DWORD, uml::SCALE_x4); // load i0,base,0,dword
2136	1228
2137	1229	if (seqhead->delay.first() != NULL && seqhead->physpc != seqhead->delay.first()->physpc)
2138	1230	{
2139		base = arm->direct->read_decrypted_ptr(seqhead->delay.first()->physpc);
2140		UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword
2141		UML_ADD(block, I0, I0, I1); // add i0,i0,i1
	1231	base = m_direct->read_decrypted_ptr(seqhead->delay.first()->physpc);
	1232	UML_LOAD(block, uml::I1, base, 0, uml::SIZE_DWORD, uml::SCALE_x4); // load i1,base,dword
	1233	UML_ADD(block, uml::I0, uml::I0, uml::I1); // add i0,i0,i1
2142	1234
2143	1235	sum += seqhead->delay.first()->opptr.l[0];
2144	1236	}
2145	1237
2146		UML_CMP(block, I0, sum); // cmp i0,opptr[0]
2147		UML_EXHc(block, COND_NE, *arm->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc
	1238	UML_CMP(block, uml::I0, sum); // cmp i0,opptr[0]
	1239	UML_EXHc(block, uml::COND_NE, *m_impstate.nocode, epc(seqhead)); // exne nocode,seqhead->pc
2148	1240	}
2149	1241	}
2150	1242
r24074	r24075
2152	1244	else
2153	1245	{
2154	1246	UINT32 sum = 0;
2155		void *base = arm->direct->read_decrypted_ptr(seqhead->physpc);
2156		UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword
	1247	void *base = m_direct->read_decrypted_ptr(seqhead->physpc);
	1248	UML_LOAD(block, uml::I0, base, 0, uml::SIZE_DWORD, uml::SCALE_x4); // load i0,base,0,dword
2157	1249	sum += seqhead->opptr.l[0];
2158	1250	for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next())
2159	1251	if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP))
2160	1252	{
2161		base = arm->direct->read_decrypted_ptr(curdesc->physpc);
2162		UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword
2163		UML_ADD(block, I0, I0, I1); // add i0,i0,i1
	1253	base = m_direct->read_decrypted_ptr(curdesc->physpc);
	1254	UML_LOAD(block, uml::I1, base, 0, uml::SIZE_DWORD, uml::SCALE_x4); // load i1,base,dword
	1255	UML_ADD(block, uml::I0, uml::I0, uml::I1); // add i0,i0,i1
2164	1256	sum += curdesc->opptr.l[0];
2165	1257
2166	1258	if (curdesc->delay.first() != NULL && (curdesc == seqlast \|\| (curdesc->next() != NULL && curdesc->next()->physpc != curdesc->delay.first()->physpc)))
2167	1259	{
2168		base = arm->direct->read_decrypted_ptr(curdesc->delay.first()->physpc);
2169		UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword
2170		UML_ADD(block, I0, I0, I1); // add i0,i0,i1
	1260	base = m_direct->read_decrypted_ptr(curdesc->delay.first()->physpc);
	1261	UML_LOAD(block, uml::I1, base, 0, uml::SIZE_DWORD, uml::SCALE_x4); // load i1,base,dword
	1262	UML_ADD(block, uml::I0, uml::I0, uml::I1); // add i0,i0,i1
2171	1263	sum += curdesc->delay.first()->opptr.l[0];
2172	1264	}
2173	1265	}
2174		UML_CMP(block, I0, sum); // cmp i0,sum
2175		UML_EXHc(block, COND_NE, *arm->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc
	1266	UML_CMP(block, uml::I0, sum); // cmp i0,sum
	1267	UML_EXHc(block, uml::COND_NE, *m_impstate.nocode, epc(seqhead)); // exne nocode,seqhead->pc
2176	1268	}
2177	1269	}
2178	1270
r24074	r24075
2182	1274	for a single instruction in a sequence
2183	1275	-------------------------------------------------*/
2184	1276
2185		~~static~~ void generate_sequence_instruction(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1277	void arm7_cpu_device::generate_sequence_instruction(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
2186	1278	{
2187		offs_t expc;
	1279	//offs_t expc;
2188	1280	int hotnum;
2189	1281
2190	1282	/* add an entry for the log */
2191		if (LOG_UML && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
2192		log_add_disasm_comment(arm, block, desc->pc, desc->opptr.l[0]);
	1283	// TODO FIXME
	1284	// if (LOG_UML && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
	1285	// log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]);
2193	1286
2194	1287	/* set the PC map variable */
2195	1288	//expc = (desc->flags & OPFLAG_IN_DELAY_SLOT) ? desc->pc - 3 : desc->pc;
r24074	r24075
2202	1295	UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
2203	1296
2204	1297	/* is this a hotspot? */
2205		for (hotnum = 0; hotnum < M~~IPS3~~_MAX_HOTSPOTS; hotnum++)
	1298	for (hotnum = 0; hotnum < ARM7_MAX_HOTSPOTS; hotnum++)
2206	1299	{
2207		if (arm->impstate->hotspot[hotnum].pc != 0 && desc->pc == arm->impstate->hotspot[hotnum].pc && desc->opptr.l[0] == arm->impstate->hotspot[hotnum].opcode)
	1300	if (m_impstate.hotspot[hotnum].pc != 0 && desc->pc == m_impstate.hotspot[hotnum].pc && desc->opptr.l[0] == m_impstate.hotspot[hotnum].opcode)
2208	1301	{
2209		compiler->cycles += arm->impstate->hotspot[hotnum].cycles;
	1302	compiler->cycles += m_impstate.hotspot[hotnum].cycles;
2210	1303	break;
2211	1304	}
2212	1305	}
r24074	r24075
2215	1308	UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
2216	1309
2217	1310	/* if we are debugging, call the debugger */
2218		if ((~~arm->device->~~machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	1311	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
2219	1312	{
2220		UML_MOV(block, mem(&R15), desc->pc); // mov [pc],desc->pc
2221		save_fast_iregs(arm, block);
	1313	UML_MOV(block, uml::mem(&R15), desc->pc); // mov [pc],desc->pc
	1314	save_fast_iregs(block);
2222	1315	UML_DEBUG(block, desc->pc); // debug desc->pc
2223	1316	}
2224	1317
2225	1318	/* if we hit an unmapped address, fatal error */
2226	1319	if (desc->flags & OPFLAG_COMPILER_UNMAPPED)
2227	1320	{
2228		UML_MOV(block, mem(&R15), desc->pc); // mov R15,desc->pc
2229		save_fast_iregs(arm, block);
	1321	UML_MOV(block, uml::mem(&R15), desc->pc); // mov R15,desc->pc
	1322	save_fast_iregs(block);
2230	1323	UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE
2231	1324	}
2232	1325
r24074	r24075
2234	1327	else if (!(desc->flags & OPFLAG_VIRTUAL_NOOP))
2235	1328	{
2236	1329	/* compile the instruction */
2237		if (!generate_opcode(~~arm,~~ block, compiler, desc))
	1330	if (!generate_opcode(block, compiler, desc))
2238	1331	{
2239		UML_MOV(block, mem(&R15), desc->pc); // mov R15,desc->pc
2240		UML_MOV(block, mem(&arm->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
2241		UML_CALLC(block, cfunc_unimplemented, arm); // callc cfunc_unimplemented
	1332	UML_MOV(block, uml::mem(&R15), desc->pc); // mov R15,desc->pc
	1333	UML_MOV(block, uml::mem(&m_impstate.arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
	1334	//UML_CALLC(block, cfunc_unimplemented, arm); // callc cfunc_unimplemented // TODO FIXME
2242	1335	}
2243	1336	}
2244	1337	}
r24074	r24075
2248	1341	generate_delay_slot_and_branch
2249	1342	------------------------------------------------------------------*/
2250	1343
2251		~~static~~ void generate_delay_slot_and_branch(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc, UINT8 linkreg)
	1344	void arm7_cpu_device::generate_delay_slot_and_branch(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT8 linkreg)
2252	1345	{
2253	1346	compiler_state compiler_temp = *compiler;
2254		UINT32 op = desc->opptr.l[0];
2255	1347
2256	1348	/* update the cycles and jump through the hash table to the target */
2257	1349	if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
2258	1350	{
2259		generate_update_cycles(arm, block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles>
2260		UML_HASHJMP(block, 0, desc->targetpc, *arm->impstate->nocode);
	1351	generate_update_cycles(block, &compiler_temp, desc->targetpc); // <subtract cycles>
	1352	UML_HASHJMP(block, 0, desc->targetpc, *m_impstate.nocode);
2261	1353	// hashjmp 0,desc->targetpc,nocode
2262	1354	}
2263	1355	else
2264	1356	{
2265		generate_update_cycles(~~arm,~~ block, &compiler_temp, mem(&arm->impstate->jmpdest)~~, TRUE~~);
	1357	generate_update_cycles(block, &compiler_temp, uml::mem(&m_impstate.jmpdest));
2266	1358	// <subtract cycles>
2267		UML_HASHJMP(block, 0, mem(&arm->impstate->jmpdest), *arm->impstate->nocode);// hashjmp 0,<rsreg>,nocode
	1359	UML_HASHJMP(block, 0, uml::mem(&m_impstate.jmpdest), *m_impstate.nocode);// hashjmp 0,<rsreg>,nocode
2268	1360	}
2269	1361
2270	1362	/* update the label */
r24074	r24075
2275	1367	UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
2276	1368	}
2277	1369
2278		typedef const bool (drcarm7ops_ophandler)(arm_state, drcuml_block, compiler_state, const opcode_desc*, UINT32);
2279	1370
2280		static drcarm7ops_ophandler drcops_handler[0x10] =
	1371	const arm7_cpu_device::drcarm7ops_ophandler arm7_cpu_device::drcops_handler[0x10] =
2281	1372	{
2282		drcarm7ops_0123, drcarm7ops_0123, drcarm7ops_0123, drcarm7ops_0123,
2283		drcarm7ops_4567, drcarm7ops_4567, drcarm7ops_4567, drcarm7ops_4567,
2284		drcarm7ops_89, drcarm7ops_89, drcarm7ops_ab, drcarm7ops_ab,
2285		drcarm7ops_cd, drcarm7ops_cd, drcarm7ops_e, drcarm7ops_f,
	1373	&arm7_cpu_device::drcarm7ops_0123, &arm7_cpu_device::drcarm7ops_0123, &arm7_cpu_device::drcarm7ops_0123, &arm7_cpu_device::drcarm7ops_0123,
	1374	&arm7_cpu_device::drcarm7ops_4567, &arm7_cpu_device::drcarm7ops_4567, &arm7_cpu_device::drcarm7ops_4567, &arm7_cpu_device::drcarm7ops_4567,
	1375	&arm7_cpu_device::drcarm7ops_89, &arm7_cpu_device::drcarm7ops_89, &arm7_cpu_device::drcarm7ops_ab, &arm7_cpu_device::drcarm7ops_ab,
	1376	&arm7_cpu_device::drcarm7ops_cd, &arm7_cpu_device::drcarm7ops_cd, &arm7_cpu_device::drcarm7ops_e, &arm7_cpu_device::drcarm7ops_f,
2286	1377	};
2287	1378
2288		~~INLINE~~ void saturate_qbit_overflow(~~arm_state arm,~~ drcuml_block block)
	1379	void arm7_cpu_device::saturate_qbit_overflow(drcuml_block *block)
2289	1380	{
2290		UML_MOV(block, I1, 0);
2291		UML_DCMP(block, I0, 0x000000007fffffffL);
2292		UML_MOVc(block, COND_G, I1, Q_MASK);
2293		UML_MOVc(block, COND_G, I0, 0x7fffffff);
2294		UML_DCMP(block, I0, 0xffffffff80000000L);
2295		UML_MOVc(block, COND_L, I1, Q_MASK);
2296		UML_MOVc(block, COND_L, I0, 0x80000000);
2297		UML_OR(block, DRC_CPSR, DRC_CPSR, I1);
	1381	UML_MOV(block, uml::I1, 0);
	1382	UML_DCMP(block, uml::I0, 0x000000007fffffffL);
	1383	UML_MOVc(block, uml::COND_G, uml::I1, Q_MASK);
	1384	UML_MOVc(block, uml::COND_G, uml::I0, 0x7fffffff);
	1385	UML_DCMP(block, uml::I0, 0xffffffff80000000L);
	1386	UML_MOVc(block, uml::COND_L, uml::I1, Q_MASK);
	1387	UML_MOVc(block, uml::COND_L, uml::I0, 0x80000000);
	1388	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
2298	1389	}
2299	1390
2300		~~const~~ bool drcarm7ops_0123(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc, UINT32 op)
	1391	bool arm7_cpu_device::drcarm7ops_0123(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 insn)
2301	1392	{
2302		code_label done;
	1393	uml::code_label done;
2303	1394	/* Branch and Exchange (BX) */
2304	1395	if ((insn & 0x0ffffff0) == 0x012fff10) // bits 27-4 == 000100101111111111110001
2305	1396	{
2306	1397	UML_MOV(block, DRC_PC, DRC_REG(insn & 0x0f));
2307	1398	UML_TEST(block, DRC_PC, 1);
2308		UML_JMPc(block, COND_Z, done = compiler->labelnum++);
	1399	UML_JMPc(block, uml::COND_Z, done = compiler->labelnum++);
2309	1400	UML_OR(block, DRC_CPSR, DRC_CPSR, T_MASK);
2310	1401	UML_AND(block, DRC_PC, DRC_PC, ~1);
2311	1402	}
r24074	r24075
2322	1413	UINT32 rm = insn&0xf;
2323	1414	UINT32 rn = (insn>>16)&0xf;
2324	1415	UINT32 rd = (insn>>12)&0xf;
2325		UML_DSEXT(block, I0, DRC_REG(rm), SIZE_DWORD);
2326		UML_DSEXT(block, I1, DRC_REG(rn), SIZE_DWORD);
2327		UML_DADD(block, I0, I0, I1);
2328		saturate_qbit_overflow(arm, block);
2329		UML_MOV(block, DRC_REG(rd), I0);
	1416	UML_DSEXT(block, uml::I0, DRC_REG(rm), uml::SIZE_DWORD);
	1417	UML_DSEXT(block, uml::I1, DRC_REG(rn), uml::SIZE_DWORD);
	1418	UML_DADD(block, uml::I0, uml::I0, uml::I1);
	1419	saturate_qbit_overflow(block);
	1420	UML_MOV(block, DRC_REG(rd), uml::I0);
2330	1421	UML_ADD(block, DRC_PC, DRC_PC, 4);
2331	1422	}
2332	1423	else if ((insn & 0x0ff000f0) == 0x01400050) // QDADD - v5
r24074	r24075
2335	1426	UINT32 rn = (insn>>16)&0xf;
2336	1427	UINT32 rd = (insn>>12)&0xf;
2337	1428
2338		UML_DSEXT(block, I1, DRC_REG(rn), SIZE_DWORD);
2339		UML_DADD(block, I0, I1, I1);
2340		saturate_qbit_overflow(arm, block);
	1429	UML_DSEXT(block, uml::I1, DRC_REG(rn), uml::SIZE_DWORD);
	1430	UML_DADD(block, uml::I0, uml::I1, uml::I1);
	1431	saturate_qbit_overflow(block);
2341	1432
2342		UML_DSEXT(block, I0, DRC_REG(rm), SIZE_DWORD);
2343		UML_DSEXT(block, I1, DRC_REG(rn), SIZE_DWORD);
2344		UML_DADD(block, I1, I1, I1);
2345		UML_DADD(block, I0, I0, I1);
2346		saturate_qbit_overflow(arm, block);
2347		UML_MOV(block, DRC_REG(rd), I0);
	1433	UML_DSEXT(block, uml::I0, DRC_REG(rm), uml::SIZE_DWORD);
	1434	UML_DSEXT(block, uml::I1, DRC_REG(rn), uml::SIZE_DWORD);
	1435	UML_DADD(block, uml::I1, uml::I1, uml::I1);
	1436	UML_DADD(block, uml::I0, uml::I0, uml::I1);
	1437	saturate_qbit_overflow(block);
	1438	UML_MOV(block, DRC_REG(rd), uml::I0);
2348	1439
2349	1440	UML_ADD(block, DRC_PC, DRC_PC, 4);
2350	1441	}
r24074	r24075
2354	1445	UINT32 rn = (insn>>16)&0xf;
2355	1446	UINT32 rd = (insn>>12)&0xf;
2356	1447
2357		UML_DSEXT(block, I0, DRC_REG(rm), SIZE_DWORD);
2358		UML_DSEXT(block, I1, DRC_REG(rn), SIZE_DWORD);
2359		UML_DSUB(block, I0, I0, I1);
2360		saturate_qbit_overflow(arm, block);
2361		UML_MOV(block, DRC_REG(rd), I0);
	1448	UML_DSEXT(block, uml::I0, DRC_REG(rm), uml::SIZE_DWORD);
	1449	UML_DSEXT(block, uml::I1, DRC_REG(rn), uml::SIZE_DWORD);
	1450	UML_DSUB(block, uml::I0, uml::I0, uml::I1);
	1451	saturate_qbit_overflow(block);
	1452	UML_MOV(block, DRC_REG(rd), uml::I0);
2362	1453	UML_ADD(block, DRC_PC, DRC_PC, 4);
2363	1454	}
2364	1455	else if ((insn & 0x0ff000f0) == 0x01600050) // QDSUB - v5
r24074	r24075
2367	1458	UINT32 rn = (insn>>16)&0xf;
2368	1459	UINT32 rd = (insn>>12)&0xf;
2369	1460
2370		UML_DSEXT(block, I1, DRC_REG(rn), SIZE_DWORD);
2371		UML_DADD(block, I0, I1, I1);
2372		saturate_qbit_overflow(arm, block);
	1461	UML_DSEXT(block, uml::I1, DRC_REG(rn), uml::SIZE_DWORD);
	1462	UML_DADD(block, uml::I0, uml::I1, uml::I1);
	1463	saturate_qbit_overflow(block);
2373	1464
2374		UML_DSEXT(block, I0, DRC_REG(rm), SIZE_DWORD);
2375		UML_DSEXT(block, I1, DRC_REG(rn), SIZE_DWORD);
2376		UML_DADD(block, I1, I1, I1);
2377		UML_DSUB(block, I0, I0, I1);
2378		saturate_qbit_overflow(arm, block);
2379		UML_MOV(block, DRC_REG(rd), I0);
	1465	UML_DSEXT(block, uml::I0, DRC_REG(rm), uml::SIZE_DWORD);
	1466	UML_DSEXT(block, uml::I1, DRC_REG(rn), uml::SIZE_DWORD);
	1467	UML_DADD(block, uml::I1, uml::I1, uml::I1);
	1468	UML_DSUB(block, uml::I0, uml::I0, uml::I1);
	1469	saturate_qbit_overflow(block);
	1470	UML_MOV(block, DRC_REG(rd), uml::I0);
2380	1471
2381	1472	UML_ADD(block, DRC_PC, DRC_PC, 4);
2382	1473	}
r24074	r24075
2387	1478	UINT32 rd = (insn>>16)&0xf;
2388	1479	UINT32 ra = (insn>>12)&0xf;
2389	1480
2390		UML_MOV(block, I0, DRC_REG(rm));
2391		UML_MOV(block, I1, DRC_REG(rn));
	1481	UML_MOV(block, uml::I0, DRC_REG(rm));
	1482	UML_MOV(block, uml::I1, DRC_REG(rn));
2392	1483
2393	1484	// select top and bottom halves of src1/src2 and sign extend if necessary
2394	1485	if (insn & 0x20)
2395	1486	{
2396		UML_SHR(block, I0, I0, 16);
	1487	UML_SHR(block, uml::I0, uml::I0, 16);
2397	1488	}
2398		UML_SEXT(block, I0, I0, SIZE_WORD);
	1489	UML_SEXT(block, uml::I0, uml::I0, uml::SIZE_WORD);
2399	1490
2400	1491	if (insn & 0x40)
2401	1492	{
2402		UML_SHR(block, I1, I1, 16);
	1493	UML_SHR(block, uml::I1, uml::I1, 16);
2403	1494	}
2404		UML_SEXT(block, I0, I0, SIZE_WORD);
	1495	UML_SEXT(block, uml::I0, uml::I0, uml::SIZE_WORD);
2405	1496
2406	1497	// do the signed multiply
2407		UML_MULS(block, I0, I1, I0, I1);
2408		UML_DSHL(block, I0, I0, 32);
2409		UML_DOR(block, I0, I0, I1);
2410		UML_MOV(block, I1, DRC_REG(ra));
2411		UML_DADD(block, I0, I0, I1);
	1498	UML_MULS(block, uml::I0, uml::I1, uml::I0, uml::I1);
	1499	UML_DSHL(block, uml::I0, uml::I0, 32);
	1500	UML_DOR(block, uml::I0, uml::I0, uml::I1);
	1501	UML_MOV(block, uml::I1, DRC_REG(ra));
	1502	UML_DADD(block, uml::I0, uml::I0, uml::I1);
2412	1503	// and the accumulate. NOTE: only the accumulate can cause an overflow, which is why we do it this way.
2413		saturate_qbit_overflow(arm, block);
2414		UML_MOV(block, DRC_REG(rd), I0);
	1504	saturate_qbit_overflow(block);
	1505	UML_MOV(block, DRC_REG(rd), uml::I0);
2415	1506	UML_ADD(block, DRC_PC, DRC_PC, 4);
2416	1507	}
2417	1508	else if ((insn & 0x0ff00090) == 0x01400080) // SMLALxy - v5
r24074	r24075
2421	1512	UINT32 rdh = (insn>>16)&0xf;
2422	1513	UINT32 rdl = (insn>>12)&0xf;
2423	1514
2424		UML_DSEXT(block, I0, DRC_REG(rm), SIZE_DWORD);
2425		UML_DSEXT(block, I1, DRC_REG(rn), SIZE_DWORD);
	1515	UML_DSEXT(block, uml::I0, DRC_REG(rm), uml::SIZE_DWORD);
	1516	UML_DSEXT(block, uml::I1, DRC_REG(rn), uml::SIZE_DWORD);
2426	1517	// do the signed multiply
2427		UML_DMULS(block, I2, I3, I0, I1);
	1518	UML_DMULS(block, uml::I2, uml::I3, uml::I0, uml::I1);
2428	1519
2429		UML_MOV(block, I0, DRC_REG(rdh));
2430		UML_MOV(block, I1, DRC_REG(rdl));
2431		UML_DSHL(block, I0, I0, 32);
2432		UML_DOR(block, I0, I0, I1);
2433		UML_DADD(block, I0, I0, I2);
2434		UML_MOV(block, DRC_REG(rdl), I0);
2435		UML_DSHR(block, I0, I0, 32);
2436		UML_MOV(block, DRC_REG(rdh), I0);
	1520	UML_MOV(block, uml::I0, DRC_REG(rdh));
	1521	UML_MOV(block, uml::I1, DRC_REG(rdl));
	1522	UML_DSHL(block, uml::I0, uml::I0, 32);
	1523	UML_DOR(block, uml::I0, uml::I0, uml::I1);
	1524	UML_DADD(block, uml::I0, uml::I0, uml::I2);
	1525	UML_MOV(block, DRC_REG(rdl), uml::I0);
	1526	UML_DSHR(block, uml::I0, uml::I0, 32);
	1527	UML_MOV(block, DRC_REG(rdh), uml::I0);
2437	1528	}
2438	1529	else if ((insn & 0x0ff00090) == 0x01600080) // SMULxy - v5
2439	1530	{
2440		INT32 src1 = GET_REGISTER(arm, insn&0xf);
2441		INT32 src2 = GET_REGISTER(arm, (insn>>8)&0xf);
	1531	INT32 src1 = GET_REGISTER(insn&0xf);
	1532	INT32 src2 = GET_REGISTER((insn>>8)&0xf);
2442	1533	INT32 res;
2443	1534
2444	1535	// select top and bottom halves of src1/src2 and sign extend if necessary
r24074	r24075
2465	1556	}
2466	1557
2467	1558	res = src1 * src2;
2468		SET_REGISTER(~~cpustart,~~ (insn>>16)&0xf, res);
	1559	SET_REGISTER((insn>>16)&0xf, res);
2469	1560	R15 += 4;
2470	1561	}
2471	1562	else if ((insn & 0x0ff000b0) == 0x012000a0) // SMULWy - v5
2472	1563	{
2473		INT32 src1 = GET_REGISTER(arm, insn&0xf);
2474		INT32 src2 = GET_REGISTER(arm, (insn>>8)&0xf);
	1564	INT32 src1 = GET_REGISTER(insn&0xf);
	1565	INT32 src2 = GET_REGISTER((insn>>8)&0xf);
2475	1566	INT64 res;
2476	1567
2477	1568	if (insn & 0x40)
r24074	r24075
2489	1580
2490	1581	res = (INT64)src1 * (INT64)src2;
2491	1582	res >>= 16;
2492		SET_REGISTER(~~cpustart,~~ (insn>>16)&0xf, (UINT32)res);
	1583	SET_REGISTER((insn>>16)&0xf, (UINT32)res);
2493	1584	}
2494	1585	else if ((insn & 0x0ff000b0) == 0x01200080) // SMLAWy - v5
2495	1586	{
2496		INT32 src1 = GET_REGISTER(arm, insn&0xf);
2497		INT32 src2 = GET_REGISTER(arm, (insn>>8)&0xf);
2498		INT32 src3 = GET_REGISTER(arm, (insn>>12)&0xf);
	1587	INT32 src1 = GET_REGISTER(insn&0xf);
	1588	INT32 src2 = GET_REGISTER((insn>>8)&0xf);
	1589	INT32 src3 = GET_REGISTER((insn>>12)&0xf);
2499	1590	INT64 res;
2500	1591
2501	1592	if (insn & 0x40)
r24074	r24075
2515	1606	res >>= 16;
2516	1607
2517	1608	// check for overflow and set the Q bit
2518		saturate_qbit_overflow(~~arm,~~ (INT64)src3 + res);
	1609	saturate_qbit_overflow((INT64)src3 + res);
2519	1610
2520	1611	// do the real accumulate
2521	1612	src3 += (INT32)res;
2522	1613
2523	1614	// write the result back
2524		SET_REGISTER(~~cpustart,~~ (insn>>16)&0xf, (UINT32)res);
	1615	SET_REGISTER((insn>>16)&0xf, (UINT32)res);
2525	1616	}
2526	1617	else
2527	1618	/* Multiply OR Swap OR Half Word Data Transfer */
r24074	r24075
2530	1621	/* Half Word Data Transfer */
2531	1622	if (insn & 0x60) // bits = 6-5 != 00
2532	1623	{
2533		HandleHalfWordDT(~~arm,~~ insn);
	1624	HandleHalfWordDT(insn);
2534	1625	}
2535	1626	else
2536	1627	/* Swap */
2537	1628	if (insn & 0x01000000) // bit 24 = 1
2538	1629	{
2539		HandleSwap(~~arm,~~ insn);
	1630	HandleSwap(insn);
2540	1631	}
2541	1632	/* Multiply Or Multiply Long */
2542	1633	else
r24074	r24075
2546	1637	{
2547	1638	/* Signed? */
2548	1639	if (insn & 0x00400000)
2549		HandleSMulLong(~~arm,~~ insn);
	1640	HandleSMulLong(insn);
2550	1641	else
2551		HandleUMulLong(~~arm,~~ insn);
	1642	HandleUMulLong(insn);
2552	1643	}
2553	1644	/* multiply */
2554	1645	else
2555	1646	{
2556		HandleMul(~~arm,~~ insn);
	1647	HandleMul(insn);
2557	1648	}
2558	1649	R15 += 4;
2559	1650	}
r24074	r24075
2564	1655	/* PSR Transfer (MRS & MSR) */
2565	1656	if (((insn & 0x00100000) == 0) && ((insn & 0x01800000) == 0x01000000)) // S bit must be clear, and bit 24,23 = 10
2566	1657	{
2567		HandlePSRTransfer(~~arm,~~ insn);
	1658	HandlePSRTransfer(insn);
2568	1659	ARM7_ICOUNT += 2; // PSR only takes 1 - S Cycle, so we add + 2, since at end, we -3..
2569	1660	R15 += 4;
2570	1661	}
2571	1662	/* Data Processing */
2572	1663	else
2573	1664	{
2574		HandleALU(~~arm,~~ insn);
	1665	HandleALU(insn);
2575	1666	}
2576	1667	}
2577	1668
r24074	r24075
2579	1670	return true;
2580	1671	}
2581	1672
2582		~~const~~ bool drcarm7ops_4567(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc, UINT32 op)
	1673	bool arm7_cpu_device::drcarm7ops_4567(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op)
2583	1674	{
	1675	return false;
2584	1676	}
2585	1677
2586		~~const~~ bool drcarm7ops_89(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc, UINT32 op)
	1678	bool arm7_cpu_device::drcarm7ops_89(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op)
2587	1679	{
	1680	return false;
2588	1681	}
2589	1682
2590		~~const~~ bool drcarm7ops_ab(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc, UINT32 op)
	1683	bool arm7_cpu_device::drcarm7ops_ab(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op)
2591	1684	{
	1685	return false;
2592	1686	}
2593	1687
2594		~~const~~ bool drcarm7ops_cd(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc, UINT32 op)
	1688	bool arm7_cpu_device::drcarm7ops_cd(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op)
2595	1689	{
	1690	return false;
2596	1691	}
2597	1692
2598		~~const~~ bool drcarm7ops_e(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc, UINT32 op)
	1693	bool arm7_cpu_device::drcarm7ops_e(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op)
2599	1694	{
	1695	return false;
2600	1696	}
2601	1697
2602		~~const~~ bool drcarm7ops_f(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc, UINT32 op)
	1698	bool arm7_cpu_device::drcarm7ops_f(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op)
2603	1699	{
	1700	return false;
2604	1701	}
2605	1702
2606	1703	/*-------------------------------------------------
r24074	r24075
2608	1705	opcode
2609	1706	-------------------------------------------------*/
2610	1707
2611		~~stat~~i~~c i~~nt generate_opcode(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1708	int arm7_cpu_device::generate_opcode(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
2612	1709	{
2613	1710	//int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
2614	1711	UINT32 op = desc->opptr.l[0];
2615	1712	UINT8 opswitch = op >> 26;
2616		code_label skip;
2617		code_label contdecode;
2618		code_label unexecuted;
	1713	uml::code_label skip;
	1714	uml::code_label contdecode;
	1715	uml::code_label unexecuted;
2619	1716
2620	1717	if (T_IS_SET(GET_CPSR))
2621	1718	{
2622	1719	// "In Thumb state, bit [0] is undefined and must be ignored. Bits [31:1] contain the PC."
2623		UML_AND(block, I0, DRC_PC, ~1);
	1720	UML_AND(block, uml::I0, DRC_PC, ~1);
2624	1721	}
2625	1722	else
2626	1723	{
2627		UML_AND(block, I0, DRC_PC, ~3);
	1724	UML_AND(block, uml::I0, DRC_PC, ~3);
2628	1725	}
2629	1726
2630		UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN
2631		UML_MOVc(block, COND_NZ, I2, ARM7_TLB_ABORT_P \| ARM7_TLB_READ); // movnz i0, ARM7_TLB_ABORT_P \| ARM7_TLB_READ
2632		UML_CALLHc(block, COND_NZ, *arm->impstate->tlb_translate); // callhnz tlb_translate);
	1727	UML_TEST(block, uml::mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN
	1728	UML_MOVc(block, uml::COND_NZ, uml::I2, ARM7_TLB_ABORT_P \| ARM7_TLB_READ); // movnz i0, ARM7_TLB_ABORT_P \| ARM7_TLB_READ
	1729	UML_CALLHc(block, uml::COND_NZ, *m_impstate.tlb_translate); // callhnz tlb_translate);
2633	1730
2634	1731	if (T_IS_SET(GET_CPSR))
2635	1732	{
2636		UML_CALLH(block, *arm->impstate->drcthumb[(op & 0xffc0) >> 6); // callh drcthumb[op]
	1733	//UML_CALLH(block, *m_impstate.drcthumb[(op & 0xffc0) >> 6]); // callh drcthumb[op] // TODO FIXME
2637	1734	return TRUE;
2638	1735	}
2639	1736
r24074	r24075
2641	1738	{
2642	1739	case COND_EQ:
2643	1740	UML_TEST(block, DRC_CPSR, Z_MASK);
2644		UML_JMPc(block, COND_Z, unexecuted = compiler->labelnum++);
	1741	UML_JMPc(block, uml::COND_Z, unexecuted = compiler->labelnum++);
2645	1742	break;
2646	1743	case COND_NE:
2647	1744	UML_TEST(block, DRC_CPSR, Z_MASK);
2648		UML_JMPc(block, COND_NZ, unexecuted = compiler->labelnum++);
	1745	UML_JMPc(block, uml::COND_NZ, unexecuted = compiler->labelnum++);
2649	1746	break;
2650	1747	case COND_CS:
2651	1748	UML_TEST(block, DRC_CPSR, C_MASK);
2652		UML_JMPc(block, COND_Z, unexecuted = compiler->labelnum++);
	1749	UML_JMPc(block, uml::COND_Z, unexecuted = compiler->labelnum++);
2653	1750	break;
2654	1751	case COND_CC:
2655	1752	UML_TEST(block, DRC_CPSR, C_MASK);
2656		UML_JMPc(block, COND_NZ, unexecuted = compiler->labelnum++);
	1753	UML_JMPc(block, uml::COND_NZ, unexecuted = compiler->labelnum++);
2657	1754	break;
2658	1755	case COND_MI:
2659	1756	UML_TEST(block, DRC_CPSR, N_MASK);
2660		UML_JMPc(block, COND_Z, unexecuted = compiler->labelnum++);
	1757	UML_JMPc(block, uml::COND_Z, unexecuted = compiler->labelnum++);
2661	1758	break;
2662	1759	case COND_PL:
2663	1760	UML_TEST(block, DRC_CPSR, N_MASK);
2664		UML_JMPc(block, COND_NZ, unexecuted = compiler->labelnum++);
	1761	UML_JMPc(block, uml::COND_NZ, unexecuted = compiler->labelnum++);
2665	1762	break;
2666	1763	case COND_VS:
2667	1764	UML_TEST(block, DRC_CPSR, V_MASK);
2668		UML_JMPc(block, COND_Z, unexecuted = compiler->labelnum++);
	1765	UML_JMPc(block, uml::COND_Z, unexecuted = compiler->labelnum++);
2669	1766	break;
2670	1767	case COND_VC:
2671	1768	UML_TEST(block, DRC_CPSR, V_MASK);
2672		UML_JMPc(block, COND_NZ, unexecuted = compiler->labelnum++);
	1769	UML_JMPc(block, uml::COND_NZ, unexecuted = compiler->labelnum++);
2673	1770	break;
2674	1771	case COND_HI:
2675	1772	UML_TEST(block, DRC_CPSR, Z_MASK);
2676		UML_JMPc(block, COND_NZ, unexecuted = compiler->labelnum++);
	1773	UML_JMPc(block, uml::COND_NZ, unexecuted = compiler->labelnum++);
2677	1774	UML_TEST(block, DRC_CPSR, C_MASK);
2678		UML_JMPc(block, COND_Z, unexecuted = compiler->labelnum++);
	1775	UML_JMPc(block, uml::COND_Z, unexecuted = compiler->labelnum++);
2679	1776	break;
2680	1777	case COND_LS:
2681	1778	UML_TEST(block, DRC_CPSR, Z_MASK);
2682		UML_JMPc(block, COND_NZ, contdecode = compiler->labelnum++);
	1779	UML_JMPc(block, uml::COND_NZ, contdecode = compiler->labelnum++);
2683	1780	UML_TEST(block, DRC_CPSR, C_MASK);
2684		UML_JMPc(block, COND_Z, contdecode);
	1781	UML_JMPc(block, uml::COND_Z, contdecode);
2685	1782	UML_JMP(block, unexecuted);
2686	1783	break;
2687	1784	case COND_GE:
2688	1785	UML_TEST(block, DRC_CPSR, N_MASK);
2689		UML_MOVc(block, COND_Z, I0, 0);
2690		UML_MOVc(block, COND_NZ, I0, 1);
	1786	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
	1787	UML_MOVc(block, uml::COND_NZ, uml::I0, 1);
2691	1788	UML_TEST(block, DRC_CPSR, V_MASK);
2692		UML_MOVc(block, COND_Z, I1, 0);
2693		UML_MOVc(block, COND_NZ, I1, 1);
2694		UML_CMP(block, I0, I1);
2695		UML_JMPc(block, COND_NE, unexecuted);
	1789	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1790	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1791	UML_CMP(block, uml::I0, uml::I1);
	1792	UML_JMPc(block, uml::COND_NE, unexecuted);
2696	1793	break;
2697	1794	case COND_LT:
2698	1795	UML_TEST(block, DRC_CPSR, N_MASK);
2699		UML_MOVc(block, COND_Z, I0, 0);
2700		UML_MOVc(block, COND_NZ, I0, 1);
	1796	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
	1797	UML_MOVc(block, uml::COND_NZ, uml::I0, 1);
2701	1798	UML_TEST(block, DRC_CPSR, V_MASK);
2702		UML_MOVc(block, COND_Z, I1, 0);
2703		UML_MOVc(block, COND_NZ, I1, 1);
2704		UML_CMP(block, I0, I1);
2705		UML_JMPc(block, COND_E, unexecuted);
	1799	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1800	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1801	UML_CMP(block, uml::I0, uml::I1);
	1802	UML_JMPc(block, uml::COND_E, unexecuted);
2706	1803	break;
2707	1804	case COND_GT:
2708	1805	UML_TEST(block, DRC_CPSR, Z_MASK);
2709		UML_JMPc(block, COND_NZ, unexecuted);
	1806	UML_JMPc(block, uml::COND_NZ, unexecuted);
2710	1807	UML_TEST(block, DRC_CPSR, N_MASK);
2711		UML_MOVc(block, COND_Z, I0, 0);
2712		UML_MOVc(block, COND_NZ, I0, 1);
	1808	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
	1809	UML_MOVc(block, uml::COND_NZ, uml::I0, 1);
2713	1810	UML_TEST(block, DRC_CPSR, V_MASK);
2714		UML_MOVc(block, COND_Z, I1, 0);
2715		UML_MOVc(block, COND_NZ, I1, 1);
2716		UML_CMP(block, I0, I1);
2717		UML_JMPc(block, COND_NE, unexecuted);
	1811	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1812	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1813	UML_CMP(block, uml::I0, uml::I1);
	1814	UML_JMPc(block, uml::COND_NE, unexecuted);
2718	1815	break;
2719	1816	case COND_LE:
2720	1817	UML_TEST(block, DRC_CPSR, N_MASK);
2721		UML_MOVc(block, COND_Z, I0, 0);
2722		UML_MOVc(block, COND_NZ, I0, 1);
	1818	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
	1819	UML_MOVc(block, uml::COND_NZ, uml::I0, 1);
2723	1820	UML_TEST(block, DRC_CPSR, V_MASK);
2724		UML_MOVc(block, COND_Z, I1, 0);
2725		UML_MOVc(block, COND_NZ, I1, 1);
2726		UML_CMP(block, I0, I1);
2727		UML_JMPc(block, COND_NE, contdecode);
	1821	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1822	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1823	UML_CMP(block, uml::I0, uml::I1);
	1824	UML_JMPc(block, uml::COND_NE, contdecode);
2728	1825	UML_TEST(block, DRC_CPSR, Z_MASK);
2729		UML_JMPc(block, COND_Z, unexecuted);
	1826	UML_JMPc(block, uml::COND_Z, unexecuted);
2730	1827	break;
2731	1828	case COND_NV:
2732	1829	UML_JMP(block, unexecuted);
r24074	r24075
2735	1832
2736	1833	UML_LABEL(block, contdecode);
2737	1834
2738		drcops_handler[(op & 0xF000000) >> 24](~~arm,~~ block, compiler, desc);
	1835	(this->*drcops_handler[(op & 0xF000000) >> 24])(block, compiler, desc, op);
2739	1836
2740	1837	UML_LABEL(block, unexecuted);
2741	1838	UML_ADD(block, DRC_PC, DRC_PC, 4);
r24074	r24075
2748	1845	/* ----- sub-groups ----- */
2749	1846
2750	1847	case 0x00: /* SPECIAL - MIPS I */
2751		UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
2752		UML_JMPc(block, COND_NE, skip = compiler->labelnum++); // jmp skip,NE
2753		generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp>
2754		UML_LABEL(block, skip); // skip:
2755	1848	return TRUE;
2756	1849
2757		DEFINE_LEGACY_CPU_DEVICE(ARM7, arm7);
2758		DEFINE_LEGACY_CPU_DEVICE(ARM7_BE, arm7_be);
2759		DEFINE_LEGACY_CPU_DEVICE(ARM7500, arm7500);
2760		DEFINE_LEGACY_CPU_DEVICE(ARM9, arm9);
2761		DEFINE_LEGACY_CPU_DEVICE(ARM920T, arm920t);
2762		DEFINE_LEGACY_CPU_DEVICE(PXA255, pxa255);
2763		DEFINE_LEGACY_CPU_DEVICE(SA1110, sa1110);
	1850	// TODO: FINISH ME
	1851	}
2764	1852
2765		#endif // ARM7_USE_DRC
	1853	return FALSE;
	1854	}

trunk/src/emu/cpu/arm7/arm7core.c
r24074	r24075
77	77	*****************************************************************************/
78	78
79	79
80		/* Prototypes */
81
82
83		extern UINT32 decodeShift(arm_state arm, UINT32 insn, UINT32 pCarry);
84
85		void arm7_check_irq_state(arm_state *arm);
86
87
88		/* Static Vars */
89		// Note: for multi-cpu implementation, this approach won't work w/o modification
90		write32_device_func arm7_coproc_do_callback; // holder for the co processor Data Operations Callback func.
91		read32_device_func arm7_coproc_rt_r_callback; // holder for the co processor Register Transfer Read Callback func.
92		write32_device_func arm7_coproc_rt_w_callback; // holder for the co processor Register Transfer Write Callback Callback func.
93
94		#ifdef UNUSED_DEFINITION
95		// custom dasm callback handlers for co-processor instructions
96		char (arm7_dasm_cop_dt_callback)(arm_state arm, char pBuf, UINT32 opcode, char pConditionCode, char pBuf0);
97		char (arm7_dasm_cop_rt_callback)(arm_state arm, char pBuf, UINT32 opcode, char pConditionCode, char pBuf0);
98		char (arm7_dasm_cop_do_callback)(arm_state arm, char pBuf, UINT32 opcode, char pConditionCode, char pBuf0);
99		#endif
100
101
102	80	// convert cpsr mode num into to text
103	81	static const char modetext[ARM7_NUM_MODES][5] = {
104	82	"USER", "FIRQ", "IRQ", "SVC", "ILL1", "ILL2", "ILL3", "ABT",
r24074	r24075
116	94	* Main CPU Funcs
117	95	***************************************************************************/
118	96
119		// CPU INIT
120		static void arm7_core_init(device_t device, const char cpuname)
121		{
122		arm_state *arm = get_safe_token(device);
123
124		device->save_item(NAME(arm->r));
125		device->save_item(NAME(arm->pendingIrq));
126		device->save_item(NAME(arm->pendingFiq));
127		device->save_item(NAME(arm->pendingAbtD));
128		device->save_item(NAME(arm->pendingAbtP));
129		device->save_item(NAME(arm->pendingUnd));
130		device->save_item(NAME(arm->pendingSwi));
131		}
132
133		// CPU RESET
134		static void arm7_core_reset(legacy_cpu_device *device)
135		{
136		arm_state *arm = get_safe_token(device);
137
138		device_irq_acknowledge_callback save_irqcallback = arm->irq_callback;
139
140		memset(arm, 0, sizeof(arm_state));
141		arm->irq_callback = save_irqcallback;
142		arm->device = device;
143		arm->program = &device->space(AS_PROGRAM);
144		arm->endian = ENDIANNESS_LITTLE;
145		arm->direct = &arm->program->direct();
146
147		/* start up in SVC mode with interrupts disabled. */
148		ARM7REG(eCPSR) = I_MASK \| F_MASK \| 0x10;
149		SwitchMode(arm, eARM7_MODE_SVC);
150		R15 = 0;
151		}
152
153	97	// CPU CHECK IRQ STATE
154	98	// Note: couldn't find any exact cycle counts for most of these exceptions
155		void arm7_check_irq_state(~~arm_state *arm~~)
	99	void arm7_cpu_device::arm7_check_irq_state()
156	100	{
157		UINT32 cpsr = GET_CPSR; /* save current CPSR */
158		UINT32 pc = R15 + 4; /* save old pc (already incremented in pipeline) */;
	101	UINT32 cpsr = m_r[eCPSR]; /* save current CPSR */
	102	UINT32 pc = m_r[eR15] + 4; /* save old pc (already incremented in pipeline) */;
159	103
160	104	/* Exception priorities:
161	105
r24074	r24075
169	113	*/
170	114
171	115	// Data Abort
172		if (arm->pendingAbtD) {
	116	if (m_pendingAbtD) {
173	117	if (MODE26) fatalerror( "pendingAbtD (todo)\n");
174		SwitchMode(arm, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
175		SET_REGISTER(arm, 14, pc - 8 + 8); /* save PC to R14 */
176		SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
	118	SwitchMode(eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
	119	SET_REGISTER(14, pc - 8 + 8); /* save PC to R14 */
	120	SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
177	121	SET_CPSR(GET_CPSR \| I_MASK); /* Mask IRQ */
178	122	SET_CPSR(GET_CPSR & ~T_MASK);
179	123	R15 = 0x10; /* IRQ Vector address */
180	124	if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 \|= 0xFFFF0000;
181		arm->pendingAbtD = 0;
	125	m_pendingAbtD = 0;
182	126	return;
183	127	}
184	128
185	129	// FIQ
186		if (arm->pendingFiq && (cpsr & F_MASK) == 0) {
	130	if (m_pendingFiq && (cpsr & F_MASK) == 0) {
187	131	if (MODE26) fatalerror( "pendingFiq (todo)\n");
188		SwitchMode(arm, eARM7_MODE_FIQ); /* Set FIQ mode so PC is saved to correct R14 bank */
189		SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
190		SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
	132	SwitchMode(eARM7_MODE_FIQ); /* Set FIQ mode so PC is saved to correct R14 bank */
	133	SET_REGISTER(14, pc - 4 + 4); /* save PC to R14 */
	134	SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
191	135	SET_CPSR(GET_CPSR \| I_MASK \| F_MASK); /* Mask both IRQ & FIQ */
192	136	SET_CPSR(GET_CPSR & ~T_MASK);
193	137	R15 = 0x1c; /* IRQ Vector address */
r24074	r24075
196	140	}
197	141
198	142	// IRQ
199		if (arm->pendingIrq && (cpsr & I_MASK) == 0) {
200		SwitchMode(arm, eARM7_MODE_IRQ); /* Set IRQ mode so PC is saved to correct R14 bank */
201		SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
	143	if (m_pendingIrq && (cpsr & I_MASK) == 0) {
	144	SwitchMode(eARM7_MODE_IRQ); /* Set IRQ mode so PC is saved to correct R14 bank */
	145	SET_REGISTER(14, pc - 4 + 4); /* save PC to R14 */
202	146	if (MODE32)
203	147	{
204		SET_REGISTER(~~arm,~~ SPSR, cpsr); /* Save current CPSR */
	148	SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
205	149	SET_CPSR(GET_CPSR \| I_MASK); /* Mask IRQ */
206	150	SET_CPSR(GET_CPSR & ~T_MASK);
207	151	R15 = 0x18; /* IRQ Vector address */
r24074	r24075
218	162	}
219	163
220	164	// Prefetch Abort
221		if (arm->pendingAbtP) {
	165	if (m_pendingAbtP) {
222	166	if (MODE26) fatalerror( "pendingAbtP (todo)\n");
223		SwitchMode(arm, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
224		SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
225		SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
	167	SwitchMode(eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
	168	SET_REGISTER(14, pc - 4 + 4); /* save PC to R14 */
	169	SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
226	170	SET_CPSR(GET_CPSR \| I_MASK); /* Mask IRQ */
227	171	SET_CPSR(GET_CPSR & ~T_MASK);
228	172	R15 = 0x0c; /* IRQ Vector address */
229	173	if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 \|= 0xFFFF0000;
230		arm->pendingAbtP = 0;
	174	m_pendingAbtP = 0;
231	175	return;
232	176	}
233	177
234	178	// Undefined instruction
235		if (arm->pendingUnd) {
	179	if (m_pendingUnd) {
236	180	if (MODE26) fatalerror( "pendingUnd (todo)\n");
237		SwitchMode(~~arm,~~ eARM7_MODE_UND); /* Set UND mode so PC is saved to correct R14 bank */
	181	SwitchMode(eARM7_MODE_UND); /* Set UND mode so PC is saved to correct R14 bank */
238	182	// compensate for prefetch (should this also be done for normal IRQ?)
239	183	if (T_IS_SET(GET_CPSR))
240	184	{
241		SET_REGISTER(~~arm,~~ 14, pc - 4 + 2); /* save PC to R14 */
	185	SET_REGISTER(14, pc - 4 + 2); /* save PC to R14 */
242	186	}
243	187	else
244	188	{
245		SET_REGISTER(~~arm,~~ 14, pc - 4 + 4 - 4); /* save PC to R14 */
	189	SET_REGISTER(14, pc - 4 + 4 - 4); /* save PC to R14 */
246	190	}
247		SET_REGISTER(~~arm,~~ SPSR, cpsr); /* Save current CPSR */
	191	SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
248	192	SET_CPSR(GET_CPSR \| I_MASK); /* Mask IRQ */
249	193	SET_CPSR(GET_CPSR & ~T_MASK);
250	194	R15 = 0x04; /* IRQ Vector address */
251	195	if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 \|= 0xFFFF0000;
252		arm->pendingUnd = 0;
	196	m_pendingUnd = 0;
253	197	return;
254	198	}
255	199
256	200	// Software Interrupt
257		if (arm->pendingSwi) {
258		SwitchMode(arm, eARM7_MODE_SVC); /* Set SVC mode so PC is saved to correct R14 bank */
	201	if (m_pendingSwi) {
	202	SwitchMode(eARM7_MODE_SVC); /* Set SVC mode so PC is saved to correct R14 bank */
259	203	// compensate for prefetch (should this also be done for normal IRQ?)
260	204	if (T_IS_SET(GET_CPSR))
261	205	{
262		SET_REGISTER(~~arm,~~ 14, pc - 4 + 2); /* save PC to R14 */
	206	SET_REGISTER(14, pc - 4 + 2); /* save PC to R14 */
263	207	}
264	208	else
265	209	{
266		SET_REGISTER(~~arm,~~ 14, pc - 4 + 4); /* save PC to R14 */
	210	SET_REGISTER(14, pc - 4 + 4); /* save PC to R14 */
267	211	}
268	212	if (MODE32)
269	213	{
270		SET_REGISTER(~~arm,~~ SPSR, cpsr); /* Save current CPSR */
	214	SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
271	215	SET_CPSR(GET_CPSR \| I_MASK); /* Mask IRQ */
272	216	SET_CPSR(GET_CPSR & ~T_MASK); /* Go to ARM mode */
273	217	R15 = 0x08; /* Jump to the SWI vector */
r24074	r24075
280	224	SET_CPSR(temp); /* Mask IRQ */
281	225	}
282	226	if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 \|= 0xFFFF0000;
283		arm->pendingSwi = 0;
	227	m_pendingSwi = 0;
284	228	return;
285	229	}
286	230	}
287	231
288		// CPU - SET IRQ LINE
289		static void arm7_core_set_irq_line(arm_state *arm, int irqline, int state)
290		{
291		switch (irqline) {
292		case ARM7_IRQ_LINE: /* IRQ */
293		arm->pendingIrq = state & 1;
294		break;
295
296		case ARM7_FIRQ_LINE: /* FIRQ */
297		arm->pendingFiq = state & 1;
298		break;
299
300		case ARM7_ABORT_EXCEPTION:
301		arm->pendingAbtD = state & 1;
302		break;
303		case ARM7_ABORT_PREFETCH_EXCEPTION:
304		arm->pendingAbtP = state & 1;
305		break;
306
307		case ARM7_UNDEFINE_EXCEPTION:
308		arm->pendingUnd = state & 1;
309		break;
310		}
311
312		ARM7_CHECKIRQ;
313		}

trunk/src/emu/cpu/arm7/arm7thmb.c
r24074	r24075
1	1	#include "emu.h"
	2	#include "arm7.h"
2	3	#include "arm7core.h"
3		#include "arm7thmb.h"
4	4	#include "arm7help.h"
5	5
6	6	// this is our master dispatch jump table for THUMB mode, representing [(INSN & 0xffc0) >> 6] bits of the 16-bit decoded instruction
7		arm7thumb_ophandler thumb_handler[0x40*0x10] =
	7	const arm7_cpu_device::arm7thumb_ophandler arm7_cpu_device::thumb_handler[0x40*0x10] =
8	8	{
9	9	// #define THUMB_SHIFT_R ((UINT16)0x0800)
10		tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0, tg00_0,
11		tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1, tg00_1,
	10	&arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0,
	11	&arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0,
	12	&arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0,
	13	&arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0,
	14	&arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0,
	15	&arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0,
	16	&arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0,
	17	&arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0, &arm7_cpu_device::tg00_0,
	18	&arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1,
	19	&arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1,
	20	&arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1,
	21	&arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1,
	22	&arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1,
	23	&arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1,
	24	&arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1,
	25	&arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1, &arm7_cpu_device::tg00_1,
12	26	// #define THUMB_INSN_ADDSUB ((UINT16)0x0800) // #define THUMB_ADDSUB_TYPE ((UINT16)0x0600)
13		tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0, tg01_0,
14		tg01_10, tg01_10, tg01_10, tg01_10, tg01_10, tg01_10, tg01_10, tg01_10, tg01_11, tg01_11, tg01_11, tg01_11, tg01_11, tg01_11, tg01_11, tg01_11, tg01_12, tg01_12, tg01_12, tg01_12, tg01_12, tg01_12, tg01_12, tg01_12, tg01_13, tg01_13, tg01_13, tg01_13, tg01_13, tg01_13, tg01_13, tg01_13,
	27	&arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0,
	28	&arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0,
	29	&arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0,
	30	&arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0,
	31	&arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0,
	32	&arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0,
	33	&arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0,
	34	&arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0, &arm7_cpu_device::tg01_0,
	35	&arm7_cpu_device::tg01_10, &arm7_cpu_device::tg01_10, &arm7_cpu_device::tg01_10, &arm7_cpu_device::tg01_10,
	36	&arm7_cpu_device::tg01_10, &arm7_cpu_device::tg01_10, &arm7_cpu_device::tg01_10, &arm7_cpu_device::tg01_10,
	37	&arm7_cpu_device::tg01_11, &arm7_cpu_device::tg01_11, &arm7_cpu_device::tg01_11, &arm7_cpu_device::tg01_11,
	38	&arm7_cpu_device::tg01_11, &arm7_cpu_device::tg01_11, &arm7_cpu_device::tg01_11, &arm7_cpu_device::tg01_11,
	39	&arm7_cpu_device::tg01_12, &arm7_cpu_device::tg01_12, &arm7_cpu_device::tg01_12, &arm7_cpu_device::tg01_12,
	40	&arm7_cpu_device::tg01_12, &arm7_cpu_device::tg01_12, &arm7_cpu_device::tg01_12, &arm7_cpu_device::tg01_12,
	41	&arm7_cpu_device::tg01_13, &arm7_cpu_device::tg01_13, &arm7_cpu_device::tg01_13, &arm7_cpu_device::tg01_13,
	42	&arm7_cpu_device::tg01_13, &arm7_cpu_device::tg01_13, &arm7_cpu_device::tg01_13, &arm7_cpu_device::tg01_13,
15	43	// #define THUMB_INSN_CMP ((UINT16)0x0800)
16		tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0, tg02_0,
17		tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1, tg02_1,
	44	&arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0,
	45	&arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0,
	46	&arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0,
	47	&arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0,
	48	&arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0,
	49	&arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0,
	50	&arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0,
	51	&arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0, &arm7_cpu_device::tg02_0,
	52	&arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1,
	53	&arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1,
	54	&arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1,
	55	&arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1,
	56	&arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1,
	57	&arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1,
	58	&arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1,
	59	&arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1, &arm7_cpu_device::tg02_1,
18	60	// #define THUMB_INSN_SUB ((UINT16)0x0800)
19		tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0, tg03_0,
20		tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1, tg03_1,
	61	&arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0,
	62	&arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0,
	63	&arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0,
	64	&arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0,
	65	&arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0,
	66	&arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0,
	67	&arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0,
	68	&arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0, &arm7_cpu_device::tg03_0,
	69	&arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1,
	70	&arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1,
	71	&arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1,
	72	&arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1,
	73	&arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1,
	74	&arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1,
	75	&arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1,
	76	&arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1, &arm7_cpu_device::tg03_1,
21	77	//#define THUMB_GROUP4_TYPE ((UINT16)0x0c00) //#define THUMB_ALUOP_TYPE ((UINT16)0x03c0) // #define THUMB_HIREG_OP ((UINT16)0x0300) // #define THUMB_HIREG_H ((UINT16)0x00c0)
22		tg04_00_00, tg04_00_01, tg04_00_02, tg04_00_03, tg04_00_04, tg04_00_05, tg04_00_06, tg04_00_07, tg04_00_08, tg04_00_09, tg04_00_0a, tg04_00_0b, tg04_00_0c, tg04_00_0d, tg04_00_0e, tg04_00_0f, tg04_01_00, tg04_01_01, tg04_01_02, tg04_01_03, tg04_01_10, tg04_01_11, tg04_01_12, tg04_01_13, tg04_01_20, tg04_01_21, tg04_01_22, tg04_01_23, tg04_01_30, tg04_01_31, tg04_01_32, tg04_01_33,
23		tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203, tg04_0203,
	78	&arm7_cpu_device::tg04_00_00, &arm7_cpu_device::tg04_00_01, &arm7_cpu_device::tg04_00_02, &arm7_cpu_device::tg04_00_03,
	79	&arm7_cpu_device::tg04_00_04, &arm7_cpu_device::tg04_00_05, &arm7_cpu_device::tg04_00_06, &arm7_cpu_device::tg04_00_07,
	80	&arm7_cpu_device::tg04_00_08, &arm7_cpu_device::tg04_00_09, &arm7_cpu_device::tg04_00_0a, &arm7_cpu_device::tg04_00_0b,
	81	&arm7_cpu_device::tg04_00_0c, &arm7_cpu_device::tg04_00_0d, &arm7_cpu_device::tg04_00_0e, &arm7_cpu_device::tg04_00_0f,
	82	&arm7_cpu_device::tg04_01_00, &arm7_cpu_device::tg04_01_01, &arm7_cpu_device::tg04_01_02, &arm7_cpu_device::tg04_01_03,
	83	&arm7_cpu_device::tg04_01_10, &arm7_cpu_device::tg04_01_11, &arm7_cpu_device::tg04_01_12, &arm7_cpu_device::tg04_01_13,
	84	&arm7_cpu_device::tg04_01_20, &arm7_cpu_device::tg04_01_21, &arm7_cpu_device::tg04_01_22, &arm7_cpu_device::tg04_01_23,
	85	&arm7_cpu_device::tg04_01_30, &arm7_cpu_device::tg04_01_31, &arm7_cpu_device::tg04_01_32, &arm7_cpu_device::tg04_01_33,
	86	&arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203,
	87	&arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203,
	88	&arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203,
	89	&arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203,
	90	&arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203,
	91	&arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203,
	92	&arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203,
	93	&arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203, &arm7_cpu_device::tg04_0203,
24	94	//#define THUMB_GROUP5_TYPE ((UINT16)0x0e00)
25		tg05_0, tg05_0, tg05_0, tg05_0, tg05_0, tg05_0, tg05_0, tg05_0, tg05_1, tg05_1, tg05_1, tg05_1, tg05_1, tg05_1, tg05_1, tg05_1, tg05_2, tg05_2, tg05_2, tg05_2, tg05_2, tg05_2, tg05_2, tg05_2, tg05_3, tg05_3, tg05_3, tg05_3, tg05_3, tg05_3, tg05_3, tg05_3,
26		tg05_4, tg05_4, tg05_4, tg05_4, tg05_4, tg05_4, tg05_4, tg05_4, tg05_5, tg05_5, tg05_5, tg05_5, tg05_5, tg05_5, tg05_5, tg05_5, tg05_6, tg05_6, tg05_6, tg05_6, tg05_6, tg05_6, tg05_6, tg05_6, tg05_7, tg05_7, tg05_7, tg05_7, tg05_7, tg05_7, tg05_7, tg05_7,
	95	&arm7_cpu_device::tg05_0, &arm7_cpu_device::tg05_0, &arm7_cpu_device::tg05_0, &arm7_cpu_device::tg05_0,
	96	&arm7_cpu_device::tg05_0, &arm7_cpu_device::tg05_0, &arm7_cpu_device::tg05_0, &arm7_cpu_device::tg05_0,
	97	&arm7_cpu_device::tg05_1, &arm7_cpu_device::tg05_1, &arm7_cpu_device::tg05_1, &arm7_cpu_device::tg05_1,
	98	&arm7_cpu_device::tg05_1, &arm7_cpu_device::tg05_1, &arm7_cpu_device::tg05_1, &arm7_cpu_device::tg05_1,
	99	&arm7_cpu_device::tg05_2, &arm7_cpu_device::tg05_2, &arm7_cpu_device::tg05_2, &arm7_cpu_device::tg05_2,
	100	&arm7_cpu_device::tg05_2, &arm7_cpu_device::tg05_2, &arm7_cpu_device::tg05_2, &arm7_cpu_device::tg05_2,
	101	&arm7_cpu_device::tg05_3, &arm7_cpu_device::tg05_3, &arm7_cpu_device::tg05_3, &arm7_cpu_device::tg05_3,
	102	&arm7_cpu_device::tg05_3, &arm7_cpu_device::tg05_3, &arm7_cpu_device::tg05_3, &arm7_cpu_device::tg05_3,
	103	&arm7_cpu_device::tg05_4, &arm7_cpu_device::tg05_4, &arm7_cpu_device::tg05_4, &arm7_cpu_device::tg05_4,
	104	&arm7_cpu_device::tg05_4, &arm7_cpu_device::tg05_4, &arm7_cpu_device::tg05_4, &arm7_cpu_device::tg05_4,
	105	&arm7_cpu_device::tg05_5, &arm7_cpu_device::tg05_5, &arm7_cpu_device::tg05_5, &arm7_cpu_device::tg05_5,
	106	&arm7_cpu_device::tg05_5, &arm7_cpu_device::tg05_5, &arm7_cpu_device::tg05_5, &arm7_cpu_device::tg05_5,
	107	&arm7_cpu_device::tg05_6, &arm7_cpu_device::tg05_6, &arm7_cpu_device::tg05_6, &arm7_cpu_device::tg05_6,
	108	&arm7_cpu_device::tg05_6, &arm7_cpu_device::tg05_6, &arm7_cpu_device::tg05_6, &arm7_cpu_device::tg05_6,
	109	&arm7_cpu_device::tg05_7, &arm7_cpu_device::tg05_7, &arm7_cpu_device::tg05_7, &arm7_cpu_device::tg05_7,
	110	&arm7_cpu_device::tg05_7, &arm7_cpu_device::tg05_7, &arm7_cpu_device::tg05_7, &arm7_cpu_device::tg05_7,
27	111	//#define THUMB_LSOP_L ((UINT16)0x0800)
28		tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0, tg06_0,
29		tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1, tg06_1,
	112	&arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0,
	113	&arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0,
	114	&arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0,
	115	&arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0,
	116	&arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0,
	117	&arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0,
	118	&arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0,
	119	&arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0, &arm7_cpu_device::tg06_0,
	120	&arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1,
	121	&arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1,
	122	&arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1,
	123	&arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1,
	124	&arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1,
	125	&arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1,
	126	&arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1,
	127	&arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1, &arm7_cpu_device::tg06_1,
30	128	//#define THUMB_LSOP_L ((UINT16)0x0800)
31		tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0, tg07_0,
32		tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1, tg07_1,
	129	&arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0,
	130	&arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0,
	131	&arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0,
	132	&arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0,
	133	&arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0,
	134	&arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0,
	135	&arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0,
	136	&arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0, &arm7_cpu_device::tg07_0,
	137	&arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1,
	138	&arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1,
	139	&arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1,
	140	&arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1,
	141	&arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1,
	142	&arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1,
	143	&arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1,
	144	&arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1, &arm7_cpu_device::tg07_1,
33	145	// #define THUMB_HALFOP_L ((UINT16)0x0800)
34		tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0, tg08_0,
35		tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1, tg08_1,
	146	&arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0,
	147	&arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0,
	148	&arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0,
	149	&arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0,
	150	&arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0,
	151	&arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0,
	152	&arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0,
	153	&arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0, &arm7_cpu_device::tg08_0,
	154	&arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1,
	155	&arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1,
	156	&arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1,
	157	&arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1,
	158	&arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1,
	159	&arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1,
	160	&arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1,
	161	&arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1, &arm7_cpu_device::tg08_1,
36	162	// #define THUMB_STACKOP_L ((UINT16)0x0800)
37		tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0, tg09_0,
38		tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1, tg09_1,
	163	&arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0,
	164	&arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0,
	165	&arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0,
	166	&arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0,
	167	&arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0,
	168	&arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0,
	169	&arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0,
	170	&arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0, &arm7_cpu_device::tg09_0,
	171	&arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1,
	172	&arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1,
	173	&arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1,
	174	&arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1,
	175	&arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1,
	176	&arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1,
	177	&arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1,
	178	&arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1, &arm7_cpu_device::tg09_1,
39	179	// #define THUMB_RELADDR_SP ((UINT16)0x0800)
40		tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0, tg0a_0,
41		tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1, tg0a_1,
	180	&arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0,
	181	&arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0,
	182	&arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0,
	183	&arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0,
	184	&arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0,
	185	&arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0,
	186	&arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0,
	187	&arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0, &arm7_cpu_device::tg0a_0,
	188	&arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1,
	189	&arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1,
	190	&arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1,
	191	&arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1,
	192	&arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1,
	193	&arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1,
	194	&arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1,
	195	&arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1, &arm7_cpu_device::tg0a_1,
42	196	// #define THUMB_STACKOP_TYPE ((UINT16)0x0f00)
43		tg0b_0, tg0b_0, tg0b_0, tg0b_0, tg0b_1, tg0b_1, tg0b_1, tg0b_1, tg0b_2, tg0b_2, tg0b_2, tg0b_2, tg0b_3, tg0b_3, tg0b_3, tg0b_3, tg0b_4, tg0b_4, tg0b_4, tg0b_4, tg0b_5, tg0b_5, tg0b_5, tg0b_5, tg0b_6, tg0b_6, tg0b_6, tg0b_6, tg0b_7, tg0b_7, tg0b_7, tg0b_7,
44		tg0b_8, tg0b_8, tg0b_8, tg0b_8, tg0b_9, tg0b_9, tg0b_9, tg0b_9, tg0b_a, tg0b_a, tg0b_a, tg0b_a, tg0b_b, tg0b_b, tg0b_b, tg0b_b, tg0b_c, tg0b_c, tg0b_c, tg0b_c, tg0b_d, tg0b_d, tg0b_d, tg0b_d, tg0b_e, tg0b_e, tg0b_e, tg0b_e, tg0b_f, tg0b_f, tg0b_f, tg0b_f,
	197	&arm7_cpu_device::tg0b_0, &arm7_cpu_device::tg0b_0, &arm7_cpu_device::tg0b_0, &arm7_cpu_device::tg0b_0,
	198	&arm7_cpu_device::tg0b_1, &arm7_cpu_device::tg0b_1, &arm7_cpu_device::tg0b_1, &arm7_cpu_device::tg0b_1,
	199	&arm7_cpu_device::tg0b_2, &arm7_cpu_device::tg0b_2, &arm7_cpu_device::tg0b_2, &arm7_cpu_device::tg0b_2,
	200	&arm7_cpu_device::tg0b_3, &arm7_cpu_device::tg0b_3, &arm7_cpu_device::tg0b_3, &arm7_cpu_device::tg0b_3,
	201	&arm7_cpu_device::tg0b_4, &arm7_cpu_device::tg0b_4, &arm7_cpu_device::tg0b_4, &arm7_cpu_device::tg0b_4,
	202	&arm7_cpu_device::tg0b_5, &arm7_cpu_device::tg0b_5, &arm7_cpu_device::tg0b_5, &arm7_cpu_device::tg0b_5,
	203	&arm7_cpu_device::tg0b_6, &arm7_cpu_device::tg0b_6, &arm7_cpu_device::tg0b_6, &arm7_cpu_device::tg0b_6,
	204	&arm7_cpu_device::tg0b_7, &arm7_cpu_device::tg0b_7, &arm7_cpu_device::tg0b_7, &arm7_cpu_device::tg0b_7,
	205	&arm7_cpu_device::tg0b_8, &arm7_cpu_device::tg0b_8, &arm7_cpu_device::tg0b_8, &arm7_cpu_device::tg0b_8,
	206	&arm7_cpu_device::tg0b_9, &arm7_cpu_device::tg0b_9, &arm7_cpu_device::tg0b_9, &arm7_cpu_device::tg0b_9,
	207	&arm7_cpu_device::tg0b_a, &arm7_cpu_device::tg0b_a, &arm7_cpu_device::tg0b_a, &arm7_cpu_device::tg0b_a,
	208	&arm7_cpu_device::tg0b_b, &arm7_cpu_device::tg0b_b, &arm7_cpu_device::tg0b_b, &arm7_cpu_device::tg0b_b,
	209	&arm7_cpu_device::tg0b_c, &arm7_cpu_device::tg0b_c, &arm7_cpu_device::tg0b_c, &arm7_cpu_device::tg0b_c,
	210	&arm7_cpu_device::tg0b_d, &arm7_cpu_device::tg0b_d, &arm7_cpu_device::tg0b_d, &arm7_cpu_device::tg0b_d,
	211	&arm7_cpu_device::tg0b_e, &arm7_cpu_device::tg0b_e, &arm7_cpu_device::tg0b_e, &arm7_cpu_device::tg0b_e,
	212	&arm7_cpu_device::tg0b_f, &arm7_cpu_device::tg0b_f, &arm7_cpu_device::tg0b_f, &arm7_cpu_device::tg0b_f,
45	213	// #define THUMB_MULTLS ((UINT16)0x0800)
46		tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0, tg0c_0,
47		tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1, tg0c_1,
	214	&arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0,
	215	&arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0,
	216	&arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0,
	217	&arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0,
	218	&arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0,
	219	&arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0,
	220	&arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0,
	221	&arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0, &arm7_cpu_device::tg0c_0,
	222	&arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1,
	223	&arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1,
	224	&arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1,
	225	&arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1,
	226	&arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1,
	227	&arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1,
	228	&arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1,
	229	&arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1, &arm7_cpu_device::tg0c_1,
48	230	// #define THUMB_COND_TYPE ((UINT16)0x0f00)
49		tg0d_0, tg0d_0, tg0d_0, tg0d_0, tg0d_1, tg0d_1, tg0d_1, tg0d_1, tg0d_2, tg0d_2, tg0d_2, tg0d_2, tg0d_3, tg0d_3, tg0d_3, tg0d_3, tg0d_4, tg0d_4, tg0d_4, tg0d_4, tg0d_5, tg0d_5, tg0d_5, tg0d_5, tg0d_6, tg0d_6, tg0d_6, tg0d_6, tg0d_7, tg0d_7, tg0d_7, tg0d_7,
50		tg0d_8, tg0d_8, tg0d_8, tg0d_8, tg0d_9, tg0d_9, tg0d_9, tg0d_9, tg0d_a, tg0d_a, tg0d_a, tg0d_a, tg0d_b, tg0d_b, tg0d_b, tg0d_b, tg0d_c, tg0d_c, tg0d_c, tg0d_c, tg0d_d, tg0d_d, tg0d_d, tg0d_d, tg0d_e, tg0d_e, tg0d_e, tg0d_e, tg0d_f, tg0d_f, tg0d_f, tg0d_f,
	231	&arm7_cpu_device::tg0d_0, &arm7_cpu_device::tg0d_0, &arm7_cpu_device::tg0d_0, &arm7_cpu_device::tg0d_0,
	232	&arm7_cpu_device::tg0d_1, &arm7_cpu_device::tg0d_1, &arm7_cpu_device::tg0d_1, &arm7_cpu_device::tg0d_1,
	233	&arm7_cpu_device::tg0d_2, &arm7_cpu_device::tg0d_2, &arm7_cpu_device::tg0d_2, &arm7_cpu_device::tg0d_2,
	234	&arm7_cpu_device::tg0d_3, &arm7_cpu_device::tg0d_3, &arm7_cpu_device::tg0d_3, &arm7_cpu_device::tg0d_3,
	235	&arm7_cpu_device::tg0d_4, &arm7_cpu_device::tg0d_4, &arm7_cpu_device::tg0d_4, &arm7_cpu_device::tg0d_4,
	236	&arm7_cpu_device::tg0d_5, &arm7_cpu_device::tg0d_5, &arm7_cpu_device::tg0d_5, &arm7_cpu_device::tg0d_5,
	237	&arm7_cpu_device::tg0d_6, &arm7_cpu_device::tg0d_6, &arm7_cpu_device::tg0d_6, &arm7_cpu_device::tg0d_6,
	238	&arm7_cpu_device::tg0d_7, &arm7_cpu_device::tg0d_7, &arm7_cpu_device::tg0d_7, &arm7_cpu_device::tg0d_7,
	239	&arm7_cpu_device::tg0d_8, &arm7_cpu_device::tg0d_8, &arm7_cpu_device::tg0d_8, &arm7_cpu_device::tg0d_8,
	240	&arm7_cpu_device::tg0d_9, &arm7_cpu_device::tg0d_9, &arm7_cpu_device::tg0d_9, &arm7_cpu_device::tg0d_9,
	241	&arm7_cpu_device::tg0d_a, &arm7_cpu_device::tg0d_a, &arm7_cpu_device::tg0d_a, &arm7_cpu_device::tg0d_a,
	242	&arm7_cpu_device::tg0d_b, &arm7_cpu_device::tg0d_b, &arm7_cpu_device::tg0d_b, &arm7_cpu_device::tg0d_b,
	243	&arm7_cpu_device::tg0d_c, &arm7_cpu_device::tg0d_c, &arm7_cpu_device::tg0d_c, &arm7_cpu_device::tg0d_c,
	244	&arm7_cpu_device::tg0d_d, &arm7_cpu_device::tg0d_d, &arm7_cpu_device::tg0d_d, &arm7_cpu_device::tg0d_d,
	245	&arm7_cpu_device::tg0d_e, &arm7_cpu_device::tg0d_e, &arm7_cpu_device::tg0d_e, &arm7_cpu_device::tg0d_e,
	246	&arm7_cpu_device::tg0d_f, &arm7_cpu_device::tg0d_f, &arm7_cpu_device::tg0d_f, &arm7_cpu_device::tg0d_f,
51	247	// #define THUMB_BLOP_LO ((UINT16)0x0800)
52		tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0, tg0e_0,
53		tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1, tg0e_1,
	248	&arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0,
	249	&arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0,
	250	&arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0,
	251	&arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0,
	252	&arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0,
	253	&arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0,
	254	&arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0,
	255	&arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0, &arm7_cpu_device::tg0e_0,
	256	&arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1,
	257	&arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1,
	258	&arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1,
	259	&arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1,
	260	&arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1,
	261	&arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1,
	262	&arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1,
	263	&arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1, &arm7_cpu_device::tg0e_1,
54	264	// #define THUMB_BLOP_LO ((UINT16)0x0800)
55		tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0, tg0f_0,
56		tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1, tg0f_1,
	265	&arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0,
	266	&arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0,
	267	&arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0,
	268	&arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0,
	269	&arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0,
	270	&arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0,
	271	&arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0,
	272	&arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0, &arm7_cpu_device::tg0f_0,
	273	&arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1,
	274	&arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1,
	275	&arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1,
	276	&arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1,
	277	&arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1,
	278	&arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1,
	279	&arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1,
	280	&arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1, &arm7_cpu_device::tg0f_1,
57	281	};
58	282
59	283	/* Shift operations */
60	284
61		~~const~~ void tg00_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Shift left */
	285	void arm7_cpu_device::tg00_0(UINT32 pc, UINT32 op) /* Shift left */
62	286	{
63	287	UINT32 rs, rd, rrs;
64	288	INT32 offs;
r24074	r24075
67	291
68	292	rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
69	293	rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
70		rrs = GET_REGISTER(~~arm,~~ rs);
	294	rrs = GET_REGISTER(rs);
71	295	offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
72	296	if (offs != 0)
73	297	{
74		SET_REGISTER(~~arm,~~ rd, rrs << offs);
	298	SET_REGISTER(rd, rrs << offs);
75	299	if (rrs & (1 << (31 - (offs - 1))))
76	300	{
77	301	SET_CPSR(GET_CPSR \| C_MASK);
r24074	r24075
83	307	}
84	308	else
85	309	{
86		SET_REGISTER(~~arm,~~ rd, rrs);
	310	SET_REGISTER(rd, rrs);
87	311	}
88	312	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
89		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	313	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
90	314	R15 += 2;
91	315	}
92	316
93		~~const~~ void tg00_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Shift right */
	317	void arm7_cpu_device::tg00_1(UINT32 pc, UINT32 op) /* Shift right */
94	318	{
95	319	UINT32 rs, rd, rrs;
96	320	INT32 offs;
97	321
98	322	rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
99	323	rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
100		rrs = GET_REGISTER(~~arm,~~ rs);
	324	rrs = GET_REGISTER(rs);
101	325	offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
102	326	if (offs != 0)
103	327	{
104		SET_REGISTER(~~arm,~~ rd, rrs >> offs);
	328	SET_REGISTER(rd, rrs >> offs);
105	329	if (rrs & (1 << (offs - 1)))
106	330	{
107	331	SET_CPSR(GET_CPSR \| C_MASK);
r24074	r24075
113	337	}
114	338	else
115	339	{
116		SET_REGISTER(~~arm,~~ rd, 0);
	340	SET_REGISTER(rd, 0);
117	341	if (rrs & 0x80000000)
118	342	{
119	343	SET_CPSR(GET_CPSR \| C_MASK);
r24074	r24075
124	348	}
125	349	}
126	350	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
127		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	351	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
128	352	R15 += 2;
129	353	}
130	354
131	355	/* Arithmetic */
132	356
133		~~const~~ void tg01_0(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	357	void arm7_cpu_device::tg01_0(UINT32 pc, UINT32 op)
134	358	{
135	359	UINT32 rs, rd, rrs;
136	360	INT32 offs;
r24074	r24075
139	363	{
140	364	rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
141	365	rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
142		rrs = GET_REGISTER(~~arm,~~ rs);
	366	rrs = GET_REGISTER(rs);
143	367	offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
144	368	if (offs == 0)
145	369	{
r24074	r24075
155	379	{
156	380	SET_CPSR(GET_CPSR & ~C_MASK);
157	381	}
158		SET_REGISTER(~~arm,~~ rd, (rrs & 0x80000000) ? 0xFFFFFFFF : 0x00000000);
	382	SET_REGISTER(rd, (rrs & 0x80000000) ? 0xFFFFFFFF : 0x00000000);
159	383	}
160	384	else
161	385	{
r24074	r24075
167	391	{
168	392	SET_CPSR(GET_CPSR & ~C_MASK);
169	393	}
170		SET_REGISTER(~~arm,~~ rd,
	394	SET_REGISTER(rd,
171	395	(rrs & 0x80000000)
172	396	? ((0xFFFFFFFF << (32 - offs)) \| (rrs >> offs))
173	397	: (rrs >> offs));
174	398	}
175	399	SET_CPSR(GET_CPSR & ~(N_MASK \| Z_MASK));
176		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	400	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
177	401	R15 += 2;
178	402	}
179	403	}
180	404
181		~~const~~ void tg01_10(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ADD Rd, Rs, Rn */
	405	void arm7_cpu_device::tg01_10(UINT32 pc, UINT32 op) /* ADD Rd, Rs, Rn */
182	406	{
183		UINT32 rn = GET_REGISTER(arm, (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT);
184		UINT32 rs = GET_REGISTER(arm, (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
	407	UINT32 rn = GET_REGISTER((op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT);
	408	UINT32 rs = GET_REGISTER((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
185	409	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
186		SET_REGISTER(arm, rd, rs + rn);
187		HandleThumbALUAddFlags(GET_REGISTER(arm, rd), rs, rn);
	410	SET_REGISTER(rd, rs + rn);
	411	HandleThumbALUAddFlags(GET_REGISTER(rd), rs, rn);
188	412
189	413	}
190	414
191		~~const~~ void tg01_11(~~arm_state arm,~~ UINT32 pc, UINT32 op) / SUB Rd, Rs, Rn */
	415	void arm7_cpu_device::tg01_11(UINT32 pc, UINT32 op) /* SUB Rd, Rs, Rn */
192	416	{
193		UINT32 rn = GET_REGISTER(arm, (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT);
194		UINT32 rs = GET_REGISTER(arm, (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
	417	UINT32 rn = GET_REGISTER((op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT);
	418	UINT32 rs = GET_REGISTER((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
195	419	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
196		SET_REGISTER(arm, rd, rs - rn);
197		HandleThumbALUSubFlags(GET_REGISTER(arm, rd), rs, rn);
	420	SET_REGISTER(rd, rs - rn);
	421	HandleThumbALUSubFlags(GET_REGISTER(rd), rs, rn);
198	422
199	423	}
200	424
201		~~const~~ void tg01_12(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ADD Rd, Rs, #imm */
	425	void arm7_cpu_device::tg01_12(UINT32 pc, UINT32 op) /* ADD Rd, Rs, #imm */
202	426	{
203	427	UINT32 imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
204		UINT32 rs = GET_REGISTER(~~arm,~~ (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
	428	UINT32 rs = GET_REGISTER((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
205	429	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
206		SET_REGISTER(arm, rd, rs + imm);
207		HandleThumbALUAddFlags(GET_REGISTER(arm, rd), rs, imm);
	430	SET_REGISTER(rd, rs + imm);
	431	HandleThumbALUAddFlags(GET_REGISTER(rd), rs, imm);
208	432
209	433	}
210	434
211		~~const~~ void tg01_13(~~arm_state arm,~~ UINT32 pc, UINT32 op) / SUB Rd, Rs, #imm */
	435	void arm7_cpu_device::tg01_13(UINT32 pc, UINT32 op) /* SUB Rd, Rs, #imm */
212	436	{
213	437	UINT32 imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
214		UINT32 rs = GET_REGISTER(~~arm,~~ (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
	438	UINT32 rs = GET_REGISTER((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
215	439	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
216		SET_REGISTER(arm, rd, rs - imm);
217		HandleThumbALUSubFlags(GET_REGISTER(arm, rd), rs,imm);
	440	SET_REGISTER(rd, rs - imm);
	441	HandleThumbALUSubFlags(GET_REGISTER(rd), rs,imm);
218	442
219	443	}
220	444
221	445	/* CMP / MOV */
222	446
223		~~const~~ void tg02_0(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	447	void arm7_cpu_device::tg02_0(UINT32 pc, UINT32 op)
224	448	{
225	449	UINT32 rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
226	450	UINT32 op2 = (op & THUMB_INSN_IMM);
227		SET_REGISTER(~~arm,~~ rd, op2);
	451	SET_REGISTER(rd, op2);
228	452	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
229		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	453	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
230	454	R15 += 2;
231	455	}
232	456
233		~~const~~ void tg02_1(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	457	void arm7_cpu_device::tg02_1(UINT32 pc, UINT32 op)
234	458	{
235		UINT32 rn = GET_REGISTER(~~arm,~~ (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
	459	UINT32 rn = GET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
236	460	UINT32 op2 = op & THUMB_INSN_IMM;
237	461	UINT32 rd = rn - op2;
238	462	HandleThumbALUSubFlags(rd, rn, op2);
r24074	r24075
240	464
241	465	/* ADD/SUB immediate */
242	466
243		~~const~~ void tg03_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ADD Rd, #Offset8 */
	467	void arm7_cpu_device::tg03_0(UINT32 pc, UINT32 op) /* ADD Rd, #Offset8 */
244	468	{
245		UINT32 rn = GET_REGISTER(~~arm,~~ (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
	469	UINT32 rn = GET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
246	470	UINT32 op2 = op & THUMB_INSN_IMM;
247	471	UINT32 rd = rn + op2;
248		SET_REGISTER(~~arm,~~ (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, rd);
	472	SET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, rd);
249	473	HandleThumbALUAddFlags(rd, rn, op2);
250	474	}
251	475
252		~~const~~ void tg03_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / SUB Rd, #Offset8 */
	476	void arm7_cpu_device::tg03_1(UINT32 pc, UINT32 op) /* SUB Rd, #Offset8 */
253	477	{
254		UINT32 rn = GET_REGISTER(~~arm,~~ (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
	478	UINT32 rn = GET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
255	479	UINT32 op2 = op & THUMB_INSN_IMM;
256	480	UINT32 rd = rn - op2;
257		SET_REGISTER(~~arm,~~ (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, rd);
	481	SET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, rd);
258	482	HandleThumbALUSubFlags(rd, rn, op2);
259	483	}
260	484
261	485	/* Rd & Rm instructions */
262	486
263		~~const~~ void tg04_00_00(~~arm_state arm,~~ UINT32 pc, UINT32 op) / AND Rd, Rs */
	487	void arm7_cpu_device::tg04_00_00(UINT32 pc, UINT32 op) /* AND Rd, Rs */
264	488	{
265	489	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
266	490	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
267		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(ar~~m, r~~d) & GET_REGISTER(~~arm,~~ rs));
	491	SET_REGISTER(rd, GET_REGISTER(rd) & GET_REGISTER(rs));
268	492	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
269		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	493	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
270	494	R15 += 2;
271	495	}
272	496
273		~~const~~ void tg04_00_01(~~arm_state arm,~~ UINT32 pc, UINT32 op) / EOR Rd, Rs */
	497	void arm7_cpu_device::tg04_00_01(UINT32 pc, UINT32 op) /* EOR Rd, Rs */
274	498	{
275	499	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
276	500	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
277		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(ar~~m, r~~d) ^ GET_REGISTER(~~arm,~~ rs));
	501	SET_REGISTER(rd, GET_REGISTER(rd) ^ GET_REGISTER(rs));
278	502	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
279		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	503	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
280	504	R15 += 2;
281	505	}
282	506
283		~~const~~ void tg04_00_02(~~arm_state arm,~~ UINT32 pc, UINT32 op) / LSL Rd, Rs */
	507	void arm7_cpu_device::tg04_00_02(UINT32 pc, UINT32 op) /* LSL Rd, Rs */
284	508	{
285	509	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
286	510	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
287		UINT32 rrd = GET_REGISTER(arm, rd);
288		INT32 offs = GET_REGISTER(arm, rs) & 0x000000ff;
	511	UINT32 rrd = GET_REGISTER(rd);
	512	INT32 offs = GET_REGISTER(rs) & 0x000000ff;
289	513	if (offs > 0)
290	514	{
291	515	if (offs < 32)
292	516	{
293		SET_REGISTER(~~arm,~~ rd, rrd << offs);
	517	SET_REGISTER(rd, rrd << offs);
294	518	if (rrd & (1 << (31 - (offs - 1))))
295	519	{
296	520	SET_CPSR(GET_CPSR \| C_MASK);
r24074	r24075
302	526	}
303	527	else if (offs == 32)
304	528	{
305		SET_REGISTER(~~arm,~~ rd, 0);
	529	SET_REGISTER(rd, 0);
306	530	if (rrd & 1)
307	531	{
308	532	SET_CPSR(GET_CPSR \| C_MASK);
r24074	r24075
314	538	}
315	539	else
316	540	{
317		SET_REGISTER(~~arm,~~ rd, 0);
	541	SET_REGISTER(rd, 0);
318	542	SET_CPSR(GET_CPSR & ~C_MASK);
319	543	}
320	544	}
321	545	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
322		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	546	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
323	547	R15 += 2;
324	548	}
325	549
326		~~const~~ void tg04_00_03(~~arm_state arm,~~ UINT32 pc, UINT32 op) / LSR Rd, Rs */
	550	void arm7_cpu_device::tg04_00_03(UINT32 pc, UINT32 op) /* LSR Rd, Rs */
327	551	{
328	552	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
329	553	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
330		UINT32 rrd = GET_REGISTER(arm, rd);
331		INT32 offs = GET_REGISTER(arm, rs) & 0x000000ff;
	554	UINT32 rrd = GET_REGISTER(rd);
	555	INT32 offs = GET_REGISTER(rs) & 0x000000ff;
332	556	if (offs > 0)
333	557	{
334	558	if (offs < 32)
335	559	{
336		SET_REGISTER(~~arm,~~ rd, rrd >> offs);
	560	SET_REGISTER(rd, rrd >> offs);
337	561	if (rrd & (1 << (offs - 1)))
338	562	{
339	563	SET_CPSR(GET_CPSR \| C_MASK);
r24074	r24075
345	569	}
346	570	else if (offs == 32)
347	571	{
348		SET_REGISTER(~~arm,~~ rd, 0);
	572	SET_REGISTER(rd, 0);
349	573	if (rrd & 0x80000000)
350	574	{
351	575	SET_CPSR(GET_CPSR \| C_MASK);
r24074	r24075
357	581	}
358	582	else
359	583	{
360		SET_REGISTER(~~arm,~~ rd, 0);
	584	SET_REGISTER(rd, 0);
361	585	SET_CPSR(GET_CPSR & ~C_MASK);
362	586	}
363	587	}
364	588	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
365		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	589	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
366	590	R15 += 2;
367	591	}
368	592
369		~~const~~ void tg04_00_04(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ASR Rd, Rs */
	593	void arm7_cpu_device::tg04_00_04(UINT32 pc, UINT32 op) /* ASR Rd, Rs */
370	594	{
371	595	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
372	596	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
373		UINT32 rrs = GET_REGISTER(arm, rs)&0xff;
374		UINT32 rrd = GET_REGISTER(arm, rd);
	597	UINT32 rrs = GET_REGISTER(rs)&0xff;
	598	UINT32 rrd = GET_REGISTER(rd);
375	599	if (rrs != 0)
376	600	{
377	601	if (rrs >= 32)
r24074	r24075
384	608	{
385	609	SET_CPSR(GET_CPSR & ~C_MASK);
386	610	}
387		SET_REGISTER(ar~~m, r~~d, (GET_REGISTER(~~arm,~~ rd) & 0x80000000) ? 0xFFFFFFFF : 0x00000000);
	611	SET_REGISTER(rd, (GET_REGISTER(rd) & 0x80000000) ? 0xFFFFFFFF : 0x00000000);
388	612	}
389	613	else
390	614	{
r24074	r24075
396	620	{
397	621	SET_CPSR(GET_CPSR & ~C_MASK);
398	622	}
399		SET_REGISTER(~~arm,~~ rd, (rrd & 0x80000000)
	623	SET_REGISTER(rd, (rrd & 0x80000000)
400	624	? ((0xFFFFFFFF << (32 - rrs)) \| (rrd >> rrs))
401	625	: (rrd >> rrs));
402	626	}
403	627	}
404	628	SET_CPSR(GET_CPSR & ~(N_MASK \| Z_MASK));
405		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	629	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
406	630	R15 += 2;
407	631	}
408	632
409		~~const~~ void tg04_00_05(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ADC Rd, Rs */
	633	void arm7_cpu_device::tg04_00_05(UINT32 pc, UINT32 op) /* ADC Rd, Rs */
410	634	{
411	635	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
412	636	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
413	637	UINT32 op2 = (GET_CPSR & C_MASK) ? 1 : 0;
414		UINT32 rn = GET_REGISTER(arm, rd) + GET_REGISTER(arm, rs) + op2;
415		HandleThumbALUAddFlags(rn, GET_REGISTER(arm, rd), (GET_REGISTER(arm, rs))); // ?
416		SET_REGISTER(arm, rd, rn);
	638	UINT32 rn = GET_REGISTER(rd) + GET_REGISTER(rs) + op2;
	639	HandleThumbALUAddFlags(rn, GET_REGISTER(rd), (GET_REGISTER(rs))); // ?
	640	SET_REGISTER(rd, rn);
417	641	}
418	642
419		~~const~~ void tg04_00_06(~~arm_state arm,~~ UINT32 pc, UINT32 op) / SBC Rd, Rs */
	643	void arm7_cpu_device::tg04_00_06(UINT32 pc, UINT32 op) /* SBC Rd, Rs */
420	644	{
421	645	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
422	646	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
423	647	UINT32 op2 = (GET_CPSR & C_MASK) ? 0 : 1;
424		UINT32 rn = GET_REGISTER(arm, rd) - GET_REGISTER(arm, rs) - op2;
425		HandleThumbALUSubFlags(rn, GET_REGISTER(arm, rd), (GET_REGISTER(arm, rs))); //?
426		SET_REGISTER(arm, rd, rn);
	648	UINT32 rn = GET_REGISTER(rd) - GET_REGISTER(rs) - op2;
	649	HandleThumbALUSubFlags(rn, GET_REGISTER(rd), (GET_REGISTER(rs))); //?
	650	SET_REGISTER(rd, rn);
427	651	}
428	652
429		~~const~~ void tg04_00_07(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ROR Rd, Rs */
	653	void arm7_cpu_device::tg04_00_07(UINT32 pc, UINT32 op) /* ROR Rd, Rs */
430	654	{
431	655	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
432	656	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
433		UINT32 rrd = GET_REGISTER(arm, rd);
434		UINT32 imm = GET_REGISTER(arm, rs) & 0x0000001f;
435		SET_REGISTER(arm, rd, (rrd >> imm) \| (rrd << (32 - imm)));
	657	UINT32 rrd = GET_REGISTER(rd);
	658	UINT32 imm = GET_REGISTER(rs) & 0x0000001f;
	659	SET_REGISTER(rd, (rrd >> imm) \| (rrd << (32 - imm)));
436	660	if (rrd & (1 << (imm - 1)))
437	661	{
438	662	SET_CPSR(GET_CPSR \| C_MASK);
r24074	r24075
442	666	SET_CPSR(GET_CPSR & ~C_MASK);
443	667	}
444	668	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
445		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	669	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
446	670	R15 += 2;
447	671	}
448	672
449		~~const~~ void tg04_00_08(~~arm_state arm,~~ UINT32 pc, UINT32 op) / TST Rd, Rs */
	673	void arm7_cpu_device::tg04_00_08(UINT32 pc, UINT32 op) /* TST Rd, Rs */
450	674	{
451	675	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
452	676	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
453	677	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
454		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(ar~~m, r~~d) & GET_REGISTER(~~arm,~~ rs)));
	678	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd) & GET_REGISTER(rs)));
455	679	R15 += 2;
456	680	}
457	681
458		~~const~~ void tg04_00_09(~~arm_state arm,~~ UINT32 pc, UINT32 op) / NEG Rd, Rs */
	682	void arm7_cpu_device::tg04_00_09(UINT32 pc, UINT32 op) /* NEG Rd, Rs */
459	683	{
460	684	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
461	685	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
462		UINT32 rrs = GET_REGISTER(arm, rs);
463		SET_REGISTER(arm, rd, 0 - rrs);
464		HandleThumbALUSubFlags(GET_REGISTER(arm, rd), 0, rrs);
	686	UINT32 rrs = GET_REGISTER(rs);
	687	SET_REGISTER(rd, 0 - rrs);
	688	HandleThumbALUSubFlags(GET_REGISTER(rd), 0, rrs);
465	689	}
466	690
467		~~const~~ void tg04_00_0a(~~arm_state arm,~~ UINT32 pc, UINT32 op) / CMP Rd, Rs */
	691	void arm7_cpu_device::tg04_00_0a(UINT32 pc, UINT32 op) /* CMP Rd, Rs */
468	692	{
469	693	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
470	694	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
471		UINT32 rn = GET_REGISTER(arm, rd) - GET_REGISTER(arm, rs);
472		HandleThumbALUSubFlags(rn, GET_REGISTER(arm, rd), GET_REGISTER(arm, rs));
	695	UINT32 rn = GET_REGISTER(rd) - GET_REGISTER(rs);
	696	HandleThumbALUSubFlags(rn, GET_REGISTER(rd), GET_REGISTER(rs));
473	697	}
474	698
475		~~const~~ void tg04_00_0b(~~arm_state arm,~~ UINT32 pc, UINT32 op) / CMN Rd, Rs - check flags, add dasm */
	699	void arm7_cpu_device::tg04_00_0b(UINT32 pc, UINT32 op) /* CMN Rd, Rs - check flags, add dasm */
476	700	{
477	701	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
478	702	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
479		UINT32 rn = GET_REGISTER(arm, rd) + GET_REGISTER(arm, rs);
480		HandleThumbALUAddFlags(rn, GET_REGISTER(arm, rd), GET_REGISTER(arm, rs));
	703	UINT32 rn = GET_REGISTER(rd) + GET_REGISTER(rs);
	704	HandleThumbALUAddFlags(rn, GET_REGISTER(rd), GET_REGISTER(rs));
481	705	}
482	706
483		~~const~~ void tg04_00_0c(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ORR Rd, Rs */
	707	void arm7_cpu_device::tg04_00_0c(UINT32 pc, UINT32 op) /* ORR Rd, Rs */
484	708	{
485	709	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
486	710	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
487		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(ar~~m, r~~d) \| GET_REGISTER(~~arm,~~ rs));
	711	SET_REGISTER(rd, GET_REGISTER(rd) \| GET_REGISTER(rs));
488	712	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
489		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	713	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
490	714	R15 += 2;
491	715	}
492	716
493		~~const~~ void tg04_00_0d(~~arm_state arm,~~ UINT32 pc, UINT32 op) / MUL Rd, Rs */
	717	void arm7_cpu_device::tg04_00_0d(UINT32 pc, UINT32 op) /* MUL Rd, Rs */
494	718	{
495	719	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
496	720	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
497		UINT32 rn = GET_REGISTER(ar~~m, r~~d) * GET_REGISTER(~~arm,~~ rs);
	721	UINT32 rn = GET_REGISTER(rd) * GET_REGISTER(rs);
498	722	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
499		SET_REGISTER(~~arm,~~ rd, rn);
	723	SET_REGISTER(rd, rn);
500	724	SET_CPSR(GET_CPSR \| HandleALUNZFlags(rn));
501	725	R15 += 2;
502	726	}
503	727
504		~~const~~ void tg04_00_0e(~~arm_state arm,~~ UINT32 pc, UINT32 op) / BIC Rd, Rs */
	728	void arm7_cpu_device::tg04_00_0e(UINT32 pc, UINT32 op) /* BIC Rd, Rs */
505	729	{
506	730	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
507	731	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
508		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(ar~~m, r~~d) & (~GET_REGISTER(~~arm,~~ rs)));
	732	SET_REGISTER(rd, GET_REGISTER(rd) & (~GET_REGISTER(rs)));
509	733	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
510		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	734	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
511	735	R15 += 2;
512	736	}
513	737
514		~~const~~ void tg04_00_0f(~~arm_state arm,~~ UINT32 pc, UINT32 op) / MVN Rd, Rs */
	738	void arm7_cpu_device::tg04_00_0f(UINT32 pc, UINT32 op) /* MVN Rd, Rs */
515	739	{
516	740	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
517	741	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
518		UINT32 op2 = GET_REGISTER(arm, rs);
519		SET_REGISTER(arm, rd, ~op2);
	742	UINT32 op2 = GET_REGISTER(rs);
	743	SET_REGISTER(rd, ~op2);
520	744	SET_CPSR(GET_CPSR & ~(Z_MASK \| N_MASK));
521		SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(~~arm,~~ rd)));
	745	SET_CPSR(GET_CPSR \| HandleALUNZFlags(GET_REGISTER(rd)));
522	746	R15 += 2;
523	747	}
524	748
525	749	/* ADD Rd, Rs group */
526	750
527		~~const~~ void tg04_01_00(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	751	void arm7_cpu_device::tg04_01_00(UINT32 pc, UINT32 op)
528	752	{
529	753	fatalerror("%08x: G4-1-0 Undefined Thumb instruction: %04x %x\n", pc, op, (op & THUMB_HIREG_H) >> THUMB_HIREG_H_SHIFT);
530	754	}
531	755
532		~~const~~ void tg04_01_01(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ADD Rd, HRs */
	756	void arm7_cpu_device::tg04_01_01(UINT32 pc, UINT32 op) /* ADD Rd, HRs */
533	757	{
534	758	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
535	759	UINT32 rd = op & THUMB_HIREG_RD;
536		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(ar~~m, r~~d) + GET_REGISTER(~~arm,~~ rs+8));
	760	SET_REGISTER(rd, GET_REGISTER(rd) + GET_REGISTER(rs+8));
537	761	// emulate the effects of pre-fetch
538	762	if (rs == 7)
539	763	{
540		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(~~arm,~~ rd) + 4);
	764	SET_REGISTER(rd, GET_REGISTER(rd) + 4);
541	765	}
542	766
543	767	R15 += 2;
544	768	}
545	769
546		~~const~~ void tg04_01_02(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ADD HRd, Rs */
	770	void arm7_cpu_device::tg04_01_02(UINT32 pc, UINT32 op) /* ADD HRd, Rs */
547	771	{
548	772	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
549	773	UINT32 rd = op & THUMB_HIREG_RD;
550		SET_REGISTER(ar~~m, r~~d+8, GET_REGISTER(ar~~m, r~~d+8) + GET_REGISTER(~~arm,~~ rs));
	774	SET_REGISTER(rd+8, GET_REGISTER(rd+8) + GET_REGISTER(rs));
551	775	if (rd == 7)
552	776	{
553	777	R15 += 2;
r24074	r24075
556	780	R15 += 2;
557	781	}
558	782
559		~~const~~ void tg04_01_03(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Add HRd, HRs */
	783	void arm7_cpu_device::tg04_01_03(UINT32 pc, UINT32 op) /* Add HRd, HRs */
560	784	{
561	785	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
562	786	UINT32 rd = op & THUMB_HIREG_RD;
563		SET_REGISTER(ar~~m, r~~d+8, GET_REGISTER(ar~~m, r~~d+8) + GET_REGISTER(~~arm,~~ rs+8));
	787	SET_REGISTER(rd+8, GET_REGISTER(rd+8) + GET_REGISTER(rs+8));
564	788	// emulate the effects of pre-fetch
565	789	if (rs == 7)
566	790	{
567		SET_REGISTER(ar~~m, r~~d+8, GET_REGISTER(~~arm,~~ rd+8) + 4);
	791	SET_REGISTER(rd+8, GET_REGISTER(rd+8) + 4);
568	792	}
569	793	if (rd == 7)
570	794	{
r24074	r24075
574	798	R15 += 2;
575	799	}
576	800
577		~~const~~ void tg04_01_10(~~arm_state arm,~~ UINT32 pc, UINT32 op) / CMP Rd, Rs */
	801	void arm7_cpu_device::tg04_01_10(UINT32 pc, UINT32 op) /* CMP Rd, Rs */
578	802	{
579		UINT32 rs = GET_REGISTER(arm, ((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
580		UINT32 rd = GET_REGISTER(arm, op & THUMB_HIREG_RD);
	803	UINT32 rs = GET_REGISTER(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
	804	UINT32 rd = GET_REGISTER(op & THUMB_HIREG_RD);
581	805	UINT32 rn = rd - rs;
582	806	HandleThumbALUSubFlags(rn, rd, rs);
583	807	}
584	808
585		~~const~~ void tg04_01_11(~~arm_state arm,~~ UINT32 pc, UINT32 op) / CMP Rd, Hs */
	809	void arm7_cpu_device::tg04_01_11(UINT32 pc, UINT32 op) /* CMP Rd, Hs */
586	810	{
587		UINT32 rs = GET_REGISTER(arm, ((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT) + 8);
588		UINT32 rd = GET_REGISTER(arm, op & THUMB_HIREG_RD);
	811	UINT32 rs = GET_REGISTER(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT) + 8);
	812	UINT32 rd = GET_REGISTER(op & THUMB_HIREG_RD);
589	813	UINT32 rn = rd - rs;
590	814	HandleThumbALUSubFlags(rn, rd, rs);
591	815	}
592	816
593		~~const~~ void tg04_01_12(~~arm_state arm,~~ UINT32 pc, UINT32 op) / CMP Hd, Rs */
	817	void arm7_cpu_device::tg04_01_12(UINT32 pc, UINT32 op) /* CMP Hd, Rs */
594	818	{
595		UINT32 rs = GET_REGISTER(arm, ((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
596		UINT32 rd = GET_REGISTER(arm, (op & THUMB_HIREG_RD) + 8);
	819	UINT32 rs = GET_REGISTER(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
	820	UINT32 rd = GET_REGISTER((op & THUMB_HIREG_RD) + 8);
597	821	UINT32 rn = rd - rs;
598	822	HandleThumbALUSubFlags(rn, rd, rs);
599	823	}
600	824
601		~~const~~ void tg04_01_13(~~arm_state arm,~~ UINT32 pc, UINT32 op) / CMP Hd, Hs */
	825	void arm7_cpu_device::tg04_01_13(UINT32 pc, UINT32 op) /* CMP Hd, Hs */
602	826	{
603		UINT32 rs = GET_REGISTER(arm, ((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT) + 8);
604		UINT32 rd = GET_REGISTER(arm, (op & THUMB_HIREG_RD) + 8);
	827	UINT32 rs = GET_REGISTER(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT) + 8);
	828	UINT32 rd = GET_REGISTER((op & THUMB_HIREG_RD) + 8);
605	829	UINT32 rn = rd - rs;
606	830	HandleThumbALUSubFlags(rn, rd, rs);
607	831	}
r24074	r24075
609	833	/* MOV group */
610	834
611	835	// "The action of H1 = 0, H2 = 0 for Op = 00 (ADD), Op = 01 (CMP) and Op = 10 (MOV) is undefined, and should not be used."
612		~~const~~ void tg04_01_20(~~arm_state arm,~~ UINT32 pc, UINT32 op) / MOV Rd, Rs (undefined) */
	836	void arm7_cpu_device::tg04_01_20(UINT32 pc, UINT32 op) /* MOV Rd, Rs (undefined) */
613	837	{
614	838	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
615	839	UINT32 rd = op & THUMB_HIREG_RD;
616		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(~~arm,~~ rs));
	840	SET_REGISTER(rd, GET_REGISTER(rs));
617	841	R15 += 2;
618	842	}
619	843
620		~~const~~ void tg04_01_21(~~arm_state arm,~~ UINT32 pc, UINT32 op) / MOV Rd, Hs */
	844	void arm7_cpu_device::tg04_01_21(UINT32 pc, UINT32 op) /* MOV Rd, Hs */
621	845	{
622	846	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
623	847	UINT32 rd = op & THUMB_HIREG_RD;
624		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(~~arm,~~ rs + 8));
	848	SET_REGISTER(rd, GET_REGISTER(rs + 8));
625	849	if (rs == 7)
626	850	{
627		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(~~arm,~~ rd) + 4);
	851	SET_REGISTER(rd, GET_REGISTER(rd) + 4);
628	852	}
629	853	R15 += 2;
630	854	}
631	855
632		~~const~~ void tg04_01_22(~~arm_state arm,~~ UINT32 pc, UINT32 op) / MOV Hd, Rs */
	856	void arm7_cpu_device::tg04_01_22(UINT32 pc, UINT32 op) /* MOV Hd, Rs */
633	857	{
634	858	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
635	859	UINT32 rd = op & THUMB_HIREG_RD;
636		SET_REGISTER(ar~~m, r~~d + 8, GET_REGISTER(~~arm,~~ rs));
	860	SET_REGISTER(rd + 8, GET_REGISTER(rs));
637	861	if (rd != 7)
638	862	{
639	863	R15 += 2;
r24074	r24075
644	868	}
645	869	}
646	870
647		~~const~~ void tg04_01_23(~~arm_state arm,~~ UINT32 pc, UINT32 op) / MOV Hd, Hs */
	871	void arm7_cpu_device::tg04_01_23(UINT32 pc, UINT32 op) /* MOV Hd, Hs */
648	872	{
649	873	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
650	874	UINT32 rd = op & THUMB_HIREG_RD;
651	875	if (rs == 7)
652	876	{
653		SET_REGISTER(ar~~m, r~~d + 8, GET_REGISTER(~~arm,~~ rs+8)+4);
	877	SET_REGISTER(rd + 8, GET_REGISTER(rs+8)+4);
654	878	}
655	879	else
656	880	{
657		SET_REGISTER(ar~~m, r~~d + 8, GET_REGISTER(~~arm,~~ rs+8));
	881	SET_REGISTER(rd + 8, GET_REGISTER(rs+8));
658	882	}
659	883	if (rd != 7)
660	884	{
r24074	r24075
666	890	}
667	891	}
668	892
669		~~const~~ void tg04_01_30(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	893	void arm7_cpu_device::tg04_01_30(UINT32 pc, UINT32 op)
670	894	{
671	895	UINT32 rd = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
672		UINT32 addr = GET_REGISTER(~~arm,~~ rd);
	896	UINT32 addr = GET_REGISTER(rd);
673	897	if (addr & 1)
674	898	{
675	899	addr &= ~1;
r24074	r24075
685	909	R15 = addr;
686	910	}
687	911
688		~~const~~ void tg04_01_31(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	912	void arm7_cpu_device::tg04_01_31(UINT32 pc, UINT32 op)
689	913	{
690	914	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
691		UINT32 addr = GET_REGISTER(~~arm,~~ rs+8);
	915	UINT32 addr = GET_REGISTER(rs+8);
692	916	if (rs == 7)
693	917	{
694	918	addr += 2;
r24074	r24075
708	932	R15 = addr;
709	933	}
710	934
711		~~const~~ void tg04_01_32(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	935	void arm7_cpu_device::tg04_01_32(UINT32 pc, UINT32 op)
712	936	{
713	937	fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, op);
714	938	}
715	939
716		~~const~~ void tg04_01_33(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	940	void arm7_cpu_device::tg04_01_33(UINT32 pc, UINT32 op)
717	941	{
718	942	fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, op);
719	943	}
720	944
721		~~const~~ void tg04_0203(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	945	void arm7_cpu_device::tg04_0203(UINT32 pc, UINT32 op)
722	946	{
723	947	UINT32 readword = READ32((R15 & ~2) + 4 + ((op & THUMB_INSN_IMM) << 2));
724		SET_REGISTER(~~arm,~~ (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, readword);
	948	SET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, readword);
725	949	R15 += 2;
726	950	}
727	951
728	952	/* LDR* STR* group */
729	953
730		~~const~~ void tg05_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / STR Rd, [Rn, Rm] */
	954	void arm7_cpu_device::tg05_0(UINT32 pc, UINT32 op) /* STR Rd, [Rn, Rm] */
731	955	{
732	956	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
733	957	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
734	958	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
735		UINT32 addr = GET_REGISTER(arm, rn) + GET_REGISTER(arm, rm);
736		WRITE32(addr, GET_REGISTER(arm, rd));
	959	UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
	960	WRITE32(addr, GET_REGISTER(rd));
737	961	R15 += 2;
738	962	}
739	963
740		~~const~~ void tg05_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / STRH Rd, [Rn, Rm] */
	964	void arm7_cpu_device::tg05_1(UINT32 pc, UINT32 op) /* STRH Rd, [Rn, Rm] */
741	965	{
742	966	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
743	967	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
744	968	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
745		UINT32 addr = GET_REGISTER(arm, rn) + GET_REGISTER(arm, rm);
746		WRITE16(addr, GET_REGISTER(arm, rd));
	969	UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
	970	WRITE16(addr, GET_REGISTER(rd));
747	971	R15 += 2;
748	972	}
749	973
750		~~const~~ void tg05_2(~~arm_state arm,~~ UINT32 pc, UINT32 op) / STRB Rd, [Rn, Rm] */
	974	void arm7_cpu_device::tg05_2(UINT32 pc, UINT32 op) /* STRB Rd, [Rn, Rm] */
751	975	{
752	976	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
753	977	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
754	978	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
755		UINT32 addr = GET_REGISTER(arm, rn) + GET_REGISTER(arm, rm);
756		WRITE8(addr, GET_REGISTER(arm, rd));
	979	UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
	980	WRITE8(addr, GET_REGISTER(rd));
757	981	R15 += 2;
758	982	}
759	983
760		~~const~~ void tg05_3(~~arm_state arm,~~ UINT32 pc, UINT32 op) / LDSB Rd, [Rn, Rm] todo, add dasm */
	984	void arm7_cpu_device::tg05_3(UINT32 pc, UINT32 op) /* LDSB Rd, [Rn, Rm] todo, add dasm */
761	985	{
762	986	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
763	987	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
764	988	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
765		UINT32 addr = GET_REGISTER(ar~~m, r~~n) + GET_REGISTER(~~arm,~~ rm);
	989	UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
766	990	UINT32 op2 = READ8(addr);
767	991	if (op2 & 0x00000080)
768	992	{
769	993	op2 \|= 0xffffff00;
770	994	}
771		SET_REGISTER(~~arm,~~ rd, op2);
	995	SET_REGISTER(rd, op2);
772	996	R15 += 2;
773	997	}
774	998
775		~~const~~ void tg05_4(~~arm_state arm,~~ UINT32 pc, UINT32 op) / LDR Rd, [Rn, Rm] */
	999	void arm7_cpu_device::tg05_4(UINT32 pc, UINT32 op) /* LDR Rd, [Rn, Rm] */
776	1000	{
777	1001	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
778	1002	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
779	1003	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
780		UINT32 addr = GET_REGISTER(ar~~m, r~~n) + GET_REGISTER(~~arm,~~ rm);
	1004	UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
781	1005	UINT32 op2 = READ32(addr);
782		SET_REGISTER(~~arm,~~ rd, op2);
	1006	SET_REGISTER(rd, op2);
783	1007	R15 += 2;
784	1008	}
785	1009
786		~~const~~ void tg05_5(~~arm_state arm,~~ UINT32 pc, UINT32 op) / LDRH Rd, [Rn, Rm] */
	1010	void arm7_cpu_device::tg05_5(UINT32 pc, UINT32 op) /* LDRH Rd, [Rn, Rm] */
787	1011	{
788	1012	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
789	1013	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
790	1014	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
791		UINT32 addr = GET_REGISTER(ar~~m, r~~n) + GET_REGISTER(~~arm,~~ rm);
	1015	UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
792	1016	UINT32 op2 = READ16(addr);
793		SET_REGISTER(~~arm,~~ rd, op2);
	1017	SET_REGISTER(rd, op2);
794	1018	R15 += 2;
795	1019	}
796	1020
797		~~const~~ void tg05_6(~~arm_state arm,~~ UINT32 pc, UINT32 op) / LDRB Rd, [Rn, Rm] */
	1021	void arm7_cpu_device::tg05_6(UINT32 pc, UINT32 op) /* LDRB Rd, [Rn, Rm] */
798	1022	{
799	1023	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
800	1024	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
801	1025	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
802		UINT32 addr = GET_REGISTER(ar~~m, r~~n) + GET_REGISTER(~~arm,~~ rm);
	1026	UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
803	1027	UINT32 op2 = READ8(addr);
804		SET_REGISTER(~~arm,~~ rd, op2);
	1028	SET_REGISTER(rd, op2);
805	1029	R15 += 2;
806	1030	}
807	1031
808		~~const~~ void tg05_7(~~arm_state arm,~~ UINT32 pc, UINT32 op) / LDSH Rd, [Rn, Rm] */
	1032	void arm7_cpu_device::tg05_7(UINT32 pc, UINT32 op) /* LDSH Rd, [Rn, Rm] */
809	1033	{
810	1034	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
811	1035	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
812	1036	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
813		UINT32 addr = GET_REGISTER(ar~~m, r~~n) + GET_REGISTER(~~arm,~~ rm);
	1037	UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
814	1038	UINT32 op2 = READ16(addr);
815	1039	if (op2 & 0x00008000)
816	1040	{
817	1041	op2 \|= 0xffff0000;
818	1042	}
819		SET_REGISTER(~~arm,~~ rd, op2);
	1043	SET_REGISTER(rd, op2);
820	1044	R15 += 2;
821	1045	}
822	1046
823	1047	/* Word Store w/ Immediate Offset */
824	1048
825		~~const~~ void tg06_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Store */
	1049	void arm7_cpu_device::tg06_0(UINT32 pc, UINT32 op) /* Store */
826	1050	{
827	1051	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
828	1052	UINT32 rd = op & THUMB_ADDSUB_RD;
829	1053	INT32 offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
830		WRITE32(GET_REGISTER(ar~~m, r~~n) + offs, GET_REGISTER(~~arm,~~ rd));
	1054	WRITE32(GET_REGISTER(rn) + offs, GET_REGISTER(rd));
831	1055	R15 += 2;
832	1056	}
833	1057
834		~~const~~ void tg06_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Load */
	1058	void arm7_cpu_device::tg06_1(UINT32 pc, UINT32 op) /* Load */
835	1059	{
836	1060	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
837	1061	UINT32 rd = op & THUMB_ADDSUB_RD;
838	1062	INT32 offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
839		SET_REGISTER(ar~~m, r~~d, READ32(GET_REGISTER(~~arm,~~ rn) + offs)); // fix
	1063	SET_REGISTER(rd, READ32(GET_REGISTER(rn) + offs)); // fix
840	1064	R15 += 2;
841	1065	}
842	1066
843	1067	/* Byte Store w/ Immeidate Offset */
844	1068
845		~~const~~ void tg07_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Store */
	1069	void arm7_cpu_device::tg07_0(UINT32 pc, UINT32 op) /* Store */
846	1070	{
847	1071	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
848	1072	UINT32 rd = op & THUMB_ADDSUB_RD;
849	1073	INT32 offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
850		WRITE8(GET_REGISTER(ar~~m, r~~n) + offs, GET_REGISTER(~~arm,~~ rd));
	1074	WRITE8(GET_REGISTER(rn) + offs, GET_REGISTER(rd));
851	1075	R15 += 2;
852	1076	}
853	1077
854		~~const~~ void tg07_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Load */
	1078	void arm7_cpu_device::tg07_1(UINT32 pc, UINT32 op) /* Load */
855	1079	{
856	1080	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
857	1081	UINT32 rd = op & THUMB_ADDSUB_RD;
858	1082	INT32 offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
859		SET_REGISTER(ar~~m, r~~d, READ8(GET_REGISTER(~~arm,~~ rn) + offs));
	1083	SET_REGISTER(rd, READ8(GET_REGISTER(rn) + offs));
860	1084	R15 += 2;
861	1085	}
862	1086
863	1087	/* Load/Store Halfword */
864	1088
865		~~const~~ void tg08_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Store */
	1089	void arm7_cpu_device::tg08_0(UINT32 pc, UINT32 op) /* Store */
866	1090	{
867	1091	UINT32 imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
868	1092	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
869	1093	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
870		WRITE16(GET_REGISTER(ar~~m, r~~s) + (imm << 1), GET_REGISTER(~~arm,~~ rd));
	1094	WRITE16(GET_REGISTER(rs) + (imm << 1), GET_REGISTER(rd));
871	1095	R15 += 2;
872	1096	}
873	1097
874		~~const~~ void tg08_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Load */
	1098	void arm7_cpu_device::tg08_1(UINT32 pc, UINT32 op) /* Load */
875	1099	{
876	1100	UINT32 imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
877	1101	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
878	1102	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
879		SET_REGISTER(ar~~m, r~~d, READ16(GET_REGISTER(~~arm,~~ rs) + (imm << 1)));
	1103	SET_REGISTER(rd, READ16(GET_REGISTER(rs) + (imm << 1)));
880	1104	R15 += 2;
881	1105	}
882	1106
883	1107	/* Stack-Relative Load/Store */
884	1108
885		~~const~~ void tg09_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Store */
	1109	void arm7_cpu_device::tg09_0(UINT32 pc, UINT32 op) /* Store */
886	1110	{
887	1111	UINT32 rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
888	1112	INT32 offs = (UINT8)(op & THUMB_INSN_IMM);
889		WRITE32(GET_REGISTER(~~arm,~~ 13) + ((UINT32)offs << 2), GET_REGISTER(~~arm,~~ rd));
	1113	WRITE32(GET_REGISTER(13) + ((UINT32)offs << 2), GET_REGISTER(rd));
890	1114	R15 += 2;
891	1115	}
892	1116
893		~~const~~ void tg09_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Load */
	1117	void arm7_cpu_device::tg09_1(UINT32 pc, UINT32 op) /* Load */
894	1118	{
895	1119	UINT32 rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
896	1120	INT32 offs = (UINT8)(op & THUMB_INSN_IMM);
897		UINT32 readword = READ32(GET_REGISTER(arm, 13) + ((UINT32)offs << 2));
898		SET_REGISTER(arm, rd, readword);
	1121	UINT32 readword = READ32(GET_REGISTER(13) + ((UINT32)offs << 2));
	1122	SET_REGISTER(rd, readword);
899	1123	R15 += 2;
900	1124	}
901	1125
902	1126	/* Get relative address */
903	1127
904		~~const~~ void tg0a_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ADD Rd, PC, #nn */
	1128	void arm7_cpu_device::tg0a_0(UINT32 pc, UINT32 op) /* ADD Rd, PC, #nn */
905	1129	{
906	1130	UINT32 rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
907	1131	INT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
908		SET_REGISTER(~~arm,~~ rd, ((R15 + 4) & ~2) + offs);
	1132	SET_REGISTER(rd, ((R15 + 4) & ~2) + offs);
909	1133	R15 += 2;
910	1134	}
911	1135
912		~~const~~ void tg0a_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ADD Rd, SP, #nn */
	1136	void arm7_cpu_device::tg0a_1(UINT32 pc, UINT32 op) /* ADD Rd, SP, #nn */
913	1137	{
914	1138	UINT32 rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
915	1139	INT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
916		SET_REGISTER(ar~~m, r~~d, GET_REGISTER(~~arm,~~ 13) + offs);
	1140	SET_REGISTER(rd, GET_REGISTER(13) + offs);
917	1141	R15 += 2;
918	1142	}
919	1143
920	1144	/* Stack-Related Opcodes */
921	1145
922		~~const~~ void tg0b_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / ADD SP, #imm */
	1146	void arm7_cpu_device::tg0b_0(UINT32 pc, UINT32 op) /* ADD SP, #imm */
923	1147	{
924	1148	UINT32 addr = (op & THUMB_INSN_IMM);
925	1149	addr &= ~THUMB_INSN_IMM_S;
926		SET_REGISTER(~~arm,~~ 13, GET_REGISTER(~~arm,~~ 13) + ((op & THUMB_INSN_IMM_S) ? -(addr << 2) : (addr << 2)));
	1150	SET_REGISTER(13, GET_REGISTER(13) + ((op & THUMB_INSN_IMM_S) ? -(addr << 2) : (addr << 2)));
927	1151	R15 += 2;
928	1152	}
929	1153
930		~~const~~ void tg0b_1(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1154	void arm7_cpu_device::tg0b_1(UINT32 pc, UINT32 op)
931	1155	{
932	1156	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
933	1157	}
934	1158
935		~~const~~ void tg0b_2(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1159	void arm7_cpu_device::tg0b_2(UINT32 pc, UINT32 op)
936	1160	{
937	1161	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
938	1162	}
939	1163
940		~~const~~ void tg0b_3(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1164	void arm7_cpu_device::tg0b_3(UINT32 pc, UINT32 op)
941	1165	{
942	1166	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
943	1167	}
944	1168
945		~~const~~ void tg0b_4(~~arm_state arm,~~ UINT32 pc, UINT32 op) / PUSH {Rlist} */
	1169	void arm7_cpu_device::tg0b_4(UINT32 pc, UINT32 op) /* PUSH {Rlist} */
946	1170	{
947	1171	for (INT32 offs = 7; offs >= 0; offs--)
948	1172	{
949	1173	if (op & (1 << offs))
950	1174	{
951		SET_REGISTER(arm, 13, GET_REGISTER(arm, 13) - 4);
952		WRITE32(GET_REGISTER(arm, 13), GET_REGISTER(arm, offs));
	1175	SET_REGISTER(13, GET_REGISTER(13) - 4);
	1176	WRITE32(GET_REGISTER(13), GET_REGISTER(offs));
953	1177	}
954	1178	}
955	1179	R15 += 2;
956	1180	}
957	1181
958		~~const~~ void tg0b_5(~~arm_state arm,~~ UINT32 pc, UINT32 op) / PUSH {Rlist}{LR} */
	1182	void arm7_cpu_device::tg0b_5(UINT32 pc, UINT32 op) /* PUSH {Rlist}{LR} */
959	1183	{
960		SET_REGISTER(arm, 13, GET_REGISTER(arm, 13) - 4);
961		WRITE32(GET_REGISTER(arm, 13), GET_REGISTER(arm, 14));
	1184	SET_REGISTER(13, GET_REGISTER(13) - 4);
	1185	WRITE32(GET_REGISTER(13), GET_REGISTER(14));
962	1186	for (INT32 offs = 7; offs >= 0; offs--)
963	1187	{
964	1188	if (op & (1 << offs))
965	1189	{
966		SET_REGISTER(arm, 13, GET_REGISTER(arm, 13) - 4);
967		WRITE32(GET_REGISTER(arm, 13), GET_REGISTER(arm, offs));
	1190	SET_REGISTER(13, GET_REGISTER(13) - 4);
	1191	WRITE32(GET_REGISTER(13), GET_REGISTER(offs));
968	1192	}
969	1193	}
970	1194	R15 += 2;
971	1195	}
972	1196
973		~~const~~ void tg0b_6(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1197	void arm7_cpu_device::tg0b_6(UINT32 pc, UINT32 op)
974	1198	{
975	1199	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
976	1200	}
977	1201
978		~~const~~ void tg0b_7(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1202	void arm7_cpu_device::tg0b_7(UINT32 pc, UINT32 op)
979	1203	{
980	1204	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
981	1205	}
982	1206
983		~~const~~ void tg0b_8(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1207	void arm7_cpu_device::tg0b_8(UINT32 pc, UINT32 op)
984	1208	{
985	1209	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
986	1210	}
987	1211
988		~~const~~ void tg0b_9(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1212	void arm7_cpu_device::tg0b_9(UINT32 pc, UINT32 op)
989	1213	{
990	1214	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
991	1215	}
992	1216
993		~~const~~ void tg0b_a(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1217	void arm7_cpu_device::tg0b_a(UINT32 pc, UINT32 op)
994	1218	{
995	1219	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
996	1220	}
997	1221
998		~~const~~ void tg0b_b(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1222	void arm7_cpu_device::tg0b_b(UINT32 pc, UINT32 op)
999	1223	{
1000	1224	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1001	1225	}
1002	1226
1003		~~const~~ void tg0b_c(~~arm_state arm,~~ UINT32 pc, UINT32 op) / POP {Rlist} */
	1227	void arm7_cpu_device::tg0b_c(UINT32 pc, UINT32 op) /* POP {Rlist} */
1004	1228	{
1005	1229	for (INT32 offs = 0; offs < 8; offs++)
1006	1230	{
1007	1231	if (op & (1 << offs))
1008	1232	{
1009		SET_REGISTER(arm, offs, READ32(GET_REGISTER(arm, 13)));
1010		SET_REGISTER(arm, 13, GET_REGISTER(arm, 13) + 4);
	1233	SET_REGISTER(offs, READ32(GET_REGISTER(13)));
	1234	SET_REGISTER(13, GET_REGISTER(13) + 4);
1011	1235	}
1012	1236	}
1013	1237	R15 += 2;
1014	1238	}
1015	1239
1016		~~const~~ void tg0b_d(~~arm_state arm,~~ UINT32 pc, UINT32 op) / POP {Rlist}{PC} */
	1240	void arm7_cpu_device::tg0b_d(UINT32 pc, UINT32 op) /* POP {Rlist}{PC} */
1017	1241	{
1018	1242	for (INT32 offs = 0; offs < 8; offs++)
1019	1243	{
1020	1244	if (op & (1 << offs))
1021	1245	{
1022		SET_REGISTER(arm, offs, READ32(GET_REGISTER(arm, 13)));
1023		SET_REGISTER(arm, 13, GET_REGISTER(arm, 13) + 4);
	1246	SET_REGISTER(offs, READ32(GET_REGISTER(13)));
	1247	SET_REGISTER(13, GET_REGISTER(13) + 4);
1024	1248	}
1025	1249	}
1026		UINT32 addr = READ32(GET_REGISTER(arm, 13));
1027		if (arm->archRev < 5)
	1250	UINT32 addr = READ32(GET_REGISTER(13));
	1251	if (m_archRev < 5)
1028	1252	{
1029	1253	R15 = addr & ~1;
1030	1254	}
r24074	r24075
1045	1269
1046	1270	R15 = addr;
1047	1271	}
1048		SET_REGISTER(~~arm,~~ 13, GET_REGISTER(~~arm,~~ 13) + 4);
	1272	SET_REGISTER(13, GET_REGISTER(13) + 4);
1049	1273	}
1050	1274
1051		~~const~~ void tg0b_e(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1275	void arm7_cpu_device::tg0b_e(UINT32 pc, UINT32 op)
1052	1276	{
1053	1277	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1054	1278	}
1055	1279
1056		~~const~~ void tg0b_f(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1280	void arm7_cpu_device::tg0b_f(UINT32 pc, UINT32 op)
1057	1281	{
1058	1282	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1059	1283	}
r24074	r24075
1066	1290	// GBA "BB Ball" performs an unaligned read with A[1:0] = 2 and expects A[1] not to be ignored [BP 800B90A,(R4&3)!=0]
1067	1291	// GBA "Gadget Racers" performs an unaligned read with A[1:0] = 1 and expects A[0] to be ignored [BP B72,(R0&3)!=0]
1068	1292
1069		~~const~~ void tg0c_0(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Store */
	1293	void arm7_cpu_device::tg0c_0(UINT32 pc, UINT32 op) /* Store */
1070	1294	{
1071	1295	UINT32 rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
1072		UINT32 ld_st_address = GET_REGISTER(~~arm,~~ rd);
	1296	UINT32 ld_st_address = GET_REGISTER(rd);
1073	1297	for (INT32 offs = 0; offs < 8; offs++)
1074	1298	{
1075	1299	if (op & (1 << offs))
1076	1300	{
1077		WRITE32(ld_st_address & ~3, GET_REGISTER(~~arm,~~ offs));
	1301	WRITE32(ld_st_address & ~3, GET_REGISTER(offs));
1078	1302	ld_st_address += 4;
1079	1303	}
1080	1304	}
1081		SET_REGISTER(~~arm,~~ rd, ld_st_address);
	1305	SET_REGISTER(rd, ld_st_address);
1082	1306	R15 += 2;
1083	1307	}
1084	1308
1085		~~const~~ void tg0c_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / Load */
	1309	void arm7_cpu_device::tg0c_1(UINT32 pc, UINT32 op) /* Load */
1086	1310	{
1087	1311	UINT32 rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
1088	1312	int rd_in_list = op & (1 << rd);
1089		UINT32 ld_st_address = GET_REGISTER(~~arm,~~ rd);
	1313	UINT32 ld_st_address = GET_REGISTER(rd);
1090	1314	for (INT32 offs = 0; offs < 8; offs++)
1091	1315	{
1092	1316	if (op & (1 << offs))
1093	1317	{
1094		SET_REGISTER(~~arm,~~ offs, READ32(ld_st_address & ~1));
	1318	SET_REGISTER(offs, READ32(ld_st_address & ~1));
1095	1319	ld_st_address += 4;
1096	1320	}
1097	1321	}
1098	1322	if (!rd_in_list)
1099	1323	{
1100		SET_REGISTER(~~arm,~~ rd, ld_st_address);
	1324	SET_REGISTER(rd, ld_st_address);
1101	1325	}
1102	1326	R15 += 2;
1103	1327	}
1104	1328
1105	1329	/* Conditional Branch */
1106	1330
1107		~~const~~ void tg0d_0(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_EQ:
	1331	void arm7_cpu_device::tg0d_0(UINT32 pc, UINT32 op) // COND_EQ:
1108	1332	{
1109	1333	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1110	1334	if (Z_IS_SET(GET_CPSR))
r24074	r24075
1118	1342
1119	1343	}
1120	1344
1121		~~const~~ void tg0d_1(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_NE:
	1345	void arm7_cpu_device::tg0d_1(UINT32 pc, UINT32 op) // COND_NE:
1122	1346	{
1123	1347	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1124	1348	if (Z_IS_CLEAR(GET_CPSR))
r24074	r24075
1131	1355	}
1132	1356	}
1133	1357
1134		~~const~~ void tg0d_2(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_CS:
	1358	void arm7_cpu_device::tg0d_2(UINT32 pc, UINT32 op) // COND_CS:
1135	1359	{
1136	1360	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1137	1361	if (C_IS_SET(GET_CPSR))
r24074	r24075
1144	1368	}
1145	1369	}
1146	1370
1147		~~const~~ void tg0d_3(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_CC:
	1371	void arm7_cpu_device::tg0d_3(UINT32 pc, UINT32 op) // COND_CC:
1148	1372	{
1149	1373	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1150	1374	if (C_IS_CLEAR(GET_CPSR))
r24074	r24075
1157	1381	}
1158	1382	}
1159	1383
1160		~~const~~ void tg0d_4(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_MI:
	1384	void arm7_cpu_device::tg0d_4(UINT32 pc, UINT32 op) // COND_MI:
1161	1385	{
1162	1386	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1163	1387	if (N_IS_SET(GET_CPSR))
r24074	r24075
1170	1394	}
1171	1395	}
1172	1396
1173		~~const~~ void tg0d_5(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_PL:
	1397	void arm7_cpu_device::tg0d_5(UINT32 pc, UINT32 op) // COND_PL:
1174	1398	{
1175	1399	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1176	1400	if (N_IS_CLEAR(GET_CPSR))
r24074	r24075
1183	1407	}
1184	1408	}
1185	1409
1186		~~const~~ void tg0d_6(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_VS:
	1410	void arm7_cpu_device::tg0d_6(UINT32 pc, UINT32 op) // COND_VS:
1187	1411	{
1188	1412	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1189	1413	if (V_IS_SET(GET_CPSR))
r24074	r24075
1196	1420	}
1197	1421	}
1198	1422
1199		~~const~~ void tg0d_7(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_VC:
	1423	void arm7_cpu_device::tg0d_7(UINT32 pc, UINT32 op) // COND_VC:
1200	1424	{
1201	1425	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1202	1426	if (V_IS_CLEAR(GET_CPSR))
r24074	r24075
1209	1433	}
1210	1434	}
1211	1435
1212		~~const~~ void tg0d_8(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_HI:
	1436	void arm7_cpu_device::tg0d_8(UINT32 pc, UINT32 op) // COND_HI:
1213	1437	{
1214	1438	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1215	1439	if (C_IS_SET(GET_CPSR) && Z_IS_CLEAR(GET_CPSR))
r24074	r24075
1222	1446	}
1223	1447	}
1224	1448
1225		~~const~~ void tg0d_9(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_LS:
	1449	void arm7_cpu_device::tg0d_9(UINT32 pc, UINT32 op) // COND_LS:
1226	1450	{
1227	1451	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1228	1452	if (C_IS_CLEAR(GET_CPSR) \|\| Z_IS_SET(GET_CPSR))
r24074	r24075
1235	1459	}
1236	1460	}
1237	1461
1238		~~const~~ void tg0d_a(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_GE:
	1462	void arm7_cpu_device::tg0d_a(UINT32 pc, UINT32 op) // COND_GE:
1239	1463	{
1240	1464	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1241	1465	if (!(GET_CPSR & N_MASK) == !(GET_CPSR & V_MASK))
r24074	r24075
1248	1472	}
1249	1473	}
1250	1474
1251		~~const~~ void tg0d_b(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_LT:
	1475	void arm7_cpu_device::tg0d_b(UINT32 pc, UINT32 op) // COND_LT:
1252	1476	{
1253	1477	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1254	1478	if (!(GET_CPSR & N_MASK) != !(GET_CPSR & V_MASK))
r24074	r24075
1261	1485	}
1262	1486	}
1263	1487
1264		~~const~~ void tg0d_c(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_GT:
	1488	void arm7_cpu_device::tg0d_c(UINT32 pc, UINT32 op) // COND_GT:
1265	1489	{
1266	1490	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1267	1491	if (Z_IS_CLEAR(GET_CPSR) && !(GET_CPSR & N_MASK) == !(GET_CPSR & V_MASK))
r24074	r24075
1274	1498	}
1275	1499	}
1276	1500
1277		~~const~~ void tg0d_d(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_LE:
	1501	void arm7_cpu_device::tg0d_d(UINT32 pc, UINT32 op) // COND_LE:
1278	1502	{
1279	1503	INT32 offs = (INT8)(op & THUMB_INSN_IMM);
1280	1504	if (Z_IS_SET(GET_CPSR) \|\| !(GET_CPSR & N_MASK) != !(GET_CPSR & V_MASK))
r24074	r24075
1287	1511	}
1288	1512	}
1289	1513
1290		~~const~~ void tg0d_e(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_AL:
	1514	void arm7_cpu_device::tg0d_e(UINT32 pc, UINT32 op) // COND_AL:
1291	1515	{
1292	1516	fatalerror("%08x: Undefined Thumb instruction: %04x (ARM9 reserved)\n", pc, op);
1293	1517	}
1294	1518
1295		~~const~~ void tg0d_f(~~arm_state *arm,~~ UINT32 pc, UINT32 op) // COND_NV: // SWI (this is sort of a "hole" in the opcode encoding)
	1519	void arm7_cpu_device::tg0d_f(UINT32 pc, UINT32 op) // COND_NV: // SWI (this is sort of a "hole" in the opcode encoding)
1296	1520	{
1297		arm->pendingSwi = 1;
	1521	m_pendingSwi = 1;
1298	1522	ARM7_CHECKIRQ;
1299	1523	}
1300	1524
1301	1525	/* B #offs */
1302	1526
1303		~~const~~ void tg0e_0(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1527	void arm7_cpu_device::tg0e_0(UINT32 pc, UINT32 op)
1304	1528	{
1305	1529	INT32 offs = (op & THUMB_BRANCH_OFFS) << 1;
1306	1530	if (offs & 0x00000800)
r24074	r24075
1310	1534	R15 += 4 + offs;
1311	1535	}
1312	1536
1313		~~const~~ void tg0e_1(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1537	void arm7_cpu_device::tg0e_1(UINT32 pc, UINT32 op)
1314	1538	{
1315		UINT32 addr = GET_REGISTER(~~arm,~~ 14);
	1539	UINT32 addr = GET_REGISTER(14);
1316	1540	addr += (op & THUMB_BLOP_OFFS) << 1;
1317	1541	addr &= 0xfffffffc;
1318		SET_REGISTER(~~arm,~~ 14, (R15 + 4) \| 1);
	1542	SET_REGISTER(14, (R15 + 4) \| 1);
1319	1543	R15 = addr;
1320	1544	}
1321	1545
1322	1546	/* BL */
1323	1547
1324		~~const~~ void tg0f_0(~~arm_state *arm,~~ UINT32 pc, UINT32 op)
	1548	void arm7_cpu_device::tg0f_0(UINT32 pc, UINT32 op)
1325	1549	{
1326	1550	UINT32 addr = (op & THUMB_BLOP_OFFS) << 12;
1327	1551	if (addr & (1 << 22))
r24074	r24075
1329	1553	addr \|= 0xff800000;
1330	1554	}
1331	1555	addr += R15 + 4;
1332		SET_REGISTER(~~arm,~~ 14, addr);
	1556	SET_REGISTER(14, addr);
1333	1557	R15 += 2;
1334	1558	}
1335	1559
1336		~~const~~ void tg0f_1(~~arm_state arm,~~ UINT32 pc, UINT32 op) / BL */
	1560	void arm7_cpu_device::tg0f_1(UINT32 pc, UINT32 op) /* BL */
1337	1561	{
1338		UINT32 addr = GET_REGISTER(~~arm,~~ 14) & ~1;
	1562	UINT32 addr = GET_REGISTER(14) & ~1;
1339	1563	addr += (op & THUMB_BLOP_OFFS) << 1;
1340		SET_REGISTER(~~arm,~~ 14, (R15 + 2) \| 1);
	1564	SET_REGISTER(14, (R15 + 2) \| 1);
1341	1565	R15 = addr;
1342	1566	//R15 += 2;
1343	1567	}

trunk/src/emu/cpu/arm7/arm7tdrc.c
r24074	r24075
1	1	#include "emu.h"
2	2	#include "arm7core.h"
3		#include "arm7thmb.h"
4	3	#include "arm7help.h"
5	4
6		#ifdef ARM7_USE_DRC
7	5
8		arm7thumb_drcophandler drcthumb_handler[0x40*0x10] =
	6	const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[0x40*0x10] =
9	7	{
10	8	// #define THUMB_SHIFT_R ((UINT16)0x0800)
11		drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0,
12		drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0,
13		drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0,
14		drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0,
15		drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1,
16		drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1,
17		drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1,
18		drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1,
	9	&arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
	10	&arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
	11	&arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
	12	&arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
	13	&arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
	14	&arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
	15	&arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
	16	&arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
19	17	// #define THUMB_INSN_ADDSUB ((UINT16)0x0800) // #define THUMB_ADDSUB_TYPE ((UINT16)0x0600)
20		drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0,
21		drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0,
22		drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0,
23		drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0,
24		drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10,
25		drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11,
26		drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12,
27		drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13,
	18	&arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
	19	&arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
	20	&arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
	21	&arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
	22	&arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10,
	23	&arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11,
	24	&arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12,
	25	&arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13,
28	26	// #define THUMB_INSN_CMP ((UINT16)0x0800)
29		drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0,
30		drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0,
31		drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0,
32		drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0,
33		drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1,
34		drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1,
35		drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1,
36		drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1,
	27	&arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
	28	&arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
	29	&arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
	30	&arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
	31	&arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
	32	&arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
	33	&arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
	34	&arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
37	35	// #define THUMB_INSN_SUB ((UINT16)0x0800)
38		drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0,
39		drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0,
40		drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0,
41		drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0,
42		drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1,
43		drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1,
44		drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1,
45		drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1,
	36	&arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
	37	&arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
	38	&arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
	39	&arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
	40	&arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
	41	&arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
	42	&arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
	43	&arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
46	44	//#define THUMB_GROUP4_TYPE ((UINT16)0x0c00) //#define THUMB_ALUOP_TYPE ((UINT16)0x03c0) // #define THUMB_HIREG_OP ((UINT16)0x0300) // #define THUMB_HIREG_H ((UINT16)0x00c0)
47		drctg04_00_00, drctg04_00_01, drctg04_00_02, drctg04_00_03, drctg04_00_04, drctg04_00_05, drctg04_00_06, drctg04_00_07,
48		drctg04_00_08, drctg04_00_09, drctg04_00_0a, drctg04_00_0b, drctg04_00_0c, drctg04_00_0d, drctg04_00_0e, drctg04_00_0f,
49		drctg04_01_00, drctg04_01_01, drctg04_01_02, drctg04_01_03, drctg04_01_10, drctg04_01_11, drctg04_01_12, drctg04_01_13,
50		drctg04_01_20, drctg04_01_21, drctg04_01_22, drctg04_01_23, drctg04_01_30, drctg04_01_31, drctg04_01_32, drctg04_01_33,
51		drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203,
52		drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203,
53		drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203,
54		drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203,
	45	&arm7_cpu_device::drctg04_00_00, &arm7_cpu_device::drctg04_00_01, &arm7_cpu_device::drctg04_00_02, &arm7_cpu_device::drctg04_00_03, &arm7_cpu_device::drctg04_00_04, &arm7_cpu_device::drctg04_00_05, &arm7_cpu_device::drctg04_00_06, &arm7_cpu_device::drctg04_00_07,
	46	&arm7_cpu_device::drctg04_00_08, &arm7_cpu_device::drctg04_00_09, &arm7_cpu_device::drctg04_00_0a, &arm7_cpu_device::drctg04_00_0b, &arm7_cpu_device::drctg04_00_0c, &arm7_cpu_device::drctg04_00_0d, &arm7_cpu_device::drctg04_00_0e, &arm7_cpu_device::drctg04_00_0f,
	47	&arm7_cpu_device::drctg04_01_00, &arm7_cpu_device::drctg04_01_01, &arm7_cpu_device::drctg04_01_02, &arm7_cpu_device::drctg04_01_03, &arm7_cpu_device::drctg04_01_10, &arm7_cpu_device::drctg04_01_11, &arm7_cpu_device::drctg04_01_12, &arm7_cpu_device::drctg04_01_13,
	48	&arm7_cpu_device::drctg04_01_20, &arm7_cpu_device::drctg04_01_21, &arm7_cpu_device::drctg04_01_22, &arm7_cpu_device::drctg04_01_23, &arm7_cpu_device::drctg04_01_30, &arm7_cpu_device::drctg04_01_31, &arm7_cpu_device::drctg04_01_32, &arm7_cpu_device::drctg04_01_33,
	49	&arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
	50	&arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
	51	&arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
	52	&arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
55	53	//#define THUMB_GROUP5_TYPE ((UINT16)0x0e00)
56		drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0,
57		drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1,
58		drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2,
59		drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3,
60		drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4,
61		drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5,
62		drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6,
63		drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7,
	54	&arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0,
	55	&arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1,
	56	&arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2,
	57	&arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3,
	58	&arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4,
	59	&arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5,
	60	&arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6,
	61	&arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7,
64	62	//#define THUMB_LSOP_L ((UINT16)0x0800)
65		drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0,
66		drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0,
67		drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0,
68		drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0,
69		drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1,
70		drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1,
71		drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1,
72		drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1,
	63	&arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
	64	&arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
	65	&arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
	66	&arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
	67	&arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
	68	&arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
	69	&arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
	70	&arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
73	71	//#define THUMB_LSOP_L ((UINT16)0x0800)
74		drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0,
75		drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0,
76		drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0,
77		drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0,
78		drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1,
79		drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1,
80		drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1,
81		drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1,
	72	&arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
	73	&arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
	74	&arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
	75	&arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
	76	&arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
	77	&arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
	78	&arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
	79	&arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
82	80	// #define THUMB_HALFOP_L ((UINT16)0x0800)
83		drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0,
84		drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0,
85		drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0,
86		drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0,
87		drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1,
88		drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1,
89		drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1,
90		drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1,
	81	&arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
	82	&arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
	83	&arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
	84	&arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
	85	&arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
	86	&arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
	87	&arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
	88	&arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
91	89	// #define THUMB_STACKOP_L ((UINT16)0x0800)
92		drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0,
93		drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0,
94		drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0,
95		drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0,
96		drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1,
97		drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1,
98		drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1,
99		drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1,
	90	&arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
	91	&arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
	92	&arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
	93	&arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
	94	&arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
	95	&arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
	96	&arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
	97	&arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
100	98	// #define THUMB_RELADDR_SP ((UINT16)0x0800)
101		drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0,
102		drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0,
103		drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0,
104		drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0,
105		drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1,
106		drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1,
107		drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1,
108		drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1,
	99	&arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
	100	&arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
	101	&arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
	102	&arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
	103	&arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
	104	&arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
	105	&arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
	106	&arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
109	107	// #define THUMB_STACKOP_TYPE ((UINT16)0x0f00)
110		drctg0b_0, drctg0b_0, drctg0b_0, drctg0b_0, drctg0b_1, drctg0b_1, drctg0b_1, drctg0b_1,
111		drctg0b_2, drctg0b_2, drctg0b_2, drctg0b_2, drctg0b_3, drctg0b_3, drctg0b_3, drctg0b_3,
112		drctg0b_4, drctg0b_4, drctg0b_4, drctg0b_4, drctg0b_5, drctg0b_5, drctg0b_5, drctg0b_5,
113		drctg0b_6, drctg0b_6, drctg0b_6, drctg0b_6, drctg0b_7, drctg0b_7, drctg0b_7, drctg0b_7,
114		drctg0b_8, drctg0b_8, drctg0b_8, drctg0b_8, drctg0b_9, drctg0b_9, drctg0b_9, drctg0b_9,
115		drctg0b_a, drctg0b_a, drctg0b_a, drctg0b_a, drctg0b_b, drctg0b_b, drctg0b_b, drctg0b_b,
116		drctg0b_c, drctg0b_c, drctg0b_c, drctg0b_c, drctg0b_d, drctg0b_d, drctg0b_d, drctg0b_d,
117		drctg0b_e, drctg0b_e, drctg0b_e, drctg0b_e, drctg0b_f, drctg0b_f, drctg0b_f, drctg0b_f,
	108	&arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_1, &arm7_cpu_device::drctg0b_1, &arm7_cpu_device::drctg0b_1, &arm7_cpu_device::drctg0b_1,
	109	&arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_3, &arm7_cpu_device::drctg0b_3, &arm7_cpu_device::drctg0b_3, &arm7_cpu_device::drctg0b_3,
	110	&arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_5, &arm7_cpu_device::drctg0b_5, &arm7_cpu_device::drctg0b_5, &arm7_cpu_device::drctg0b_5,
	111	&arm7_cpu_device::drctg0b_6, &arm7_cpu_device::drctg0b_6, &arm7_cpu_device::drctg0b_6, &arm7_cpu_device::drctg0b_6, &arm7_cpu_device::drctg0b_7, &arm7_cpu_device::drctg0b_7, &arm7_cpu_device::drctg0b_7, &arm7_cpu_device::drctg0b_7,
	112	&arm7_cpu_device::drctg0b_8, &arm7_cpu_device::drctg0b_8, &arm7_cpu_device::drctg0b_8, &arm7_cpu_device::drctg0b_8, &arm7_cpu_device::drctg0b_9, &arm7_cpu_device::drctg0b_9, &arm7_cpu_device::drctg0b_9, &arm7_cpu_device::drctg0b_9,
	113	&arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_b, &arm7_cpu_device::drctg0b_b, &arm7_cpu_device::drctg0b_b, &arm7_cpu_device::drctg0b_b,
	114	&arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_d, &arm7_cpu_device::drctg0b_d, &arm7_cpu_device::drctg0b_d, &arm7_cpu_device::drctg0b_d,
	115	&arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_f, &arm7_cpu_device::drctg0b_f, &arm7_cpu_device::drctg0b_f, &arm7_cpu_device::drctg0b_f,
118	116	// #define THUMB_MULTLS ((UINT16)0x0800)
119		drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0,
120		drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0,
121		drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0,
122		drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0,
123		drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1,
124		drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1,
125		drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1,
126		drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1,
	117	&arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
	118	&arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
	119	&arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
	120	&arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
	121	&arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
	122	&arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
	123	&arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
	124	&arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
127	125	// #define THUMB_COND_TYPE ((UINT16)0x0f00)
128		drctg0d_0, drctg0d_0, drctg0d_0, drctg0d_0, drctg0d_1, drctg0d_1, drctg0d_1, drctg0d_1,
129		drctg0d_2, drctg0d_2, drctg0d_2, drctg0d_2, drctg0d_3, drctg0d_3, drctg0d_3, drctg0d_3,
130		drctg0d_4, drctg0d_4, drctg0d_4, drctg0d_4, drctg0d_5, drctg0d_5, drctg0d_5, drctg0d_5,
131		drctg0d_6, drctg0d_6, drctg0d_6, drctg0d_6, drctg0d_7, drctg0d_7, drctg0d_7, drctg0d_7,
132		drctg0d_8, drctg0d_8, drctg0d_8, drctg0d_8, drctg0d_9, drctg0d_9, drctg0d_9, drctg0d_9,
133		drctg0d_a, drctg0d_a, drctg0d_a, drctg0d_a, drctg0d_b, drctg0d_b, drctg0d_b, drctg0d_b,
134		drctg0d_c, drctg0d_c, drctg0d_c, drctg0d_c, drctg0d_d, drctg0d_d, drctg0d_d, drctg0d_d,
135		drctg0d_e, drctg0d_e, drctg0d_e, drctg0d_e, drctg0d_f, drctg0d_f, drctg0d_f, drctg0d_f,
	126	&arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_1, &arm7_cpu_device::drctg0d_1, &arm7_cpu_device::drctg0d_1, &arm7_cpu_device::drctg0d_1,
	127	&arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_3, &arm7_cpu_device::drctg0d_3, &arm7_cpu_device::drctg0d_3, &arm7_cpu_device::drctg0d_3,
	128	&arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_5, &arm7_cpu_device::drctg0d_5, &arm7_cpu_device::drctg0d_5, &arm7_cpu_device::drctg0d_5,
	129	&arm7_cpu_device::drctg0d_6, &arm7_cpu_device::drctg0d_6, &arm7_cpu_device::drctg0d_6, &arm7_cpu_device::drctg0d_6, &arm7_cpu_device::drctg0d_7, &arm7_cpu_device::drctg0d_7, &arm7_cpu_device::drctg0d_7, &arm7_cpu_device::drctg0d_7,
	130	&arm7_cpu_device::drctg0d_8, &arm7_cpu_device::drctg0d_8, &arm7_cpu_device::drctg0d_8, &arm7_cpu_device::drctg0d_8, &arm7_cpu_device::drctg0d_9, &arm7_cpu_device::drctg0d_9, &arm7_cpu_device::drctg0d_9, &arm7_cpu_device::drctg0d_9,
	131	&arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_b, &arm7_cpu_device::drctg0d_b, &arm7_cpu_device::drctg0d_b, &arm7_cpu_device::drctg0d_b,
	132	&arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_d, &arm7_cpu_device::drctg0d_d, &arm7_cpu_device::drctg0d_d, &arm7_cpu_device::drctg0d_d,
	133	&arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_f, &arm7_cpu_device::drctg0d_f, &arm7_cpu_device::drctg0d_f, &arm7_cpu_device::drctg0d_f,
136	134	// #define THUMB_BLOP_LO ((UINT16)0x0800)
137		drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0,
138		drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0,
139		drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0,
140		drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0,
141		drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1,
142		drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1,
143		drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1,
144		drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1,
	135	&arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
	136	&arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
	137	&arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
	138	&arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
	139	&arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
	140	&arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
	141	&arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
	142	&arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
145	143	// #define THUMB_BLOP_LO ((UINT16)0x0800)
146		drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0,
147		drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0,
148		drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0,
149		drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0,
150		drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1,
151		drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1,
152		drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1,
153		drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1,
	144	&arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
	145	&arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
	146	&arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
	147	&arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
	148	&arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1,
	149	&arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1,
	150	&arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1,
	151	&arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1,
154	152	};
155	153
156	154	/* Shift operations */
157	155
158		~~const~~ void drctg00_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Shift left */
	156	void arm7_cpu_device::drctg00_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Shift left */
159	157	{
160	158	UINT32 op = desc->opptr.l[0];
161		UINT32 pc = desc->pc;
162	159	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
163	160	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
164	161	INT32 offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
165	162
166		UML_MOV(block, I0, DRC_RS); // rrs
	163	UML_MOV(block, uml::I0, DRC_RS); // rrs
167	164	if (offs != 0)
168	165	{
169	166	UML_SHL(block, DRC_RD, DRC_RS, offs);
170	167	UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
171		UML_TEST(block, I0, 1 << (31 - (offs - 1)));
172		UML_MOVc(block, COND_NZ, I1, C_MASK);
173		UML_MOVc(block, COND_Z, I1, 0);
174		UML_OR(block, DRC_CPSR, I1);
	168	UML_TEST(block, uml::I0, 1 << (31 - (offs - 1)));
	169	UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
	170	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	171	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
175	172	}
176	173	else
177	174	{
r24074	r24075
179	176	}
180	177	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
181	178	DRCHandleALUNZFlags(DRC_RD);
182		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	179	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
183	180	UML_ADD(block, DRC_PC, DRC_PC, 2);
184	181	}
185	182
186		~~const~~ void drctg00_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Shift right */
	183	void arm7_cpu_device::drctg00_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Shift right */
187	184	{
188	185	UINT32 op = desc->opptr.l[0];
189		UINT32 pc = desc->pc;
190	186	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
191	187	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
192	188	INT32 offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
193	189
194		UML_MOV(block, I0, DRC_RS); // rrs
	190	UML_MOV(block, uml::I0, DRC_RS); // rrs
195	191	if (offs != 0)
196	192	{
197	193	UML_SHR(block, DRC_RD, DRC_RS, offs);
198	194	UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
199		UML_TEST(block, I0, 1 << (31 - (offs - 1)));
200		UML_MOVc(block, COND_NZ, I1, C_MASK);
201		UML_MOVc(block, COND_Z, I1, 0);
202		UML_OR(block, DRC_CPSR, I1);
	195	UML_TEST(block, uml::I0, 1 << (31 - (offs - 1)));
	196	UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
	197	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	198	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
203	199	}
204	200	else
205	201	{
206	202	UML_MOV(block, DRC_RD, 0);
207	203	UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
208		UML_TEST(block, I0, 0x80000000);
209		UML_MOVc(block, COND_NZ, I1, C_MASK);
210		UML_MOVc(block, COND_Z, I1, 0);
211		UML_OR(block, DRC_CPSR, I1);
	204	UML_TEST(block, uml::I0, 0x80000000);
	205	UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
	206	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	207	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
212	208	}
213	209	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
214	210	DRCHandleALUNZFlags(DRC_RD);
215		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	211	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
216	212	UML_ADD(block, DRC_PC, DRC_PC, 2);
217	213	}
218	214
219	215	/* Arithmetic */
220	216
221		~~const~~ void drctg01_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	217	void arm7_cpu_device::drctg01_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
222	218	{
223	219	UINT32 op = desc->opptr.l[0];
224		UINT32 pc = desc->pc;
225	220	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
226	221	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
227	222	INT32 offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
228	223
229	224	/* ASR.. */
230		UML_MOV(block, I0, DRC_RS);
	225	UML_MOV(block, uml::I0, DRC_RS);
231	226	if (offs == 0)
232	227	{
233	228	offs = 32;
r24074	r24075
235	230	if (offs >= 32)
236	231	{
237	232	UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
238		UML_SHR(block, I1, I0, 31);
239		UML_TEST(block, I1, ~0);
240		UML_MOVc(block, COND_NZ, I1, C_MASK);
241		UML_MOVc(block, COND_Z, I1, 0);
242		UML_OR(block, DRC_CPSR, DRC_CPSR, I1);
243		UML_TEST(block, I0, 0x80000000);
244		UML_MOVc(block, COND_NZ, DRC_RD, ~0);
245		UML_MOVc(block, COND_Z, DRC_RD, 0);
	233	UML_SHR(block, uml::I1, uml::I0, 31);
	234	UML_TEST(block, uml::I1, ~0);
	235	UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
	236	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	237	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
	238	UML_TEST(block, uml::I0, 0x80000000);
	239	UML_MOVc(block, uml::COND_NZ, DRC_RD, ~0);
	240	UML_MOVc(block, uml::COND_Z, DRC_RD, 0);
246	241	}
247	242	else
248	243	{
249	244	UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
250		UML_TEST(block, I0, 1 << (offs - 1));
251		UML_MOVc(block, COND_NZ, I1, C_MASK);
252		UML_MOVc(block, COND_Z, I1, 0);
253		UML_OR(block, DRC_CPSR, DRC_CPSR, I1);
254		UML_SHR(block, I1, I0, offs);
255		UML_SHL(block, I2, ~0, 32 - offs);
256		UML_TEST(block, I0, 0x80000000);
257		UML_MOVc(block, COND_Z, I2, 0);
258		UML_OR(block, DRC_RD, I1, I2);
	245	UML_TEST(block, uml::I0, 1 << (offs - 1));
	246	UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
	247	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	248	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
	249	UML_SHR(block, uml::I1, uml::I0, offs);
	250	UML_SHL(block, uml::I2, ~0, 32 - offs);
	251	UML_TEST(block, uml::I0, 0x80000000);
	252	UML_MOVc(block, uml::COND_Z, uml::I2, 0);
	253	UML_OR(block, DRC_RD, uml::I1, uml::I2);
259	254	}
260	255	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
261	256	DRCHandleALUNZFlags(DRC_RD);
262		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	257	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
263	258	UML_ADD(block, DRC_PC, DRC_PC, 2);
264	259	}
265	260
266		~~const~~ void drctg01_10(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	261	void arm7_cpu_device::drctg01_10(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
267	262	{
268	263	UINT32 op = desc->opptr.l[0];
269	264	UINT32 rn = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
r24074	r24075
273	268	DRCHandleThumbALUAddFlags(DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
274	269	}
275	270
276		~~const~~ void drctg01_11(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* SUB Rd, Rs, Rn */
	271	void arm7_cpu_device::drctg01_11(drcuml_block block, compiler_state compiler, const opcode_desc desc) / SUB Rd, Rs, Rn */
277	272	{
278	273	UINT32 op = desc->opptr.l[0];
279	274	UINT32 rn = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
r24074	r24075
283	278	DRCHandleThumbALUSubFlags(DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
284	279	}
285	280
286		~~const~~ void drctg01_12(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ADD Rd, Rs, #imm */
	281	void arm7_cpu_device::drctg01_12(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ADD Rd, Rs, #imm */
287	282	{
288	283	UINT32 op = desc->opptr.l[0];
289	284	UINT32 imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
r24074	r24075
293	288	DRCHandleThumbALUAddFlags(DRC_REG(rd), DRC_REG(rs), imm);
294	289	}
295	290
296		~~const~~ void drctg01_13(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* SUB Rd, Rs, #imm */
	291	void arm7_cpu_device::drctg01_13(drcuml_block block, compiler_state compiler, const opcode_desc desc) / SUB Rd, Rs, #imm */
297	292	{
298	293	UINT32 op = desc->opptr.l[0];
299	294	UINT32 imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
r24074	r24075
305	300
306	301	/* CMP / MOV */
307	302
308		~~const~~ void drctg02_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	303	void arm7_cpu_device::drctg02_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
309	304	{
310	305	UINT32 op = desc->opptr.l[0];
311	306	UINT32 rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
r24074	r24075
313	308	UML_MOV(block, DRC_REG(rd), op2);
314	309	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
315	310	DRCHandleALUNZFlags(DRC_REG(rd));
316		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	311	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
317	312	UML_ADD(block, DRC_PC, DRC_PC, 2);
318	313	}
319	314
320		~~const~~ void drctg02_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	315	void arm7_cpu_device::drctg02_1(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
321	316	{
322	317	UINT32 op = desc->opptr.l[0];
323	318	UINT32 rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
324	319	UINT32 op2 = op & THUMB_INSN_IMM;
325	320
326		UML_SUB(block, I3, DRC_REG(rn), op2);
327		DRCHandleThumbALUSubFlags(I3, DRC_REG(rn), op2);
	321	UML_SUB(block, uml::I3, DRC_REG(rn), op2);
	322	DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rn), op2);
328	323	}
329	324
330	325	/* ADD/SUB immediate */
331	326
332		~~const~~ void drctg03_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ADD Rd, #Offset8 */
	327	void arm7_cpu_device::drctg03_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ADD Rd, #Offset8 */
333	328	{
334	329	UINT32 op = desc->opptr.l[0];
335	330	UINT32 rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
r24074	r24075
339	334	DRCHandleThumbALUAddFlags(DRC_REG(rd), DRC_REG(rn), op2);
340	335	}
341	336
342		~~const~~ void drctg03_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* SUB Rd, #Offset8 */
	337	void arm7_cpu_device::drctg03_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / SUB Rd, #Offset8 */
343	338	{
344	339	UINT32 op = desc->opptr.l[0];
345	340	UINT32 rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
r24074	r24075
351	346
352	347	/* Rd & Rm instructions */
353	348
354		~~const~~ void drctg04_00_00(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* AND Rd, Rs */
	349	void arm7_cpu_device::drctg04_00_00(drcuml_block block, compiler_state compiler, const opcode_desc desc) / AND Rd, Rs */
355	350	{
356	351	UINT32 op = desc->opptr.l[0];
357	352	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
r24074	r24075
359	354	UML_AND(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs));
360	355	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
361	356	DRCHandleALUNZFlags(DRC_REG(rd));
362		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	357	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
363	358	UML_ADD(block, DRC_PC, DRC_PC, 2);
364	359	}
365	360
366		~~const~~ void drctg04_00_01(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* EOR Rd, Rs */
	361	void arm7_cpu_device::drctg04_00_01(drcuml_block block, compiler_state compiler, const opcode_desc desc) / EOR Rd, Rs */
367	362	{
368	363	UINT32 op = desc->opptr.l[0];
369	364	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
r24074	r24075
371	366	UML_XOR(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs));
372	367	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
373	368	DRCHandleALUNZFlags(DRC_REG(rd));
374		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	369	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
375	370	UML_ADD(block, DRC_PC, DRC_PC, 2);
376	371	}
377	372
378		~~const~~ void drctg04_00_02(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* LSL Rd, Rs */
	373	void arm7_cpu_device::drctg04_00_02(drcuml_block block, compiler_state compiler, const opcode_desc desc) / LSL Rd, Rs */
379	374	{
380	375	UINT32 op = desc->opptr.l[0];
381	376	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
382	377	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
383		code_label skip;
384		code_label offsg32;
385		code_label offs32;
	378	uml::code_label skip;
	379	uml::code_label offsg32;
	380	uml::code_label offs32;
386	381
387		UML_AND(block, I1, DRC_REG(rs), 0xff);
	382	UML_AND(block, uml::I1, DRC_REG(rs), 0xff);
388	383	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK \| C_MASK));
389	384
390		UML_CMP(block, I1, 0);
391		UML_JMPc(block, COND_E, skip = compiler->labelnum++);
	385	UML_CMP(block, uml::I1, 0);
	386	UML_JMPc(block, uml::COND_E, skip = compiler->labelnum++);
392	387
393		UML_CMP(block, I1, 32);
394		UML_JMPc(block, COND_A, offsg32 = compiler->labelnum++);
395		UML_JMPc(block, COND_E, offs32 = compiler->labelnum++);
	388	UML_CMP(block, uml::I1, 32);
	389	UML_JMPc(block, uml::COND_A, offsg32 = compiler->labelnum++);
	390	UML_JMPc(block, uml::COND_E, offs32 = compiler->labelnum++);
396	391
397		UML_SHL(block, DRC_REG(rd), DRC_REG(rd), I1);
398		UML_SUB(block, I1, I1, 1);
399		UML_SUB(block, I1, 31, I1);
400		UML_SHL(block, I1, 1, I1);
401		UML_TEST(block, DRC_REG(rd), I1);
402		UML_MOVc(block, COND_NZ, I0, C_MASK);
403		UML_MOVc(block, COND_Z, I0, 0);
404		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	392	UML_SHL(block, DRC_REG(rd), DRC_REG(rd), uml::I1);
	393	UML_SUB(block, uml::I1, uml::I1, 1);
	394	UML_SUB(block, uml::I1, 31, uml::I1);
	395	UML_SHL(block, uml::I1, 1, uml::I1);
	396	UML_TEST(block, DRC_REG(rd), uml::I1);
	397	UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
	398	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
	399	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
405	400	UML_JMP(block, skip);
406	401
407	402	UML_LABEL(block, offs32);
408	403	UML_TEST(block, DRC_REG(rd), 1);
409		UML_MOVc(block, COND_NZ, I0, C_MASK);
410		UML_MOVc(block, COND_Z, I0, 0);
411		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	404	UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
	405	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
	406	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
412	407	UML_MOV(block, DRC_REG(rd), 0);
413	408	UML_JMP(block, skip);
414	409
r24074	r24075
418	413	UML_LABEL(block, skip);
419	414
420	415	DRCHandleALUNZFlags(DRC_REG(rd));
421		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	416	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
422	417	UML_ADD(block, DRC_PC, DRC_PC, 2);
423	418	}
424	419
425		~~const~~ void drctg04_00_03(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* LSR Rd, Rs */
	420	void arm7_cpu_device::drctg04_00_03(drcuml_block block, compiler_state compiler, const opcode_desc desc) / LSR Rd, Rs */
426	421	{
427	422	UINT32 op = desc->opptr.l[0];
428	423	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
429	424	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
430		code_label skip;
431		code_label offsg32;
432		code_label offs32;
	425	uml::code_label skip;
	426	uml::code_label offsg32;
	427	uml::code_label offs32;
433	428
434		UML_AND(block, I1, DRC_REG(rs), 0xff);
	429	UML_AND(block, uml::I1, DRC_REG(rs), 0xff);
435	430	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK \| C_MASK));
436		UML_CMP(block, I1, 0);
437		UML_JMPc(block, COND_E, skip = compiler->labelnum++);
	431	UML_CMP(block, uml::I1, 0);
	432	UML_JMPc(block, uml::COND_E, skip = compiler->labelnum++);
438	433
439		UML_CMP(block, I1, 32);
440		UML_JMPc(block, COND_A, offsg32 = compiler->labelnum++);
441		UML_JMPc(block, COND_E, offs32 = compiler->labelnum++);
	434	UML_CMP(block, uml::I1, 32);
	435	UML_JMPc(block, uml::COND_A, offsg32 = compiler->labelnum++);
	436	UML_JMPc(block, uml::COND_E, offs32 = compiler->labelnum++);
442	437
443		UML_SHR(block, DRC_REG(rd), DRC_REG(rd), I1);
444		UML_SUB(block, I1, 1);
445		UML_SHL(block, I1, 1, I1);
446		UML_TEST(block, DRC_REG(rd), I1);
447		UML_MOVc(block, COND_NZ, I0, C_MASK);
448		UML_MOVc(block, COND_Z, I0, 0);
449		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	438	UML_SHR(block, DRC_REG(rd), DRC_REG(rd), uml::I1);
	439	UML_SUB(block, uml::I1, uml::I1, 1); // WP: TODO, Check this used to be "block, I1, 1"
	440	UML_SHL(block, uml::I1, 1, uml::I1);
	441	UML_TEST(block, DRC_REG(rd), uml::I1);
	442	UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
	443	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
	444	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
450	445	UML_JMP(block, skip);
451	446
452	447	UML_LABEL(block, offs32);
453	448	UML_TEST(block, DRC_REG(rd), 0x80000000);
454		UML_MOVc(block, COND_NZ, I0, C_MASK);
455		UML_MOVc(block, COND_Z, I0, 0);
456		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	449	UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
	450	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
	451	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
457	452	UML_MOV(block, DRC_REG(rd), 0);
458	453	UML_JMP(block, skip);
459	454
r24074	r24075
463	458	UML_LABEL(block, skip);
464	459
465	460	DRCHandleALUNZFlags(DRC_REG(rd));
466		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	461	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
467	462	UML_ADD(block, DRC_PC, DRC_PC, 2);
468	463	}
469	464
470		~~const~~ void drctg04_00_04(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ASR Rd, Rs */
	465	void arm7_cpu_device::drctg04_00_04(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ASR Rd, Rs */
471	466	{
472	467	UINT32 op = desc->opptr.l[0];
473	468	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
474	469	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
475		code_label skip;
476		code_label offsg32;
477		code_label offs32;
	470	uml::code_label skip;
	471	uml::code_label offsg32;
	472	uml::code_label offs32;
478	473
479		UML_MOV(block, I0, DRC_REG(rd));
480		UML_AND(block, I1, DRC_REG(rs), 0xff);
	474	UML_MOV(block, uml::I0, DRC_REG(rd));
	475	UML_AND(block, uml::I1, DRC_REG(rs), 0xff);
481	476	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK \| C_MASK));
482		UML_CMP(block, I1, 0);
483		UML_JMPc(block, COND_E, skip = compiler->labelnum++);
	477	UML_CMP(block, uml::I1, 0);
	478	UML_JMPc(block, uml::COND_E, skip = compiler->labelnum++);
484	479
485		UML_SHR(block, I2, I0, I1);
486		UML_SUB(block, I1, 32, I1);
487		UML_SHL(block, I1, ~0, I1);
488		UML_TEST(block, I0, 0x80000000);
489		UML_MOVc(block, COND_NZ, DRC_REG(RD), I1);
490		UML_MOVc(block, COND_Z, DRC_REG(RD), 0);
491		UML_OR(block, DRC_REG(rd), DRC_REG(RD), I2);
492		UML_JMPc(block, COND_B, offsl32 = compiler->labelnum++);
	480	UML_SHR(block, uml::I2, uml::I0, uml::I1);
	481	UML_SUB(block, uml::I1, 32, uml::I1);
	482	UML_SHL(block, uml::I1, ~0, uml::I1);
	483	UML_TEST(block, uml::I0, 0x80000000);
	484	UML_MOVc(block, uml::COND_NZ, DRC_REG(rd), uml::I1);
	485	UML_MOVc(block, uml::COND_Z, DRC_REG(rd), 0);
	486	UML_OR(block, DRC_REG(rd), DRC_REG(rd), uml::I2);
	487	UML_JMPc(block, uml::COND_B, offs32 = compiler->labelnum++);
493	488
494		UML_TEST(block, I0, 0x80000000);
495		UML_MOVc(block, COND_NZ, DRC_REG(rd), ~0);
496		UML_MOVc(block, COND_Z, DRC_REG(rd), 0);
497		UML_MOVc(block, COND_NZ, I1, C_MASK);
498		UML_MOVc(block, COND_Z, I1, 0);
499		UML_OR(block, DRC_CPSR, DRC_CPSR, I1);
	489	UML_TEST(block, uml::I0, 0x80000000);
	490	UML_MOVc(block, uml::COND_NZ, DRC_REG(rd), ~0);
	491	UML_MOVc(block, uml::COND_Z, DRC_REG(rd), 0);
	492	UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
	493	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	494	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
500	495	UML_JMP(block, skip);
501	496
502		UML_LABEL(block, offsl32);
503		UML_SUB(block, I1, I1, 1);
504		UML_SHL(block, I1, 1, I1);
505		UML_TEST(block, I0, I1);
506		UML_MOVc(block, COND_NZ, I1, C_MASK);
507		UML_MOVc(block, COND_Z, I1, 0);
508		UML_OR(block, DRC_CPSR, DRC_CPSR, I1);
	497	UML_LABEL(block, offs32);
	498	UML_SUB(block, uml::I1, uml::I1, 1);
	499	UML_SHL(block, uml::I1, 1, uml::I1);
	500	UML_TEST(block, uml::I0, uml::I1);
	501	UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
	502	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	503	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
509	504	UML_JMP(block, skip);
510	505
511	506	UML_LABEL(block, skip);
512	507	DRCHandleALUNZFlags(DRC_REG(rd));
513		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	508	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
514	509	UML_ADD(block, DRC_PC, DRC_PC, 2);
515	510
516	511	}
517	512
518		~~const~~ void drctg04_00_05(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ADC Rd, Rs */
	513	void arm7_cpu_device::drctg04_00_05(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ADC Rd, Rs */
519	514	{
520	515	UINT32 op = desc->opptr.l[0];
521	516	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
522	517	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
523	518	UML_TEST(block, DRC_CPSR, C_MASK);
524		UML_MOVc(block, COND_NZ, I3, 1);
525		UML_MOVc(block, COND_Z, I3, 0);
526		UML_ADD(block, I3, I3, DRC_REG(rd);
527		UML_ADD(block, I3, I3, DRC_REG(rs);
528		DRCHandleThumbALUAddFlags(I3, DRC_REG(rd), DRC_REG(rs));
529		UML_MOV(block, DRC_REG(rd), I3);
	519	UML_MOVc(block, uml::COND_NZ, uml::I3, 1);
	520	UML_MOVc(block, uml::COND_Z, uml::I3, 0);
	521	UML_ADD(block, uml::I3, uml::I3, DRC_REG(rd));
	522	UML_ADD(block, uml::I3, uml::I3, DRC_REG(rs));
	523	DRCHandleThumbALUAddFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
	524	UML_MOV(block, DRC_REG(rd), uml::I3);
530	525	}
531	526
532		~~const~~ void drctg04_00_06(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* SBC Rd, Rs */
	527	void arm7_cpu_device::drctg04_00_06(drcuml_block block, compiler_state compiler, const opcode_desc desc) / SBC Rd, Rs */
533	528	{
	529	UINT32 op = desc->opptr.l[0];
534	530	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
535	531	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
536	532	UML_TEST(block, DRC_CPSR, C_MASK);
537		UML_MOVc(block, COND_NZ, I3, 0);
538		UML_MOVc(block, COND_Z, I3, 1);
539		UML_SUB(block, I3, DRC_REG(rs), I3);
540		UML_ADD(block, I3, DRC_REG(rd), I3);
541		DRCHandleThumbALUSubFlags(I3, DRC_REG(rd), DRC_REG(rs));
542		UML_MOV(block, DRC_REG(rd), I3);
	533	UML_MOVc(block, uml::COND_NZ, uml::I3, 0);
	534	UML_MOVc(block, uml::COND_Z, uml::I3, 1);
	535	UML_SUB(block, uml::I3, DRC_REG(rs), uml::I3);
	536	UML_ADD(block, uml::I3, DRC_REG(rd), uml::I3);
	537	DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
	538	UML_MOV(block, DRC_REG(rd), uml::I3);
543	539	}
544	540
545		~~const~~ void drctg04_00_07(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ROR Rd, Rs */
	541	void arm7_cpu_device::drctg04_00_07(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ROR Rd, Rs */
546	542	{
547	543	UINT32 op = desc->opptr.l[0];
548	544	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
549	545	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
550		UML_MOV(block, I0, DRC_REG(rd));
551		UML_AND(block, I1, DRC_REG(rs), 0x1f);
552		UML_SHR(block, DRC_REG(rd), I0, I1);
553		UML_SUB(block, I2, 32, I1);
554		UML_SHL(block( I2, I0, I2);
555		UML_OR(block, DRC_REG(rd), DRC_REG(rd), I2);
556		UML_SUB(block, I1, I1, 1);
557		UML_SHL(block, I1, 1, I1);
558		UML_TEST(block, I0, I1);
559		UML_MOVc(block, COND_NZ, I0, C_MASK);
560		UML_MOVc(block, COND_Z, I0, 0);
	546	UML_MOV(block, uml::I0, DRC_REG(rd));
	547	UML_AND(block, uml::I1, DRC_REG(rs), 0x1f);
	548	UML_SHR(block, DRC_REG(rd), uml::I0, uml::I1);
	549	UML_SUB(block, uml::I2, 32, uml::I1);
	550	UML_SHL(block, uml::I2, uml::I0, uml::I2);
	551	UML_OR(block, DRC_REG(rd), DRC_REG(rd), uml::I2);
	552	UML_SUB(block, uml::I1, uml::I1, 1);
	553	UML_SHL(block, uml::I1, 1, uml::I1);
	554	UML_TEST(block, uml::I0, uml::I1);
	555	UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
	556	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
561	557	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK \| C_MASK));
562	558	DRCHandleALUNZFlags(DRC_REG(rd));
563		UML_OR(block, DRC_CSPR, DRC_CPSR, I0);
	559	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
564	560	UML_ADD(block, DRC_PC, DRC_PC, 2);
565	561	}
566	562
567		~~const~~ void drctg04_00_08(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* TST Rd, Rs */
	563	void arm7_cpu_device::drctg04_00_08(drcuml_block block, compiler_state compiler, const opcode_desc desc) / TST Rd, Rs */
568	564	{
569	565	UINT32 op = desc->opptr.l[0];
570	566	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
571	567	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
572	568	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
573		UML_AND(block, I2, DRC_REG(rd), DRC_REG(rs));
574		DRCHandleALUNZFlags(I2);
575		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	569	UML_AND(block, uml::I2, DRC_REG(rd), DRC_REG(rs));
	570	DRCHandleALUNZFlags(uml::I2);
	571	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
576	572	UML_ADD(block, DRC_PC, DRC_PC, 2);
577	573	}
578	574
579		~~const~~ void drctg04_00_09(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* NEG Rd, Rs */
	575	void arm7_cpu_device::drctg04_00_09(drcuml_block block, compiler_state compiler, const opcode_desc desc) / NEG Rd, Rs */
580	576	{
581	577	UINT32 op = desc->opptr.l[0];
582	578	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
583	579	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
584		UML_MOV(block, I3, DRC_REG(rs));
585		UML_SUB(block, DRC_REG(rd), 0, I3);
586		DRCHandleThumbALUSubFlags(DRC_REG(rd), 0, I3);
	580	UML_MOV(block, uml::I3, DRC_REG(rs));
	581	UML_SUB(block, DRC_REG(rd), 0, uml::I3);
	582	DRCHandleThumbALUSubFlags(DRC_REG(rd), 0, uml::I3);
587	583	}
588	584
589		~~const~~ void drctg04_00_0a(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* CMP Rd, Rs */
	585	void arm7_cpu_device::drctg04_00_0a(drcuml_block block, compiler_state compiler, const opcode_desc desc) / CMP Rd, Rs */
590	586	{
591	587	UINT32 op = desc->opptr.l[0];
592	588	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
593	589	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
594		UML_SUB(block, I3, DRC_REG(rd), DRC_REG(rs));
595		DRCHandleThumbALUSubFlags(I3, DRC_REG(rd), DRC_REG(rs));
	590	UML_SUB(block, uml::I3, DRC_REG(rd), DRC_REG(rs));
	591	DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
596	592	}
597	593
598		~~const~~ void drctg04_00_0b(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* CMN Rd, Rs - check flags, add dasm */
	594	void arm7_cpu_device::drctg04_00_0b(drcuml_block block, compiler_state compiler, const opcode_desc desc) / CMN Rd, Rs - check flags, add dasm */
599	595	{
600	596	UINT32 op = desc->opptr.l[0];
601	597	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
602	598	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
603		UML_ADD(block, I3, DRC_REG(rd), DRC_REG(rs));
604		DRCHandleThumbALUAddFlags(I3, DRC_REG(rd), DRC_REG(rs));
	599	UML_ADD(block, uml::I3, DRC_REG(rd), DRC_REG(rs));
	600	DRCHandleThumbALUAddFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
605	601	}
606	602
607		~~const~~ void drctg04_00_0c(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ORR Rd, Rs */
	603	void arm7_cpu_device::drctg04_00_0c(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ORR Rd, Rs */
608	604	{
609	605	UINT32 op = desc->opptr.l[0];
610	606	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
r24074	r24075
612	608	UML_OR(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs));
613	609	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
614	610	DRCHandleALUNZFlags(DRC_REG(rd));
615		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	611	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
616	612	UML_ADD(block, DRC_PC, DRC_PC, 2);
617	613	}
618	614
619		~~const~~ void drctg04_00_0d(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* MUL Rd, Rs */
	615	void arm7_cpu_device::drctg04_00_0d(drcuml_block block, compiler_state compiler, const opcode_desc desc) / MUL Rd, Rs */
620	616	{
621	617	UINT32 op = desc->opptr.l[0];
622	618	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
623	619	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
624	620	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
625		UML_MULU(block, DRC_REG(rd), I1, DRC_REG(rd), DRC_REG(rs));
	621	UML_MULU(block, DRC_REG(rd), uml::I1, DRC_REG(rd), DRC_REG(rs));
626	622	DRCHandleALUNZFlags(DRC_REG(rd));
627		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	623	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
628	624	UML_ADD(block, DRC_PC, DRC_PC, 2);
629	625	}
630	626
631		~~const~~ void drctg04_00_0e(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* BIC Rd, Rs */
	627	void arm7_cpu_device::drctg04_00_0e(drcuml_block block, compiler_state compiler, const opcode_desc desc) / BIC Rd, Rs */
632	628	{
633	629	UINT32 op = desc->opptr.l[0];
634	630	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
635	631	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
636	632	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
637		UML_XOR(block, I0, DRC_REG(rs), ~0);
638		UML_AND(block, DRC_REG(rd), DRC_REG(rd), I0);
	633	UML_XOR(block, uml::I0, DRC_REG(rs), ~0);
	634	UML_AND(block, DRC_REG(rd), DRC_REG(rd), uml::I0);
639	635	DRCHandleALUNZFlags(DRC_REG(rd));
640		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	636	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
641	637	UML_ADD(block, DRC_PC, DRC_PC, 2);
642	638	}
643	639
644		~~const~~ void drctg04_00_0f(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* MVN Rd, Rs */
	640	void arm7_cpu_device::drctg04_00_0f(drcuml_block block, compiler_state compiler, const opcode_desc desc) / MVN Rd, Rs */
645	641	{
646	642	UINT32 op = desc->opptr.l[0];
647	643	UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
648	644	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
649		UML_XOR(block, I0, DRC_REG(rs), ~0);
650		UML_MOV(block, DRC_REG(rd), I0);
	645	UML_XOR(block, uml::I0, DRC_REG(rs), ~0);
	646	UML_MOV(block, DRC_REG(rd), uml::I0);
651	647	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK \| N_MASK));
652	648	DRCHandleALUNZFlags(DRC_REG(rd));
653		UML_OR(block, DRC_CPSR, DRC_CPSR, I0);
	649	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
654	650	UML_ADD(block, DRC_PC, DRC_PC, 2);
655	651	}
656	652
657	653	/* ADD Rd, Rs group */
658	654
659		~~const~~ void drctg04_01_00(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	655	void arm7_cpu_device::drctg04_01_00(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
660	656	{
661	657	UINT32 op = desc->opptr.l[0];
	658	UINT32 pc = desc->pc;
662	659	fatalerror("%08x: G4-1-0 Undefined Thumb instruction: %04x %x\n", pc, op, (op & THUMB_HIREG_H) >> THUMB_HIREG_H_SHIFT);
663	660	}
664	661
665		~~const~~ void drctg04_01_01(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ADD Rd, HRs */
	662	void arm7_cpu_device::drctg04_01_01(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ADD Rd, HRs */
666	663	{
667	664	UINT32 op = desc->opptr.l[0];
668	665	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
r24074	r24075
675	672	UML_ADD(block, DRC_PC, DRC_PC, 2);
676	673	}
677	674
678		~~const~~ void drctg04_01_02(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ADD HRd, Rs */
	675	void arm7_cpu_device::drctg04_01_02(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ADD HRd, Rs */
679	676	{
680	677	UINT32 op = desc->opptr.l[0];
681	678	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
r24074	r24075
688	685	UML_ADD(block, DRC_PC, DRC_PC, 2);
689	686	}
690	687
691		~~const~~ void drctg04_01_03(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Add HRd, HRs */
	688	void arm7_cpu_device::drctg04_01_03(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Add HRd, HRs */
692	689	{
693	690	UINT32 op = desc->opptr.l[0];
694	691	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
r24074	r24075
706	703	UML_ADD(block, DRC_PC, DRC_PC, 2);
707	704	}
708	705
709		~~const~~ void drctg04_01_10(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* CMP Rd, Rs */
	706	void arm7_cpu_device::drctg04_01_10(drcuml_block block, compiler_state compiler, const opcode_desc desc) / CMP Rd, Rs */
710	707	{
711	708	UINT32 op = desc->opptr.l[0];
712	709	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
713	710	UINT32 rd = op & THUMB_HIREG_RD;
714		UML_SUB(block, I3, DRC_REG(rd), DRC_REG(rs));
715		DRCHandleThumbALUSubFlags(I3, DRC_REG(rd), DRC_REG(rs));
	711	UML_SUB(block, uml::I3, DRC_REG(rd), DRC_REG(rs));
	712	DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
716	713	}
717	714
718		~~const~~ void drctg04_01_11(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* CMP Rd, Hs */
	715	void arm7_cpu_device::drctg04_01_11(drcuml_block block, compiler_state compiler, const opcode_desc desc) / CMP Rd, Hs */
719	716	{
720	717	UINT32 op = desc->opptr.l[0];
721	718	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
722	719	UINT32 rd = op & THUMB_HIREG_RD;
723		UML_SUB(block, I3, DRC_REG(rd), DRC_REG(rs+8));
724		DRCHandleThumbALUSubFlags(I3, DRC_REG(rd), DRC_REG(rs+8));
	720	UML_SUB(block, uml::I3, DRC_REG(rd), DRC_REG(rs+8));
	721	DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs+8));
725	722	}
726	723
727		~~const~~ void drctg04_01_12(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* CMP Hd, Rs */
	724	void arm7_cpu_device::drctg04_01_12(drcuml_block block, compiler_state compiler, const opcode_desc desc) / CMP Hd, Rs */
728	725	{
729	726	UINT32 op = desc->opptr.l[0];
730		UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
	727	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
731	728	UINT32 rd = op & THUMB_HIREG_RD;
732		UML_SUB(block, I3, DRC_REG(rd+8), DRC_REG(rs));
733		DRCHandleThumbALUSubFlags(I3, DRC_REG(rd+8), DRC_REG(rs));
	729	UML_SUB(block, uml::I3, DRC_REG(rd+8), DRC_REG(rs));
	730	DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd+8), DRC_REG(rs));
734	731	}
735	732
736		~~const~~ void drctg04_01_13(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* CMP Hd, Hs */
	733	void arm7_cpu_device::drctg04_01_13(drcuml_block block, compiler_state compiler, const opcode_desc desc) / CMP Hd, Hs */
737	734	{
738	735	UINT32 op = desc->opptr.l[0];
739		UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
	736	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
740	737	UINT32 rd = op & THUMB_HIREG_RD;
741		UML_SUB(block, I3, DRC_REG(rd+8), DRC_REG(rs+8));
742		DRCHandleThumbALUSubFlags(I3, DRC_REG(rd+8), DRC_REG(rs+8));
	738	UML_SUB(block, uml::I3, DRC_REG(rd+8), DRC_REG(rs+8));
	739	DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd+8), DRC_REG(rs+8));
743	740	}
744	741
745	742	/* MOV group */
746	743
747		~~const~~ void drctg04_01_20(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* MOV Rd, Rs (undefined) */
	744	void arm7_cpu_device::drctg04_01_20(drcuml_block block, compiler_state compiler, const opcode_desc desc) / MOV Rd, Rs (undefined) */
748	745	{
749	746	UINT32 op = desc->opptr.l[0];
750	747	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
r24074	r24075
753	750	UML_ADD(block, DRC_PC, DRC_PC, 2);
754	751	}
755	752
756		~~const~~ void drctg04_01_21(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* MOV Rd, Hs */
	753	void arm7_cpu_device::drctg04_01_21(drcuml_block block, compiler_state compiler, const opcode_desc desc) / MOV Rd, Hs */
757	754	{
758	755	UINT32 op = desc->opptr.l[0];
759	756	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
r24074	r24075
766	763	UML_ADD(block, DRC_PC, DRC_PC, 2);
767	764	}
768	765
769		~~const~~ void drctg04_01_22(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* MOV Hd, Rs */
	766	void arm7_cpu_device::drctg04_01_22(drcuml_block block, compiler_state compiler, const opcode_desc desc) / MOV Hd, Rs */
770	767	{
771	768	UINT32 op = desc->opptr.l[0];
772	769	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
r24074	r24075
783	780	}
784	781	}
785	782
786		~~const~~ void drctg04_01_23(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* MOV Hd, Hs */
	783	void arm7_cpu_device::drctg04_01_23(drcuml_block block, compiler_state compiler, const opcode_desc desc) / MOV Hd, Hs */
787	784	{
788	785	UINT32 op = desc->opptr.l[0];
789	786	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
r24074	r24075
804	801
805	802	}
806	803
807		~~const~~ void drctg04_01_30(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	804	void arm7_cpu_device::drctg04_01_30(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
808	805	{
809	806	UINT32 op = desc->opptr.l[0];
810		code_label switch_state;
811		code_label done;
	807	uml::code_label switch_state;
	808	uml::code_label done;
812	809	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
813		UML_MOV(block, I0, DRC_REG(rs);
814		UML_TEST(block, I0, 1);
815		UML_JMPc(block, COND_Z, switch_state = compiler->labelnum++);
816		UML_AND(block, I0, I0, ~1);
	810	UML_MOV(block, uml::I0, DRC_REG(rs));
	811	UML_TEST(block, uml::I0, 1);
	812	UML_JMPc(block, uml::COND_Z, switch_state = compiler->labelnum++);
	813	UML_AND(block, uml::I0, uml::I0, ~1);
817	814	UML_JMP(block, done = compiler->labelnum++);
818	815
819	816	UML_LABEL(block, switch_state);
820	817	UML_AND(block, DRC_CPSR, DRC_CPSR, ~T_MASK);
821		UML_TEST(block, I0, 2);
822		UML_MOVc(block, COND_NZ, I1, 2);
823		UML_MOVc(block, COND_Z, I1, 0);
824		UML_ADD(block, I0, I0, I1);
	818	UML_TEST(block, uml::I0, 2);
	819	UML_MOVc(block, uml::COND_NZ, uml::I1, 2);
	820	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	821	UML_ADD(block, uml::I0, uml::I0, uml::I1);
825	822
826	823	UML_LABEL(block, done);
827		UML_MOV(block, DRC_PC, I0);
	824	UML_MOV(block, DRC_PC, uml::I0);
828	825	}
829	826
830		~~const~~ void drctg04_01_31(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	827	void arm7_cpu_device::drctg04_01_31(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
831	828	{
832	829	UINT32 op = desc->opptr.l[0];
833		code_label switch_state;
834		code_label done;
	830	uml::code_label switch_state;
	831	uml::code_label done;
835	832	UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
836		UML_MOV(block, I0, DRC_REG(rs+8);
	833	UML_MOV(block, uml::I0, DRC_REG(rs+8));
837	834	if(rs == 7)
838	835	{
839		UML_ADD(block, I0, I0, 2);
	836	UML_ADD(block, uml::I0, uml::I0, 2);
840	837	}
841		UML_TEST(block, I0, 1);
842		UML_JMPc(block, COND_Z, switch_state = compiler->labelnum++);
843		UML_AND(block, I0, I0, ~1);
	838	UML_TEST(block, uml::I0, 1);
	839	UML_JMPc(block, uml::COND_Z, switch_state = compiler->labelnum++);
	840	UML_AND(block, uml::I0, uml::I0, ~1);
844	841	UML_JMP(block, done = compiler->labelnum++);
845	842
846	843	UML_LABEL(block, switch_state);
847	844	UML_AND(block, DRC_CPSR, DRC_CPSR, ~T_MASK);
848		UML_TEST(block, I0, 2);
849		UML_MOVc(block, COND_NZ, I1, 2);
850		UML_MOVc(block, COND_Z, I1, 0);
851		UML_ADD(block, I0, I0, I1);
	845	UML_TEST(block, uml::I0, 2);
	846	UML_MOVc(block, uml::COND_NZ, uml::I1, 2);
	847	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	848	UML_ADD(block, uml::I0, uml::I0, uml::I1);
852	849
853	850	UML_LABEL(block, done);
854		UML_MOV(block, DRC_PC, I0);
	851	UML_MOV(block, DRC_PC, uml::I0);
855	852	}
856	853
857		~~const~~ void drctg04_01_32(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	854	void arm7_cpu_device::drctg04_01_32(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
858	855	{
859	856	UINT32 op = desc->opptr.l[0];
	857	UINT32 pc = desc->pc;
860	858	fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, op);
861	859	}
862	860
863		~~const~~ void drctg04_01_33(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	861	void arm7_cpu_device::drctg04_01_33(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
864	862	{
865	863	UINT32 op = desc->opptr.l[0];
	864	UINT32 pc = desc->pc;
866	865	fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, op);
867	866	}
868	867
869		~~const~~ void drctg04_0203(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	868	void arm7_cpu_device::drctg04_0203(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
870	869	{
871	870	UINT32 op = desc->opptr.l[0];
872	871	UINT32 rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
873	872	UINT32 imm = 4 + ((op & THUMB_INSN_IMM) << 2);
874		UML_AND(block, I0, DRC_PC, ~2);
875		UML_ADD(block, I0, I0, imm);
876		UML_CALLH(block, *arm->impstate->read32);
877		UML_MOV(block, DRC_REG(rd), I0);
	873	UML_AND(block, uml::I0, DRC_PC, ~2);
	874	UML_ADD(block, uml::I0, uml::I0, imm);
	875	UML_CALLH(block, *m_impstate.read32);
	876	UML_MOV(block, DRC_REG(rd), uml::I0);
878	877	UML_ADD(block, DRC_PC, DRC_PC, 2);
879	878	}
880	879
881	880	/* LDR* STR* group */
882	881
883		~~const~~ void drctg05_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* STR Rd, [Rn, Rm] */
	882	void arm7_cpu_device::drctg05_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / STR Rd, [Rn, Rm] */
884	883	{
885	884	UINT32 op = desc->opptr.l[0];
886	885	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
887	886	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
888	887	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
889		UINT32 addr = GET_REGISTER(arm, rn) + GET_REGISTER(arm, rm);
890		UML_MOV(block, I1, DRC_REG(rd));
891		UML_ADD(block, I0, DRC_REG(rn), DRC_REG(rm));
892		UML_CALLH(block, *arm->impstate->write32);
	888	UML_MOV(block, uml::I1, DRC_REG(rd));
	889	UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
	890	UML_CALLH(block, *m_impstate.write32);
893	891	UML_ADD(block, DRC_PC, DRC_PC, 2);
894	892	}
895	893
896		~~const~~ void drctg05_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* STRH Rd, [Rn, Rm] */
	894	void arm7_cpu_device::drctg05_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / STRH Rd, [Rn, Rm] */
897	895	{
898	896	UINT32 op = desc->opptr.l[0];
899	897	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
900	898	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
901	899	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
902		UML_MOV(block, I1, DRC_REG(rd));
903		UML_ADD(block, I0, DRC_REG(rn), DRC_REG(rm));
904		UML_CALLH(block, *arm->impstate->write16);
	900	UML_MOV(block, uml::I1, DRC_REG(rd));
	901	UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
	902	UML_CALLH(block, *m_impstate.write16);
905	903	UML_ADD(block, DRC_PC, DRC_PC, 2);
906	904	}
907	905
908		~~const~~ void drctg05_2(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* STRB Rd, [Rn, Rm] */
	906	void arm7_cpu_device::drctg05_2(drcuml_block block, compiler_state compiler, const opcode_desc desc) / STRB Rd, [Rn, Rm] */
909	907	{
910	908	UINT32 op = desc->opptr.l[0];
911	909	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
912	910	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
913	911	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
914		UINT32 addr = GET_REGISTER(arm, rn) + GET_REGISTER(arm, rm);
915		UML_MOV(block, I1, DRC_REG(rd));
916		UML_ADD(block, I0, DRC_REG(rn), DRC_REG(rm));
917		UML_CALLH(block, *arm->impstate->write16);
	912	UML_MOV(block, uml::I1, DRC_REG(rd));
	913	UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
	914	UML_CALLH(block, *m_impstate.write16);
918	915	UML_ADD(block, DRC_PC, DRC_PC, 2);
919	916	}
920	917
921		~~const~~ void drctg05_3(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* LDSB Rd, [Rn, Rm] todo, add dasm */
	918	void arm7_cpu_device::drctg05_3(drcuml_block block, compiler_state compiler, const opcode_desc desc) / LDSB Rd, [Rn, Rm] todo, add dasm */
922	919	{
923	920	UINT32 op = desc->opptr.l[0];
924	921	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
925	922	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
926	923	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
927		UML_ADD(block, I0, DRC_REG(rn), DRC_REG(rm));
928		UML_CALLH(block, *arm->impstate->read8);
929		UML_SEXT(block, DRC_REG(rd), I0, SIZE_BYTE);
	924	UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
	925	UML_CALLH(block, *m_impstate.read8);
	926	UML_SEXT(block, DRC_REG(rd), uml::I0, uml::SIZE_BYTE);
930	927	UML_ADD(block, DRC_PC, DRC_PC, 2);
931	928	}
932	929
933		~~const~~ void drctg05_4(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* LDR Rd, [Rn, Rm] */
	930	void arm7_cpu_device::drctg05_4(drcuml_block block, compiler_state compiler, const opcode_desc desc) / LDR Rd, [Rn, Rm] */
934	931	{
935	932	UINT32 op = desc->opptr.l[0];
936	933	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
937	934	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
938	935	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
939		UML_ADD(block, I0, DRC_REG(rn), DRC_REG(rm));
940		UML_CALLH(block, *arm->impstate->read32);
941		UML_MOV(block, DRC_REG(rd), I0);
	936	UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
	937	UML_CALLH(block, *m_impstate.read32);
	938	UML_MOV(block, DRC_REG(rd), uml::I0);
942	939	UML_ADD(block, DRC_PC, DRC_PC, 2);
943	940	}
944	941
945		~~const~~ void drctg05_5(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* LDRH Rd, [Rn, Rm] */
	942	void arm7_cpu_device::drctg05_5(drcuml_block block, compiler_state compiler, const opcode_desc desc) / LDRH Rd, [Rn, Rm] */
946	943	{
947	944	UINT32 op = desc->opptr.l[0];
948	945	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
949	946	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
950	947	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
951		UML_ADD(block, I0, DRC_REG(rn), DRC_REG(rm));
952		UML_CALLH(block, *arm->impstate->read16);
953		UML_MOV(block, DRC_REG(rd), I0);
	948	UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
	949	UML_CALLH(block, *m_impstate.read16);
	950	UML_MOV(block, DRC_REG(rd), uml::I0);
954	951	UML_ADD(block, DRC_PC, DRC_PC, 2);
955	952	}
956	953
957		~~const~~ void drctg05_6(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* LDRB Rd, [Rn, Rm] */
	954	void arm7_cpu_device::drctg05_6(drcuml_block block, compiler_state compiler, const opcode_desc desc) / LDRB Rd, [Rn, Rm] */
958	955	{
959	956	UINT32 op = desc->opptr.l[0];
960	957	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
961	958	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
962	959	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
963		UML_ADD(block, I0, DRC_REG(rn), DRC_REG(rm));
964		UML_CALLH(block, *arm->impstate->read8);
965		UML_MOV(block, DRC_REG(rd), I0);
	960	UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
	961	UML_CALLH(block, *m_impstate.read8);
	962	UML_MOV(block, DRC_REG(rd), uml::I0);
966	963	UML_ADD(block, DRC_PC, DRC_PC, 2);
967	964	}
968	965
969		~~const~~ void drctg05_7(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* LDSH Rd, [Rn, Rm] */
	966	void arm7_cpu_device::drctg05_7(drcuml_block block, compiler_state compiler, const opcode_desc desc) / LDSH Rd, [Rn, Rm] */
970	967	{
971	968	UINT32 op = desc->opptr.l[0];
972	969	UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
973	970	UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
974	971	UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
975		UML_ADD(block, I0, DRC_REG(rn), DRC_REG(rm));
976		UML_CALLH(block, *arm->impstate->read16);
977		UML_SEXT(block, DRC_REG(rd), I0, SIZE_WORD);
	972	UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
	973	UML_CALLH(block, *m_impstate.read16);
	974	UML_SEXT(block, DRC_REG(rd), uml::I0, uml::SIZE_WORD);
978	975	UML_ADD(block, DRC_PC, DRC_PC, 2);
979	976	}
980	977
981	978	/* Word Store w/ Immediate Offset */
982	979
983		~~const~~ void drctg06_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Store */
	980	void arm7_cpu_device::drctg06_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Store */
984	981	{
985	982	UINT32 op = desc->opptr.l[0];
986	983	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
987	984	UINT32 rd = op & THUMB_ADDSUB_RD;
988	985	INT32 offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
989		UML_ADD(block, I0, DRC_REG(rn), offs);
990		UML_MOV(block, I1, DRC_REG(rd));
991		UML_CALLH(block, *arm->impstate->write32);
	986	UML_ADD(block, uml::I0, DRC_REG(rn), offs);
	987	UML_MOV(block, uml::I1, DRC_REG(rd));
	988	UML_CALLH(block, *m_impstate.write32);
992	989	UML_ADD(block, DRC_PC, DRC_PC, 2);
993	990	}
994	991
995		~~const~~ void drctg06_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Load */
	992	void arm7_cpu_device::drctg06_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Load */
996	993	{
997	994	UINT32 op = desc->opptr.l[0];
998	995	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
999	996	UINT32 rd = op & THUMB_ADDSUB_RD;
1000	997	INT32 offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
1001		UML_ADD(block, I0, DRC_REG(rn), offs);
1002		UML_CALLH(block, *arm->impstate->read32);
1003		UML_MOV(block, DRC_REG(rd), I0);
	998	UML_ADD(block, uml::I0, DRC_REG(rn), offs);
	999	UML_CALLH(block, *m_impstate.read32);
	1000	UML_MOV(block, DRC_REG(rd), uml::I0);
1004	1001	UML_ADD(block, DRC_PC, DRC_PC, 2);
1005	1002	}
1006	1003
1007	1004	/* Byte Store w/ Immeidate Offset */
1008	1005
1009		~~const~~ void drctg07_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Store */
	1006	void arm7_cpu_device::drctg07_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Store */
1010	1007	{
1011	1008	UINT32 op = desc->opptr.l[0];
1012	1009	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
1013	1010	UINT32 rd = op & THUMB_ADDSUB_RD;
1014	1011	INT32 offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
1015		UML_ADD(block, I0, DRC_REG(rn), offs);
1016		UML_MOV(block, I1, DRC_REG(rd));
1017		UML_CALLH(block, *arm->impstate->write8);
	1012	UML_ADD(block, uml::I0, DRC_REG(rn), offs);
	1013	UML_MOV(block, uml::I1, DRC_REG(rd));
	1014	UML_CALLH(block, *m_impstate.write8);
1018	1015	UML_ADD(block, DRC_PC, DRC_PC, 2);
1019	1016	}
1020	1017
1021		~~const~~ void drctg07_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Load */
	1018	void arm7_cpu_device::drctg07_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Load */
1022	1019	{
1023	1020	UINT32 op = desc->opptr.l[0];
1024	1021	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
1025	1022	UINT32 rd = op & THUMB_ADDSUB_RD;
1026	1023	INT32 offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
1027		UML_ADD(block, I0, DRC_REG(rn), offs);
1028		UML_CALLH(block, *arm->impstate->read8);
1029		UML_MOV(block, DRC_REG(rd), I0);
	1024	UML_ADD(block, uml::I0, DRC_REG(rn), offs);
	1025	UML_CALLH(block, *m_impstate.read8);
	1026	UML_MOV(block, DRC_REG(rd), uml::I0);
1030	1027	UML_ADD(block, DRC_PC, DRC_PC, 2);
1031	1028	}
1032	1029
1033	1030	/* Load/Store Halfword */
1034	1031
1035		~~const~~ void drctg08_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Store */
	1032	void arm7_cpu_device::drctg08_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Store */
1036	1033	{
1037	1034	UINT32 op = desc->opptr.l[0];
1038	1035	UINT32 offs = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
1039		UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
	1036	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
1040	1037	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
1041		UML_ADD(block, I0, DRC_REG(rn), offs << 1);
1042		UML_MOV(block, I1, DRC_REG(rd));
1043		UML_CALLH(block, *arm->impstate->write16);
	1038	UML_ADD(block, uml::I0, DRC_REG(rn), offs << 1);
	1039	UML_MOV(block, uml::I1, DRC_REG(rd));
	1040	UML_CALLH(block, *m_impstate.write16);
1044	1041	UML_ADD(block, DRC_PC, DRC_PC, 2);
1045	1042	}
1046	1043
1047		~~const~~ void drctg08_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Load */
	1044	void arm7_cpu_device::drctg08_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Load */
1048	1045	{
1049	1046	UINT32 op = desc->opptr.l[0];
1050	1047	UINT32 offs = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
1051		UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
	1048	UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
1052	1049	UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
1053		UML_ADD(block, I0, DRC_REG(rn), offs << 1);
1054		UML_CALLH(block, *arm->impstate->read16);
1055		UML_MOV(block, DRC_REG(rd), I0);
	1050	UML_ADD(block, uml::I0, DRC_REG(rn), offs << 1);
	1051	UML_CALLH(block, *m_impstate.read16);
	1052	UML_MOV(block, DRC_REG(rd), uml::I0);
1056	1053	UML_ADD(block, DRC_PC, DRC_PC, 2);
1057	1054	}
1058	1055
1059	1056	/* Stack-Relative Load/Store */
1060	1057
1061		~~const~~ void drctg09_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Store */
	1058	void arm7_cpu_device::drctg09_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Store */
1062	1059	{
1063	1060	UINT32 op = desc->opptr.l[0];
1064	1061	UINT32 rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
1065	1062	INT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
1066		UML_ADD(block, I0, DRC_REG(13), offs);
1067		UML_MOV(block, I1, DRC_REG(rd));
1068		UML_CALLH(block, *arm->impstate->write32);
	1063	UML_ADD(block, uml::I0, DRC_REG(13), offs);
	1064	UML_MOV(block, uml::I1, DRC_REG(rd));
	1065	UML_CALLH(block, *m_impstate.write32);
1069	1066	UML_ADD(block, DRC_PC, DRC_PC, 2);
1070	1067	}
1071	1068
1072		~~const~~ void drctg09_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Load */
	1069	void arm7_cpu_device::drctg09_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Load */
1073	1070	{
1074	1071	UINT32 op = desc->opptr.l[0];
1075	1072	UINT32 rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
1076	1073	UINT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
1077		UML_ADD(block, I0, DRC_REG(13), offs);
1078		UML_CALLH(block, *arm->impstate->read32);
1079		UML_MOV(block, DRC_REG(rd), I0);
	1074	UML_ADD(block, uml::I0, DRC_REG(13), offs);
	1075	UML_CALLH(block, *m_impstate.read32);
	1076	UML_MOV(block, DRC_REG(rd), uml::I0);
1080	1077	UML_ADD(block, DRC_PC, DRC_PC, 2);
1081	1078	}
1082	1079
1083	1080	/* Get relative address */
1084	1081
1085		~~const~~ void drctg0a_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ADD Rd, PC, #nn */
	1082	void arm7_cpu_device::drctg0a_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ADD Rd, PC, #nn */
1086	1083	{
1087	1084	UINT32 op = desc->opptr.l[0];
1088	1085	UINT32 rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
1089	1086	INT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
1090		UML_ADD(block, I0, DRC_PC, 4);
1091		UML_AND(block, I0, I0, ~2);
1092		UML_ADD(block, DRC_REG(rd), I0, offs);
	1087	UML_ADD(block, uml::I0, DRC_PC, 4);
	1088	UML_AND(block, uml::I0, uml::I0, ~2);
	1089	UML_ADD(block, DRC_REG(rd), uml::I0, offs);
1093	1090	UML_ADD(block, DRC_PC, DRC_PC, 2);
1094	1091	}
1095	1092
1096		~~const~~ void drctg0a_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ADD Rd, SP, #nn */
	1093	void arm7_cpu_device::drctg0a_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ADD Rd, SP, #nn */
1097	1094	{
1098	1095	UINT32 op = desc->opptr.l[0];
1099	1096	UINT32 rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
r24074	r24075
1104	1101
1105	1102	/* Stack-Related Opcodes */
1106	1103
1107		~~const~~ void drctg0b_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* ADD SP, #imm */
	1104	void arm7_cpu_device::drctg0b_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / ADD SP, #imm */
1108	1105	{
1109	1106	UINT32 op = desc->opptr.l[0];
1110	1107	INT32 addr = (op & THUMB_INSN_IMM);
r24074	r24075
1114	1111	UML_ADD(block, DRC_PC, DRC_PC, 2);
1115	1112	}
1116	1113
1117		~~const~~ void drctg0b_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1114	void arm7_cpu_device::drctg0b_1(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1118	1115	{
1119	1116	UINT32 op = desc->opptr.l[0];
	1117	UINT32 pc = desc->pc;
1120	1118	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1121	1119	}
1122	1120
1123		~~const~~ void drctg0b_2(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1121	void arm7_cpu_device::drctg0b_2(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1124	1122	{
1125	1123	UINT32 op = desc->opptr.l[0];
	1124	UINT32 pc = desc->pc;
1126	1125	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1127	1126	}
1128	1127
1129		~~const~~ void drctg0b_3(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1128	void arm7_cpu_device::drctg0b_3(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1130	1129	{
1131	1130	UINT32 op = desc->opptr.l[0];
	1131	UINT32 pc = desc->pc;
1132	1132	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1133	1133	}
1134	1134
1135		~~const~~ void drctg0b_4(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* PUSH {Rlist} */
	1135	void arm7_cpu_device::drctg0b_4(drcuml_block block, compiler_state compiler, const opcode_desc desc) / PUSH {Rlist} */
1136	1136	{
1137	1137	UINT32 op = desc->opptr.l[0];
1138	1138	for (INT32 offs = 7; offs >= 0; offs--)
r24074	r24075
1140	1140	if (op & (1 << offs))
1141	1141	{
1142	1142	UML_SUB(block, DRC_REG(13), DRC_REG(13), 4);
1143		UML_MOV(block, I0, DRC_REG(13));
1144		UML_MOV(block, I1, DRC_REG(offs));
1145		UML_CALLH(block, *arm->impstate->write32);
	1143	UML_MOV(block, uml::I0, DRC_REG(13));
	1144	UML_MOV(block, uml::I1, DRC_REG(offs));
	1145	UML_CALLH(block, *m_impstate.write32);
1146	1146	}
1147	1147	}
1148	1148	UML_ADD(block, DRC_PC, DRC_PC, 2);
1149	1149	}
1150	1150
1151		~~const~~ void drctg0b_5(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* PUSH {Rlist}{LR} */
	1151	void arm7_cpu_device::drctg0b_5(drcuml_block block, compiler_state compiler, const opcode_desc desc) / PUSH {Rlist}{LR} */
1152	1152	{
1153	1153	UINT32 op = desc->opptr.l[0];
1154	1154	UML_SUB(block, DRC_REG(13), DRC_REG(13), 4);
1155		UML_MOV(block, I0, DRC_REG(13));
1156		UML_MOV(block, I1, DRC_REG(14));
1157		UML_CALLH(block, *arm->impstate->write32);
	1155	UML_MOV(block, uml::I0, DRC_REG(13));
	1156	UML_MOV(block, uml::I1, DRC_REG(14));
	1157	UML_CALLH(block, *m_impstate.write32);
1158	1158	for (INT32 offs = 7; offs >= 0; offs--)
1159	1159	{
1160	1160	if (op & (1 << offs))
1161	1161	{
1162	1162	UML_SUB(block, DRC_REG(13), DRC_REG(13), 4);
1163		UML_MOV(block, I0, DRC_REG(13));
1164		UML_MOV(block, I1, DRC_REG(offs));
1165		UML_CALLH(block, *arm->impstate->write32);
	1163	UML_MOV(block, uml::I0, DRC_REG(13));
	1164	UML_MOV(block, uml::I1, DRC_REG(offs));
	1165	UML_CALLH(block, *m_impstate.write32);
1166	1166	}
1167	1167	}
1168	1168	UML_ADD(block, DRC_PC, DRC_PC, 2);
1169	1169	}
1170	1170
1171		~~const~~ void drctg0b_6(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1171	void arm7_cpu_device::drctg0b_6(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1172	1172	{
1173	1173	UINT32 op = desc->opptr.l[0];
	1174	UINT32 pc = desc->pc;
1174	1175	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1175	1176	}
1176	1177
1177		~~const~~ void drctg0b_7(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1178	void arm7_cpu_device::drctg0b_7(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1178	1179	{
1179	1180	UINT32 op = desc->opptr.l[0];
	1181	UINT32 pc = desc->pc;
1180	1182	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1181	1183	}
1182	1184
1183		~~const~~ void drctg0b_8(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1185	void arm7_cpu_device::drctg0b_8(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1184	1186	{
1185	1187	UINT32 op = desc->opptr.l[0];
	1188	UINT32 pc = desc->pc;
1186	1189	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1187	1190	}
1188	1191
1189		~~const~~ void drctg0b_9(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1192	void arm7_cpu_device::drctg0b_9(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1190	1193	{
1191	1194	UINT32 op = desc->opptr.l[0];
	1195	UINT32 pc = desc->pc;
1192	1196	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1193	1197	}
1194	1198
1195		~~const~~ void drctg0b_a(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1199	void arm7_cpu_device::drctg0b_a(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1196	1200	{
1197	1201	UINT32 op = desc->opptr.l[0];
	1202	UINT32 pc = desc->pc;
1198	1203	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1199	1204	}
1200	1205
1201		~~const~~ void drctg0b_b(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1206	void arm7_cpu_device::drctg0b_b(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1202	1207	{
1203	1208	UINT32 op = desc->opptr.l[0];
	1209	UINT32 pc = desc->pc;
1204	1210	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1205	1211	}
1206	1212
1207		~~const~~ void tg0b_c(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* POP {Rlist} */
	1213	void arm7_cpu_device::drctg0b_c(drcuml_block block, compiler_state compiler, const opcode_desc desc) / POP {Rlist} */
1208	1214	{
1209	1215	UINT32 op = desc->opptr.l[0];
1210	1216	for (INT32 offs = 0; offs < 8; offs++)
1211	1217	{
1212	1218	if (op & (1 << offs))
1213	1219	{
1214		UML_MOV(block, I0, DRC_REG(13));
1215		UML_CALLH(block, *arm->impstate->read32);
1216		UML_MOV(block, DRC_REG(offs), I0);
	1220	UML_MOV(block, uml::I0, DRC_REG(13));
	1221	UML_CALLH(block, *m_impstate.read32);
	1222	UML_MOV(block, DRC_REG(offs), uml::I0);
1217	1223	UML_ADD(block, DRC_REG(13), DRC_REG(13), 4);
1218	1224	}
1219	1225	}
1220	1226	UML_ADD(block, DRC_PC, DRC_PC, 2);
1221	1227	}
1222	1228
1223		~~const~~ void drctg0b_d(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* POP {Rlist}{PC} */
	1229	void arm7_cpu_device::drctg0b_d(drcuml_block block, compiler_state compiler, const opcode_desc desc) / POP {Rlist}{PC} */
1224	1230	{
1225	1231	UINT32 op = desc->opptr.l[0];
1226		code_label arch5up;
1227		code_label done;
1228		code_label switch_mode;
	1232	uml::code_label arch5up;
	1233	uml::code_label done;
	1234	uml::code_label switch_mode;
1229	1235	for (INT32 offs = 0; offs < 8; offs++)
1230	1236	{
1231	1237	if (op & (1 << offs))
1232	1238	{
1233		UML_MOV(block, I0, DRC_REG(13));
1234		UML_CALLH(block, *arm->impstate->read32);
1235		UML_MOV(block, DRC_REG(offs), I0);
	1239	UML_MOV(block, uml::I0, DRC_REG(13));
	1240	UML_CALLH(block, *m_impstate.read32);
	1241	UML_MOV(block, DRC_REG(offs), uml::I0);
1236	1242	UML_ADD(block, DRC_REG(13), DRC_REG(13), 4);
1237	1243	}
1238	1244	}
1239		UML_MOV(block, I0, DRC_REG(13));
1240		UML_CALLH(block, *arm->impstate->read32);
1241		UML_CMP(block, mem(&arm->archRev), 4);
1242		UML_JMPc(block, COND_A, arch5up = compiler->labelnum++);
1243		UML_AND(block, DRC_PC, I0, ~1);
	1245	UML_MOV(block, uml::I0, DRC_REG(13));
	1246	UML_CALLH(block, *m_impstate.read32);
	1247	UML_CMP(block, uml::mem(&m_archRev), 4);
	1248	UML_JMPc(block, uml::COND_A, arch5up = compiler->labelnum++);
	1249	UML_AND(block, DRC_PC, uml::I0, ~1);
1244	1250
1245	1251	UML_LABEL(block, arch5up);
1246	1252
1247		UML_TEST(block, I0, 1);
1248		UML_JMPc(block, COND_Z, switch_mode = compiler->labelnum++);
	1253	UML_TEST(block, uml::I0, 1);
	1254	UML_JMPc(block, uml::COND_Z, switch_mode = compiler->labelnum++);
1249	1255
1250		UML_AND(block, I0, I0, ~1);
1251		UML_MOV(block, DRC_PC, I0);
1252		UML_JMP(block done);
	1256	UML_AND(block, uml::I0, uml::I0, ~1);
	1257	UML_MOV(block, DRC_PC, uml::I0);
	1258	UML_JMP(block, done);
1253	1259
1254	1260	UML_LABEL(block, switch_mode);
1255	1261	UML_AND(block, DRC_CPSR, DRC_CPSR, ~T_MASK);
1256		UML_TEST(block, I0, 2);
1257		UML_MOVc(block, COND_NZ, I1, 2);
1258		UML_MOVc(block, COND_Z, I1, 0);
1259		UML_ADD(block, I0, I0, I1);
1260		UML_MOV(block, DRC_PC, I0);
	1262	UML_TEST(block, uml::I0, 2);
	1263	UML_MOVc(block, uml::COND_NZ, uml::I1, 2);
	1264	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1265	UML_ADD(block, uml::I0, uml::I0, uml::I1);
	1266	UML_MOV(block, DRC_PC, uml::I0);
1261	1267
1262	1268	UML_LABEL(block, done);
1263	1269	UML_ADD(block, DRC_REG(13), DRC_REG(13), 4);
1264	1270	}
1265	1271
1266		~~const~~ void drctg0b_e(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1272	void arm7_cpu_device::drctg0b_e(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1267	1273	{
1268	1274	UINT32 op = desc->opptr.l[0];
	1275	UINT32 pc = desc->pc;
1269	1276	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1270	1277	}
1271	1278
1272		~~const~~ void drctg0b_f(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1279	void arm7_cpu_device::drctg0b_f(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1273	1280	{
1274	1281	UINT32 op = desc->opptr.l[0];
	1282	UINT32 pc = desc->pc;
1275	1283	fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1276	1284	}
1277	1285
r24074	r24075
1283	1291	// GBA "BB Ball" performs an unaligned read with A[1:0] = 2 and expects A[1] not to be ignored [BP 800B90A,(R4&3)!=0]
1284	1292	// GBA "Gadget Racers" performs an unaligned read with A[1:0] = 1 and expects A[0] to be ignored [BP B72,(R0&3)!=0]
1285	1293
1286		~~const~~ void drctg0c_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Store */
	1294	void arm7_cpu_device::drctg0c_0(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Store */
1287	1295	{
1288	1296	UINT32 op = desc->opptr.l[0];
1289	1297	UINT32 rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
1290		UML_MOV(block, I2, DRC_REG(rd));
	1298	UML_MOV(block, uml::I2, DRC_REG(rd));
1291	1299	for (INT32 offs = 0; offs < 8; offs++)
1292	1300	{
1293	1301	if (op & (1 << offs))
1294	1302	{
1295		UML_AND(block, I0, I2, ~3);
1296		UML_MOV(block, I1, DRC_REG(offs));
1297		UML_CALLH(block, *arm->impstate->write32);
1298		UML_ADD(block, I2, I2, 4);
	1303	UML_AND(block, uml::I0, uml::I2, ~3);
	1304	UML_MOV(block, uml::I1, DRC_REG(offs));
	1305	UML_CALLH(block, *m_impstate.write32);
	1306	UML_ADD(block, uml::I2, uml::I2, 4);
1299	1307	}
1300	1308	}
1301		UML_MOV(block, DRC_REG(rd), I2);
	1309	UML_MOV(block, DRC_REG(rd), uml::I2);
1302	1310	UML_ADD(block, DRC_PC, DRC_PC, 2);
1303	1311	}
1304	1312
1305		~~const~~ void drctg0c_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* Load */
	1313	void arm7_cpu_device::drctg0c_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / Load */
1306	1314	{
1307	1315	UINT32 op = desc->opptr.l[0];
1308	1316	UINT32 rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
1309	1317	int rd_in_list = op & (1 << rd);
1310		UML_MOV(block, I2, DRC_REG(rd));
	1318	UML_MOV(block, uml::I2, DRC_REG(rd));
1311	1319	for (INT32 offs = 0; offs < 8; offs++)
1312	1320	{
1313	1321	if (op & (1 << offs))
1314	1322	{
1315		UML_AND(block, I0, I2, ~1);
1316		UML_CALLH(block, *arm->impstate->read32);
1317		UML_ADD(block, I2, I2, 4);
	1323	UML_AND(block, uml::I0, uml::I2, ~1);
	1324	UML_CALLH(block, *m_impstate.read32);
	1325	UML_ADD(block, uml::I2, uml::I2, 4);
1318	1326	}
1319	1327	}
1320	1328	if (!rd_in_list)
1321	1329	{
1322		UML_MOV(block, DRC_REG(rd), I2);
	1330	UML_MOV(block, DRC_REG(rd), uml::I2);
1323	1331	}
1324	1332	UML_ADD(block, DRC_PC, DRC_PC, 2);
1325	1333	}
1326	1334
1327	1335	/* Conditional Branch */
1328	1336
1329		~~const~~ void drctg0d_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_EQ:
	1337	void arm7_cpu_device::drctg0d_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_EQ:
1330	1338	{
1331	1339	UINT32 op = desc->opptr.l[0];
1332	1340	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1333	1341	UML_TEST(block, DRC_CPSR, Z_MASK);
1334		UML_MOVc(block, COND_NZ, I0, offs);
1335		UML_MOVc(block, COND_Z, I0, 2);
1336		UML_ADD(block, COND_PC, COND_PC, I0);
	1342	UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
	1343	UML_MOVc(block, uml::COND_Z, uml::I0, 2);
	1344	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1337	1345	}
1338	1346
1339		~~const~~ void drctg0d_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_NE:
	1347	void arm7_cpu_device::drctg0d_1(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_NE:
1340	1348	{
1341	1349	UINT32 op = desc->opptr.l[0];
1342	1350	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1343	1351	UML_TEST(block, DRC_CPSR, Z_MASK);
1344		UML_MOVc(block, COND_Z, I0, offs);
1345		UML_MOVc(block, COND_NZ, I0, 2);
1346		UML_ADD(block, COND_PC, COND_PC, I0);
	1352	UML_MOVc(block, uml::COND_Z, uml::I0, offs);
	1353	UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
	1354	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1347	1355	}
1348	1356
1349		~~const~~ void drctg0d_2(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_CS:
	1357	void arm7_cpu_device::drctg0d_2(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_CS:
1350	1358	{
1351	1359	UINT32 op = desc->opptr.l[0];
1352	1360	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1353	1361	UML_TEST(block, DRC_CPSR, C_MASK);
1354		UML_MOVc(block, COND_NZ, I0, offs);
1355		UML_MOVc(block, COND_Z, I0, 2);
1356		UML_ADD(block, COND_PC, COND_PC, I0);
	1362	UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
	1363	UML_MOVc(block, uml::COND_Z, uml::I0, 2);
	1364	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1357	1365	}
1358	1366
1359		~~const~~ void drctg0d_3(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_CC:
	1367	void arm7_cpu_device::drctg0d_3(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_CC:
1360	1368	{
1361	1369	UINT32 op = desc->opptr.l[0];
1362	1370	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1363	1371	UML_TEST(block, DRC_CPSR, C_MASK);
1364		UML_MOVc(block, COND_Z, I0, offs);
1365		UML_MOVc(block, COND_NZ, I0, 2);
1366		UML_ADD(block, COND_PC, COND_PC, I0);
	1372	UML_MOVc(block, uml::COND_Z, uml::I0, offs);
	1373	UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
	1374	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1367	1375	}
1368	1376
1369		~~const~~ void drctg0d_4(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_MI:
	1377	void arm7_cpu_device::drctg0d_4(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_MI:
1370	1378	{
1371	1379	UINT32 op = desc->opptr.l[0];
1372	1380	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1373	1381	UML_TEST(block, DRC_CPSR, N_MASK);
1374		UML_MOVc(block, COND_NZ, I0, offs);
1375		UML_MOVc(block, COND_Z, I0, 2);
1376		UML_ADD(block, COND_PC, COND_PC, I0);
	1382	UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
	1383	UML_MOVc(block, uml::COND_Z, uml::I0, 2);
	1384	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1377	1385	}
1378	1386
1379		~~const~~ void drctg0d_5(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_PL:
	1387	void arm7_cpu_device::drctg0d_5(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_PL:
1380	1388	{
1381	1389	UINT32 op = desc->opptr.l[0];
1382	1390	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1383	1391	UML_TEST(block, DRC_CPSR, N_MASK);
1384		UML_MOVc(block, COND_Z, I0, offs);
1385		UML_MOVc(block, COND_NZ, I0, 2);
1386		UML_ADD(block, COND_PC, COND_PC, I0);
	1392	UML_MOVc(block, uml::COND_Z, uml::I0, offs);
	1393	UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
	1394	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1387	1395	}
1388	1396
1389		~~const~~ void drctg0d_6(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_VS:
	1397	void arm7_cpu_device::drctg0d_6(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_VS:
1390	1398	{
1391	1399	UINT32 op = desc->opptr.l[0];
1392	1400	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1393	1401	UML_TEST(block, DRC_CPSR, V_MASK);
1394		UML_MOVc(block, COND_NZ, I0, offs);
1395		UML_MOVc(block, COND_Z, I0, 2);
1396		UML_ADD(block, COND_PC, COND_PC, I0);
	1402	UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
	1403	UML_MOVc(block, uml::COND_Z, uml::I0, 2);
	1404	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1397	1405	}
1398	1406
1399		~~const~~ void drctg0d_7(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_VC:
	1407	void arm7_cpu_device::drctg0d_7(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_VC:
1400	1408	{
1401	1409	UINT32 op = desc->opptr.l[0];
1402	1410	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1403	1411	UML_TEST(block, DRC_CPSR, V_MASK);
1404		UML_MOVc(block, COND_Z, I0, offs);
1405		UML_MOVc(block, COND_NZ, I0, 2);
1406		UML_ADD(block, COND_PC, COND_PC, I0);
	1412	UML_MOVc(block, uml::COND_Z, uml::I0, offs);
	1413	UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
	1414	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1407	1415	}
1408	1416
1409		~~const~~ void drctg0d_8(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_HI:
	1417	void arm7_cpu_device::drctg0d_8(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_HI:
1410	1418	{
1411	1419	UINT32 op = desc->opptr.l[0];
1412	1420	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1413	1421	UML_TEST(block, DRC_CPSR, C_MASK);
1414		UML_MOVc(block, COND_NZ, I0, 1);
1415		UML_MOVc(block, COND_Z, I0, 0);
	1422	UML_MOVc(block, uml::COND_NZ, uml::I0, 1);
	1423	UML_MOVc(block, uml::COND_Z, uml::I0, 0);
1416	1424	UML_TEST(block, DRC_CPSR, Z_MASK);
1417		UML_MOVc(block, COND_NZ, I1, 0);
1418		UML_MOVc(block, COND_Z, I1, 1);
1419		UML_AND(block, I0, I0, I1);
1420		UML_TEST(block, I0, 1);
1421		UML_MOVc(block, COND_NZ, I0, offs);
1422		UML_MOVc(block, COND_Z, I0, 2);
1423		UML_ADD(block, COND_PC, COND_PC, I0);
	1425	UML_MOVc(block, uml::COND_NZ, uml::I1, 0);
	1426	UML_MOVc(block, uml::COND_Z, uml::I1, 1);
	1427	UML_AND(block, uml::I0, uml::I0, uml::I1);
	1428	UML_TEST(block, uml::I0, 1);
	1429	UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
	1430	UML_MOVc(block, uml::COND_Z, uml::I0, 2);
	1431	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1424	1432	}
1425	1433
1426		~~const~~ void drctg0d_9(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_LS:
	1434	void arm7_cpu_device::drctg0d_9(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_LS:
1427	1435	{
1428	1436	UINT32 op = desc->opptr.l[0];
1429	1437	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1430	1438	UML_TEST(block, DRC_CPSR, C_MASK);
1431		UML_MOVc(block, COND_Z, I0, 1);
1432		UML_MOVc(block, COND_NZ, I0, 0);
	1439	UML_MOVc(block, uml::COND_Z, uml::I0, 1);
	1440	UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1433	1441	UML_TEST(block, DRC_CPSR, Z_MASK);
1434		UML_MOVc(block, COND_Z, I1, 0);
1435		UML_MOVc(block, COND_NZ, I1, 1);
1436		UML_AND(block, I0, I0, I1);
1437		UML_TEST(block, I0, 1);
1438		UML_MOVc(block, COND_NZ, I0, offs);
1439		UML_MOVc(block, COND_Z, I0, 2);
1440		UML_ADD(block, COND_PC, COND_PC, I0);
	1442	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1443	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1444	UML_AND(block, uml::I0, uml::I0, uml::I1);
	1445	UML_TEST(block, uml::I0, 1);
	1446	UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
	1447	UML_MOVc(block, uml::COND_Z, uml::I0, 2);
	1448	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1441	1449	}
1442	1450
1443		~~const~~ void drctg0d_a(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_GE:
	1451	void arm7_cpu_device::drctg0d_a(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_GE:
1444	1452	{
1445	1453	UINT32 op = desc->opptr.l[0];
	1454	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1446	1455	UML_TEST(block, DRC_CPSR, N_MASK);
1447		UML_MOVc(block, COND_Z, I0, 1);
1448		UML_MOVc(block, COND_NZ, I0, 0);
	1456	UML_MOVc(block, uml::COND_Z, uml::I0, 1);
	1457	UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1449	1458	UML_TEST(block, DRC_CPSR, V_MASK);
1450		UML_MOVc(block, COND_Z, I1, 0);
1451		UML_MOVc(block, COND_NZ, I1, 1);
1452		UML_CMP(block, I0, I1);
1453		UML_MOVc(block, COND_E, I0, offs);
1454		UML_MOVc(block, COND_NE, I0, 2);
1455		UML_ADD(block, COND_PC, COND_PC, I0);
	1459	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1460	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1461	UML_CMP(block, uml::I0, uml::I1);
	1462	UML_MOVc(block, uml::COND_E, uml::I0, offs);
	1463	UML_MOVc(block, uml::COND_NE, uml::I0, 2);
	1464	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1456	1465	}
1457	1466
1458		~~const~~ void drctg0d_b(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_LT:
	1467	void arm7_cpu_device::drctg0d_b(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_LT:
1459	1468	{
1460	1469	UINT32 op = desc->opptr.l[0];
	1470	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1461	1471	UML_TEST(block, DRC_CPSR, N_MASK);
1462		UML_MOVc(block, COND_Z, I0, 1);
1463		UML_MOVc(block, COND_NZ, I0, 0);
	1472	UML_MOVc(block, uml::COND_Z, uml::I0, 1);
	1473	UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1464	1474	UML_TEST(block, DRC_CPSR, V_MASK);
1465		UML_MOVc(block, COND_Z, I1, 0);
1466		UML_MOVc(block, COND_NZ, I1, 1);
1467		UML_CMP(block, I0, I1);
1468		UML_MOVc(block, COND_NE, I0, offs);
1469		UML_MOVc(block, COND_E, I0, 2);
1470		UML_ADD(block, COND_PC, COND_PC, I0);
	1475	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1476	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1477	UML_CMP(block, uml::I0, uml::I1);
	1478	UML_MOVc(block, uml::COND_NE, uml::I0, offs);
	1479	UML_MOVc(block, uml::COND_E, uml::I0, 2);
	1480	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1471	1481	}
1472	1482
1473		~~const~~ void drctg0d_c(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_GT:
	1483	void arm7_cpu_device::drctg0d_c(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_GT:
1474	1484	{
1475	1485	UINT32 op = desc->opptr.l[0];
	1486	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1476	1487	UML_TEST(block, DRC_CPSR, N_MASK);
1477		UML_MOVc(block, COND_Z, I0, 1);
1478		UML_MOVc(block, COND_NZ, I0, 0);
	1488	UML_MOVc(block, uml::COND_Z, uml::I0, 1);
	1489	UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1479	1490	UML_TEST(block, DRC_CPSR, V_MASK);
1480		UML_MOVc(block, COND_Z, I1, 0);
1481		UML_MOVc(block, COND_NZ, I1, 1);
1482		UML_CMP(block, I0, I1);
1483		UML_MOVc(block, COND_E, I0, 1);
1484		UML_MOVc(block, COND_NE, I0, 0);
	1491	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1492	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1493	UML_CMP(block, uml::I0, uml::I1);
	1494	UML_MOVc(block, uml::COND_E, uml::I0, 1);
	1495	UML_MOVc(block, uml::COND_NE, uml::I0, 0);
1485	1496	UML_TEST(block, DRC_CPSR, Z_MASK);
1486		UML_MOVc(block, COND_NZ, I1, 1);
1487		UML_MOVc(block, COND_Z, I1, 0);
1488		UML_AND(block, I0, I0, I1);
1489		UML_TEST(block, I0, 1);
1490		UML_MOVc(block, COND_NZ, I0, offs);
1491		UML_MOVc(block, COND_Z, I0, 2);
1492		UML_ADD(block, COND_PC, COND_PC, I0);
	1497	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1498	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1499	UML_AND(block, uml::I0, uml::I0, uml::I1);
	1500	UML_TEST(block, uml::I0, 1);
	1501	UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
	1502	UML_MOVc(block, uml::COND_Z, uml::I0, 2);
	1503	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1493	1504	}
1494	1505
1495		~~const~~ void drctg0d_d(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_LE:
	1506	void arm7_cpu_device::drctg0d_d(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_LE:
1496	1507	{
1497	1508	UINT32 op = desc->opptr.l[0];
	1509	INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
1498	1510	UML_TEST(block, DRC_CPSR, N_MASK);
1499		UML_MOVc(block, COND_Z, I0, 1);
1500		UML_MOVc(block, COND_NZ, I0, 0);
	1511	UML_MOVc(block, uml::COND_Z, uml::I0, 1);
	1512	UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1501	1513	UML_TEST(block, DRC_CPSR, V_MASK);
1502		UML_MOVc(block, COND_Z, I1, 0);
1503		UML_MOVc(block, COND_NZ, I1, 1);
1504		UML_CMP(block, I0, I1);
1505		UML_MOVc(block, COND_NE, I0, 1);
1506		UML_MOVc(block, COND_E, I0, 0);
	1514	UML_MOVc(block, uml::COND_Z, uml::I1, 0);
	1515	UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
	1516	UML_CMP(block, uml::I0, uml::I1);
	1517	UML_MOVc(block, uml::COND_NE, uml::I0, 1);
	1518	UML_MOVc(block, uml::COND_E, uml::I0, 0);
1507	1519	UML_TEST(block, DRC_CPSR, Z_MASK);
1508		UML_MOVc(block, COND_NZ, I1, 0);
1509		UML_MOVc(block, COND_Z, I1, 1);
1510		UML_AND(block, I0, I0, I1);
1511		UML_TEST(block, I0, 1);
1512		UML_MOVc(block, COND_NZ, I0, offs);
1513		UML_MOVc(block, COND_Z, I0, 2);
1514		UML_ADD(block, COND_PC, COND_PC, I0);
	1520	UML_MOVc(block, uml::COND_NZ, uml::I1, 0);
	1521	UML_MOVc(block, uml::COND_Z, uml::I1, 1);
	1522	UML_AND(block, uml::I0, uml::I0, uml::I1);
	1523	UML_TEST(block, uml::I0, 1);
	1524	UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
	1525	UML_MOVc(block, uml::COND_Z, uml::I0, 2);
	1526	UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1515	1527	}
1516	1528
1517		~~const~~ void drctg0d_e(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // COND_AL:
	1529	void arm7_cpu_device::drctg0d_e(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // COND_AL:
1518	1530	{
1519	1531	UINT32 op = desc->opptr.l[0];
	1532	UINT32 pc = desc->pc;
1520	1533	fatalerror("%08x: Undefined Thumb instruction: %04x (ARM9 reserved)\n", pc, op);
1521	1534	}
1522	1535
1523		~~const~~ void drctg0d_f(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) // SWI (this is sort of a "hole" in the opcode encoding)
	1536	void arm7_cpu_device::drctg0d_f(drcuml_block block, compiler_state compiler, const opcode_desc *desc) // SWI (this is sort of a "hole" in the opcode encoding)
1524	1537	{
1525		UINT32 op = desc->opptr.l[0];
1526		UML_MOV(block, mem(&arm->pendingSwi), 1);
1527		UML_CALLH(block, *arm->impstate->check_irq);
	1538	UML_MOV(block, uml::mem(&m_pendingSwi), 1);
	1539	UML_CALLH(block, *m_impstate.check_irq);
1528	1540	}
1529	1541
1530	1542	/* B #offs */
1531	1543
1532		~~const~~ void drctg0e_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1544	void arm7_cpu_device::drctg0e_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1533	1545	{
1534	1546	UINT32 op = desc->opptr.l[0];
1535	1547	INT32 offs = (op & THUMB_BRANCH_OFFS) << 1;
r24074	r24075
1540	1552	UML_ADD(block, DRC_PC, DRC_PC, offs + 4);
1541	1553	}
1542	1554
1543		~~const~~ void drctg0e_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1555	void arm7_cpu_device::drctg0e_1(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1544	1556	{
1545	1557	UINT32 op = desc->opptr.l[0];
1546	1558	UINT32 offs = (op & THUMB_BLOP_OFFS) << 1;
1547		UML_MOV(block, I0, DRC_REG(14));
1548		UML_ADD(block, I0, I0, offs);
1549		UML_AND(block, I0, I0, ~3);
	1559	UML_MOV(block, uml::I0, DRC_REG(14));
	1560	UML_ADD(block, uml::I0, uml::I0, offs);
	1561	UML_AND(block, uml::I0, uml::I0, ~3);
1550	1562	UML_ADD(block, DRC_REG(14), DRC_PC, 4);
1551	1563	UML_OR(block, DRC_REG(14), DRC_REG(14), 1);
1552		UML_MOV(block, DRC_PC, I0);
	1564	UML_MOV(block, DRC_PC, uml::I0);
1553	1565	}
1554	1566
1555	1567	/* BL */
1556	1568
1557		~~const~~ void drctg0f_0(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc)
	1569	void arm7_cpu_device::drctg0f_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc)
1558	1570	{
1559	1571	UINT32 op = desc->opptr.l[0];
1560	1572	UINT32 addr = (op & THUMB_BLOP_OFFS) << 12;
r24074	r24075
1567	1579	UML_ADD(block, DRC_PC, DRC_PC, 2);
1568	1580	}
1569	1581
1570		~~const~~ void drctg0f_1(~~arm_state arm,~~ drcuml_block block, compiler_state compiler, const opcode_desc desc) /* BL */
	1582	void arm7_cpu_device::drctg0f_1(drcuml_block block, compiler_state compiler, const opcode_desc desc) / BL */
1571	1583	{
1572	1584	UINT32 op = desc->opptr.l[0];
1573	1585	UINT32 addr = (op & THUMB_BLOP_OFFS) << 1;
1574		UML_AND(block, I0, DRC_REG(14), ~1);
1575		UML_ADD(block, I0, I0, addr);
	1586	UML_AND(block, uml::I0, DRC_REG(14), ~1);
	1587	UML_ADD(block, uml::I0, uml::I0, addr);
1576	1588	UML_ADD(block, DRC_REG(14), DRC_PC, 2);
1577	1589	UML_OR(block, DRC_REG(14), DRC_REG(14), 1);
1578		UML_MOV(block, DRC_PC, I0);
	1590	UML_MOV(block, DRC_PC, uml::I0);
1579	1591	}
1580	1592
1581		#endif // ARM7_USE_DRC

trunk/src/emu/cpu/arm7/arm7core.h
r24074	r24075
93	93	};
94	94
95	95	/* Coprocessor-related macros */
96		#define COPRO_TLB_BASE arm->tlbBase
	96	#define COPRO_TLB_BASE m_tlbBase
97	97	#define COPRO_TLB_BASE_MASK 0xffffc000
98	98	#define COPRO_TLB_VADDR_FLTI_MASK 0xfff00000
99	99	#define COPRO_TLB_VADDR_FLTI_MASK_SHIFT 18
r24074	r24075
117	117	#define COPRO_TLB_SECTION_TABLE 2
118	118	#define COPRO_TLB_FINE_TABLE 3
119	119
120		#define COPRO_CTRL arm->control
	120	#define COPRO_CTRL m_control
121	121	#define COPRO_CTRL_MMU_EN 0x00000001
122	122	#define COPRO_CTRL_ADDRFAULT_EN 0x00000002
123	123	#define COPRO_CTRL_DCACHE_EN 0x00000004
r24074	r24075
141	141	#define COPRO_CTRL_INTVEC_F 1
142	142	#define COPRO_CTRL_MASK 0x0000338f
143	143
144		#define COPRO_DOMAIN_ACCESS_CONTROL arm->domainAccessControl
	144	#define COPRO_DOMAIN_ACCESS_CONTROL m_domainAccessControl
145	145
146		#define COPRO_FAULT_STATUS_D arm->faultStatus[0]
147		#define COPRO_FAULT_STATUS_P arm->faultStatus[1]
	146	#define COPRO_FAULT_STATUS_D m_faultStatus[0]
	147	#define COPRO_FAULT_STATUS_P m_faultStatus[1]
148	148
149		#define COPRO_FAULT_ADDRESS arm->faultAddress
	149	#define COPRO_FAULT_ADDRESS m_faultAddress
150	150
151		#define COPRO_FCSE_PID arm->fcsePID
	151	#define COPRO_FCSE_PID m_fcsePID
152	152
153		/* Coprocessor Registers */
154		#define ARM7COPRO_REGS \
155		UINT32 control; \
156		UINT32 tlbBase; \
157		UINT32 faultStatus[2]; \
158		UINT32 faultAddress; \
159		UINT32 fcsePID; \
160		UINT32 domainAccessControl;
161
162	153	enum
163	154	{
164	155	eARM_ARCHFLAGS_T = 1, // Thumb present
r24074	r24075
170	161	eARM_ARCHFLAGS_MODE26 = 64, // supports 26-bit backwards compatibility mode
171	162	};
172	163
173		#define ARM7CORE_REGS \
174		UINT32 r[NUM_REGS]; \
175		UINT32 pendingIrq; \
176		UINT32 pendingFiq; \
177		UINT32 pendingAbtD; \
178		UINT32 pendingAbtP; \
179		UINT32 pendingUnd; \
180		UINT32 pendingSwi; \
181		int icount; \
182		endianness_t endian; \
183		device_irq_acknowledge_callback irq_callback; \
184		legacy_cpu_device *device; \
185		address_space *program; \
186		direct_read_data *direct;
187	164
188	165	//#define ARM7_USE_DRC
189	166
r24074	r24075
197	174	/* CPU state struct */
198	175	struct arm_state
199	176	{
200		ARM7CORE_REGS // these must be included in your cpu specific register implementation
201		ARM7COPRO_REGS
	177	UINT32 m_r[NUM_REGS];
	178	UINT32 m_pendingIrq;
	179	UINT32 m_pendingFiq;
	180	UINT32 m_pendingAbtD;
	181	UINT32 m_pendingAbtP;
	182	UINT32 m_pendingUnd;
	183	UINT32 m_pendingSwi;
	184	int m_icount;
	185	endianness_t m_endian;
	186	device_irq_acknowledge_callback m_irq_callback;
	187	legacy_cpu_device *m_device;
	188	address_space *m_program;
	189	direct_read_data *m_direct;
202	190
203		UINT8 archRev; // ARM architecture revision (3, 4, and 5 are valid)
204		UINT8 archFlags; // architecture flags
	191	/* Coprocessor Registers */
	192	UINT32 m_control;
	193	UINT32 m_tlbBase;
	194	UINT32 m_faultStatus[2];
	195	UINT32 m_faultAddress;
	196	UINT32 m_fcsePID;
	197	UINT32 m_domainAccessControl;
205	198
	199	UINT8 m_archRev; // ARM architecture revision (3, 4, and 5 are valid)
	200	UINT8 m_archFlags; // architecture flags
	201
206	202	#if ARM7_MMU_ENABLE_HACK
207	203	UINT32 mmu_enable_addr; // workaround for "MMU is enabled when PA != VA" problem
208	204	#endif
209		arm7imp_state impstate;
	205	arm7imp_state m_impstate;
210	206	};
211	207
212	208	/****************************************************************************************************
r24074	r24075
501	497	#define ROR(v, s) (LSR((v), (s)) \| (LSL((v), 32u - (s))))
502	498
503	499	/* Convenience Macros */
504		#define R15 ~~ARM7REG(~~eR15)
	500	#define R15 m_r[eR15]
505	501	#define SPSR 17 // SPSR is always the 18th register in our 0 based array sRegisterTable[][18]
506		#define GET_CPSR ARM7REG(eCPSR)
507		#define SET_CPSR(v) set_cpsr(arm,v)
	502	#define GET_CPSR m_r[eCPSR]
	503	#define SET_CPSR(v) set_cpsr(v)
508	504	#define MODE_FLAG 0xF // Mode bits are 4:0 of CPSR, but we ignore bit 4.
509	505	#define GET_MODE (GET_CPSR & MODE_FLAG)
510	506	#define SIGN_BIT ((UINT32)(1 << 31))
r24074	r24075
525	521	#define ARM7_TLB_WRITE (1 << 3)
526	522
527	523	/* At one point I thought these needed to be cpu implementation specific, but they don't.. */
528		#define GET_REGISTER(state, reg) GetRegister(state, reg)
529		#define SET_REGISTER(state, reg, val) SetRegister(state, reg, val)
530		#define GET_MODE_REGISTER(state, mode, reg) GetModeRegister(state, mode, reg)
531		#define SET_MODE_REGISTER(state, mode, reg, val) SetModeRegister(state, mode, reg, val)
532		#define ARM7_CHECKIRQ arm7_check_irq_state(arm)
	524	#define GET_REGISTER(reg) GetRegister(reg)
	525	#define SET_REGISTER(reg, val) SetRegister(reg, val)
	526	#define GET_MODE_REGISTER(mode, reg) GetModeRegister(mode, reg)
	527	#define SET_MODE_REGISTER(mode, reg, val) SetModeRegister(mode, reg, val)
	528	#define ARM7_CHECKIRQ arm7_check_irq_state()
533	529
534		extern write32_device_func arm7_coproc_do_callback;
535		extern read32_device_func arm7_coproc_rt_r_callback;
536		extern write32_device_func arm7_coproc_rt_w_callback;
537		extern void arm7_dt_r_callback(arm_state arm, UINT32 insn, UINT32 prn, UINT32 (read32)(arm_state arm, UINT32 addr));
538		extern void arm7_dt_w_callback(arm_state arm, UINT32 insn, UINT32 prn, void (write32)(arm_state arm, UINT32 addr, UINT32 data));
539	530
540		#ifdef UNUSED_DEFINITION
541		extern char (arm7_dasm_cop_dt_callback)(arm_state arm, char pBuf, UINT32 opcode, char pConditionCode, char pBuf0);
542		extern char (arm7_dasm_cop_rt_callback)(arm_state arm, char pBuf, UINT32 opcode, char pConditionCode, char pBuf0);
543		extern char (arm7_dasm_cop_do_callback)(arm_state arm, char pBuf, UINT32 opcode, char pConditionCode, char pBuf0);
544		#endif
545
546	531	/* ARM flavors */
547	532	enum arm_flavor
548	533	{

trunk/src/emu/cpu/arm7/arm7help.h
r24074	r24075
1	1	/* ARM7 core helper Macros / Functions */
2	2
3	3	/* Macros that need to be defined according to the cpu implementation specific need */
4		#define ARM7REG(reg) arm->r[reg]
5		#define ARM7_ICOUNT arm->icount
	4	#define ARM7REG(reg) m_r[reg]
	5	#define ARM7_ICOUNT m_icount
6	6
7	7
8		extern void SwitchMode(arm_state *arm, int cpsr_mode_val);
9
10	8	#if 0
11	9	#define LOG(x) mame_printf_debug x
12	10	#else
r24074	r24075
45	43	#define DRCHandleThumbALUAddFlags(rd, rn, op2) \
46	44	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK \| Z_MASK \| V_MASK \| C_MASK)); \
47	45	DRCHandleALUNZFlags(rd); \
48		UML_XOR(block, I1, rn, ~0); \
49		UML_CMP(block, I1, op2); \
50		UML_MOVc(block, COND_B, I1, C_BIT); \
51		UML_MOVc(block, COND_AE, I1, 0); \
52		UML_OR(block, I0, I0, I1); \
53		UML_XOR(block, I1, rn, op2); \
54		UML_XOR(block, I2, rn, rd); \
55		UML_AND(block, I1, I1, I2); \
56		UML_TEST(block, I1, 1 << 31); \
57		UML_MOVc(block, COND_NZ, I1, V_BIT); \
58		UML_MOVc(block, COND_Z, I1, 0); \
59		UML_OR(block, I0, I0, I1); \
60		UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \
	46	UML_XOR(block, uml::I1, rn, ~0); \
	47	UML_CMP(block, uml::I1, op2); \
	48	UML_MOVc(block, uml::COND_B, uml::I1, C_BIT); \
	49	UML_MOVc(block, uml::COND_AE, uml::I1, 0); \
	50	UML_OR(block, uml::I0, uml::I0, uml::I1); \
	51	UML_XOR(block, uml::I1, rn, op2); \
	52	UML_XOR(block, uml::I2, rn, rd); \
	53	UML_AND(block, uml::I1, uml::I1, uml::I2); \
	54	UML_TEST(block, uml::I1, 1 << 31); \
	55	UML_MOVc(block, uml::COND_NZ, uml::I1, V_BIT); \
	56	UML_MOVc(block, uml::COND_Z, uml::I1, 0); \
	57	UML_OR(block, uml::I0, uml::I0, uml::I1); \
	58	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0); \
61	59	UML_ADD(block, DRC_PC, DRC_PC, 2);
62	60
63	61	#define HandleALUSubFlags(rd, rn, op2) \
r24074	r24075
78	76	#define DRCHandleThumbALUSubFlags(rd, rn, op2) \
79	77	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK \| Z_MASK \| V_MASK \| C_MASK)); \
80	78	DRCHandleALUNZFlags(rd); \
81		UML_XOR(block, I1, rn, op2); \
82		UML_XOR(block, I2, rn, rd); \
83		UML_AND(block, I1, I1, I2); \
84		UML_TEST(block, I1, 1 << 31); \
85		UML_MOVc(block, COND_NZ, I1, V_BIT); \
86		UML_MOVc(block, COND_Z, I1, 0); \
87		UML_OR(block, I0, I0, I1); \
88		UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \
89		UML_AND(block, I0, rd, 1 << 31); \
90		UML_AND(block, I1, op2, 1 << 31); \
91		UML_AND(block, I2, rn, 1 << 31); \
92		UML_XOR(block, I2, I2, ~0); \
93		UML_AND(block, I1, I1, I2); \
94		UML_AND(block, I2, I2, I0); \
95		UML_OR(block, I1, I1, I2); \
96		UML_AND(block, I2, op2, 1 << 31); \
97		UML_AND(block, I2, I2, I0); \
98		UML_OR(block, I1, I1, I2); \
99		UML_TEST(block, I1, 1 << 31); \
100		UML_MOVc(block, COND_NZ, I0, C_MASK); \
101		UML_MOVc(block, COND_Z, I0, 0); \
102		UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \
	79	UML_XOR(block, uml::I1, rn, op2); \
	80	UML_XOR(block, uml::I2, rn, rd); \
	81	UML_AND(block, uml::I1, uml::I1, uml::I2); \
	82	UML_TEST(block, uml::I1, 1 << 31); \
	83	UML_MOVc(block, uml::COND_NZ, uml::I1, V_BIT); \
	84	UML_MOVc(block, uml::COND_Z, uml::I1, 0); \
	85	UML_OR(block, uml::I0, uml::I0, uml::I1); \
	86	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0); \
	87	UML_AND(block, uml::I0, rd, 1 << 31); \
	88	UML_AND(block, uml::I1, op2, 1 << 31); \
	89	UML_AND(block, uml::I2, rn, 1 << 31); \
	90	UML_XOR(block, uml::I2, uml::I2, ~0); \
	91	UML_AND(block, uml::I1, uml::I1, uml::I2); \
	92	UML_AND(block, uml::I2, uml::I2, uml::I0); \
	93	UML_OR(block, uml::I1, uml::I1, uml::I2); \
	94	UML_AND(block, uml::I2, op2, 1 << 31); \
	95	UML_AND(block, uml::I2, uml::I2, uml::I0); \
	96	UML_OR(block, uml::I1, uml::I1, uml::I2); \
	97	UML_TEST(block, uml::I1, 1 << 31); \
	98	UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK); \
	99	UML_MOVc(block, uml::COND_Z, uml::I0, 0); \
	100	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0); \
103	101	UML_ADD(block, DRC_PC, DRC_PC, 2);
104	102
105	103	/* Set NZC flags for logical operations. */
r24074	r24075
109	107	#define HandleALUNZFlags(rd) \
110	108	(((rd) & SIGN_BIT) \| ((!(rd)) << Z_BIT))
111	109
112		#define DRCHandleALUNZFlags(rd) \
113		UML_AND(block, I0, rd, SIGN_BIT); \
114		UML_CMP(block, rd, 0); \
115		UML_MOVc(block, COND_E, I1, 1); \
116		UML_MOVc(block, COND_NE, I1, 0); \
117		UML_ROLINS(block, I0, I1, Z_BIT, 1 << Z_BIT);
	110	#define DRCHandleALUNZFlags(rd) \
	111	UML_AND(block, uml::I0, rd, SIGN_BIT); \
	112	UML_CMP(block, rd, 0); \
	113	UML_MOVc(block, uml::COND_E, uml::I1, 1); \
	114	UML_MOVc(block, uml::COND_NE, uml::I1, 0); \
	115	UML_ROLINS(block, uml::I0, uml::I1, Z_BIT, 1 << Z_BIT);
118	116
119	117	// Long ALU Functions use bit 63
120	118	#define HandleLongALUNZFlags(rd) \
r24074	r24075
127	125	\| (((sc) != 0) << C_BIT))); \
128	126	R15 += 4;
129	127
130		#define DRC_RD mem(&GET_REGISTER(arm, rd))
131		#define DRC_RS mem(&GET_REGISTER(arm, rs))
132		#define DRC_CPSR mem(&GET_CPSR)
133		#define DRC_PC mem(&R15)
134		#define DRC_REG(i) mem(&arm->r[(i)]);
	128	#define DRC_RD uml::mem(&GET_REGISTER(rd))
	129	#define DRC_RS uml::mem(&GET_REGISTER(rs))
	130	#define DRC_CPSR uml::mem(&GET_CPSR)
	131	#define DRC_PC uml::mem(&R15)
	132	#define DRC_REG(i) uml::mem(&m_r[(i)])
135	133
136	134	#define DRCHandleALULogicalFlags(rd, sc) \
137	135	if (insn & INSN_S) \
r24074	r24075
139	137	UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK \| Z_MASK \| C_MASK); \
140	138	DRCHandleALUNZFlags(rd); \
141	139	UML_TEST(block, sc, ~0); \
142		UML_MOVc(block, COND_Z, I1, C_BIT); \
143		UML_MOVc(block, COND_NZ, I1, 0); \
144		UML_OR(block, I0, I0, I1); \
145		UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \
	140	UML_MOVc(block, uml::COND_Z, uml::I1, C_BIT); \
	141	UML_MOVc(block, uml::COND_NZ, uml::I1, 0); \
	142	UML_OR(block, uml::I0, uml::I0, uml::I1); \
	143	UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0); \
146	144	} \
147	145	UML_ADD(block, DRC_PC, DRC_PC, 4);
148	146
149		void set_cpsr( arm_state *arm, UINT32 val);
150	147
151	148	// used to be functions, but no longer a need, so we'll use define for better speed.
152		#define GetRegister(arm, rIndex) ARM7REG(sRegisterTable[GET_MODE][rIndex])
153		#define SetRegister(arm, rIndex, value) ARM7REG(sRegisterTable[GET_MODE][rIndex]) = value
	149	#define GetRegister(rIndex) m_r[sRegisterTable[GET_MODE][rIndex]]
	150	#define SetRegister(rIndex, value) m_r[sRegisterTable[GET_MODE][rIndex]] = value
154	151
155		#define GetModeRegister(arm, mode, rIndex) ARM7REG(sRegisterTable[mode][rIndex])
156		#define SetModeRegister(arm, mode, rIndex, value) ARM7REG(sRegisterTable[mode][rIndex]) = value
	152	#define GetModeRegister(mode, rIndex) m_r[sRegisterTable[mode][rIndex]]
	153	#define SetModeRegister(mode, rIndex, value) m_r[sRegisterTable[mode][rIndex]] = value
157	154
158		int arm7_tlb_translate(arm_state arm, UINT32 addr, int flags);
159		void arm7_check_irq_state(arm_state *arm);
160	155
161		typedef const void (arm7thumb_ophandler)(arm_state, UINT32, UINT32);
162		extern arm7thumb_ophandler thumb_handler[0x40*0x10];
163
164		typedef const void (arm7ops_ophandler)(arm_state, UINT32);
165
166		extern arm7ops_ophandler ops_handler[0x10];
167
168		extern void (arm7_coproc_dt_r_callback)(arm_state arm, UINT32 insn, UINT32 prn, UINT32 (read32)(arm_state *arm, UINT32 addr));
169		extern void (arm7_coproc_dt_w_callback)(arm_state arm, UINT32 insn, UINT32 prn, void (write32)(arm_state *arm, UINT32 addr, UINT32 data));
170
171
172		/***************************************************************************
173		* Default Memory Handlers
174		***************************************************************************/
175		INLINE void arm7_cpu_write32(arm_state *arm, UINT32 addr, UINT32 data)
176		{
177		if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
178		{
179		if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D \| ARM7_TLB_WRITE ))
180		{
181		return;
182		}
183		}
184
185		addr &= ~3;
186		if ( arm->endian == ENDIANNESS_BIG )
187		arm->program->write_dword(addr, data);
188		else
189		arm->program->write_dword(addr, data);
190		}
191
192
193		INLINE void arm7_cpu_write16(arm_state *arm, UINT32 addr, UINT16 data)
194		{
195		if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
196		{
197		if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D \| ARM7_TLB_WRITE ))
198		{
199		return;
200		}
201		}
202
203		addr &= ~1;
204		if ( arm->endian == ENDIANNESS_BIG )
205		arm->program->write_word(addr, data);
206		else
207		arm->program->write_word(addr, data);
208		}
209
210		INLINE void arm7_cpu_write8(arm_state *arm, UINT32 addr, UINT8 data)
211		{
212		if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
213		{
214		if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D \| ARM7_TLB_WRITE ))
215		{
216		return;
217		}
218		}
219
220		if ( arm->endian == ENDIANNESS_BIG )
221		arm->program->write_byte(addr, data);
222		else
223		arm->program->write_byte(addr, data);
224		}
225
226		INLINE UINT32 arm7_cpu_read32(arm_state *arm, UINT32 addr)
227		{
228		UINT32 result;
229
230		if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
231		{
232		if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D \| ARM7_TLB_READ ))
233		{
234		return 0;
235		}
236		}
237
238		if (addr & 3)
239		{
240		if ( arm->endian == ENDIANNESS_BIG )
241		result = arm->program->read_dword(addr & ~3);
242		else
243		result = arm->program->read_dword(addr & ~3);
244		result = (result >> (8 * (addr & 3))) \| (result << (32 - (8 * (addr & 3))));
245		}
246		else
247		{
248		if ( arm->endian == ENDIANNESS_BIG )
249		result = arm->program->read_dword(addr);
250		else
251		result = arm->program->read_dword(addr);
252		}
253
254		return result;
255		}
256
257		INLINE UINT16 arm7_cpu_read16(arm_state *arm, UINT32 addr)
258		{
259		UINT16 result;
260
261		if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
262		{
263		if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D \| ARM7_TLB_READ ))
264		{
265		return 0;
266		}
267		}
268
269		if ( arm->endian == ENDIANNESS_BIG )
270		result = arm->program->read_word(addr & ~1);
271		else
272		result = arm->program->read_word(addr & ~1);
273
274		if (addr & 1)
275		{
276		result = ((result >> 8) & 0xff) \| ((result & 0xff) << 8);
277		}
278
279		return result;
280		}
281
282		INLINE UINT8 arm7_cpu_read8(arm_state *arm, UINT32 addr)
283		{
284		if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
285		{
286		if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D \| ARM7_TLB_READ ))
287		{
288		return 0;
289		}
290		}
291
292		// Handle through normal 8 bit handler (for 32 bit cpu)
293		if ( arm->endian == ENDIANNESS_BIG )
294		return arm->program->read_byte(addr);
295		else
296		return arm->program->read_byte(addr);
297		}
298
299
300	156	/* Macros that can be re-defined for custom cpu implementations - The core expects these to be defined */
301	157	/* In this case, we are using the default arm7 handlers (supplied by the core)
302	158	- but simply changes these and define your own if needed for cpu implementation specific needs */
303		#define READ8(addr) arm7_cpu_read8(arm, addr)
304		#define WRITE8(addr,data) arm7_cpu_write8(arm, addr,data)
305		#define READ16(addr) arm7_cpu_read16(arm, addr)
306		#define WRITE16(addr,data) arm7_cpu_write16(arm, addr,data)
307		#define READ32(addr) arm7_cpu_read32(arm, addr)
308		#define WRITE32(addr,data) arm7_cpu_write32(arm, addr,data)
	159	#define READ8(addr) arm7_cpu_read8(addr)
	160	#define WRITE8(addr,data) arm7_cpu_write8(addr,data)
	161	#define READ16(addr) arm7_cpu_read16(addr)
	162	#define WRITE16(addr,data) arm7_cpu_write16(addr,data)
	163	#define READ32(addr) arm7_cpu_read32(addr)
	164	#define WRITE32(addr,data) arm7_cpu_write32(addr,data)
309	165	#define PTR_READ32 &arm7_cpu_read32
310	166	#define PTR_WRITE32 &arm7_cpu_write32

trunk/src/emu/cpu/arm7/arm7.c
r24074	r24075
33	33
34	34	See the notes in the arm7core.c file itself regarding issues/limitations of the arm7 core.
35	35	**
	36
	37	TODO:
	38	- Cleanups
	39	- Fix and finish the DRC code, or remove it entirely
	40
36	41	*****************************************************************************/
37	42	#include "emu.h"
38	43	#include "debugger.h"
39	44	#include "arm7.h"
40	45	#include "arm7core.h" //include arm7 core
41		#include "arm7thmb.h"
42	46	#include "arm7help.h"
43	47
44	48
45	49	/* prototypes of coprocessor functions */
46		static DECLARE_WRITE32_DEVICE_HANDLER(arm7_do_callback);
47		static DECLARE_READ32_DEVICE_HANDLER(arm7_rt_r_callback);
48		static DECLARE_WRITE32_DEVICE_HANDLER(arm7_rt_w_callback);
49	50	void arm7_dt_r_callback(arm_state arm, UINT32 insn, UINT32 prn, UINT32 (read32)(arm_state arm, UINT32 addr));
50	51	void arm7_dt_w_callback(arm_state arm, UINT32 insn, UINT32 prn, void (write32)(arm_state arm, UINT32 addr, UINT32 data));
51	52
r24074	r24075
54	55	void (arm7_coproc_dt_w_callback)(arm_state arm, UINT32 insn, UINT32 prn, void (write32)(arm_state *arm, UINT32 addr, UINT32 data));
55	56
56	57
57		INLINE arm_state get_safe_token(device_t device)
	58	const device_type ARM7 = &device_creator<arm7_cpu_device>;
	59	const device_type ARM7_BE = &device_creator<arm7_be_cpu_device>;
	60	const device_type ARM7500 = &device_creator<arm7500_cpu_device>;
	61	const device_type ARM9 = &device_creator<arm9_cpu_device>;
	62	const device_type ARM920T = &device_creator<arm920t_cpu_device>;
	63	const device_type PXA255 = &device_creator<pxa255_cpu_device>;
	64	const device_type SA1110 = &device_creator<sa1110_cpu_device>;
	65
	66
	67	arm7_cpu_device::arm7_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	68	: cpu_device(mconfig, ARM7, "ARM7", tag, owner, clock, "arm7", __FILE__)
	69	, m_program_config("program", ENDIANNESS_LITTLE, 32, 32, 0)
	70	, m_endian(ENDIANNESS_LITTLE)
	71	, m_archRev(4) // ARMv4
	72	, m_archFlags(eARM_ARCHFLAGS_T) // has Thumb
	73	, m_copro_id(0x41 \| (1 << 23) \| (7 << 12)) // <-- where did this come from?
58	74	{
59		assert(device != NULL);
60		assert(device->type() == ARM7 \|\| device->type() == ARM7_BE \|\| device->type() == ARM7500 \|\| device->type() == ARM9 \|\| device->type() == ARM920T \|\| device->type() == PXA255);
61		return (arm_state )downcast<legacy_cpu_device >(device)->token();
62	75	}
63	76
64		void set_cpsr( arm_state *arm, UINT32 val)
	77
	78	arm7_cpu_device::arm7_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source, UINT8 archRev, UINT8 archFlags, endianness_t endianness)
	79	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
	80	, m_program_config("program", endianness, 32, 32, 0)
	81	, m_endian(endianness)
	82	, m_archRev(archRev)
	83	, m_archFlags(archFlags)
	84	, m_copro_id(0x41 \| (1 << 23) \| (7 << 12)) // <-- where did this come from?
65	85	{
66		if (arm->archFlags & eARM_ARCHFLAGS_MODE26)
	86	}
	87
	88
	89	arm7_be_cpu_device::arm7_be_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	90	: arm7_cpu_device(mconfig, ARM7_BE, "ARM7 (big endian)", tag, owner, clock, "arm7 be", __FILE__, 4, eARM_ARCHFLAGS_T, ENDIANNESS_BIG)
	91	{
	92	}
	93
	94
	95	arm7500_cpu_device::arm7500_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	96	: arm7_cpu_device(mconfig, ARM7500, "ARM7500", tag, owner, clock, "arm7500", __FILE__, 3, eARM_ARCHFLAGS_MODE26)
	97	{
	98	m_copro_id = (0x41 << 24) \| (0 << 20) \| (1 << 16) \| (0x710 << 4) \| (0 << 0);
	99	}
	100
	101
	102	arm9_cpu_device::arm9_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	103	: arm7_cpu_device(mconfig, ARM9, "ARM9", tag, owner, clock, "arm9", __FILE__, 5, eARM_ARCHFLAGS_T \| eARM_ARCHFLAGS_E)
	104	// ARMv5
	105	// has TE extensions
	106	{
	107	}
	108
	109
	110	arm920t_cpu_device::arm920t_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	111	: arm7_cpu_device(mconfig, ARM920T, "ARM920T", tag, owner, clock, "arm920t", __FILE__, 4, eARM_ARCHFLAGS_T)
	112	// ARMv4
	113	// has T extension
	114	{
	115	m_copro_id = (0x41 << 24) \| (1 << 20) \| (2 << 16) \| (0x920 << 4) \| (0 << 0);
	116	}
	117
	118
	119	pxa255_cpu_device::pxa255_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	120	: arm7_cpu_device(mconfig, PXA255, "PXA255", tag, owner, clock, "pxa255", __FILE__, 5, eARM_ARCHFLAGS_T \| eARM_ARCHFLAGS_E \| eARM_ARCHFLAGS_XSCALE)
	121	// ARMv5
	122	// has TE and XScale extensions
	123	{
	124	}
	125
	126
	127	sa1110_cpu_device::sa1110_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	128	: arm7_cpu_device(mconfig, SA1110, "SA1110", tag, owner, clock, "sa1110", __FILE__, 4, eARM_ARCHFLAGS_SA)
	129	// ARMv4
	130	// has StrongARM, no Thumb, no Enhanced DSP
	131	{
	132	}
	133
	134
	135	void arm7_cpu_device::set_cpsr(UINT32 val)
	136	{
	137	if (m_archFlags & eARM_ARCHFLAGS_MODE26)
67	138	{
68		if ((val & 0x10) != (~~ARM7REG(~~eCPSR) & 0x10))
	139	if ((val & 0x10) != (m_r[eCPSR] & 0x10))
69	140	{
70	141	if (val & 0x10)
71	142	{
72	143	// 26 -> 32
73		val = (val & 0x0FFFFF3F) \| (R15 & 0xF0000000) /* N Z C V / \| ((R15 & 0x0C000000) >> (26 - 6)) / I F */;
74		R15 = R15 & 0x03FFFFFC;
	144	val = (val & 0x0FFFFF3F) \| (m_r[eR15] & 0xF0000000) /* N Z C V / \| ((m_r[eR15] & 0x0C000000) >> (26 - 6)) / I F */;
	145	m_r[eR15] = m_r[eR15] & 0x03FFFFFC;
75	146	}
76	147	else
77	148	{
78	149	// 32 -> 26
79		R15 = (R15 & 0x03FFFFFC) /* PC / \| (val & 0xF0000000) / N Z C V / \| ((val & 0x000000C0) << (26 - 6)) / I F / \| (val & 0x00000003) / M1 M0 */;
	150	m_r[eR15] = (m_r[eR15] & 0x03FFFFFC) /* PC / \| (val & 0xF0000000) / N Z C V / \| ((val & 0x000000C0) << (26 - 6)) / I F / \| (val & 0x00000003) / M1 M0 */;
80	151	}
81	152	}
82	153	else
r24074	r24075
84	155	if (!(val & 0x10))
85	156	{
86	157	// mirror bits in pc
87		R15 = (R15 & 0x03FFFFFF) \| (val & 0xF0000000) /* N Z C V / \| ((val & 0x000000C0) << (26 - 6)) / I F */;
	158	m_r[eR15] = (m_r[eR15] & 0x03FFFFFF) \| (val & 0xF0000000) /* N Z C V / \| ((val & 0x000000C0) << (26 - 6)) / I F */;
88	159	}
89	160	}
90	161	}
r24074	r24075
92	163	{
93	164	val \|= 0x10; // force valid mode
94	165	}
95		~~ARM7REG(~~eCPSR) = val;
	166	m_r[eCPSR] = val;
96	167	}
97	168
98	169
r24074	r24075
113	184	FAULT_PERMISSION,
114	185	};
115	186
116		INLINE UINT32 arm7_tlb_get_first_level_descriptor( arm_state *arm, UINT32 vaddr )
	187
	188	UINT32 arm7_cpu_device::arm7_tlb_get_first_level_descriptor( UINT32 vaddr )
117	189	{
118		UINT32 entry_paddr = ( COPRO_TLB_BASE & COPRO_TLB_BASE_MASK ) \| ( ( vaddr & COPRO_TLB_VADDR_FLTI_MASK ) >> COPRO_TLB_VADDR_FLTI_MASK_SHIFT );
119		return arm->program->read_dword( entry_paddr );
	190	UINT32 entry_paddr = ( m_tlbBase & COPRO_TLB_BASE_MASK ) \| ( ( vaddr & COPRO_TLB_VADDR_FLTI_MASK ) >> COPRO_TLB_VADDR_FLTI_MASK_SHIFT );
	191	return m_program->read_dword( entry_paddr );
120	192	}
121	193
	194
122	195	// COARSE, desc_level1, vaddr
123		~~INLINE~~ UINT32 arm7_tlb_get_second_level_descriptor( ~~arm_state *arm,~~ UINT32 granularity, UINT32 first_desc, UINT32 vaddr )
	196	UINT32 arm7_cpu_device::arm7_tlb_get_second_level_descriptor( UINT32 granularity, UINT32 first_desc, UINT32 vaddr )
124	197	{
125	198	UINT32 desc_lvl2 = vaddr;
126	199
r24074	r24075
138	211	break;
139	212	}
140	213
141		return arm->program->read_dword( desc_lvl2 );
	214	return m_program->read_dword( desc_lvl2 );
142	215	}
143	216
144		INLINE int detect_fault( arm_state *arm, int permission, int ap, int flags)
	217
	218	int arm7_cpu_device::detect_fault(int permission, int ap, int flags)
145	219	{
146	220	switch (permission)
147	221	{
r24074	r24075
156	230	{
157	231	case 0 :
158	232	{
159		int s = (COPRO_CTRL & COPRO_CTRL_SYSTEM) ? 1 : 0;
160		int r = (COPRO_CTRL & COPRO_CTRL_ROM) ? 1 : 0;
	233	int s = (m_control & COPRO_CTRL_SYSTEM) ? 1 : 0;
	234	int r = (m_control & COPRO_CTRL_ROM) ? 1 : 0;
161	235	if (s == 0)
162	236	{
163	237	if (r == 0) // "Any access generates a permission fault"
r24074	r24075
176	250	{
177	251	if (r == 0) // "Only Supervisor read permitted"
178	252	{
179		if ((~~GET~~_MODE == eARM7_MODE_USER) \|\| (flags & ARM7_TLB_WRITE))
	253	if (((m_r[eCPSR] & MODE_FLAG) == eARM7_MODE_USER) \|\| (flags & ARM7_TLB_WRITE))
180	254	{
181	255	return FAULT_PERMISSION;
182	256	}
r24074	r24075
190	264	break;
191	265	case 1 : // "Access allowed only in Supervisor mode"
192	266	{
193		if (~~GET~~_MODE == eARM7_MODE_USER)
	267	if ((m_r[eCPSR] & MODE_FLAG) == eARM7_MODE_USER)
194	268	{
195	269	return FAULT_PERMISSION;
196	270	}
r24074	r24075
198	272	break;
199	273	case 2 : // "Writes in User mode cause permission fault"
200	274	{
201		if ((~~GET~~_MODE == eARM7_MODE_USER) && (flags & ARM7_TLB_WRITE))
	275	if (((m_r[eCPSR] & MODE_FLAG) == eARM7_MODE_USER) && (flags & ARM7_TLB_WRITE))
202	276	{
203	277	return FAULT_PERMISSION;
204	278	}
r24074	r24075
226	300	return FAULT_NONE;
227	301	}
228	302
229		int arm7_tlb_translate(arm_state arm, UINT32 addr, int flags)
	303
	304	bool arm7_cpu_device::arm7_tlb_translate(offs_t &addr, int flags)
230	305	{
231	306	UINT32 desc_lvl1;
232	307	UINT32 desc_lvl2 = 0;
233		UINT32 paddr, vaddr = *addr;
	308	UINT32 paddr, vaddr = addr;
234	309	UINT8 domain, permission;
235	310
236	311	if (vaddr < 32 * 1024 * 1024)
237	312	{
238		UINT32 pid = ((~~COPRO~~_~~FCSE_~~PID >> 25) & 0x7F);
	313	UINT32 pid = ((m_fcsePID >> 25) & 0x7F);
239	314	if (pid > 0)
240	315	{
241	316	//LOG( ( "ARM7: FCSE PID vaddr %08X -> %08X\n", vaddr, vaddr + (pid * (32 * 1024 * 1024))) );
242		vaddr = vaddr + (((~~COPRO~~_~~FCSE_~~PID >> 25) & 0x7F) * (32 * 1024 * 1024));
	317	vaddr = vaddr + (((m_fcsePID >> 25) & 0x7F) * (32 * 1024 * 1024));
243	318	}
244	319	}
245	320
246		desc_lvl1 = arm7_tlb_get_first_level_descriptor( ~~arm,~~ vaddr );
	321	desc_lvl1 = arm7_tlb_get_first_level_descriptor( vaddr );
247	322
248	323	paddr = vaddr;
249	324
250	325	#if ARM7_MMU_ENABLE_HACK
251		if ((R15 == (arm->mmu_enable_addr + 4)) \|\| (R15 == (arm->mmu_enable_addr + 8)))
	326	if ((m_r[eR15] == (m_mmu_enable_addr + 4)) \|\| (m_r[eR15] == (m_mmu_enable_addr + 8)))
252	327	{
253		LOG( ( "ARM7: fetch flat, PC = %08x, vaddr = %08x\n", R15, vaddr ) );
	328	LOG( ( "ARM7: fetch flat, PC = %08x, vaddr = %08x\n", m_r[eR15], vaddr ) );
254	329	*addr = vaddr;
255		return ~~TRUE~~;
	330	return true;
256	331	}
257	332	else
258	333	{
259		arm->mmu_enable_addr = 1;
	334	m_mmu_enable_addr = 1;
260	335	}
261	336	#endif
262	337
263	338	domain = (desc_lvl1 >> 5) & 0xF;
264		permission = (~~COPRO~~_~~DOM~~A~~IN_A~~C~~CESS_CONTROL~~ >> (domain << 1)) & 3;
	339	permission = (m_domainAccessControl >> (domain << 1)) & 3;
265	340
266	341	switch( desc_lvl1 & 3 )
267	342	{
r24074	r24075
269	344	// Unmapped, generate a translation fault
270	345	if (flags & ARM7_TLB_ABORT_D)
271	346	{
272		LOG( ( "ARM7: Translation fault on unmapped virtual address, PC = %08x, vaddr = %08x\n", R15, vaddr ) );
273		COPRO_FAULT_STATUS_D = (5 << 0); // 5 = section translation fault
274		COPRO_FAULT_ADDRESS = vaddr;
275		arm->pendingAbtD = 1;
	347	LOG( ( "ARM7: Translation fault on unmapped virtual address, PC = %08x, vaddr = %08x\n", m_r[eR15], vaddr ) );
	348	m_faultStatus[0] = (5 << 0); // 5 = section translation fault
	349	m_faultAddress = vaddr;
	350	m_pendingAbtD = 1;
276	351	}
277	352	else if (flags & ARM7_TLB_ABORT_P)
278	353	{
279		LOG( ( "ARM7: Translation fault on unmapped virtual address, PC = %08x, vaddr = %08x\n", R15, vaddr ) );
280		arm->pendingAbtP = 1;
	354	LOG( ( "ARM7: Translation fault on unmapped virtual address, PC = %08x, vaddr = %08x\n", m_r[eR15], vaddr ) );
	355	m_pendingAbtP = 1;
281	356	}
282	357	return FALSE;
283	358	case COPRO_TLB_COARSE_TABLE:
284	359	// Entry is the physical address of a coarse second-level table
285	360	if ((permission == 1) \|\| (permission == 3))
286	361	{
287		desc_lvl2 = arm7_tlb_get_second_level_descriptor( ~~arm,~~ TLB_COARSE, desc_lvl1, vaddr );
	362	desc_lvl2 = arm7_tlb_get_second_level_descriptor( TLB_COARSE, desc_lvl1, vaddr );
288	363	}
289	364	else
290	365	{
291		fatalerror("ARM7: Not Yet Implemented: Coarse Table, Section Domain fault on virtual address, vaddr = %08x, domain = %08x, PC = %08x\n", vaddr, domain, R15);
	366	fatalerror("ARM7: Not Yet Implemented: Coarse Table, Section Domain fault on virtual address, vaddr = %08x, domain = %08x, PC = %08x\n", vaddr, domain, m_r[eR15]);
292	367	}
293	368	break;
294	369	case COPRO_TLB_SECTION_TABLE:
295	370	{
296	371	// Entry is a section
297	372	UINT8 ap = (desc_lvl1 >> 10) & 3;
298		int fault = detect_fault( ~~arm,~~ permission, ap, flags);
	373	int fault = detect_fault(permission, ap, flags);
299	374	if (fault == FAULT_NONE)
300	375	{
301	376	paddr = ( desc_lvl1 & COPRO_TLB_SECTION_PAGE_MASK ) \| ( vaddr & ~COPRO_TLB_SECTION_PAGE_MASK );
r24074	r24075
304	379	{
305	380	if (flags & ARM7_TLB_ABORT_D)
306	381	{
307		LOG( ( "ARM7: Section Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
308		COPRO_FAULT_STATUS_D = ((fault == FAULT_DOMAIN) ? (9 << 0) : (13 << 0)) \| (domain << 4); // 9 = section domain fault, 13 = section permission fault
309		COPRO_FAULT_ADDRESS = vaddr;
310		arm->pendingAbtD = 1;
	382	LOG( ( "ARM7: Section Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, m_r[eR15] ) );
	383	m_faultStatus[0] = ((fault == FAULT_DOMAIN) ? (9 << 0) : (13 << 0)) \| (domain << 4); // 9 = section domain fault, 13 = section permission fault
	384	m_faultAddress = vaddr;
	385	m_pendingAbtD = 1;
311	386	LOG( ( "vaddr %08X desc_lvl1 %08X domain %d permission %d ap %d s %d r %d mode %d read %d write %d\n",
312		vaddr, desc_lvl1, domain, permission, ap, (COPRO_CTRL & COPRO_CTRL_SYSTEM) ? 1 : 0, (COPRO_CTRL & COPRO_CTRL_ROM) ? 1 : 0,
313		GET_MODE, flags & ARM7_TLB_READ ? 1 : 0, flags & ARM7_TLB_WRITE ? 1 : 0) );
	387	vaddr, desc_lvl1, domain, permission, ap, (m_control & COPRO_CTRL_SYSTEM) ? 1 : 0, (m_control & COPRO_CTRL_ROM) ? 1 : 0,
	388	m_r[eCPSR] & MODE_FLAG, flags & ARM7_TLB_READ ? 1 : 0, flags & ARM7_TLB_WRITE ? 1 : 0) );
314	389	}
315	390	else if (flags & ARM7_TLB_ABORT_P)
316	391	{
317		LOG( ( "ARM7: Section Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
318		arm->pendingAbtP = 1;
	392	LOG( ( "ARM7: Section Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, m_r[eR15] ) );
	393	m_pendingAbtP = 1;
319	394	}
320		return ~~FALSE~~;
	395	return false;
321	396	}
322	397	}
323	398	break;
r24074	r24075
325	400	// Entry is the physical address of a coarse second-level table
326	401	if ((permission == 1) \|\| (permission == 3))
327	402	{
328		desc_lvl2 = arm7_tlb_get_second_level_descriptor( ~~arm,~~ TLB_FINE, desc_lvl1, vaddr );
	403	desc_lvl2 = arm7_tlb_get_second_level_descriptor( TLB_FINE, desc_lvl1, vaddr );
329	404	}
330	405	else
331	406	{
332		fatalerror("ARM7: Not Yet Implemented: Fine Table, Section Domain fault on virtual address, vaddr = %08x, domain = %08x, PC = %08x\n", vaddr, domain, R15);
	407	fatalerror("ARM7: Not Yet Implemented: Fine Table, Section Domain fault on virtual address, vaddr = %08x, domain = %08x, PC = %08x\n", vaddr, domain, m_r[eR15]);
333	408	}
334	409	break;
335	410	default:
r24074	r24075
345	420	// Unmapped, generate a translation fault
346	421	if (flags & ARM7_TLB_ABORT_D)
347	422	{
348		LOG( ( "ARM7: Translation fault on unmapped virtual address, vaddr = %08x, PC %08X\n", vaddr, R15 ) );
349		COPRO_FAULT_STATUS_D = (7 << 0) \| (domain << 4); // 7 = page translation fault
350		COPRO_FAULT_ADDRESS = vaddr;
351		arm->pendingAbtD = 1;
	423	LOG( ( "ARM7: Translation fault on unmapped virtual address, vaddr = %08x, PC %08X\n", vaddr, m_r[eR15] ) );
	424	m_faultStatus[0] = (7 << 0) \| (domain << 4); // 7 = page translation fault
	425	m_faultAddress = vaddr;
	426	m_pendingAbtD = 1;
352	427	}
353	428	else if (flags & ARM7_TLB_ABORT_P)
354	429	{
355		LOG( ( "ARM7: Translation fault on unmapped virtual address, vaddr = %08x, PC %08X\n", vaddr, R15 ) );
356		arm->pendingAbtP = 1;
	430	LOG( ( "ARM7: Translation fault on unmapped virtual address, vaddr = %08x, PC %08X\n", vaddr, m_r[eR15] ) );
	431	m_pendingAbtP = 1;
357	432	}
358	433	return FALSE;
359	434	case COPRO_TLB_LARGE_PAGE:
r24074	r24075
364	439	// Small page descriptor
365	440	{
366	441	UINT8 ap = ((((desc_lvl2 >> 4) & 0xFF) >> (((vaddr >> 10) & 3) << 1)) & 3);
367		int fault = detect_fault( ~~arm,~~ permission, ap, flags);
	442	int fault = detect_fault(permission, ap, flags);
368	443	if (fault == FAULT_NONE)
369	444	{
370	445	paddr = ( desc_lvl2 & COPRO_TLB_SMALL_PAGE_MASK ) \| ( vaddr & ~COPRO_TLB_SMALL_PAGE_MASK );
r24074	r24075
374	449	if (flags & ARM7_TLB_ABORT_D)
375	450	{
376	451	// hapyfish expects a data abort when something tries to write to a read-only memory location from user mode
377		LOG( ( "ARM7: Page Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
378		COPRO_FAULT_STATUS_D = ((fault == FAULT_DOMAIN) ? (11 << 0) : (15 << 0)) \| (domain << 4); // 11 = page domain fault, 15 = page permission fault
379		COPRO_FAULT_ADDRESS = vaddr;
380		arm->pendingAbtD = 1;
	452	LOG( ( "ARM7: Page Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, m_r[eR15] ) );
	453	m_faultStatus[0] = ((fault == FAULT_DOMAIN) ? (11 << 0) : (15 << 0)) \| (domain << 4); // 11 = page domain fault, 15 = page permission fault
	454	m_faultAddress = vaddr;
	455	m_pendingAbtD = 1;
381	456	LOG( ( "vaddr %08X desc_lvl2 %08X domain %d permission %d ap %d s %d r %d mode %d read %d write %d\n",
382		vaddr, desc_lvl2, domain, permission, ap, (COPRO_CTRL & COPRO_CTRL_SYSTEM) ? 1 : 0, (COPRO_CTRL & COPRO_CTRL_ROM) ? 1 : 0,
383		GET_MODE, flags & ARM7_TLB_READ ? 1 : 0, flags & ARM7_TLB_WRITE ? 1 : 0) );
	457	vaddr, desc_lvl2, domain, permission, ap, (m_control & COPRO_CTRL_SYSTEM) ? 1 : 0, (m_control & COPRO_CTRL_ROM) ? 1 : 0,
	458	m_r[eCPSR] & MODE_FLAG, flags & ARM7_TLB_READ ? 1 : 0, flags & ARM7_TLB_WRITE ? 1 : 0) );
384	459	}
385	460	else if (flags & ARM7_TLB_ABORT_P)
386	461	{
387		LOG( ( "ARM7: Page Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
388		arm->pendingAbtP = 1;
	462	LOG( ( "ARM7: Page Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, m_r[eR15] ) );
	463	m_pendingAbtP = 1;
389	464	}
390		return ~~FALSE~~;
	465	return false;
391	466	}
392	467	}
393	468	break;
r24074	r24075
401	476	break;
402	477	}
403	478	}
404		*addr = paddr;
405		return TRUE;
	479	addr = paddr;
	480	return true;
406	481	}
407	482
408		static CPU_TRANSLATE( arm7 )
409		{
410		arm_state arm = (device != NULL) ? (arm_state )device->token() : NULL;
411	483
	484	bool arm7_cpu_device::memory_translate(address_spacenum spacenum, int intention, offs_t &address)
	485	{
412	486	/* only applies to the program address space and only does something if the MMU's enabled */
413		if( space == AS_PROGRAM && ( ~~COPRO~~_~~CTRL~~ & COPRO_CTRL_MMU_EN ) )
	487	if( spacenum == AS_PROGRAM && ( m_control & COPRO_CTRL_MMU_EN ) )
414	488	{
415		return arm7_tlb_translate(a~~rm, a~~ddress, 0);
	489	return arm7_tlb_translate(address, 0);
416	490	}
417		return ~~TRUE~~;
	491	return true;
418	492	}
419	493
420	494
r24074	r24075
424	498	/***************************************************************************
425	499	* CPU SPECIFIC IMPLEMENTATIONS
426	500	**************************************************************************/
427		static CPU_INIT( arm7 )
428		{
429		arm_state *arm = get_safe_token(device);
430	501
431		// must call core
432		arm7_core_init(device, "arm7");
433
434		arm->irq_callback = irqcallback;
435		arm->device = device;
436		arm->program = &device->space(AS_PROGRAM);
437		arm->direct = &arm->program->direct();
438
439		// setup co-proc callbacks
440		arm7_coproc_do_callback = arm7_do_callback;
441		arm7_coproc_rt_r_callback = arm7_rt_r_callback;
442		arm7_coproc_rt_w_callback = arm7_rt_w_callback;
443		arm7_coproc_dt_r_callback = arm7_dt_r_callback;
444		arm7_coproc_dt_w_callback = arm7_dt_w_callback;
445		}
446
447		static CPU_RESET( arm7 )
	502	void arm7_cpu_device::device_start()
448	503	{
449		arm_state *arm = get_safe_token(device);
	504	m_program = &space(AS_PROGRAM);
	505	m_direct = &m_program->direct();
450	506
451		// must call core reset
452		arm7_core_reset(device);
	507	save_item(NAME(m_r));
	508	save_item(NAME(m_pendingIrq));
	509	save_item(NAME(m_pendingFiq));
	510	save_item(NAME(m_pendingAbtD));
	511	save_item(NAME(m_pendingAbtP));
	512	save_item(NAME(m_pendingUnd));
	513	save_item(NAME(m_pendingSwi));
453	514
454		arm->archRev = 4; // ARMv4
455		arm->archFlags = eARM_ARCHFLAGS_T; // has Thumb
456		}
	515	m_icountptr = &m_icount;
457	516
458		static CPU_RESET( arm7_be )
459		{
460		arm_state *arm = get_safe_token(device);
	517	state_add(STATE_GENPC, "curpc", m_pc).callexport().formatstr("%08X");
	518	/* registers shared by all operating modes */
	519	state_add( ARM7_R0, "R0", m_r[ 0]).formatstr("%08X");
	520	state_add( ARM7_R1, "R1", m_r[ 1]).formatstr("%08X");
	521	state_add( ARM7_R2, "R2", m_r[ 2]).formatstr("%08X");
	522	state_add( ARM7_R3, "R3", m_r[ 3]).formatstr("%08X");
	523	state_add( ARM7_R4, "R4", m_r[ 4]).formatstr("%08X");
	524	state_add( ARM7_R5, "R5", m_r[ 5]).formatstr("%08X");
	525	state_add( ARM7_R6, "R6", m_r[ 6]).formatstr("%08X");
	526	state_add( ARM7_R7, "R7", m_r[ 7]).formatstr("%08X");
	527	state_add( ARM7_R8, "R8", m_r[ 8]).formatstr("%08X");
	528	state_add( ARM7_R9, "R9", m_r[ 9]).formatstr("%08X");
	529	state_add( ARM7_R10, "R10", m_r[10]).formatstr("%08X");
	530	state_add( ARM7_R11, "R11", m_r[11]).formatstr("%08X");
	531	state_add( ARM7_R12, "R12", m_r[12]).formatstr("%08X");
	532	state_add( ARM7_R13, "R13", m_r[13]).formatstr("%08X");
	533	state_add( ARM7_R14, "R14", m_r[14]).formatstr("%08X");
	534	state_add( ARM7_R15, "R15", m_r[15]).formatstr("%08X");
	535	/* FIRQ Mode Shadowed Registers */
	536	state_add( ARM7_FR8, "FR8", m_r[eR8_FIQ] ).formatstr("%08X");
	537	state_add( ARM7_FR9, "FR9", m_r[eR9_FIQ] ).formatstr("%08X");
	538	state_add( ARM7_FR10, "FR10", m_r[eR10_FIQ] ).formatstr("%08X");
	539	state_add( ARM7_FR11, "FR11", m_r[eR11_FIQ] ).formatstr("%08X");
	540	state_add( ARM7_FR12, "FR12", m_r[eR12_FIQ] ).formatstr("%08X");
	541	state_add( ARM7_FR13, "FR13", m_r[eR13_FIQ] ).formatstr("%08X");
	542	state_add( ARM7_FR14, "FR14", m_r[eR14_FIQ] ).formatstr("%08X");
	543	state_add( ARM7_FSPSR, "FR16", m_r[eSPSR_FIQ]).formatstr("%08X");
	544	/* IRQ Mode Shadowed Registers */
	545	state_add( ARM7_IR13, "IR13", m_r[eR13_IRQ] ).formatstr("%08X");
	546	state_add( ARM7_IR14, "IR14", m_r[eR14_IRQ] ).formatstr("%08X");
	547	state_add( ARM7_ISPSR, "IR16", m_r[eSPSR_IRQ]).formatstr("%08X");
	548	/* Supervisor Mode Shadowed Registers */
	549	state_add( ARM7_SR13, "SR13", m_r[eR13_SVC] ).formatstr("%08X");
	550	state_add( ARM7_SR14, "SR14", m_r[eR14_SVC] ).formatstr("%08X");
	551	state_add( ARM7_SSPSR, "SR16", m_r[eSPSR_SVC]).formatstr("%08X");
	552	/* Abort Mode Shadowed Registers */
	553	state_add( ARM7_AR13, "AR13", m_r[eR13_ABT] ).formatstr("%08X");
	554	state_add( ARM7_AR14, "AR14", m_r[eR14_ABT] ).formatstr("%08X");
	555	state_add( ARM7_ASPSR, "AR16", m_r[eSPSR_ABT]).formatstr("%08X");
	556	/* Undefined Mode Shadowed Registers */
	557	state_add( ARM7_UR13, "UR13", m_r[eR13_UND] ).formatstr("%08X");
	558	state_add( ARM7_UR14, "UR14", m_r[eR14_UND] ).formatstr("%08X");
	559	state_add( ARM7_USPSR, "UR16", m_r[eSPSR_UND]).formatstr("%08X");
461	560
462		CPU_RESET_CALL( arm7 );
463		arm->endian = ENDIANNESS_BIG;
	561	state_add(STATE_GENFLAGS, "GENFLAGS", m_r[eCPSR]).formatstr("%13s").noshow();
464	562	}
465	563
466		static CPU_RESET( arm7500 )
467		{
468		arm_state *arm = get_safe_token(device);
469	564
470		// must call core reset
471		arm7_core_reset(device);
472
473		arm->archRev = 3; // ARMv3
474		arm->archFlags = eARM_ARCHFLAGS_MODE26;
475		}
476
477		static CPU_RESET( arm9 )
	565	void arm7_cpu_device::state_export(const device_state_entry &entry)
478	566	{
479		arm_state *arm = get_safe_token(device);
480
481		// must call core reset
482		arm7_core_reset(device);
483
484		arm->archRev = 5; // ARMv5
485		arm->archFlags = eARM_ARCHFLAGS_T \| eARM_ARCHFLAGS_E; // has TE extensions
	567	switch (entry.index())
	568	{
	569	case STATE_GENPC:
	570	m_pc = GET_PC;
	571	break;
	572	}
486	573	}
487	574
488		static CPU_RESET( arm920t )
489		{
490		arm_state *arm = get_safe_token(device);
491	575
492		// must call core reset
493		arm7_core_reset(device);
494
495		arm->archRev = 4; // ARMv4
496		arm->archFlags = eARM_ARCHFLAGS_T; // has T extension
497		}
498
499		static CPU_RESET( pxa255 )
	576	void arm7_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
500	577	{
501		arm_state *arm = get_safe_token(device);
502
503		// must call core reset
504		arm7_core_reset(device);
505
506		arm->archRev = 5; // ARMv5
507		arm->archFlags = eARM_ARCHFLAGS_T \| eARM_ARCHFLAGS_E \| eARM_ARCHFLAGS_XSCALE; // has TE and XScale extensions
	578	switch (entry.index())
	579	{
	580	case STATE_GENFLAGS:
	581	string.printf("%c%c%c%c%c%c%c%c %s",
	582	(ARM7REG(eCPSR) & N_MASK) ? 'N' : '-',
	583	(ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-',
	584	(ARM7REG(eCPSR) & C_MASK) ? 'C' : '-',
	585	(ARM7REG(eCPSR) & V_MASK) ? 'V' : '-',
	586	(ARM7REG(eCPSR) & Q_MASK) ? 'Q' : '-',
	587	(ARM7REG(eCPSR) & I_MASK) ? 'I' : '-',
	588	(ARM7REG(eCPSR) & F_MASK) ? 'F' : '-',
	589	(ARM7REG(eCPSR) & T_MASK) ? 'T' : '-',
	590	GetModeText(ARM7REG(eCPSR)) );
	591	break;
	592	}
508	593	}
509	594
510		static ~~CPU~~_~~RESET(~~ s~~a1110~~ )
	595	void arm7_cpu_device::device_reset()
511	596	{
512		arm_state *arm = get_safe_token(device);
	597	memset(m_r, 0, sizeof(m_r));
	598	m_pendingIrq = 0;
	599	m_pendingFiq = 0;
	600	m_pendingAbtD = 0;
	601	m_pendingAbtP = 0;
	602	m_pendingUnd = 0;
	603	m_pendingSwi = 0;
	604	m_control = 0;
	605	m_tlbBase = 0;
	606	m_faultStatus[0] = 0;
	607	m_faultStatus[1] = 0;
	608	m_faultAddress = 0;
	609	m_fcsePID = 0;
	610	m_domainAccessControl = 0;
513	611
514		// must call core reset
515		arm7_core_reset(device);
	612	/* start up in SVC mode with interrupts disabled. */
	613	m_r[eCPSR] = I_MASK \| F_MASK \| 0x10;
	614	SwitchMode(eARM7_MODE_SVC);
	615	m_r[eR15] = 0;
516	616
517		arm->archRev = 4; // ARMv4
518		arm->archFlags = eARM_ARCHFLAGS_SA; // has StrongARM, no Thumb, no Enhanced DSP
	617	m_impstate.cache_dirty = TRUE;
519	618	}
520	619
521		static CPU_EXIT( arm7 )
522		{
523		/* nothing to do here */
524		}
525	620
526	621	#define UNEXECUTED() \
527		R15 += 4; \
528		ARM7_ICOUNT +=2; /* Any unexecuted instruction only takes 1 cycle (page 193) */
529		static CPU_EXECUTE( arm7 )
	622	m_r[eR15] += 4; \
	623	m_icount +=2; /* Any unexecuted instruction only takes 1 cycle (page 193) */
	624
	625	void arm7_cpu_device::execute_run()
530	626	{
531		UINT32 pc;
532	627	UINT32 insn;
533		arm_state *arm = get_safe_token(device);
534	628
535	629	do
536	630	{
537		~~debugger_instru~~c~~tion_hook(arm->device,~~ GET_PC);
	631	UINT32 pc = GET_PC;
538	632
	633	debugger_instruction_hook(this, pc);
	634
539	635	/* handle Thumb instructions if active */
540		if (T_IS_SET(~~GET~~_CPSR))
	636	if (T_IS_SET(m_r[eCPSR]))
541	637	{
542		~~UINT32~~ raddr;
	638	offs_t raddr;
543	639
544		pc = R15;
	640	pc = m_r[eR15];
545	641
546	642	// "In Thumb state, bit [0] is undefined and must be ignored. Bits [31:1] contain the PC."
547	643	raddr = pc & (~1);
548	644
549		if ( ~~COPRO~~_~~CTRL~~ & COPRO_CTRL_MMU_EN )
	645	if ( m_control & COPRO_CTRL_MMU_EN )
550	646	{
551		if (!arm7_tlb_translate(~~arm, &~~raddr, ARM7_TLB_ABORT_P \| ARM7_TLB_READ))
	647	if (!arm7_tlb_translate(raddr, ARM7_TLB_ABORT_P \| ARM7_TLB_READ))
552	648	{
553	649	goto skip_exec;
554	650	}
555	651	}
556	652
557		insn = arm->direct->read_decrypted_word(raddr);
558		thumb_handler[(insn & 0xffc0) >> 6](arm, pc, insn);
	653	insn = m_direct->read_decrypted_word(raddr);
	654	(this->*thumb_handler[(insn & 0xffc0) >> 6])(pc, insn);
559	655
560	656	}
561	657	else
562	658	{
563		~~UINT32~~ raddr;
	659	offs_t raddr;
564	660
565	661	/* load 32 bit instruction */
566		pc = GET_PC;
567	662
568	663	// "In ARM state, bits [1:0] of r15 are undefined and must be ignored. Bits [31:2] contain the PC."
569	664	raddr = pc & (~3);
570	665
571		if ( COPRO_CTRL & COPRO_CTRL_MMU_EN )
572		{
573		if (!arm7_tlb_translate(arm, &raddr, ARM7_TLB_ABORT_P \| ARM7_TLB_READ))
	666	if ( m_control & COPRO_CTRL_MMU_EN )
574	667	{
575		goto skip_exec;
	668	if (!arm7_tlb_translate(raddr, ARM7_TLB_ABORT_P \| ARM7_TLB_READ))
	669	{
	670	goto skip_exec;
	671	}
576	672	}
577		}
578	673
579	674	#if 0
580	675	if (MODE26)
r24074	r24075
586	681	}
587	682	#endif
588	683
589		insn = arm->direct->read_decrypted_dword(raddr);
	684	insn = m_direct->read_decrypted_dword(raddr);
590	685
591	686	/* process condition codes for this instruction */
592	687	switch (insn >> INSN_COND_SHIFT)
593	688	{
594	689	case COND_EQ:
595		if (Z_IS_CLEAR(~~GET~~_CPSR))
	690	if (Z_IS_CLEAR(m_r[eCPSR]))
596	691	{ UNEXECUTED(); goto skip_exec; }
597	692	break;
598	693	case COND_NE:
599		if (Z_IS_SET(~~GET~~_CPSR))
	694	if (Z_IS_SET(m_r[eCPSR]))
600	695	{ UNEXECUTED(); goto skip_exec; }
601	696	break;
602	697	case COND_CS:
603		if (C_IS_CLEAR(~~GET~~_CPSR))
	698	if (C_IS_CLEAR(m_r[eCPSR]))
604	699	{ UNEXECUTED(); goto skip_exec; }
605	700	break;
606	701	case COND_CC:
607		if (C_IS_SET(~~GET~~_CPSR))
	702	if (C_IS_SET(m_r[eCPSR]))
608	703	{ UNEXECUTED(); goto skip_exec; }
609	704	break;
610	705	case COND_MI:
611		if (N_IS_CLEAR(~~GET~~_CPSR))
	706	if (N_IS_CLEAR(m_r[eCPSR]))
612	707	{ UNEXECUTED(); goto skip_exec; }
613	708	break;
614	709	case COND_PL:
615		if (N_IS_SET(~~GET~~_CPSR))
	710	if (N_IS_SET(m_r[eCPSR]))
616	711	{ UNEXECUTED(); goto skip_exec; }
617	712	break;
618	713	case COND_VS:
619		if (V_IS_CLEAR(~~GET~~_CPSR))
	714	if (V_IS_CLEAR(m_r[eCPSR]))
620	715	{ UNEXECUTED(); goto skip_exec; }
621	716	break;
622	717	case COND_VC:
623		if (V_IS_SET(~~GET~~_CPSR))
	718	if (V_IS_SET(m_r[eCPSR]))
624	719	{ UNEXECUTED(); goto skip_exec; }
625	720	break;
626	721	case COND_HI:
627		if (C_IS_CLEAR(~~GET~~_CPSR) \|\| Z_IS_SET(~~GET~~_CPSR))
	722	if (C_IS_CLEAR(m_r[eCPSR]) \|\| Z_IS_SET(m_r[eCPSR]))
628	723	{ UNEXECUTED(); goto skip_exec; }
629	724	break;
630	725	case COND_LS:
631		if (C_IS_SET(~~GET~~_CPSR) && Z_IS_CLEAR(~~GET~~_CPSR))
	726	if (C_IS_SET(m_r[eCPSR]) && Z_IS_CLEAR(m_r[eCPSR]))
632	727	{ UNEXECUTED(); goto skip_exec; }
633	728	break;
634	729	case COND_GE:
635		if (!(~~GET~~_CPSR & N_MASK) != !(~~GET~~_CPSR & V_MASK)) /* Use x ^ (x >> ...) method */
	730	if (!(m_r[eCPSR] & N_MASK) != !(m_r[eCPSR] & V_MASK)) /* Use x ^ (x >> ...) method */
636	731	{ UNEXECUTED(); goto skip_exec; }
637	732	break;
638	733	case COND_LT:
639		if (!(~~GET~~_CPSR & N_MASK) == !(~~GET~~_CPSR & V_MASK))
	734	if (!(m_r[eCPSR] & N_MASK) == !(m_r[eCPSR] & V_MASK))
640	735	{ UNEXECUTED(); goto skip_exec; }
641	736	break;
642	737	case COND_GT:
643		if (Z_IS_SET(~~GET~~_CPSR) \|\| (!(~~GET~~_CPSR & N_MASK) != !(~~GET~~_CPSR & V_MASK)))
	738	if (Z_IS_SET(m_r[eCPSR]) \|\| (!(m_r[eCPSR] & N_MASK) != !(m_r[eCPSR] & V_MASK)))
644	739	{ UNEXECUTED(); goto skip_exec; }
645	740	break;
646	741	case COND_LE:
647		if (Z_IS_CLEAR(~~GET~~_CPSR) && (!(~~GET~~_CPSR & N_MASK) == !(~~GET~~_CPSR & V_MASK)))
	742	if (Z_IS_CLEAR(m_r[eCPSR]) && (!(m_r[eCPSR] & N_MASK) == !(m_r[eCPSR] & V_MASK)))
648	743	{ UNEXECUTED(); goto skip_exec; }
649	744	break;
650	745	case COND_NV:
r24074	r24075
654	749	/*******************************************************************/
655	750	/* If we got here - condition satisfied, so decode the instruction */
656	751	/*******************************************************************/
657		ops_handler[((insn & 0xF000000) >> 24)](~~arm,~~ insn);
	752	(this->*ops_handler[((insn & 0xF000000) >> 24)])(insn);
658	753	}
659	754
660	755	skip_exec:
661	756
662		~~ARM~~7_~~CHECKIRQ~~;
	757	arm7_check_irq_state();
663	758
664	759	/* All instructions remove 3 cycles.. Others taking less / more will have adjusted this # prior to here */
665		ARM7_ICOUNT -= 3;
666		} while (ARM7_ICOUNT > 0);
	760	m_icount -= 3;
	761	} while (m_icount > 0);
667	762	}
668	763
669		static void set_irq_line(arm_state *arm, int irqline, int state)
670		{
671		// must call core
672		arm7_core_set_irq_line(arm, irqline, state);
673		}
674	764
675		static ~~CPU~~_~~DISASSEMBLE~~( arm7 )
	765	void arm7_cpu_device::execute_set_input(int irqline, int state)
676	766	{
677		CPU_DISASSEMBLE( arm7arm );
678		CPU_DISASSEMBLE( arm7thumb );
	767	switch (irqline) {
	768	case ARM7_IRQ_LINE: /* IRQ */
	769	m_pendingIrq = state & 1;
	770	break;
679	771
680		arm_state *arm = get_safe_token(device);
	772	case ARM7_FIRQ_LINE: /* FIRQ */
	773	m_pendingFiq = state & 1;
	774	break;
681	775
682		if (T_IS_SET(GET_CPSR))
683		return CPU_DISASSEMBLE_CALL(arm7thumb);
684		else
685		return CPU_DISASSEMBLE_CALL(arm7arm);
686		}
687
688		static CPU_DISASSEMBLE( arm7_be )
689		{
690		CPU_DISASSEMBLE( arm7arm_be );
691		CPU_DISASSEMBLE( arm7thumb_be );
692
693		arm_state *arm = get_safe_token(device);
694
695		if (T_IS_SET(GET_CPSR))
696		return CPU_DISASSEMBLE_CALL(arm7thumb_be);
697		else
698		return CPU_DISASSEMBLE_CALL(arm7arm_be);
699		}
700
701
702		/**************************************************************************
703		* Generic set_info
704		**************************************************************************/
705
706		static CPU_SET_INFO( arm7 )
707		{
708		arm_state *arm = get_safe_token(device);
709
710		switch (state)
711		{
712		/* --- the following bits of info are set as 64-bit signed integers --- */
713
714		/* interrupt lines/exceptions */
715		case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: set_irq_line(arm, ARM7_IRQ_LINE, info->i); break;
716		case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: set_irq_line(arm, ARM7_FIRQ_LINE, info->i); break;
717		case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: set_irq_line(arm, ARM7_ABORT_EXCEPTION, info->i); break;
718		case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: set_irq_line(arm, ARM7_ABORT_PREFETCH_EXCEPTION, info->i); break;
719		case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: set_irq_line(arm, ARM7_UNDEFINE_EXCEPTION, info->i); break;
720
721		/* registers shared by all operating modes */
722		case CPUINFO_INT_REGISTER + ARM7_R0: ARM7REG( 0) = info->i; break;
723		case CPUINFO_INT_REGISTER + ARM7_R1: ARM7REG( 1) = info->i; break;
724		case CPUINFO_INT_REGISTER + ARM7_R2: ARM7REG( 2) = info->i; break;
725		case CPUINFO_INT_REGISTER + ARM7_R3: ARM7REG( 3) = info->i; break;
726		case CPUINFO_INT_REGISTER + ARM7_R4: ARM7REG( 4) = info->i; break;
727		case CPUINFO_INT_REGISTER + ARM7_R5: ARM7REG( 5) = info->i; break;
728		case CPUINFO_INT_REGISTER + ARM7_R6: ARM7REG( 6) = info->i; break;
729		case CPUINFO_INT_REGISTER + ARM7_R7: ARM7REG( 7) = info->i; break;
730		case CPUINFO_INT_REGISTER + ARM7_R8: ARM7REG( 8) = info->i; break;
731		case CPUINFO_INT_REGISTER + ARM7_R9: ARM7REG( 9) = info->i; break;
732		case CPUINFO_INT_REGISTER + ARM7_R10: ARM7REG(10) = info->i; break;
733		case CPUINFO_INT_REGISTER + ARM7_R11: ARM7REG(11) = info->i; break;
734		case CPUINFO_INT_REGISTER + ARM7_R12: ARM7REG(12) = info->i; break;
735		case CPUINFO_INT_REGISTER + ARM7_R13: ARM7REG(13) = info->i; break;
736		case CPUINFO_INT_REGISTER + ARM7_R14: ARM7REG(14) = info->i; break;
737		case CPUINFO_INT_REGISTER + ARM7_R15: ARM7REG(15) = info->i; break;
738		case CPUINFO_INT_REGISTER + ARM7_CPSR: SET_CPSR(info->i); break;
739
740		case CPUINFO_INT_PC:
741		case CPUINFO_INT_REGISTER + ARM7_PC: R15 = info->i; break;
742		case CPUINFO_INT_SP: SetRegister(arm, 13,info->i); break;
743
744		/* FIRQ Mode Shadowed Registers */
745		case CPUINFO_INT_REGISTER + ARM7_FR8: ARM7REG(eR8_FIQ) = info->i; break;
746		case CPUINFO_INT_REGISTER + ARM7_FR9: ARM7REG(eR9_FIQ) = info->i; break;
747		case CPUINFO_INT_REGISTER + ARM7_FR10: ARM7REG(eR10_FIQ) = info->i; break;
748		case CPUINFO_INT_REGISTER + ARM7_FR11: ARM7REG(eR11_FIQ) = info->i; break;
749		case CPUINFO_INT_REGISTER + ARM7_FR12: ARM7REG(eR12_FIQ) = info->i; break;
750		case CPUINFO_INT_REGISTER + ARM7_FR13: ARM7REG(eR13_FIQ) = info->i; break;
751		case CPUINFO_INT_REGISTER + ARM7_FR14: ARM7REG(eR14_FIQ) = info->i; break;
752		case CPUINFO_INT_REGISTER + ARM7_FSPSR: ARM7REG(eSPSR_FIQ) = info->i; break;
753
754		/* IRQ Mode Shadowed Registers */
755		case CPUINFO_INT_REGISTER + ARM7_IR13: ARM7REG(eR13_IRQ) = info->i; break;
756		case CPUINFO_INT_REGISTER + ARM7_IR14: ARM7REG(eR14_IRQ) = info->i; break;
757		case CPUINFO_INT_REGISTER + ARM7_ISPSR: ARM7REG(eSPSR_IRQ) = info->i; break;
758
759		/* Supervisor Mode Shadowed Registers */
760		case CPUINFO_INT_REGISTER + ARM7_SR13: ARM7REG(eR13_SVC) = info->i; break;
761		case CPUINFO_INT_REGISTER + ARM7_SR14: ARM7REG(eR14_SVC) = info->i; break;
762		case CPUINFO_INT_REGISTER + ARM7_SSPSR: ARM7REG(eSPSR_SVC) = info->i; break;
763
764		/* Abort Mode Shadowed Registers */
765		case CPUINFO_INT_REGISTER + ARM7_AR13: ARM7REG(eR13_ABT) = info->i; break;
766		case CPUINFO_INT_REGISTER + ARM7_AR14: ARM7REG(eR14_ABT) = info->i; break;
767		case CPUINFO_INT_REGISTER + ARM7_ASPSR: ARM7REG(eSPSR_ABT) = info->i; break;
768
769		/* Undefined Mode Shadowed Registers */
770		case CPUINFO_INT_REGISTER + ARM7_UR13: ARM7REG(eR13_UND) = info->i; break;
771		case CPUINFO_INT_REGISTER + ARM7_UR14: ARM7REG(eR14_UND) = info->i; break;
772		case CPUINFO_INT_REGISTER + ARM7_USPSR: ARM7REG(eSPSR_UND) = info->i; break;
773		}
774		}
775
776
777
778		/**************************************************************************
779		* Generic get_info
780		**************************************************************************/
781
782		CPU_GET_INFO( arm7 )
783		{
784		arm_state *arm = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
785
786		switch (state)
787		{
788		/* --- the following bits of info are returned as 64-bit signed integers --- */
789
790		/* cpu implementation data */
791		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(arm_state); break;
792		case CPUINFO_INT_INPUT_LINES: info->i = ARM7_NUM_LINES; break;
793		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
794		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
795		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
796		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
797		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
798		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
799		case CPUINFO_INT_MIN_CYCLES: info->i = 3; break;
800		case CPUINFO_INT_MAX_CYCLES: info->i = 4; break;
801
802		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
803		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
804		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
805		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
806		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
807		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
808		case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
809		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
810		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
811
812		/* interrupt lines/exceptions */
813		case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: info->i = arm->pendingIrq; break;
814		case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: info->i = arm->pendingFiq; break;
815		case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: info->i = arm->pendingAbtD; break;
816		case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: info->i = arm->pendingAbtP; break;
817		case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: info->i = arm->pendingUnd; break;
818
819		/* registers shared by all operating modes */
820		case CPUINFO_INT_REGISTER + ARM7_R0: info->i = ARM7REG( 0); break;
821		case CPUINFO_INT_REGISTER + ARM7_R1: info->i = ARM7REG( 1); break;
822		case CPUINFO_INT_REGISTER + ARM7_R2: info->i = ARM7REG( 2); break;
823		case CPUINFO_INT_REGISTER + ARM7_R3: info->i = ARM7REG( 3); break;
824		case CPUINFO_INT_REGISTER + ARM7_R4: info->i = ARM7REG( 4); break;
825		case CPUINFO_INT_REGISTER + ARM7_R5: info->i = ARM7REG( 5); break;
826		case CPUINFO_INT_REGISTER + ARM7_R6: info->i = ARM7REG( 6); break;
827		case CPUINFO_INT_REGISTER + ARM7_R7: info->i = ARM7REG( 7); break;
828		case CPUINFO_INT_REGISTER + ARM7_R8: info->i = ARM7REG( 8); break;
829		case CPUINFO_INT_REGISTER + ARM7_R9: info->i = ARM7REG( 9); break;
830		case CPUINFO_INT_REGISTER + ARM7_R10: info->i = ARM7REG(10); break;
831		case CPUINFO_INT_REGISTER + ARM7_R11: info->i = ARM7REG(11); break;
832		case CPUINFO_INT_REGISTER + ARM7_R12: info->i = ARM7REG(12); break;
833		case CPUINFO_INT_REGISTER + ARM7_R13: info->i = ARM7REG(13); break;
834		case CPUINFO_INT_REGISTER + ARM7_R14: info->i = ARM7REG(14); break;
835		case CPUINFO_INT_REGISTER + ARM7_R15: info->i = ARM7REG(15); break;
836
837		case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* not implemented */ break;
838		case CPUINFO_INT_PC:
839		case CPUINFO_INT_REGISTER + ARM7_PC: info->i = GET_PC; break;
840		case CPUINFO_INT_SP: info->i = GetRegister(arm, 13); break;
841
842		/* FIRQ Mode Shadowed Registers */
843		case CPUINFO_INT_REGISTER + ARM7_FR8: info->i = ARM7REG(eR8_FIQ); break;
844		case CPUINFO_INT_REGISTER + ARM7_FR9: info->i = ARM7REG(eR9_FIQ); break;
845		case CPUINFO_INT_REGISTER + ARM7_FR10: info->i = ARM7REG(eR10_FIQ); break;
846		case CPUINFO_INT_REGISTER + ARM7_FR11: info->i = ARM7REG(eR11_FIQ); break;
847		case CPUINFO_INT_REGISTER + ARM7_FR12: info->i = ARM7REG(eR12_FIQ); break;
848		case CPUINFO_INT_REGISTER + ARM7_FR13: info->i = ARM7REG(eR13_FIQ); break;
849		case CPUINFO_INT_REGISTER + ARM7_FR14: info->i = ARM7REG(eR14_FIQ); break;
850		case CPUINFO_INT_REGISTER + ARM7_FSPSR: info->i = ARM7REG(eSPSR_FIQ); break;
851
852		/* IRQ Mode Shadowed Registers */
853		case CPUINFO_INT_REGISTER + ARM7_IR13: info->i = ARM7REG(eR13_IRQ); break;
854		case CPUINFO_INT_REGISTER + ARM7_IR14: info->i = ARM7REG(eR14_IRQ); break;
855		case CPUINFO_INT_REGISTER + ARM7_ISPSR: info->i = ARM7REG(eSPSR_IRQ); break;
856
857		/* Supervisor Mode Shadowed Registers */
858		case CPUINFO_INT_REGISTER + ARM7_SR13: info->i = ARM7REG(eR13_SVC); break;
859		case CPUINFO_INT_REGISTER + ARM7_SR14: info->i = ARM7REG(eR14_SVC); break;
860		case CPUINFO_INT_REGISTER + ARM7_SSPSR: info->i = ARM7REG(eSPSR_SVC); break;
861
862		/* Abort Mode Shadowed Registers */
863		case CPUINFO_INT_REGISTER + ARM7_AR13: info->i = ARM7REG(eR13_ABT); break;
864		case CPUINFO_INT_REGISTER + ARM7_AR14: info->i = ARM7REG(eR14_ABT); break;
865		case CPUINFO_INT_REGISTER + ARM7_ASPSR: info->i = ARM7REG(eSPSR_ABT); break;
866
867		/* Undefined Mode Shadowed Registers */
868		case CPUINFO_INT_REGISTER + ARM7_UR13: info->i = ARM7REG(eR13_UND); break;
869		case CPUINFO_INT_REGISTER + ARM7_UR14: info->i = ARM7REG(eR14_UND); break;
870		case CPUINFO_INT_REGISTER + ARM7_USPSR: info->i = ARM7REG(eSPSR_UND); break;
871
872		/* --- the following bits of info are returned as pointers to data or functions --- */
873		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(arm7); break;
874		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(arm7); break;
875		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm7); break;
876		case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(arm7); break;
877		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(arm7); break;
878		case CPUINFO_FCT_BURN: info->burn = NULL; break;
879		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(arm7); break;
880		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &ARM7_ICOUNT; break;
881		case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(arm7); break;
882
883		/* --- the following bits of info are returned as NULL-terminated strings --- */
884		case CPUINFO_STR_NAME: strcpy(info->s, "ARM7"); break;
885		case CPUINFO_STR_FAMILY: strcpy(info->s, "Acorn Risc Machine"); break;
886		case CPUINFO_STR_VERSION: strcpy(info->s, "2.0"); break;
887		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
888		case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Steve Ellenoff, sellenoff@hotmail.com"); break;
889
890		case CPUINFO_STR_FLAGS:
891		sprintf(info->s, "%c%c%c%c%c%c%c%c %s",
892		(ARM7REG(eCPSR) & N_MASK) ? 'N' : '-',
893		(ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-',
894		(ARM7REG(eCPSR) & C_MASK) ? 'C' : '-',
895		(ARM7REG(eCPSR) & V_MASK) ? 'V' : '-',
896		(ARM7REG(eCPSR) & Q_MASK) ? 'Q' : '-',
897		(ARM7REG(eCPSR) & I_MASK) ? 'I' : '-',
898		(ARM7REG(eCPSR) & F_MASK) ? 'F' : '-',
899		(ARM7REG(eCPSR) & T_MASK) ? 'T' : '-',
900		GetModeText(ARM7REG(eCPSR)));
	776	case ARM7_ABORT_EXCEPTION:
	777	m_pendingAbtD = state & 1;
901	778	break;
	779	case ARM7_ABORT_PREFETCH_EXCEPTION:
	780	m_pendingAbtP = state & 1;
	781	break;
902	782
903		/* registers shared by all operating modes */
904		case CPUINFO_STR_REGISTER + ARM7_PC: sprintf(info->s, "PC :%08x", GET_PC); break;
905		case CPUINFO_STR_REGISTER + ARM7_R0: sprintf(info->s, "R0 :%08x", ARM7REG( 0)); break;
906		case CPUINFO_STR_REGISTER + ARM7_R1: sprintf(info->s, "R1 :%08x", ARM7REG( 1)); break;
907		case CPUINFO_STR_REGISTER + ARM7_R2: sprintf(info->s, "R2 :%08x", ARM7REG( 2)); break;
908		case CPUINFO_STR_REGISTER + ARM7_R3: sprintf(info->s, "R3 :%08x", ARM7REG( 3)); break;
909		case CPUINFO_STR_REGISTER + ARM7_R4: sprintf(info->s, "R4 :%08x", ARM7REG( 4)); break;
910		case CPUINFO_STR_REGISTER + ARM7_R5: sprintf(info->s, "R5 :%08x", ARM7REG( 5)); break;
911		case CPUINFO_STR_REGISTER + ARM7_R6: sprintf(info->s, "R6 :%08x", ARM7REG( 6)); break;
912		case CPUINFO_STR_REGISTER + ARM7_R7: sprintf(info->s, "R7 :%08x", ARM7REG( 7)); break;
913		case CPUINFO_STR_REGISTER + ARM7_R8: sprintf(info->s, "R8 :%08x", ARM7REG( 8)); break;
914		case CPUINFO_STR_REGISTER + ARM7_R9: sprintf(info->s, "R9 :%08x", ARM7REG( 9)); break;
915		case CPUINFO_STR_REGISTER + ARM7_R10: sprintf(info->s, "R10 :%08x", ARM7REG(10)); break;
916		case CPUINFO_STR_REGISTER + ARM7_R11: sprintf(info->s, "R11 :%08x", ARM7REG(11)); break;
917		case CPUINFO_STR_REGISTER + ARM7_R12: sprintf(info->s, "R12 :%08x", ARM7REG(12)); break;
918		case CPUINFO_STR_REGISTER + ARM7_R13: sprintf(info->s, "R13 :%08x", ARM7REG(13)); break;
919		case CPUINFO_STR_REGISTER + ARM7_R14: sprintf(info->s, "R14 :%08x", ARM7REG(14)); break;
920		case CPUINFO_STR_REGISTER + ARM7_R15: sprintf(info->s, "R15 :%08x", ARM7REG(15)); break;
921
922		/* FIRQ Mode Shadowed Registers */
923		case CPUINFO_STR_REGISTER + ARM7_FR8: sprintf(info->s, "FR8 :%08x", ARM7REG(eR8_FIQ) ); break;
924		case CPUINFO_STR_REGISTER + ARM7_FR9: sprintf(info->s, "FR9 :%08x", ARM7REG(eR9_FIQ) ); break;
925		case CPUINFO_STR_REGISTER + ARM7_FR10: sprintf(info->s, "FR10:%08x", ARM7REG(eR10_FIQ) ); break;
926		case CPUINFO_STR_REGISTER + ARM7_FR11: sprintf(info->s, "FR11:%08x", ARM7REG(eR11_FIQ) ); break;
927		case CPUINFO_STR_REGISTER + ARM7_FR12: sprintf(info->s, "FR12:%08x", ARM7REG(eR12_FIQ) ); break;
928		case CPUINFO_STR_REGISTER + ARM7_FR13: sprintf(info->s, "FR13:%08x", ARM7REG(eR13_FIQ) ); break;
929		case CPUINFO_STR_REGISTER + ARM7_FR14: sprintf(info->s, "FR14:%08x", ARM7REG(eR14_FIQ) ); break;
930		case CPUINFO_STR_REGISTER + ARM7_FSPSR: sprintf(info->s, "FR16:%08x", ARM7REG(eSPSR_FIQ)); break;
931
932		/* IRQ Mode Shadowed Registers */
933		case CPUINFO_STR_REGISTER + ARM7_IR13: sprintf(info->s, "IR13:%08x", ARM7REG(eR13_IRQ) ); break;
934		case CPUINFO_STR_REGISTER + ARM7_IR14: sprintf(info->s, "IR14:%08x", ARM7REG(eR14_IRQ) ); break;
935		case CPUINFO_STR_REGISTER + ARM7_ISPSR: sprintf(info->s, "IR16:%08x", ARM7REG(eSPSR_IRQ)); break;
936
937		/* Supervisor Mode Shadowed Registers */
938		case CPUINFO_STR_REGISTER + ARM7_SR13: sprintf(info->s, "SR13:%08x", ARM7REG(eR13_SVC) ); break;
939		case CPUINFO_STR_REGISTER + ARM7_SR14: sprintf(info->s, "SR14:%08x", ARM7REG(eR14_SVC) ); break;
940		case CPUINFO_STR_REGISTER + ARM7_SSPSR: sprintf(info->s, "SR16:%08x", ARM7REG(eSPSR_SVC)); break;
941
942		/* Abort Mode Shadowed Registers */
943		case CPUINFO_STR_REGISTER + ARM7_AR13: sprintf(info->s, "AR13:%08x", ARM7REG(eR13_ABT) ); break;
944		case CPUINFO_STR_REGISTER + ARM7_AR14: sprintf(info->s, "AR14:%08x", ARM7REG(eR14_ABT) ); break;
945		case CPUINFO_STR_REGISTER + ARM7_ASPSR: sprintf(info->s, "AR16:%08x", ARM7REG(eSPSR_ABT)); break;
946
947		/* Undefined Mode Shadowed Registers */
948		case CPUINFO_STR_REGISTER + ARM7_UR13: sprintf(info->s, "UR13:%08x", ARM7REG(eR13_UND) ); break;
949		case CPUINFO_STR_REGISTER + ARM7_UR14: sprintf(info->s, "UR14:%08x", ARM7REG(eR14_UND) ); break;
950		case CPUINFO_STR_REGISTER + ARM7_USPSR: sprintf(info->s, "UR16:%08x", ARM7REG(eSPSR_UND)); break;
	783	case ARM7_UNDEFINE_EXCEPTION:
	784	m_pendingUnd = state & 1;
	785	break;
951	786	}
952		}
953	787
954
955		CPU_GET_INFO( arm7_be )
956		{
957		switch (state)
958		{
959		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
960		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm7_be); break;
961		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(arm7_be); break;
962		case CPUINFO_STR_NAME: strcpy(info->s, "ARM7 (big endian)"); break;
963		default: CPU_GET_INFO_CALL(arm7);
964		}
	788	arm7_check_irq_state();
965	789	}
966	790
967		CPU_GET_INFO( arm7500 )
968		{
969		switch (state)
970		{
971		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm7500); break;
972		case CPUINFO_STR_NAME: strcpy(info->s, "ARM7500"); break;
973		default: CPU_GET_INFO_CALL(arm7);
974		break;
975		}
976		}
977	791
978		~~CPU~~_~~GET~~_IN~~FO(~~ arm9 )
	792	offs_t arm7_cpu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
979	793	{
980		switch (state)
981		{
982		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm9); break;
983		case CPUINFO_STR_NAME: strcpy(info->s, "ARM9"); break;
984		default: CPU_GET_INFO_CALL(arm7);
985		break;
986		}
987		}
	794	extern CPU_DISASSEMBLE( arm7arm );
	795	extern CPU_DISASSEMBLE( arm7thumb );
	796	extern CPU_DISASSEMBLE( arm7arm_be );
	797	extern CPU_DISASSEMBLE( arm7thumb_be );
988	798
989		CPU_GET_INFO( arm920t )
990		{
991		switch (state)
	799	if (T_IS_SET(m_r[eCPSR]))
992	800	{
993		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(arm920t); break;
994		case CPUINFO_STR_NAME: strcpy(info->s, "ARM920T"); break;
995		default: CPU_GET_INFO_CALL(arm7);
996		break;
	801	if ( m_endian == ENDIANNESS_BIG )
	802	return CPU_DISASSEMBLE_NAME(arm7thumb_be)(this, buffer, pc, oprom, opram, options);
	803	else
	804	return CPU_DISASSEMBLE_NAME(arm7thumb)(this, buffer, pc, oprom, opram, options);
997	805	}
998		}
999
1000		CPU_GET_INFO( pxa255 )
1001		{
1002		switch (state)
	806	else
1003	807	{
1004		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(pxa255); break;
1005		case CPUINFO_STR_NAME: strcpy(info->s, "PXA255"); break;
1006		default: CPU_GET_INFO_CALL(arm7);
1007		break;
	808	if ( m_endian == ENDIANNESS_BIG )
	809	return CPU_DISASSEMBLE_NAME(arm7arm_be)(this, buffer, pc, oprom, opram, options);
	810	else
	811	return CPU_DISASSEMBLE_NAME(arm7arm)(this, buffer, pc, oprom, opram, options);
1008	812	}
1009	813	}
1010	814
1011		CPU_GET_INFO( sa1110 )
1012		{
1013		switch (state)
1014		{
1015		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sa1110); break;
1016		case CPUINFO_STR_NAME: strcpy(info->s, "SA1110"); break;
1017		default: CPU_GET_INFO_CALL(arm7);
1018		break;
1019		}
1020		}
1021	815
1022	816	/* ARM system coprocessor support */
1023	817
1024		~~static~~ WRITE32_DE~~VIC~~E~~_HANDLE~~R( arm7_do_callback )
	818	WRITE32_MEMBER( arm7_cpu_device::arm7_do_callback )
1025	819	{
1026		arm_state *arm = get_safe_token(device);
1027		arm->pendingUnd = 1;
	820	m_pendingUnd = 1;
1028	821	}
1029	822
1030		~~static~~ READ32_DE~~VIC~~E~~_HANDLE~~R( arm7_rt_r_callback )
	823	READ32_MEMBER( arm7_cpu_device::arm7_rt_r_callback )
1031	824	{
1032		arm_state *arm = get_safe_token(device);
1033	825	UINT32 opcode = offset;
1034	826	UINT8 cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
1035	827	UINT8 op2 = ( opcode & INSN_COPRO_OP2 ) >> INSN_COPRO_OP2_SHIFT;
r24074	r24075
1042	834	// we only handle system copro here
1043	835	if (cpnum != 15)
1044	836	{
1045		if (arm->archFlags & eARM_ARCHFLAGS_XSCALE)
	837	if (m_archFlags & eARM_ARCHFLAGS_XSCALE)
1046	838	{
1047	839	// handle XScale specific CP14
1048	840	if (cpnum == 14)
r24074	r24075
1050	842	switch( cReg )
1051	843	{
1052	844	case 1: // clock counter
1053		data = (UINT32)~~arm->device->~~total_cycles();
	845	data = (UINT32)total_cycles();
1054	846	break;
1055	847
1056	848	default:
r24074	r24075
1059	851	}
1060	852	else
1061	853	{
1062		fatalerror("XScale: Unhandled coprocessor %d (archFlags %x)\n", cpnum, arm->archFlags);
	854	fatalerror("XScale: Unhandled coprocessor %d (archFlags %x)\n", cpnum, m_archFlags);
1063	855	}
1064	856
1065	857	return data;
1066	858	}
1067	859	else
1068	860	{
1069		LOG( ("ARM7: Unhandled coprocessor %d (archFlags %x)\n", cpnum, arm->archFlags) );
1070		arm->pendingUnd = 1;
	861	LOG( ("ARM7: Unhandled coprocessor %d (archFlags %x)\n", cpnum, m_archFlags) );
	862	m_pendingUnd = 1;
1071	863	return 0;
1072	864	}
1073	865	}
r24074	r24075
1088	880	switch(op2)
1089	881	{
1090	882	case 0:
1091		switch (arm->archRev)
	883	switch (m_archRev)
1092	884	{
1093	885	case 3: // ARM6 32-bit
1094	886	data = 0x41;
1095	887	break;
1096	888
1097		case 4: // ARM7/SA11xx
1098		if (arm->archFlags & eARM_ARCHFLAGS_SA)
1099		{
1100		// ARM Architecture Version 4
1101		// Part Number 0xB11 (SA1110)
1102		// Stepping B5
1103		data = 0x69 \| ( 0x01 << 16 ) \| ( 0xB11 << 4 ) \| 0x9;
1104		}
1105		else
1106		{
1107		if (device->type() == ARM920T)
	889	case 4: // ARM7/SA11xx
	890	if (m_archFlags & eARM_ARCHFLAGS_SA)
1108	891	{
1109		data = (0x41 << 24) \| (1 << 20) \| (2 << 16) \| (0x920 << 4) \| (0 << 0); // ARM920T (S3C24xx)
	892	// ARM Architecture Version 4
	893	// Part Number 0xB11 (SA1110)
	894	// Stepping B5
	895	data = 0x69 \| ( 0x01 << 16 ) \| ( 0xB11 << 4 ) \| 0x9;
1110	896	}
1111		else if (device->type() == ARM7500)
1112		{
1113		data = (0x41 << 24) \| (0 << 20) \| (1 << 16) \| (0x710 << 4) \| (0 << 0); // ARM7500
1114		}
1115	897	else
1116	898	{
1117		data = ~~0x41 \| (1 << 23) \| (7 << 12); // <-- where did this~~ co~~me f~~rom?
	899	data = m_copro_id;
1118	900	}
1119		}
1120		break;
	901	break;
1121	902
1122		case 5: // ARM9/10/XScale
1123		data = 0x41 \| (9 << 12);
1124		if (arm->archFlags & eARM_ARCHFLAGS_T)
1125		{
1126		if (arm->archFlags & eARM_ARCHFLAGS_E)
	903	case 5: // ARM9/10/XScale
	904	data = 0x41 \| (9 << 12);
	905	if (m_archFlags & eARM_ARCHFLAGS_T)
1127	906	{
1128		if (arm->archFlags & eARM_ARCHFLAGS_J)
	907	if (m_archFlags & eARM_ARCHFLAGS_E)
1129	908	{
1130		data \|= (6<<16); // v5TEJ
	909	if (m_archFlags & eARM_ARCHFLAGS_J)
	910	{
	911	data \|= (6<<16); // v5TEJ
	912	}
	913	else
	914	{
	915	data \|= (5<<16); // v5TE
	916	}
1131	917	}
1132	918	else
1133	919	{
1134		data \|= (5<<16); // v5TE
	920	data \|= (4<<16); // v5T
1135	921	}
1136	922	}
1137		else
1138		{
1139		data \|= (4<<16); // v5T
1140		}
1141		}
1142		break;
	923	break;
1143	924
1144		case 6: // ARM11
1145		data = 0x41 \| (10<< 12) \| (7<<16); // v6
1146		break;
	925	case 6: // ARM11
	926	data = 0x41 \| (10<< 12) \| (7<<16); // v6
	927	break;
1147	928	}
1148	929	break;
1149		case 1: // cache type
	930	case 1: // cache type
1150	931	data = 0x0f0d2112; // HACK: value expected by ARMWrestler (probably Nintendo DS ARM9's value)
1151	932	//data = (6 << 25) \| (1 << 24) \| (0x172 << 12) \| (0x172 << 0); // ARM920T (S3C24xx)
1152	933	break;
r24074	r24075
1199	980	return data;
1200	981	}
1201	982
1202		~~static~~ WRITE32_DE~~VIC~~E~~_HANDLE~~R( arm7_rt_w_callback )
	983	WRITE32_MEMBER( arm7_cpu_device::arm7_rt_w_callback )
1203	984	{
1204		arm_state *arm = get_safe_token(device);
1205	985	UINT32 opcode = offset;
1206	986	UINT8 cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
1207	987	UINT8 op2 = ( opcode & INSN_COPRO_OP2 ) >> INSN_COPRO_OP2_SHIFT;
r24074	r24075
1219	999	else
1220	1000	{
1221	1001	LOG( ("ARM7: Unhandled coprocessor %d\n", cpnum) );
1222		arm->pendingUnd = 1;
	1002	m_pendingUnd = 1;
1223	1003	return;
1224	1004	}
1225	1005	}
r24074	r24075
1249	1029	#if ARM7_MMU_ENABLE_HACK
1250	1030	if (((data & COPRO_CTRL_MMU_EN) != 0) && ((COPRO_CTRL & COPRO_CTRL_MMU_EN) == 0))
1251	1031	{
1252		~~arm-~~>mmu_enable_addr = R15;
	1032	>m_mmu_enable_addr = R15;
1253	1033	}
1254	1034	if (((data & COPRO_CTRL_MMU_EN) == 0) && ((COPRO_CTRL & COPRO_CTRL_MMU_EN) != 0))
1255	1035	{
1256		if (!arm7_tlb_translate( ~~arm, &~~R15, 0))
	1036	if (!arm7_tlb_translate( R15, 0))
1257	1037	{
1258	1038	fatalerror("ARM7_MMU_ENABLE_HACK translate failed\n");
1259	1039	}
r24074	r24075
1303	1083	}
1304	1084	}
1305	1085
1306		void arm7_dt_r_callback(arm_state arm, UINT32 insn, UINT32 prn, UINT32 (read32)(arm_state arm, UINT32 addr))
	1086
	1087	void arm7_cpu_device::arm7_dt_r_callback(UINT32 insn, UINT32 *prn)
1307	1088	{
1308	1089	UINT8 cpn = (insn >> 8) & 0xF;
1309		if ((arm->archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
	1090	if ((m_archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
1310	1091	{
1311	1092	LOG( ( "arm7_dt_r_callback: DSP Coprocessor 0 (CP0) not yet emulated (PC %08x)\n", GET_PC ) );
1312	1093	}
1313	1094	else
1314	1095	{
1315		arm->pendingUnd = 1;
	1096	m_pendingUnd = 1;
1316	1097	}
1317	1098	}
1318	1099
1319		void arm7_dt_w_callback(arm_state arm, UINT32 insn, UINT32 prn, void (write32)(arm_state arm, UINT32 addr, UINT32 data))
	1100
	1101	void arm7_cpu_device::arm7_dt_w_callback(UINT32 insn, UINT32 *prn)
1320	1102	{
1321	1103	UINT8 cpn = (insn >> 8) & 0xF;
1322		if ((arm->archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
	1104	if ((m_archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
1323	1105	{
1324	1106	LOG( ( "arm7_dt_w_callback: DSP Coprocessor 0 (CP0) not yet emulated (PC %08x)\n", GET_PC ) );
1325	1107	}
1326	1108	else
1327	1109	{
1328		arm->pendingUnd = 1;
	1110	m_pendingUnd = 1;
1329	1111	}
1330	1112	}
1331	1113
1332		DEFINE_LEGACY_CPU_DEVICE(ARM7, arm7);
1333		DEFINE_LEGACY_CPU_DEVICE(ARM7_BE, arm7_be);
1334		DEFINE_LEGACY_CPU_DEVICE(ARM7500, arm7500);
1335		DEFINE_LEGACY_CPU_DEVICE(ARM9, arm9);
1336		DEFINE_LEGACY_CPU_DEVICE(ARM920T, arm920t);
1337		DEFINE_LEGACY_CPU_DEVICE(PXA255, pxa255);
1338		DEFINE_LEGACY_CPU_DEVICE(SA1110, sa1110);
	1114
	1115	/***************************************************************************
	1116	* Default Memory Handlers
	1117	***************************************************************************/
	1118	void arm7_cpu_device::arm7_cpu_write32(UINT32 addr, UINT32 data)
	1119	{
	1120	if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
	1121	{
	1122	if (!arm7_tlb_translate( addr, ARM7_TLB_ABORT_D \| ARM7_TLB_WRITE ))
	1123	{
	1124	return;
	1125	}
	1126	}
	1127
	1128	addr &= ~3;
	1129	m_program->write_dword(addr, data);
	1130	}
	1131
	1132
	1133	void arm7_cpu_device::arm7_cpu_write16(UINT32 addr, UINT16 data)
	1134	{
	1135	if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
	1136	{
	1137	if (!arm7_tlb_translate( addr, ARM7_TLB_ABORT_D \| ARM7_TLB_WRITE ))
	1138	{
	1139	return;
	1140	}
	1141	}
	1142
	1143	addr &= ~1;
	1144	m_program->write_word(addr, data);
	1145	}
	1146
	1147	void arm7_cpu_device::arm7_cpu_write8(UINT32 addr, UINT8 data)
	1148	{
	1149	if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
	1150	{
	1151	if (!arm7_tlb_translate( addr, ARM7_TLB_ABORT_D \| ARM7_TLB_WRITE ))
	1152	{
	1153	return;
	1154	}
	1155	}
	1156
	1157	m_program->write_byte(addr, data);
	1158	}
	1159
	1160	UINT32 arm7_cpu_device::arm7_cpu_read32(UINT32 addr)
	1161	{
	1162	UINT32 result;
	1163
	1164	if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
	1165	{
	1166	if (!arm7_tlb_translate( addr, ARM7_TLB_ABORT_D \| ARM7_TLB_READ ))
	1167	{
	1168	return 0;
	1169	}
	1170	}
	1171
	1172	if (addr & 3)
	1173	{
	1174	result = m_program->read_dword(addr & ~3);
	1175	result = (result >> (8 * (addr & 3))) \| (result << (32 - (8 * (addr & 3))));
	1176	}
	1177	else
	1178	{
	1179	result = m_program->read_dword(addr);
	1180	}
	1181
	1182	return result;
	1183	}
	1184
	1185	UINT16 arm7_cpu_device::arm7_cpu_read16(UINT32 addr)
	1186	{
	1187	UINT16 result;
	1188
	1189	if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
	1190	{
	1191	if (!arm7_tlb_translate( addr, ARM7_TLB_ABORT_D \| ARM7_TLB_READ ))
	1192	{
	1193	return 0;
	1194	}
	1195	}
	1196
	1197	result = m_program->read_word(addr & ~1);
	1198
	1199	if (addr & 1)
	1200	{
	1201	result = ((result >> 8) & 0xff) \| ((result & 0xff) << 8);
	1202	}
	1203
	1204	return result;
	1205	}
	1206
	1207	UINT8 arm7_cpu_device::arm7_cpu_read8(UINT32 addr)
	1208	{
	1209	if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
	1210	{
	1211	if (!arm7_tlb_translate( addr, ARM7_TLB_ABORT_D \| ARM7_TLB_READ ))
	1212	{
	1213	return 0;
	1214	}
	1215	}
	1216
	1217	// Handle through normal 8 bit handler (for 32 bit cpu)
	1218	return m_program->read_byte(addr);
	1219	}
	1220
	1221	#include "arm7drc.c"
	1222

trunk/src/emu/cpu/arm7/arm7ops.c
r24074	r24075
1	1	#include "emu.h"
	2	#include "arm7.h"
2	3	#include "arm7core.h"
3		#include "arm7ops.h"
4	4	#include "arm7help.h"
5	5
6		IN~~LINE IN~~T64 saturate_qbit_overflow(~~arm_state *arm,~~ INT64 res)
	6	INT64 arm7_cpu_device::saturate_qbit_overflow(INT64 res)
7	7	{
8	8	if (res > 2147483647) // INT32_MAX
9	9	{ // overflow high? saturate and set Q
r24074	r24075
19	19	return res;
20	20	}
21	21
22		// I could prob. convert to macro, but Switchmode shouldn't occur that often in emulated code..
23		void SwitchMode(arm_state *arm, int cpsr_mode_val)
	22
	23	void arm7_cpu_device::SwitchMode(UINT32 cpsr_mode_val)
24	24	{
25		UINT32 cspr = GET_CPSR & ~MODE_FLAG;
26		SET_CPSR(cspr \| cpsr_mode_val);
	25	UINT32 cspr = m_r[eCPSR] & ~MODE_FLAG;
	26	set_cpsr(cspr \| cpsr_mode_val);
27	27	}
28	28
29	29
r24074	r24075
45	45	ROR >32 = Same result as ROR n-32 until amount in range of 1-32 then follow rules
46	46	*/
47	47
48		UINT32 decodeShift(~~arm_state arm,~~ UINT32 insn, UINT32 pCarry)
	48	UINT32 arm7_cpu_device::decodeShift(UINT32 insn, UINT32 *pCarry)
49	49	{
50	50	UINT32 k = (insn & INSN_OP2_SHIFT) >> INSN_OP2_SHIFT_SHIFT; // Bits 11-7
51		UINT32 rm = GET_REGISTER(~~arm,~~ insn & INSN_OP2_RM);
	51	UINT32 rm = GET_REGISTER(insn & INSN_OP2_RM);
52	52	UINT32 t = (insn & INSN_OP2_SHIFT_TYPE) >> INSN_OP2_SHIFT_TYPE_SHIFT;
53	53
54	54	if ((insn & INSN_OP2_RM) == 0xf) {
r24074	r24075
59	59	/* All shift types ending in 1 are Rk, not #k */
60	60	if (t & 1)
61	61	{
62		// LOG(("%08x: RegShift %02x %02x\n", R15, k >> 1, GET_REGISTER(~~arm,~~ k >> 1)));
	62	// LOG(("%08x: RegShift %02x %02x\n", R15, k >> 1, GET_REGISTER(k >> 1)));
63	63	#if ARM7_DEBUG_CORE
64	64	if ((insn & 0x80) == 0x80)
65	65	LOG(("%08x: RegShift ERROR (p36)\n", R15));
66	66	#endif
67	67
68	68	// see p35 for check on this
69		//k = GET_REGISTER(~~arm,~~ k >> 1) & 0x1f;
	69	//k = GET_REGISTER(k >> 1) & 0x1f;
70	70
71	71	// Keep only the bottom 8 bits for a Register Shift
72		k = GET_REGISTER(~~arm,~~ k >> 1) & 0xff;
	72	k = GET_REGISTER(k >> 1) & 0xff;
73	73
74	74	if (k == 0) /* Register shift by 0 is a no-op */
75	75	{
r24074	r24075
167	167	} /* decodeShift */
168	168
169	169
170		~~stat~~i~~c i~~nt loadInc(~~arm_state *arm,~~ UINT32 pat, UINT32 rbv, UINT32 s, int mode)
	170	int arm7_cpu_device::loadInc(UINT32 pat, UINT32 rbv, UINT32 s, int mode)
171	171	{
172	172	int i, result;
173	173	UINT32 data;
r24074	r24075
178	178	{
179	179	if ((pat >> i) & 1)
180	180	{
181		if (arm->pendingAbtD == 0) // "Overwriting of registers stops when the abort happens."
	181	if (m_pendingAbtD == 0) // "Overwriting of registers stops when the abort happens."
182	182	{
183	183	data = READ32(rbv += 4);
184	184	if (i == 15) {
185	185	if (s) /* Pull full contents from stack */
186		SET_MODE_REGISTER(~~arm,~~ mode, 15, data);
	186	SET_MODE_REGISTER(mode, 15, data);
187	187	else /* Pull only address, preserve mode & status flags */
188	188	if (MODE32)
189		SET_MODE_REGISTER(~~arm,~~ mode, 15, data);
	189	SET_MODE_REGISTER(mode, 15, data);
190	190	else
191	191	{
192		SET_MODE_REGISTER(arm~~, m~~ode, 15, (GET_MODE_REGISTER(~~arm,~~ mode, 15) & ~0x03FFFFFC) \| (data & 0x03FFFFFC));
	192	SET_MODE_REGISTER(mode, 15, (GET_MODE_REGISTER(mode, 15) & ~0x03FFFFFC) \| (data & 0x03FFFFFC));
193	193	}
194	194	} else
195		SET_MODE_REGISTER(~~arm,~~ mode, i, data);
	195	SET_MODE_REGISTER(mode, i, data);
196	196	}
197	197	result++;
198	198	}
r24074	r24075
200	200	return result;
201	201	}
202	202
203		static int loadDec(arm_state *arm, UINT32 pat, UINT32 rbv, UINT32 s, int mode)
	203
	204	int arm7_cpu_device::loadDec(UINT32 pat, UINT32 rbv, UINT32 s, int mode)
204	205	{
205	206	int i, result;
206	207	UINT32 data;
r24074	r24075
211	212	{
212	213	if ((pat >> i) & 1)
213	214	{
214		if (arm->pendingAbtD == 0) // "Overwriting of registers stops when the abort happens."
	215	if (m_pendingAbtD == 0) // "Overwriting of registers stops when the abort happens."
215	216	{
216	217	data = READ32(rbv -= 4);
217	218	if (i == 15) {
218	219	if (s) /* Pull full contents from stack */
219		SET_MODE_REGISTER(~~arm,~~ mode, 15, data);
	220	SET_MODE_REGISTER(mode, 15, data);
220	221	else /* Pull only address, preserve mode & status flags */
221	222	if (MODE32)
222		SET_MODE_REGISTER(~~arm,~~ mode, 15, data);
	223	SET_MODE_REGISTER(mode, 15, data);
223	224	else
224	225	{
225		SET_MODE_REGISTER(arm~~, m~~ode, 15, (GET_MODE_REGISTER(~~arm,~~ mode, 15) & ~0x03FFFFFC) \| (data & 0x03FFFFFC));
	226	SET_MODE_REGISTER(mode, 15, (GET_MODE_REGISTER(mode, 15) & ~0x03FFFFFC) \| (data & 0x03FFFFFC));
226	227	}
227	228	}
228	229	else
229		SET_MODE_REGISTER(~~arm,~~ mode, i, data);
	230	SET_MODE_REGISTER(mode, i, data);
230	231	}
231	232	result++;
232	233	}
r24074	r24075
234	235	return result;
235	236	}
236	237
237		static int storeInc(arm_state *arm, UINT32 pat, UINT32 rbv, int mode)
	238
	239	int arm7_cpu_device::storeInc(UINT32 pat, UINT32 rbv, int mode)
238	240	{
239	241	int i, result;
240	242
r24074	r24075
247	249	if (i == 15) /* R15 is plus 12 from address of STM */
248	250	LOG(("%08x: StoreInc on R15\n", R15));
249	251	#endif
250		WRITE32(rbv += 4, GET_MODE_REGISTER(~~arm,~~ mode, i));
	252	WRITE32(rbv += 4, GET_MODE_REGISTER(mode, i));
251	253	result++;
252	254	}
253	255	}
254	256	return result;
255	257	} /* storeInc */
256	258
257		static int storeDec(arm_state *arm, UINT32 pat, UINT32 rbv, int mode)
	259
	260	int arm7_cpu_device::storeDec(UINT32 pat, UINT32 rbv, int mode)
258	261	{
259	262	int i, result;
260	263
r24074	r24075
267	270	if (i == 15) /* R15 is plus 12 from address of STM */
268	271	LOG(("%08x: StoreDec on R15\n", R15));
269	272	#endif
270		WRITE32(rbv -= 4, GET_MODE_REGISTER(~~arm,~~ mode, i));
	273	WRITE32(rbv -= 4, GET_MODE_REGISTER(mode, i));
271	274	result++;
272	275	}
273	276	}
274	277	return result;
275	278	} /* storeDec */
276	279
	280
277	281	/***************************************************************************
278	282	* OPCODE HANDLING
279	283	***************************************************************************/
280	284
281	285	// Co-Processor Data Operation
282		~~static~~ void HandleCoProcDO(~~arm_state *arm,~~ UINT32 insn)
	286	void arm7_cpu_device::HandleCoProcDO(UINT32 insn)
283	287	{
284	288	// This instruction simply instructs the co-processor to do something, no data is returned to ARM7 core
285		if (arm7_coproc_do_callback)
286		arm7_coproc_do_callback(arm->device, *arm->program, insn, 0, 0); // simply pass entire opcode to callback - since data format is actually dependent on co-proc implementation
287		else
288		LOG(("%08x: Co-Processor Data Operation executed, but no callback defined!\n", R15));
	289	arm7_do_callback(*m_program, insn, 0, 0); // simply pass entire opcode to callback - since data format is actually dependent on co-proc implementation
289	290	}
290	291
291	292	// Co-Processor Register Transfer - To/From Arm to Co-Proc
292		~~static~~ void HandleCoProcRT(~~arm_state *arm,~~ UINT32 insn)
	293	void arm7_cpu_device::HandleCoProcRT(UINT32 insn)
293	294	{
294	295	/* xxxx 1110 oooL nnnn dddd cccc ppp1 mmmm */
295	296
296	297	// Load (MRC) data from Co-Proc to ARM7 register
297	298	if (insn & 0x00100000) // Bit 20 = Load or Store
298	299	{
299		if (arm7_coproc_rt_r_callback)
	300	UINT32 res = arm7_rt_r_callback(*m_program, insn, 0); // RT Read handler must parse opcode & return appropriate result
	301	if (m_pendingUnd == 0)
300	302	{
301		UINT32 res = arm7_coproc_rt_r_callback(arm->device, *arm->program, insn, 0); // RT Read handler must parse opcode & return appropriate result
302		if (arm->pendingUnd == 0)
303		{
304		SET_REGISTER(arm, (insn >> 12) & 0xf, res);
305		}
	303	SET_REGISTER((insn >> 12) & 0xf, res);
306	304	}
307		else
308		LOG(("%08x: Co-Processor Register Transfer executed, but no RT Read callback defined!\n", R15));
309	305	}
310	306	// Store (MCR) data from ARM7 to Co-Proc register
311	307	else
312	308	{
313		if (arm7_coproc_rt_w_callback)
314		arm7_coproc_rt_w_callback(arm->device, *arm->program, insn, GET_REGISTER(arm, (insn >> 12) & 0xf), 0);
315		else
316		LOG(("%08x: Co-Processor Register Transfer executed, but no RT Write callback defined!\n", R15));
	309	arm7_rt_w_callback(*m_program, insn, GET_REGISTER((insn >> 12) & 0xf), 0);
317	310	}
318	311	}
319	312
r24074	r24075
329	322	but if co-proc reads multiple address, it must handle the offset adjustment itself.
330	323	*/
331	324	// todo: test with valid instructions
332		~~static~~ void HandleCoProcDT(~~arm_state *arm,~~ UINT32 insn)
	325	void arm7_cpu_device::HandleCoProcDT(UINT32 insn)
333	326	{
334	327	UINT32 rn = (insn >> 16) & 0xf;
335		UINT32 rnv = GET_REGISTER(~~arm,~~ rn); // Get Address Value stored from Rn
	328	UINT32 rnv = GET_REGISTER(rn); // Get Address Value stored from Rn
336	329	UINT32 ornv = rnv; // Keep value of Rn
337	330	UINT32 off = (insn & 0xff) << 2; // Offset is << 2 according to manual
338	331	UINT32 *prn = &ARM7REG(rn); // Pointer to our register, so it can be changed in the callback
339	332
340		// Pointers to read32/write32 functions
341		void (write32)(arm_state arm, UINT32 addr, UINT32 data);
342		UINT32 (read32)(arm_state arm, UINT32 addr);
343		write32 = PTR_WRITE32;
344		read32 = PTR_READ32;
345
346	333	#if ARM7_DEBUG_CORE
347	334	if (((insn >> 16) & 0xf) == 15 && (insn & 0x200000))
348	335	LOG(("%08x: Illegal use of R15 as base for write back value!\n", R15));
r24074	r24075
361	348	// Load (LDC) data from ARM7 memory to Co-Proc memory
362	349	if (insn & 0x00100000)
363	350	{
364		if (arm7_coproc_dt_r_callback)
365		arm7_coproc_dt_r_callback(arm, insn, prn, read32);
366		else
367		LOG(("%08x: Co-Processer Data Transfer executed, but no READ callback defined!\n", R15));
	351	arm7_dt_r_callback(insn, prn);
368	352	}
369	353	// Store (STC) data from Co-Proc to ARM7 memory
370	354	else
371	355	{
372		if (arm7_coproc_dt_w_callback)
373		arm7_coproc_dt_w_callback(arm, insn, prn, write32);
374		else
375		LOG(("%08x: Co-Processer Data Transfer executed, but no WRITE callback defined!\n", R15));
	356	arm7_dt_w_callback(insn, prn);
376	357	}
377	358
378		if (arm->pendingUnd != 0) return;
	359	if (m_pendingUnd != 0) return;
379	360
380	361	// If writeback not used - ensure the original value of RN is restored in case co-proc callback changed value
381	362	if ((insn & 0x200000) == 0)
382		SET_REGISTER(~~arm,~~ rn, ornv);
	363	SET_REGISTER(rn, ornv);
383	364	}
384	365
385		~~INLINE~~ void HandleBranch(~~arm_state *arm,~~ UINT32 insn)
	366	void arm7_cpu_device::HandleBranch(UINT32 insn)
386	367	{
387	368	UINT32 off = (insn & INSN_BRANCH) << 2;
388	369
389	370	/* Save PC into LR if this is a branch with link */
390	371	if (insn & INSN_BL)
391	372	{
392		SET_REGISTER(~~arm,~~ 14, R15 + 4);
	373	SET_REGISTER(14, R15 + 4);
393	374	}
394	375
395	376	/* Sign-extend the 24-bit offset in our calculations */
r24074	r24075
409	390	}
410	391	}
411	392
412		~~static~~ void HandleMemSingle(~~arm_state *arm,~~ UINT32 insn)
	393	void arm7_cpu_device::HandleMemSingle(UINT32 insn)
413	394	{
414	395	UINT32 rn, rnv, off, rd, rnv_old = 0;
415	396
r24074	r24075
417	398	if (insn & INSN_I)
418	399	{
419	400	/* Register Shift */
420		off = decodeShift(~~arm,~~ insn, NULL);
	401	off = decodeShift(insn, NULL);
421	402	}
422	403	else
423	404	{
r24074	r24075
434	415	if (insn & INSN_SDT_U)
435	416	{
436	417	if ((MODE32) \|\| (rn != eR15))
437		rnv = (GET_REGISTER(~~arm,~~ rn) + off);
	418	rnv = (GET_REGISTER(rn) + off);
438	419	else
439	420	rnv = (GET_PC + off);
440	421	}
441	422	else
442	423	{
443	424	if ((MODE32) \|\| (rn != eR15))
444		rnv = (GET_REGISTER(~~arm,~~ rn) - off);
	425	rnv = (GET_REGISTER(rn) - off);
445	426	else
446	427	rnv = (GET_PC - off);
447	428	}
448	429
449	430	if (insn & INSN_SDT_W)
450	431	{
451		rnv_old = GET_REGISTER(arm, rn);
452		SET_REGISTER(arm, rn, rnv);
	432	rnv_old = GET_REGISTER(rn);
	433	SET_REGISTER(rn, rnv);
453	434
454	435	// check writeback???
455	436	}
r24074	r24075
470	451	}
471	452	else
472	453	{
473		rnv = GET_REGISTER(~~arm,~~ rn);
	454	rnv = GET_REGISTER(rn);
474	455	}
475	456	}
476	457
r24074	r24075
482	463	if (insn & INSN_SDT_B)
483	464	{
484	465	UINT32 data = READ8(rnv);
485		if (arm->pendingAbtD == 0)
	466	if (m_pendingAbtD == 0)
486	467	{
487		SET_REGISTER(~~arm,~~ rd, data);
	468	SET_REGISTER(rd, data);
488	469	}
489	470	}
490	471	else
491	472	{
492	473	UINT32 data = READ32(rnv);
493		if (arm->pendingAbtD == 0)
	474	if (m_pendingAbtD == 0)
494	475	{
495	476	if (rd == eR15)
496	477	{
r24074	r24075
503	484	}
504	485	else
505	486	{
506		SET_REGISTER(~~arm,~~ rd, data);
	487	SET_REGISTER(rd, data);
507	488	}
508	489	}
509	490	}
r24074	r24075
518	499	LOG(("Wrote R15 in byte mode\n"));
519	500	#endif
520	501
521		WRITE8(rnv, (UINT8) GET_REGISTER(~~arm,~~ rd) & 0xffu);
	502	WRITE8(rnv, (UINT8) GET_REGISTER(rd) & 0xffu);
522	503	}
523	504	else
524	505	{
r24074	r24075
527	508	LOG(("Wrote R15 in 32bit mode\n"));
528	509	#endif
529	510
530		//WRITE32(rnv, rd == eR15 ? R15 + 8 : GET_REGISTER(arm, rd));
531		WRITE32(rnv, rd == eR15 ? R15 + 8 + 4 : GET_REGISTER(arm, rd)); // manual says STR rd = PC, +12
	511	//WRITE32(rnv, rd == eR15 ? R15 + 8 : GET_REGISTER(rd));
	512	WRITE32(rnv, rd == eR15 ? R15 + 8 + 4 : GET_REGISTER(rd)); // manual says STR rd = PC, +12
532	513	}
533	514	// Store takes only 2 N Cycles, so add + 1
534	515	ARM7_ICOUNT += 1;
535	516	}
536	517
537		if (arm->pendingAbtD != 0)
	518	if (m_pendingAbtD != 0)
538	519	{
539	520	if ((insn & INSN_SDT_P) && (insn & INSN_SDT_W))
540	521	{
541		SET_REGISTER(~~arm,~~ rn, rnv_old);
	522	SET_REGISTER(rn, rnv_old);
542	523	}
543	524	}
544	525	else
r24074	r24075
551	532	/* Writeback is applied in pipeline, before value is read from mem,
552	533	so writeback is effectively ignored */
553	534	if (rd == rn) {
554		SET_REGISTER(ar~~m, r~~n, GET_REGISTER(~~arm,~~ rd));
	535	SET_REGISTER(rn, GET_REGISTER(rd));
555	536	// todo: check for offs... ?
556	537	}
557	538	else {
558	539	if ((insn & INSN_SDT_W) != 0)
559	540	LOG(("%08x: RegisterWritebackIncrement %d %d %d\n", R15, (insn & INSN_SDT_P) != 0, (insn & INSN_SDT_W) != 0, (insn & INSN_SDT_U) != 0));
560	541
561		SET_REGISTER(~~arm,~~ rn, (rnv + off));
	542	SET_REGISTER(rn, (rnv + off));
562	543	}
563	544	}
564	545	else
r24074	r24075
566	547	/* Writeback is applied in pipeline, before value is read from mem,
567	548	so writeback is effectively ignored */
568	549	if (rd == rn) {
569		SET_REGISTER(ar~~m, r~~n, GET_REGISTER(~~arm,~~ rd));
	550	SET_REGISTER(rn, GET_REGISTER(rd));
570	551	}
571	552	else {
572		SET_REGISTER(~~arm,~~ rn, (rnv - off));
	553	SET_REGISTER(rn, (rnv - off));
573	554
574	555	if ((insn & INSN_SDT_W) != 0)
575	556	LOG(("%08x: RegisterWritebackDecrement %d %d %d\n", R15, (insn & INSN_SDT_P) != 0, (insn & INSN_SDT_W) != 0, (insn & INSN_SDT_U) != 0));
r24074	r24075
583	564
584	565	} /* HandleMemSingle */
585	566
586		~~static~~ void HandleHalfWordDT(~~arm_state *arm,~~ UINT32 insn)
	567	void arm7_cpu_device::HandleHalfWordDT(UINT32 insn)
587	568	{
588	569	UINT32 rn, rnv, off, rd, rnv_old = 0;
589	570
r24074	r24075
594	575	}
595	576	else {
596	577	// register
597		off = GET_REGISTER(~~arm,~~ insn & 0x0f);
	578	off = GET_REGISTER(insn & 0x0f);
598	579	}
599	580
600	581	/* Calculate Rn, accounting for PC */
r24074	r24075
605	586	/* Pre-indexed addressing */
606	587	if (insn & INSN_SDT_U)
607	588	{
608		rnv = (GET_REGISTER(~~arm,~~ rn) + off);
	589	rnv = (GET_REGISTER(rn) + off);
609	590	}
610	591	else
611	592	{
612		rnv = (GET_REGISTER(~~arm,~~ rn) - off);
	593	rnv = (GET_REGISTER(rn) - off);
613	594	}
614	595
615	596	if (insn & INSN_SDT_W)
616	597	{
617		rnv_old = GET_REGISTER(arm, rn);
618		SET_REGISTER(arm, rn, rnv);
	598	rnv_old = GET_REGISTER(rn);
	599	SET_REGISTER(rn, rnv);
619	600
620	601	// check writeback???
621	602	}
r24074	r24075
633	614	}
634	615	else
635	616	{
636		rnv = GET_REGISTER(~~arm,~~ rn);
	617	rnv = GET_REGISTER(rn);
637	618	}
638	619	}
639	620
r24074	r24075
664	645	newval = (UINT32)(signbyte << 8)\|databyte;
665	646	}
666	647
667		if (arm->pendingAbtD == 0)
	648	if (m_pendingAbtD == 0)
668	649	{
669	650	// PC?
670	651	if (rd == eR15)
r24074	r24075
676	657	}
677	658	else
678	659	{
679		SET_REGISTER(~~arm,~~ rd, newval);
	660	SET_REGISTER(rd, newval);
680	661	R15 += 4;
681	662	}
682	663
r24074	r24075
692	673	{
693	674	UINT32 newval = READ16(rnv);
694	675
695		if (arm->pendingAbtD == 0)
	676	if (m_pendingAbtD == 0)
696	677	{
697	678	if (rd == eR15)
698	679	{
r24074	r24075
702	683	}
703	684	else
704	685	{
705		SET_REGISTER(~~arm,~~ rd, newval);
	686	SET_REGISTER(rd, newval);
706	687	R15 += 4;
707	688	}
708	689
r24074	r24075
721	702	{
722	703	if ((insn & 0x60) == 0x40) // LDRD
723	704	{
724		SET_REGISTER(arm, rd, READ32(rnv));
725		SET_REGISTER(arm, rd+1, READ32(rnv+4));
	705	SET_REGISTER(rd, READ32(rnv));
	706	SET_REGISTER(rd+1, READ32(rnv+4));
726	707	R15 += 4;
727	708	}
728	709	else if ((insn & 0x60) == 0x60) // STRD
729	710	{
730		WRITE32(rnv, GET_REGISTER(arm, rd));
731		WRITE32(rnv+4, GET_REGISTER(arm, rd+1));
	711	WRITE32(rnv, GET_REGISTER(rd));
	712	WRITE32(rnv+4, GET_REGISTER(rd+1));
732	713	R15 += 4;
733	714	}
734	715	else
735	716	{
736		// WRITE16(rnv, rd == eR15 ? R15 + 8 : GET_REGISTER(arm, rd));
737		WRITE16(rnv, rd == eR15 ? R15 + 8 + 4 : GET_REGISTER(arm, rd)); // manual says STR RD=PC, +12 of address
	717	// WRITE16(rnv, rd == eR15 ? R15 + 8 : GET_REGISTER(rd));
	718	WRITE16(rnv, rd == eR15 ? R15 + 8 + 4 : GET_REGISTER(rd)); // manual says STR RD=PC, +12 of address
738	719
739	720	// if R15 is not increased then e.g. "STRH R10, [R15,#$10]" will be executed over and over again
740	721	#if 0
r24074	r24075
747	728	}
748	729	}
749	730
750		if (arm->pendingAbtD != 0)
	731	if (m_pendingAbtD != 0)
751	732	{
752	733	if ((insn & INSN_SDT_P) && (insn & INSN_SDT_W))
753	734	{
754		SET_REGISTER(~~arm,~~ rn, rnv_old);
	735	SET_REGISTER(rn, rnv_old);
755	736	}
756	737	}
757	738	else
r24074	r24075
766	747	/* Writeback is applied in pipeline, before value is read from mem,
767	748	so writeback is effectively ignored */
768	749	if (rd == rn) {
769		SET_REGISTER(ar~~m, r~~n, GET_REGISTER(~~arm,~~ rd));
	750	SET_REGISTER(rn, GET_REGISTER(rd));
770	751	// todo: check for offs... ?
771	752	}
772	753	else {
773	754	if ((insn & INSN_SDT_W) != 0)
774	755	LOG(("%08x: RegisterWritebackIncrement %d %d %d\n", R15, (insn & INSN_SDT_P) != 0, (insn & INSN_SDT_W) != 0, (insn & INSN_SDT_U) != 0));
775	756
776		SET_REGISTER(~~arm,~~ rn, (rnv + off));
	757	SET_REGISTER(rn, (rnv + off));
777	758	}
778	759	}
779	760	else
r24074	r24075
781	762	/* Writeback is applied in pipeline, before value is read from mem,
782	763	so writeback is effectively ignored */
783	764	if (rd == rn) {
784		SET_REGISTER(ar~~m, r~~n, GET_REGISTER(~~arm,~~ rd));
	765	SET_REGISTER(rn, GET_REGISTER(rd));
785	766	}
786	767	else {
787		SET_REGISTER(~~arm,~~ rn, (rnv - off));
	768	SET_REGISTER(rn, (rnv - off));
788	769
789	770	if ((insn & INSN_SDT_W) != 0)
790	771	LOG(("%08x: RegisterWritebackDecrement %d %d %d\n", R15, (insn & INSN_SDT_P) != 0, (insn & INSN_SDT_W) != 0, (insn & INSN_SDT_U) != 0));
r24074	r24075
796	777
797	778	}
798	779
799		~~static~~ void HandleSwap(~~arm_state *arm,~~ UINT32 insn)
	780	void arm7_cpu_device::HandleSwap(UINT32 insn)
800	781	{
801	782	UINT32 rn, rm, rd, tmp;
802	783
803		rn = GET_REGISTER(arm, (insn >> 16) & 0xf); // reg. w/read address
804		rm = GET_REGISTER(arm, insn & 0xf); // reg. w/write address
	784	rn = GET_REGISTER((insn >> 16) & 0xf); // reg. w/read address
	785	rm = GET_REGISTER(insn & 0xf); // reg. w/write address
805	786	rd = (insn >> 12) & 0xf; // dest reg
806	787
807	788	#if ARM7_DEBUG_CORE
r24074	r24075
814	795	{
815	796	tmp = READ8(rn);
816	797	WRITE8(rn, rm);
817		SET_REGISTER(~~arm,~~ rd, tmp);
	798	SET_REGISTER(rd, tmp);
818	799	}
819	800	else
820	801	{
821	802	tmp = READ32(rn);
822	803	WRITE32(rn, rm);
823		SET_REGISTER(~~arm,~~ rd, tmp);
	804	SET_REGISTER(rd, tmp);
824	805	}
825	806
826	807	R15 += 4;
r24074	r24075
828	809	ARM7_ICOUNT -= 1;
829	810	}
830	811
831		~~static~~ void HandlePSRTransfer(~~arm_state *arm,~~ UINT32 insn)
	812	void arm7_cpu_device::HandlePSRTransfer(UINT32 insn)
832	813	{
833	814	int reg = (insn & 0x400000) ? SPSR : eCPSR; // Either CPSR or SPSR
834	815	UINT32 newval, val = 0;
835	816	int oldmode = GET_CPSR & MODE_FLAG;
836	817
837	818	// get old value of CPSR/SPSR
838		newval = GET_REGISTER(~~arm,~~ reg);
	819	newval = GET_REGISTER(reg);
839	820
840	821	// MSR (bit 21 set) - Copy value to CPSR/SPSR
841	822	if ((insn & 0x00200000))
r24074	r24075
852	833	// Value from Register
853	834	else
854	835	{
855		val = GET_REGISTER(~~arm,~~ insn & 0x0f);
	836	val = GET_REGISTER(insn & 0x0f);
856	837	}
857	838
858	839	// apply field code bits
r24074	r24075
914	895	if (reg == eCPSR)
915	896	SET_CPSR(newval);
916	897	else
917		SET_REGISTER(~~arm,~~ reg, newval);
	898	SET_REGISTER(reg, newval);
918	899
919	900	// Switch to new mode if changed
920	901	if ((newval & MODE_FLAG) != oldmode)
921		SwitchMode(~~arm,~~ GET_MODE);
	902	SwitchMode(GET_MODE);
922	903
923	904	}
924	905	// MRS (bit 21 clear) - Copy CPSR or SPSR to specified Register
925	906	else
926	907	{
927		SET_REGISTER(~~arm,~~ (insn >> 12)& 0x0f, GET_REGISTER(~~arm,~~ reg));
	908	SET_REGISTER((insn >> 12)& 0x0f, GET_REGISTER(reg));
928	909	}
929	910	}
930	911
931		~~static~~ void HandleALU(~~arm_state *arm,~~ UINT32 insn)
	912	void arm7_cpu_device::HandleALU(UINT32 insn)
932	913	{
933	914	UINT32 op2, sc = 0, rd, rn, opcode;
934	915	UINT32 by, rdn;
r24074	r24075
965	946	/* Op2 = Register Value */
966	947	else
967	948	{
968		op2 = decodeShift(~~arm,~~ insn, (insn & INSN_S) ? &sc : NULL);
	949	op2 = decodeShift(insn, (insn & INSN_S) ? &sc : NULL);
969	950
970	951	// LD TODO sc will always be 0 if this applies
971	952	if (!(insn & INSN_S))
r24074	r24075
991	972	}
992	973	else
993	974	{
994		rn = GET_REGISTER(~~arm,~~ rn);
	975	rn = GET_REGISTER(rn);
995	976	}
996	977	}
997	978
r24074	r24075
1087	1068	if (GET_MODE != eARM7_MODE_USER)
1088	1069	{
1089	1070	// Update CPSR from SPSR
1090		SET_CPSR(GET_REGISTER(arm, SPSR));
1091		SwitchMode(arm, GET_MODE);
	1071	SET_CPSR(GET_REGISTER(SPSR));
	1072	SwitchMode(GET_MODE);
1092	1073	}
1093	1074
1094	1075	R15 = rd;
r24074	r24075
1100	1081	R15 = rd; //(R15 & 0x03FFFFFC) \| (rd & 0xFC000003);
1101	1082	temp = (GET_CPSR & 0x0FFFFF20) \| (rd & 0xF0000000) /* N Z C V / \| ((rd & 0x0C000000) >> (26 - 6)) / I F / \| (rd & 0x00000003) / M1 M0 */;
1102	1083	SET_CPSR( temp);
1103		SwitchMode( ~~arm,~~ temp & 3);
	1084	SwitchMode( temp & 3);
1104	1085	}
1105	1086
1106	1087	// extra cycles (PC written)
r24074	r24075
1111	1092	}
1112	1093	else
1113	1094	/* S Flag is set - Write results to register & update CPSR (which was already handled using HandleALU flag macros) */
1114		SET_REGISTER(~~arm,~~ rdn, rd);
	1095	SET_REGISTER(rdn, rd);
1115	1096	}
1116	1097	}
1117	1098	// SJE: Don't think this applies any more.. (see page 44 at bottom)
r24074	r24075
1130	1111	R15 = (R15 & 0x03FFFFFC) \| (rd & ~0x03FFFFFC);
1131	1112	temp = (GET_CPSR & 0x0FFFFF20) \| (rd & 0xF0000000) /* N Z C V / \| ((rd & 0x0C000000) >> (26 - 6)) / I F / \| (rd & 0x00000003) / M1 M0 */;
1132	1113	SET_CPSR( temp);
1133		SwitchMode( ~~arm,~~ temp & 3);
	1114	SwitchMode( temp & 3);
1134	1115	}
1135	1116
1136	1117	/* IRQ masks may have changed in this instruction */
r24074	r24075
1150	1131	ARM7_ICOUNT += 2;
1151	1132	}
1152	1133
1153		~~static~~ void HandleMul(~~arm_state *arm,~~ UINT32 insn)
	1134	void arm7_cpu_device::HandleMul(UINT32 insn)
1154	1135	{
1155	1136	UINT32 r, rm, rs;
1156	1137
r24074	r24075
1160	1141	// multiply, which is controlled by the value of the multiplier operand
1161	1142	// specified by Rs.
1162	1143
1163		rm = GET_REGISTER(arm, insn & INSN_MUL_RM);
1164		rs = GET_REGISTER(arm, (insn & INSN_MUL_RS) >> INSN_MUL_RS_SHIFT);
	1144	rm = GET_REGISTER(insn & INSN_MUL_RM);
	1145	rs = GET_REGISTER((insn & INSN_MUL_RS) >> INSN_MUL_RS_SHIFT);
1165	1146
1166	1147	/* Do the basic multiply of Rm and Rs */
1167	1148	r = rm * rs;
r24074	r24075
1176	1157	/* Add on Rn if this is a MLA */
1177	1158	if (insn & INSN_MUL_A)
1178	1159	{
1179		r += GET_REGISTER(~~arm,~~ (insn & INSN_MUL_RN) >> INSN_MUL_RN_SHIFT);
	1160	r += GET_REGISTER((insn & INSN_MUL_RN) >> INSN_MUL_RN_SHIFT);
1180	1161	// extra cycle for MLA
1181	1162	ARM7_ICOUNT -= 1;
1182	1163	}
1183	1164
1184	1165	/* Write the result */
1185		SET_REGISTER(~~arm,~~ (insn & INSN_MUL_RD) >> INSN_MUL_RD_SHIFT, r);
	1166	SET_REGISTER((insn & INSN_MUL_RD) >> INSN_MUL_RD_SHIFT, r);
1186	1167
1187	1168	/* Set N and Z if asked */
1188	1169	if (insn & INSN_S)
r24074	r24075
1200	1181	}
1201	1182
1202	1183	// todo: add proper cycle counts
1203		~~static~~ void HandleSMulLong(~~arm_state *arm,~~ UINT32 insn)
	1184	void arm7_cpu_device::HandleSMulLong(UINT32 insn)
1204	1185	{
1205	1186	INT32 rm, rs;
1206	1187	UINT32 rhi, rlo;
r24074	r24075
1210	1191	// number of 8 bit multiplier array cycles required to complete the multiply, which is
1211	1192	// controlled by the value of the multiplier operand specified by Rs.
1212	1193
1213		rm = (INT32)GET_REGISTER(arm, insn & 0xf);
1214		rs = (INT32)GET_REGISTER(arm, ((insn >> 8) & 0xf));
	1194	rm = (INT32)GET_REGISTER(insn & 0xf);
	1195	rs = (INT32)GET_REGISTER(((insn >> 8) & 0xf));
1215	1196	rhi = (insn >> 16) & 0xf;
1216	1197	rlo = (insn >> 12) & 0xf;
1217	1198
r24074	r24075
1226	1207	/* Add on Rn if this is a MLA */
1227	1208	if (insn & INSN_MUL_A)
1228	1209	{
1229		INT64 acum = (INT64)((((INT64)(GET_REGISTER(ar~~m, r~~hi))) << 32) \| GET_REGISTER(~~arm,~~ rlo));
	1210	INT64 acum = (INT64)((((INT64)(GET_REGISTER(rhi))) << 32) \| GET_REGISTER(rlo));
1230	1211	res += acum;
1231	1212	// extra cycle for MLA
1232	1213	ARM7_ICOUNT -= 1;
1233	1214	}
1234	1215
1235	1216	/* Write the result (upper dword goes to RHi, lower to RLo) */
1236		SET_REGISTER(arm, rhi, res >> 32);
1237		SET_REGISTER(arm, rlo, res & 0xFFFFFFFF);
	1217	SET_REGISTER(rhi, res >> 32);
	1218	SET_REGISTER(rlo, res & 0xFFFFFFFF);
1238	1219
1239	1220	/* Set N and Z if asked */
1240	1221	if (insn & INSN_S)
r24074	r24075
1252	1233	}
1253	1234
1254	1235	// todo: add proper cycle counts
1255		~~static~~ void HandleUMulLong(~~arm_state *arm,~~ UINT32 insn)
	1236	void arm7_cpu_device::HandleUMulLong(UINT32 insn)
1256	1237	{
1257	1238	UINT32 rm, rs;
1258	1239	UINT32 rhi, rlo;
r24074	r24075
1262	1243	// number of 8 bit multiplier array cycles required to complete the multiply, which is
1263	1244	// controlled by the value of the multiplier operand specified by Rs.
1264	1245
1265		rm = (INT32)GET_REGISTER(arm, insn & 0xf);
1266		rs = (INT32)GET_REGISTER(arm, ((insn >> 8) & 0xf));
	1246	rm = (INT32)GET_REGISTER(insn & 0xf);
	1247	rs = (INT32)GET_REGISTER(((insn >> 8) & 0xf));
1267	1248	rhi = (insn >> 16) & 0xf;
1268	1249	rlo = (insn >> 12) & 0xf;
1269	1250
r24074	r24075
1278	1259	/* Add on Rn if this is a MLA */
1279	1260	if (insn & INSN_MUL_A)
1280	1261	{
1281		UINT64 acum = (UINT64)((((UINT64)(GET_REGISTER(ar~~m, r~~hi))) << 32) \| GET_REGISTER(~~arm,~~ rlo));
	1262	UINT64 acum = (UINT64)((((UINT64)(GET_REGISTER(rhi))) << 32) \| GET_REGISTER(rlo));
1282	1263	res += acum;
1283	1264	// extra cycle for MLA
1284	1265	ARM7_ICOUNT -= 1;
1285	1266	}
1286	1267
1287	1268	/* Write the result (upper dword goes to RHi, lower to RLo) */
1288		SET_REGISTER(arm, rhi, res >> 32);
1289		SET_REGISTER(arm, rlo, res & 0xFFFFFFFF);
	1269	SET_REGISTER(rhi, res >> 32);
	1270	SET_REGISTER(rlo, res & 0xFFFFFFFF);
1290	1271
1291	1272	/* Set N and Z if asked */
1292	1273	if (insn & INSN_S)
r24074	r24075
1302	1283	ARM7_ICOUNT += 3;
1303	1284	}
1304	1285
1305		~~static~~ void HandleMemBlock(~~arm_state *arm,~~ UINT32 insn)
	1286	void arm7_cpu_device::HandleMemBlock(UINT32 insn)
1306	1287	{
1307	1288	UINT32 rb = (insn & INSN_RN) >> INSN_RN_SHIFT;
1308		UINT32 rbp = GET_REGISTER(~~arm,~~ rb);
	1289	UINT32 rbp = GET_REGISTER(rb);
1309	1290	int result;
1310	1291
1311	1292	#if ARM7_DEBUG_CORE
r24074	r24075
1335	1316	// !! actually switching to user mode triggers a section permission fault in Happy Fish 302-in-1 (BP C0030DF4, press F5 ~16 times) !!
1336	1317	// set to user mode - then do the transfer, and set back
1337	1318	//int curmode = GET_MODE;
1338		//SwitchMode(~~arm,~~ eARM7_MODE_USER);
	1319	//SwitchMode(eARM7_MODE_USER);
1339	1320	LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15));
1340		result = loadInc(~~arm,~~ insn & 0xffff, rbp, insn & INSN_BDT_S, eARM7_MODE_USER);
	1321	result = loadInc(insn & 0xffff, rbp, insn & INSN_BDT_S, eARM7_MODE_USER);
1341	1322	// todo - not sure if Writeback occurs on User registers also..
1342		//SwitchMode(~~arm,~~ curmode);
	1323	//SwitchMode(curmode);
1343	1324	}
1344	1325	else
1345		result = loadInc(~~arm,~~ insn & 0xffff, rbp, insn & INSN_BDT_S, GET_MODE);
	1326	result = loadInc(insn & 0xffff, rbp, insn & INSN_BDT_S, GET_MODE);
1346	1327
1347		if ((insn & INSN_BDT_W) && (arm->pendingAbtD == 0))
	1328	if ((insn & INSN_BDT_W) && (m_pendingAbtD == 0))
1348	1329	{
1349	1330	#if ARM7_DEBUG_CORE
1350	1331	if (rb == 15)
r24074	r24075
1354	1335	// GBA "V-Rally 3" expects R0 not to be overwritten with the updated base value [BP 8077B0C]
1355	1336	if (((insn >> rb) & 1) == 0)
1356	1337	{
1357		SET_REGISTER(ar~~m, r~~b, GET_REGISTER(~~arm,~~ rb) + result * 4);
	1338	SET_REGISTER(rb, GET_REGISTER(rb) + result * 4);
1358	1339	}
1359	1340	}
1360	1341
1361	1342	// R15 included? (NOTE: CPSR restore must occur LAST otherwise wrong registers restored!)
1362		if ((insn & 0x8000) && (arm->pendingAbtD == 0)) {
	1343	if ((insn & 0x8000) && (m_pendingAbtD == 0)) {
1363	1344	R15 -= 4; // SJE: I forget why i did this?
1364	1345	// S - Flag Set? Signals transfer of current mode SPSR->CPSR
1365	1346	if (insn & INSN_BDT_S)
1366	1347	{
1367	1348	if (MODE32)
1368	1349	{
1369		SET_CPSR(GET_REGISTER(arm, SPSR));
1370		SwitchMode(arm, GET_MODE);
	1350	SET_CPSR(GET_REGISTER(SPSR));
	1351	SwitchMode(GET_MODE);
1371	1352	}
1372	1353	else
1373	1354	{
r24074	r24075
1375	1356	// LOG(("LDM + S \| R15 %08X CPSR %08X\n", R15, GET_CPSR));
1376	1357	temp = (GET_CPSR & 0x0FFFFF20) \| (R15 & 0xF0000000) /* N Z C V / \| ((R15 & 0x0C000000) >> (26 - 6)) / I F / \| (R15 & 0x00000003) / M1 M0 */;
1377	1358	SET_CPSR( temp);
1378		SwitchMode(~~arm,~~ temp & 3);
	1359	SwitchMode(temp & 3);
1379	1360	}
1380	1361	}
1381	1362	// LDM PC - takes 2 extra cycles
r24074	r24075
1395	1376	{
1396	1377	// set to user mode - then do the transfer, and set back
1397	1378	//int curmode = GET_MODE;
1398		//SwitchMode(~~arm,~~ eARM7_MODE_USER);
	1379	//SwitchMode(eARM7_MODE_USER);
1399	1380	LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15));
1400		result = loadDec(~~arm,~~ insn & 0xffff, rbp, insn & INSN_BDT_S, eARM7_MODE_USER);
	1381	result = loadDec(insn & 0xffff, rbp, insn & INSN_BDT_S, eARM7_MODE_USER);
1401	1382	// todo - not sure if Writeback occurs on User registers also..
1402		//SwitchMode(~~arm,~~ curmode);
	1383	//SwitchMode(curmode);
1403	1384	}
1404	1385	else
1405		result = loadDec(~~arm,~~ insn & 0xffff, rbp, insn & INSN_BDT_S, GET_MODE);
	1386	result = loadDec(insn & 0xffff, rbp, insn & INSN_BDT_S, GET_MODE);
1406	1387
1407		if ((insn & INSN_BDT_W) && (arm->pendingAbtD == 0))
	1388	if ((insn & INSN_BDT_W) && (m_pendingAbtD == 0))
1408	1389	{
1409	1390	if (rb == 0xf)
1410	1391	LOG(("%08x: Illegal LDRM writeback to r15\n", R15));
1411	1392	// "A LDM will always overwrite the updated base if the base is in the list." (also for a user bank transfer?)
1412	1393	if (((insn >> rb) & 1) == 0)
1413	1394	{
1414		SET_REGISTER(ar~~m, r~~b, GET_REGISTER(~~arm,~~ rb) - result * 4);
	1395	SET_REGISTER(rb, GET_REGISTER(rb) - result * 4);
1415	1396	}
1416	1397	}
1417	1398
1418	1399	// R15 included? (NOTE: CPSR restore must occur LAST otherwise wrong registers restored!)
1419		if ((insn & 0x8000) && (arm->pendingAbtD == 0)) {
	1400	if ((insn & 0x8000) && (m_pendingAbtD == 0)) {
1420	1401	R15 -= 4; // SJE: I forget why i did this?
1421	1402	// S - Flag Set? Signals transfer of current mode SPSR->CPSR
1422	1403	if (insn & INSN_BDT_S)
1423	1404	{
1424	1405	if (MODE32)
1425	1406	{
1426		SET_CPSR(GET_REGISTER(arm, SPSR));
1427		SwitchMode(arm, GET_MODE);
	1407	SET_CPSR(GET_REGISTER(SPSR));
	1408	SwitchMode(GET_MODE);
1428	1409	}
1429	1410	else
1430	1411	{
r24074	r24075
1432	1413	// LOG(("LDM + S \| R15 %08X CPSR %08X\n", R15, GET_CPSR));
1433	1414	temp = (GET_CPSR & 0x0FFFFF20) /* N Z C V I F M4 M3 M2 M1 M0 / \| (R15 & 0xF0000000) / N Z C V / \| ((R15 & 0x0C000000) >> (26 - 6)) / I F / \| (R15 & 0x00000003) / M1 M0 */;
1434	1415	SET_CPSR( temp);
1435		SwitchMode(~~arm,~~ temp & 3);
	1416	SwitchMode(temp & 3);
1436	1417	}
1437	1418	}
1438	1419	// LDM PC - takes 2 extra cycles
r24074	r24075
1468	1449
1469	1450	// set to user mode - then do the transfer, and set back
1470	1451	//int curmode = GET_MODE;
1471		//SwitchMode(~~arm,~~ eARM7_MODE_USER);
	1452	//SwitchMode(eARM7_MODE_USER);
1472	1453	LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15));
1473		result = storeInc(~~arm,~~ insn & 0xffff, rbp, eARM7_MODE_USER);
	1454	result = storeInc(insn & 0xffff, rbp, eARM7_MODE_USER);
1474	1455	// todo - not sure if Writeback occurs on User registers also..
1475		//SwitchMode(~~arm,~~ curmode);
	1456	//SwitchMode(curmode);
1476	1457	}
1477	1458	else
1478		result = storeInc(~~arm,~~ insn & 0xffff, rbp, GET_MODE);
	1459	result = storeInc(insn & 0xffff, rbp, GET_MODE);
1479	1460
1480		if ((insn & INSN_BDT_W) && (arm->pendingAbtD == 0))
	1461	if ((insn & INSN_BDT_W) && (m_pendingAbtD == 0))
1481	1462	{
1482		SET_REGISTER(ar~~m, r~~b, GET_REGISTER(~~arm,~~ rb) + result * 4);
	1463	SET_REGISTER(rb, GET_REGISTER(rb) + result * 4);
1483	1464	}
1484	1465	}
1485	1466	else
r24074	r24075
1495	1476	{
1496	1477	// set to user mode - then do the transfer, and set back
1497	1478	//int curmode = GET_MODE;
1498		//SwitchMode(~~arm,~~ eARM7_MODE_USER);
	1479	//SwitchMode(eARM7_MODE_USER);
1499	1480	LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15));
1500		result = storeDec(~~arm,~~ insn & 0xffff, rbp, eARM7_MODE_USER);
	1481	result = storeDec(insn & 0xffff, rbp, eARM7_MODE_USER);
1501	1482	// todo - not sure if Writeback occurs on User registers also..
1502		//SwitchMode(~~arm,~~ curmode);
	1483	//SwitchMode(curmode);
1503	1484	}
1504	1485	else
1505		result = storeDec(~~arm,~~ insn & 0xffff, rbp, GET_MODE);
	1486	result = storeDec(insn & 0xffff, rbp, GET_MODE);
1506	1487
1507		if ((insn & INSN_BDT_W) && (arm->pendingAbtD == 0))
	1488	if ((insn & INSN_BDT_W) && (m_pendingAbtD == 0))
1508	1489	{
1509		SET_REGISTER(ar~~m, r~~b, GET_REGISTER(~~arm,~~ rb) - result * 4);
	1490	SET_REGISTER(rb, GET_REGISTER(rb) - result * 4);
1510	1491	}
1511	1492	}
1512	1493	if (insn & (1 << eR15))
r24074	r24075
1522	1503	} /* HandleMemBlock */
1523	1504
1524	1505
1525		arm7ops_ophandler ops_handler[0x10] =
	1506	const arm7_cpu_device::arm7ops_ophandler arm7_cpu_device::ops_handler[0x10] =
1526	1507	{
1527		arm7ops_0123, arm7ops_0123, arm7ops_0123, arm7ops_0123,
1528		arm7ops_4567, arm7ops_4567, arm7ops_4567, arm7ops_4567,
1529		arm7ops_89, arm7ops_89, arm7ops_ab, arm7ops_ab,
1530		arm7ops_cd, arm7ops_cd, arm7ops_e, arm7ops_f,
	1508	&arm7_cpu_device::arm7ops_0123, &arm7_cpu_device::arm7ops_0123, &arm7_cpu_device::arm7ops_0123, &arm7_cpu_device::arm7ops_0123,
	1509	&arm7_cpu_device::arm7ops_4567, &arm7_cpu_device::arm7ops_4567, &arm7_cpu_device::arm7ops_4567, &arm7_cpu_device::arm7ops_4567,
	1510	&arm7_cpu_device::arm7ops_89, &arm7_cpu_device::arm7ops_89, &arm7_cpu_device::arm7ops_ab, &arm7_cpu_device::arm7ops_ab,
	1511	&arm7_cpu_device::arm7ops_cd, &arm7_cpu_device::arm7ops_cd, &arm7_cpu_device::arm7ops_e, &arm7_cpu_device::arm7ops_f,
1531	1512	};
1532	1513
1533		~~const~~ void arm7ops_0123(~~arm_state *arm,~~ UINT32 insn)
	1514	void arm7_cpu_device::arm7ops_0123(UINT32 insn)
1534	1515	{
1535	1516	//case 0:
1536	1517	//case 1:
r24074	r24075
1539	1520	/* Branch and Exchange (BX) */
1540	1521	if ((insn & 0x0ffffff0) == 0x012fff10) // bits 27-4 == 000100101111111111110001
1541	1522	{
1542		R15 = GET_REGISTER(~~arm,~~ insn & 0x0f);
	1523	R15 = GET_REGISTER(insn & 0x0f);
1543	1524	// If new PC address has A0 set, switch to Thumb mode
1544	1525	if (R15 & 1) {
1545	1526	SET_CPSR(GET_CPSR\|T_MASK);
r24074	r24075
1551	1532	UINT32 rm = insn&0xf;
1552	1533	UINT32 rd = (insn>>12)&0xf;
1553	1534
1554		SET_REGISTER(ar~~m, r~~d, count_leading_zeros(GET_REGISTER(~~arm,~~ rm)));
	1535	SET_REGISTER(rd, count_leading_zeros(GET_REGISTER(rm)));
1555	1536
1556	1537	R15 += 4;
1557	1538	}
1558	1539	else if ((insn & 0x0ff000f0) == 0x01000050) // QADD - v5
1559	1540	{
1560		INT32 src1 = GET_REGISTER(arm, insn&0xf);
1561		INT32 src2 = GET_REGISTER(arm, (insn>>16)&0xf);
	1541	INT32 src1 = GET_REGISTER(insn&0xf);
	1542	INT32 src2 = GET_REGISTER((insn>>16)&0xf);
1562	1543	INT64 res;
1563	1544
1564		res = saturate_qbit_overflow(~~arm,~~ (INT64)src1 + (INT64)src2);
	1545	res = saturate_qbit_overflow((INT64)src1 + (INT64)src2);
1565	1546
1566		SET_REGISTER(~~arm,~~ (insn>>12)&0xf, (INT32)res);
	1547	SET_REGISTER((insn>>12)&0xf, (INT32)res);
1567	1548	R15 += 4;
1568	1549	}
1569	1550	else if ((insn & 0x0ff000f0) == 0x01400050) // QDADD - v5
1570	1551	{
1571		INT32 src1 = GET_REGISTER(arm, insn&0xf);
1572		INT32 src2 = GET_REGISTER(arm, (insn>>16)&0xf);
	1552	INT32 src1 = GET_REGISTER(insn&0xf);
	1553	INT32 src2 = GET_REGISTER((insn>>16)&0xf);
1573	1554	INT64 res;
1574	1555
1575	1556	// check if doubling operation will overflow
1576	1557	res = (INT64)src2 * 2;
1577		saturate_qbit_overflow(~~arm,~~ res);
	1558	saturate_qbit_overflow(res);
1578	1559
1579	1560	src2 *= 2;
1580		res = saturate_qbit_overflow(~~arm,~~ (INT64)src1 + (INT64)src2);
	1561	res = saturate_qbit_overflow((INT64)src1 + (INT64)src2);
1581	1562
1582		SET_REGISTER(~~arm,~~ (insn>>12)&0xf, (INT32)res);
	1563	SET_REGISTER((insn>>12)&0xf, (INT32)res);
1583	1564	R15 += 4;
1584	1565	}
1585	1566	else if ((insn & 0x0ff000f0) == 0x01200050) // QSUB - v5
1586	1567	{
1587		INT32 src1 = GET_REGISTER(arm, insn&0xf);
1588		INT32 src2 = GET_REGISTER(arm, (insn>>16)&0xf);
	1568	INT32 src1 = GET_REGISTER(insn&0xf);
	1569	INT32 src2 = GET_REGISTER((insn>>16)&0xf);
1589	1570	INT64 res;
1590	1571
1591		res = saturate_qbit_overflow(~~arm,~~ (INT64)src1 - (INT64)src2);
	1572	res = saturate_qbit_overflow((INT64)src1 - (INT64)src2);
1592	1573
1593		SET_REGISTER(~~arm,~~ (insn>>12)&0xf, (INT32)res);
	1574	SET_REGISTER((insn>>12)&0xf, (INT32)res);
1594	1575	R15 += 4;
1595	1576	}
1596	1577	else if ((insn & 0x0ff000f0) == 0x01600050) // QDSUB - v5
1597	1578	{
1598		INT32 src1 = GET_REGISTER(arm, insn&0xf);
1599		INT32 src2 = GET_REGISTER(arm, (insn>>16)&0xf);
	1579	INT32 src1 = GET_REGISTER(insn&0xf);
	1580	INT32 src2 = GET_REGISTER((insn>>16)&0xf);
1600	1581	INT64 res;
1601	1582
1602	1583	// check if doubling operation will overflow
1603	1584	res = (INT64)src2 * 2;
1604		saturate_qbit_overflow(~~arm,~~ res);
	1585	saturate_qbit_overflow(res);
1605	1586
1606	1587	src2 *= 2;
1607		res = saturate_qbit_overflow(~~arm,~~ (INT64)src1 - (INT64)src2);
	1588	res = saturate_qbit_overflow((INT64)src1 - (INT64)src2);
1608	1589
1609		SET_REGISTER(~~arm,~~ (insn>>12)&0xf, (INT32)res);
	1590	SET_REGISTER((insn>>12)&0xf, (INT32)res);
1610	1591	R15 += 4;
1611	1592	}
1612	1593	else if ((insn & 0x0ff00090) == 0x01000080) // SMLAxy - v5
1613	1594	{
1614		INT32 src1 = GET_REGISTER(arm, insn&0xf);
1615		INT32 src2 = GET_REGISTER(arm, (insn>>8)&0xf);
	1595	INT32 src1 = GET_REGISTER(insn&0xf);
	1596	INT32 src2 = GET_REGISTER((insn>>8)&0xf);
1616	1597	INT32 res1;
1617	1598
1618	1599	// select top and bottom halves of src1/src2 and sign extend if necessary
r24074	r24075
1641	1622	// do the signed multiply
1642	1623	res1 = src1 * src2;
1643	1624	// and the accumulate. NOTE: only the accumulate can cause an overflow, which is why we do it this way.
1644		saturate_qbit_overflow(~~arm,~~ (INT64)res1 + (INT64)GET_REGISTER(~~arm,~~ (insn>>12)&0xf));
	1625	saturate_qbit_overflow((INT64)res1 + (INT64)GET_REGISTER((insn>>12)&0xf));
1645	1626
1646		SET_REGISTER(~~arm,~~ (insn>>16)&0xf, res1 + GET_REGISTER(~~arm,~~ (insn>>12)&0xf));
	1627	SET_REGISTER((insn>>16)&0xf, res1 + GET_REGISTER((insn>>12)&0xf));
1647	1628	R15 += 4;
1648	1629	}
1649	1630	else if ((insn & 0x0ff00090) == 0x01400080) // SMLALxy - v5
1650	1631	{
1651		INT32 src1 = GET_REGISTER(arm, insn&0xf);
1652		INT32 src2 = GET_REGISTER(arm, (insn>>8)&0xf);
	1632	INT32 src1 = GET_REGISTER(insn&0xf);
	1633	INT32 src2 = GET_REGISTER((insn>>8)&0xf);
1653	1634	INT64 dst;
1654	1635
1655		dst = (INT64)GET_REGISTER(arm, (insn>>12)&0xf);
1656		dst \|= (INT64)GET_REGISTER(arm, (insn>>16)&0xf)<<32;
	1636	dst = (INT64)GET_REGISTER((insn>>12)&0xf);
	1637	dst \|= (INT64)GET_REGISTER((insn>>16)&0xf)<<32;
1657	1638
1658	1639	// do the multiply and accumulate
1659	1640	dst += (INT64)src1 * (INT64)src2;
1660	1641
1661	1642	// write back the result
1662		SET_REGISTER(cpustart, (insn>>12)&0xf, (UINT32)dst);
1663		SET_REGISTER(cpustart, (insn>>16)&0xf, (UINT32)(dst >> 32));
	1643	SET_REGISTER((insn>>12)&0xf, (UINT32)dst);
	1644	SET_REGISTER((insn>>16)&0xf, (UINT32)(dst >> 32));
1664	1645	R15 += 4;
1665	1646	}
1666	1647	else if ((insn & 0x0ff00090) == 0x01600080) // SMULxy - v5
1667	1648	{
1668		INT32 src1 = GET_REGISTER(arm, insn&0xf);
1669		INT32 src2 = GET_REGISTER(arm, (insn>>8)&0xf);
	1649	INT32 src1 = GET_REGISTER(insn&0xf);
	1650	INT32 src2 = GET_REGISTER((insn>>8)&0xf);
1670	1651	INT32 res;
1671	1652
1672	1653	// select top and bottom halves of src1/src2 and sign extend if necessary
r24074	r24075
1693	1674	}
1694	1675
1695	1676	res = src1 * src2;
1696		SET_REGISTER(~~cpustart,~~ (insn>>16)&0xf, res);
	1677	SET_REGISTER((insn>>16)&0xf, res);
1697	1678	R15 += 4;
1698	1679	}
1699	1680	else if ((insn & 0x0ff000b0) == 0x012000a0) // SMULWy - v5
1700	1681	{
1701		INT32 src1 = GET_REGISTER(arm, insn&0xf);
1702		INT32 src2 = GET_REGISTER(arm, (insn>>8)&0xf);
	1682	INT32 src1 = GET_REGISTER(insn&0xf);
	1683	INT32 src2 = GET_REGISTER((insn>>8)&0xf);
1703	1684	INT64 res;
1704	1685
1705	1686	if (insn & 0x40)
r24074	r24075
1715	1696
1716	1697	res = (INT64)src1 * (INT64)src2;
1717	1698	res >>= 16;
1718		SET_REGISTER(~~cpustart,~~ (insn>>16)&0xf, (UINT32)res);
	1699	SET_REGISTER((insn>>16)&0xf, (UINT32)res);
1719	1700	R15 += 4;
1720	1701	}
1721	1702	else if ((insn & 0x0ff000b0) == 0x01200080) // SMLAWy - v5
1722	1703	{
1723		INT32 src1 = GET_REGISTER(arm, insn&0xf);
1724		INT32 src2 = GET_REGISTER(arm, (insn>>8)&0xf);
1725		INT32 src3 = GET_REGISTER(arm, (insn>>12)&0xf);
	1704	INT32 src1 = GET_REGISTER(insn&0xf);
	1705	INT32 src2 = GET_REGISTER((insn>>8)&0xf);
	1706	INT32 src3 = GET_REGISTER((insn>>12)&0xf);
1726	1707	INT64 res;
1727	1708
1728	1709	if (insn & 0x40)
r24074	r24075
1740	1721	res >>= 16;
1741	1722
1742	1723	// check for overflow and set the Q bit
1743		saturate_qbit_overflow(~~arm,~~ (INT64)src3 + res);
	1724	saturate_qbit_overflow((INT64)src3 + res);
1744	1725
1745	1726	// do the real accumulate
1746	1727	src3 += (INT32)res;
1747	1728
1748	1729	// write the result back
1749		SET_REGISTER(~~cpustart,~~ (insn>>16)&0xf, (UINT32)res);
	1730	SET_REGISTER((insn>>16)&0xf, (UINT32)res);
1750	1731	R15 += 4;
1751	1732	}
1752	1733	else
r24074	r24075
1756	1737	/* Half Word Data Transfer */
1757	1738	if (insn & 0x60) // bits = 6-5 != 00
1758	1739	{
1759		HandleHalfWordDT(~~arm,~~ insn);
	1740	HandleHalfWordDT(insn);
1760	1741	}
1761	1742	else
1762	1743	/* Swap */
1763	1744	if (insn & 0x01000000) // bit 24 = 1
1764	1745	{
1765		HandleSwap(~~arm,~~ insn);
	1746	HandleSwap(insn);
1766	1747	}
1767	1748	/* Multiply Or Multiply Long */
1768	1749	else
r24074	r24075
1772	1753	{
1773	1754	/* Signed? */
1774	1755	if (insn & 0x00400000)
1775		HandleSMulLong(~~arm,~~ insn);
	1756	HandleSMulLong(insn);
1776	1757	else
1777		HandleUMulLong(~~arm,~~ insn);
	1758	HandleUMulLong(insn);
1778	1759	}
1779	1760	/* multiply */
1780	1761	else
1781	1762	{
1782		HandleMul(~~arm,~~ insn);
	1763	HandleMul(insn);
1783	1764	}
1784	1765	R15 += 4;
1785	1766	}
r24074	r24075
1790	1771	/* PSR Transfer (MRS & MSR) */
1791	1772	if (((insn & 0x00100000) == 0) && ((insn & 0x01800000) == 0x01000000)) // S bit must be clear, and bit 24,23 = 10
1792	1773	{
1793		HandlePSRTransfer(~~arm,~~ insn);
	1774	HandlePSRTransfer(insn);
1794	1775	ARM7_ICOUNT += 2; // PSR only takes 1 - S Cycle, so we add + 2, since at end, we -3..
1795	1776	R15 += 4;
1796	1777	}
1797	1778	/* Data Processing */
1798	1779	else
1799	1780	{
1800		HandleALU(~~arm,~~ insn);
	1781	HandleALU(insn);
1801	1782	}
1802	1783	}
1803	1784	// break;
1804	1785	}
1805	1786
1806		~~const~~ void arm7ops_4567(~~arm_state arm,~~ UINT32 insn) / Data Transfer - Single Data Access */
	1787	void arm7_cpu_device::arm7ops_4567(UINT32 insn) /* Data Transfer - Single Data Access */
1807	1788	{
1808	1789	//case 4:
1809	1790	//case 5:
1810	1791	//case 6:
1811	1792	//case 7:
1812		HandleMemSingle(~~arm,~~ insn);
	1793	HandleMemSingle(insn);
1813	1794	R15 += 4;
1814	1795	// break;
1815	1796	}
1816	1797
1817		~~const~~ void arm7ops_89(~~arm_state arm,~~ UINT32 insn) / Block Data Transfer/Access */
	1798	void arm7_cpu_device::arm7ops_89(UINT32 insn) /* Block Data Transfer/Access */
1818	1799	{
1819	1800	//case 8:
1820	1801	//case 9:
1821		HandleMemBlock(~~arm,~~ insn);
	1802	HandleMemBlock(insn);
1822	1803	R15 += 4;
1823	1804	// break;
1824	1805	}
1825	1806
1826		~~const~~ void arm7ops_a~~b(a~~rm_sta~~te arm,~~ UINT32 insn) / Branch or Branch & Link */
	1807	void arm7_cpu_device::arm7ops_ab(UINT32 insn) /* Branch or Branch & Link */
1827	1808	{
1828	1809	//case 0xa:
1829	1810	//case 0xb:
1830		HandleBranch(~~arm,~~ insn);
	1811	HandleBranch(insn);
1831	1812	// break;
1832	1813	}
1833	1814
1834		~~const~~ void arm7~~ops~~_c~~d(arm~~_~~stat~~e arm, UINT32 insn) / Co-Processor Data Transfer */
	1815	void arm7_cpu_device::arm7ops_cd(UINT32 insn) /* Co-Processor Data Transfer */
1835	1816	{
1836	1817	//case 0xc:
1837	1818	//case 0xd:
1838		HandleCoProcDT(~~arm,~~ insn);
	1819	HandleCoProcDT(insn);
1839	1820	R15 += 4;
1840	1821	// break;
1841	1822	}
1842	1823
1843		~~const~~ void arm7ops_e(arm_s~~tat~~e arm, UINT32 insn) / Co-Processor Data Operation or Register Transfer */
	1824	void arm7_cpu_device::arm7ops_e(UINT32 insn) /* Co-Processor Data Operation or Register Transfer */
1844	1825	{
1845	1826	//case 0xe:
1846	1827	if (insn & 0x10)
1847		HandleCoProcRT(~~arm,~~ insn);
	1828	HandleCoProcRT(insn);
1848	1829	else
1849		HandleCoProcDO(~~arm,~~ insn);
	1830	HandleCoProcDO(insn);
1850	1831	R15 += 4;
1851	1832	// break;
1852	1833	}
1853	1834
1854		~~const~~ void arm7ops_~~f(arm_stat~~e arm, UINT32 insn) / Software Interrupt */
	1835	void arm7_cpu_device::arm7ops_f(UINT32 insn) /* Software Interrupt */
1855	1836	{
1856		arm->pendingSwi = 1;
	1837	m_pendingSwi = 1;
1857	1838	ARM7_CHECKIRQ;
1858	1839	//couldn't find any cycle counts for SWI
1859	1840	// break;

trunk/src/emu/cpu/arm7/arm7.h
r24074	r24075
33	33	#ifndef __ARM7_H__
34	34	#define __ARM7_H__
35	35
	36	#include "cpu/drcfe.h"
	37	#include "cpu/drcuml.h"
	38	#include "cpu/drcumlsh.h"
36	39
	40
37	41	#define ARM7_MAX_FASTRAM 4
38	42	#define ARM7_MAX_HOTSPOTS 16
39	43
r24074	r24075
68	72	* PUBLIC FUNCTIONS
69	73	***************************************************************************************************/
70	74
71		DECLARE_LEGACY_CPU_DEVICE(ARM7, arm7);
72		DECLARE_LEGACY_CPU_DEVICE(ARM7_BE, arm7_be);
73		DECLARE_LEGACY_CPU_DEVICE(ARM7500, arm7500);
74		DECLARE_LEGACY_CPU_DEVICE(ARM9, arm9);
75		DECLARE_LEGACY_CPU_DEVICE(ARM920T, arm920t);
76		DECLARE_LEGACY_CPU_DEVICE(PXA255, pxa255);
77		DECLARE_LEGACY_CPU_DEVICE(SA1110, sa1110);
	75	class arm7_cpu_device : public cpu_device
	76	{
	77	public:
	78	// construction/destruction
	79	arm7_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	80	arm7_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source, UINT8 archRev, UINT8 archFlags, endianness_t endianness = ENDIANNESS_LITTLE);
78	81
	82	protected:
	83	// device-level overrides
	84	virtual void device_start();
	85	virtual void device_reset();
	86
	87	// device_execute_interface overrides
	88	virtual UINT32 execute_min_cycles() const { return 3; }
	89	virtual UINT32 execute_max_cycles() const { return 4; }
	90	virtual UINT32 execute_input_lines() const { return 4; } /* There are actually only 2 input lines: we use 3 variants of the ABORT line while there is only 1 real one */
	91	virtual void execute_run();
	92	virtual void execute_set_input(int inputnum, int state);
	93
	94	// device_memory_interface overrides
	95	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
	96	virtual bool memory_translate(address_spacenum spacenum, int intention, offs_t &address);
	97
	98	// device_state_interface overrides
	99	virtual void state_export(const device_state_entry &entry);
	100	void state_string_export(const device_state_entry &entry, astring &string);
	101
	102	// device_disasm_interface overrides
	103	virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
	104	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
	105	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	106
	107	address_space_config m_program_config;
	108
	109	UINT32 m_r[/NUM_REGS/37];
	110	UINT32 m_pendingIrq;
	111	UINT32 m_pendingFiq;
	112	UINT32 m_pendingAbtD;
	113	UINT32 m_pendingAbtP;
	114	UINT32 m_pendingUnd;
	115	UINT32 m_pendingSwi;
	116	int m_icount;
	117	endianness_t m_endian;
	118	device_irq_acknowledge_callback m_irq_callback;
	119	address_space *m_program;
	120	direct_read_data *m_direct;
	121
	122	/* Coprocessor Registers */
	123	UINT32 m_control;
	124	UINT32 m_tlbBase;
	125	UINT32 m_faultStatus[2];
	126	UINT32 m_faultAddress;
	127	UINT32 m_fcsePID;
	128	UINT32 m_domainAccessControl;
	129
	130	UINT8 m_archRev; // ARM architecture revision (3, 4, and 5 are valid)
	131	UINT8 m_archFlags; // architecture flags
	132
	133	//#if ARM7_MMU_ENABLE_HACK
	134	// UINT32 mmu_enable_addr; // workaround for "MMU is enabled when PA != VA" problem
	135	//#endif
	136
	137	UINT32 m_copro_id;
	138
	139	// For debugger
	140	UINT32 m_pc;
	141
	142	INT64 saturate_qbit_overflow(INT64 res);
	143	void SwitchMode(UINT32 cpsr_mode_val);
	144	UINT32 decodeShift(UINT32 insn, UINT32 *pCarry);
	145	int loadInc(UINT32 pat, UINT32 rbv, UINT32 s, int mode);
	146	int loadDec(UINT32 pat, UINT32 rbv, UINT32 s, int mode);
	147	int storeInc(UINT32 pat, UINT32 rbv, int mode);
	148	int storeDec(UINT32 pat, UINT32 rbv, int mode);
	149	void HandleCoProcDO(UINT32 insn);
	150	void HandleCoProcRT(UINT32 insn);
	151	void HandleCoProcDT(UINT32 insn);
	152	void HandleBranch(UINT32 insn);
	153	void HandleMemSingle(UINT32 insn);
	154	void HandleHalfWordDT(UINT32 insn);
	155	void HandleSwap(UINT32 insn);
	156	void HandlePSRTransfer(UINT32 insn);
	157	void HandleALU(UINT32 insn);
	158	void HandleMul(UINT32 insn);
	159	void HandleSMulLong(UINT32 insn);
	160	void HandleUMulLong(UINT32 insn);
	161	void HandleMemBlock(UINT32 insn);
	162	void arm7ops_0123(UINT32 insn);
	163	void arm7ops_4567(UINT32 insn);
	164	void arm7ops_89(UINT32 insn);
	165	void arm7ops_ab(UINT32 insn);
	166	void arm7ops_cd(UINT32 insn);
	167	void arm7ops_e(UINT32 insn);
	168	void arm7ops_f(UINT32 insn);
	169	void set_cpsr(UINT32 val);
	170	bool arm7_tlb_translate(offs_t &addr, int flags);
	171	UINT32 arm7_tlb_get_first_level_descriptor( UINT32 vaddr );
	172	UINT32 arm7_tlb_get_second_level_descriptor( UINT32 granularity, UINT32 first_desc, UINT32 vaddr );
	173	int detect_fault(int permission, int ap, int flags);
	174	void arm7_check_irq_state();
	175	void arm7_cpu_write32(UINT32 addr, UINT32 data);
	176	void arm7_cpu_write16(UINT32 addr, UINT16 data);
	177	void arm7_cpu_write8(UINT32 addr, UINT8 data);
	178	UINT32 arm7_cpu_read32(UINT32 addr);
	179	UINT16 arm7_cpu_read16(UINT32 addr);
	180	UINT8 arm7_cpu_read8(UINT32 addr);
	181
	182	// Coprocessor support
	183	DECLARE_WRITE32_MEMBER( arm7_do_callback );
	184	DECLARE_READ32_MEMBER( arm7_rt_r_callback );
	185	DECLARE_WRITE32_MEMBER( arm7_rt_w_callback );
	186	void arm7_dt_r_callback(UINT32 insn, UINT32 *prn);
	187	void arm7_dt_w_callback(UINT32 insn, UINT32 *prn);
	188
	189	void tg00_0(UINT32 pc, UINT32 insn);
	190	void tg00_1(UINT32 pc, UINT32 insn);
	191	void tg01_0(UINT32 pc, UINT32 insn);
	192	void tg01_10(UINT32 pc, UINT32 insn);
	193	void tg01_11(UINT32 pc, UINT32 insn);
	194	void tg01_12(UINT32 pc, UINT32 insn);
	195	void tg01_13(UINT32 pc, UINT32 insn);
	196	void tg02_0(UINT32 pc, UINT32 insn);
	197	void tg02_1(UINT32 pc, UINT32 insn);
	198	void tg03_0(UINT32 pc, UINT32 insn);
	199	void tg03_1(UINT32 pc, UINT32 insn);
	200	void tg04_00_00(UINT32 pc, UINT32 insn);
	201	void tg04_00_01(UINT32 pc, UINT32 insn);
	202	void tg04_00_02(UINT32 pc, UINT32 insn);
	203	void tg04_00_03(UINT32 pc, UINT32 insn);
	204	void tg04_00_04(UINT32 pc, UINT32 insn);
	205	void tg04_00_05(UINT32 pc, UINT32 insn);
	206	void tg04_00_06(UINT32 pc, UINT32 insn);
	207	void tg04_00_07(UINT32 pc, UINT32 insn);
	208	void tg04_00_08(UINT32 pc, UINT32 insn);
	209	void tg04_00_09(UINT32 pc, UINT32 insn);
	210	void tg04_00_0a(UINT32 pc, UINT32 insn);
	211	void tg04_00_0b(UINT32 pc, UINT32 insn);
	212	void tg04_00_0c(UINT32 pc, UINT32 insn);
	213	void tg04_00_0d(UINT32 pc, UINT32 insn);
	214	void tg04_00_0e(UINT32 pc, UINT32 insn);
	215	void tg04_00_0f(UINT32 pc, UINT32 insn);
	216	void tg04_01_00(UINT32 pc, UINT32 insn);
	217	void tg04_01_01(UINT32 pc, UINT32 insn);
	218	void tg04_01_02(UINT32 pc, UINT32 insn);
	219	void tg04_01_03(UINT32 pc, UINT32 insn);
	220	void tg04_01_10(UINT32 pc, UINT32 insn);
	221	void tg04_01_11(UINT32 pc, UINT32 insn);
	222	void tg04_01_12(UINT32 pc, UINT32 insn);
	223	void tg04_01_13(UINT32 pc, UINT32 insn);
	224	void tg04_01_20(UINT32 pc, UINT32 insn);
	225	void tg04_01_21(UINT32 pc, UINT32 insn);
	226	void tg04_01_22(UINT32 pc, UINT32 insn);
	227	void tg04_01_23(UINT32 pc, UINT32 insn);
	228	void tg04_01_30(UINT32 pc, UINT32 insn);
	229	void tg04_01_31(UINT32 pc, UINT32 insn);
	230	void tg04_01_32(UINT32 pc, UINT32 insn);
	231	void tg04_01_33(UINT32 pc, UINT32 insn);
	232	void tg04_0203(UINT32 pc, UINT32 insn);
	233	void tg05_0(UINT32 pc, UINT32 insn);
	234	void tg05_1(UINT32 pc, UINT32 insn);
	235	void tg05_2(UINT32 pc, UINT32 insn);
	236	void tg05_3(UINT32 pc, UINT32 insn);
	237	void tg05_4(UINT32 pc, UINT32 insn);
	238	void tg05_5(UINT32 pc, UINT32 insn);
	239	void tg05_6(UINT32 pc, UINT32 insn);
	240	void tg05_7(UINT32 pc, UINT32 insn);
	241	void tg06_0(UINT32 pc, UINT32 insn);
	242	void tg06_1(UINT32 pc, UINT32 insn);
	243	void tg07_0(UINT32 pc, UINT32 insn);
	244	void tg07_1(UINT32 pc, UINT32 insn);
	245	void tg08_0(UINT32 pc, UINT32 insn);
	246	void tg08_1(UINT32 pc, UINT32 insn);
	247	void tg09_0(UINT32 pc, UINT32 insn);
	248	void tg09_1(UINT32 pc, UINT32 insn);
	249	void tg0a_0(UINT32 pc, UINT32 insn);
	250	void tg0a_1(UINT32 pc, UINT32 insn);
	251	void tg0b_0(UINT32 pc, UINT32 insn);
	252	void tg0b_1(UINT32 pc, UINT32 insn);
	253	void tg0b_2(UINT32 pc, UINT32 insn);
	254	void tg0b_3(UINT32 pc, UINT32 insn);
	255	void tg0b_4(UINT32 pc, UINT32 insn);
	256	void tg0b_5(UINT32 pc, UINT32 insn);
	257	void tg0b_6(UINT32 pc, UINT32 insn);
	258	void tg0b_7(UINT32 pc, UINT32 insn);
	259	void tg0b_8(UINT32 pc, UINT32 insn);
	260	void tg0b_9(UINT32 pc, UINT32 insn);
	261	void tg0b_a(UINT32 pc, UINT32 insn);
	262	void tg0b_b(UINT32 pc, UINT32 insn);
	263	void tg0b_c(UINT32 pc, UINT32 insn);
	264	void tg0b_d(UINT32 pc, UINT32 insn);
	265	void tg0b_e(UINT32 pc, UINT32 insn);
	266	void tg0b_f(UINT32 pc, UINT32 insn);
	267	void tg0c_0(UINT32 pc, UINT32 insn);
	268	void tg0c_1(UINT32 pc, UINT32 insn);
	269	void tg0d_0(UINT32 pc, UINT32 insn);
	270	void tg0d_1(UINT32 pc, UINT32 insn);
	271	void tg0d_2(UINT32 pc, UINT32 insn);
	272	void tg0d_3(UINT32 pc, UINT32 insn);
	273	void tg0d_4(UINT32 pc, UINT32 insn);
	274	void tg0d_5(UINT32 pc, UINT32 insn);
	275	void tg0d_6(UINT32 pc, UINT32 insn);
	276	void tg0d_7(UINT32 pc, UINT32 insn);
	277	void tg0d_8(UINT32 pc, UINT32 insn);
	278	void tg0d_9(UINT32 pc, UINT32 insn);
	279	void tg0d_a(UINT32 pc, UINT32 insn);
	280	void tg0d_b(UINT32 pc, UINT32 insn);
	281	void tg0d_c(UINT32 pc, UINT32 insn);
	282	void tg0d_d(UINT32 pc, UINT32 insn);
	283	void tg0d_e(UINT32 pc, UINT32 insn);
	284	void tg0d_f(UINT32 pc, UINT32 insn);
	285	void tg0e_0(UINT32 pc, UINT32 insn);
	286	void tg0e_1(UINT32 pc, UINT32 insn);
	287	void tg0f_0(UINT32 pc, UINT32 insn);
	288	void tg0f_1(UINT32 pc, UINT32 insn);
	289
	290	typedef void ( arm7_cpu_device::*arm7thumb_ophandler ) (UINT32, UINT32);
	291	static const arm7thumb_ophandler thumb_handler[0x40*0x10];
	292
	293	typedef void ( arm7_cpu_device::*arm7ops_ophandler )(UINT32);
	294	static const arm7ops_ophandler ops_handler[0x10];
	295
	296	//
	297	// DRC
	298	//
	299
	300	/* fast RAM info */
	301	struct fast_ram_info
	302	{
	303	offs_t start; /* start of the RAM block */
	304	offs_t end; /* end of the RAM block */
	305	UINT8 readonly; /* TRUE if read-only */
	306	void * base; /* base in memory where the RAM lives */
	307	};
	308
	309	struct hotspot_info
	310	{
	311	UINT32 pc;
	312	UINT32 opcode;
	313	UINT32 cycles;
	314	};
	315
	316	/* internal compiler state */
	317	struct compiler_state
	318	{
	319	UINT32 cycles; /* accumulated cycles */
	320	UINT8 checkints; /* need to check interrupts before next instruction */
	321	UINT8 checksoftints; /* need to check software interrupts before next instruction */
	322	uml::code_label labelnum; /* index for local labels */
	323	};
	324
	325	/* ARM7 registers */
	326	struct arm7imp_state
	327	{
	328	/* core state */
	329	drc_cache * cache; /* pointer to the DRC code cache */
	330	drcuml_state * drcuml; /* DRC UML generator state */
	331	//arm7_frontend * drcfe; /* pointer to the DRC front-end state */
	332	UINT32 drcoptions; /* configurable DRC options */
	333
	334	/* internal stuff */
	335	UINT8 cache_dirty; /* true if we need to flush the cache */
	336	UINT32 jmpdest; /* destination jump target */
	337
	338	/* parameters for subroutines */
	339	UINT64 numcycles; /* return value from gettotalcycles */
	340	UINT32 mode; /* current global mode */
	341	const char * format; /* format string for print_debug */
	342	UINT32 arg0; /* print_debug argument 1 */
	343	UINT32 arg1; /* print_debug argument 2 */
	344
	345	/* register mappings */
	346	uml::parameter regmap[/NUM_REGS/37]; /* parameter to register mappings for all 16 integer registers */
	347
	348	/* subroutines */
	349	uml::code_handle * entry; /* entry point */
	350	uml::code_handle * nocode; /* nocode exception handler */
	351	uml::code_handle * out_of_cycles; /* out of cycles exception handler */
	352	uml::code_handle * tlb_translate; /* tlb translation handler */
	353	uml::code_handle * detect_fault; /* tlb fault detection handler */
	354	uml::code_handle * check_irq; /* irq check handler */
	355	uml::code_handle * read8; /* read byte */
	356	uml::code_handle * write8; /* write byte */
	357	uml::code_handle * read16; /* read half */
	358	uml::code_handle * write16; /* write half */
	359	uml::code_handle * read32; /* read word */
	360	uml::code_handle * write32; /* write word */
	361
	362	/* fast RAM */
	363	UINT32 fastram_select;
	364	fast_ram_info fastram[ARM7_MAX_FASTRAM];
	365
	366	/* hotspots */
	367	UINT32 hotspot_select;
	368	hotspot_info hotspot[ARM7_MAX_HOTSPOTS];
	369	} m_impstate;
	370
	371	typedef void ( arm7_cpu_device::arm7thumb_drcophandler)(drcuml_block, compiler_state, const opcode_desc);
	372	static const arm7thumb_drcophandler drcthumb_handler[0x40*0x10];
	373
	374	void drctg00_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Shift left */
	375	void drctg00_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Shift right */
	376	void drctg01_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	377	void drctg01_10(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	378	void drctg01_11(drcuml_block block, compiler_state compiler, const opcode_desc desc); / SUB Rd, Rs, Rn */
	379	void drctg01_12(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ADD Rd, Rs, #imm */
	380	void drctg01_13(drcuml_block block, compiler_state compiler, const opcode_desc desc); / SUB Rd, Rs, #imm */
	381	void drctg02_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	382	void drctg02_1(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	383	void drctg03_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ADD Rd, #Offset8 */
	384	void drctg03_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / SUB Rd, #Offset8 */
	385	void drctg04_00_00(drcuml_block block, compiler_state compiler, const opcode_desc desc); / AND Rd, Rs */
	386	void drctg04_00_01(drcuml_block block, compiler_state compiler, const opcode_desc desc); / EOR Rd, Rs */
	387	void drctg04_00_02(drcuml_block block, compiler_state compiler, const opcode_desc desc); / LSL Rd, Rs */
	388	void drctg04_00_03(drcuml_block block, compiler_state compiler, const opcode_desc desc); / LSR Rd, Rs */
	389	void drctg04_00_04(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ASR Rd, Rs */
	390	void drctg04_00_05(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ADC Rd, Rs */
	391	void drctg04_00_06(drcuml_block block, compiler_state compiler, const opcode_desc desc); / SBC Rd, Rs */
	392	void drctg04_00_07(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ROR Rd, Rs */
	393	void drctg04_00_08(drcuml_block block, compiler_state compiler, const opcode_desc desc); / TST Rd, Rs */
	394	void drctg04_00_09(drcuml_block block, compiler_state compiler, const opcode_desc desc); / NEG Rd, Rs */
	395	void drctg04_00_0a(drcuml_block block, compiler_state compiler, const opcode_desc desc); / CMP Rd, Rs */
	396	void drctg04_00_0b(drcuml_block block, compiler_state compiler, const opcode_desc desc); / CMN Rd, Rs - check flags, add dasm */
	397	void drctg04_00_0c(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ORR Rd, Rs */
	398	void drctg04_00_0d(drcuml_block block, compiler_state compiler, const opcode_desc desc); / MUL Rd, Rs */
	399	void drctg04_00_0e(drcuml_block block, compiler_state compiler, const opcode_desc desc); / BIC Rd, Rs */
	400	void drctg04_00_0f(drcuml_block block, compiler_state compiler, const opcode_desc desc); / MVN Rd, Rs */
	401	void drctg04_01_00(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	402	void drctg04_01_01(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ADD Rd, HRs */
	403	void drctg04_01_02(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ADD HRd, Rs */
	404	void drctg04_01_03(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Add HRd, HRs */
	405	void drctg04_01_10(drcuml_block block, compiler_state compiler, const opcode_desc desc); / CMP Rd, Rs */
	406	void drctg04_01_11(drcuml_block block, compiler_state compiler, const opcode_desc desc); / CMP Rd, Hs */
	407	void drctg04_01_12(drcuml_block block, compiler_state compiler, const opcode_desc desc); / CMP Hd, Rs */
	408	void drctg04_01_13(drcuml_block block, compiler_state compiler, const opcode_desc desc); / CMP Hd, Hs */
	409	void drctg04_01_20(drcuml_block block, compiler_state compiler, const opcode_desc desc); / MOV Rd, Rs (undefined) */
	410	void drctg04_01_21(drcuml_block block, compiler_state compiler, const opcode_desc desc); / MOV Rd, Hs */
	411	void drctg04_01_22(drcuml_block block, compiler_state compiler, const opcode_desc desc); / MOV Hd, Rs */
	412	void drctg04_01_23(drcuml_block block, compiler_state compiler, const opcode_desc desc); / MOV Hd, Hs */
	413	void drctg04_01_30(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	414	void drctg04_01_31(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	415	void drctg04_01_32(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	416	void drctg04_01_33(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	417	void drctg04_0203(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	418	void drctg05_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / STR Rd, [Rn, Rm] */
	419	void drctg05_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / STRH Rd, [Rn, Rm] */
	420	void drctg05_2(drcuml_block block, compiler_state compiler, const opcode_desc desc); / STRB Rd, [Rn, Rm] */
	421	void drctg05_3(drcuml_block block, compiler_state compiler, const opcode_desc desc); / LDSB Rd, [Rn, Rm] todo, add dasm */
	422	void drctg05_4(drcuml_block block, compiler_state compiler, const opcode_desc desc); / LDR Rd, [Rn, Rm] */
	423	void drctg05_5(drcuml_block block, compiler_state compiler, const opcode_desc desc); / LDRH Rd, [Rn, Rm] */
	424	void drctg05_6(drcuml_block block, compiler_state compiler, const opcode_desc desc); / LDRB Rd, [Rn, Rm] */
	425	void drctg05_7(drcuml_block block, compiler_state compiler, const opcode_desc desc); / LDSH Rd, [Rn, Rm] */
	426	void drctg06_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Store */
	427	void drctg06_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Load */
	428	void drctg07_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Store */
	429	void drctg07_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Load */
	430	void drctg08_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Store */
	431	void drctg08_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Load */
	432	void drctg09_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Store */
	433	void drctg09_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Load */
	434	void drctg0a_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ADD Rd, PC, #nn */
	435	void drctg0a_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ADD Rd, SP, #nn */
	436	void drctg0b_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / ADD SP, #imm */
	437	void drctg0b_1(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	438	void drctg0b_2(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	439	void drctg0b_3(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	440	void drctg0b_4(drcuml_block block, compiler_state compiler, const opcode_desc desc); / PUSH {Rlist} */
	441	void drctg0b_5(drcuml_block block, compiler_state compiler, const opcode_desc desc); / PUSH {Rlist}{LR} */
	442	void drctg0b_6(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	443	void drctg0b_7(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	444	void drctg0b_8(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	445	void drctg0b_9(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	446	void drctg0b_a(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	447	void drctg0b_b(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	448	void drctg0b_c(drcuml_block block, compiler_state compiler, const opcode_desc desc); / POP {Rlist} */
	449	void drctg0b_d(drcuml_block block, compiler_state compiler, const opcode_desc desc); / POP {Rlist}{PC} */
	450	void drctg0b_e(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	451	void drctg0b_f(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	452	void drctg0c_0(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Store */
	453	void drctg0c_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / Load */
	454	void drctg0d_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_EQ:
	455	void drctg0d_1(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_NE:
	456	void drctg0d_2(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_CS:
	457	void drctg0d_3(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_CC:
	458	void drctg0d_4(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_MI:
	459	void drctg0d_5(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_PL:
	460	void drctg0d_6(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_VS:
	461	void drctg0d_7(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_VC:
	462	void drctg0d_8(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_HI:
	463	void drctg0d_9(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_LS:
	464	void drctg0d_a(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_GE:
	465	void drctg0d_b(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_LT:
	466	void drctg0d_c(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_GT:
	467	void drctg0d_d(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_LE:
	468	void drctg0d_e(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // COND_AL:
	469	void drctg0d_f(drcuml_block block, compiler_state compiler, const opcode_desc *desc); // SWI (this is sort of a "hole" in the opcode encoding)
	470	void drctg0e_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	471	void drctg0e_1(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	472	void drctg0f_0(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	473	void drctg0f_1(drcuml_block block, compiler_state compiler, const opcode_desc desc); / BL */
	474
	475	void load_fast_iregs(drcuml_block *block);
	476	void save_fast_iregs(drcuml_block *block);
	477	void arm7_drc_init();
	478	void arm7_drc_exit();
	479	void execute_run_drc();
	480	void arm7drc_set_options(UINT32 options);
	481	void arm7drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
	482	void arm7drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
	483	void code_flush_cache();
	484	void code_compile_block(UINT8 mode, offs_t pc);
	485	void cfunc_get_cycles();
	486	void cfunc_unimplemented();
	487	void static_generate_entry_point();
	488	void static_generate_check_irq();
	489	void static_generate_nocode_handler();
	490	void static_generate_out_of_cycles();
	491	void static_generate_detect_fault(uml::code_handle **handleptr);
	492	void static_generate_tlb_translate(uml::code_handle **handleptr);
	493	void static_generate_memory_accessor(int size, bool istlb, bool iswrite, const char name, uml::code_handle *handleptr);
	494	void generate_update_cycles(drcuml_block block, compiler_state compiler, uml::parameter param);
	495	void generate_checksum_block(drcuml_block block, compiler_state compiler, const opcode_desc seqhead, const opcode_desc seqlast);
	496	void generate_sequence_instruction(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	497	void generate_delay_slot_and_branch(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT8 linkreg);
	498
	499	typedef bool ( arm7_cpu_device::drcarm7ops_ophandler)(drcuml_block, compiler_state, const opcode_desc, UINT32);
	500	static const drcarm7ops_ophandler drcops_handler[0x10];
	501
	502	void saturate_qbit_overflow(drcuml_block *block);
	503	bool drcarm7ops_0123(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op);
	504	bool drcarm7ops_4567(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op);
	505	bool drcarm7ops_89(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op);
	506	bool drcarm7ops_ab(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op);
	507	bool drcarm7ops_cd(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op);
	508	bool drcarm7ops_e(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op);
	509	bool drcarm7ops_f(drcuml_block block, compiler_state compiler, const opcode_desc *desc, UINT32 op);
	510	int generate_opcode(drcuml_block block, compiler_state compiler, const opcode_desc *desc);
	511
	512	};
	513
	514
	515	class arm7_be_cpu_device : public arm7_cpu_device
	516	{
	517	public:
	518	// construction/destruction
	519	arm7_be_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	520
	521	};
	522
	523
	524	class arm7500_cpu_device : public arm7_cpu_device
	525	{
	526	public:
	527	// construction/destruction
	528	arm7500_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	529
	530	};
	531
	532
	533	class arm9_cpu_device : public arm7_cpu_device
	534	{
	535	public:
	536	// construction/destruction
	537	arm9_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	538
	539	};
	540
	541
	542	class arm920t_cpu_device : public arm7_cpu_device
	543	{
	544	public:
	545	// construction/destruction
	546	arm920t_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	547
	548	};
	549
	550
	551	class pxa255_cpu_device : public arm7_cpu_device
	552	{
	553	public:
	554	// construction/destruction
	555	pxa255_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	556
	557	};
	558
	559
	560	class sa1110_cpu_device : public arm7_cpu_device
	561	{
	562	public:
	563	// construction/destruction
	564	sa1110_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	565
	566	};
	567
	568
	569	extern const device_type ARM7;
	570	extern const device_type ARM7_BE;
	571	extern const device_type ARM7500;
	572	extern const device_type ARM9;
	573	extern const device_type ARM920T;
	574	extern const device_type PXA255;
	575	extern const device_type SA1110;
	576
79	577	#endif /* __ARM7_H__ */

trunk/src/emu/cpu/cpu.mak
r24074	r24075
95	95	$(CPUSRC)/arm7/arm7help.h \
96	96	$(CPUSRC)/arm7/arm7thmb.c \
97	97	$(CPUSRC)/arm7/arm7ops.c \
98		$(CPUSRC)/arm7/arm7core.c
	98	$(CPUSRC)/arm7/arm7core.c \
	99	$(CPUSRC)/arm7/arm7drc.c \
	100	$(CPUSRC)/arm7/arm7tdrc.c
99	101
100	102	$(CPUOBJ)/arm7/arm7ops.o: $(CPUSRC)/arm7/arm7ops.c \
101	103	$(CPUSRC)/arm7/arm7.h \

199869 Revisions