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r24003 Saturday 29th June, 2013 at 18:15:27 UTC by hap
removed useless branches
[src/emu/cpu/arm]arm.c

trunk/src/emu/cpu/arm/arm.c
r24002r24003
2222CPU_DISASSEMBLE( arm );
2323CPU_DISASSEMBLE( arm_be );
2424
25#define READ8(addr)         cpu_read8(addr)
26#define WRITE8(addr,data)   cpu_write8(addr,data)
27#define READ32(addr)        cpu_read32(addr)
28#define WRITE32(addr,data)  cpu_write32(addr,data)
29
3025#define ARM_DEBUG_CORE 0
3126#define ARM_DEBUG_COPRO 0
3227
r24002r24003
256251void arm_cpu_device::cpu_write32( int addr, UINT32 data )
257252{
258253   /* Unaligned writes are treated as normal writes */
259   if ( m_endian == ENDIANNESS_BIG )
260      m_program->write_dword(addr&ADDRESS_MASK,data);
261   else
262      m_program->write_dword(addr&ADDRESS_MASK,data);
254   m_program->write_dword(addr&ADDRESS_MASK,data);
263255   if (ARM_DEBUG_CORE && addr&3) logerror("%08x: Unaligned write %08x\n",R15,addr);
264256}
265257
266258void arm_cpu_device::cpu_write8( int addr, UINT8 data )
267259{
268   if ( m_endian == ENDIANNESS_BIG )
269      m_program->write_byte(addr,data);
270   else
271      m_program->write_byte(addr,data);
260   m_program->write_byte(addr,data);
272261}
273262
274263UINT32 arm_cpu_device::cpu_read32( int addr )
275264{
276   UINT32 result;
265   UINT32 result = m_program->read_dword(addr&ADDRESS_MASK);
277266
278   if ( m_endian == ENDIANNESS_BIG )
279      result = m_program->read_dword(addr&ADDRESS_MASK);
280   else
281      result = m_program->read_dword(addr&ADDRESS_MASK);
282
283267   /* Unaligned reads rotate the word, they never combine words */
284   if (addr&3) {
268   if (addr&3)
269   {
285270      if (ARM_DEBUG_CORE && addr&1)
286271         logerror("%08x: Unaligned byte read %08x\n",R15,addr);
287272
r24002r24003
298283
299284UINT8 arm_cpu_device::cpu_read8( int addr )
300285{
301   if ( m_endian == ENDIANNESS_BIG )
302      return m_program->read_byte(addr);
303   else
304      return m_program->read_byte(addr);
286   return m_program->read_byte(addr);
305287}
306288
307289UINT32 arm_cpu_device::GetRegister( int rIndex )
r24002r24003
470452       Undefined instruction
471453   */
472454
473   if (m_pendingFiq && (pc&F_MASK)==0) {
455   if (m_pendingFiq && (pc&F_MASK)==0)
456   {
474457      R15 = eARM_MODE_FIQ;    /* Set FIQ mode so PC is saved to correct R14 bank */
475458      SetRegister( 14, pc );    /* save PC */
476459      R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set PC=0x1c */
r24002r24003
478461      return;
479462   }
480463
481   if (m_pendingIrq && (pc&I_MASK)==0) {
464   if (m_pendingIrq && (pc&I_MASK)==0)
465   {
482466      R15 = eARM_MODE_IRQ;    /* Set IRQ mode so PC is saved to correct R14 bank */
483467      SetRegister( 14, pc );    /* save PC */
484468      R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=0x18 */
r24002r24003
490474
491475void arm_cpu_device::execute_set_input(int irqline, int state)
492476{
493   switch (irqline) {
477   switch (irqline)
478   {
494479   case ARM_IRQ_LINE: /* IRQ */
495480      if (state && (R15&0x3)!=eARM_MODE_IRQ) /* Don't allow nested IRQs */
496481         m_pendingIrq=1;
r24002r24003
672657      {
673658         if (ARM_DEBUG_CORE && rd == eR15)
674659            logerror("read byte R15 %08x\n", R15);
675         SetRegister(rd,(UINT32) READ8(rnv) );
660         SetRegister(rd,(UINT32) cpu_read8(rnv) );
676661      }
677662      else
678663      {
679664         if (rd == eR15)
680665         {
681            R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK);
666            R15 = (cpu_read32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK);
682667
683668            /*
684669            The docs are explicit in that the bottom bits should be masked off
r24002r24003
688673
689674            In other cases, 4 is subracted from R15 here to account for pipelining.
690675            */
691            if ((READ32(rnv)&3)==0)
676            if ((cpu_read32(rnv)&3)==0)
692677               R15 -= 4;
693678
694679            m_icount -= S_CYCLE + N_CYCLE;
695680         }
696681         else
697682         {
698            SetRegister(rd, READ32(rnv));
683            SetRegister(rd, cpu_read32(rnv));
699684         }
700685      }
701686   }
r24002r24003
708693         if (ARM_DEBUG_CORE && rd==eR15)
709694            logerror("Wrote R15 in byte mode\n");
710695
711         WRITE8(rnv, (UINT8) GetRegister(rd) & 0xffu);
696         cpu_write8(rnv, (UINT8) GetRegister(rd) & 0xffu);
712697      }
713698      else
714699      {
715700         if (ARM_DEBUG_CORE && rd==eR15)
716701            logerror("Wrote R15 in 32bit mode\n");
717702
718         WRITE32(rnv, rd == eR15 ? R15 + 8 : GetRegister(rd));
703         cpu_write32(rnv, rd == eR15 ? R15 + 8 : GetRegister(rd));
719704      }
720705   }
721706
r24002r24003
726711      {
727712         /* Writeback is applied in pipeline, before value is read from mem,
728713             so writeback is effectively ignored */
729         if (rd==rn) {
714         if (rd==rn)
715         {
730716            SetRegister(rn,GetRegister(rd));
731717         }
732         else {
718         else
719         {
733720            if ((insn&INSN_SDT_W)!=0)
734721            logerror("%08x:  RegisterWritebackIncrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0);
735722
r24002r24003
740727      {
741728         /* Writeback is applied in pipeline, before value is read from mem,
742729             so writeback is effectively ignored */
743         if (rd==rn) {
730         if (rd==rn)
731         {
744732            SetRegister(rn,GetRegister(rd));
745733         }
746         else {
734         else
735         {
747736            SetRegister(rn,(rnv - off));
748737
749738            if ((insn&INSN_SDT_W)!=0)
r24002r24003
10191008   {
10201009      if( (pat>>i)&1 )
10211010      {
1022         if (i==15) {
1011         if (i==15)
1012         {
10231013            if (s) /* Pull full contents from stack */
1024               SetRegister( 15, READ32(rbv+=4) );
1014               SetRegister( 15, cpu_read32(rbv+=4) );
10251015            else /* Pull only address, preserve mode & status flags */
1026               SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv+=4))&ADDRESS_MASK) );
1027         } else
1028            SetRegister( i, READ32(rbv+=4) );
1016               SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv+=4))&ADDRESS_MASK) );
1017         }
1018         else
1019            SetRegister( i, cpu_read32(rbv+=4) );
10291020
10301021         result++;
10311022      }
r24002r24003
10431034   {
10441035      if( (pat>>i)&1 )
10451036      {
1046         if (i==15) {
1037         if (i==15)
1038         {
10471039            *defer=1;
10481040            if (s) /* Pull full contents from stack */
1049               *deferredR15=READ32(rbv-=4);
1041               *deferredR15=cpu_read32(rbv-=4);
10501042            else /* Pull only address, preserve mode & status flags */
1051               *deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv-=4))&ADDRESS_MASK);
1043               *deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv-=4))&ADDRESS_MASK);
10521044         }
10531045         else
1054            SetRegister( i, READ32(rbv -=4) );
1046            SetRegister( i, cpu_read32(rbv -=4) );
10551047         result++;
10561048      }
10571049   }
r24002r24003
10711063         if (ARM_DEBUG_CORE && i==15) /* R15 is plus 12 from address of STM */
10721064            logerror("%08x: StoreInc on R15\n",R15);
10731065
1074         WRITE32( rbv += 4, GetRegister(i) );
1066         cpu_write32( rbv += 4, GetRegister(i) );
10751067         result++;
10761068      }
10771069   }
r24002r24003
10911083         if (ARM_DEBUG_CORE && i==15) /* R15 is plus 12 from address of STM */
10921084            logerror("%08x: StoreDec on R15\n",R15);
10931085
1094         WRITE32( rbv -= 4, GetRegister(i) );
1086         cpu_write32( rbv -= 4, GetRegister(i) );
10951087         result++;
10961088      }
10971089   }
r24002r24003
11201112
11211113         result = loadInc( insn & 0xffff, rbp, insn&INSN_BDT_S );
11221114
1123         if (insn & 0x8000) {
1115         if (insn & 0x8000)
1116         {
11241117            R15-=4;
11251118            m_icount -= S_CYCLE + N_CYCLE;
11261119         }
r24002r24003
11731166         if (defer)
11741167            SetRegister(15, deferredR15);
11751168
1176         if (insn & 0x8000) {
1169         if (insn & 0x8000)
1170         {
11771171            m_icount -= S_CYCLE + N_CYCLE;
11781172            R15-=4;
11791173         }
r24002r24003
12421236   UINT32 rm   = GetRegister( insn & INSN_OP2_RM );
12431237   UINT32 t    = (insn & INSN_OP2_SHIFT_TYPE) >> INSN_OP2_SHIFT_TYPE_SHIFT;
12441238
1245   if ((insn & INSN_OP2_RM)==0xf) {
1239   if ((insn & INSN_OP2_RM)==0xf)
1240   {
12461241      /* If hardwired shift, then PC is 8 bytes ahead, else if register shift
12471242      is used, then 12 bytes - TODO?? */
12481243      rm+=8;

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