trunk/src/mess/machine/apollo.c
r23981 | r23982 | |
375 | 375 | } |
376 | 376 | |
377 | 377 | READ8_MEMBER(apollo_state::apollo_dma_2_r){ |
| 378 | // Nasty hack (13-06-15 - ost): |
| 379 | // MD self_test will test wrong DMA register and |
| 380 | // mem-to-mem DMA in am9517a.c is often starting much too late (for MD self_test) |
| 381 | // (8237dma.c was always fast enough to omit these problems) |
| 382 | if (offset == 8) |
| 383 | { |
| 384 | switch (space.device().safe_pcbase()) |
| 385 | { |
| 386 | case 0x00102e22: // DN3000 |
| 387 | case 0x01002f3c: // DN3500 |
| 388 | case 0x010029a6: // DN5500 |
| 389 | offset = 16; |
| 390 | break; |
| 391 | } |
| 392 | } |
378 | 393 | UINT8 data = get_device_dma8237_2(&space.device())->read(space, offset / 2); |
379 | 394 | SLOG1(("apollo_dma_2_r: reading DMA Controller 2 at offset %02x = %02x", offset/2, data)); |
380 | 395 | return data; |
r23981 | r23982 | |
495 | 510 | |
496 | 511 | READ8_MEMBER(apollo_state::apollo_dma8237_ctape_dack_r ) { |
497 | 512 | UINT8 data = sc499_dack_r(&space.machine()); |
498 | | // DLOG2(("dma ctape dack read %02x",data)); |
| 513 | CLOG2(("dma ctape dack read %02x",data)); |
499 | 514 | |
500 | 515 | // hack for DN3000: select appropriate DMA channel No. |
501 | 516 | dn3000_dma_channel1 = 1; // 1 = ctape, 2 = floppy dma channel |
r23981 | r23982 | |
504 | 519 | } |
505 | 520 | |
506 | 521 | WRITE8_MEMBER(apollo_state::apollo_dma8237_ctape_dack_w ) { |
507 | | // DLOG2(("dma ctape dack write %02x", data)); |
| 522 | CLOG2(("dma ctape dack write %02x", data)); |
508 | 523 | sc499_dack_w(&space.machine(), data); |
509 | 524 | |
510 | 525 | // hack for DN3000: select appropriate DMA channel No. |
r23981 | r23982 | |
515 | 530 | READ8_MEMBER(apollo_state::apollo_dma8237_fdc_dack_r ) { |
516 | 531 | pc_fdc_at_device *fdc = space.machine().device<pc_fdc_at_device>(APOLLO_FDC_TAG); |
517 | 532 | UINT8 data = fdc->dma_r(); |
518 | | // DLOG2(("dma fdc dack read %02x",data)); |
| 533 | CLOG2(("dma fdc dack read %02x",data)); |
519 | 534 | |
520 | 535 | // hack for DN3000: select appropriate DMA channel No. |
521 | 536 | dn3000_dma_channel1 = 2; // 1 = ctape, 2 = floppy dma channel |
r23981 | r23982 | |
525 | 540 | |
526 | 541 | WRITE8_MEMBER(apollo_state::apollo_dma8237_fdc_dack_w ) { |
527 | 542 | pc_fdc_at_device *fdc = space.machine().device<pc_fdc_at_device>(APOLLO_FDC_TAG); |
528 | | // DLOG2(("dma fdc dack write %02x", data)); |
| 543 | CLOG2(("dma fdc dack write %02x", data)); |
529 | 544 | fdc->dma_w(data); |
530 | 545 | |
531 | 546 | // hack for DN3000: select appropriate DMA channel No. |
r23981 | r23982 | |
535 | 550 | |
536 | 551 | READ8_MEMBER(apollo_state::apollo_dma8237_wdc_dack_r ) { |
537 | 552 | UINT8 data = 0xff; // omti8621_dack_r(device->machine); |
538 | | //DLOG1(("dma wdc dack read %02x (not used, not emulated!)",data)); |
| 553 | CLOG1(("dma wdc dack read %02x (not used, not emulated!)",data)); |
539 | 554 | return data; |
540 | 555 | } |
541 | 556 | |
542 | 557 | WRITE8_MEMBER(apollo_state::apollo_dma8237_wdc_dack_w ) { |
543 | | //DLOG1(("dma wdc dack write %02x (not used, not emulated!)", data)); |
| 558 | CLOG1(("dma wdc dack write %02x (not used, not emulated!)", data)); |
544 | 559 | // omti8621_dack_w(machine, data); |
545 | 560 | } |
546 | 561 | |
547 | 562 | WRITE_LINE_MEMBER(apollo_state::apollo_dma8237_out_eop ) { |
548 | 563 | pc_fdc_at_device *fdc = machine().device<pc_fdc_at_device>(APOLLO_FDC_TAG); |
549 | | //DLOG1(("dma out eop state %02x", state)); |
| 564 | CLOG1(("dma out eop state %02x", state)); |
550 | 565 | fdc->tc_w(!state); |
551 | 566 | sc499_set_tc_state(&machine(), state); |
552 | 567 | } |
553 | 568 | |
554 | 569 | WRITE_LINE_MEMBER(apollo_state::apollo_dma_1_hrq_changed ) { |
555 | | // DLOG2(("dma 1 hrq changed state %02x", state)); |
556 | | m_dma8237_2->dreq0_w(state); |
| 570 | CLOG2(("dma 1 hrq changed state %02x", state)); |
| 571 | m_dma8237_1->dreq0_w(state); |
557 | 572 | |
558 | 573 | /* Assert HLDA */ |
559 | | //m_dma8237_1->hack_w(state); |
| 574 | m_dma8237_1->hack_w(state); |
560 | 575 | |
561 | 576 | // cascade mode? |
562 | 577 | // i8237_hlda_w(get_device_dma8237_2(device), state); |
563 | 578 | } |
564 | 579 | |
565 | 580 | WRITE_LINE_MEMBER(apollo_state::apollo_dma_2_hrq_changed ) { |
566 | | // DLOG2(("dma 2 hrq changed state %02x", state)); |
| 581 | CLOG2(("dma 2 hrq changed state %02x", state)); |
567 | 582 | m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE); |
568 | 583 | |
569 | 584 | /* Assert HLDA */ |